1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 #include <net/dst_metadata.h> 27 28 #include "mtk_eth_soc.h" 29 #include "mtk_wed.h" 30 31 static int mtk_msg_level = -1; 32 module_param_named(msg_level, mtk_msg_level, int, 0); 33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 34 35 #define MTK_ETHTOOL_STAT(x) { #x, \ 36 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 37 38 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 40 sizeof(u64) } 41 42 static const struct mtk_reg_map mtk_reg_map = { 43 .tx_irq_mask = 0x1a1c, 44 .tx_irq_status = 0x1a18, 45 .pdma = { 46 .rx_ptr = 0x0900, 47 .rx_cnt_cfg = 0x0904, 48 .pcrx_ptr = 0x0908, 49 .glo_cfg = 0x0a04, 50 .rst_idx = 0x0a08, 51 .delay_irq = 0x0a0c, 52 .irq_status = 0x0a20, 53 .irq_mask = 0x0a28, 54 .adma_rx_dbg0 = 0x0a38, 55 .int_grp = 0x0a50, 56 }, 57 .qdma = { 58 .qtx_cfg = 0x1800, 59 .qtx_sch = 0x1804, 60 .rx_ptr = 0x1900, 61 .rx_cnt_cfg = 0x1904, 62 .qcrx_ptr = 0x1908, 63 .glo_cfg = 0x1a04, 64 .rst_idx = 0x1a08, 65 .delay_irq = 0x1a0c, 66 .fc_th = 0x1a10, 67 .tx_sch_rate = 0x1a14, 68 .int_grp = 0x1a20, 69 .hred = 0x1a44, 70 .ctx_ptr = 0x1b00, 71 .dtx_ptr = 0x1b04, 72 .crx_ptr = 0x1b10, 73 .drx_ptr = 0x1b14, 74 .fq_head = 0x1b20, 75 .fq_tail = 0x1b24, 76 .fq_count = 0x1b28, 77 .fq_blen = 0x1b2c, 78 }, 79 .gdm1_cnt = 0x2400, 80 .gdma_to_ppe = 0x4444, 81 .ppe_base = 0x0c00, 82 .wdma_base = { 83 [0] = 0x2800, 84 [1] = 0x2c00, 85 }, 86 .pse_iq_sta = 0x0110, 87 .pse_oq_sta = 0x0118, 88 }; 89 90 static const struct mtk_reg_map mt7628_reg_map = { 91 .tx_irq_mask = 0x0a28, 92 .tx_irq_status = 0x0a20, 93 .pdma = { 94 .rx_ptr = 0x0900, 95 .rx_cnt_cfg = 0x0904, 96 .pcrx_ptr = 0x0908, 97 .glo_cfg = 0x0a04, 98 .rst_idx = 0x0a08, 99 .delay_irq = 0x0a0c, 100 .irq_status = 0x0a20, 101 .irq_mask = 0x0a28, 102 .int_grp = 0x0a50, 103 }, 104 }; 105 106 static const struct mtk_reg_map mt7986_reg_map = { 107 .tx_irq_mask = 0x461c, 108 .tx_irq_status = 0x4618, 109 .pdma = { 110 .rx_ptr = 0x6100, 111 .rx_cnt_cfg = 0x6104, 112 .pcrx_ptr = 0x6108, 113 .glo_cfg = 0x6204, 114 .rst_idx = 0x6208, 115 .delay_irq = 0x620c, 116 .irq_status = 0x6220, 117 .irq_mask = 0x6228, 118 .adma_rx_dbg0 = 0x6238, 119 .int_grp = 0x6250, 120 }, 121 .qdma = { 122 .qtx_cfg = 0x4400, 123 .qtx_sch = 0x4404, 124 .rx_ptr = 0x4500, 125 .rx_cnt_cfg = 0x4504, 126 .qcrx_ptr = 0x4508, 127 .glo_cfg = 0x4604, 128 .rst_idx = 0x4608, 129 .delay_irq = 0x460c, 130 .fc_th = 0x4610, 131 .int_grp = 0x4620, 132 .hred = 0x4644, 133 .ctx_ptr = 0x4700, 134 .dtx_ptr = 0x4704, 135 .crx_ptr = 0x4710, 136 .drx_ptr = 0x4714, 137 .fq_head = 0x4720, 138 .fq_tail = 0x4724, 139 .fq_count = 0x4728, 140 .fq_blen = 0x472c, 141 .tx_sch_rate = 0x4798, 142 }, 143 .gdm1_cnt = 0x1c00, 144 .gdma_to_ppe = 0x3333, 145 .ppe_base = 0x2000, 146 .wdma_base = { 147 [0] = 0x4800, 148 [1] = 0x4c00, 149 }, 150 .pse_iq_sta = 0x0180, 151 .pse_oq_sta = 0x01a0, 152 }; 153 154 /* strings used by ethtool */ 155 static const struct mtk_ethtool_stats { 156 char str[ETH_GSTRING_LEN]; 157 u32 offset; 158 } mtk_ethtool_stats[] = { 159 MTK_ETHTOOL_STAT(tx_bytes), 160 MTK_ETHTOOL_STAT(tx_packets), 161 MTK_ETHTOOL_STAT(tx_skip), 162 MTK_ETHTOOL_STAT(tx_collisions), 163 MTK_ETHTOOL_STAT(rx_bytes), 164 MTK_ETHTOOL_STAT(rx_packets), 165 MTK_ETHTOOL_STAT(rx_overflow), 166 MTK_ETHTOOL_STAT(rx_fcs_errors), 167 MTK_ETHTOOL_STAT(rx_short_errors), 168 MTK_ETHTOOL_STAT(rx_long_errors), 169 MTK_ETHTOOL_STAT(rx_checksum_errors), 170 MTK_ETHTOOL_STAT(rx_flow_control_packets), 171 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 172 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 173 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 174 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 175 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 176 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 177 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 178 }; 179 180 static const char * const mtk_clks_source_name[] = { 181 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 182 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 183 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 184 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 185 }; 186 187 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 188 { 189 __raw_writel(val, eth->base + reg); 190 } 191 192 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 193 { 194 return __raw_readl(eth->base + reg); 195 } 196 197 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 198 { 199 u32 val; 200 201 val = mtk_r32(eth, reg); 202 val &= ~mask; 203 val |= set; 204 mtk_w32(eth, val, reg); 205 return reg; 206 } 207 208 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 209 { 210 unsigned long t_start = jiffies; 211 212 while (1) { 213 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 214 return 0; 215 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 216 break; 217 cond_resched(); 218 } 219 220 dev_err(eth->dev, "mdio: MDIO timeout\n"); 221 return -ETIMEDOUT; 222 } 223 224 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 225 u32 write_data) 226 { 227 int ret; 228 229 ret = mtk_mdio_busy_wait(eth); 230 if (ret < 0) 231 return ret; 232 233 mtk_w32(eth, PHY_IAC_ACCESS | 234 PHY_IAC_START_C22 | 235 PHY_IAC_CMD_WRITE | 236 PHY_IAC_REG(phy_reg) | 237 PHY_IAC_ADDR(phy_addr) | 238 PHY_IAC_DATA(write_data), 239 MTK_PHY_IAC); 240 241 ret = mtk_mdio_busy_wait(eth); 242 if (ret < 0) 243 return ret; 244 245 return 0; 246 } 247 248 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 249 u32 devad, u32 phy_reg, u32 write_data) 250 { 251 int ret; 252 253 ret = mtk_mdio_busy_wait(eth); 254 if (ret < 0) 255 return ret; 256 257 mtk_w32(eth, PHY_IAC_ACCESS | 258 PHY_IAC_START_C45 | 259 PHY_IAC_CMD_C45_ADDR | 260 PHY_IAC_REG(devad) | 261 PHY_IAC_ADDR(phy_addr) | 262 PHY_IAC_DATA(phy_reg), 263 MTK_PHY_IAC); 264 265 ret = mtk_mdio_busy_wait(eth); 266 if (ret < 0) 267 return ret; 268 269 mtk_w32(eth, PHY_IAC_ACCESS | 270 PHY_IAC_START_C45 | 271 PHY_IAC_CMD_WRITE | 272 PHY_IAC_REG(devad) | 273 PHY_IAC_ADDR(phy_addr) | 274 PHY_IAC_DATA(write_data), 275 MTK_PHY_IAC); 276 277 ret = mtk_mdio_busy_wait(eth); 278 if (ret < 0) 279 return ret; 280 281 return 0; 282 } 283 284 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 285 { 286 int ret; 287 288 ret = mtk_mdio_busy_wait(eth); 289 if (ret < 0) 290 return ret; 291 292 mtk_w32(eth, PHY_IAC_ACCESS | 293 PHY_IAC_START_C22 | 294 PHY_IAC_CMD_C22_READ | 295 PHY_IAC_REG(phy_reg) | 296 PHY_IAC_ADDR(phy_addr), 297 MTK_PHY_IAC); 298 299 ret = mtk_mdio_busy_wait(eth); 300 if (ret < 0) 301 return ret; 302 303 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 304 } 305 306 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 307 u32 devad, u32 phy_reg) 308 { 309 int ret; 310 311 ret = mtk_mdio_busy_wait(eth); 312 if (ret < 0) 313 return ret; 314 315 mtk_w32(eth, PHY_IAC_ACCESS | 316 PHY_IAC_START_C45 | 317 PHY_IAC_CMD_C45_ADDR | 318 PHY_IAC_REG(devad) | 319 PHY_IAC_ADDR(phy_addr) | 320 PHY_IAC_DATA(phy_reg), 321 MTK_PHY_IAC); 322 323 ret = mtk_mdio_busy_wait(eth); 324 if (ret < 0) 325 return ret; 326 327 mtk_w32(eth, PHY_IAC_ACCESS | 328 PHY_IAC_START_C45 | 329 PHY_IAC_CMD_C45_READ | 330 PHY_IAC_REG(devad) | 331 PHY_IAC_ADDR(phy_addr), 332 MTK_PHY_IAC); 333 334 ret = mtk_mdio_busy_wait(eth); 335 if (ret < 0) 336 return ret; 337 338 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 339 } 340 341 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 342 int phy_reg, u16 val) 343 { 344 struct mtk_eth *eth = bus->priv; 345 346 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 347 } 348 349 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 350 int devad, int phy_reg, u16 val) 351 { 352 struct mtk_eth *eth = bus->priv; 353 354 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 355 } 356 357 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 358 { 359 struct mtk_eth *eth = bus->priv; 360 361 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 362 } 363 364 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 365 int phy_reg) 366 { 367 struct mtk_eth *eth = bus->priv; 368 369 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 370 } 371 372 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 373 phy_interface_t interface) 374 { 375 u32 val; 376 377 /* Check DDR memory type. 378 * Currently TRGMII mode with DDR2 memory is not supported. 379 */ 380 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 381 if (interface == PHY_INTERFACE_MODE_TRGMII && 382 val & SYSCFG_DRAM_TYPE_DDR2) { 383 dev_err(eth->dev, 384 "TRGMII mode with DDR2 memory is not supported!\n"); 385 return -EOPNOTSUPP; 386 } 387 388 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 389 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 390 391 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 392 ETHSYS_TRGMII_MT7621_MASK, val); 393 394 return 0; 395 } 396 397 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 398 phy_interface_t interface, int speed) 399 { 400 u32 val; 401 int ret; 402 403 if (interface == PHY_INTERFACE_MODE_TRGMII) { 404 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 405 val = 500000000; 406 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 407 if (ret) 408 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 409 return; 410 } 411 412 val = (speed == SPEED_1000) ? 413 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 414 mtk_w32(eth, val, INTF_MODE); 415 416 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 417 ETHSYS_TRGMII_CLK_SEL362_5, 418 ETHSYS_TRGMII_CLK_SEL362_5); 419 420 val = (speed == SPEED_1000) ? 250000000 : 500000000; 421 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 422 if (ret) 423 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 424 425 val = (speed == SPEED_1000) ? 426 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 427 mtk_w32(eth, val, TRGMII_RCK_CTRL); 428 429 val = (speed == SPEED_1000) ? 430 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 431 mtk_w32(eth, val, TRGMII_TCK_CTRL); 432 } 433 434 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 435 phy_interface_t interface) 436 { 437 struct mtk_mac *mac = container_of(config, struct mtk_mac, 438 phylink_config); 439 struct mtk_eth *eth = mac->hw; 440 unsigned int sid; 441 442 if (interface == PHY_INTERFACE_MODE_SGMII || 443 phy_interface_mode_is_8023z(interface)) { 444 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 445 0 : mac->id; 446 447 return mtk_sgmii_select_pcs(eth->sgmii, sid); 448 } 449 450 return NULL; 451 } 452 453 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 454 const struct phylink_link_state *state) 455 { 456 struct mtk_mac *mac = container_of(config, struct mtk_mac, 457 phylink_config); 458 struct mtk_eth *eth = mac->hw; 459 int val, ge_mode, err = 0; 460 u32 i; 461 462 /* MT76x8 has no hardware settings between for the MAC */ 463 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 464 mac->interface != state->interface) { 465 /* Setup soc pin functions */ 466 switch (state->interface) { 467 case PHY_INTERFACE_MODE_TRGMII: 468 if (mac->id) 469 goto err_phy; 470 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 471 MTK_GMAC1_TRGMII)) 472 goto err_phy; 473 fallthrough; 474 case PHY_INTERFACE_MODE_RGMII_TXID: 475 case PHY_INTERFACE_MODE_RGMII_RXID: 476 case PHY_INTERFACE_MODE_RGMII_ID: 477 case PHY_INTERFACE_MODE_RGMII: 478 case PHY_INTERFACE_MODE_MII: 479 case PHY_INTERFACE_MODE_REVMII: 480 case PHY_INTERFACE_MODE_RMII: 481 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 482 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 483 if (err) 484 goto init_err; 485 } 486 break; 487 case PHY_INTERFACE_MODE_1000BASEX: 488 case PHY_INTERFACE_MODE_2500BASEX: 489 case PHY_INTERFACE_MODE_SGMII: 490 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 491 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 492 if (err) 493 goto init_err; 494 } 495 break; 496 case PHY_INTERFACE_MODE_GMII: 497 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 498 err = mtk_gmac_gephy_path_setup(eth, mac->id); 499 if (err) 500 goto init_err; 501 } 502 break; 503 default: 504 goto err_phy; 505 } 506 507 /* Setup clock for 1st gmac */ 508 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 509 !phy_interface_mode_is_8023z(state->interface) && 510 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 511 if (MTK_HAS_CAPS(mac->hw->soc->caps, 512 MTK_TRGMII_MT7621_CLK)) { 513 if (mt7621_gmac0_rgmii_adjust(mac->hw, 514 state->interface)) 515 goto err_phy; 516 } else { 517 /* FIXME: this is incorrect. Not only does it 518 * use state->speed (which is not guaranteed 519 * to be correct) but it also makes use of it 520 * in a code path that will only be reachable 521 * when the PHY interface mode changes, not 522 * when the speed changes. Consequently, RGMII 523 * is probably broken. 524 */ 525 mtk_gmac0_rgmii_adjust(mac->hw, 526 state->interface, 527 state->speed); 528 529 /* mt7623_pad_clk_setup */ 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mtk_w32(mac->hw, 532 TD_DM_DRVP(8) | TD_DM_DRVN(8), 533 TRGMII_TD_ODT(i)); 534 535 /* Assert/release MT7623 RXC reset */ 536 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 537 TRGMII_RCK_CTRL); 538 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 539 } 540 } 541 542 ge_mode = 0; 543 switch (state->interface) { 544 case PHY_INTERFACE_MODE_MII: 545 case PHY_INTERFACE_MODE_GMII: 546 ge_mode = 1; 547 break; 548 case PHY_INTERFACE_MODE_REVMII: 549 ge_mode = 2; 550 break; 551 case PHY_INTERFACE_MODE_RMII: 552 if (mac->id) 553 goto err_phy; 554 ge_mode = 3; 555 break; 556 default: 557 break; 558 } 559 560 /* put the gmac into the right mode */ 561 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 562 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 563 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 564 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 565 566 mac->interface = state->interface; 567 } 568 569 /* SGMII */ 570 if (state->interface == PHY_INTERFACE_MODE_SGMII || 571 phy_interface_mode_is_8023z(state->interface)) { 572 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 573 * being setup done. 574 */ 575 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 576 577 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 578 SYSCFG0_SGMII_MASK, 579 ~(u32)SYSCFG0_SGMII_MASK); 580 581 /* Save the syscfg0 value for mac_finish */ 582 mac->syscfg0 = val; 583 } else if (phylink_autoneg_inband(mode)) { 584 dev_err(eth->dev, 585 "In-band mode not supported in non SGMII mode!\n"); 586 return; 587 } 588 589 return; 590 591 err_phy: 592 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 593 mac->id, phy_modes(state->interface)); 594 return; 595 596 init_err: 597 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 598 mac->id, phy_modes(state->interface), err); 599 } 600 601 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 602 phy_interface_t interface) 603 { 604 struct mtk_mac *mac = container_of(config, struct mtk_mac, 605 phylink_config); 606 struct mtk_eth *eth = mac->hw; 607 u32 mcr_cur, mcr_new; 608 609 /* Enable SGMII */ 610 if (interface == PHY_INTERFACE_MODE_SGMII || 611 phy_interface_mode_is_8023z(interface)) 612 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 613 SYSCFG0_SGMII_MASK, mac->syscfg0); 614 615 /* Setup gmac */ 616 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 617 mcr_new = mcr_cur; 618 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 619 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 620 MAC_MCR_RX_FIFO_CLR_DIS; 621 622 /* Only update control register when needed! */ 623 if (mcr_new != mcr_cur) 624 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 625 626 return 0; 627 } 628 629 static void mtk_mac_pcs_get_state(struct phylink_config *config, 630 struct phylink_link_state *state) 631 { 632 struct mtk_mac *mac = container_of(config, struct mtk_mac, 633 phylink_config); 634 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 635 636 state->link = (pmsr & MAC_MSR_LINK); 637 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 638 639 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 640 case 0: 641 state->speed = SPEED_10; 642 break; 643 case MAC_MSR_SPEED_100: 644 state->speed = SPEED_100; 645 break; 646 case MAC_MSR_SPEED_1000: 647 state->speed = SPEED_1000; 648 break; 649 default: 650 state->speed = SPEED_UNKNOWN; 651 break; 652 } 653 654 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 655 if (pmsr & MAC_MSR_RX_FC) 656 state->pause |= MLO_PAUSE_RX; 657 if (pmsr & MAC_MSR_TX_FC) 658 state->pause |= MLO_PAUSE_TX; 659 } 660 661 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 662 phy_interface_t interface) 663 { 664 struct mtk_mac *mac = container_of(config, struct mtk_mac, 665 phylink_config); 666 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 667 668 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 669 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 670 } 671 672 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 673 int speed) 674 { 675 const struct mtk_soc_data *soc = eth->soc; 676 u32 ofs, val; 677 678 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 679 return; 680 681 val = MTK_QTX_SCH_MIN_RATE_EN | 682 /* minimum: 10 Mbps */ 683 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 684 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 685 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 686 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 687 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 688 689 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 690 switch (speed) { 691 case SPEED_10: 692 val |= MTK_QTX_SCH_MAX_RATE_EN | 693 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 694 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 695 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 696 break; 697 case SPEED_100: 698 val |= MTK_QTX_SCH_MAX_RATE_EN | 699 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 700 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 701 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 702 break; 703 case SPEED_1000: 704 val |= MTK_QTX_SCH_MAX_RATE_EN | 705 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 706 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 707 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 708 break; 709 default: 710 break; 711 } 712 } else { 713 switch (speed) { 714 case SPEED_10: 715 val |= MTK_QTX_SCH_MAX_RATE_EN | 716 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 717 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 718 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 719 break; 720 case SPEED_100: 721 val |= MTK_QTX_SCH_MAX_RATE_EN | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 723 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 724 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 725 break; 726 case SPEED_1000: 727 val |= MTK_QTX_SCH_MAX_RATE_EN | 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 729 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 731 break; 732 default: 733 break; 734 } 735 } 736 737 ofs = MTK_QTX_OFFSET * idx; 738 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 739 } 740 741 static void mtk_mac_link_up(struct phylink_config *config, 742 struct phy_device *phy, 743 unsigned int mode, phy_interface_t interface, 744 int speed, int duplex, bool tx_pause, bool rx_pause) 745 { 746 struct mtk_mac *mac = container_of(config, struct mtk_mac, 747 phylink_config); 748 u32 mcr; 749 750 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 751 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 752 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 753 MAC_MCR_FORCE_RX_FC); 754 755 /* Configure speed */ 756 switch (speed) { 757 case SPEED_2500: 758 case SPEED_1000: 759 mcr |= MAC_MCR_SPEED_1000; 760 break; 761 case SPEED_100: 762 mcr |= MAC_MCR_SPEED_100; 763 break; 764 } 765 766 /* Configure duplex */ 767 if (duplex == DUPLEX_FULL) 768 mcr |= MAC_MCR_FORCE_DPX; 769 770 /* Configure pause modes - phylink will avoid these for half duplex */ 771 if (tx_pause) 772 mcr |= MAC_MCR_FORCE_TX_FC; 773 if (rx_pause) 774 mcr |= MAC_MCR_FORCE_RX_FC; 775 776 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 777 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 778 } 779 780 static const struct phylink_mac_ops mtk_phylink_ops = { 781 .mac_select_pcs = mtk_mac_select_pcs, 782 .mac_pcs_get_state = mtk_mac_pcs_get_state, 783 .mac_config = mtk_mac_config, 784 .mac_finish = mtk_mac_finish, 785 .mac_link_down = mtk_mac_link_down, 786 .mac_link_up = mtk_mac_link_up, 787 }; 788 789 static int mtk_mdio_init(struct mtk_eth *eth) 790 { 791 struct device_node *mii_np; 792 int ret; 793 794 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 795 if (!mii_np) { 796 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 797 return -ENODEV; 798 } 799 800 if (!of_device_is_available(mii_np)) { 801 ret = -ENODEV; 802 goto err_put_node; 803 } 804 805 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 806 if (!eth->mii_bus) { 807 ret = -ENOMEM; 808 goto err_put_node; 809 } 810 811 eth->mii_bus->name = "mdio"; 812 eth->mii_bus->read = mtk_mdio_read_c22; 813 eth->mii_bus->write = mtk_mdio_write_c22; 814 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 815 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 816 eth->mii_bus->priv = eth; 817 eth->mii_bus->parent = eth->dev; 818 819 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 820 ret = of_mdiobus_register(eth->mii_bus, mii_np); 821 822 err_put_node: 823 of_node_put(mii_np); 824 return ret; 825 } 826 827 static void mtk_mdio_cleanup(struct mtk_eth *eth) 828 { 829 if (!eth->mii_bus) 830 return; 831 832 mdiobus_unregister(eth->mii_bus); 833 } 834 835 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 836 { 837 unsigned long flags; 838 u32 val; 839 840 spin_lock_irqsave(ð->tx_irq_lock, flags); 841 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 842 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 843 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 844 } 845 846 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 847 { 848 unsigned long flags; 849 u32 val; 850 851 spin_lock_irqsave(ð->tx_irq_lock, flags); 852 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 853 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 854 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 855 } 856 857 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 858 { 859 unsigned long flags; 860 u32 val; 861 862 spin_lock_irqsave(ð->rx_irq_lock, flags); 863 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 864 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 865 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 866 } 867 868 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 869 { 870 unsigned long flags; 871 u32 val; 872 873 spin_lock_irqsave(ð->rx_irq_lock, flags); 874 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 875 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 876 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 877 } 878 879 static int mtk_set_mac_address(struct net_device *dev, void *p) 880 { 881 int ret = eth_mac_addr(dev, p); 882 struct mtk_mac *mac = netdev_priv(dev); 883 struct mtk_eth *eth = mac->hw; 884 const char *macaddr = dev->dev_addr; 885 886 if (ret) 887 return ret; 888 889 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 890 return -EBUSY; 891 892 spin_lock_bh(&mac->hw->page_lock); 893 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 894 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 895 MT7628_SDM_MAC_ADRH); 896 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 897 (macaddr[4] << 8) | macaddr[5], 898 MT7628_SDM_MAC_ADRL); 899 } else { 900 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 901 MTK_GDMA_MAC_ADRH(mac->id)); 902 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 903 (macaddr[4] << 8) | macaddr[5], 904 MTK_GDMA_MAC_ADRL(mac->id)); 905 } 906 spin_unlock_bh(&mac->hw->page_lock); 907 908 return 0; 909 } 910 911 void mtk_stats_update_mac(struct mtk_mac *mac) 912 { 913 struct mtk_hw_stats *hw_stats = mac->hw_stats; 914 struct mtk_eth *eth = mac->hw; 915 916 u64_stats_update_begin(&hw_stats->syncp); 917 918 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 919 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 920 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 921 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 922 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 923 hw_stats->rx_checksum_errors += 924 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 925 } else { 926 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 927 unsigned int offs = hw_stats->reg_offset; 928 u64 stats; 929 930 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 931 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 932 if (stats) 933 hw_stats->rx_bytes += (stats << 32); 934 hw_stats->rx_packets += 935 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 936 hw_stats->rx_overflow += 937 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 938 hw_stats->rx_fcs_errors += 939 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 940 hw_stats->rx_short_errors += 941 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 942 hw_stats->rx_long_errors += 943 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 944 hw_stats->rx_checksum_errors += 945 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 946 hw_stats->rx_flow_control_packets += 947 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 948 hw_stats->tx_skip += 949 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 950 hw_stats->tx_collisions += 951 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 952 hw_stats->tx_bytes += 953 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 954 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 955 if (stats) 956 hw_stats->tx_bytes += (stats << 32); 957 hw_stats->tx_packets += 958 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 959 } 960 961 u64_stats_update_end(&hw_stats->syncp); 962 } 963 964 static void mtk_stats_update(struct mtk_eth *eth) 965 { 966 int i; 967 968 for (i = 0; i < MTK_MAC_COUNT; i++) { 969 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 970 continue; 971 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 972 mtk_stats_update_mac(eth->mac[i]); 973 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 974 } 975 } 976 } 977 978 static void mtk_get_stats64(struct net_device *dev, 979 struct rtnl_link_stats64 *storage) 980 { 981 struct mtk_mac *mac = netdev_priv(dev); 982 struct mtk_hw_stats *hw_stats = mac->hw_stats; 983 unsigned int start; 984 985 if (netif_running(dev) && netif_device_present(dev)) { 986 if (spin_trylock_bh(&hw_stats->stats_lock)) { 987 mtk_stats_update_mac(mac); 988 spin_unlock_bh(&hw_stats->stats_lock); 989 } 990 } 991 992 do { 993 start = u64_stats_fetch_begin(&hw_stats->syncp); 994 storage->rx_packets = hw_stats->rx_packets; 995 storage->tx_packets = hw_stats->tx_packets; 996 storage->rx_bytes = hw_stats->rx_bytes; 997 storage->tx_bytes = hw_stats->tx_bytes; 998 storage->collisions = hw_stats->tx_collisions; 999 storage->rx_length_errors = hw_stats->rx_short_errors + 1000 hw_stats->rx_long_errors; 1001 storage->rx_over_errors = hw_stats->rx_overflow; 1002 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1003 storage->rx_errors = hw_stats->rx_checksum_errors; 1004 storage->tx_aborted_errors = hw_stats->tx_skip; 1005 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1006 1007 storage->tx_errors = dev->stats.tx_errors; 1008 storage->rx_dropped = dev->stats.rx_dropped; 1009 storage->tx_dropped = dev->stats.tx_dropped; 1010 } 1011 1012 static inline int mtk_max_frag_size(int mtu) 1013 { 1014 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1015 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1016 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1017 1018 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1019 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1020 } 1021 1022 static inline int mtk_max_buf_size(int frag_size) 1023 { 1024 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1025 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1026 1027 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1028 1029 return buf_size; 1030 } 1031 1032 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1033 struct mtk_rx_dma_v2 *dma_rxd) 1034 { 1035 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1036 if (!(rxd->rxd2 & RX_DMA_DONE)) 1037 return false; 1038 1039 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1040 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1041 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1042 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1043 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1044 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1045 } 1046 1047 return true; 1048 } 1049 1050 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1051 { 1052 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1053 unsigned long data; 1054 1055 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1056 get_order(size)); 1057 1058 return (void *)data; 1059 } 1060 1061 /* the qdma core needs scratch memory to be setup */ 1062 static int mtk_init_fq_dma(struct mtk_eth *eth) 1063 { 1064 const struct mtk_soc_data *soc = eth->soc; 1065 dma_addr_t phy_ring_tail; 1066 int cnt = MTK_QDMA_RING_SIZE; 1067 dma_addr_t dma_addr; 1068 int i; 1069 1070 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1071 cnt * soc->txrx.txd_size, 1072 ð->phy_scratch_ring, 1073 GFP_KERNEL); 1074 if (unlikely(!eth->scratch_ring)) 1075 return -ENOMEM; 1076 1077 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1078 if (unlikely(!eth->scratch_head)) 1079 return -ENOMEM; 1080 1081 dma_addr = dma_map_single(eth->dma_dev, 1082 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1083 DMA_FROM_DEVICE); 1084 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1085 return -ENOMEM; 1086 1087 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1088 1089 for (i = 0; i < cnt; i++) { 1090 struct mtk_tx_dma_v2 *txd; 1091 1092 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1093 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1094 if (i < cnt - 1) 1095 txd->txd2 = eth->phy_scratch_ring + 1096 (i + 1) * soc->txrx.txd_size; 1097 1098 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1099 txd->txd4 = 0; 1100 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1101 txd->txd5 = 0; 1102 txd->txd6 = 0; 1103 txd->txd7 = 0; 1104 txd->txd8 = 0; 1105 } 1106 } 1107 1108 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1109 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1110 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1111 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1112 1113 return 0; 1114 } 1115 1116 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1117 { 1118 return ring->dma + (desc - ring->phys); 1119 } 1120 1121 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1122 void *txd, u32 txd_size) 1123 { 1124 int idx = (txd - ring->dma) / txd_size; 1125 1126 return &ring->buf[idx]; 1127 } 1128 1129 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1130 struct mtk_tx_dma *dma) 1131 { 1132 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1133 } 1134 1135 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1136 { 1137 return (dma - ring->dma) / txd_size; 1138 } 1139 1140 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1141 struct xdp_frame_bulk *bq, bool napi) 1142 { 1143 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1144 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1145 dma_unmap_single(eth->dma_dev, 1146 dma_unmap_addr(tx_buf, dma_addr0), 1147 dma_unmap_len(tx_buf, dma_len0), 1148 DMA_TO_DEVICE); 1149 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1150 dma_unmap_page(eth->dma_dev, 1151 dma_unmap_addr(tx_buf, dma_addr0), 1152 dma_unmap_len(tx_buf, dma_len0), 1153 DMA_TO_DEVICE); 1154 } 1155 } else { 1156 if (dma_unmap_len(tx_buf, dma_len0)) { 1157 dma_unmap_page(eth->dma_dev, 1158 dma_unmap_addr(tx_buf, dma_addr0), 1159 dma_unmap_len(tx_buf, dma_len0), 1160 DMA_TO_DEVICE); 1161 } 1162 1163 if (dma_unmap_len(tx_buf, dma_len1)) { 1164 dma_unmap_page(eth->dma_dev, 1165 dma_unmap_addr(tx_buf, dma_addr1), 1166 dma_unmap_len(tx_buf, dma_len1), 1167 DMA_TO_DEVICE); 1168 } 1169 } 1170 1171 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1172 if (tx_buf->type == MTK_TYPE_SKB) { 1173 struct sk_buff *skb = tx_buf->data; 1174 1175 if (napi) 1176 napi_consume_skb(skb, napi); 1177 else 1178 dev_kfree_skb_any(skb); 1179 } else { 1180 struct xdp_frame *xdpf = tx_buf->data; 1181 1182 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1183 xdp_return_frame_rx_napi(xdpf); 1184 else if (bq) 1185 xdp_return_frame_bulk(xdpf, bq); 1186 else 1187 xdp_return_frame(xdpf); 1188 } 1189 } 1190 tx_buf->flags = 0; 1191 tx_buf->data = NULL; 1192 } 1193 1194 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1195 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1196 size_t size, int idx) 1197 { 1198 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1199 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1200 dma_unmap_len_set(tx_buf, dma_len0, size); 1201 } else { 1202 if (idx & 1) { 1203 txd->txd3 = mapped_addr; 1204 txd->txd2 |= TX_DMA_PLEN1(size); 1205 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1206 dma_unmap_len_set(tx_buf, dma_len1, size); 1207 } else { 1208 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1209 txd->txd1 = mapped_addr; 1210 txd->txd2 = TX_DMA_PLEN0(size); 1211 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1212 dma_unmap_len_set(tx_buf, dma_len0, size); 1213 } 1214 } 1215 } 1216 1217 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1218 struct mtk_tx_dma_desc_info *info) 1219 { 1220 struct mtk_mac *mac = netdev_priv(dev); 1221 struct mtk_eth *eth = mac->hw; 1222 struct mtk_tx_dma *desc = txd; 1223 u32 data; 1224 1225 WRITE_ONCE(desc->txd1, info->addr); 1226 1227 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1228 FIELD_PREP(TX_DMA_PQID, info->qid); 1229 if (info->last) 1230 data |= TX_DMA_LS0; 1231 WRITE_ONCE(desc->txd3, data); 1232 1233 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1234 if (info->first) { 1235 if (info->gso) 1236 data |= TX_DMA_TSO; 1237 /* tx checksum offload */ 1238 if (info->csum) 1239 data |= TX_DMA_CHKSUM; 1240 /* vlan header offload */ 1241 if (info->vlan) 1242 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1243 } 1244 WRITE_ONCE(desc->txd4, data); 1245 } 1246 1247 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1248 struct mtk_tx_dma_desc_info *info) 1249 { 1250 struct mtk_mac *mac = netdev_priv(dev); 1251 struct mtk_tx_dma_v2 *desc = txd; 1252 struct mtk_eth *eth = mac->hw; 1253 u32 data; 1254 1255 WRITE_ONCE(desc->txd1, info->addr); 1256 1257 data = TX_DMA_PLEN0(info->size); 1258 if (info->last) 1259 data |= TX_DMA_LS0; 1260 WRITE_ONCE(desc->txd3, data); 1261 1262 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1263 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1264 WRITE_ONCE(desc->txd4, data); 1265 1266 data = 0; 1267 if (info->first) { 1268 if (info->gso) 1269 data |= TX_DMA_TSO_V2; 1270 /* tx checksum offload */ 1271 if (info->csum) 1272 data |= TX_DMA_CHKSUM_V2; 1273 } 1274 WRITE_ONCE(desc->txd5, data); 1275 1276 data = 0; 1277 if (info->first && info->vlan) 1278 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1279 WRITE_ONCE(desc->txd6, data); 1280 1281 WRITE_ONCE(desc->txd7, 0); 1282 WRITE_ONCE(desc->txd8, 0); 1283 } 1284 1285 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1286 struct mtk_tx_dma_desc_info *info) 1287 { 1288 struct mtk_mac *mac = netdev_priv(dev); 1289 struct mtk_eth *eth = mac->hw; 1290 1291 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1292 mtk_tx_set_dma_desc_v2(dev, txd, info); 1293 else 1294 mtk_tx_set_dma_desc_v1(dev, txd, info); 1295 } 1296 1297 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1298 int tx_num, struct mtk_tx_ring *ring, bool gso) 1299 { 1300 struct mtk_tx_dma_desc_info txd_info = { 1301 .size = skb_headlen(skb), 1302 .gso = gso, 1303 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1304 .vlan = skb_vlan_tag_present(skb), 1305 .qid = skb_get_queue_mapping(skb), 1306 .vlan_tci = skb_vlan_tag_get(skb), 1307 .first = true, 1308 .last = !skb_is_nonlinear(skb), 1309 }; 1310 struct netdev_queue *txq; 1311 struct mtk_mac *mac = netdev_priv(dev); 1312 struct mtk_eth *eth = mac->hw; 1313 const struct mtk_soc_data *soc = eth->soc; 1314 struct mtk_tx_dma *itxd, *txd; 1315 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1316 struct mtk_tx_buf *itx_buf, *tx_buf; 1317 int i, n_desc = 1; 1318 int queue = skb_get_queue_mapping(skb); 1319 int k = 0; 1320 1321 txq = netdev_get_tx_queue(dev, queue); 1322 itxd = ring->next_free; 1323 itxd_pdma = qdma_to_pdma(ring, itxd); 1324 if (itxd == ring->last_free) 1325 return -ENOMEM; 1326 1327 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1328 memset(itx_buf, 0, sizeof(*itx_buf)); 1329 1330 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1331 DMA_TO_DEVICE); 1332 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1333 return -ENOMEM; 1334 1335 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1336 1337 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1338 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1339 MTK_TX_FLAGS_FPORT1; 1340 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1341 k++); 1342 1343 /* TX SG offload */ 1344 txd = itxd; 1345 txd_pdma = qdma_to_pdma(ring, txd); 1346 1347 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1348 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1349 unsigned int offset = 0; 1350 int frag_size = skb_frag_size(frag); 1351 1352 while (frag_size) { 1353 bool new_desc = true; 1354 1355 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1356 (i & 0x1)) { 1357 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1358 txd_pdma = qdma_to_pdma(ring, txd); 1359 if (txd == ring->last_free) 1360 goto err_dma; 1361 1362 n_desc++; 1363 } else { 1364 new_desc = false; 1365 } 1366 1367 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1368 txd_info.size = min_t(unsigned int, frag_size, 1369 soc->txrx.dma_max_len); 1370 txd_info.qid = queue; 1371 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1372 !(frag_size - txd_info.size); 1373 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1374 offset, txd_info.size, 1375 DMA_TO_DEVICE); 1376 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1377 goto err_dma; 1378 1379 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1380 1381 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1382 soc->txrx.txd_size); 1383 if (new_desc) 1384 memset(tx_buf, 0, sizeof(*tx_buf)); 1385 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1386 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1387 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1388 MTK_TX_FLAGS_FPORT1; 1389 1390 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1391 txd_info.size, k++); 1392 1393 frag_size -= txd_info.size; 1394 offset += txd_info.size; 1395 } 1396 } 1397 1398 /* store skb to cleanup */ 1399 itx_buf->type = MTK_TYPE_SKB; 1400 itx_buf->data = skb; 1401 1402 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1403 if (k & 0x1) 1404 txd_pdma->txd2 |= TX_DMA_LS0; 1405 else 1406 txd_pdma->txd2 |= TX_DMA_LS1; 1407 } 1408 1409 netdev_tx_sent_queue(txq, skb->len); 1410 skb_tx_timestamp(skb); 1411 1412 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1413 atomic_sub(n_desc, &ring->free_count); 1414 1415 /* make sure that all changes to the dma ring are flushed before we 1416 * continue 1417 */ 1418 wmb(); 1419 1420 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1421 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1422 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1423 } else { 1424 int next_idx; 1425 1426 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1427 ring->dma_size); 1428 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1429 } 1430 1431 return 0; 1432 1433 err_dma: 1434 do { 1435 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1436 1437 /* unmap dma */ 1438 mtk_tx_unmap(eth, tx_buf, NULL, false); 1439 1440 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1441 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1442 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1443 1444 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1445 itxd_pdma = qdma_to_pdma(ring, itxd); 1446 } while (itxd != txd); 1447 1448 return -ENOMEM; 1449 } 1450 1451 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1452 { 1453 int i, nfrags = 1; 1454 skb_frag_t *frag; 1455 1456 if (skb_is_gso(skb)) { 1457 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1458 frag = &skb_shinfo(skb)->frags[i]; 1459 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1460 eth->soc->txrx.dma_max_len); 1461 } 1462 } else { 1463 nfrags += skb_shinfo(skb)->nr_frags; 1464 } 1465 1466 return nfrags; 1467 } 1468 1469 static int mtk_queue_stopped(struct mtk_eth *eth) 1470 { 1471 int i; 1472 1473 for (i = 0; i < MTK_MAC_COUNT; i++) { 1474 if (!eth->netdev[i]) 1475 continue; 1476 if (netif_queue_stopped(eth->netdev[i])) 1477 return 1; 1478 } 1479 1480 return 0; 1481 } 1482 1483 static void mtk_wake_queue(struct mtk_eth *eth) 1484 { 1485 int i; 1486 1487 for (i = 0; i < MTK_MAC_COUNT; i++) { 1488 if (!eth->netdev[i]) 1489 continue; 1490 netif_tx_wake_all_queues(eth->netdev[i]); 1491 } 1492 } 1493 1494 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1495 { 1496 struct mtk_mac *mac = netdev_priv(dev); 1497 struct mtk_eth *eth = mac->hw; 1498 struct mtk_tx_ring *ring = ð->tx_ring; 1499 struct net_device_stats *stats = &dev->stats; 1500 bool gso = false; 1501 int tx_num; 1502 1503 /* normally we can rely on the stack not calling this more than once, 1504 * however we have 2 queues running on the same ring so we need to lock 1505 * the ring access 1506 */ 1507 spin_lock(ð->page_lock); 1508 1509 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1510 goto drop; 1511 1512 tx_num = mtk_cal_txd_req(eth, skb); 1513 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1514 netif_tx_stop_all_queues(dev); 1515 netif_err(eth, tx_queued, dev, 1516 "Tx Ring full when queue awake!\n"); 1517 spin_unlock(ð->page_lock); 1518 return NETDEV_TX_BUSY; 1519 } 1520 1521 /* TSO: fill MSS info in tcp checksum field */ 1522 if (skb_is_gso(skb)) { 1523 if (skb_cow_head(skb, 0)) { 1524 netif_warn(eth, tx_err, dev, 1525 "GSO expand head fail.\n"); 1526 goto drop; 1527 } 1528 1529 if (skb_shinfo(skb)->gso_type & 1530 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1531 gso = true; 1532 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1533 } 1534 } 1535 1536 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1537 goto drop; 1538 1539 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1540 netif_tx_stop_all_queues(dev); 1541 1542 spin_unlock(ð->page_lock); 1543 1544 return NETDEV_TX_OK; 1545 1546 drop: 1547 spin_unlock(ð->page_lock); 1548 stats->tx_dropped++; 1549 dev_kfree_skb_any(skb); 1550 return NETDEV_TX_OK; 1551 } 1552 1553 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1554 { 1555 int i; 1556 struct mtk_rx_ring *ring; 1557 int idx; 1558 1559 if (!eth->hwlro) 1560 return ð->rx_ring[0]; 1561 1562 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1563 struct mtk_rx_dma *rxd; 1564 1565 ring = ð->rx_ring[i]; 1566 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1567 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1568 if (rxd->rxd2 & RX_DMA_DONE) { 1569 ring->calc_idx_update = true; 1570 return ring; 1571 } 1572 } 1573 1574 return NULL; 1575 } 1576 1577 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1578 { 1579 struct mtk_rx_ring *ring; 1580 int i; 1581 1582 if (!eth->hwlro) { 1583 ring = ð->rx_ring[0]; 1584 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1585 } else { 1586 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1587 ring = ð->rx_ring[i]; 1588 if (ring->calc_idx_update) { 1589 ring->calc_idx_update = false; 1590 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1591 } 1592 } 1593 } 1594 } 1595 1596 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1597 { 1598 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1599 } 1600 1601 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1602 struct xdp_rxq_info *xdp_q, 1603 int id, int size) 1604 { 1605 struct page_pool_params pp_params = { 1606 .order = 0, 1607 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1608 .pool_size = size, 1609 .nid = NUMA_NO_NODE, 1610 .dev = eth->dma_dev, 1611 .offset = MTK_PP_HEADROOM, 1612 .max_len = MTK_PP_MAX_BUF_SIZE, 1613 }; 1614 struct page_pool *pp; 1615 int err; 1616 1617 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1618 : DMA_FROM_DEVICE; 1619 pp = page_pool_create(&pp_params); 1620 if (IS_ERR(pp)) 1621 return pp; 1622 1623 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1624 eth->rx_napi.napi_id, PAGE_SIZE); 1625 if (err < 0) 1626 goto err_free_pp; 1627 1628 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1629 if (err) 1630 goto err_unregister_rxq; 1631 1632 return pp; 1633 1634 err_unregister_rxq: 1635 xdp_rxq_info_unreg(xdp_q); 1636 err_free_pp: 1637 page_pool_destroy(pp); 1638 1639 return ERR_PTR(err); 1640 } 1641 1642 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1643 gfp_t gfp_mask) 1644 { 1645 struct page *page; 1646 1647 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1648 if (!page) 1649 return NULL; 1650 1651 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1652 return page_address(page); 1653 } 1654 1655 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1656 { 1657 if (ring->page_pool) 1658 page_pool_put_full_page(ring->page_pool, 1659 virt_to_head_page(data), napi); 1660 else 1661 skb_free_frag(data); 1662 } 1663 1664 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1665 struct mtk_tx_dma_desc_info *txd_info, 1666 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1667 void *data, u16 headroom, int index, bool dma_map) 1668 { 1669 struct mtk_tx_ring *ring = ð->tx_ring; 1670 struct mtk_mac *mac = netdev_priv(dev); 1671 struct mtk_tx_dma *txd_pdma; 1672 1673 if (dma_map) { /* ndo_xdp_xmit */ 1674 txd_info->addr = dma_map_single(eth->dma_dev, data, 1675 txd_info->size, DMA_TO_DEVICE); 1676 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1677 return -ENOMEM; 1678 1679 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1680 } else { 1681 struct page *page = virt_to_head_page(data); 1682 1683 txd_info->addr = page_pool_get_dma_addr(page) + 1684 sizeof(struct xdp_frame) + headroom; 1685 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1686 txd_info->size, DMA_BIDIRECTIONAL); 1687 } 1688 mtk_tx_set_dma_desc(dev, txd, txd_info); 1689 1690 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1691 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1692 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1693 1694 txd_pdma = qdma_to_pdma(ring, txd); 1695 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1696 index); 1697 1698 return 0; 1699 } 1700 1701 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1702 struct net_device *dev, bool dma_map) 1703 { 1704 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1705 const struct mtk_soc_data *soc = eth->soc; 1706 struct mtk_tx_ring *ring = ð->tx_ring; 1707 struct mtk_mac *mac = netdev_priv(dev); 1708 struct mtk_tx_dma_desc_info txd_info = { 1709 .size = xdpf->len, 1710 .first = true, 1711 .last = !xdp_frame_has_frags(xdpf), 1712 .qid = mac->id, 1713 }; 1714 int err, index = 0, n_desc = 1, nr_frags; 1715 struct mtk_tx_buf *htx_buf, *tx_buf; 1716 struct mtk_tx_dma *htxd, *txd; 1717 void *data = xdpf->data; 1718 1719 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1720 return -EBUSY; 1721 1722 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1723 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1724 return -EBUSY; 1725 1726 spin_lock(ð->page_lock); 1727 1728 txd = ring->next_free; 1729 if (txd == ring->last_free) { 1730 spin_unlock(ð->page_lock); 1731 return -ENOMEM; 1732 } 1733 htxd = txd; 1734 1735 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1736 memset(tx_buf, 0, sizeof(*tx_buf)); 1737 htx_buf = tx_buf; 1738 1739 for (;;) { 1740 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1741 data, xdpf->headroom, index, dma_map); 1742 if (err < 0) 1743 goto unmap; 1744 1745 if (txd_info.last) 1746 break; 1747 1748 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1749 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1750 if (txd == ring->last_free) 1751 goto unmap; 1752 1753 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1754 soc->txrx.txd_size); 1755 memset(tx_buf, 0, sizeof(*tx_buf)); 1756 n_desc++; 1757 } 1758 1759 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1760 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1761 txd_info.last = index + 1 == nr_frags; 1762 txd_info.qid = mac->id; 1763 data = skb_frag_address(&sinfo->frags[index]); 1764 1765 index++; 1766 } 1767 /* store xdpf for cleanup */ 1768 htx_buf->data = xdpf; 1769 1770 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1771 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1772 1773 if (index & 1) 1774 txd_pdma->txd2 |= TX_DMA_LS0; 1775 else 1776 txd_pdma->txd2 |= TX_DMA_LS1; 1777 } 1778 1779 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1780 atomic_sub(n_desc, &ring->free_count); 1781 1782 /* make sure that all changes to the dma ring are flushed before we 1783 * continue 1784 */ 1785 wmb(); 1786 1787 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1788 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1789 } else { 1790 int idx; 1791 1792 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1793 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1794 MT7628_TX_CTX_IDX0); 1795 } 1796 1797 spin_unlock(ð->page_lock); 1798 1799 return 0; 1800 1801 unmap: 1802 while (htxd != txd) { 1803 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1804 mtk_tx_unmap(eth, tx_buf, NULL, false); 1805 1806 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1807 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1808 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1809 1810 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1811 } 1812 1813 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1814 } 1815 1816 spin_unlock(ð->page_lock); 1817 1818 return err; 1819 } 1820 1821 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1822 struct xdp_frame **frames, u32 flags) 1823 { 1824 struct mtk_mac *mac = netdev_priv(dev); 1825 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1826 struct mtk_eth *eth = mac->hw; 1827 int i, nxmit = 0; 1828 1829 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1830 return -EINVAL; 1831 1832 for (i = 0; i < num_frame; i++) { 1833 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1834 break; 1835 nxmit++; 1836 } 1837 1838 u64_stats_update_begin(&hw_stats->syncp); 1839 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1840 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1841 u64_stats_update_end(&hw_stats->syncp); 1842 1843 return nxmit; 1844 } 1845 1846 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1847 struct xdp_buff *xdp, struct net_device *dev) 1848 { 1849 struct mtk_mac *mac = netdev_priv(dev); 1850 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1851 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1852 struct bpf_prog *prog; 1853 u32 act = XDP_PASS; 1854 1855 rcu_read_lock(); 1856 1857 prog = rcu_dereference(eth->prog); 1858 if (!prog) 1859 goto out; 1860 1861 act = bpf_prog_run_xdp(prog, xdp); 1862 switch (act) { 1863 case XDP_PASS: 1864 count = &hw_stats->xdp_stats.rx_xdp_pass; 1865 goto update_stats; 1866 case XDP_REDIRECT: 1867 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1868 act = XDP_DROP; 1869 break; 1870 } 1871 1872 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1873 goto update_stats; 1874 case XDP_TX: { 1875 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1876 1877 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1878 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1879 act = XDP_DROP; 1880 break; 1881 } 1882 1883 count = &hw_stats->xdp_stats.rx_xdp_tx; 1884 goto update_stats; 1885 } 1886 default: 1887 bpf_warn_invalid_xdp_action(dev, prog, act); 1888 fallthrough; 1889 case XDP_ABORTED: 1890 trace_xdp_exception(dev, prog, act); 1891 fallthrough; 1892 case XDP_DROP: 1893 break; 1894 } 1895 1896 page_pool_put_full_page(ring->page_pool, 1897 virt_to_head_page(xdp->data), true); 1898 1899 update_stats: 1900 u64_stats_update_begin(&hw_stats->syncp); 1901 *count = *count + 1; 1902 u64_stats_update_end(&hw_stats->syncp); 1903 out: 1904 rcu_read_unlock(); 1905 1906 return act; 1907 } 1908 1909 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1910 struct mtk_eth *eth) 1911 { 1912 struct dim_sample dim_sample = {}; 1913 struct mtk_rx_ring *ring; 1914 bool xdp_flush = false; 1915 int idx; 1916 struct sk_buff *skb; 1917 u8 *data, *new_data; 1918 struct mtk_rx_dma_v2 *rxd, trxd; 1919 int done = 0, bytes = 0; 1920 1921 while (done < budget) { 1922 unsigned int pktlen, *rxdcsum; 1923 bool has_hwaccel_tag = false; 1924 struct net_device *netdev; 1925 u16 vlan_proto, vlan_tci; 1926 dma_addr_t dma_addr; 1927 u32 hash, reason; 1928 int mac = 0; 1929 1930 ring = mtk_get_rx_ring(eth); 1931 if (unlikely(!ring)) 1932 goto rx_done; 1933 1934 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1935 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1936 data = ring->data[idx]; 1937 1938 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1939 break; 1940 1941 /* find out which mac the packet come from. values start at 1 */ 1942 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1943 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1944 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1945 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1946 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1947 1948 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1949 !eth->netdev[mac])) 1950 goto release_desc; 1951 1952 netdev = eth->netdev[mac]; 1953 1954 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1955 goto release_desc; 1956 1957 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1958 1959 /* alloc new buffer */ 1960 if (ring->page_pool) { 1961 struct page *page = virt_to_head_page(data); 1962 struct xdp_buff xdp; 1963 u32 ret; 1964 1965 new_data = mtk_page_pool_get_buff(ring->page_pool, 1966 &dma_addr, 1967 GFP_ATOMIC); 1968 if (unlikely(!new_data)) { 1969 netdev->stats.rx_dropped++; 1970 goto release_desc; 1971 } 1972 1973 dma_sync_single_for_cpu(eth->dma_dev, 1974 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1975 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1976 1977 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1978 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1979 false); 1980 xdp_buff_clear_frags_flag(&xdp); 1981 1982 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1983 if (ret == XDP_REDIRECT) 1984 xdp_flush = true; 1985 1986 if (ret != XDP_PASS) 1987 goto skip_rx; 1988 1989 skb = build_skb(data, PAGE_SIZE); 1990 if (unlikely(!skb)) { 1991 page_pool_put_full_page(ring->page_pool, 1992 page, true); 1993 netdev->stats.rx_dropped++; 1994 goto skip_rx; 1995 } 1996 1997 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1998 skb_put(skb, xdp.data_end - xdp.data); 1999 skb_mark_for_recycle(skb); 2000 } else { 2001 if (ring->frag_size <= PAGE_SIZE) 2002 new_data = napi_alloc_frag(ring->frag_size); 2003 else 2004 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2005 2006 if (unlikely(!new_data)) { 2007 netdev->stats.rx_dropped++; 2008 goto release_desc; 2009 } 2010 2011 dma_addr = dma_map_single(eth->dma_dev, 2012 new_data + NET_SKB_PAD + eth->ip_align, 2013 ring->buf_size, DMA_FROM_DEVICE); 2014 if (unlikely(dma_mapping_error(eth->dma_dev, 2015 dma_addr))) { 2016 skb_free_frag(new_data); 2017 netdev->stats.rx_dropped++; 2018 goto release_desc; 2019 } 2020 2021 dma_unmap_single(eth->dma_dev, trxd.rxd1, 2022 ring->buf_size, DMA_FROM_DEVICE); 2023 2024 skb = build_skb(data, ring->frag_size); 2025 if (unlikely(!skb)) { 2026 netdev->stats.rx_dropped++; 2027 skb_free_frag(data); 2028 goto skip_rx; 2029 } 2030 2031 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2032 skb_put(skb, pktlen); 2033 } 2034 2035 skb->dev = netdev; 2036 bytes += skb->len; 2037 2038 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2039 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2040 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2041 if (hash != MTK_RXD5_FOE_ENTRY) 2042 skb_set_hash(skb, jhash_1word(hash, 0), 2043 PKT_HASH_TYPE_L4); 2044 rxdcsum = &trxd.rxd3; 2045 } else { 2046 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2047 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2048 if (hash != MTK_RXD4_FOE_ENTRY) 2049 skb_set_hash(skb, jhash_1word(hash, 0), 2050 PKT_HASH_TYPE_L4); 2051 rxdcsum = &trxd.rxd4; 2052 } 2053 2054 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2055 skb->ip_summed = CHECKSUM_UNNECESSARY; 2056 else 2057 skb_checksum_none_assert(skb); 2058 skb->protocol = eth_type_trans(skb, netdev); 2059 2060 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2061 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2062 if (trxd.rxd3 & RX_DMA_VTAG_V2) { 2063 vlan_proto = RX_DMA_VPID(trxd.rxd4); 2064 vlan_tci = RX_DMA_VID(trxd.rxd4); 2065 has_hwaccel_tag = true; 2066 } 2067 } else if (trxd.rxd2 & RX_DMA_VTAG) { 2068 vlan_proto = RX_DMA_VPID(trxd.rxd3); 2069 vlan_tci = RX_DMA_VID(trxd.rxd3); 2070 has_hwaccel_tag = true; 2071 } 2072 } 2073 2074 /* When using VLAN untagging in combination with DSA, the 2075 * hardware treats the MTK special tag as a VLAN and untags it. 2076 */ 2077 if (has_hwaccel_tag && netdev_uses_dsa(netdev)) { 2078 unsigned int port = vlan_proto & GENMASK(2, 0); 2079 2080 if (port < ARRAY_SIZE(eth->dsa_meta) && 2081 eth->dsa_meta[port]) 2082 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2083 } else if (has_hwaccel_tag) { 2084 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vlan_tci); 2085 } 2086 2087 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2088 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2089 2090 skb_record_rx_queue(skb, 0); 2091 napi_gro_receive(napi, skb); 2092 2093 skip_rx: 2094 ring->data[idx] = new_data; 2095 rxd->rxd1 = (unsigned int)dma_addr; 2096 release_desc: 2097 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2098 rxd->rxd2 = RX_DMA_LSO; 2099 else 2100 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2101 2102 ring->calc_idx = idx; 2103 done++; 2104 } 2105 2106 rx_done: 2107 if (done) { 2108 /* make sure that all changes to the dma ring are flushed before 2109 * we continue 2110 */ 2111 wmb(); 2112 mtk_update_rx_cpu_idx(eth); 2113 } 2114 2115 eth->rx_packets += done; 2116 eth->rx_bytes += bytes; 2117 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2118 &dim_sample); 2119 net_dim(ð->rx_dim, dim_sample); 2120 2121 if (xdp_flush) 2122 xdp_do_flush_map(); 2123 2124 return done; 2125 } 2126 2127 struct mtk_poll_state { 2128 struct netdev_queue *txq; 2129 unsigned int total; 2130 unsigned int done; 2131 unsigned int bytes; 2132 }; 2133 2134 static void 2135 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2136 struct sk_buff *skb) 2137 { 2138 struct netdev_queue *txq; 2139 struct net_device *dev; 2140 unsigned int bytes = skb->len; 2141 2142 state->total++; 2143 eth->tx_packets++; 2144 eth->tx_bytes += bytes; 2145 2146 dev = eth->netdev[mac]; 2147 if (!dev) 2148 return; 2149 2150 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2151 if (state->txq == txq) { 2152 state->done++; 2153 state->bytes += bytes; 2154 return; 2155 } 2156 2157 if (state->txq) 2158 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2159 2160 state->txq = txq; 2161 state->done = 1; 2162 state->bytes = bytes; 2163 } 2164 2165 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2166 struct mtk_poll_state *state) 2167 { 2168 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2169 struct mtk_tx_ring *ring = ð->tx_ring; 2170 struct mtk_tx_buf *tx_buf; 2171 struct xdp_frame_bulk bq; 2172 struct mtk_tx_dma *desc; 2173 u32 cpu, dma; 2174 2175 cpu = ring->last_free_ptr; 2176 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2177 2178 desc = mtk_qdma_phys_to_virt(ring, cpu); 2179 xdp_frame_bulk_init(&bq); 2180 2181 while ((cpu != dma) && budget) { 2182 u32 next_cpu = desc->txd2; 2183 int mac = 0; 2184 2185 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2186 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2187 break; 2188 2189 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2190 eth->soc->txrx.txd_size); 2191 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2192 mac = 1; 2193 2194 if (!tx_buf->data) 2195 break; 2196 2197 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2198 if (tx_buf->type == MTK_TYPE_SKB) 2199 mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2200 2201 budget--; 2202 } 2203 mtk_tx_unmap(eth, tx_buf, &bq, true); 2204 2205 ring->last_free = desc; 2206 atomic_inc(&ring->free_count); 2207 2208 cpu = next_cpu; 2209 } 2210 xdp_flush_frame_bulk(&bq); 2211 2212 ring->last_free_ptr = cpu; 2213 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2214 2215 return budget; 2216 } 2217 2218 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2219 struct mtk_poll_state *state) 2220 { 2221 struct mtk_tx_ring *ring = ð->tx_ring; 2222 struct mtk_tx_buf *tx_buf; 2223 struct xdp_frame_bulk bq; 2224 struct mtk_tx_dma *desc; 2225 u32 cpu, dma; 2226 2227 cpu = ring->cpu_idx; 2228 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2229 xdp_frame_bulk_init(&bq); 2230 2231 while ((cpu != dma) && budget) { 2232 tx_buf = &ring->buf[cpu]; 2233 if (!tx_buf->data) 2234 break; 2235 2236 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2237 if (tx_buf->type == MTK_TYPE_SKB) 2238 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2239 budget--; 2240 } 2241 mtk_tx_unmap(eth, tx_buf, &bq, true); 2242 2243 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2244 ring->last_free = desc; 2245 atomic_inc(&ring->free_count); 2246 2247 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2248 } 2249 xdp_flush_frame_bulk(&bq); 2250 2251 ring->cpu_idx = cpu; 2252 2253 return budget; 2254 } 2255 2256 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2257 { 2258 struct mtk_tx_ring *ring = ð->tx_ring; 2259 struct dim_sample dim_sample = {}; 2260 struct mtk_poll_state state = {}; 2261 2262 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2263 budget = mtk_poll_tx_qdma(eth, budget, &state); 2264 else 2265 budget = mtk_poll_tx_pdma(eth, budget, &state); 2266 2267 if (state.txq) 2268 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2269 2270 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2271 &dim_sample); 2272 net_dim(ð->tx_dim, dim_sample); 2273 2274 if (mtk_queue_stopped(eth) && 2275 (atomic_read(&ring->free_count) > ring->thresh)) 2276 mtk_wake_queue(eth); 2277 2278 return state.total; 2279 } 2280 2281 static void mtk_handle_status_irq(struct mtk_eth *eth) 2282 { 2283 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2284 2285 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2286 mtk_stats_update(eth); 2287 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2288 MTK_INT_STATUS2); 2289 } 2290 } 2291 2292 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2293 { 2294 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2295 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2296 int tx_done = 0; 2297 2298 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2299 mtk_handle_status_irq(eth); 2300 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2301 tx_done = mtk_poll_tx(eth, budget); 2302 2303 if (unlikely(netif_msg_intr(eth))) { 2304 dev_info(eth->dev, 2305 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2306 mtk_r32(eth, reg_map->tx_irq_status), 2307 mtk_r32(eth, reg_map->tx_irq_mask)); 2308 } 2309 2310 if (tx_done == budget) 2311 return budget; 2312 2313 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2314 return budget; 2315 2316 if (napi_complete_done(napi, tx_done)) 2317 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2318 2319 return tx_done; 2320 } 2321 2322 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2323 { 2324 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2325 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2326 int rx_done_total = 0; 2327 2328 mtk_handle_status_irq(eth); 2329 2330 do { 2331 int rx_done; 2332 2333 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2334 reg_map->pdma.irq_status); 2335 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2336 rx_done_total += rx_done; 2337 2338 if (unlikely(netif_msg_intr(eth))) { 2339 dev_info(eth->dev, 2340 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2341 mtk_r32(eth, reg_map->pdma.irq_status), 2342 mtk_r32(eth, reg_map->pdma.irq_mask)); 2343 } 2344 2345 if (rx_done_total == budget) 2346 return budget; 2347 2348 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2349 eth->soc->txrx.rx_irq_done_mask); 2350 2351 if (napi_complete_done(napi, rx_done_total)) 2352 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2353 2354 return rx_done_total; 2355 } 2356 2357 static int mtk_tx_alloc(struct mtk_eth *eth) 2358 { 2359 const struct mtk_soc_data *soc = eth->soc; 2360 struct mtk_tx_ring *ring = ð->tx_ring; 2361 int i, sz = soc->txrx.txd_size; 2362 struct mtk_tx_dma_v2 *txd; 2363 int ring_size; 2364 u32 ofs, val; 2365 2366 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2367 ring_size = MTK_QDMA_RING_SIZE; 2368 else 2369 ring_size = MTK_DMA_SIZE; 2370 2371 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2372 GFP_KERNEL); 2373 if (!ring->buf) 2374 goto no_tx_mem; 2375 2376 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2377 &ring->phys, GFP_KERNEL); 2378 if (!ring->dma) 2379 goto no_tx_mem; 2380 2381 for (i = 0; i < ring_size; i++) { 2382 int next = (i + 1) % ring_size; 2383 u32 next_ptr = ring->phys + next * sz; 2384 2385 txd = ring->dma + i * sz; 2386 txd->txd2 = next_ptr; 2387 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2388 txd->txd4 = 0; 2389 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2390 txd->txd5 = 0; 2391 txd->txd6 = 0; 2392 txd->txd7 = 0; 2393 txd->txd8 = 0; 2394 } 2395 } 2396 2397 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2398 * only as the framework. The real HW descriptors are the PDMA 2399 * descriptors in ring->dma_pdma. 2400 */ 2401 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2402 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2403 &ring->phys_pdma, GFP_KERNEL); 2404 if (!ring->dma_pdma) 2405 goto no_tx_mem; 2406 2407 for (i = 0; i < ring_size; i++) { 2408 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2409 ring->dma_pdma[i].txd4 = 0; 2410 } 2411 } 2412 2413 ring->dma_size = ring_size; 2414 atomic_set(&ring->free_count, ring_size - 2); 2415 ring->next_free = ring->dma; 2416 ring->last_free = (void *)txd; 2417 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2418 ring->thresh = MAX_SKB_FRAGS; 2419 2420 /* make sure that all changes to the dma ring are flushed before we 2421 * continue 2422 */ 2423 wmb(); 2424 2425 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2426 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2427 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2428 mtk_w32(eth, 2429 ring->phys + ((ring_size - 1) * sz), 2430 soc->reg_map->qdma.crx_ptr); 2431 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2432 2433 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2434 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2435 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2436 2437 val = MTK_QTX_SCH_MIN_RATE_EN | 2438 /* minimum: 10 Mbps */ 2439 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2440 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2441 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2442 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2443 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2444 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2445 ofs += MTK_QTX_OFFSET; 2446 } 2447 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2448 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2449 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2450 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2451 } else { 2452 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2453 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2454 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2455 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2456 } 2457 2458 return 0; 2459 2460 no_tx_mem: 2461 return -ENOMEM; 2462 } 2463 2464 static void mtk_tx_clean(struct mtk_eth *eth) 2465 { 2466 const struct mtk_soc_data *soc = eth->soc; 2467 struct mtk_tx_ring *ring = ð->tx_ring; 2468 int i; 2469 2470 if (ring->buf) { 2471 for (i = 0; i < ring->dma_size; i++) 2472 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2473 kfree(ring->buf); 2474 ring->buf = NULL; 2475 } 2476 2477 if (ring->dma) { 2478 dma_free_coherent(eth->dma_dev, 2479 ring->dma_size * soc->txrx.txd_size, 2480 ring->dma, ring->phys); 2481 ring->dma = NULL; 2482 } 2483 2484 if (ring->dma_pdma) { 2485 dma_free_coherent(eth->dma_dev, 2486 ring->dma_size * soc->txrx.txd_size, 2487 ring->dma_pdma, ring->phys_pdma); 2488 ring->dma_pdma = NULL; 2489 } 2490 } 2491 2492 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2493 { 2494 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2495 struct mtk_rx_ring *ring; 2496 int rx_data_len, rx_dma_size; 2497 int i; 2498 2499 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2500 if (ring_no) 2501 return -EINVAL; 2502 ring = ð->rx_ring_qdma; 2503 } else { 2504 ring = ð->rx_ring[ring_no]; 2505 } 2506 2507 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2508 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2509 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2510 } else { 2511 rx_data_len = ETH_DATA_LEN; 2512 rx_dma_size = MTK_DMA_SIZE; 2513 } 2514 2515 ring->frag_size = mtk_max_frag_size(rx_data_len); 2516 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2517 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2518 GFP_KERNEL); 2519 if (!ring->data) 2520 return -ENOMEM; 2521 2522 if (mtk_page_pool_enabled(eth)) { 2523 struct page_pool *pp; 2524 2525 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2526 rx_dma_size); 2527 if (IS_ERR(pp)) 2528 return PTR_ERR(pp); 2529 2530 ring->page_pool = pp; 2531 } 2532 2533 ring->dma = dma_alloc_coherent(eth->dma_dev, 2534 rx_dma_size * eth->soc->txrx.rxd_size, 2535 &ring->phys, GFP_KERNEL); 2536 if (!ring->dma) 2537 return -ENOMEM; 2538 2539 for (i = 0; i < rx_dma_size; i++) { 2540 struct mtk_rx_dma_v2 *rxd; 2541 dma_addr_t dma_addr; 2542 void *data; 2543 2544 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2545 if (ring->page_pool) { 2546 data = mtk_page_pool_get_buff(ring->page_pool, 2547 &dma_addr, GFP_KERNEL); 2548 if (!data) 2549 return -ENOMEM; 2550 } else { 2551 if (ring->frag_size <= PAGE_SIZE) 2552 data = netdev_alloc_frag(ring->frag_size); 2553 else 2554 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2555 2556 if (!data) 2557 return -ENOMEM; 2558 2559 dma_addr = dma_map_single(eth->dma_dev, 2560 data + NET_SKB_PAD + eth->ip_align, 2561 ring->buf_size, DMA_FROM_DEVICE); 2562 if (unlikely(dma_mapping_error(eth->dma_dev, 2563 dma_addr))) { 2564 skb_free_frag(data); 2565 return -ENOMEM; 2566 } 2567 } 2568 rxd->rxd1 = (unsigned int)dma_addr; 2569 ring->data[i] = data; 2570 2571 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2572 rxd->rxd2 = RX_DMA_LSO; 2573 else 2574 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2575 2576 rxd->rxd3 = 0; 2577 rxd->rxd4 = 0; 2578 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2579 rxd->rxd5 = 0; 2580 rxd->rxd6 = 0; 2581 rxd->rxd7 = 0; 2582 rxd->rxd8 = 0; 2583 } 2584 } 2585 2586 ring->dma_size = rx_dma_size; 2587 ring->calc_idx_update = false; 2588 ring->calc_idx = rx_dma_size - 1; 2589 if (rx_flag == MTK_RX_FLAGS_QDMA) 2590 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2591 ring_no * MTK_QRX_OFFSET; 2592 else 2593 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2594 ring_no * MTK_QRX_OFFSET; 2595 /* make sure that all changes to the dma ring are flushed before we 2596 * continue 2597 */ 2598 wmb(); 2599 2600 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2601 mtk_w32(eth, ring->phys, 2602 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2603 mtk_w32(eth, rx_dma_size, 2604 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2605 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2606 reg_map->qdma.rst_idx); 2607 } else { 2608 mtk_w32(eth, ring->phys, 2609 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2610 mtk_w32(eth, rx_dma_size, 2611 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2612 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2613 reg_map->pdma.rst_idx); 2614 } 2615 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2616 2617 return 0; 2618 } 2619 2620 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2621 { 2622 int i; 2623 2624 if (ring->data && ring->dma) { 2625 for (i = 0; i < ring->dma_size; i++) { 2626 struct mtk_rx_dma *rxd; 2627 2628 if (!ring->data[i]) 2629 continue; 2630 2631 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2632 if (!rxd->rxd1) 2633 continue; 2634 2635 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2636 ring->buf_size, DMA_FROM_DEVICE); 2637 mtk_rx_put_buff(ring, ring->data[i], false); 2638 } 2639 kfree(ring->data); 2640 ring->data = NULL; 2641 } 2642 2643 if (ring->dma) { 2644 dma_free_coherent(eth->dma_dev, 2645 ring->dma_size * eth->soc->txrx.rxd_size, 2646 ring->dma, ring->phys); 2647 ring->dma = NULL; 2648 } 2649 2650 if (ring->page_pool) { 2651 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2652 xdp_rxq_info_unreg(&ring->xdp_q); 2653 page_pool_destroy(ring->page_pool); 2654 ring->page_pool = NULL; 2655 } 2656 } 2657 2658 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2659 { 2660 int i; 2661 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2662 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2663 2664 /* set LRO rings to auto-learn modes */ 2665 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2666 2667 /* validate LRO ring */ 2668 ring_ctrl_dw2 |= MTK_RING_VLD; 2669 2670 /* set AGE timer (unit: 20us) */ 2671 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2672 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2673 2674 /* set max AGG timer (unit: 20us) */ 2675 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2676 2677 /* set max LRO AGG count */ 2678 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2679 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2680 2681 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2682 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2683 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2684 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2685 } 2686 2687 /* IPv4 checksum update enable */ 2688 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2689 2690 /* switch priority comparison to packet count mode */ 2691 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2692 2693 /* bandwidth threshold setting */ 2694 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2695 2696 /* auto-learn score delta setting */ 2697 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2698 2699 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2700 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2701 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2702 2703 /* set HW LRO mode & the max aggregation count for rx packets */ 2704 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2705 2706 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2707 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2708 2709 /* enable HW LRO */ 2710 lro_ctrl_dw0 |= MTK_LRO_EN; 2711 2712 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2713 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2714 2715 return 0; 2716 } 2717 2718 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2719 { 2720 int i; 2721 u32 val; 2722 2723 /* relinquish lro rings, flush aggregated packets */ 2724 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2725 2726 /* wait for relinquishments done */ 2727 for (i = 0; i < 10; i++) { 2728 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2729 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2730 msleep(20); 2731 continue; 2732 } 2733 break; 2734 } 2735 2736 /* invalidate lro rings */ 2737 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2738 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2739 2740 /* disable HW LRO */ 2741 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2742 } 2743 2744 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2745 { 2746 u32 reg_val; 2747 2748 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2749 2750 /* invalidate the IP setting */ 2751 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2752 2753 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2754 2755 /* validate the IP setting */ 2756 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2757 } 2758 2759 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2760 { 2761 u32 reg_val; 2762 2763 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2764 2765 /* invalidate the IP setting */ 2766 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2767 2768 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2769 } 2770 2771 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2772 { 2773 int cnt = 0; 2774 int i; 2775 2776 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2777 if (mac->hwlro_ip[i]) 2778 cnt++; 2779 } 2780 2781 return cnt; 2782 } 2783 2784 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2785 struct ethtool_rxnfc *cmd) 2786 { 2787 struct ethtool_rx_flow_spec *fsp = 2788 (struct ethtool_rx_flow_spec *)&cmd->fs; 2789 struct mtk_mac *mac = netdev_priv(dev); 2790 struct mtk_eth *eth = mac->hw; 2791 int hwlro_idx; 2792 2793 if ((fsp->flow_type != TCP_V4_FLOW) || 2794 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2795 (fsp->location > 1)) 2796 return -EINVAL; 2797 2798 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2799 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2800 2801 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2802 2803 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2804 2805 return 0; 2806 } 2807 2808 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2809 struct ethtool_rxnfc *cmd) 2810 { 2811 struct ethtool_rx_flow_spec *fsp = 2812 (struct ethtool_rx_flow_spec *)&cmd->fs; 2813 struct mtk_mac *mac = netdev_priv(dev); 2814 struct mtk_eth *eth = mac->hw; 2815 int hwlro_idx; 2816 2817 if (fsp->location > 1) 2818 return -EINVAL; 2819 2820 mac->hwlro_ip[fsp->location] = 0; 2821 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2822 2823 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2824 2825 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2826 2827 return 0; 2828 } 2829 2830 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2831 { 2832 struct mtk_mac *mac = netdev_priv(dev); 2833 struct mtk_eth *eth = mac->hw; 2834 int i, hwlro_idx; 2835 2836 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2837 mac->hwlro_ip[i] = 0; 2838 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2839 2840 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2841 } 2842 2843 mac->hwlro_ip_cnt = 0; 2844 } 2845 2846 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2847 struct ethtool_rxnfc *cmd) 2848 { 2849 struct mtk_mac *mac = netdev_priv(dev); 2850 struct ethtool_rx_flow_spec *fsp = 2851 (struct ethtool_rx_flow_spec *)&cmd->fs; 2852 2853 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2854 return -EINVAL; 2855 2856 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2857 fsp->flow_type = TCP_V4_FLOW; 2858 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2859 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2860 2861 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2862 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2863 fsp->h_u.tcp_ip4_spec.psrc = 0; 2864 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2865 fsp->h_u.tcp_ip4_spec.pdst = 0; 2866 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2867 fsp->h_u.tcp_ip4_spec.tos = 0; 2868 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2869 2870 return 0; 2871 } 2872 2873 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2874 struct ethtool_rxnfc *cmd, 2875 u32 *rule_locs) 2876 { 2877 struct mtk_mac *mac = netdev_priv(dev); 2878 int cnt = 0; 2879 int i; 2880 2881 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2882 if (mac->hwlro_ip[i]) { 2883 rule_locs[cnt] = i; 2884 cnt++; 2885 } 2886 } 2887 2888 cmd->rule_cnt = cnt; 2889 2890 return 0; 2891 } 2892 2893 static netdev_features_t mtk_fix_features(struct net_device *dev, 2894 netdev_features_t features) 2895 { 2896 if (!(features & NETIF_F_LRO)) { 2897 struct mtk_mac *mac = netdev_priv(dev); 2898 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2899 2900 if (ip_cnt) { 2901 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2902 2903 features |= NETIF_F_LRO; 2904 } 2905 } 2906 2907 return features; 2908 } 2909 2910 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2911 { 2912 struct mtk_mac *mac = netdev_priv(dev); 2913 struct mtk_eth *eth = mac->hw; 2914 netdev_features_t diff = dev->features ^ features; 2915 int i; 2916 2917 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2918 mtk_hwlro_netdev_disable(dev); 2919 2920 /* Set RX VLAN offloading */ 2921 if (!(diff & NETIF_F_HW_VLAN_CTAG_RX)) 2922 return 0; 2923 2924 mtk_w32(eth, !!(features & NETIF_F_HW_VLAN_CTAG_RX), 2925 MTK_CDMP_EG_CTRL); 2926 2927 /* sync features with other MAC */ 2928 for (i = 0; i < MTK_MAC_COUNT; i++) { 2929 if (!eth->netdev[i] || eth->netdev[i] == dev) 2930 continue; 2931 eth->netdev[i]->features &= ~NETIF_F_HW_VLAN_CTAG_RX; 2932 eth->netdev[i]->features |= features & NETIF_F_HW_VLAN_CTAG_RX; 2933 } 2934 2935 return 0; 2936 } 2937 2938 /* wait for DMA to finish whatever it is doing before we start using it again */ 2939 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2940 { 2941 unsigned int reg; 2942 int ret; 2943 u32 val; 2944 2945 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2946 reg = eth->soc->reg_map->qdma.glo_cfg; 2947 else 2948 reg = eth->soc->reg_map->pdma.glo_cfg; 2949 2950 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2951 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2952 5, MTK_DMA_BUSY_TIMEOUT_US); 2953 if (ret) 2954 dev_err(eth->dev, "DMA init timeout\n"); 2955 2956 return ret; 2957 } 2958 2959 static int mtk_dma_init(struct mtk_eth *eth) 2960 { 2961 int err; 2962 u32 i; 2963 2964 if (mtk_dma_busy_wait(eth)) 2965 return -EBUSY; 2966 2967 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2968 /* QDMA needs scratch memory for internal reordering of the 2969 * descriptors 2970 */ 2971 err = mtk_init_fq_dma(eth); 2972 if (err) 2973 return err; 2974 } 2975 2976 err = mtk_tx_alloc(eth); 2977 if (err) 2978 return err; 2979 2980 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2981 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2982 if (err) 2983 return err; 2984 } 2985 2986 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2987 if (err) 2988 return err; 2989 2990 if (eth->hwlro) { 2991 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2992 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2993 if (err) 2994 return err; 2995 } 2996 err = mtk_hwlro_rx_init(eth); 2997 if (err) 2998 return err; 2999 } 3000 3001 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3002 /* Enable random early drop and set drop threshold 3003 * automatically 3004 */ 3005 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3006 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3007 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3008 } 3009 3010 return 0; 3011 } 3012 3013 static void mtk_dma_free(struct mtk_eth *eth) 3014 { 3015 const struct mtk_soc_data *soc = eth->soc; 3016 int i; 3017 3018 for (i = 0; i < MTK_MAC_COUNT; i++) 3019 if (eth->netdev[i]) 3020 netdev_reset_queue(eth->netdev[i]); 3021 if (eth->scratch_ring) { 3022 dma_free_coherent(eth->dma_dev, 3023 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3024 eth->scratch_ring, eth->phy_scratch_ring); 3025 eth->scratch_ring = NULL; 3026 eth->phy_scratch_ring = 0; 3027 } 3028 mtk_tx_clean(eth); 3029 mtk_rx_clean(eth, ð->rx_ring[0]); 3030 mtk_rx_clean(eth, ð->rx_ring_qdma); 3031 3032 if (eth->hwlro) { 3033 mtk_hwlro_rx_uninit(eth); 3034 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3035 mtk_rx_clean(eth, ð->rx_ring[i]); 3036 } 3037 3038 kfree(eth->scratch_head); 3039 } 3040 3041 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3042 { 3043 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3044 3045 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3046 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3047 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3048 } 3049 3050 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3051 { 3052 struct mtk_mac *mac = netdev_priv(dev); 3053 struct mtk_eth *eth = mac->hw; 3054 3055 if (test_bit(MTK_RESETTING, ð->state)) 3056 return; 3057 3058 if (!mtk_hw_reset_check(eth)) 3059 return; 3060 3061 eth->netdev[mac->id]->stats.tx_errors++; 3062 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3063 3064 schedule_work(ð->pending_work); 3065 } 3066 3067 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3068 { 3069 struct mtk_eth *eth = _eth; 3070 3071 eth->rx_events++; 3072 if (likely(napi_schedule_prep(ð->rx_napi))) { 3073 __napi_schedule(ð->rx_napi); 3074 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3075 } 3076 3077 return IRQ_HANDLED; 3078 } 3079 3080 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3081 { 3082 struct mtk_eth *eth = _eth; 3083 3084 eth->tx_events++; 3085 if (likely(napi_schedule_prep(ð->tx_napi))) { 3086 __napi_schedule(ð->tx_napi); 3087 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3088 } 3089 3090 return IRQ_HANDLED; 3091 } 3092 3093 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3094 { 3095 struct mtk_eth *eth = _eth; 3096 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3097 3098 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3099 eth->soc->txrx.rx_irq_done_mask) { 3100 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3101 eth->soc->txrx.rx_irq_done_mask) 3102 mtk_handle_irq_rx(irq, _eth); 3103 } 3104 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3105 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3106 mtk_handle_irq_tx(irq, _eth); 3107 } 3108 3109 return IRQ_HANDLED; 3110 } 3111 3112 #ifdef CONFIG_NET_POLL_CONTROLLER 3113 static void mtk_poll_controller(struct net_device *dev) 3114 { 3115 struct mtk_mac *mac = netdev_priv(dev); 3116 struct mtk_eth *eth = mac->hw; 3117 3118 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3119 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3120 mtk_handle_irq_rx(eth->irq[2], dev); 3121 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3122 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3123 } 3124 #endif 3125 3126 static int mtk_start_dma(struct mtk_eth *eth) 3127 { 3128 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3129 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3130 int err; 3131 3132 err = mtk_dma_init(eth); 3133 if (err) { 3134 mtk_dma_free(eth); 3135 return err; 3136 } 3137 3138 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3139 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3140 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3141 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3142 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3143 3144 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3145 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3146 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3147 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3148 else 3149 val |= MTK_RX_BT_32DWORDS; 3150 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3151 3152 mtk_w32(eth, 3153 MTK_RX_DMA_EN | rx_2b_offset | 3154 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3155 reg_map->pdma.glo_cfg); 3156 } else { 3157 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3158 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3159 reg_map->pdma.glo_cfg); 3160 } 3161 3162 return 0; 3163 } 3164 3165 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3166 { 3167 int i; 3168 3169 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3170 return; 3171 3172 for (i = 0; i < MTK_MAC_COUNT; i++) { 3173 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3174 3175 /* default setup the forward port to send frame to PDMA */ 3176 val &= ~0xffff; 3177 3178 /* Enable RX checksum */ 3179 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3180 3181 val |= config; 3182 3183 if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) 3184 val |= MTK_GDMA_SPECIAL_TAG; 3185 3186 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3187 } 3188 /* Reset and enable PSE */ 3189 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3190 mtk_w32(eth, 0, MTK_RST_GL); 3191 } 3192 3193 3194 static bool mtk_uses_dsa(struct net_device *dev) 3195 { 3196 #if IS_ENABLED(CONFIG_NET_DSA) 3197 return netdev_uses_dsa(dev) && 3198 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3199 #else 3200 return false; 3201 #endif 3202 } 3203 3204 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3205 { 3206 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3207 struct mtk_eth *eth = mac->hw; 3208 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3209 struct ethtool_link_ksettings s; 3210 struct net_device *ldev; 3211 struct list_head *iter; 3212 struct dsa_port *dp; 3213 3214 if (event != NETDEV_CHANGE) 3215 return NOTIFY_DONE; 3216 3217 netdev_for_each_lower_dev(dev, ldev, iter) { 3218 if (netdev_priv(ldev) == mac) 3219 goto found; 3220 } 3221 3222 return NOTIFY_DONE; 3223 3224 found: 3225 if (!dsa_slave_dev_check(dev)) 3226 return NOTIFY_DONE; 3227 3228 if (__ethtool_get_link_ksettings(dev, &s)) 3229 return NOTIFY_DONE; 3230 3231 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3232 return NOTIFY_DONE; 3233 3234 dp = dsa_port_from_netdev(dev); 3235 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3236 return NOTIFY_DONE; 3237 3238 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3239 3240 return NOTIFY_DONE; 3241 } 3242 3243 static int mtk_open(struct net_device *dev) 3244 { 3245 struct mtk_mac *mac = netdev_priv(dev); 3246 struct mtk_eth *eth = mac->hw; 3247 int i, err; 3248 3249 if (mtk_uses_dsa(dev) && !eth->prog) { 3250 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3251 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3252 3253 if (md_dst) 3254 continue; 3255 3256 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3257 GFP_KERNEL); 3258 if (!md_dst) 3259 return -ENOMEM; 3260 3261 md_dst->u.port_info.port_id = i; 3262 eth->dsa_meta[i] = md_dst; 3263 } 3264 } else { 3265 /* Hardware special tag parsing needs to be disabled if at least 3266 * one MAC does not use DSA. 3267 */ 3268 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3269 val &= ~MTK_CDMP_STAG_EN; 3270 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3271 } 3272 3273 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3274 if (err) { 3275 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3276 err); 3277 return err; 3278 } 3279 3280 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3281 if (!refcount_read(ð->dma_refcnt)) { 3282 const struct mtk_soc_data *soc = eth->soc; 3283 u32 gdm_config; 3284 int i; 3285 3286 err = mtk_start_dma(eth); 3287 if (err) { 3288 phylink_disconnect_phy(mac->phylink); 3289 return err; 3290 } 3291 3292 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3293 mtk_ppe_start(eth->ppe[i]); 3294 3295 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3296 : MTK_GDMA_TO_PDMA; 3297 mtk_gdm_config(eth, gdm_config); 3298 3299 napi_enable(ð->tx_napi); 3300 napi_enable(ð->rx_napi); 3301 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3302 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3303 refcount_set(ð->dma_refcnt, 1); 3304 } 3305 else 3306 refcount_inc(ð->dma_refcnt); 3307 3308 phylink_start(mac->phylink); 3309 netif_tx_start_all_queues(dev); 3310 3311 return 0; 3312 } 3313 3314 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3315 { 3316 u32 val; 3317 int i; 3318 3319 /* stop the dma engine */ 3320 spin_lock_bh(ð->page_lock); 3321 val = mtk_r32(eth, glo_cfg); 3322 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3323 glo_cfg); 3324 spin_unlock_bh(ð->page_lock); 3325 3326 /* wait for dma stop */ 3327 for (i = 0; i < 10; i++) { 3328 val = mtk_r32(eth, glo_cfg); 3329 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3330 msleep(20); 3331 continue; 3332 } 3333 break; 3334 } 3335 } 3336 3337 static int mtk_stop(struct net_device *dev) 3338 { 3339 struct mtk_mac *mac = netdev_priv(dev); 3340 struct mtk_eth *eth = mac->hw; 3341 int i; 3342 3343 phylink_stop(mac->phylink); 3344 3345 netif_tx_disable(dev); 3346 3347 phylink_disconnect_phy(mac->phylink); 3348 3349 /* only shutdown DMA if this is the last user */ 3350 if (!refcount_dec_and_test(ð->dma_refcnt)) 3351 return 0; 3352 3353 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3354 3355 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3356 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3357 napi_disable(ð->tx_napi); 3358 napi_disable(ð->rx_napi); 3359 3360 cancel_work_sync(ð->rx_dim.work); 3361 cancel_work_sync(ð->tx_dim.work); 3362 3363 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3364 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3365 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3366 3367 mtk_dma_free(eth); 3368 3369 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3370 mtk_ppe_stop(eth->ppe[i]); 3371 3372 return 0; 3373 } 3374 3375 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3376 struct netlink_ext_ack *extack) 3377 { 3378 struct mtk_mac *mac = netdev_priv(dev); 3379 struct mtk_eth *eth = mac->hw; 3380 struct bpf_prog *old_prog; 3381 bool need_update; 3382 3383 if (eth->hwlro) { 3384 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3385 return -EOPNOTSUPP; 3386 } 3387 3388 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3389 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3390 return -EOPNOTSUPP; 3391 } 3392 3393 need_update = !!eth->prog != !!prog; 3394 if (netif_running(dev) && need_update) 3395 mtk_stop(dev); 3396 3397 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3398 if (old_prog) 3399 bpf_prog_put(old_prog); 3400 3401 if (netif_running(dev) && need_update) 3402 return mtk_open(dev); 3403 3404 return 0; 3405 } 3406 3407 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3408 { 3409 switch (xdp->command) { 3410 case XDP_SETUP_PROG: 3411 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3412 default: 3413 return -EINVAL; 3414 } 3415 } 3416 3417 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3418 { 3419 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3420 reset_bits, 3421 reset_bits); 3422 3423 usleep_range(1000, 1100); 3424 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3425 reset_bits, 3426 ~reset_bits); 3427 mdelay(10); 3428 } 3429 3430 static void mtk_clk_disable(struct mtk_eth *eth) 3431 { 3432 int clk; 3433 3434 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3435 clk_disable_unprepare(eth->clks[clk]); 3436 } 3437 3438 static int mtk_clk_enable(struct mtk_eth *eth) 3439 { 3440 int clk, ret; 3441 3442 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3443 ret = clk_prepare_enable(eth->clks[clk]); 3444 if (ret) 3445 goto err_disable_clks; 3446 } 3447 3448 return 0; 3449 3450 err_disable_clks: 3451 while (--clk >= 0) 3452 clk_disable_unprepare(eth->clks[clk]); 3453 3454 return ret; 3455 } 3456 3457 static void mtk_dim_rx(struct work_struct *work) 3458 { 3459 struct dim *dim = container_of(work, struct dim, work); 3460 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3461 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3462 struct dim_cq_moder cur_profile; 3463 u32 val, cur; 3464 3465 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3466 dim->profile_ix); 3467 spin_lock_bh(ð->dim_lock); 3468 3469 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3470 val &= MTK_PDMA_DELAY_TX_MASK; 3471 val |= MTK_PDMA_DELAY_RX_EN; 3472 3473 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3474 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3475 3476 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3477 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3478 3479 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3480 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3481 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3482 3483 spin_unlock_bh(ð->dim_lock); 3484 3485 dim->state = DIM_START_MEASURE; 3486 } 3487 3488 static void mtk_dim_tx(struct work_struct *work) 3489 { 3490 struct dim *dim = container_of(work, struct dim, work); 3491 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3492 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3493 struct dim_cq_moder cur_profile; 3494 u32 val, cur; 3495 3496 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3497 dim->profile_ix); 3498 spin_lock_bh(ð->dim_lock); 3499 3500 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3501 val &= MTK_PDMA_DELAY_RX_MASK; 3502 val |= MTK_PDMA_DELAY_TX_EN; 3503 3504 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3505 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3506 3507 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3508 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3509 3510 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3511 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3512 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3513 3514 spin_unlock_bh(ð->dim_lock); 3515 3516 dim->state = DIM_START_MEASURE; 3517 } 3518 3519 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3520 { 3521 struct mtk_eth *eth = mac->hw; 3522 u32 mcr_cur, mcr_new; 3523 3524 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3525 return; 3526 3527 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3528 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3529 3530 if (val <= 1518) 3531 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3532 else if (val <= 1536) 3533 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3534 else if (val <= 1552) 3535 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3536 else 3537 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3538 3539 if (mcr_new != mcr_cur) 3540 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3541 } 3542 3543 static void mtk_hw_reset(struct mtk_eth *eth) 3544 { 3545 u32 val; 3546 3547 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3548 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3549 val = RSTCTRL_PPE0_V2; 3550 } else { 3551 val = RSTCTRL_PPE0; 3552 } 3553 3554 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3555 val |= RSTCTRL_PPE1; 3556 3557 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3558 3559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3560 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3561 0x3ffffff); 3562 } 3563 3564 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3565 { 3566 u32 val; 3567 3568 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3569 return val; 3570 } 3571 3572 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3573 { 3574 u32 rst_mask, val; 3575 3576 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3577 RSTCTRL_FE); 3578 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3579 val & RSTCTRL_FE, 1, 1000)) { 3580 dev_err(eth->dev, "warm reset failed\n"); 3581 mtk_hw_reset(eth); 3582 return; 3583 } 3584 3585 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3586 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3587 else 3588 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3589 3590 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3591 rst_mask |= RSTCTRL_PPE1; 3592 3593 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3594 3595 udelay(1); 3596 val = mtk_hw_reset_read(eth); 3597 if (!(val & rst_mask)) 3598 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3599 val, rst_mask); 3600 3601 rst_mask |= RSTCTRL_FE; 3602 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3603 3604 udelay(1); 3605 val = mtk_hw_reset_read(eth); 3606 if (val & rst_mask) 3607 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3608 val, rst_mask); 3609 } 3610 3611 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3612 { 3613 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3614 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3615 bool oq_hang, cdm1_busy, adma_busy; 3616 bool wtx_busy, cdm_full, oq_free; 3617 u32 wdidx, val, gdm1_fc, gdm2_fc; 3618 bool qfsm_hang, qfwd_hang; 3619 bool ret = false; 3620 3621 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3622 return false; 3623 3624 /* WDMA sanity checks */ 3625 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3626 3627 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3628 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3629 3630 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3631 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3632 3633 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3634 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3635 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3636 3637 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3638 if (++eth->reset.wdma_hang_count > 2) { 3639 eth->reset.wdma_hang_count = 0; 3640 ret = true; 3641 } 3642 goto out; 3643 } 3644 3645 /* QDMA sanity checks */ 3646 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3647 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3648 3649 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3650 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3651 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3652 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3653 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3654 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3655 3656 if (qfsm_hang && qfwd_hang && 3657 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3658 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3659 if (++eth->reset.qdma_hang_count > 2) { 3660 eth->reset.qdma_hang_count = 0; 3661 ret = true; 3662 } 3663 goto out; 3664 } 3665 3666 /* ADMA sanity checks */ 3667 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3668 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3669 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3670 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3671 3672 if (oq_hang && cdm1_busy && adma_busy) { 3673 if (++eth->reset.adma_hang_count > 2) { 3674 eth->reset.adma_hang_count = 0; 3675 ret = true; 3676 } 3677 goto out; 3678 } 3679 3680 eth->reset.wdma_hang_count = 0; 3681 eth->reset.qdma_hang_count = 0; 3682 eth->reset.adma_hang_count = 0; 3683 out: 3684 eth->reset.wdidx = wdidx; 3685 3686 return ret; 3687 } 3688 3689 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3690 { 3691 struct delayed_work *del_work = to_delayed_work(work); 3692 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3693 reset.monitor_work); 3694 3695 if (test_bit(MTK_RESETTING, ð->state)) 3696 goto out; 3697 3698 /* DMA stuck checks */ 3699 if (mtk_hw_check_dma_hang(eth)) 3700 schedule_work(ð->pending_work); 3701 3702 out: 3703 schedule_delayed_work(ð->reset.monitor_work, 3704 MTK_DMA_MONITOR_TIMEOUT); 3705 } 3706 3707 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3708 { 3709 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3710 ETHSYS_DMA_AG_MAP_PPE; 3711 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3712 int i, val, ret; 3713 3714 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3715 return 0; 3716 3717 if (!reset) { 3718 pm_runtime_enable(eth->dev); 3719 pm_runtime_get_sync(eth->dev); 3720 3721 ret = mtk_clk_enable(eth); 3722 if (ret) 3723 goto err_disable_pm; 3724 } 3725 3726 if (eth->ethsys) 3727 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3728 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3729 3730 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3731 ret = device_reset(eth->dev); 3732 if (ret) { 3733 dev_err(eth->dev, "MAC reset failed!\n"); 3734 goto err_disable_pm; 3735 } 3736 3737 /* set interrupt delays based on current Net DIM sample */ 3738 mtk_dim_rx(ð->rx_dim.work); 3739 mtk_dim_tx(ð->tx_dim.work); 3740 3741 /* disable delay and normal interrupt */ 3742 mtk_tx_irq_disable(eth, ~0); 3743 mtk_rx_irq_disable(eth, ~0); 3744 3745 return 0; 3746 } 3747 3748 msleep(100); 3749 3750 if (reset) 3751 mtk_hw_warm_reset(eth); 3752 else 3753 mtk_hw_reset(eth); 3754 3755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3756 /* Set FE to PDMAv2 if necessary */ 3757 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3758 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3759 } 3760 3761 if (eth->pctl) { 3762 /* Set GE2 driving and slew rate */ 3763 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3764 3765 /* set GE2 TDSEL */ 3766 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3767 3768 /* set GE2 TUNE */ 3769 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3770 } 3771 3772 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3773 * up with the more appropriate value when mtk_mac_config call is being 3774 * invoked. 3775 */ 3776 for (i = 0; i < MTK_MAC_COUNT; i++) { 3777 struct net_device *dev = eth->netdev[i]; 3778 3779 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3780 if (dev) { 3781 struct mtk_mac *mac = netdev_priv(dev); 3782 3783 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3784 } 3785 } 3786 3787 /* Indicates CDM to parse the MTK special tag from CPU 3788 * which also is working out for untag packets. 3789 */ 3790 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3791 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3792 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3793 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3794 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3795 } 3796 3797 /* Enable RX VLan Offloading */ 3798 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3799 3800 /* set interrupt delays based on current Net DIM sample */ 3801 mtk_dim_rx(ð->rx_dim.work); 3802 mtk_dim_tx(ð->tx_dim.work); 3803 3804 /* disable delay and normal interrupt */ 3805 mtk_tx_irq_disable(eth, ~0); 3806 mtk_rx_irq_disable(eth, ~0); 3807 3808 /* FE int grouping */ 3809 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3810 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3811 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3812 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3813 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3814 3815 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3816 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3817 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3818 3819 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3820 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3821 3822 /* PSE Free Queue Flow Control */ 3823 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3824 3825 /* PSE config input queue threshold */ 3826 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3827 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3828 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3829 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3830 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3831 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3832 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3833 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3834 3835 /* PSE config output queue threshold */ 3836 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3837 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3838 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3839 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3840 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3841 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3842 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3843 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3844 3845 /* GDM and CDM Threshold */ 3846 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3847 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3848 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3849 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3850 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3851 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3852 } 3853 3854 return 0; 3855 3856 err_disable_pm: 3857 if (!reset) { 3858 pm_runtime_put_sync(eth->dev); 3859 pm_runtime_disable(eth->dev); 3860 } 3861 3862 return ret; 3863 } 3864 3865 static int mtk_hw_deinit(struct mtk_eth *eth) 3866 { 3867 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3868 return 0; 3869 3870 mtk_clk_disable(eth); 3871 3872 pm_runtime_put_sync(eth->dev); 3873 pm_runtime_disable(eth->dev); 3874 3875 return 0; 3876 } 3877 3878 static int __init mtk_init(struct net_device *dev) 3879 { 3880 struct mtk_mac *mac = netdev_priv(dev); 3881 struct mtk_eth *eth = mac->hw; 3882 int ret; 3883 3884 ret = of_get_ethdev_address(mac->of_node, dev); 3885 if (ret) { 3886 /* If the mac address is invalid, use random mac address */ 3887 eth_hw_addr_random(dev); 3888 dev_err(eth->dev, "generated random MAC address %pM\n", 3889 dev->dev_addr); 3890 } 3891 3892 return 0; 3893 } 3894 3895 static void mtk_uninit(struct net_device *dev) 3896 { 3897 struct mtk_mac *mac = netdev_priv(dev); 3898 struct mtk_eth *eth = mac->hw; 3899 3900 phylink_disconnect_phy(mac->phylink); 3901 mtk_tx_irq_disable(eth, ~0); 3902 mtk_rx_irq_disable(eth, ~0); 3903 } 3904 3905 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3906 { 3907 int length = new_mtu + MTK_RX_ETH_HLEN; 3908 struct mtk_mac *mac = netdev_priv(dev); 3909 struct mtk_eth *eth = mac->hw; 3910 3911 if (rcu_access_pointer(eth->prog) && 3912 length > MTK_PP_MAX_BUF_SIZE) { 3913 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3914 return -EINVAL; 3915 } 3916 3917 mtk_set_mcr_max_rx(mac, length); 3918 dev->mtu = new_mtu; 3919 3920 return 0; 3921 } 3922 3923 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3924 { 3925 struct mtk_mac *mac = netdev_priv(dev); 3926 3927 switch (cmd) { 3928 case SIOCGMIIPHY: 3929 case SIOCGMIIREG: 3930 case SIOCSMIIREG: 3931 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3932 default: 3933 break; 3934 } 3935 3936 return -EOPNOTSUPP; 3937 } 3938 3939 static void mtk_prepare_for_reset(struct mtk_eth *eth) 3940 { 3941 u32 val; 3942 int i; 3943 3944 /* disabe FE P3 and P4 */ 3945 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; 3946 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3947 val |= MTK_FE_LINK_DOWN_P4; 3948 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3949 3950 /* adjust PPE configurations to prepare for reset */ 3951 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3952 mtk_ppe_prepare_reset(eth->ppe[i]); 3953 3954 /* disable NETSYS interrupts */ 3955 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 3956 3957 /* force link down GMAC */ 3958 for (i = 0; i < 2; i++) { 3959 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 3960 mtk_w32(eth, val, MTK_MAC_MCR(i)); 3961 } 3962 } 3963 3964 static void mtk_pending_work(struct work_struct *work) 3965 { 3966 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3967 unsigned long restart = 0; 3968 u32 val; 3969 int i; 3970 3971 rtnl_lock(); 3972 set_bit(MTK_RESETTING, ð->state); 3973 3974 mtk_prepare_for_reset(eth); 3975 mtk_wed_fe_reset(); 3976 /* Run again reset preliminary configuration in order to avoid any 3977 * possible race during FE reset since it can run releasing RTNL lock. 3978 */ 3979 mtk_prepare_for_reset(eth); 3980 3981 /* stop all devices to make sure that dma is properly shut down */ 3982 for (i = 0; i < MTK_MAC_COUNT; i++) { 3983 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 3984 continue; 3985 3986 mtk_stop(eth->netdev[i]); 3987 __set_bit(i, &restart); 3988 } 3989 3990 usleep_range(15000, 16000); 3991 3992 if (eth->dev->pins) 3993 pinctrl_select_state(eth->dev->pins->p, 3994 eth->dev->pins->default_state); 3995 mtk_hw_init(eth, true); 3996 3997 /* restart DMA and enable IRQs */ 3998 for (i = 0; i < MTK_MAC_COUNT; i++) { 3999 if (!test_bit(i, &restart)) 4000 continue; 4001 4002 if (mtk_open(eth->netdev[i])) { 4003 netif_alert(eth, ifup, eth->netdev[i], 4004 "Driver up/down cycle failed\n"); 4005 dev_close(eth->netdev[i]); 4006 } 4007 } 4008 4009 /* enabe FE P3 and P4 */ 4010 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; 4011 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4012 val &= ~MTK_FE_LINK_DOWN_P4; 4013 mtk_w32(eth, val, MTK_FE_GLO_CFG); 4014 4015 clear_bit(MTK_RESETTING, ð->state); 4016 4017 mtk_wed_fe_reset_complete(); 4018 4019 rtnl_unlock(); 4020 } 4021 4022 static int mtk_free_dev(struct mtk_eth *eth) 4023 { 4024 int i; 4025 4026 for (i = 0; i < MTK_MAC_COUNT; i++) { 4027 if (!eth->netdev[i]) 4028 continue; 4029 free_netdev(eth->netdev[i]); 4030 } 4031 4032 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4033 if (!eth->dsa_meta[i]) 4034 break; 4035 metadata_dst_free(eth->dsa_meta[i]); 4036 } 4037 4038 return 0; 4039 } 4040 4041 static int mtk_unreg_dev(struct mtk_eth *eth) 4042 { 4043 int i; 4044 4045 for (i = 0; i < MTK_MAC_COUNT; i++) { 4046 struct mtk_mac *mac; 4047 if (!eth->netdev[i]) 4048 continue; 4049 mac = netdev_priv(eth->netdev[i]); 4050 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4051 unregister_netdevice_notifier(&mac->device_notifier); 4052 unregister_netdev(eth->netdev[i]); 4053 } 4054 4055 return 0; 4056 } 4057 4058 static int mtk_cleanup(struct mtk_eth *eth) 4059 { 4060 mtk_unreg_dev(eth); 4061 mtk_free_dev(eth); 4062 cancel_work_sync(ð->pending_work); 4063 cancel_delayed_work_sync(ð->reset.monitor_work); 4064 4065 return 0; 4066 } 4067 4068 static int mtk_get_link_ksettings(struct net_device *ndev, 4069 struct ethtool_link_ksettings *cmd) 4070 { 4071 struct mtk_mac *mac = netdev_priv(ndev); 4072 4073 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4074 return -EBUSY; 4075 4076 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4077 } 4078 4079 static int mtk_set_link_ksettings(struct net_device *ndev, 4080 const struct ethtool_link_ksettings *cmd) 4081 { 4082 struct mtk_mac *mac = netdev_priv(ndev); 4083 4084 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4085 return -EBUSY; 4086 4087 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4088 } 4089 4090 static void mtk_get_drvinfo(struct net_device *dev, 4091 struct ethtool_drvinfo *info) 4092 { 4093 struct mtk_mac *mac = netdev_priv(dev); 4094 4095 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4096 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4097 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4098 } 4099 4100 static u32 mtk_get_msglevel(struct net_device *dev) 4101 { 4102 struct mtk_mac *mac = netdev_priv(dev); 4103 4104 return mac->hw->msg_enable; 4105 } 4106 4107 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4108 { 4109 struct mtk_mac *mac = netdev_priv(dev); 4110 4111 mac->hw->msg_enable = value; 4112 } 4113 4114 static int mtk_nway_reset(struct net_device *dev) 4115 { 4116 struct mtk_mac *mac = netdev_priv(dev); 4117 4118 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4119 return -EBUSY; 4120 4121 if (!mac->phylink) 4122 return -ENOTSUPP; 4123 4124 return phylink_ethtool_nway_reset(mac->phylink); 4125 } 4126 4127 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4128 { 4129 int i; 4130 4131 switch (stringset) { 4132 case ETH_SS_STATS: { 4133 struct mtk_mac *mac = netdev_priv(dev); 4134 4135 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4136 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4137 data += ETH_GSTRING_LEN; 4138 } 4139 if (mtk_page_pool_enabled(mac->hw)) 4140 page_pool_ethtool_stats_get_strings(data); 4141 break; 4142 } 4143 default: 4144 break; 4145 } 4146 } 4147 4148 static int mtk_get_sset_count(struct net_device *dev, int sset) 4149 { 4150 switch (sset) { 4151 case ETH_SS_STATS: { 4152 int count = ARRAY_SIZE(mtk_ethtool_stats); 4153 struct mtk_mac *mac = netdev_priv(dev); 4154 4155 if (mtk_page_pool_enabled(mac->hw)) 4156 count += page_pool_ethtool_stats_get_count(); 4157 return count; 4158 } 4159 default: 4160 return -EOPNOTSUPP; 4161 } 4162 } 4163 4164 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4165 { 4166 struct page_pool_stats stats = {}; 4167 int i; 4168 4169 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4170 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4171 4172 if (!ring->page_pool) 4173 continue; 4174 4175 page_pool_get_stats(ring->page_pool, &stats); 4176 } 4177 page_pool_ethtool_stats_get(data, &stats); 4178 } 4179 4180 static void mtk_get_ethtool_stats(struct net_device *dev, 4181 struct ethtool_stats *stats, u64 *data) 4182 { 4183 struct mtk_mac *mac = netdev_priv(dev); 4184 struct mtk_hw_stats *hwstats = mac->hw_stats; 4185 u64 *data_src, *data_dst; 4186 unsigned int start; 4187 int i; 4188 4189 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4190 return; 4191 4192 if (netif_running(dev) && netif_device_present(dev)) { 4193 if (spin_trylock_bh(&hwstats->stats_lock)) { 4194 mtk_stats_update_mac(mac); 4195 spin_unlock_bh(&hwstats->stats_lock); 4196 } 4197 } 4198 4199 data_src = (u64 *)hwstats; 4200 4201 do { 4202 data_dst = data; 4203 start = u64_stats_fetch_begin(&hwstats->syncp); 4204 4205 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4206 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4207 if (mtk_page_pool_enabled(mac->hw)) 4208 mtk_ethtool_pp_stats(mac->hw, data_dst); 4209 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4210 } 4211 4212 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4213 u32 *rule_locs) 4214 { 4215 int ret = -EOPNOTSUPP; 4216 4217 switch (cmd->cmd) { 4218 case ETHTOOL_GRXRINGS: 4219 if (dev->hw_features & NETIF_F_LRO) { 4220 cmd->data = MTK_MAX_RX_RING_NUM; 4221 ret = 0; 4222 } 4223 break; 4224 case ETHTOOL_GRXCLSRLCNT: 4225 if (dev->hw_features & NETIF_F_LRO) { 4226 struct mtk_mac *mac = netdev_priv(dev); 4227 4228 cmd->rule_cnt = mac->hwlro_ip_cnt; 4229 ret = 0; 4230 } 4231 break; 4232 case ETHTOOL_GRXCLSRULE: 4233 if (dev->hw_features & NETIF_F_LRO) 4234 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4235 break; 4236 case ETHTOOL_GRXCLSRLALL: 4237 if (dev->hw_features & NETIF_F_LRO) 4238 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4239 rule_locs); 4240 break; 4241 default: 4242 break; 4243 } 4244 4245 return ret; 4246 } 4247 4248 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4249 { 4250 int ret = -EOPNOTSUPP; 4251 4252 switch (cmd->cmd) { 4253 case ETHTOOL_SRXCLSRLINS: 4254 if (dev->hw_features & NETIF_F_LRO) 4255 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4256 break; 4257 case ETHTOOL_SRXCLSRLDEL: 4258 if (dev->hw_features & NETIF_F_LRO) 4259 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4260 break; 4261 default: 4262 break; 4263 } 4264 4265 return ret; 4266 } 4267 4268 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4269 struct net_device *sb_dev) 4270 { 4271 struct mtk_mac *mac = netdev_priv(dev); 4272 unsigned int queue = 0; 4273 4274 if (netdev_uses_dsa(dev)) 4275 queue = skb_get_queue_mapping(skb) + 3; 4276 else 4277 queue = mac->id; 4278 4279 if (queue >= dev->num_tx_queues) 4280 queue = 0; 4281 4282 return queue; 4283 } 4284 4285 static const struct ethtool_ops mtk_ethtool_ops = { 4286 .get_link_ksettings = mtk_get_link_ksettings, 4287 .set_link_ksettings = mtk_set_link_ksettings, 4288 .get_drvinfo = mtk_get_drvinfo, 4289 .get_msglevel = mtk_get_msglevel, 4290 .set_msglevel = mtk_set_msglevel, 4291 .nway_reset = mtk_nway_reset, 4292 .get_link = ethtool_op_get_link, 4293 .get_strings = mtk_get_strings, 4294 .get_sset_count = mtk_get_sset_count, 4295 .get_ethtool_stats = mtk_get_ethtool_stats, 4296 .get_rxnfc = mtk_get_rxnfc, 4297 .set_rxnfc = mtk_set_rxnfc, 4298 }; 4299 4300 static const struct net_device_ops mtk_netdev_ops = { 4301 .ndo_init = mtk_init, 4302 .ndo_uninit = mtk_uninit, 4303 .ndo_open = mtk_open, 4304 .ndo_stop = mtk_stop, 4305 .ndo_start_xmit = mtk_start_xmit, 4306 .ndo_set_mac_address = mtk_set_mac_address, 4307 .ndo_validate_addr = eth_validate_addr, 4308 .ndo_eth_ioctl = mtk_do_ioctl, 4309 .ndo_change_mtu = mtk_change_mtu, 4310 .ndo_tx_timeout = mtk_tx_timeout, 4311 .ndo_get_stats64 = mtk_get_stats64, 4312 .ndo_fix_features = mtk_fix_features, 4313 .ndo_set_features = mtk_set_features, 4314 #ifdef CONFIG_NET_POLL_CONTROLLER 4315 .ndo_poll_controller = mtk_poll_controller, 4316 #endif 4317 .ndo_setup_tc = mtk_eth_setup_tc, 4318 .ndo_bpf = mtk_xdp, 4319 .ndo_xdp_xmit = mtk_xdp_xmit, 4320 .ndo_select_queue = mtk_select_queue, 4321 }; 4322 4323 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4324 { 4325 const __be32 *_id = of_get_property(np, "reg", NULL); 4326 phy_interface_t phy_mode; 4327 struct phylink *phylink; 4328 struct mtk_mac *mac; 4329 int id, err; 4330 int txqs = 1; 4331 4332 if (!_id) { 4333 dev_err(eth->dev, "missing mac id\n"); 4334 return -EINVAL; 4335 } 4336 4337 id = be32_to_cpup(_id); 4338 if (id >= MTK_MAC_COUNT) { 4339 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4340 return -EINVAL; 4341 } 4342 4343 if (eth->netdev[id]) { 4344 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4345 return -EINVAL; 4346 } 4347 4348 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4349 txqs = MTK_QDMA_NUM_QUEUES; 4350 4351 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4352 if (!eth->netdev[id]) { 4353 dev_err(eth->dev, "alloc_etherdev failed\n"); 4354 return -ENOMEM; 4355 } 4356 mac = netdev_priv(eth->netdev[id]); 4357 eth->mac[id] = mac; 4358 mac->id = id; 4359 mac->hw = eth; 4360 mac->of_node = np; 4361 4362 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4363 mac->hwlro_ip_cnt = 0; 4364 4365 mac->hw_stats = devm_kzalloc(eth->dev, 4366 sizeof(*mac->hw_stats), 4367 GFP_KERNEL); 4368 if (!mac->hw_stats) { 4369 dev_err(eth->dev, "failed to allocate counter memory\n"); 4370 err = -ENOMEM; 4371 goto free_netdev; 4372 } 4373 spin_lock_init(&mac->hw_stats->stats_lock); 4374 u64_stats_init(&mac->hw_stats->syncp); 4375 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4376 4377 /* phylink create */ 4378 err = of_get_phy_mode(np, &phy_mode); 4379 if (err) { 4380 dev_err(eth->dev, "incorrect phy-mode\n"); 4381 goto free_netdev; 4382 } 4383 4384 /* mac config is not set */ 4385 mac->interface = PHY_INTERFACE_MODE_NA; 4386 mac->speed = SPEED_UNKNOWN; 4387 4388 mac->phylink_config.dev = ð->netdev[id]->dev; 4389 mac->phylink_config.type = PHYLINK_NETDEV; 4390 /* This driver makes use of state->speed in mac_config */ 4391 mac->phylink_config.legacy_pre_march2020 = true; 4392 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4393 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4394 4395 __set_bit(PHY_INTERFACE_MODE_MII, 4396 mac->phylink_config.supported_interfaces); 4397 __set_bit(PHY_INTERFACE_MODE_GMII, 4398 mac->phylink_config.supported_interfaces); 4399 4400 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4401 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4402 4403 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4404 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4405 mac->phylink_config.supported_interfaces); 4406 4407 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4408 __set_bit(PHY_INTERFACE_MODE_SGMII, 4409 mac->phylink_config.supported_interfaces); 4410 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4411 mac->phylink_config.supported_interfaces); 4412 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4413 mac->phylink_config.supported_interfaces); 4414 } 4415 4416 phylink = phylink_create(&mac->phylink_config, 4417 of_fwnode_handle(mac->of_node), 4418 phy_mode, &mtk_phylink_ops); 4419 if (IS_ERR(phylink)) { 4420 err = PTR_ERR(phylink); 4421 goto free_netdev; 4422 } 4423 4424 mac->phylink = phylink; 4425 4426 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4427 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4428 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4429 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4430 4431 eth->netdev[id]->hw_features = eth->soc->hw_features; 4432 if (eth->hwlro) 4433 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4434 4435 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4436 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 4437 eth->netdev[id]->features |= eth->soc->hw_features; 4438 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4439 4440 eth->netdev[id]->irq = eth->irq[0]; 4441 eth->netdev[id]->dev.of_node = np; 4442 4443 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4444 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4445 else 4446 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4447 4448 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4449 mac->device_notifier.notifier_call = mtk_device_event; 4450 register_netdevice_notifier(&mac->device_notifier); 4451 } 4452 4453 if (mtk_page_pool_enabled(eth)) 4454 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4455 NETDEV_XDP_ACT_REDIRECT | 4456 NETDEV_XDP_ACT_NDO_XMIT | 4457 NETDEV_XDP_ACT_NDO_XMIT_SG; 4458 4459 return 0; 4460 4461 free_netdev: 4462 free_netdev(eth->netdev[id]); 4463 return err; 4464 } 4465 4466 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4467 { 4468 struct net_device *dev, *tmp; 4469 LIST_HEAD(dev_list); 4470 int i; 4471 4472 rtnl_lock(); 4473 4474 for (i = 0; i < MTK_MAC_COUNT; i++) { 4475 dev = eth->netdev[i]; 4476 4477 if (!dev || !(dev->flags & IFF_UP)) 4478 continue; 4479 4480 list_add_tail(&dev->close_list, &dev_list); 4481 } 4482 4483 dev_close_many(&dev_list, false); 4484 4485 eth->dma_dev = dma_dev; 4486 4487 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4488 list_del_init(&dev->close_list); 4489 dev_open(dev, NULL); 4490 } 4491 4492 rtnl_unlock(); 4493 } 4494 4495 static int mtk_probe(struct platform_device *pdev) 4496 { 4497 struct resource *res = NULL; 4498 struct device_node *mac_np; 4499 struct mtk_eth *eth; 4500 int err, i; 4501 4502 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4503 if (!eth) 4504 return -ENOMEM; 4505 4506 eth->soc = of_device_get_match_data(&pdev->dev); 4507 4508 eth->dev = &pdev->dev; 4509 eth->dma_dev = &pdev->dev; 4510 eth->base = devm_platform_ioremap_resource(pdev, 0); 4511 if (IS_ERR(eth->base)) 4512 return PTR_ERR(eth->base); 4513 4514 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4515 eth->ip_align = NET_IP_ALIGN; 4516 4517 spin_lock_init(ð->page_lock); 4518 spin_lock_init(ð->tx_irq_lock); 4519 spin_lock_init(ð->rx_irq_lock); 4520 spin_lock_init(ð->dim_lock); 4521 4522 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4523 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4524 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4525 4526 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4527 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4528 4529 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4530 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4531 "mediatek,ethsys"); 4532 if (IS_ERR(eth->ethsys)) { 4533 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4534 return PTR_ERR(eth->ethsys); 4535 } 4536 } 4537 4538 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4539 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4540 "mediatek,infracfg"); 4541 if (IS_ERR(eth->infra)) { 4542 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4543 return PTR_ERR(eth->infra); 4544 } 4545 } 4546 4547 if (of_dma_is_coherent(pdev->dev.of_node)) { 4548 struct regmap *cci; 4549 4550 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4551 "cci-control-port"); 4552 /* enable CPU/bus coherency */ 4553 if (!IS_ERR(cci)) 4554 regmap_write(cci, 0, 3); 4555 } 4556 4557 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4558 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 4559 GFP_KERNEL); 4560 if (!eth->sgmii) 4561 return -ENOMEM; 4562 4563 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 4564 eth->soc->ana_rgc3); 4565 4566 if (err) 4567 return err; 4568 } 4569 4570 if (eth->soc->required_pctl) { 4571 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4572 "mediatek,pctl"); 4573 if (IS_ERR(eth->pctl)) { 4574 dev_err(&pdev->dev, "no pctl regmap found\n"); 4575 return PTR_ERR(eth->pctl); 4576 } 4577 } 4578 4579 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4581 if (!res) 4582 return -EINVAL; 4583 } 4584 4585 if (eth->soc->offload_version) { 4586 for (i = 0;; i++) { 4587 struct device_node *np; 4588 phys_addr_t wdma_phy; 4589 u32 wdma_base; 4590 4591 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4592 break; 4593 4594 np = of_parse_phandle(pdev->dev.of_node, 4595 "mediatek,wed", i); 4596 if (!np) 4597 break; 4598 4599 wdma_base = eth->soc->reg_map->wdma_base[i]; 4600 wdma_phy = res ? res->start + wdma_base : 0; 4601 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4602 wdma_phy, i); 4603 } 4604 } 4605 4606 for (i = 0; i < 3; i++) { 4607 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4608 eth->irq[i] = eth->irq[0]; 4609 else 4610 eth->irq[i] = platform_get_irq(pdev, i); 4611 if (eth->irq[i] < 0) { 4612 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4613 err = -ENXIO; 4614 goto err_wed_exit; 4615 } 4616 } 4617 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4618 eth->clks[i] = devm_clk_get(eth->dev, 4619 mtk_clks_source_name[i]); 4620 if (IS_ERR(eth->clks[i])) { 4621 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4622 err = -EPROBE_DEFER; 4623 goto err_wed_exit; 4624 } 4625 if (eth->soc->required_clks & BIT(i)) { 4626 dev_err(&pdev->dev, "clock %s not found\n", 4627 mtk_clks_source_name[i]); 4628 err = -EINVAL; 4629 goto err_wed_exit; 4630 } 4631 eth->clks[i] = NULL; 4632 } 4633 } 4634 4635 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4636 INIT_WORK(ð->pending_work, mtk_pending_work); 4637 4638 err = mtk_hw_init(eth, false); 4639 if (err) 4640 goto err_wed_exit; 4641 4642 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4643 4644 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4645 if (!of_device_is_compatible(mac_np, 4646 "mediatek,eth-mac")) 4647 continue; 4648 4649 if (!of_device_is_available(mac_np)) 4650 continue; 4651 4652 err = mtk_add_mac(eth, mac_np); 4653 if (err) { 4654 of_node_put(mac_np); 4655 goto err_deinit_hw; 4656 } 4657 } 4658 4659 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4660 err = devm_request_irq(eth->dev, eth->irq[0], 4661 mtk_handle_irq, 0, 4662 dev_name(eth->dev), eth); 4663 } else { 4664 err = devm_request_irq(eth->dev, eth->irq[1], 4665 mtk_handle_irq_tx, 0, 4666 dev_name(eth->dev), eth); 4667 if (err) 4668 goto err_free_dev; 4669 4670 err = devm_request_irq(eth->dev, eth->irq[2], 4671 mtk_handle_irq_rx, 0, 4672 dev_name(eth->dev), eth); 4673 } 4674 if (err) 4675 goto err_free_dev; 4676 4677 /* No MT7628/88 support yet */ 4678 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4679 err = mtk_mdio_init(eth); 4680 if (err) 4681 goto err_free_dev; 4682 } 4683 4684 if (eth->soc->offload_version) { 4685 u32 num_ppe; 4686 4687 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4688 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4689 for (i = 0; i < num_ppe; i++) { 4690 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4691 4692 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, 4693 eth->soc->offload_version, i); 4694 if (!eth->ppe[i]) { 4695 err = -ENOMEM; 4696 goto err_deinit_ppe; 4697 } 4698 } 4699 4700 err = mtk_eth_offload_init(eth); 4701 if (err) 4702 goto err_deinit_ppe; 4703 } 4704 4705 for (i = 0; i < MTK_MAX_DEVS; i++) { 4706 if (!eth->netdev[i]) 4707 continue; 4708 4709 err = register_netdev(eth->netdev[i]); 4710 if (err) { 4711 dev_err(eth->dev, "error bringing up device\n"); 4712 goto err_deinit_ppe; 4713 } else 4714 netif_info(eth, probe, eth->netdev[i], 4715 "mediatek frame engine at 0x%08lx, irq %d\n", 4716 eth->netdev[i]->base_addr, eth->irq[0]); 4717 } 4718 4719 /* we run 2 devices on the same DMA ring so we need a dummy device 4720 * for NAPI to work 4721 */ 4722 init_dummy_netdev(ð->dummy_dev); 4723 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4724 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4725 4726 platform_set_drvdata(pdev, eth); 4727 schedule_delayed_work(ð->reset.monitor_work, 4728 MTK_DMA_MONITOR_TIMEOUT); 4729 4730 return 0; 4731 4732 err_deinit_ppe: 4733 mtk_ppe_deinit(eth); 4734 mtk_mdio_cleanup(eth); 4735 err_free_dev: 4736 mtk_free_dev(eth); 4737 err_deinit_hw: 4738 mtk_hw_deinit(eth); 4739 err_wed_exit: 4740 mtk_wed_exit(); 4741 4742 return err; 4743 } 4744 4745 static int mtk_remove(struct platform_device *pdev) 4746 { 4747 struct mtk_eth *eth = platform_get_drvdata(pdev); 4748 struct mtk_mac *mac; 4749 int i; 4750 4751 /* stop all devices to make sure that dma is properly shut down */ 4752 for (i = 0; i < MTK_MAC_COUNT; i++) { 4753 if (!eth->netdev[i]) 4754 continue; 4755 mtk_stop(eth->netdev[i]); 4756 mac = netdev_priv(eth->netdev[i]); 4757 phylink_disconnect_phy(mac->phylink); 4758 } 4759 4760 mtk_wed_exit(); 4761 mtk_hw_deinit(eth); 4762 4763 netif_napi_del(ð->tx_napi); 4764 netif_napi_del(ð->rx_napi); 4765 mtk_cleanup(eth); 4766 mtk_mdio_cleanup(eth); 4767 4768 return 0; 4769 } 4770 4771 static const struct mtk_soc_data mt2701_data = { 4772 .reg_map = &mtk_reg_map, 4773 .caps = MT7623_CAPS | MTK_HWLRO, 4774 .hw_features = MTK_HW_FEATURES, 4775 .required_clks = MT7623_CLKS_BITMAP, 4776 .required_pctl = true, 4777 .txrx = { 4778 .txd_size = sizeof(struct mtk_tx_dma), 4779 .rxd_size = sizeof(struct mtk_rx_dma), 4780 .rx_irq_done_mask = MTK_RX_DONE_INT, 4781 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4782 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4783 .dma_len_offset = 16, 4784 }, 4785 }; 4786 4787 static const struct mtk_soc_data mt7621_data = { 4788 .reg_map = &mtk_reg_map, 4789 .caps = MT7621_CAPS, 4790 .hw_features = MTK_HW_FEATURES, 4791 .required_clks = MT7621_CLKS_BITMAP, 4792 .required_pctl = false, 4793 .offload_version = 1, 4794 .hash_offset = 2, 4795 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4796 .txrx = { 4797 .txd_size = sizeof(struct mtk_tx_dma), 4798 .rxd_size = sizeof(struct mtk_rx_dma), 4799 .rx_irq_done_mask = MTK_RX_DONE_INT, 4800 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4801 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4802 .dma_len_offset = 16, 4803 }, 4804 }; 4805 4806 static const struct mtk_soc_data mt7622_data = { 4807 .reg_map = &mtk_reg_map, 4808 .ana_rgc3 = 0x2028, 4809 .caps = MT7622_CAPS | MTK_HWLRO, 4810 .hw_features = MTK_HW_FEATURES, 4811 .required_clks = MT7622_CLKS_BITMAP, 4812 .required_pctl = false, 4813 .offload_version = 2, 4814 .hash_offset = 2, 4815 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4816 .txrx = { 4817 .txd_size = sizeof(struct mtk_tx_dma), 4818 .rxd_size = sizeof(struct mtk_rx_dma), 4819 .rx_irq_done_mask = MTK_RX_DONE_INT, 4820 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4821 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4822 .dma_len_offset = 16, 4823 }, 4824 }; 4825 4826 static const struct mtk_soc_data mt7623_data = { 4827 .reg_map = &mtk_reg_map, 4828 .caps = MT7623_CAPS | MTK_HWLRO, 4829 .hw_features = MTK_HW_FEATURES, 4830 .required_clks = MT7623_CLKS_BITMAP, 4831 .required_pctl = true, 4832 .offload_version = 1, 4833 .hash_offset = 2, 4834 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4835 .txrx = { 4836 .txd_size = sizeof(struct mtk_tx_dma), 4837 .rxd_size = sizeof(struct mtk_rx_dma), 4838 .rx_irq_done_mask = MTK_RX_DONE_INT, 4839 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4840 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4841 .dma_len_offset = 16, 4842 }, 4843 }; 4844 4845 static const struct mtk_soc_data mt7629_data = { 4846 .reg_map = &mtk_reg_map, 4847 .ana_rgc3 = 0x128, 4848 .caps = MT7629_CAPS | MTK_HWLRO, 4849 .hw_features = MTK_HW_FEATURES, 4850 .required_clks = MT7629_CLKS_BITMAP, 4851 .required_pctl = false, 4852 .txrx = { 4853 .txd_size = sizeof(struct mtk_tx_dma), 4854 .rxd_size = sizeof(struct mtk_rx_dma), 4855 .rx_irq_done_mask = MTK_RX_DONE_INT, 4856 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4857 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4858 .dma_len_offset = 16, 4859 }, 4860 }; 4861 4862 static const struct mtk_soc_data mt7986_data = { 4863 .reg_map = &mt7986_reg_map, 4864 .ana_rgc3 = 0x128, 4865 .caps = MT7986_CAPS, 4866 .hw_features = MTK_HW_FEATURES, 4867 .required_clks = MT7986_CLKS_BITMAP, 4868 .required_pctl = false, 4869 .offload_version = 2, 4870 .hash_offset = 4, 4871 .foe_entry_size = sizeof(struct mtk_foe_entry), 4872 .txrx = { 4873 .txd_size = sizeof(struct mtk_tx_dma_v2), 4874 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4875 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4876 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4877 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4878 .dma_len_offset = 8, 4879 }, 4880 }; 4881 4882 static const struct mtk_soc_data rt5350_data = { 4883 .reg_map = &mt7628_reg_map, 4884 .caps = MT7628_CAPS, 4885 .hw_features = MTK_HW_FEATURES_MT7628, 4886 .required_clks = MT7628_CLKS_BITMAP, 4887 .required_pctl = false, 4888 .txrx = { 4889 .txd_size = sizeof(struct mtk_tx_dma), 4890 .rxd_size = sizeof(struct mtk_rx_dma), 4891 .rx_irq_done_mask = MTK_RX_DONE_INT, 4892 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4893 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4894 .dma_len_offset = 16, 4895 }, 4896 }; 4897 4898 const struct of_device_id of_mtk_match[] = { 4899 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4900 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4901 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4902 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4903 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4904 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4905 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4906 {}, 4907 }; 4908 MODULE_DEVICE_TABLE(of, of_mtk_match); 4909 4910 static struct platform_driver mtk_driver = { 4911 .probe = mtk_probe, 4912 .remove = mtk_remove, 4913 .driver = { 4914 .name = "mtk_soc_eth", 4915 .of_match_table = of_mtk_match, 4916 }, 4917 }; 4918 4919 module_platform_driver(mtk_driver); 4920 4921 MODULE_LICENSE("GPL"); 4922 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4923 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4924