1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 27 #include "mtk_eth_soc.h" 28 #include "mtk_wed.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 static const struct mtk_reg_map mtk_reg_map = { 38 .tx_irq_mask = 0x1a1c, 39 .tx_irq_status = 0x1a18, 40 .pdma = { 41 .rx_ptr = 0x0900, 42 .rx_cnt_cfg = 0x0904, 43 .pcrx_ptr = 0x0908, 44 .glo_cfg = 0x0a04, 45 .rst_idx = 0x0a08, 46 .delay_irq = 0x0a0c, 47 .irq_status = 0x0a20, 48 .irq_mask = 0x0a28, 49 .int_grp = 0x0a50, 50 }, 51 .qdma = { 52 .qtx_cfg = 0x1800, 53 .rx_ptr = 0x1900, 54 .rx_cnt_cfg = 0x1904, 55 .qcrx_ptr = 0x1908, 56 .glo_cfg = 0x1a04, 57 .rst_idx = 0x1a08, 58 .delay_irq = 0x1a0c, 59 .fc_th = 0x1a10, 60 .int_grp = 0x1a20, 61 .hred = 0x1a44, 62 .ctx_ptr = 0x1b00, 63 .dtx_ptr = 0x1b04, 64 .crx_ptr = 0x1b10, 65 .drx_ptr = 0x1b14, 66 .fq_head = 0x1b20, 67 .fq_tail = 0x1b24, 68 .fq_count = 0x1b28, 69 .fq_blen = 0x1b2c, 70 }, 71 .gdm1_cnt = 0x2400, 72 }; 73 74 static const struct mtk_reg_map mt7628_reg_map = { 75 .tx_irq_mask = 0x0a28, 76 .tx_irq_status = 0x0a20, 77 .pdma = { 78 .rx_ptr = 0x0900, 79 .rx_cnt_cfg = 0x0904, 80 .pcrx_ptr = 0x0908, 81 .glo_cfg = 0x0a04, 82 .rst_idx = 0x0a08, 83 .delay_irq = 0x0a0c, 84 .irq_status = 0x0a20, 85 .irq_mask = 0x0a28, 86 .int_grp = 0x0a50, 87 }, 88 }; 89 90 static const struct mtk_reg_map mt7986_reg_map = { 91 .tx_irq_mask = 0x461c, 92 .tx_irq_status = 0x4618, 93 .pdma = { 94 .rx_ptr = 0x6100, 95 .rx_cnt_cfg = 0x6104, 96 .pcrx_ptr = 0x6108, 97 .glo_cfg = 0x6204, 98 .rst_idx = 0x6208, 99 .delay_irq = 0x620c, 100 .irq_status = 0x6220, 101 .irq_mask = 0x6228, 102 .int_grp = 0x6250, 103 }, 104 .qdma = { 105 .qtx_cfg = 0x4400, 106 .rx_ptr = 0x4500, 107 .rx_cnt_cfg = 0x4504, 108 .qcrx_ptr = 0x4508, 109 .glo_cfg = 0x4604, 110 .rst_idx = 0x4608, 111 .delay_irq = 0x460c, 112 .fc_th = 0x4610, 113 .int_grp = 0x4620, 114 .hred = 0x4644, 115 .ctx_ptr = 0x4700, 116 .dtx_ptr = 0x4704, 117 .crx_ptr = 0x4710, 118 .drx_ptr = 0x4714, 119 .fq_head = 0x4720, 120 .fq_tail = 0x4724, 121 .fq_count = 0x4728, 122 .fq_blen = 0x472c, 123 }, 124 .gdm1_cnt = 0x1c00, 125 }; 126 127 /* strings used by ethtool */ 128 static const struct mtk_ethtool_stats { 129 char str[ETH_GSTRING_LEN]; 130 u32 offset; 131 } mtk_ethtool_stats[] = { 132 MTK_ETHTOOL_STAT(tx_bytes), 133 MTK_ETHTOOL_STAT(tx_packets), 134 MTK_ETHTOOL_STAT(tx_skip), 135 MTK_ETHTOOL_STAT(tx_collisions), 136 MTK_ETHTOOL_STAT(rx_bytes), 137 MTK_ETHTOOL_STAT(rx_packets), 138 MTK_ETHTOOL_STAT(rx_overflow), 139 MTK_ETHTOOL_STAT(rx_fcs_errors), 140 MTK_ETHTOOL_STAT(rx_short_errors), 141 MTK_ETHTOOL_STAT(rx_long_errors), 142 MTK_ETHTOOL_STAT(rx_checksum_errors), 143 MTK_ETHTOOL_STAT(rx_flow_control_packets), 144 }; 145 146 static const char * const mtk_clks_source_name[] = { 147 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 148 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 149 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 150 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 151 }; 152 153 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 154 { 155 __raw_writel(val, eth->base + reg); 156 } 157 158 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 159 { 160 return __raw_readl(eth->base + reg); 161 } 162 163 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 164 { 165 u32 val; 166 167 val = mtk_r32(eth, reg); 168 val &= ~mask; 169 val |= set; 170 mtk_w32(eth, val, reg); 171 return reg; 172 } 173 174 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 175 { 176 unsigned long t_start = jiffies; 177 178 while (1) { 179 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 180 return 0; 181 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 182 break; 183 cond_resched(); 184 } 185 186 dev_err(eth->dev, "mdio: MDIO timeout\n"); 187 return -ETIMEDOUT; 188 } 189 190 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 191 u32 write_data) 192 { 193 int ret; 194 195 ret = mtk_mdio_busy_wait(eth); 196 if (ret < 0) 197 return ret; 198 199 if (phy_reg & MII_ADDR_C45) { 200 mtk_w32(eth, PHY_IAC_ACCESS | 201 PHY_IAC_START_C45 | 202 PHY_IAC_CMD_C45_ADDR | 203 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 204 PHY_IAC_ADDR(phy_addr) | 205 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 206 MTK_PHY_IAC); 207 208 ret = mtk_mdio_busy_wait(eth); 209 if (ret < 0) 210 return ret; 211 212 mtk_w32(eth, PHY_IAC_ACCESS | 213 PHY_IAC_START_C45 | 214 PHY_IAC_CMD_WRITE | 215 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 216 PHY_IAC_ADDR(phy_addr) | 217 PHY_IAC_DATA(write_data), 218 MTK_PHY_IAC); 219 } else { 220 mtk_w32(eth, PHY_IAC_ACCESS | 221 PHY_IAC_START_C22 | 222 PHY_IAC_CMD_WRITE | 223 PHY_IAC_REG(phy_reg) | 224 PHY_IAC_ADDR(phy_addr) | 225 PHY_IAC_DATA(write_data), 226 MTK_PHY_IAC); 227 } 228 229 ret = mtk_mdio_busy_wait(eth); 230 if (ret < 0) 231 return ret; 232 233 return 0; 234 } 235 236 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 237 { 238 int ret; 239 240 ret = mtk_mdio_busy_wait(eth); 241 if (ret < 0) 242 return ret; 243 244 if (phy_reg & MII_ADDR_C45) { 245 mtk_w32(eth, PHY_IAC_ACCESS | 246 PHY_IAC_START_C45 | 247 PHY_IAC_CMD_C45_ADDR | 248 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 249 PHY_IAC_ADDR(phy_addr) | 250 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 251 MTK_PHY_IAC); 252 253 ret = mtk_mdio_busy_wait(eth); 254 if (ret < 0) 255 return ret; 256 257 mtk_w32(eth, PHY_IAC_ACCESS | 258 PHY_IAC_START_C45 | 259 PHY_IAC_CMD_C45_READ | 260 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 261 PHY_IAC_ADDR(phy_addr), 262 MTK_PHY_IAC); 263 } else { 264 mtk_w32(eth, PHY_IAC_ACCESS | 265 PHY_IAC_START_C22 | 266 PHY_IAC_CMD_C22_READ | 267 PHY_IAC_REG(phy_reg) | 268 PHY_IAC_ADDR(phy_addr), 269 MTK_PHY_IAC); 270 } 271 272 ret = mtk_mdio_busy_wait(eth); 273 if (ret < 0) 274 return ret; 275 276 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 277 } 278 279 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 280 int phy_reg, u16 val) 281 { 282 struct mtk_eth *eth = bus->priv; 283 284 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 285 } 286 287 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 288 { 289 struct mtk_eth *eth = bus->priv; 290 291 return _mtk_mdio_read(eth, phy_addr, phy_reg); 292 } 293 294 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 295 phy_interface_t interface) 296 { 297 u32 val; 298 299 /* Check DDR memory type. 300 * Currently TRGMII mode with DDR2 memory is not supported. 301 */ 302 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 303 if (interface == PHY_INTERFACE_MODE_TRGMII && 304 val & SYSCFG_DRAM_TYPE_DDR2) { 305 dev_err(eth->dev, 306 "TRGMII mode with DDR2 memory is not supported!\n"); 307 return -EOPNOTSUPP; 308 } 309 310 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 311 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 312 313 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 314 ETHSYS_TRGMII_MT7621_MASK, val); 315 316 return 0; 317 } 318 319 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 320 phy_interface_t interface, int speed) 321 { 322 u32 val; 323 int ret; 324 325 if (interface == PHY_INTERFACE_MODE_TRGMII) { 326 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 327 val = 500000000; 328 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 329 if (ret) 330 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 331 return; 332 } 333 334 val = (speed == SPEED_1000) ? 335 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 336 mtk_w32(eth, val, INTF_MODE); 337 338 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 339 ETHSYS_TRGMII_CLK_SEL362_5, 340 ETHSYS_TRGMII_CLK_SEL362_5); 341 342 val = (speed == SPEED_1000) ? 250000000 : 500000000; 343 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 344 if (ret) 345 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 346 347 val = (speed == SPEED_1000) ? 348 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 349 mtk_w32(eth, val, TRGMII_RCK_CTRL); 350 351 val = (speed == SPEED_1000) ? 352 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 353 mtk_w32(eth, val, TRGMII_TCK_CTRL); 354 } 355 356 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 357 phy_interface_t interface) 358 { 359 struct mtk_mac *mac = container_of(config, struct mtk_mac, 360 phylink_config); 361 struct mtk_eth *eth = mac->hw; 362 unsigned int sid; 363 364 if (interface == PHY_INTERFACE_MODE_SGMII || 365 phy_interface_mode_is_8023z(interface)) { 366 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 367 0 : mac->id; 368 369 return mtk_sgmii_select_pcs(eth->sgmii, sid); 370 } 371 372 return NULL; 373 } 374 375 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 376 const struct phylink_link_state *state) 377 { 378 struct mtk_mac *mac = container_of(config, struct mtk_mac, 379 phylink_config); 380 struct mtk_eth *eth = mac->hw; 381 int val, ge_mode, err = 0; 382 u32 i; 383 384 /* MT76x8 has no hardware settings between for the MAC */ 385 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 386 mac->interface != state->interface) { 387 /* Setup soc pin functions */ 388 switch (state->interface) { 389 case PHY_INTERFACE_MODE_TRGMII: 390 if (mac->id) 391 goto err_phy; 392 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 393 MTK_GMAC1_TRGMII)) 394 goto err_phy; 395 fallthrough; 396 case PHY_INTERFACE_MODE_RGMII_TXID: 397 case PHY_INTERFACE_MODE_RGMII_RXID: 398 case PHY_INTERFACE_MODE_RGMII_ID: 399 case PHY_INTERFACE_MODE_RGMII: 400 case PHY_INTERFACE_MODE_MII: 401 case PHY_INTERFACE_MODE_REVMII: 402 case PHY_INTERFACE_MODE_RMII: 403 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 404 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 405 if (err) 406 goto init_err; 407 } 408 break; 409 case PHY_INTERFACE_MODE_1000BASEX: 410 case PHY_INTERFACE_MODE_2500BASEX: 411 case PHY_INTERFACE_MODE_SGMII: 412 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 413 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 414 if (err) 415 goto init_err; 416 } 417 break; 418 case PHY_INTERFACE_MODE_GMII: 419 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 420 err = mtk_gmac_gephy_path_setup(eth, mac->id); 421 if (err) 422 goto init_err; 423 } 424 break; 425 default: 426 goto err_phy; 427 } 428 429 /* Setup clock for 1st gmac */ 430 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 431 !phy_interface_mode_is_8023z(state->interface) && 432 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 433 if (MTK_HAS_CAPS(mac->hw->soc->caps, 434 MTK_TRGMII_MT7621_CLK)) { 435 if (mt7621_gmac0_rgmii_adjust(mac->hw, 436 state->interface)) 437 goto err_phy; 438 } else { 439 /* FIXME: this is incorrect. Not only does it 440 * use state->speed (which is not guaranteed 441 * to be correct) but it also makes use of it 442 * in a code path that will only be reachable 443 * when the PHY interface mode changes, not 444 * when the speed changes. Consequently, RGMII 445 * is probably broken. 446 */ 447 mtk_gmac0_rgmii_adjust(mac->hw, 448 state->interface, 449 state->speed); 450 451 /* mt7623_pad_clk_setup */ 452 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 453 mtk_w32(mac->hw, 454 TD_DM_DRVP(8) | TD_DM_DRVN(8), 455 TRGMII_TD_ODT(i)); 456 457 /* Assert/release MT7623 RXC reset */ 458 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 459 TRGMII_RCK_CTRL); 460 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 461 } 462 } 463 464 ge_mode = 0; 465 switch (state->interface) { 466 case PHY_INTERFACE_MODE_MII: 467 case PHY_INTERFACE_MODE_GMII: 468 ge_mode = 1; 469 break; 470 case PHY_INTERFACE_MODE_REVMII: 471 ge_mode = 2; 472 break; 473 case PHY_INTERFACE_MODE_RMII: 474 if (mac->id) 475 goto err_phy; 476 ge_mode = 3; 477 break; 478 default: 479 break; 480 } 481 482 /* put the gmac into the right mode */ 483 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 484 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 485 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 486 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 487 488 mac->interface = state->interface; 489 } 490 491 /* SGMII */ 492 if (state->interface == PHY_INTERFACE_MODE_SGMII || 493 phy_interface_mode_is_8023z(state->interface)) { 494 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 495 * being setup done. 496 */ 497 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 498 499 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 500 SYSCFG0_SGMII_MASK, 501 ~(u32)SYSCFG0_SGMII_MASK); 502 503 /* Save the syscfg0 value for mac_finish */ 504 mac->syscfg0 = val; 505 } else if (phylink_autoneg_inband(mode)) { 506 dev_err(eth->dev, 507 "In-band mode not supported in non SGMII mode!\n"); 508 return; 509 } 510 511 return; 512 513 err_phy: 514 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 515 mac->id, phy_modes(state->interface)); 516 return; 517 518 init_err: 519 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 520 mac->id, phy_modes(state->interface), err); 521 } 522 523 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 524 phy_interface_t interface) 525 { 526 struct mtk_mac *mac = container_of(config, struct mtk_mac, 527 phylink_config); 528 struct mtk_eth *eth = mac->hw; 529 u32 mcr_cur, mcr_new; 530 531 /* Enable SGMII */ 532 if (interface == PHY_INTERFACE_MODE_SGMII || 533 phy_interface_mode_is_8023z(interface)) 534 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 535 SYSCFG0_SGMII_MASK, mac->syscfg0); 536 537 /* Setup gmac */ 538 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 539 mcr_new = mcr_cur; 540 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 541 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 542 543 /* Only update control register when needed! */ 544 if (mcr_new != mcr_cur) 545 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 546 547 return 0; 548 } 549 550 static void mtk_mac_pcs_get_state(struct phylink_config *config, 551 struct phylink_link_state *state) 552 { 553 struct mtk_mac *mac = container_of(config, struct mtk_mac, 554 phylink_config); 555 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 556 557 state->link = (pmsr & MAC_MSR_LINK); 558 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 559 560 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 561 case 0: 562 state->speed = SPEED_10; 563 break; 564 case MAC_MSR_SPEED_100: 565 state->speed = SPEED_100; 566 break; 567 case MAC_MSR_SPEED_1000: 568 state->speed = SPEED_1000; 569 break; 570 default: 571 state->speed = SPEED_UNKNOWN; 572 break; 573 } 574 575 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 576 if (pmsr & MAC_MSR_RX_FC) 577 state->pause |= MLO_PAUSE_RX; 578 if (pmsr & MAC_MSR_TX_FC) 579 state->pause |= MLO_PAUSE_TX; 580 } 581 582 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 583 phy_interface_t interface) 584 { 585 struct mtk_mac *mac = container_of(config, struct mtk_mac, 586 phylink_config); 587 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 588 589 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 590 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 591 } 592 593 static void mtk_mac_link_up(struct phylink_config *config, 594 struct phy_device *phy, 595 unsigned int mode, phy_interface_t interface, 596 int speed, int duplex, bool tx_pause, bool rx_pause) 597 { 598 struct mtk_mac *mac = container_of(config, struct mtk_mac, 599 phylink_config); 600 u32 mcr; 601 602 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 603 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 604 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 605 MAC_MCR_FORCE_RX_FC); 606 607 /* Configure speed */ 608 switch (speed) { 609 case SPEED_2500: 610 case SPEED_1000: 611 mcr |= MAC_MCR_SPEED_1000; 612 break; 613 case SPEED_100: 614 mcr |= MAC_MCR_SPEED_100; 615 break; 616 } 617 618 /* Configure duplex */ 619 if (duplex == DUPLEX_FULL) 620 mcr |= MAC_MCR_FORCE_DPX; 621 622 /* Configure pause modes - phylink will avoid these for half duplex */ 623 if (tx_pause) 624 mcr |= MAC_MCR_FORCE_TX_FC; 625 if (rx_pause) 626 mcr |= MAC_MCR_FORCE_RX_FC; 627 628 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 629 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 630 } 631 632 static const struct phylink_mac_ops mtk_phylink_ops = { 633 .validate = phylink_generic_validate, 634 .mac_select_pcs = mtk_mac_select_pcs, 635 .mac_pcs_get_state = mtk_mac_pcs_get_state, 636 .mac_config = mtk_mac_config, 637 .mac_finish = mtk_mac_finish, 638 .mac_link_down = mtk_mac_link_down, 639 .mac_link_up = mtk_mac_link_up, 640 }; 641 642 static int mtk_mdio_init(struct mtk_eth *eth) 643 { 644 struct device_node *mii_np; 645 int ret; 646 647 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 648 if (!mii_np) { 649 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 650 return -ENODEV; 651 } 652 653 if (!of_device_is_available(mii_np)) { 654 ret = -ENODEV; 655 goto err_put_node; 656 } 657 658 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 659 if (!eth->mii_bus) { 660 ret = -ENOMEM; 661 goto err_put_node; 662 } 663 664 eth->mii_bus->name = "mdio"; 665 eth->mii_bus->read = mtk_mdio_read; 666 eth->mii_bus->write = mtk_mdio_write; 667 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 668 eth->mii_bus->priv = eth; 669 eth->mii_bus->parent = eth->dev; 670 671 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 672 ret = of_mdiobus_register(eth->mii_bus, mii_np); 673 674 err_put_node: 675 of_node_put(mii_np); 676 return ret; 677 } 678 679 static void mtk_mdio_cleanup(struct mtk_eth *eth) 680 { 681 if (!eth->mii_bus) 682 return; 683 684 mdiobus_unregister(eth->mii_bus); 685 } 686 687 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 688 { 689 unsigned long flags; 690 u32 val; 691 692 spin_lock_irqsave(ð->tx_irq_lock, flags); 693 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 694 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 695 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 696 } 697 698 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 699 { 700 unsigned long flags; 701 u32 val; 702 703 spin_lock_irqsave(ð->tx_irq_lock, flags); 704 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 705 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 706 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 707 } 708 709 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 710 { 711 unsigned long flags; 712 u32 val; 713 714 spin_lock_irqsave(ð->rx_irq_lock, flags); 715 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 716 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 717 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 718 } 719 720 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 721 { 722 unsigned long flags; 723 u32 val; 724 725 spin_lock_irqsave(ð->rx_irq_lock, flags); 726 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 727 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 728 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 729 } 730 731 static int mtk_set_mac_address(struct net_device *dev, void *p) 732 { 733 int ret = eth_mac_addr(dev, p); 734 struct mtk_mac *mac = netdev_priv(dev); 735 struct mtk_eth *eth = mac->hw; 736 const char *macaddr = dev->dev_addr; 737 738 if (ret) 739 return ret; 740 741 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 742 return -EBUSY; 743 744 spin_lock_bh(&mac->hw->page_lock); 745 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 746 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 747 MT7628_SDM_MAC_ADRH); 748 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 749 (macaddr[4] << 8) | macaddr[5], 750 MT7628_SDM_MAC_ADRL); 751 } else { 752 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 753 MTK_GDMA_MAC_ADRH(mac->id)); 754 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 755 (macaddr[4] << 8) | macaddr[5], 756 MTK_GDMA_MAC_ADRL(mac->id)); 757 } 758 spin_unlock_bh(&mac->hw->page_lock); 759 760 return 0; 761 } 762 763 void mtk_stats_update_mac(struct mtk_mac *mac) 764 { 765 struct mtk_hw_stats *hw_stats = mac->hw_stats; 766 struct mtk_eth *eth = mac->hw; 767 768 u64_stats_update_begin(&hw_stats->syncp); 769 770 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 771 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 772 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 773 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 774 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 775 hw_stats->rx_checksum_errors += 776 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 777 } else { 778 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 779 unsigned int offs = hw_stats->reg_offset; 780 u64 stats; 781 782 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 783 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 784 if (stats) 785 hw_stats->rx_bytes += (stats << 32); 786 hw_stats->rx_packets += 787 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 788 hw_stats->rx_overflow += 789 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 790 hw_stats->rx_fcs_errors += 791 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 792 hw_stats->rx_short_errors += 793 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 794 hw_stats->rx_long_errors += 795 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 796 hw_stats->rx_checksum_errors += 797 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 798 hw_stats->rx_flow_control_packets += 799 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 800 hw_stats->tx_skip += 801 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 802 hw_stats->tx_collisions += 803 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 804 hw_stats->tx_bytes += 805 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 806 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 807 if (stats) 808 hw_stats->tx_bytes += (stats << 32); 809 hw_stats->tx_packets += 810 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 811 } 812 813 u64_stats_update_end(&hw_stats->syncp); 814 } 815 816 static void mtk_stats_update(struct mtk_eth *eth) 817 { 818 int i; 819 820 for (i = 0; i < MTK_MAC_COUNT; i++) { 821 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 822 continue; 823 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 824 mtk_stats_update_mac(eth->mac[i]); 825 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 826 } 827 } 828 } 829 830 static void mtk_get_stats64(struct net_device *dev, 831 struct rtnl_link_stats64 *storage) 832 { 833 struct mtk_mac *mac = netdev_priv(dev); 834 struct mtk_hw_stats *hw_stats = mac->hw_stats; 835 unsigned int start; 836 837 if (netif_running(dev) && netif_device_present(dev)) { 838 if (spin_trylock_bh(&hw_stats->stats_lock)) { 839 mtk_stats_update_mac(mac); 840 spin_unlock_bh(&hw_stats->stats_lock); 841 } 842 } 843 844 do { 845 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 846 storage->rx_packets = hw_stats->rx_packets; 847 storage->tx_packets = hw_stats->tx_packets; 848 storage->rx_bytes = hw_stats->rx_bytes; 849 storage->tx_bytes = hw_stats->tx_bytes; 850 storage->collisions = hw_stats->tx_collisions; 851 storage->rx_length_errors = hw_stats->rx_short_errors + 852 hw_stats->rx_long_errors; 853 storage->rx_over_errors = hw_stats->rx_overflow; 854 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 855 storage->rx_errors = hw_stats->rx_checksum_errors; 856 storage->tx_aborted_errors = hw_stats->tx_skip; 857 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 858 859 storage->tx_errors = dev->stats.tx_errors; 860 storage->rx_dropped = dev->stats.rx_dropped; 861 storage->tx_dropped = dev->stats.tx_dropped; 862 } 863 864 static inline int mtk_max_frag_size(int mtu) 865 { 866 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 867 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 868 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 869 870 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 871 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 872 } 873 874 static inline int mtk_max_buf_size(int frag_size) 875 { 876 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 877 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 878 879 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 880 881 return buf_size; 882 } 883 884 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 885 struct mtk_rx_dma_v2 *dma_rxd) 886 { 887 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 888 if (!(rxd->rxd2 & RX_DMA_DONE)) 889 return false; 890 891 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 892 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 893 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 894 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 895 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 896 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 897 } 898 899 return true; 900 } 901 902 /* the qdma core needs scratch memory to be setup */ 903 static int mtk_init_fq_dma(struct mtk_eth *eth) 904 { 905 const struct mtk_soc_data *soc = eth->soc; 906 dma_addr_t phy_ring_tail; 907 int cnt = MTK_DMA_SIZE; 908 dma_addr_t dma_addr; 909 int i; 910 911 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 912 cnt * soc->txrx.txd_size, 913 ð->phy_scratch_ring, 914 GFP_KERNEL); 915 if (unlikely(!eth->scratch_ring)) 916 return -ENOMEM; 917 918 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 919 if (unlikely(!eth->scratch_head)) 920 return -ENOMEM; 921 922 dma_addr = dma_map_single(eth->dma_dev, 923 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 924 DMA_FROM_DEVICE); 925 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 926 return -ENOMEM; 927 928 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 929 930 for (i = 0; i < cnt; i++) { 931 struct mtk_tx_dma_v2 *txd; 932 933 txd = eth->scratch_ring + i * soc->txrx.txd_size; 934 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 935 if (i < cnt - 1) 936 txd->txd2 = eth->phy_scratch_ring + 937 (i + 1) * soc->txrx.txd_size; 938 939 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 940 txd->txd4 = 0; 941 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 942 txd->txd5 = 0; 943 txd->txd6 = 0; 944 txd->txd7 = 0; 945 txd->txd8 = 0; 946 } 947 } 948 949 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 950 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 951 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 952 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 953 954 return 0; 955 } 956 957 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 958 { 959 return ring->dma + (desc - ring->phys); 960 } 961 962 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 963 void *txd, u32 txd_size) 964 { 965 int idx = (txd - ring->dma) / txd_size; 966 967 return &ring->buf[idx]; 968 } 969 970 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 971 struct mtk_tx_dma *dma) 972 { 973 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 974 } 975 976 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 977 { 978 return (dma - ring->dma) / txd_size; 979 } 980 981 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 982 bool napi) 983 { 984 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 985 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 986 dma_unmap_single(eth->dma_dev, 987 dma_unmap_addr(tx_buf, dma_addr0), 988 dma_unmap_len(tx_buf, dma_len0), 989 DMA_TO_DEVICE); 990 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 991 dma_unmap_page(eth->dma_dev, 992 dma_unmap_addr(tx_buf, dma_addr0), 993 dma_unmap_len(tx_buf, dma_len0), 994 DMA_TO_DEVICE); 995 } 996 } else { 997 if (dma_unmap_len(tx_buf, dma_len0)) { 998 dma_unmap_page(eth->dma_dev, 999 dma_unmap_addr(tx_buf, dma_addr0), 1000 dma_unmap_len(tx_buf, dma_len0), 1001 DMA_TO_DEVICE); 1002 } 1003 1004 if (dma_unmap_len(tx_buf, dma_len1)) { 1005 dma_unmap_page(eth->dma_dev, 1006 dma_unmap_addr(tx_buf, dma_addr1), 1007 dma_unmap_len(tx_buf, dma_len1), 1008 DMA_TO_DEVICE); 1009 } 1010 } 1011 1012 tx_buf->flags = 0; 1013 if (tx_buf->skb && 1014 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) { 1015 if (napi) 1016 napi_consume_skb(tx_buf->skb, napi); 1017 else 1018 dev_kfree_skb_any(tx_buf->skb); 1019 } 1020 tx_buf->skb = NULL; 1021 } 1022 1023 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1024 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1025 size_t size, int idx) 1026 { 1027 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1028 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1029 dma_unmap_len_set(tx_buf, dma_len0, size); 1030 } else { 1031 if (idx & 1) { 1032 txd->txd3 = mapped_addr; 1033 txd->txd2 |= TX_DMA_PLEN1(size); 1034 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1035 dma_unmap_len_set(tx_buf, dma_len1, size); 1036 } else { 1037 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1038 txd->txd1 = mapped_addr; 1039 txd->txd2 = TX_DMA_PLEN0(size); 1040 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1041 dma_unmap_len_set(tx_buf, dma_len0, size); 1042 } 1043 } 1044 } 1045 1046 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1047 struct mtk_tx_dma_desc_info *info) 1048 { 1049 struct mtk_mac *mac = netdev_priv(dev); 1050 struct mtk_eth *eth = mac->hw; 1051 struct mtk_tx_dma *desc = txd; 1052 u32 data; 1053 1054 WRITE_ONCE(desc->txd1, info->addr); 1055 1056 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size); 1057 if (info->last) 1058 data |= TX_DMA_LS0; 1059 WRITE_ONCE(desc->txd3, data); 1060 1061 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1062 if (info->first) { 1063 if (info->gso) 1064 data |= TX_DMA_TSO; 1065 /* tx checksum offload */ 1066 if (info->csum) 1067 data |= TX_DMA_CHKSUM; 1068 /* vlan header offload */ 1069 if (info->vlan) 1070 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1071 } 1072 WRITE_ONCE(desc->txd4, data); 1073 } 1074 1075 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1076 struct mtk_tx_dma_desc_info *info) 1077 { 1078 struct mtk_mac *mac = netdev_priv(dev); 1079 struct mtk_tx_dma_v2 *desc = txd; 1080 struct mtk_eth *eth = mac->hw; 1081 u32 data; 1082 1083 WRITE_ONCE(desc->txd1, info->addr); 1084 1085 data = TX_DMA_PLEN0(info->size); 1086 if (info->last) 1087 data |= TX_DMA_LS0; 1088 WRITE_ONCE(desc->txd3, data); 1089 1090 if (!info->qid && mac->id) 1091 info->qid = MTK_QDMA_GMAC2_QID; 1092 1093 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1094 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1095 WRITE_ONCE(desc->txd4, data); 1096 1097 data = 0; 1098 if (info->first) { 1099 if (info->gso) 1100 data |= TX_DMA_TSO_V2; 1101 /* tx checksum offload */ 1102 if (info->csum) 1103 data |= TX_DMA_CHKSUM_V2; 1104 } 1105 WRITE_ONCE(desc->txd5, data); 1106 1107 data = 0; 1108 if (info->first && info->vlan) 1109 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1110 WRITE_ONCE(desc->txd6, data); 1111 1112 WRITE_ONCE(desc->txd7, 0); 1113 WRITE_ONCE(desc->txd8, 0); 1114 } 1115 1116 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1117 struct mtk_tx_dma_desc_info *info) 1118 { 1119 struct mtk_mac *mac = netdev_priv(dev); 1120 struct mtk_eth *eth = mac->hw; 1121 1122 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1123 mtk_tx_set_dma_desc_v2(dev, txd, info); 1124 else 1125 mtk_tx_set_dma_desc_v1(dev, txd, info); 1126 } 1127 1128 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1129 int tx_num, struct mtk_tx_ring *ring, bool gso) 1130 { 1131 struct mtk_tx_dma_desc_info txd_info = { 1132 .size = skb_headlen(skb), 1133 .gso = gso, 1134 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1135 .vlan = skb_vlan_tag_present(skb), 1136 .qid = skb->mark & MTK_QDMA_TX_MASK, 1137 .vlan_tci = skb_vlan_tag_get(skb), 1138 .first = true, 1139 .last = !skb_is_nonlinear(skb), 1140 }; 1141 struct mtk_mac *mac = netdev_priv(dev); 1142 struct mtk_eth *eth = mac->hw; 1143 const struct mtk_soc_data *soc = eth->soc; 1144 struct mtk_tx_dma *itxd, *txd; 1145 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1146 struct mtk_tx_buf *itx_buf, *tx_buf; 1147 int i, n_desc = 1; 1148 int k = 0; 1149 1150 itxd = ring->next_free; 1151 itxd_pdma = qdma_to_pdma(ring, itxd); 1152 if (itxd == ring->last_free) 1153 return -ENOMEM; 1154 1155 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1156 memset(itx_buf, 0, sizeof(*itx_buf)); 1157 1158 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1159 DMA_TO_DEVICE); 1160 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1161 return -ENOMEM; 1162 1163 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1164 1165 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1166 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1167 MTK_TX_FLAGS_FPORT1; 1168 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1169 k++); 1170 1171 /* TX SG offload */ 1172 txd = itxd; 1173 txd_pdma = qdma_to_pdma(ring, txd); 1174 1175 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1176 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1177 unsigned int offset = 0; 1178 int frag_size = skb_frag_size(frag); 1179 1180 while (frag_size) { 1181 bool new_desc = true; 1182 1183 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1184 (i & 0x1)) { 1185 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1186 txd_pdma = qdma_to_pdma(ring, txd); 1187 if (txd == ring->last_free) 1188 goto err_dma; 1189 1190 n_desc++; 1191 } else { 1192 new_desc = false; 1193 } 1194 1195 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1196 txd_info.size = min_t(unsigned int, frag_size, 1197 soc->txrx.dma_max_len); 1198 txd_info.qid = skb->mark & MTK_QDMA_TX_MASK; 1199 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1200 !(frag_size - txd_info.size); 1201 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1202 offset, txd_info.size, 1203 DMA_TO_DEVICE); 1204 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1205 goto err_dma; 1206 1207 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1208 1209 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1210 soc->txrx.txd_size); 1211 if (new_desc) 1212 memset(tx_buf, 0, sizeof(*tx_buf)); 1213 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1214 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1215 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1216 MTK_TX_FLAGS_FPORT1; 1217 1218 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1219 txd_info.size, k++); 1220 1221 frag_size -= txd_info.size; 1222 offset += txd_info.size; 1223 } 1224 } 1225 1226 /* store skb to cleanup */ 1227 itx_buf->skb = skb; 1228 1229 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1230 if (k & 0x1) 1231 txd_pdma->txd2 |= TX_DMA_LS0; 1232 else 1233 txd_pdma->txd2 |= TX_DMA_LS1; 1234 } 1235 1236 netdev_sent_queue(dev, skb->len); 1237 skb_tx_timestamp(skb); 1238 1239 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1240 atomic_sub(n_desc, &ring->free_count); 1241 1242 /* make sure that all changes to the dma ring are flushed before we 1243 * continue 1244 */ 1245 wmb(); 1246 1247 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1248 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1249 !netdev_xmit_more()) 1250 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1251 } else { 1252 int next_idx; 1253 1254 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1255 ring->dma_size); 1256 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1257 } 1258 1259 return 0; 1260 1261 err_dma: 1262 do { 1263 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1264 1265 /* unmap dma */ 1266 mtk_tx_unmap(eth, tx_buf, false); 1267 1268 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1269 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1270 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1271 1272 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1273 itxd_pdma = qdma_to_pdma(ring, itxd); 1274 } while (itxd != txd); 1275 1276 return -ENOMEM; 1277 } 1278 1279 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1280 { 1281 int i, nfrags = 1; 1282 skb_frag_t *frag; 1283 1284 if (skb_is_gso(skb)) { 1285 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1286 frag = &skb_shinfo(skb)->frags[i]; 1287 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1288 eth->soc->txrx.dma_max_len); 1289 } 1290 } else { 1291 nfrags += skb_shinfo(skb)->nr_frags; 1292 } 1293 1294 return nfrags; 1295 } 1296 1297 static int mtk_queue_stopped(struct mtk_eth *eth) 1298 { 1299 int i; 1300 1301 for (i = 0; i < MTK_MAC_COUNT; i++) { 1302 if (!eth->netdev[i]) 1303 continue; 1304 if (netif_queue_stopped(eth->netdev[i])) 1305 return 1; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static void mtk_wake_queue(struct mtk_eth *eth) 1312 { 1313 int i; 1314 1315 for (i = 0; i < MTK_MAC_COUNT; i++) { 1316 if (!eth->netdev[i]) 1317 continue; 1318 netif_wake_queue(eth->netdev[i]); 1319 } 1320 } 1321 1322 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1323 { 1324 struct mtk_mac *mac = netdev_priv(dev); 1325 struct mtk_eth *eth = mac->hw; 1326 struct mtk_tx_ring *ring = ð->tx_ring; 1327 struct net_device_stats *stats = &dev->stats; 1328 bool gso = false; 1329 int tx_num; 1330 1331 /* normally we can rely on the stack not calling this more than once, 1332 * however we have 2 queues running on the same ring so we need to lock 1333 * the ring access 1334 */ 1335 spin_lock(ð->page_lock); 1336 1337 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1338 goto drop; 1339 1340 tx_num = mtk_cal_txd_req(eth, skb); 1341 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1342 netif_stop_queue(dev); 1343 netif_err(eth, tx_queued, dev, 1344 "Tx Ring full when queue awake!\n"); 1345 spin_unlock(ð->page_lock); 1346 return NETDEV_TX_BUSY; 1347 } 1348 1349 /* TSO: fill MSS info in tcp checksum field */ 1350 if (skb_is_gso(skb)) { 1351 if (skb_cow_head(skb, 0)) { 1352 netif_warn(eth, tx_err, dev, 1353 "GSO expand head fail.\n"); 1354 goto drop; 1355 } 1356 1357 if (skb_shinfo(skb)->gso_type & 1358 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1359 gso = true; 1360 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1361 } 1362 } 1363 1364 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1365 goto drop; 1366 1367 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1368 netif_stop_queue(dev); 1369 1370 spin_unlock(ð->page_lock); 1371 1372 return NETDEV_TX_OK; 1373 1374 drop: 1375 spin_unlock(ð->page_lock); 1376 stats->tx_dropped++; 1377 dev_kfree_skb_any(skb); 1378 return NETDEV_TX_OK; 1379 } 1380 1381 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1382 { 1383 int i; 1384 struct mtk_rx_ring *ring; 1385 int idx; 1386 1387 if (!eth->hwlro) 1388 return ð->rx_ring[0]; 1389 1390 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1391 struct mtk_rx_dma *rxd; 1392 1393 ring = ð->rx_ring[i]; 1394 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1395 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1396 if (rxd->rxd2 & RX_DMA_DONE) { 1397 ring->calc_idx_update = true; 1398 return ring; 1399 } 1400 } 1401 1402 return NULL; 1403 } 1404 1405 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1406 { 1407 struct mtk_rx_ring *ring; 1408 int i; 1409 1410 if (!eth->hwlro) { 1411 ring = ð->rx_ring[0]; 1412 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1413 } else { 1414 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1415 ring = ð->rx_ring[i]; 1416 if (ring->calc_idx_update) { 1417 ring->calc_idx_update = false; 1418 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1419 } 1420 } 1421 } 1422 } 1423 1424 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1425 struct mtk_eth *eth) 1426 { 1427 struct dim_sample dim_sample = {}; 1428 struct mtk_rx_ring *ring; 1429 int idx; 1430 struct sk_buff *skb; 1431 u8 *data, *new_data; 1432 struct mtk_rx_dma_v2 *rxd, trxd; 1433 int done = 0, bytes = 0; 1434 1435 while (done < budget) { 1436 struct net_device *netdev; 1437 unsigned int pktlen; 1438 dma_addr_t dma_addr; 1439 u32 hash, reason; 1440 int mac = 0; 1441 1442 ring = mtk_get_rx_ring(eth); 1443 if (unlikely(!ring)) 1444 goto rx_done; 1445 1446 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1447 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1448 data = ring->data[idx]; 1449 1450 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1451 break; 1452 1453 /* find out which mac the packet come from. values start at 1 */ 1454 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1455 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1456 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1457 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1458 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1459 1460 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1461 !eth->netdev[mac])) 1462 goto release_desc; 1463 1464 netdev = eth->netdev[mac]; 1465 1466 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1467 goto release_desc; 1468 1469 /* alloc new buffer */ 1470 new_data = napi_alloc_frag(ring->frag_size); 1471 if (unlikely(!new_data)) { 1472 netdev->stats.rx_dropped++; 1473 goto release_desc; 1474 } 1475 dma_addr = dma_map_single(eth->dma_dev, 1476 new_data + NET_SKB_PAD + 1477 eth->ip_align, 1478 ring->buf_size, 1479 DMA_FROM_DEVICE); 1480 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) { 1481 skb_free_frag(new_data); 1482 netdev->stats.rx_dropped++; 1483 goto release_desc; 1484 } 1485 1486 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1487 ring->buf_size, DMA_FROM_DEVICE); 1488 1489 /* receive data */ 1490 skb = build_skb(data, ring->frag_size); 1491 if (unlikely(!skb)) { 1492 skb_free_frag(data); 1493 netdev->stats.rx_dropped++; 1494 goto skip_rx; 1495 } 1496 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1497 1498 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1499 skb->dev = netdev; 1500 skb_put(skb, pktlen); 1501 if (trxd.rxd4 & eth->soc->txrx.rx_dma_l4_valid) 1502 skb->ip_summed = CHECKSUM_UNNECESSARY; 1503 else 1504 skb_checksum_none_assert(skb); 1505 skb->protocol = eth_type_trans(skb, netdev); 1506 bytes += pktlen; 1507 1508 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1509 if (hash != MTK_RXD4_FOE_ENTRY) { 1510 hash = jhash_1word(hash, 0); 1511 skb_set_hash(skb, hash, PKT_HASH_TYPE_L4); 1512 } 1513 1514 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1515 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 1516 mtk_ppe_check_skb(eth->ppe, skb, 1517 trxd.rxd4 & MTK_RXD4_FOE_ENTRY); 1518 1519 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1520 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1521 if (trxd.rxd3 & RX_DMA_VTAG_V2) 1522 __vlan_hwaccel_put_tag(skb, 1523 htons(RX_DMA_VPID(trxd.rxd4)), 1524 RX_DMA_VID(trxd.rxd4)); 1525 } else if (trxd.rxd2 & RX_DMA_VTAG) { 1526 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1527 RX_DMA_VID(trxd.rxd3)); 1528 } 1529 1530 /* If the device is attached to a dsa switch, the special 1531 * tag inserted in VLAN field by hw switch can * be offloaded 1532 * by RX HW VLAN offload. Clear vlan info. 1533 */ 1534 if (netdev_uses_dsa(netdev)) 1535 __vlan_hwaccel_clear_tag(skb); 1536 } 1537 1538 skb_record_rx_queue(skb, 0); 1539 napi_gro_receive(napi, skb); 1540 1541 skip_rx: 1542 ring->data[idx] = new_data; 1543 rxd->rxd1 = (unsigned int)dma_addr; 1544 1545 release_desc: 1546 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1547 rxd->rxd2 = RX_DMA_LSO; 1548 else 1549 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 1550 1551 ring->calc_idx = idx; 1552 1553 done++; 1554 } 1555 1556 rx_done: 1557 if (done) { 1558 /* make sure that all changes to the dma ring are flushed before 1559 * we continue 1560 */ 1561 wmb(); 1562 mtk_update_rx_cpu_idx(eth); 1563 } 1564 1565 eth->rx_packets += done; 1566 eth->rx_bytes += bytes; 1567 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1568 &dim_sample); 1569 net_dim(ð->rx_dim, dim_sample); 1570 1571 return done; 1572 } 1573 1574 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1575 unsigned int *done, unsigned int *bytes) 1576 { 1577 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1578 struct mtk_tx_ring *ring = ð->tx_ring; 1579 struct mtk_tx_dma *desc; 1580 struct sk_buff *skb; 1581 struct mtk_tx_buf *tx_buf; 1582 u32 cpu, dma; 1583 1584 cpu = ring->last_free_ptr; 1585 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 1586 1587 desc = mtk_qdma_phys_to_virt(ring, cpu); 1588 1589 while ((cpu != dma) && budget) { 1590 u32 next_cpu = desc->txd2; 1591 int mac = 0; 1592 1593 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1594 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1595 break; 1596 1597 tx_buf = mtk_desc_to_tx_buf(ring, desc, 1598 eth->soc->txrx.txd_size); 1599 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1600 mac = 1; 1601 1602 skb = tx_buf->skb; 1603 if (!skb) 1604 break; 1605 1606 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1607 bytes[mac] += skb->len; 1608 done[mac]++; 1609 budget--; 1610 } 1611 mtk_tx_unmap(eth, tx_buf, true); 1612 1613 ring->last_free = desc; 1614 atomic_inc(&ring->free_count); 1615 1616 cpu = next_cpu; 1617 } 1618 1619 ring->last_free_ptr = cpu; 1620 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 1621 1622 return budget; 1623 } 1624 1625 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1626 unsigned int *done, unsigned int *bytes) 1627 { 1628 struct mtk_tx_ring *ring = ð->tx_ring; 1629 struct mtk_tx_dma *desc; 1630 struct sk_buff *skb; 1631 struct mtk_tx_buf *tx_buf; 1632 u32 cpu, dma; 1633 1634 cpu = ring->cpu_idx; 1635 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1636 1637 while ((cpu != dma) && budget) { 1638 tx_buf = &ring->buf[cpu]; 1639 skb = tx_buf->skb; 1640 if (!skb) 1641 break; 1642 1643 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1644 bytes[0] += skb->len; 1645 done[0]++; 1646 budget--; 1647 } 1648 1649 mtk_tx_unmap(eth, tx_buf, true); 1650 1651 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 1652 ring->last_free = desc; 1653 atomic_inc(&ring->free_count); 1654 1655 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1656 } 1657 1658 ring->cpu_idx = cpu; 1659 1660 return budget; 1661 } 1662 1663 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1664 { 1665 struct mtk_tx_ring *ring = ð->tx_ring; 1666 struct dim_sample dim_sample = {}; 1667 unsigned int done[MTK_MAX_DEVS]; 1668 unsigned int bytes[MTK_MAX_DEVS]; 1669 int total = 0, i; 1670 1671 memset(done, 0, sizeof(done)); 1672 memset(bytes, 0, sizeof(bytes)); 1673 1674 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1675 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1676 else 1677 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1678 1679 for (i = 0; i < MTK_MAC_COUNT; i++) { 1680 if (!eth->netdev[i] || !done[i]) 1681 continue; 1682 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1683 total += done[i]; 1684 eth->tx_packets += done[i]; 1685 eth->tx_bytes += bytes[i]; 1686 } 1687 1688 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 1689 &dim_sample); 1690 net_dim(ð->tx_dim, dim_sample); 1691 1692 if (mtk_queue_stopped(eth) && 1693 (atomic_read(&ring->free_count) > ring->thresh)) 1694 mtk_wake_queue(eth); 1695 1696 return total; 1697 } 1698 1699 static void mtk_handle_status_irq(struct mtk_eth *eth) 1700 { 1701 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1702 1703 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1704 mtk_stats_update(eth); 1705 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1706 MTK_INT_STATUS2); 1707 } 1708 } 1709 1710 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1711 { 1712 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1713 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1714 int tx_done = 0; 1715 1716 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1717 mtk_handle_status_irq(eth); 1718 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 1719 tx_done = mtk_poll_tx(eth, budget); 1720 1721 if (unlikely(netif_msg_intr(eth))) { 1722 dev_info(eth->dev, 1723 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 1724 mtk_r32(eth, reg_map->tx_irq_status), 1725 mtk_r32(eth, reg_map->tx_irq_mask)); 1726 } 1727 1728 if (tx_done == budget) 1729 return budget; 1730 1731 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 1732 return budget; 1733 1734 if (napi_complete_done(napi, tx_done)) 1735 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1736 1737 return tx_done; 1738 } 1739 1740 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1741 { 1742 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1743 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1744 int rx_done_total = 0; 1745 1746 mtk_handle_status_irq(eth); 1747 1748 do { 1749 int rx_done; 1750 1751 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 1752 reg_map->pdma.irq_status); 1753 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 1754 rx_done_total += rx_done; 1755 1756 if (unlikely(netif_msg_intr(eth))) { 1757 dev_info(eth->dev, 1758 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 1759 mtk_r32(eth, reg_map->pdma.irq_status), 1760 mtk_r32(eth, reg_map->pdma.irq_mask)); 1761 } 1762 1763 if (rx_done_total == budget) 1764 return budget; 1765 1766 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 1767 eth->soc->txrx.rx_irq_done_mask); 1768 1769 if (napi_complete_done(napi, rx_done_total)) 1770 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 1771 1772 return rx_done_total; 1773 } 1774 1775 static int mtk_tx_alloc(struct mtk_eth *eth) 1776 { 1777 const struct mtk_soc_data *soc = eth->soc; 1778 struct mtk_tx_ring *ring = ð->tx_ring; 1779 int i, sz = soc->txrx.txd_size; 1780 struct mtk_tx_dma_v2 *txd; 1781 1782 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1783 GFP_KERNEL); 1784 if (!ring->buf) 1785 goto no_tx_mem; 1786 1787 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 1788 &ring->phys, GFP_KERNEL); 1789 if (!ring->dma) 1790 goto no_tx_mem; 1791 1792 for (i = 0; i < MTK_DMA_SIZE; i++) { 1793 int next = (i + 1) % MTK_DMA_SIZE; 1794 u32 next_ptr = ring->phys + next * sz; 1795 1796 txd = ring->dma + i * sz; 1797 txd->txd2 = next_ptr; 1798 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1799 txd->txd4 = 0; 1800 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1801 txd->txd5 = 0; 1802 txd->txd6 = 0; 1803 txd->txd7 = 0; 1804 txd->txd8 = 0; 1805 } 1806 } 1807 1808 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1809 * only as the framework. The real HW descriptors are the PDMA 1810 * descriptors in ring->dma_pdma. 1811 */ 1812 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1813 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 1814 &ring->phys_pdma, GFP_KERNEL); 1815 if (!ring->dma_pdma) 1816 goto no_tx_mem; 1817 1818 for (i = 0; i < MTK_DMA_SIZE; i++) { 1819 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1820 ring->dma_pdma[i].txd4 = 0; 1821 } 1822 } 1823 1824 ring->dma_size = MTK_DMA_SIZE; 1825 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1826 ring->next_free = ring->dma; 1827 ring->last_free = (void *)txd; 1828 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 1829 ring->thresh = MAX_SKB_FRAGS; 1830 1831 /* make sure that all changes to the dma ring are flushed before we 1832 * continue 1833 */ 1834 wmb(); 1835 1836 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1837 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 1838 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 1839 mtk_w32(eth, 1840 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1841 soc->reg_map->qdma.crx_ptr); 1842 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 1843 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1844 soc->reg_map->qdma.qtx_cfg); 1845 } else { 1846 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1847 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1848 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1849 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 1850 } 1851 1852 return 0; 1853 1854 no_tx_mem: 1855 return -ENOMEM; 1856 } 1857 1858 static void mtk_tx_clean(struct mtk_eth *eth) 1859 { 1860 const struct mtk_soc_data *soc = eth->soc; 1861 struct mtk_tx_ring *ring = ð->tx_ring; 1862 int i; 1863 1864 if (ring->buf) { 1865 for (i = 0; i < MTK_DMA_SIZE; i++) 1866 mtk_tx_unmap(eth, &ring->buf[i], false); 1867 kfree(ring->buf); 1868 ring->buf = NULL; 1869 } 1870 1871 if (ring->dma) { 1872 dma_free_coherent(eth->dma_dev, 1873 MTK_DMA_SIZE * soc->txrx.txd_size, 1874 ring->dma, ring->phys); 1875 ring->dma = NULL; 1876 } 1877 1878 if (ring->dma_pdma) { 1879 dma_free_coherent(eth->dma_dev, 1880 MTK_DMA_SIZE * soc->txrx.txd_size, 1881 ring->dma_pdma, ring->phys_pdma); 1882 ring->dma_pdma = NULL; 1883 } 1884 } 1885 1886 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1887 { 1888 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1889 struct mtk_rx_ring *ring; 1890 int rx_data_len, rx_dma_size; 1891 int i; 1892 1893 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1894 if (ring_no) 1895 return -EINVAL; 1896 ring = ð->rx_ring_qdma; 1897 } else { 1898 ring = ð->rx_ring[ring_no]; 1899 } 1900 1901 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1902 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1903 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1904 } else { 1905 rx_data_len = ETH_DATA_LEN; 1906 rx_dma_size = MTK_DMA_SIZE; 1907 } 1908 1909 ring->frag_size = mtk_max_frag_size(rx_data_len); 1910 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1911 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1912 GFP_KERNEL); 1913 if (!ring->data) 1914 return -ENOMEM; 1915 1916 for (i = 0; i < rx_dma_size; i++) { 1917 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1918 if (!ring->data[i]) 1919 return -ENOMEM; 1920 } 1921 1922 ring->dma = dma_alloc_coherent(eth->dma_dev, 1923 rx_dma_size * eth->soc->txrx.rxd_size, 1924 &ring->phys, GFP_KERNEL); 1925 if (!ring->dma) 1926 return -ENOMEM; 1927 1928 for (i = 0; i < rx_dma_size; i++) { 1929 struct mtk_rx_dma_v2 *rxd; 1930 1931 dma_addr_t dma_addr = dma_map_single(eth->dma_dev, 1932 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1933 ring->buf_size, 1934 DMA_FROM_DEVICE); 1935 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1936 return -ENOMEM; 1937 1938 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 1939 rxd->rxd1 = (unsigned int)dma_addr; 1940 1941 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1942 rxd->rxd2 = RX_DMA_LSO; 1943 else 1944 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 1945 1946 rxd->rxd3 = 0; 1947 rxd->rxd4 = 0; 1948 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1949 rxd->rxd5 = 0; 1950 rxd->rxd6 = 0; 1951 rxd->rxd7 = 0; 1952 rxd->rxd8 = 0; 1953 } 1954 } 1955 ring->dma_size = rx_dma_size; 1956 ring->calc_idx_update = false; 1957 ring->calc_idx = rx_dma_size - 1; 1958 if (rx_flag == MTK_RX_FLAGS_QDMA) 1959 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 1960 ring_no * MTK_QRX_OFFSET; 1961 else 1962 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 1963 ring_no * MTK_QRX_OFFSET; 1964 /* make sure that all changes to the dma ring are flushed before we 1965 * continue 1966 */ 1967 wmb(); 1968 1969 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1970 mtk_w32(eth, ring->phys, 1971 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 1972 mtk_w32(eth, rx_dma_size, 1973 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 1974 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 1975 reg_map->qdma.rst_idx); 1976 } else { 1977 mtk_w32(eth, ring->phys, 1978 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 1979 mtk_w32(eth, rx_dma_size, 1980 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 1981 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 1982 reg_map->pdma.rst_idx); 1983 } 1984 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1985 1986 return 0; 1987 } 1988 1989 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1990 { 1991 int i; 1992 1993 if (ring->data && ring->dma) { 1994 for (i = 0; i < ring->dma_size; i++) { 1995 struct mtk_rx_dma *rxd; 1996 1997 if (!ring->data[i]) 1998 continue; 1999 2000 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2001 if (!rxd->rxd1) 2002 continue; 2003 2004 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2005 ring->buf_size, DMA_FROM_DEVICE); 2006 skb_free_frag(ring->data[i]); 2007 } 2008 kfree(ring->data); 2009 ring->data = NULL; 2010 } 2011 2012 if (ring->dma) { 2013 dma_free_coherent(eth->dma_dev, 2014 ring->dma_size * eth->soc->txrx.rxd_size, 2015 ring->dma, ring->phys); 2016 ring->dma = NULL; 2017 } 2018 } 2019 2020 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2021 { 2022 int i; 2023 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2024 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2025 2026 /* set LRO rings to auto-learn modes */ 2027 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2028 2029 /* validate LRO ring */ 2030 ring_ctrl_dw2 |= MTK_RING_VLD; 2031 2032 /* set AGE timer (unit: 20us) */ 2033 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2034 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2035 2036 /* set max AGG timer (unit: 20us) */ 2037 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2038 2039 /* set max LRO AGG count */ 2040 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2041 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2042 2043 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2044 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2045 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2046 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2047 } 2048 2049 /* IPv4 checksum update enable */ 2050 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2051 2052 /* switch priority comparison to packet count mode */ 2053 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2054 2055 /* bandwidth threshold setting */ 2056 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2057 2058 /* auto-learn score delta setting */ 2059 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2060 2061 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2062 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2063 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2064 2065 /* set HW LRO mode & the max aggregation count for rx packets */ 2066 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2067 2068 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2069 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2070 2071 /* enable HW LRO */ 2072 lro_ctrl_dw0 |= MTK_LRO_EN; 2073 2074 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2075 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2076 2077 return 0; 2078 } 2079 2080 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2081 { 2082 int i; 2083 u32 val; 2084 2085 /* relinquish lro rings, flush aggregated packets */ 2086 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2087 2088 /* wait for relinquishments done */ 2089 for (i = 0; i < 10; i++) { 2090 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2091 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2092 msleep(20); 2093 continue; 2094 } 2095 break; 2096 } 2097 2098 /* invalidate lro rings */ 2099 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2100 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2101 2102 /* disable HW LRO */ 2103 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2104 } 2105 2106 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2107 { 2108 u32 reg_val; 2109 2110 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2111 2112 /* invalidate the IP setting */ 2113 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2114 2115 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2116 2117 /* validate the IP setting */ 2118 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2119 } 2120 2121 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2122 { 2123 u32 reg_val; 2124 2125 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2126 2127 /* invalidate the IP setting */ 2128 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2129 2130 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2131 } 2132 2133 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2134 { 2135 int cnt = 0; 2136 int i; 2137 2138 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2139 if (mac->hwlro_ip[i]) 2140 cnt++; 2141 } 2142 2143 return cnt; 2144 } 2145 2146 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2147 struct ethtool_rxnfc *cmd) 2148 { 2149 struct ethtool_rx_flow_spec *fsp = 2150 (struct ethtool_rx_flow_spec *)&cmd->fs; 2151 struct mtk_mac *mac = netdev_priv(dev); 2152 struct mtk_eth *eth = mac->hw; 2153 int hwlro_idx; 2154 2155 if ((fsp->flow_type != TCP_V4_FLOW) || 2156 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2157 (fsp->location > 1)) 2158 return -EINVAL; 2159 2160 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2161 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2162 2163 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2164 2165 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2166 2167 return 0; 2168 } 2169 2170 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2171 struct ethtool_rxnfc *cmd) 2172 { 2173 struct ethtool_rx_flow_spec *fsp = 2174 (struct ethtool_rx_flow_spec *)&cmd->fs; 2175 struct mtk_mac *mac = netdev_priv(dev); 2176 struct mtk_eth *eth = mac->hw; 2177 int hwlro_idx; 2178 2179 if (fsp->location > 1) 2180 return -EINVAL; 2181 2182 mac->hwlro_ip[fsp->location] = 0; 2183 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2184 2185 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2186 2187 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2188 2189 return 0; 2190 } 2191 2192 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2193 { 2194 struct mtk_mac *mac = netdev_priv(dev); 2195 struct mtk_eth *eth = mac->hw; 2196 int i, hwlro_idx; 2197 2198 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2199 mac->hwlro_ip[i] = 0; 2200 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2201 2202 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2203 } 2204 2205 mac->hwlro_ip_cnt = 0; 2206 } 2207 2208 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2209 struct ethtool_rxnfc *cmd) 2210 { 2211 struct mtk_mac *mac = netdev_priv(dev); 2212 struct ethtool_rx_flow_spec *fsp = 2213 (struct ethtool_rx_flow_spec *)&cmd->fs; 2214 2215 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2216 return -EINVAL; 2217 2218 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2219 fsp->flow_type = TCP_V4_FLOW; 2220 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2221 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2222 2223 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2224 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2225 fsp->h_u.tcp_ip4_spec.psrc = 0; 2226 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2227 fsp->h_u.tcp_ip4_spec.pdst = 0; 2228 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2229 fsp->h_u.tcp_ip4_spec.tos = 0; 2230 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2231 2232 return 0; 2233 } 2234 2235 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2236 struct ethtool_rxnfc *cmd, 2237 u32 *rule_locs) 2238 { 2239 struct mtk_mac *mac = netdev_priv(dev); 2240 int cnt = 0; 2241 int i; 2242 2243 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2244 if (mac->hwlro_ip[i]) { 2245 rule_locs[cnt] = i; 2246 cnt++; 2247 } 2248 } 2249 2250 cmd->rule_cnt = cnt; 2251 2252 return 0; 2253 } 2254 2255 static netdev_features_t mtk_fix_features(struct net_device *dev, 2256 netdev_features_t features) 2257 { 2258 if (!(features & NETIF_F_LRO)) { 2259 struct mtk_mac *mac = netdev_priv(dev); 2260 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2261 2262 if (ip_cnt) { 2263 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2264 2265 features |= NETIF_F_LRO; 2266 } 2267 } 2268 2269 return features; 2270 } 2271 2272 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2273 { 2274 int err = 0; 2275 2276 if (!((dev->features ^ features) & NETIF_F_LRO)) 2277 return 0; 2278 2279 if (!(features & NETIF_F_LRO)) 2280 mtk_hwlro_netdev_disable(dev); 2281 2282 return err; 2283 } 2284 2285 /* wait for DMA to finish whatever it is doing before we start using it again */ 2286 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2287 { 2288 unsigned int reg; 2289 int ret; 2290 u32 val; 2291 2292 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2293 reg = eth->soc->reg_map->qdma.glo_cfg; 2294 else 2295 reg = eth->soc->reg_map->pdma.glo_cfg; 2296 2297 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2298 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2299 5, MTK_DMA_BUSY_TIMEOUT_US); 2300 if (ret) 2301 dev_err(eth->dev, "DMA init timeout\n"); 2302 2303 return ret; 2304 } 2305 2306 static int mtk_dma_init(struct mtk_eth *eth) 2307 { 2308 int err; 2309 u32 i; 2310 2311 if (mtk_dma_busy_wait(eth)) 2312 return -EBUSY; 2313 2314 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2315 /* QDMA needs scratch memory for internal reordering of the 2316 * descriptors 2317 */ 2318 err = mtk_init_fq_dma(eth); 2319 if (err) 2320 return err; 2321 } 2322 2323 err = mtk_tx_alloc(eth); 2324 if (err) 2325 return err; 2326 2327 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2328 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2329 if (err) 2330 return err; 2331 } 2332 2333 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2334 if (err) 2335 return err; 2336 2337 if (eth->hwlro) { 2338 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2339 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2340 if (err) 2341 return err; 2342 } 2343 err = mtk_hwlro_rx_init(eth); 2344 if (err) 2345 return err; 2346 } 2347 2348 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2349 /* Enable random early drop and set drop threshold 2350 * automatically 2351 */ 2352 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2353 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2354 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2355 } 2356 2357 return 0; 2358 } 2359 2360 static void mtk_dma_free(struct mtk_eth *eth) 2361 { 2362 const struct mtk_soc_data *soc = eth->soc; 2363 int i; 2364 2365 for (i = 0; i < MTK_MAC_COUNT; i++) 2366 if (eth->netdev[i]) 2367 netdev_reset_queue(eth->netdev[i]); 2368 if (eth->scratch_ring) { 2369 dma_free_coherent(eth->dma_dev, 2370 MTK_DMA_SIZE * soc->txrx.txd_size, 2371 eth->scratch_ring, eth->phy_scratch_ring); 2372 eth->scratch_ring = NULL; 2373 eth->phy_scratch_ring = 0; 2374 } 2375 mtk_tx_clean(eth); 2376 mtk_rx_clean(eth, ð->rx_ring[0]); 2377 mtk_rx_clean(eth, ð->rx_ring_qdma); 2378 2379 if (eth->hwlro) { 2380 mtk_hwlro_rx_uninit(eth); 2381 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2382 mtk_rx_clean(eth, ð->rx_ring[i]); 2383 } 2384 2385 kfree(eth->scratch_head); 2386 } 2387 2388 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2389 { 2390 struct mtk_mac *mac = netdev_priv(dev); 2391 struct mtk_eth *eth = mac->hw; 2392 2393 eth->netdev[mac->id]->stats.tx_errors++; 2394 netif_err(eth, tx_err, dev, 2395 "transmit timed out\n"); 2396 schedule_work(ð->pending_work); 2397 } 2398 2399 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2400 { 2401 struct mtk_eth *eth = _eth; 2402 2403 eth->rx_events++; 2404 if (likely(napi_schedule_prep(ð->rx_napi))) { 2405 __napi_schedule(ð->rx_napi); 2406 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2407 } 2408 2409 return IRQ_HANDLED; 2410 } 2411 2412 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2413 { 2414 struct mtk_eth *eth = _eth; 2415 2416 eth->tx_events++; 2417 if (likely(napi_schedule_prep(ð->tx_napi))) { 2418 __napi_schedule(ð->tx_napi); 2419 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2420 } 2421 2422 return IRQ_HANDLED; 2423 } 2424 2425 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2426 { 2427 struct mtk_eth *eth = _eth; 2428 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2429 2430 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 2431 eth->soc->txrx.rx_irq_done_mask) { 2432 if (mtk_r32(eth, reg_map->pdma.irq_status) & 2433 eth->soc->txrx.rx_irq_done_mask) 2434 mtk_handle_irq_rx(irq, _eth); 2435 } 2436 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 2437 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2438 mtk_handle_irq_tx(irq, _eth); 2439 } 2440 2441 return IRQ_HANDLED; 2442 } 2443 2444 #ifdef CONFIG_NET_POLL_CONTROLLER 2445 static void mtk_poll_controller(struct net_device *dev) 2446 { 2447 struct mtk_mac *mac = netdev_priv(dev); 2448 struct mtk_eth *eth = mac->hw; 2449 2450 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2451 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2452 mtk_handle_irq_rx(eth->irq[2], dev); 2453 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2454 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2455 } 2456 #endif 2457 2458 static int mtk_start_dma(struct mtk_eth *eth) 2459 { 2460 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2461 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2462 int err; 2463 2464 err = mtk_dma_init(eth); 2465 if (err) { 2466 mtk_dma_free(eth); 2467 return err; 2468 } 2469 2470 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2471 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 2472 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2473 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2474 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 2475 2476 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2477 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 2478 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 2479 MTK_CHK_DDONE_EN; 2480 else 2481 val |= MTK_RX_BT_32DWORDS; 2482 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 2483 2484 mtk_w32(eth, 2485 MTK_RX_DMA_EN | rx_2b_offset | 2486 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2487 reg_map->pdma.glo_cfg); 2488 } else { 2489 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2490 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2491 reg_map->pdma.glo_cfg); 2492 } 2493 2494 return 0; 2495 } 2496 2497 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2498 { 2499 int i; 2500 2501 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2502 return; 2503 2504 for (i = 0; i < MTK_MAC_COUNT; i++) { 2505 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2506 2507 /* default setup the forward port to send frame to PDMA */ 2508 val &= ~0xffff; 2509 2510 /* Enable RX checksum */ 2511 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2512 2513 val |= config; 2514 2515 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2516 val |= MTK_GDMA_SPECIAL_TAG; 2517 2518 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2519 } 2520 /* Reset and enable PSE */ 2521 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2522 mtk_w32(eth, 0, MTK_RST_GL); 2523 } 2524 2525 static int mtk_open(struct net_device *dev) 2526 { 2527 struct mtk_mac *mac = netdev_priv(dev); 2528 struct mtk_eth *eth = mac->hw; 2529 int err; 2530 2531 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2532 if (err) { 2533 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2534 err); 2535 return err; 2536 } 2537 2538 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2539 if (!refcount_read(ð->dma_refcnt)) { 2540 u32 gdm_config = MTK_GDMA_TO_PDMA; 2541 2542 err = mtk_start_dma(eth); 2543 if (err) 2544 return err; 2545 2546 if (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0) 2547 gdm_config = MTK_GDMA_TO_PPE; 2548 2549 mtk_gdm_config(eth, gdm_config); 2550 2551 napi_enable(ð->tx_napi); 2552 napi_enable(ð->rx_napi); 2553 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2554 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2555 refcount_set(ð->dma_refcnt, 1); 2556 } 2557 else 2558 refcount_inc(ð->dma_refcnt); 2559 2560 phylink_start(mac->phylink); 2561 netif_start_queue(dev); 2562 return 0; 2563 } 2564 2565 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2566 { 2567 u32 val; 2568 int i; 2569 2570 /* stop the dma engine */ 2571 spin_lock_bh(ð->page_lock); 2572 val = mtk_r32(eth, glo_cfg); 2573 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2574 glo_cfg); 2575 spin_unlock_bh(ð->page_lock); 2576 2577 /* wait for dma stop */ 2578 for (i = 0; i < 10; i++) { 2579 val = mtk_r32(eth, glo_cfg); 2580 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2581 msleep(20); 2582 continue; 2583 } 2584 break; 2585 } 2586 } 2587 2588 static int mtk_stop(struct net_device *dev) 2589 { 2590 struct mtk_mac *mac = netdev_priv(dev); 2591 struct mtk_eth *eth = mac->hw; 2592 2593 phylink_stop(mac->phylink); 2594 2595 netif_tx_disable(dev); 2596 2597 phylink_disconnect_phy(mac->phylink); 2598 2599 /* only shutdown DMA if this is the last user */ 2600 if (!refcount_dec_and_test(ð->dma_refcnt)) 2601 return 0; 2602 2603 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2604 2605 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2606 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2607 napi_disable(ð->tx_napi); 2608 napi_disable(ð->rx_napi); 2609 2610 cancel_work_sync(ð->rx_dim.work); 2611 cancel_work_sync(ð->tx_dim.work); 2612 2613 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2614 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 2615 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 2616 2617 mtk_dma_free(eth); 2618 2619 if (eth->soc->offload_version) 2620 mtk_ppe_stop(eth->ppe); 2621 2622 return 0; 2623 } 2624 2625 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2626 { 2627 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2628 reset_bits, 2629 reset_bits); 2630 2631 usleep_range(1000, 1100); 2632 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2633 reset_bits, 2634 ~reset_bits); 2635 mdelay(10); 2636 } 2637 2638 static void mtk_clk_disable(struct mtk_eth *eth) 2639 { 2640 int clk; 2641 2642 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2643 clk_disable_unprepare(eth->clks[clk]); 2644 } 2645 2646 static int mtk_clk_enable(struct mtk_eth *eth) 2647 { 2648 int clk, ret; 2649 2650 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2651 ret = clk_prepare_enable(eth->clks[clk]); 2652 if (ret) 2653 goto err_disable_clks; 2654 } 2655 2656 return 0; 2657 2658 err_disable_clks: 2659 while (--clk >= 0) 2660 clk_disable_unprepare(eth->clks[clk]); 2661 2662 return ret; 2663 } 2664 2665 static void mtk_dim_rx(struct work_struct *work) 2666 { 2667 struct dim *dim = container_of(work, struct dim, work); 2668 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 2669 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2670 struct dim_cq_moder cur_profile; 2671 u32 val, cur; 2672 2673 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 2674 dim->profile_ix); 2675 spin_lock_bh(ð->dim_lock); 2676 2677 val = mtk_r32(eth, reg_map->pdma.delay_irq); 2678 val &= MTK_PDMA_DELAY_TX_MASK; 2679 val |= MTK_PDMA_DELAY_RX_EN; 2680 2681 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2682 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 2683 2684 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2685 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 2686 2687 mtk_w32(eth, val, reg_map->pdma.delay_irq); 2688 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2689 mtk_w32(eth, val, reg_map->qdma.delay_irq); 2690 2691 spin_unlock_bh(ð->dim_lock); 2692 2693 dim->state = DIM_START_MEASURE; 2694 } 2695 2696 static void mtk_dim_tx(struct work_struct *work) 2697 { 2698 struct dim *dim = container_of(work, struct dim, work); 2699 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 2700 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2701 struct dim_cq_moder cur_profile; 2702 u32 val, cur; 2703 2704 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 2705 dim->profile_ix); 2706 spin_lock_bh(ð->dim_lock); 2707 2708 val = mtk_r32(eth, reg_map->pdma.delay_irq); 2709 val &= MTK_PDMA_DELAY_RX_MASK; 2710 val |= MTK_PDMA_DELAY_TX_EN; 2711 2712 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 2713 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 2714 2715 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 2716 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 2717 2718 mtk_w32(eth, val, reg_map->pdma.delay_irq); 2719 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2720 mtk_w32(eth, val, reg_map->qdma.delay_irq); 2721 2722 spin_unlock_bh(ð->dim_lock); 2723 2724 dim->state = DIM_START_MEASURE; 2725 } 2726 2727 static int mtk_hw_init(struct mtk_eth *eth) 2728 { 2729 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 2730 ETHSYS_DMA_AG_MAP_PPE; 2731 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2732 int i, val, ret; 2733 2734 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2735 return 0; 2736 2737 pm_runtime_enable(eth->dev); 2738 pm_runtime_get_sync(eth->dev); 2739 2740 ret = mtk_clk_enable(eth); 2741 if (ret) 2742 goto err_disable_pm; 2743 2744 if (eth->ethsys) 2745 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 2746 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 2747 2748 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2749 ret = device_reset(eth->dev); 2750 if (ret) { 2751 dev_err(eth->dev, "MAC reset failed!\n"); 2752 goto err_disable_pm; 2753 } 2754 2755 /* set interrupt delays based on current Net DIM sample */ 2756 mtk_dim_rx(ð->rx_dim.work); 2757 mtk_dim_tx(ð->tx_dim.work); 2758 2759 /* disable delay and normal interrupt */ 2760 mtk_tx_irq_disable(eth, ~0); 2761 mtk_rx_irq_disable(eth, ~0); 2762 2763 return 0; 2764 } 2765 2766 val = RSTCTRL_FE | RSTCTRL_PPE; 2767 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2768 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 2769 2770 val |= RSTCTRL_ETH; 2771 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 2772 val |= RSTCTRL_PPE1; 2773 } 2774 2775 ethsys_reset(eth, val); 2776 2777 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2778 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 2779 0x3ffffff); 2780 2781 /* Set FE to PDMAv2 if necessary */ 2782 val = mtk_r32(eth, MTK_FE_GLO_MISC); 2783 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 2784 } 2785 2786 if (eth->pctl) { 2787 /* Set GE2 driving and slew rate */ 2788 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2789 2790 /* set GE2 TDSEL */ 2791 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2792 2793 /* set GE2 TUNE */ 2794 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2795 } 2796 2797 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2798 * up with the more appropriate value when mtk_mac_config call is being 2799 * invoked. 2800 */ 2801 for (i = 0; i < MTK_MAC_COUNT; i++) 2802 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2803 2804 /* Indicates CDM to parse the MTK special tag from CPU 2805 * which also is working out for untag packets. 2806 */ 2807 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2808 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2809 2810 /* Enable RX VLan Offloading */ 2811 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2812 2813 /* set interrupt delays based on current Net DIM sample */ 2814 mtk_dim_rx(ð->rx_dim.work); 2815 mtk_dim_tx(ð->tx_dim.work); 2816 2817 /* disable delay and normal interrupt */ 2818 mtk_tx_irq_disable(eth, ~0); 2819 mtk_rx_irq_disable(eth, ~0); 2820 2821 /* FE int grouping */ 2822 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 2823 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 2824 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 2825 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 2826 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2827 2828 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2829 /* PSE should not drop port8 and port9 packets */ 2830 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 2831 2832 /* PSE Free Queue Flow Control */ 2833 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 2834 2835 /* PSE config input queue threshold */ 2836 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 2837 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 2838 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 2839 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 2840 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 2841 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 2842 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 2843 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 2844 2845 /* PSE config output queue threshold */ 2846 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 2847 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 2848 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 2849 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 2850 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 2851 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 2852 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 2853 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 2854 2855 /* GDM and CDM Threshold */ 2856 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 2857 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 2858 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 2859 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 2860 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 2861 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 2862 } 2863 2864 return 0; 2865 2866 err_disable_pm: 2867 pm_runtime_put_sync(eth->dev); 2868 pm_runtime_disable(eth->dev); 2869 2870 return ret; 2871 } 2872 2873 static int mtk_hw_deinit(struct mtk_eth *eth) 2874 { 2875 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2876 return 0; 2877 2878 mtk_clk_disable(eth); 2879 2880 pm_runtime_put_sync(eth->dev); 2881 pm_runtime_disable(eth->dev); 2882 2883 return 0; 2884 } 2885 2886 static int __init mtk_init(struct net_device *dev) 2887 { 2888 struct mtk_mac *mac = netdev_priv(dev); 2889 struct mtk_eth *eth = mac->hw; 2890 int ret; 2891 2892 ret = of_get_ethdev_address(mac->of_node, dev); 2893 if (ret) { 2894 /* If the mac address is invalid, use random mac address */ 2895 eth_hw_addr_random(dev); 2896 dev_err(eth->dev, "generated random MAC address %pM\n", 2897 dev->dev_addr); 2898 } 2899 2900 return 0; 2901 } 2902 2903 static void mtk_uninit(struct net_device *dev) 2904 { 2905 struct mtk_mac *mac = netdev_priv(dev); 2906 struct mtk_eth *eth = mac->hw; 2907 2908 phylink_disconnect_phy(mac->phylink); 2909 mtk_tx_irq_disable(eth, ~0); 2910 mtk_rx_irq_disable(eth, ~0); 2911 } 2912 2913 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 2914 { 2915 int length = new_mtu + MTK_RX_ETH_HLEN; 2916 struct mtk_mac *mac = netdev_priv(dev); 2917 struct mtk_eth *eth = mac->hw; 2918 u32 mcr_cur, mcr_new; 2919 2920 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2921 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 2922 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 2923 2924 if (length <= 1518) 2925 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 2926 else if (length <= 1536) 2927 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 2928 else if (length <= 1552) 2929 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 2930 else 2931 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 2932 2933 if (mcr_new != mcr_cur) 2934 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 2935 } 2936 2937 dev->mtu = new_mtu; 2938 2939 return 0; 2940 } 2941 2942 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2943 { 2944 struct mtk_mac *mac = netdev_priv(dev); 2945 2946 switch (cmd) { 2947 case SIOCGMIIPHY: 2948 case SIOCGMIIREG: 2949 case SIOCSMIIREG: 2950 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2951 default: 2952 break; 2953 } 2954 2955 return -EOPNOTSUPP; 2956 } 2957 2958 static void mtk_pending_work(struct work_struct *work) 2959 { 2960 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2961 int err, i; 2962 unsigned long restart = 0; 2963 2964 rtnl_lock(); 2965 2966 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2967 2968 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2969 cpu_relax(); 2970 2971 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2972 /* stop all devices to make sure that dma is properly shut down */ 2973 for (i = 0; i < MTK_MAC_COUNT; i++) { 2974 if (!eth->netdev[i]) 2975 continue; 2976 mtk_stop(eth->netdev[i]); 2977 __set_bit(i, &restart); 2978 } 2979 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2980 2981 /* restart underlying hardware such as power, clock, pin mux 2982 * and the connected phy 2983 */ 2984 mtk_hw_deinit(eth); 2985 2986 if (eth->dev->pins) 2987 pinctrl_select_state(eth->dev->pins->p, 2988 eth->dev->pins->default_state); 2989 mtk_hw_init(eth); 2990 2991 /* restart DMA and enable IRQs */ 2992 for (i = 0; i < MTK_MAC_COUNT; i++) { 2993 if (!test_bit(i, &restart)) 2994 continue; 2995 err = mtk_open(eth->netdev[i]); 2996 if (err) { 2997 netif_alert(eth, ifup, eth->netdev[i], 2998 "Driver up/down cycle failed, closing device.\n"); 2999 dev_close(eth->netdev[i]); 3000 } 3001 } 3002 3003 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 3004 3005 clear_bit_unlock(MTK_RESETTING, ð->state); 3006 3007 rtnl_unlock(); 3008 } 3009 3010 static int mtk_free_dev(struct mtk_eth *eth) 3011 { 3012 int i; 3013 3014 for (i = 0; i < MTK_MAC_COUNT; i++) { 3015 if (!eth->netdev[i]) 3016 continue; 3017 free_netdev(eth->netdev[i]); 3018 } 3019 3020 return 0; 3021 } 3022 3023 static int mtk_unreg_dev(struct mtk_eth *eth) 3024 { 3025 int i; 3026 3027 for (i = 0; i < MTK_MAC_COUNT; i++) { 3028 if (!eth->netdev[i]) 3029 continue; 3030 unregister_netdev(eth->netdev[i]); 3031 } 3032 3033 return 0; 3034 } 3035 3036 static int mtk_cleanup(struct mtk_eth *eth) 3037 { 3038 mtk_unreg_dev(eth); 3039 mtk_free_dev(eth); 3040 cancel_work_sync(ð->pending_work); 3041 3042 return 0; 3043 } 3044 3045 static int mtk_get_link_ksettings(struct net_device *ndev, 3046 struct ethtool_link_ksettings *cmd) 3047 { 3048 struct mtk_mac *mac = netdev_priv(ndev); 3049 3050 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3051 return -EBUSY; 3052 3053 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 3054 } 3055 3056 static int mtk_set_link_ksettings(struct net_device *ndev, 3057 const struct ethtool_link_ksettings *cmd) 3058 { 3059 struct mtk_mac *mac = netdev_priv(ndev); 3060 3061 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3062 return -EBUSY; 3063 3064 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 3065 } 3066 3067 static void mtk_get_drvinfo(struct net_device *dev, 3068 struct ethtool_drvinfo *info) 3069 { 3070 struct mtk_mac *mac = netdev_priv(dev); 3071 3072 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 3073 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 3074 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 3075 } 3076 3077 static u32 mtk_get_msglevel(struct net_device *dev) 3078 { 3079 struct mtk_mac *mac = netdev_priv(dev); 3080 3081 return mac->hw->msg_enable; 3082 } 3083 3084 static void mtk_set_msglevel(struct net_device *dev, u32 value) 3085 { 3086 struct mtk_mac *mac = netdev_priv(dev); 3087 3088 mac->hw->msg_enable = value; 3089 } 3090 3091 static int mtk_nway_reset(struct net_device *dev) 3092 { 3093 struct mtk_mac *mac = netdev_priv(dev); 3094 3095 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3096 return -EBUSY; 3097 3098 if (!mac->phylink) 3099 return -ENOTSUPP; 3100 3101 return phylink_ethtool_nway_reset(mac->phylink); 3102 } 3103 3104 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3105 { 3106 int i; 3107 3108 switch (stringset) { 3109 case ETH_SS_STATS: 3110 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 3111 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 3112 data += ETH_GSTRING_LEN; 3113 } 3114 break; 3115 } 3116 } 3117 3118 static int mtk_get_sset_count(struct net_device *dev, int sset) 3119 { 3120 switch (sset) { 3121 case ETH_SS_STATS: 3122 return ARRAY_SIZE(mtk_ethtool_stats); 3123 default: 3124 return -EOPNOTSUPP; 3125 } 3126 } 3127 3128 static void mtk_get_ethtool_stats(struct net_device *dev, 3129 struct ethtool_stats *stats, u64 *data) 3130 { 3131 struct mtk_mac *mac = netdev_priv(dev); 3132 struct mtk_hw_stats *hwstats = mac->hw_stats; 3133 u64 *data_src, *data_dst; 3134 unsigned int start; 3135 int i; 3136 3137 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3138 return; 3139 3140 if (netif_running(dev) && netif_device_present(dev)) { 3141 if (spin_trylock_bh(&hwstats->stats_lock)) { 3142 mtk_stats_update_mac(mac); 3143 spin_unlock_bh(&hwstats->stats_lock); 3144 } 3145 } 3146 3147 data_src = (u64 *)hwstats; 3148 3149 do { 3150 data_dst = data; 3151 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 3152 3153 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 3154 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 3155 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 3156 } 3157 3158 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 3159 u32 *rule_locs) 3160 { 3161 int ret = -EOPNOTSUPP; 3162 3163 switch (cmd->cmd) { 3164 case ETHTOOL_GRXRINGS: 3165 if (dev->hw_features & NETIF_F_LRO) { 3166 cmd->data = MTK_MAX_RX_RING_NUM; 3167 ret = 0; 3168 } 3169 break; 3170 case ETHTOOL_GRXCLSRLCNT: 3171 if (dev->hw_features & NETIF_F_LRO) { 3172 struct mtk_mac *mac = netdev_priv(dev); 3173 3174 cmd->rule_cnt = mac->hwlro_ip_cnt; 3175 ret = 0; 3176 } 3177 break; 3178 case ETHTOOL_GRXCLSRULE: 3179 if (dev->hw_features & NETIF_F_LRO) 3180 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 3181 break; 3182 case ETHTOOL_GRXCLSRLALL: 3183 if (dev->hw_features & NETIF_F_LRO) 3184 ret = mtk_hwlro_get_fdir_all(dev, cmd, 3185 rule_locs); 3186 break; 3187 default: 3188 break; 3189 } 3190 3191 return ret; 3192 } 3193 3194 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3195 { 3196 int ret = -EOPNOTSUPP; 3197 3198 switch (cmd->cmd) { 3199 case ETHTOOL_SRXCLSRLINS: 3200 if (dev->hw_features & NETIF_F_LRO) 3201 ret = mtk_hwlro_add_ipaddr(dev, cmd); 3202 break; 3203 case ETHTOOL_SRXCLSRLDEL: 3204 if (dev->hw_features & NETIF_F_LRO) 3205 ret = mtk_hwlro_del_ipaddr(dev, cmd); 3206 break; 3207 default: 3208 break; 3209 } 3210 3211 return ret; 3212 } 3213 3214 static const struct ethtool_ops mtk_ethtool_ops = { 3215 .get_link_ksettings = mtk_get_link_ksettings, 3216 .set_link_ksettings = mtk_set_link_ksettings, 3217 .get_drvinfo = mtk_get_drvinfo, 3218 .get_msglevel = mtk_get_msglevel, 3219 .set_msglevel = mtk_set_msglevel, 3220 .nway_reset = mtk_nway_reset, 3221 .get_link = ethtool_op_get_link, 3222 .get_strings = mtk_get_strings, 3223 .get_sset_count = mtk_get_sset_count, 3224 .get_ethtool_stats = mtk_get_ethtool_stats, 3225 .get_rxnfc = mtk_get_rxnfc, 3226 .set_rxnfc = mtk_set_rxnfc, 3227 }; 3228 3229 static const struct net_device_ops mtk_netdev_ops = { 3230 .ndo_init = mtk_init, 3231 .ndo_uninit = mtk_uninit, 3232 .ndo_open = mtk_open, 3233 .ndo_stop = mtk_stop, 3234 .ndo_start_xmit = mtk_start_xmit, 3235 .ndo_set_mac_address = mtk_set_mac_address, 3236 .ndo_validate_addr = eth_validate_addr, 3237 .ndo_eth_ioctl = mtk_do_ioctl, 3238 .ndo_change_mtu = mtk_change_mtu, 3239 .ndo_tx_timeout = mtk_tx_timeout, 3240 .ndo_get_stats64 = mtk_get_stats64, 3241 .ndo_fix_features = mtk_fix_features, 3242 .ndo_set_features = mtk_set_features, 3243 #ifdef CONFIG_NET_POLL_CONTROLLER 3244 .ndo_poll_controller = mtk_poll_controller, 3245 #endif 3246 .ndo_setup_tc = mtk_eth_setup_tc, 3247 }; 3248 3249 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 3250 { 3251 const __be32 *_id = of_get_property(np, "reg", NULL); 3252 phy_interface_t phy_mode; 3253 struct phylink *phylink; 3254 struct mtk_mac *mac; 3255 int id, err; 3256 3257 if (!_id) { 3258 dev_err(eth->dev, "missing mac id\n"); 3259 return -EINVAL; 3260 } 3261 3262 id = be32_to_cpup(_id); 3263 if (id >= MTK_MAC_COUNT) { 3264 dev_err(eth->dev, "%d is not a valid mac id\n", id); 3265 return -EINVAL; 3266 } 3267 3268 if (eth->netdev[id]) { 3269 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 3270 return -EINVAL; 3271 } 3272 3273 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 3274 if (!eth->netdev[id]) { 3275 dev_err(eth->dev, "alloc_etherdev failed\n"); 3276 return -ENOMEM; 3277 } 3278 mac = netdev_priv(eth->netdev[id]); 3279 eth->mac[id] = mac; 3280 mac->id = id; 3281 mac->hw = eth; 3282 mac->of_node = np; 3283 3284 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 3285 mac->hwlro_ip_cnt = 0; 3286 3287 mac->hw_stats = devm_kzalloc(eth->dev, 3288 sizeof(*mac->hw_stats), 3289 GFP_KERNEL); 3290 if (!mac->hw_stats) { 3291 dev_err(eth->dev, "failed to allocate counter memory\n"); 3292 err = -ENOMEM; 3293 goto free_netdev; 3294 } 3295 spin_lock_init(&mac->hw_stats->stats_lock); 3296 u64_stats_init(&mac->hw_stats->syncp); 3297 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 3298 3299 /* phylink create */ 3300 err = of_get_phy_mode(np, &phy_mode); 3301 if (err) { 3302 dev_err(eth->dev, "incorrect phy-mode\n"); 3303 goto free_netdev; 3304 } 3305 3306 /* mac config is not set */ 3307 mac->interface = PHY_INTERFACE_MODE_NA; 3308 mac->speed = SPEED_UNKNOWN; 3309 3310 mac->phylink_config.dev = ð->netdev[id]->dev; 3311 mac->phylink_config.type = PHYLINK_NETDEV; 3312 /* This driver makes use of state->speed in mac_config */ 3313 mac->phylink_config.legacy_pre_march2020 = true; 3314 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 3315 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 3316 3317 __set_bit(PHY_INTERFACE_MODE_MII, 3318 mac->phylink_config.supported_interfaces); 3319 __set_bit(PHY_INTERFACE_MODE_GMII, 3320 mac->phylink_config.supported_interfaces); 3321 3322 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 3323 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 3324 3325 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 3326 __set_bit(PHY_INTERFACE_MODE_TRGMII, 3327 mac->phylink_config.supported_interfaces); 3328 3329 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 3330 __set_bit(PHY_INTERFACE_MODE_SGMII, 3331 mac->phylink_config.supported_interfaces); 3332 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 3333 mac->phylink_config.supported_interfaces); 3334 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 3335 mac->phylink_config.supported_interfaces); 3336 } 3337 3338 phylink = phylink_create(&mac->phylink_config, 3339 of_fwnode_handle(mac->of_node), 3340 phy_mode, &mtk_phylink_ops); 3341 if (IS_ERR(phylink)) { 3342 err = PTR_ERR(phylink); 3343 goto free_netdev; 3344 } 3345 3346 mac->phylink = phylink; 3347 3348 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 3349 eth->netdev[id]->watchdog_timeo = 5 * HZ; 3350 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 3351 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3352 3353 eth->netdev[id]->hw_features = eth->soc->hw_features; 3354 if (eth->hwlro) 3355 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3356 3357 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3358 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3359 eth->netdev[id]->features |= eth->soc->hw_features; 3360 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3361 3362 eth->netdev[id]->irq = eth->irq[0]; 3363 eth->netdev[id]->dev.of_node = np; 3364 3365 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3366 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3367 else 3368 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3369 3370 return 0; 3371 3372 free_netdev: 3373 free_netdev(eth->netdev[id]); 3374 return err; 3375 } 3376 3377 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 3378 { 3379 struct net_device *dev, *tmp; 3380 LIST_HEAD(dev_list); 3381 int i; 3382 3383 rtnl_lock(); 3384 3385 for (i = 0; i < MTK_MAC_COUNT; i++) { 3386 dev = eth->netdev[i]; 3387 3388 if (!dev || !(dev->flags & IFF_UP)) 3389 continue; 3390 3391 list_add_tail(&dev->close_list, &dev_list); 3392 } 3393 3394 dev_close_many(&dev_list, false); 3395 3396 eth->dma_dev = dma_dev; 3397 3398 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 3399 list_del_init(&dev->close_list); 3400 dev_open(dev, NULL); 3401 } 3402 3403 rtnl_unlock(); 3404 } 3405 3406 static int mtk_probe(struct platform_device *pdev) 3407 { 3408 struct device_node *mac_np; 3409 struct mtk_eth *eth; 3410 int err, i; 3411 3412 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3413 if (!eth) 3414 return -ENOMEM; 3415 3416 eth->soc = of_device_get_match_data(&pdev->dev); 3417 3418 eth->dev = &pdev->dev; 3419 eth->dma_dev = &pdev->dev; 3420 eth->base = devm_platform_ioremap_resource(pdev, 0); 3421 if (IS_ERR(eth->base)) 3422 return PTR_ERR(eth->base); 3423 3424 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3425 eth->ip_align = NET_IP_ALIGN; 3426 3427 spin_lock_init(ð->page_lock); 3428 spin_lock_init(ð->tx_irq_lock); 3429 spin_lock_init(ð->rx_irq_lock); 3430 spin_lock_init(ð->dim_lock); 3431 3432 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3433 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3434 3435 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3436 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3437 3438 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3439 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3440 "mediatek,ethsys"); 3441 if (IS_ERR(eth->ethsys)) { 3442 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3443 return PTR_ERR(eth->ethsys); 3444 } 3445 } 3446 3447 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3448 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3449 "mediatek,infracfg"); 3450 if (IS_ERR(eth->infra)) { 3451 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3452 return PTR_ERR(eth->infra); 3453 } 3454 } 3455 3456 if (of_dma_is_coherent(pdev->dev.of_node)) { 3457 struct regmap *cci; 3458 3459 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3460 "cci-control-port"); 3461 /* enable CPU/bus coherency */ 3462 if (!IS_ERR(cci)) 3463 regmap_write(cci, 0, 3); 3464 } 3465 3466 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3467 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3468 GFP_KERNEL); 3469 if (!eth->sgmii) 3470 return -ENOMEM; 3471 3472 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3473 eth->soc->ana_rgc3); 3474 3475 if (err) 3476 return err; 3477 } 3478 3479 if (eth->soc->required_pctl) { 3480 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3481 "mediatek,pctl"); 3482 if (IS_ERR(eth->pctl)) { 3483 dev_err(&pdev->dev, "no pctl regmap found\n"); 3484 return PTR_ERR(eth->pctl); 3485 } 3486 } 3487 3488 for (i = 0;; i++) { 3489 struct device_node *np = of_parse_phandle(pdev->dev.of_node, 3490 "mediatek,wed", i); 3491 static const u32 wdma_regs[] = { 3492 MTK_WDMA0_BASE, 3493 MTK_WDMA1_BASE 3494 }; 3495 void __iomem *wdma; 3496 3497 if (!np || i >= ARRAY_SIZE(wdma_regs)) 3498 break; 3499 3500 wdma = eth->base + wdma_regs[i]; 3501 mtk_wed_add_hw(np, eth, wdma, i); 3502 } 3503 3504 for (i = 0; i < 3; i++) { 3505 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 3506 eth->irq[i] = eth->irq[0]; 3507 else 3508 eth->irq[i] = platform_get_irq(pdev, i); 3509 if (eth->irq[i] < 0) { 3510 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 3511 return -ENXIO; 3512 } 3513 } 3514 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 3515 eth->clks[i] = devm_clk_get(eth->dev, 3516 mtk_clks_source_name[i]); 3517 if (IS_ERR(eth->clks[i])) { 3518 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 3519 return -EPROBE_DEFER; 3520 if (eth->soc->required_clks & BIT(i)) { 3521 dev_err(&pdev->dev, "clock %s not found\n", 3522 mtk_clks_source_name[i]); 3523 return -EINVAL; 3524 } 3525 eth->clks[i] = NULL; 3526 } 3527 } 3528 3529 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3530 INIT_WORK(ð->pending_work, mtk_pending_work); 3531 3532 err = mtk_hw_init(eth); 3533 if (err) 3534 return err; 3535 3536 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3537 3538 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3539 if (!of_device_is_compatible(mac_np, 3540 "mediatek,eth-mac")) 3541 continue; 3542 3543 if (!of_device_is_available(mac_np)) 3544 continue; 3545 3546 err = mtk_add_mac(eth, mac_np); 3547 if (err) { 3548 of_node_put(mac_np); 3549 goto err_deinit_hw; 3550 } 3551 } 3552 3553 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3554 err = devm_request_irq(eth->dev, eth->irq[0], 3555 mtk_handle_irq, 0, 3556 dev_name(eth->dev), eth); 3557 } else { 3558 err = devm_request_irq(eth->dev, eth->irq[1], 3559 mtk_handle_irq_tx, 0, 3560 dev_name(eth->dev), eth); 3561 if (err) 3562 goto err_free_dev; 3563 3564 err = devm_request_irq(eth->dev, eth->irq[2], 3565 mtk_handle_irq_rx, 0, 3566 dev_name(eth->dev), eth); 3567 } 3568 if (err) 3569 goto err_free_dev; 3570 3571 /* No MT7628/88 support yet */ 3572 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3573 err = mtk_mdio_init(eth); 3574 if (err) 3575 goto err_free_dev; 3576 } 3577 3578 if (eth->soc->offload_version) { 3579 eth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2); 3580 if (!eth->ppe) { 3581 err = -ENOMEM; 3582 goto err_free_dev; 3583 } 3584 3585 err = mtk_eth_offload_init(eth); 3586 if (err) 3587 goto err_free_dev; 3588 } 3589 3590 for (i = 0; i < MTK_MAX_DEVS; i++) { 3591 if (!eth->netdev[i]) 3592 continue; 3593 3594 err = register_netdev(eth->netdev[i]); 3595 if (err) { 3596 dev_err(eth->dev, "error bringing up device\n"); 3597 goto err_deinit_mdio; 3598 } else 3599 netif_info(eth, probe, eth->netdev[i], 3600 "mediatek frame engine at 0x%08lx, irq %d\n", 3601 eth->netdev[i]->base_addr, eth->irq[0]); 3602 } 3603 3604 /* we run 2 devices on the same DMA ring so we need a dummy device 3605 * for NAPI to work 3606 */ 3607 init_dummy_netdev(ð->dummy_dev); 3608 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3609 NAPI_POLL_WEIGHT); 3610 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3611 NAPI_POLL_WEIGHT); 3612 3613 platform_set_drvdata(pdev, eth); 3614 3615 return 0; 3616 3617 err_deinit_mdio: 3618 mtk_mdio_cleanup(eth); 3619 err_free_dev: 3620 mtk_free_dev(eth); 3621 err_deinit_hw: 3622 mtk_hw_deinit(eth); 3623 3624 return err; 3625 } 3626 3627 static int mtk_remove(struct platform_device *pdev) 3628 { 3629 struct mtk_eth *eth = platform_get_drvdata(pdev); 3630 struct mtk_mac *mac; 3631 int i; 3632 3633 /* stop all devices to make sure that dma is properly shut down */ 3634 for (i = 0; i < MTK_MAC_COUNT; i++) { 3635 if (!eth->netdev[i]) 3636 continue; 3637 mtk_stop(eth->netdev[i]); 3638 mac = netdev_priv(eth->netdev[i]); 3639 phylink_disconnect_phy(mac->phylink); 3640 } 3641 3642 mtk_hw_deinit(eth); 3643 3644 netif_napi_del(ð->tx_napi); 3645 netif_napi_del(ð->rx_napi); 3646 mtk_cleanup(eth); 3647 mtk_mdio_cleanup(eth); 3648 3649 return 0; 3650 } 3651 3652 static const struct mtk_soc_data mt2701_data = { 3653 .reg_map = &mtk_reg_map, 3654 .caps = MT7623_CAPS | MTK_HWLRO, 3655 .hw_features = MTK_HW_FEATURES, 3656 .required_clks = MT7623_CLKS_BITMAP, 3657 .required_pctl = true, 3658 .txrx = { 3659 .txd_size = sizeof(struct mtk_tx_dma), 3660 .rxd_size = sizeof(struct mtk_rx_dma), 3661 .rx_irq_done_mask = MTK_RX_DONE_INT, 3662 .rx_dma_l4_valid = RX_DMA_L4_VALID, 3663 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3664 .dma_len_offset = 16, 3665 }, 3666 }; 3667 3668 static const struct mtk_soc_data mt7621_data = { 3669 .reg_map = &mtk_reg_map, 3670 .caps = MT7621_CAPS, 3671 .hw_features = MTK_HW_FEATURES, 3672 .required_clks = MT7621_CLKS_BITMAP, 3673 .required_pctl = false, 3674 .offload_version = 2, 3675 .txrx = { 3676 .txd_size = sizeof(struct mtk_tx_dma), 3677 .rxd_size = sizeof(struct mtk_rx_dma), 3678 .rx_irq_done_mask = MTK_RX_DONE_INT, 3679 .rx_dma_l4_valid = RX_DMA_L4_VALID, 3680 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3681 .dma_len_offset = 16, 3682 }, 3683 }; 3684 3685 static const struct mtk_soc_data mt7622_data = { 3686 .reg_map = &mtk_reg_map, 3687 .ana_rgc3 = 0x2028, 3688 .caps = MT7622_CAPS | MTK_HWLRO, 3689 .hw_features = MTK_HW_FEATURES, 3690 .required_clks = MT7622_CLKS_BITMAP, 3691 .required_pctl = false, 3692 .offload_version = 2, 3693 .txrx = { 3694 .txd_size = sizeof(struct mtk_tx_dma), 3695 .rxd_size = sizeof(struct mtk_rx_dma), 3696 .rx_irq_done_mask = MTK_RX_DONE_INT, 3697 .rx_dma_l4_valid = RX_DMA_L4_VALID, 3698 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3699 .dma_len_offset = 16, 3700 }, 3701 }; 3702 3703 static const struct mtk_soc_data mt7623_data = { 3704 .reg_map = &mtk_reg_map, 3705 .caps = MT7623_CAPS | MTK_HWLRO, 3706 .hw_features = MTK_HW_FEATURES, 3707 .required_clks = MT7623_CLKS_BITMAP, 3708 .required_pctl = true, 3709 .offload_version = 2, 3710 .txrx = { 3711 .txd_size = sizeof(struct mtk_tx_dma), 3712 .rxd_size = sizeof(struct mtk_rx_dma), 3713 .rx_irq_done_mask = MTK_RX_DONE_INT, 3714 .rx_dma_l4_valid = RX_DMA_L4_VALID, 3715 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3716 .dma_len_offset = 16, 3717 }, 3718 }; 3719 3720 static const struct mtk_soc_data mt7629_data = { 3721 .reg_map = &mtk_reg_map, 3722 .ana_rgc3 = 0x128, 3723 .caps = MT7629_CAPS | MTK_HWLRO, 3724 .hw_features = MTK_HW_FEATURES, 3725 .required_clks = MT7629_CLKS_BITMAP, 3726 .required_pctl = false, 3727 .txrx = { 3728 .txd_size = sizeof(struct mtk_tx_dma), 3729 .rxd_size = sizeof(struct mtk_rx_dma), 3730 .rx_irq_done_mask = MTK_RX_DONE_INT, 3731 .rx_dma_l4_valid = RX_DMA_L4_VALID, 3732 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3733 .dma_len_offset = 16, 3734 }, 3735 }; 3736 3737 static const struct mtk_soc_data mt7986_data = { 3738 .reg_map = &mt7986_reg_map, 3739 .ana_rgc3 = 0x128, 3740 .caps = MT7986_CAPS, 3741 .required_clks = MT7986_CLKS_BITMAP, 3742 .required_pctl = false, 3743 .txrx = { 3744 .txd_size = sizeof(struct mtk_tx_dma_v2), 3745 .rxd_size = sizeof(struct mtk_rx_dma_v2), 3746 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 3747 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 3748 .dma_len_offset = 8, 3749 }, 3750 }; 3751 3752 static const struct mtk_soc_data rt5350_data = { 3753 .reg_map = &mt7628_reg_map, 3754 .caps = MT7628_CAPS, 3755 .hw_features = MTK_HW_FEATURES_MT7628, 3756 .required_clks = MT7628_CLKS_BITMAP, 3757 .required_pctl = false, 3758 .txrx = { 3759 .txd_size = sizeof(struct mtk_tx_dma), 3760 .rxd_size = sizeof(struct mtk_rx_dma), 3761 .rx_irq_done_mask = MTK_RX_DONE_INT, 3762 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 3763 .dma_max_len = MTK_TX_DMA_BUF_LEN, 3764 .dma_len_offset = 16, 3765 }, 3766 }; 3767 3768 const struct of_device_id of_mtk_match[] = { 3769 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3770 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3771 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3772 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3773 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3774 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 3775 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3776 {}, 3777 }; 3778 MODULE_DEVICE_TABLE(of, of_mtk_match); 3779 3780 static struct platform_driver mtk_driver = { 3781 .probe = mtk_probe, 3782 .remove = mtk_remove, 3783 .driver = { 3784 .name = "mtk_soc_eth", 3785 .of_match_table = of_mtk_match, 3786 }, 3787 }; 3788 3789 module_platform_driver(mtk_driver); 3790 3791 MODULE_LICENSE("GPL"); 3792 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3793 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3794