1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 26 #include "mtk_eth_soc.h" 27 28 static int mtk_msg_level = -1; 29 module_param_named(msg_level, mtk_msg_level, int, 0); 30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 31 32 #define MTK_ETHTOOL_STAT(x) { #x, \ 33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 34 35 /* strings used by ethtool */ 36 static const struct mtk_ethtool_stats { 37 char str[ETH_GSTRING_LEN]; 38 u32 offset; 39 } mtk_ethtool_stats[] = { 40 MTK_ETHTOOL_STAT(tx_bytes), 41 MTK_ETHTOOL_STAT(tx_packets), 42 MTK_ETHTOOL_STAT(tx_skip), 43 MTK_ETHTOOL_STAT(tx_collisions), 44 MTK_ETHTOOL_STAT(rx_bytes), 45 MTK_ETHTOOL_STAT(rx_packets), 46 MTK_ETHTOOL_STAT(rx_overflow), 47 MTK_ETHTOOL_STAT(rx_fcs_errors), 48 MTK_ETHTOOL_STAT(rx_short_errors), 49 MTK_ETHTOOL_STAT(rx_long_errors), 50 MTK_ETHTOOL_STAT(rx_checksum_errors), 51 MTK_ETHTOOL_STAT(rx_flow_control_packets), 52 }; 53 54 static const char * const mtk_clks_source_name[] = { 55 "ethif", "esw", "gp1", "gp2", "trgpll" 56 }; 57 58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 59 { 60 __raw_writel(val, eth->base + reg); 61 } 62 63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 64 { 65 return __raw_readl(eth->base + reg); 66 } 67 68 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 69 { 70 unsigned long t_start = jiffies; 71 72 while (1) { 73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 74 return 0; 75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 76 break; 77 usleep_range(10, 20); 78 } 79 80 dev_err(eth->dev, "mdio: MDIO timeout\n"); 81 return -1; 82 } 83 84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 85 u32 phy_register, u32 write_data) 86 { 87 if (mtk_mdio_busy_wait(eth)) 88 return -1; 89 90 write_data &= 0xffff; 91 92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 93 (phy_register << PHY_IAC_REG_SHIFT) | 94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 95 MTK_PHY_IAC); 96 97 if (mtk_mdio_busy_wait(eth)) 98 return -1; 99 100 return 0; 101 } 102 103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 104 { 105 u32 d; 106 107 if (mtk_mdio_busy_wait(eth)) 108 return 0xffff; 109 110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 111 (phy_reg << PHY_IAC_REG_SHIFT) | 112 (phy_addr << PHY_IAC_ADDR_SHIFT), 113 MTK_PHY_IAC); 114 115 if (mtk_mdio_busy_wait(eth)) 116 return 0xffff; 117 118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 119 120 return d; 121 } 122 123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 124 int phy_reg, u16 val) 125 { 126 struct mtk_eth *eth = bus->priv; 127 128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 129 } 130 131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 132 { 133 struct mtk_eth *eth = bus->priv; 134 135 return _mtk_mdio_read(eth, phy_addr, phy_reg); 136 } 137 138 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 139 { 140 u32 val; 141 int ret; 142 143 val = (speed == SPEED_1000) ? 144 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 145 mtk_w32(eth, val, INTF_MODE); 146 147 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 148 ETHSYS_TRGMII_CLK_SEL362_5, 149 ETHSYS_TRGMII_CLK_SEL362_5); 150 151 val = (speed == SPEED_1000) ? 250000000 : 500000000; 152 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 153 if (ret) 154 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 155 156 val = (speed == SPEED_1000) ? 157 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 158 mtk_w32(eth, val, TRGMII_RCK_CTRL); 159 160 val = (speed == SPEED_1000) ? 161 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 162 mtk_w32(eth, val, TRGMII_TCK_CTRL); 163 } 164 165 static void mtk_phy_link_adjust(struct net_device *dev) 166 { 167 struct mtk_mac *mac = netdev_priv(dev); 168 u16 lcl_adv = 0, rmt_adv = 0; 169 u8 flowctrl; 170 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 171 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 172 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 173 MAC_MCR_BACKPR_EN; 174 175 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 176 return; 177 178 switch (dev->phydev->speed) { 179 case SPEED_1000: 180 mcr |= MAC_MCR_SPEED_1000; 181 break; 182 case SPEED_100: 183 mcr |= MAC_MCR_SPEED_100; 184 break; 185 }; 186 187 if (mac->id == 0 && !mac->trgmii) 188 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 189 190 if (dev->phydev->link) 191 mcr |= MAC_MCR_FORCE_LINK; 192 193 if (dev->phydev->duplex) { 194 mcr |= MAC_MCR_FORCE_DPX; 195 196 if (dev->phydev->pause) 197 rmt_adv = LPA_PAUSE_CAP; 198 if (dev->phydev->asym_pause) 199 rmt_adv |= LPA_PAUSE_ASYM; 200 201 if (dev->phydev->advertising & ADVERTISED_Pause) 202 lcl_adv |= ADVERTISE_PAUSE_CAP; 203 if (dev->phydev->advertising & ADVERTISED_Asym_Pause) 204 lcl_adv |= ADVERTISE_PAUSE_ASYM; 205 206 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 207 208 if (flowctrl & FLOW_CTRL_TX) 209 mcr |= MAC_MCR_FORCE_TX_FC; 210 if (flowctrl & FLOW_CTRL_RX) 211 mcr |= MAC_MCR_FORCE_RX_FC; 212 213 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 214 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 215 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 216 } 217 218 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 219 220 if (dev->phydev->link) 221 netif_carrier_on(dev); 222 else 223 netif_carrier_off(dev); 224 225 if (!of_phy_is_fixed_link(mac->of_node)) 226 phy_print_status(dev->phydev); 227 } 228 229 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 230 struct device_node *phy_node) 231 { 232 struct phy_device *phydev; 233 int phy_mode; 234 235 phy_mode = of_get_phy_mode(phy_node); 236 if (phy_mode < 0) { 237 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 238 return -EINVAL; 239 } 240 241 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 242 mtk_phy_link_adjust, 0, phy_mode); 243 if (!phydev) { 244 dev_err(eth->dev, "could not connect to PHY\n"); 245 return -ENODEV; 246 } 247 248 dev_info(eth->dev, 249 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 250 mac->id, phydev_name(phydev), phydev->phy_id, 251 phydev->drv->name); 252 253 return 0; 254 } 255 256 static int mtk_phy_connect(struct net_device *dev) 257 { 258 struct mtk_mac *mac = netdev_priv(dev); 259 struct mtk_eth *eth; 260 struct device_node *np; 261 u32 val; 262 263 eth = mac->hw; 264 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 265 if (!np && of_phy_is_fixed_link(mac->of_node)) 266 if (!of_phy_register_fixed_link(mac->of_node)) 267 np = of_node_get(mac->of_node); 268 if (!np) 269 return -ENODEV; 270 271 switch (of_get_phy_mode(np)) { 272 case PHY_INTERFACE_MODE_TRGMII: 273 mac->trgmii = true; 274 case PHY_INTERFACE_MODE_RGMII_TXID: 275 case PHY_INTERFACE_MODE_RGMII_RXID: 276 case PHY_INTERFACE_MODE_RGMII_ID: 277 case PHY_INTERFACE_MODE_RGMII: 278 mac->ge_mode = 0; 279 break; 280 case PHY_INTERFACE_MODE_MII: 281 mac->ge_mode = 1; 282 break; 283 case PHY_INTERFACE_MODE_REVMII: 284 mac->ge_mode = 2; 285 break; 286 case PHY_INTERFACE_MODE_RMII: 287 if (!mac->id) 288 goto err_phy; 289 mac->ge_mode = 3; 290 break; 291 default: 292 goto err_phy; 293 } 294 295 /* put the gmac into the right mode */ 296 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 297 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 298 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 299 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 300 301 /* couple phydev to net_device */ 302 if (mtk_phy_connect_node(eth, mac, np)) 303 goto err_phy; 304 305 dev->phydev->autoneg = AUTONEG_ENABLE; 306 dev->phydev->speed = 0; 307 dev->phydev->duplex = 0; 308 309 if (of_phy_is_fixed_link(mac->of_node)) 310 dev->phydev->supported |= 311 SUPPORTED_Pause | SUPPORTED_Asym_Pause; 312 313 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 314 SUPPORTED_Asym_Pause; 315 dev->phydev->advertising = dev->phydev->supported | 316 ADVERTISED_Autoneg; 317 phy_start_aneg(dev->phydev); 318 319 of_node_put(np); 320 321 return 0; 322 323 err_phy: 324 if (of_phy_is_fixed_link(mac->of_node)) 325 of_phy_deregister_fixed_link(mac->of_node); 326 of_node_put(np); 327 dev_err(eth->dev, "%s: invalid phy\n", __func__); 328 return -EINVAL; 329 } 330 331 static int mtk_mdio_init(struct mtk_eth *eth) 332 { 333 struct device_node *mii_np; 334 int ret; 335 336 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 337 if (!mii_np) { 338 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 339 return -ENODEV; 340 } 341 342 if (!of_device_is_available(mii_np)) { 343 ret = -ENODEV; 344 goto err_put_node; 345 } 346 347 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 348 if (!eth->mii_bus) { 349 ret = -ENOMEM; 350 goto err_put_node; 351 } 352 353 eth->mii_bus->name = "mdio"; 354 eth->mii_bus->read = mtk_mdio_read; 355 eth->mii_bus->write = mtk_mdio_write; 356 eth->mii_bus->priv = eth; 357 eth->mii_bus->parent = eth->dev; 358 359 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 360 ret = of_mdiobus_register(eth->mii_bus, mii_np); 361 362 err_put_node: 363 of_node_put(mii_np); 364 return ret; 365 } 366 367 static void mtk_mdio_cleanup(struct mtk_eth *eth) 368 { 369 if (!eth->mii_bus) 370 return; 371 372 mdiobus_unregister(eth->mii_bus); 373 } 374 375 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 376 { 377 unsigned long flags; 378 u32 val; 379 380 spin_lock_irqsave(ð->tx_irq_lock, flags); 381 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 382 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 383 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 384 } 385 386 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 387 { 388 unsigned long flags; 389 u32 val; 390 391 spin_lock_irqsave(ð->tx_irq_lock, flags); 392 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 393 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 394 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 395 } 396 397 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 398 { 399 unsigned long flags; 400 u32 val; 401 402 spin_lock_irqsave(ð->rx_irq_lock, flags); 403 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 404 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 405 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 406 } 407 408 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 409 { 410 unsigned long flags; 411 u32 val; 412 413 spin_lock_irqsave(ð->rx_irq_lock, flags); 414 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 415 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 416 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 417 } 418 419 static int mtk_set_mac_address(struct net_device *dev, void *p) 420 { 421 int ret = eth_mac_addr(dev, p); 422 struct mtk_mac *mac = netdev_priv(dev); 423 const char *macaddr = dev->dev_addr; 424 425 if (ret) 426 return ret; 427 428 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 429 return -EBUSY; 430 431 spin_lock_bh(&mac->hw->page_lock); 432 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 433 MTK_GDMA_MAC_ADRH(mac->id)); 434 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 435 (macaddr[4] << 8) | macaddr[5], 436 MTK_GDMA_MAC_ADRL(mac->id)); 437 spin_unlock_bh(&mac->hw->page_lock); 438 439 return 0; 440 } 441 442 void mtk_stats_update_mac(struct mtk_mac *mac) 443 { 444 struct mtk_hw_stats *hw_stats = mac->hw_stats; 445 unsigned int base = MTK_GDM1_TX_GBCNT; 446 u64 stats; 447 448 base += hw_stats->reg_offset; 449 450 u64_stats_update_begin(&hw_stats->syncp); 451 452 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 453 stats = mtk_r32(mac->hw, base + 0x04); 454 if (stats) 455 hw_stats->rx_bytes += (stats << 32); 456 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 457 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 458 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 459 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 460 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 461 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 462 hw_stats->rx_flow_control_packets += 463 mtk_r32(mac->hw, base + 0x24); 464 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 465 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 466 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 467 stats = mtk_r32(mac->hw, base + 0x34); 468 if (stats) 469 hw_stats->tx_bytes += (stats << 32); 470 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 471 u64_stats_update_end(&hw_stats->syncp); 472 } 473 474 static void mtk_stats_update(struct mtk_eth *eth) 475 { 476 int i; 477 478 for (i = 0; i < MTK_MAC_COUNT; i++) { 479 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 480 continue; 481 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 482 mtk_stats_update_mac(eth->mac[i]); 483 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 484 } 485 } 486 } 487 488 static void mtk_get_stats64(struct net_device *dev, 489 struct rtnl_link_stats64 *storage) 490 { 491 struct mtk_mac *mac = netdev_priv(dev); 492 struct mtk_hw_stats *hw_stats = mac->hw_stats; 493 unsigned int start; 494 495 if (netif_running(dev) && netif_device_present(dev)) { 496 if (spin_trylock_bh(&hw_stats->stats_lock)) { 497 mtk_stats_update_mac(mac); 498 spin_unlock_bh(&hw_stats->stats_lock); 499 } 500 } 501 502 do { 503 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 504 storage->rx_packets = hw_stats->rx_packets; 505 storage->tx_packets = hw_stats->tx_packets; 506 storage->rx_bytes = hw_stats->rx_bytes; 507 storage->tx_bytes = hw_stats->tx_bytes; 508 storage->collisions = hw_stats->tx_collisions; 509 storage->rx_length_errors = hw_stats->rx_short_errors + 510 hw_stats->rx_long_errors; 511 storage->rx_over_errors = hw_stats->rx_overflow; 512 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 513 storage->rx_errors = hw_stats->rx_checksum_errors; 514 storage->tx_aborted_errors = hw_stats->tx_skip; 515 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 516 517 storage->tx_errors = dev->stats.tx_errors; 518 storage->rx_dropped = dev->stats.rx_dropped; 519 storage->tx_dropped = dev->stats.tx_dropped; 520 } 521 522 static inline int mtk_max_frag_size(int mtu) 523 { 524 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 525 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 526 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 527 528 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 529 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 530 } 531 532 static inline int mtk_max_buf_size(int frag_size) 533 { 534 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 535 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 536 537 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 538 539 return buf_size; 540 } 541 542 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 543 struct mtk_rx_dma *dma_rxd) 544 { 545 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 546 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 547 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 548 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 549 } 550 551 /* the qdma core needs scratch memory to be setup */ 552 static int mtk_init_fq_dma(struct mtk_eth *eth) 553 { 554 dma_addr_t phy_ring_tail; 555 int cnt = MTK_DMA_SIZE; 556 dma_addr_t dma_addr; 557 int i; 558 559 eth->scratch_ring = dma_alloc_coherent(eth->dev, 560 cnt * sizeof(struct mtk_tx_dma), 561 ð->phy_scratch_ring, 562 GFP_ATOMIC | __GFP_ZERO); 563 if (unlikely(!eth->scratch_ring)) 564 return -ENOMEM; 565 566 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 567 GFP_KERNEL); 568 if (unlikely(!eth->scratch_head)) 569 return -ENOMEM; 570 571 dma_addr = dma_map_single(eth->dev, 572 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 573 DMA_FROM_DEVICE); 574 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 575 return -ENOMEM; 576 577 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 578 phy_ring_tail = eth->phy_scratch_ring + 579 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 580 581 for (i = 0; i < cnt; i++) { 582 eth->scratch_ring[i].txd1 = 583 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 584 if (i < cnt - 1) 585 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 586 ((i + 1) * sizeof(struct mtk_tx_dma))); 587 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 588 } 589 590 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 591 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 592 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 593 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 594 595 return 0; 596 } 597 598 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 599 { 600 void *ret = ring->dma; 601 602 return ret + (desc - ring->phys); 603 } 604 605 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 606 struct mtk_tx_dma *txd) 607 { 608 int idx = txd - ring->dma; 609 610 return &ring->buf[idx]; 611 } 612 613 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 614 { 615 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 616 dma_unmap_single(eth->dev, 617 dma_unmap_addr(tx_buf, dma_addr0), 618 dma_unmap_len(tx_buf, dma_len0), 619 DMA_TO_DEVICE); 620 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 621 dma_unmap_page(eth->dev, 622 dma_unmap_addr(tx_buf, dma_addr0), 623 dma_unmap_len(tx_buf, dma_len0), 624 DMA_TO_DEVICE); 625 } 626 tx_buf->flags = 0; 627 if (tx_buf->skb && 628 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 629 dev_kfree_skb_any(tx_buf->skb); 630 tx_buf->skb = NULL; 631 } 632 633 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 634 int tx_num, struct mtk_tx_ring *ring, bool gso) 635 { 636 struct mtk_mac *mac = netdev_priv(dev); 637 struct mtk_eth *eth = mac->hw; 638 struct mtk_tx_dma *itxd, *txd; 639 struct mtk_tx_buf *itx_buf, *tx_buf; 640 dma_addr_t mapped_addr; 641 unsigned int nr_frags; 642 int i, n_desc = 1; 643 u32 txd4 = 0, fport; 644 645 itxd = ring->next_free; 646 if (itxd == ring->last_free) 647 return -ENOMEM; 648 649 /* set the forward port */ 650 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 651 txd4 |= fport; 652 653 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 654 memset(itx_buf, 0, sizeof(*itx_buf)); 655 656 if (gso) 657 txd4 |= TX_DMA_TSO; 658 659 /* TX Checksum offload */ 660 if (skb->ip_summed == CHECKSUM_PARTIAL) 661 txd4 |= TX_DMA_CHKSUM; 662 663 /* VLAN header offload */ 664 if (skb_vlan_tag_present(skb)) 665 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 666 667 mapped_addr = dma_map_single(eth->dev, skb->data, 668 skb_headlen(skb), DMA_TO_DEVICE); 669 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 670 return -ENOMEM; 671 672 WRITE_ONCE(itxd->txd1, mapped_addr); 673 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 674 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 675 MTK_TX_FLAGS_FPORT1; 676 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr); 677 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb)); 678 679 /* TX SG offload */ 680 txd = itxd; 681 nr_frags = skb_shinfo(skb)->nr_frags; 682 for (i = 0; i < nr_frags; i++) { 683 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 684 unsigned int offset = 0; 685 int frag_size = skb_frag_size(frag); 686 687 while (frag_size) { 688 bool last_frag = false; 689 unsigned int frag_map_size; 690 691 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 692 if (txd == ring->last_free) 693 goto err_dma; 694 695 n_desc++; 696 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 697 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 698 frag_map_size, 699 DMA_TO_DEVICE); 700 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 701 goto err_dma; 702 703 if (i == nr_frags - 1 && 704 (frag_size - frag_map_size) == 0) 705 last_frag = true; 706 707 WRITE_ONCE(txd->txd1, mapped_addr); 708 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 709 TX_DMA_PLEN0(frag_map_size) | 710 last_frag * TX_DMA_LS0)); 711 WRITE_ONCE(txd->txd4, fport); 712 713 tx_buf = mtk_desc_to_tx_buf(ring, txd); 714 memset(tx_buf, 0, sizeof(*tx_buf)); 715 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 716 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 717 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 718 MTK_TX_FLAGS_FPORT1; 719 720 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 721 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 722 frag_size -= frag_map_size; 723 offset += frag_map_size; 724 } 725 } 726 727 /* store skb to cleanup */ 728 itx_buf->skb = skb; 729 730 WRITE_ONCE(itxd->txd4, txd4); 731 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 732 (!nr_frags * TX_DMA_LS0))); 733 734 netdev_sent_queue(dev, skb->len); 735 skb_tx_timestamp(skb); 736 737 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 738 atomic_sub(n_desc, &ring->free_count); 739 740 /* make sure that all changes to the dma ring are flushed before we 741 * continue 742 */ 743 wmb(); 744 745 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 746 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 747 748 return 0; 749 750 err_dma: 751 do { 752 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 753 754 /* unmap dma */ 755 mtk_tx_unmap(eth, tx_buf); 756 757 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 758 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 759 } while (itxd != txd); 760 761 return -ENOMEM; 762 } 763 764 static inline int mtk_cal_txd_req(struct sk_buff *skb) 765 { 766 int i, nfrags; 767 struct skb_frag_struct *frag; 768 769 nfrags = 1; 770 if (skb_is_gso(skb)) { 771 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 772 frag = &skb_shinfo(skb)->frags[i]; 773 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 774 } 775 } else { 776 nfrags += skb_shinfo(skb)->nr_frags; 777 } 778 779 return nfrags; 780 } 781 782 static int mtk_queue_stopped(struct mtk_eth *eth) 783 { 784 int i; 785 786 for (i = 0; i < MTK_MAC_COUNT; i++) { 787 if (!eth->netdev[i]) 788 continue; 789 if (netif_queue_stopped(eth->netdev[i])) 790 return 1; 791 } 792 793 return 0; 794 } 795 796 static void mtk_wake_queue(struct mtk_eth *eth) 797 { 798 int i; 799 800 for (i = 0; i < MTK_MAC_COUNT; i++) { 801 if (!eth->netdev[i]) 802 continue; 803 netif_wake_queue(eth->netdev[i]); 804 } 805 } 806 807 static void mtk_stop_queue(struct mtk_eth *eth) 808 { 809 int i; 810 811 for (i = 0; i < MTK_MAC_COUNT; i++) { 812 if (!eth->netdev[i]) 813 continue; 814 netif_stop_queue(eth->netdev[i]); 815 } 816 } 817 818 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 819 { 820 struct mtk_mac *mac = netdev_priv(dev); 821 struct mtk_eth *eth = mac->hw; 822 struct mtk_tx_ring *ring = ð->tx_ring; 823 struct net_device_stats *stats = &dev->stats; 824 bool gso = false; 825 int tx_num; 826 827 /* normally we can rely on the stack not calling this more than once, 828 * however we have 2 queues running on the same ring so we need to lock 829 * the ring access 830 */ 831 spin_lock(ð->page_lock); 832 833 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 834 goto drop; 835 836 tx_num = mtk_cal_txd_req(skb); 837 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 838 mtk_stop_queue(eth); 839 netif_err(eth, tx_queued, dev, 840 "Tx Ring full when queue awake!\n"); 841 spin_unlock(ð->page_lock); 842 return NETDEV_TX_BUSY; 843 } 844 845 /* TSO: fill MSS info in tcp checksum field */ 846 if (skb_is_gso(skb)) { 847 if (skb_cow_head(skb, 0)) { 848 netif_warn(eth, tx_err, dev, 849 "GSO expand head fail.\n"); 850 goto drop; 851 } 852 853 if (skb_shinfo(skb)->gso_type & 854 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 855 gso = true; 856 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 857 } 858 } 859 860 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 861 goto drop; 862 863 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 864 mtk_stop_queue(eth); 865 866 spin_unlock(ð->page_lock); 867 868 return NETDEV_TX_OK; 869 870 drop: 871 spin_unlock(ð->page_lock); 872 stats->tx_dropped++; 873 dev_kfree_skb_any(skb); 874 return NETDEV_TX_OK; 875 } 876 877 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 878 { 879 int i; 880 struct mtk_rx_ring *ring; 881 int idx; 882 883 if (!eth->hwlro) 884 return ð->rx_ring[0]; 885 886 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 887 ring = ð->rx_ring[i]; 888 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 889 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 890 ring->calc_idx_update = true; 891 return ring; 892 } 893 } 894 895 return NULL; 896 } 897 898 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 899 { 900 struct mtk_rx_ring *ring; 901 int i; 902 903 if (!eth->hwlro) { 904 ring = ð->rx_ring[0]; 905 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 906 } else { 907 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 908 ring = ð->rx_ring[i]; 909 if (ring->calc_idx_update) { 910 ring->calc_idx_update = false; 911 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 912 } 913 } 914 } 915 } 916 917 static int mtk_poll_rx(struct napi_struct *napi, int budget, 918 struct mtk_eth *eth) 919 { 920 struct mtk_rx_ring *ring; 921 int idx; 922 struct sk_buff *skb; 923 u8 *data, *new_data; 924 struct mtk_rx_dma *rxd, trxd; 925 int done = 0; 926 927 while (done < budget) { 928 struct net_device *netdev; 929 unsigned int pktlen; 930 dma_addr_t dma_addr; 931 int mac = 0; 932 933 ring = mtk_get_rx_ring(eth); 934 if (unlikely(!ring)) 935 goto rx_done; 936 937 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 938 rxd = &ring->dma[idx]; 939 data = ring->data[idx]; 940 941 mtk_rx_get_desc(&trxd, rxd); 942 if (!(trxd.rxd2 & RX_DMA_DONE)) 943 break; 944 945 /* find out which mac the packet come from. values start at 1 */ 946 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 947 RX_DMA_FPORT_MASK; 948 mac--; 949 950 netdev = eth->netdev[mac]; 951 952 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 953 goto release_desc; 954 955 /* alloc new buffer */ 956 new_data = napi_alloc_frag(ring->frag_size); 957 if (unlikely(!new_data)) { 958 netdev->stats.rx_dropped++; 959 goto release_desc; 960 } 961 dma_addr = dma_map_single(eth->dev, 962 new_data + NET_SKB_PAD, 963 ring->buf_size, 964 DMA_FROM_DEVICE); 965 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 966 skb_free_frag(new_data); 967 netdev->stats.rx_dropped++; 968 goto release_desc; 969 } 970 971 /* receive data */ 972 skb = build_skb(data, ring->frag_size); 973 if (unlikely(!skb)) { 974 skb_free_frag(new_data); 975 netdev->stats.rx_dropped++; 976 goto release_desc; 977 } 978 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 979 980 dma_unmap_single(eth->dev, trxd.rxd1, 981 ring->buf_size, DMA_FROM_DEVICE); 982 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 983 skb->dev = netdev; 984 skb_put(skb, pktlen); 985 if (trxd.rxd4 & RX_DMA_L4_VALID) 986 skb->ip_summed = CHECKSUM_UNNECESSARY; 987 else 988 skb_checksum_none_assert(skb); 989 skb->protocol = eth_type_trans(skb, netdev); 990 991 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 992 RX_DMA_VID(trxd.rxd3)) 993 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 994 RX_DMA_VID(trxd.rxd3)); 995 skb_record_rx_queue(skb, 0); 996 napi_gro_receive(napi, skb); 997 998 ring->data[idx] = new_data; 999 rxd->rxd1 = (unsigned int)dma_addr; 1000 1001 release_desc: 1002 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1003 1004 ring->calc_idx = idx; 1005 1006 done++; 1007 } 1008 1009 rx_done: 1010 if (done) { 1011 /* make sure that all changes to the dma ring are flushed before 1012 * we continue 1013 */ 1014 wmb(); 1015 mtk_update_rx_cpu_idx(eth); 1016 } 1017 1018 return done; 1019 } 1020 1021 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1022 { 1023 struct mtk_tx_ring *ring = ð->tx_ring; 1024 struct mtk_tx_dma *desc; 1025 struct sk_buff *skb; 1026 struct mtk_tx_buf *tx_buf; 1027 unsigned int done[MTK_MAX_DEVS]; 1028 unsigned int bytes[MTK_MAX_DEVS]; 1029 u32 cpu, dma; 1030 static int condition; 1031 int total = 0, i; 1032 1033 memset(done, 0, sizeof(done)); 1034 memset(bytes, 0, sizeof(bytes)); 1035 1036 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1037 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1038 1039 desc = mtk_qdma_phys_to_virt(ring, cpu); 1040 1041 while ((cpu != dma) && budget) { 1042 u32 next_cpu = desc->txd2; 1043 int mac = 0; 1044 1045 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1046 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1047 break; 1048 1049 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1050 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1051 mac = 1; 1052 1053 skb = tx_buf->skb; 1054 if (!skb) { 1055 condition = 1; 1056 break; 1057 } 1058 1059 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1060 bytes[mac] += skb->len; 1061 done[mac]++; 1062 budget--; 1063 } 1064 mtk_tx_unmap(eth, tx_buf); 1065 1066 ring->last_free = desc; 1067 atomic_inc(&ring->free_count); 1068 1069 cpu = next_cpu; 1070 } 1071 1072 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1073 1074 for (i = 0; i < MTK_MAC_COUNT; i++) { 1075 if (!eth->netdev[i] || !done[i]) 1076 continue; 1077 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1078 total += done[i]; 1079 } 1080 1081 if (mtk_queue_stopped(eth) && 1082 (atomic_read(&ring->free_count) > ring->thresh)) 1083 mtk_wake_queue(eth); 1084 1085 return total; 1086 } 1087 1088 static void mtk_handle_status_irq(struct mtk_eth *eth) 1089 { 1090 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1091 1092 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1093 mtk_stats_update(eth); 1094 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1095 MTK_INT_STATUS2); 1096 } 1097 } 1098 1099 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1100 { 1101 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1102 u32 status, mask; 1103 int tx_done = 0; 1104 1105 mtk_handle_status_irq(eth); 1106 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1107 tx_done = mtk_poll_tx(eth, budget); 1108 1109 if (unlikely(netif_msg_intr(eth))) { 1110 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1111 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1112 dev_info(eth->dev, 1113 "done tx %d, intr 0x%08x/0x%x\n", 1114 tx_done, status, mask); 1115 } 1116 1117 if (tx_done == budget) 1118 return budget; 1119 1120 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1121 if (status & MTK_TX_DONE_INT) 1122 return budget; 1123 1124 napi_complete(napi); 1125 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1126 1127 return tx_done; 1128 } 1129 1130 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1131 { 1132 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1133 u32 status, mask; 1134 int rx_done = 0; 1135 int remain_budget = budget; 1136 1137 mtk_handle_status_irq(eth); 1138 1139 poll_again: 1140 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1141 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1142 1143 if (unlikely(netif_msg_intr(eth))) { 1144 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1145 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1146 dev_info(eth->dev, 1147 "done rx %d, intr 0x%08x/0x%x\n", 1148 rx_done, status, mask); 1149 } 1150 if (rx_done == remain_budget) 1151 return budget; 1152 1153 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1154 if (status & MTK_RX_DONE_INT) { 1155 remain_budget -= rx_done; 1156 goto poll_again; 1157 } 1158 napi_complete(napi); 1159 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1160 1161 return rx_done + budget - remain_budget; 1162 } 1163 1164 static int mtk_tx_alloc(struct mtk_eth *eth) 1165 { 1166 struct mtk_tx_ring *ring = ð->tx_ring; 1167 int i, sz = sizeof(*ring->dma); 1168 1169 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1170 GFP_KERNEL); 1171 if (!ring->buf) 1172 goto no_tx_mem; 1173 1174 ring->dma = dma_alloc_coherent(eth->dev, 1175 MTK_DMA_SIZE * sz, 1176 &ring->phys, 1177 GFP_ATOMIC | __GFP_ZERO); 1178 if (!ring->dma) 1179 goto no_tx_mem; 1180 1181 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1182 for (i = 0; i < MTK_DMA_SIZE; i++) { 1183 int next = (i + 1) % MTK_DMA_SIZE; 1184 u32 next_ptr = ring->phys + next * sz; 1185 1186 ring->dma[i].txd2 = next_ptr; 1187 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1188 } 1189 1190 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1191 ring->next_free = &ring->dma[0]; 1192 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1193 ring->thresh = MAX_SKB_FRAGS; 1194 1195 /* make sure that all changes to the dma ring are flushed before we 1196 * continue 1197 */ 1198 wmb(); 1199 1200 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1201 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1202 mtk_w32(eth, 1203 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1204 MTK_QTX_CRX_PTR); 1205 mtk_w32(eth, 1206 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1207 MTK_QTX_DRX_PTR); 1208 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1209 1210 return 0; 1211 1212 no_tx_mem: 1213 return -ENOMEM; 1214 } 1215 1216 static void mtk_tx_clean(struct mtk_eth *eth) 1217 { 1218 struct mtk_tx_ring *ring = ð->tx_ring; 1219 int i; 1220 1221 if (ring->buf) { 1222 for (i = 0; i < MTK_DMA_SIZE; i++) 1223 mtk_tx_unmap(eth, &ring->buf[i]); 1224 kfree(ring->buf); 1225 ring->buf = NULL; 1226 } 1227 1228 if (ring->dma) { 1229 dma_free_coherent(eth->dev, 1230 MTK_DMA_SIZE * sizeof(*ring->dma), 1231 ring->dma, 1232 ring->phys); 1233 ring->dma = NULL; 1234 } 1235 } 1236 1237 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1238 { 1239 struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; 1240 int rx_data_len, rx_dma_size; 1241 int i; 1242 1243 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1244 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1245 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1246 } else { 1247 rx_data_len = ETH_DATA_LEN; 1248 rx_dma_size = MTK_DMA_SIZE; 1249 } 1250 1251 ring->frag_size = mtk_max_frag_size(rx_data_len); 1252 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1253 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1254 GFP_KERNEL); 1255 if (!ring->data) 1256 return -ENOMEM; 1257 1258 for (i = 0; i < rx_dma_size; i++) { 1259 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1260 if (!ring->data[i]) 1261 return -ENOMEM; 1262 } 1263 1264 ring->dma = dma_alloc_coherent(eth->dev, 1265 rx_dma_size * sizeof(*ring->dma), 1266 &ring->phys, 1267 GFP_ATOMIC | __GFP_ZERO); 1268 if (!ring->dma) 1269 return -ENOMEM; 1270 1271 for (i = 0; i < rx_dma_size; i++) { 1272 dma_addr_t dma_addr = dma_map_single(eth->dev, 1273 ring->data[i] + NET_SKB_PAD, 1274 ring->buf_size, 1275 DMA_FROM_DEVICE); 1276 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1277 return -ENOMEM; 1278 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1279 1280 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1281 } 1282 ring->dma_size = rx_dma_size; 1283 ring->calc_idx_update = false; 1284 ring->calc_idx = rx_dma_size - 1; 1285 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1286 /* make sure that all changes to the dma ring are flushed before we 1287 * continue 1288 */ 1289 wmb(); 1290 1291 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); 1292 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); 1293 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1294 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); 1295 1296 return 0; 1297 } 1298 1299 static void mtk_rx_clean(struct mtk_eth *eth, int ring_no) 1300 { 1301 struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; 1302 int i; 1303 1304 if (ring->data && ring->dma) { 1305 for (i = 0; i < ring->dma_size; i++) { 1306 if (!ring->data[i]) 1307 continue; 1308 if (!ring->dma[i].rxd1) 1309 continue; 1310 dma_unmap_single(eth->dev, 1311 ring->dma[i].rxd1, 1312 ring->buf_size, 1313 DMA_FROM_DEVICE); 1314 skb_free_frag(ring->data[i]); 1315 } 1316 kfree(ring->data); 1317 ring->data = NULL; 1318 } 1319 1320 if (ring->dma) { 1321 dma_free_coherent(eth->dev, 1322 ring->dma_size * sizeof(*ring->dma), 1323 ring->dma, 1324 ring->phys); 1325 ring->dma = NULL; 1326 } 1327 } 1328 1329 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1330 { 1331 int i; 1332 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1333 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1334 1335 /* set LRO rings to auto-learn modes */ 1336 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1337 1338 /* validate LRO ring */ 1339 ring_ctrl_dw2 |= MTK_RING_VLD; 1340 1341 /* set AGE timer (unit: 20us) */ 1342 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1343 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1344 1345 /* set max AGG timer (unit: 20us) */ 1346 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1347 1348 /* set max LRO AGG count */ 1349 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1350 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1351 1352 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1353 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1354 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1355 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1356 } 1357 1358 /* IPv4 checksum update enable */ 1359 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1360 1361 /* switch priority comparison to packet count mode */ 1362 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1363 1364 /* bandwidth threshold setting */ 1365 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1366 1367 /* auto-learn score delta setting */ 1368 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1369 1370 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1371 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1372 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1373 1374 /* set HW LRO mode & the max aggregation count for rx packets */ 1375 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1376 1377 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1378 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1379 1380 /* enable HW LRO */ 1381 lro_ctrl_dw0 |= MTK_LRO_EN; 1382 1383 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1384 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1385 1386 return 0; 1387 } 1388 1389 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1390 { 1391 int i; 1392 u32 val; 1393 1394 /* relinquish lro rings, flush aggregated packets */ 1395 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1396 1397 /* wait for relinquishments done */ 1398 for (i = 0; i < 10; i++) { 1399 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1400 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1401 msleep(20); 1402 continue; 1403 } 1404 break; 1405 } 1406 1407 /* invalidate lro rings */ 1408 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1409 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1410 1411 /* disable HW LRO */ 1412 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1413 } 1414 1415 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1416 { 1417 u32 reg_val; 1418 1419 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1420 1421 /* invalidate the IP setting */ 1422 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1423 1424 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1425 1426 /* validate the IP setting */ 1427 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1428 } 1429 1430 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1431 { 1432 u32 reg_val; 1433 1434 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1435 1436 /* invalidate the IP setting */ 1437 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1438 1439 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1440 } 1441 1442 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1443 { 1444 int cnt = 0; 1445 int i; 1446 1447 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1448 if (mac->hwlro_ip[i]) 1449 cnt++; 1450 } 1451 1452 return cnt; 1453 } 1454 1455 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1456 struct ethtool_rxnfc *cmd) 1457 { 1458 struct ethtool_rx_flow_spec *fsp = 1459 (struct ethtool_rx_flow_spec *)&cmd->fs; 1460 struct mtk_mac *mac = netdev_priv(dev); 1461 struct mtk_eth *eth = mac->hw; 1462 int hwlro_idx; 1463 1464 if ((fsp->flow_type != TCP_V4_FLOW) || 1465 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1466 (fsp->location > 1)) 1467 return -EINVAL; 1468 1469 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1470 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1471 1472 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1473 1474 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1475 1476 return 0; 1477 } 1478 1479 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1480 struct ethtool_rxnfc *cmd) 1481 { 1482 struct ethtool_rx_flow_spec *fsp = 1483 (struct ethtool_rx_flow_spec *)&cmd->fs; 1484 struct mtk_mac *mac = netdev_priv(dev); 1485 struct mtk_eth *eth = mac->hw; 1486 int hwlro_idx; 1487 1488 if (fsp->location > 1) 1489 return -EINVAL; 1490 1491 mac->hwlro_ip[fsp->location] = 0; 1492 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1493 1494 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1495 1496 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1497 1498 return 0; 1499 } 1500 1501 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1502 { 1503 struct mtk_mac *mac = netdev_priv(dev); 1504 struct mtk_eth *eth = mac->hw; 1505 int i, hwlro_idx; 1506 1507 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1508 mac->hwlro_ip[i] = 0; 1509 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1510 1511 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1512 } 1513 1514 mac->hwlro_ip_cnt = 0; 1515 } 1516 1517 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1518 struct ethtool_rxnfc *cmd) 1519 { 1520 struct mtk_mac *mac = netdev_priv(dev); 1521 struct ethtool_rx_flow_spec *fsp = 1522 (struct ethtool_rx_flow_spec *)&cmd->fs; 1523 1524 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1525 fsp->flow_type = TCP_V4_FLOW; 1526 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1527 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1528 1529 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1530 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1531 fsp->h_u.tcp_ip4_spec.psrc = 0; 1532 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1533 fsp->h_u.tcp_ip4_spec.pdst = 0; 1534 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1535 fsp->h_u.tcp_ip4_spec.tos = 0; 1536 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1537 1538 return 0; 1539 } 1540 1541 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1542 struct ethtool_rxnfc *cmd, 1543 u32 *rule_locs) 1544 { 1545 struct mtk_mac *mac = netdev_priv(dev); 1546 int cnt = 0; 1547 int i; 1548 1549 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1550 if (mac->hwlro_ip[i]) { 1551 rule_locs[cnt] = i; 1552 cnt++; 1553 } 1554 } 1555 1556 cmd->rule_cnt = cnt; 1557 1558 return 0; 1559 } 1560 1561 static netdev_features_t mtk_fix_features(struct net_device *dev, 1562 netdev_features_t features) 1563 { 1564 if (!(features & NETIF_F_LRO)) { 1565 struct mtk_mac *mac = netdev_priv(dev); 1566 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1567 1568 if (ip_cnt) { 1569 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1570 1571 features |= NETIF_F_LRO; 1572 } 1573 } 1574 1575 return features; 1576 } 1577 1578 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1579 { 1580 int err = 0; 1581 1582 if (!((dev->features ^ features) & NETIF_F_LRO)) 1583 return 0; 1584 1585 if (!(features & NETIF_F_LRO)) 1586 mtk_hwlro_netdev_disable(dev); 1587 1588 return err; 1589 } 1590 1591 /* wait for DMA to finish whatever it is doing before we start using it again */ 1592 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1593 { 1594 unsigned long t_start = jiffies; 1595 1596 while (1) { 1597 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1598 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1599 return 0; 1600 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1601 break; 1602 } 1603 1604 dev_err(eth->dev, "DMA init timeout\n"); 1605 return -1; 1606 } 1607 1608 static int mtk_dma_init(struct mtk_eth *eth) 1609 { 1610 int err; 1611 u32 i; 1612 1613 if (mtk_dma_busy_wait(eth)) 1614 return -EBUSY; 1615 1616 /* QDMA needs scratch memory for internal reordering of the 1617 * descriptors 1618 */ 1619 err = mtk_init_fq_dma(eth); 1620 if (err) 1621 return err; 1622 1623 err = mtk_tx_alloc(eth); 1624 if (err) 1625 return err; 1626 1627 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1628 if (err) 1629 return err; 1630 1631 if (eth->hwlro) { 1632 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1633 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1634 if (err) 1635 return err; 1636 } 1637 err = mtk_hwlro_rx_init(eth); 1638 if (err) 1639 return err; 1640 } 1641 1642 /* Enable random early drop and set drop threshold automatically */ 1643 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1644 MTK_QDMA_FC_THRES); 1645 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1646 1647 return 0; 1648 } 1649 1650 static void mtk_dma_free(struct mtk_eth *eth) 1651 { 1652 int i; 1653 1654 for (i = 0; i < MTK_MAC_COUNT; i++) 1655 if (eth->netdev[i]) 1656 netdev_reset_queue(eth->netdev[i]); 1657 if (eth->scratch_ring) { 1658 dma_free_coherent(eth->dev, 1659 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1660 eth->scratch_ring, 1661 eth->phy_scratch_ring); 1662 eth->scratch_ring = NULL; 1663 eth->phy_scratch_ring = 0; 1664 } 1665 mtk_tx_clean(eth); 1666 mtk_rx_clean(eth, 0); 1667 1668 if (eth->hwlro) { 1669 mtk_hwlro_rx_uninit(eth); 1670 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1671 mtk_rx_clean(eth, i); 1672 } 1673 1674 kfree(eth->scratch_head); 1675 } 1676 1677 static void mtk_tx_timeout(struct net_device *dev) 1678 { 1679 struct mtk_mac *mac = netdev_priv(dev); 1680 struct mtk_eth *eth = mac->hw; 1681 1682 eth->netdev[mac->id]->stats.tx_errors++; 1683 netif_err(eth, tx_err, dev, 1684 "transmit timed out\n"); 1685 schedule_work(ð->pending_work); 1686 } 1687 1688 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1689 { 1690 struct mtk_eth *eth = _eth; 1691 1692 if (likely(napi_schedule_prep(ð->rx_napi))) { 1693 __napi_schedule(ð->rx_napi); 1694 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1695 } 1696 1697 return IRQ_HANDLED; 1698 } 1699 1700 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1701 { 1702 struct mtk_eth *eth = _eth; 1703 1704 if (likely(napi_schedule_prep(ð->tx_napi))) { 1705 __napi_schedule(ð->tx_napi); 1706 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1707 } 1708 1709 return IRQ_HANDLED; 1710 } 1711 1712 #ifdef CONFIG_NET_POLL_CONTROLLER 1713 static void mtk_poll_controller(struct net_device *dev) 1714 { 1715 struct mtk_mac *mac = netdev_priv(dev); 1716 struct mtk_eth *eth = mac->hw; 1717 1718 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1719 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1720 mtk_handle_irq_rx(eth->irq[2], dev); 1721 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1722 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1723 } 1724 #endif 1725 1726 static int mtk_start_dma(struct mtk_eth *eth) 1727 { 1728 int err; 1729 1730 err = mtk_dma_init(eth); 1731 if (err) { 1732 mtk_dma_free(eth); 1733 return err; 1734 } 1735 1736 mtk_w32(eth, 1737 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1738 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO, 1739 MTK_QDMA_GLO_CFG); 1740 1741 mtk_w32(eth, 1742 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1743 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1744 MTK_PDMA_GLO_CFG); 1745 1746 return 0; 1747 } 1748 1749 static int mtk_open(struct net_device *dev) 1750 { 1751 struct mtk_mac *mac = netdev_priv(dev); 1752 struct mtk_eth *eth = mac->hw; 1753 1754 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1755 if (!atomic_read(ð->dma_refcnt)) { 1756 int err = mtk_start_dma(eth); 1757 1758 if (err) 1759 return err; 1760 1761 napi_enable(ð->tx_napi); 1762 napi_enable(ð->rx_napi); 1763 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1764 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1765 } 1766 atomic_inc(ð->dma_refcnt); 1767 1768 phy_start(dev->phydev); 1769 netif_start_queue(dev); 1770 1771 return 0; 1772 } 1773 1774 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1775 { 1776 u32 val; 1777 int i; 1778 1779 /* stop the dma engine */ 1780 spin_lock_bh(ð->page_lock); 1781 val = mtk_r32(eth, glo_cfg); 1782 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1783 glo_cfg); 1784 spin_unlock_bh(ð->page_lock); 1785 1786 /* wait for dma stop */ 1787 for (i = 0; i < 10; i++) { 1788 val = mtk_r32(eth, glo_cfg); 1789 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1790 msleep(20); 1791 continue; 1792 } 1793 break; 1794 } 1795 } 1796 1797 static int mtk_stop(struct net_device *dev) 1798 { 1799 struct mtk_mac *mac = netdev_priv(dev); 1800 struct mtk_eth *eth = mac->hw; 1801 1802 netif_tx_disable(dev); 1803 phy_stop(dev->phydev); 1804 1805 /* only shutdown DMA if this is the last user */ 1806 if (!atomic_dec_and_test(ð->dma_refcnt)) 1807 return 0; 1808 1809 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 1810 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 1811 napi_disable(ð->tx_napi); 1812 napi_disable(ð->rx_napi); 1813 1814 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1815 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1816 1817 mtk_dma_free(eth); 1818 1819 return 0; 1820 } 1821 1822 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1823 { 1824 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1825 reset_bits, 1826 reset_bits); 1827 1828 usleep_range(1000, 1100); 1829 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1830 reset_bits, 1831 ~reset_bits); 1832 mdelay(10); 1833 } 1834 1835 static int mtk_hw_init(struct mtk_eth *eth) 1836 { 1837 int i, val; 1838 1839 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1840 return 0; 1841 1842 pm_runtime_enable(eth->dev); 1843 pm_runtime_get_sync(eth->dev); 1844 1845 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]); 1846 clk_prepare_enable(eth->clks[MTK_CLK_ESW]); 1847 clk_prepare_enable(eth->clks[MTK_CLK_GP1]); 1848 clk_prepare_enable(eth->clks[MTK_CLK_GP2]); 1849 ethsys_reset(eth, RSTCTRL_FE); 1850 ethsys_reset(eth, RSTCTRL_PPE); 1851 1852 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1853 for (i = 0; i < MTK_MAC_COUNT; i++) { 1854 if (!eth->mac[i]) 1855 continue; 1856 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1857 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1858 } 1859 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1860 1861 /* Set GE2 driving and slew rate */ 1862 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1863 1864 /* set GE2 TDSEL */ 1865 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1866 1867 /* set GE2 TUNE */ 1868 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1869 1870 /* GE1, Force 1000M/FD, FC ON */ 1871 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1872 1873 /* GE2, Force 1000M/FD, FC ON */ 1874 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1875 1876 /* Indicates CDM to parse the MTK special tag from CPU 1877 * which also is working out for untag packets. 1878 */ 1879 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 1880 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 1881 1882 /* Enable RX VLan Offloading */ 1883 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1884 1885 /* enable interrupt delay for RX */ 1886 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 1887 1888 /* disable delay and normal interrupt */ 1889 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1890 mtk_tx_irq_disable(eth, ~0); 1891 mtk_rx_irq_disable(eth, ~0); 1892 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1893 mtk_w32(eth, 0, MTK_RST_GL); 1894 1895 /* FE int grouping */ 1896 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1897 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1898 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1899 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1900 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1901 1902 for (i = 0; i < 2; i++) { 1903 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1904 1905 /* setup the forward port to send frame to PDMA */ 1906 val &= ~0xffff; 1907 1908 /* Enable RX checksum */ 1909 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1910 1911 /* setup the mac dma */ 1912 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1913 } 1914 1915 return 0; 1916 } 1917 1918 static int mtk_hw_deinit(struct mtk_eth *eth) 1919 { 1920 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 1921 return 0; 1922 1923 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]); 1924 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]); 1925 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]); 1926 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]); 1927 1928 pm_runtime_put_sync(eth->dev); 1929 pm_runtime_disable(eth->dev); 1930 1931 return 0; 1932 } 1933 1934 static int __init mtk_init(struct net_device *dev) 1935 { 1936 struct mtk_mac *mac = netdev_priv(dev); 1937 struct mtk_eth *eth = mac->hw; 1938 const char *mac_addr; 1939 1940 mac_addr = of_get_mac_address(mac->of_node); 1941 if (mac_addr) 1942 ether_addr_copy(dev->dev_addr, mac_addr); 1943 1944 /* If the mac address is invalid, use random mac address */ 1945 if (!is_valid_ether_addr(dev->dev_addr)) { 1946 eth_hw_addr_random(dev); 1947 dev_err(eth->dev, "generated random MAC address %pM\n", 1948 dev->dev_addr); 1949 } 1950 1951 return mtk_phy_connect(dev); 1952 } 1953 1954 static void mtk_uninit(struct net_device *dev) 1955 { 1956 struct mtk_mac *mac = netdev_priv(dev); 1957 struct mtk_eth *eth = mac->hw; 1958 1959 phy_disconnect(dev->phydev); 1960 if (of_phy_is_fixed_link(mac->of_node)) 1961 of_phy_deregister_fixed_link(mac->of_node); 1962 mtk_tx_irq_disable(eth, ~0); 1963 mtk_rx_irq_disable(eth, ~0); 1964 } 1965 1966 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1967 { 1968 switch (cmd) { 1969 case SIOCGMIIPHY: 1970 case SIOCGMIIREG: 1971 case SIOCSMIIREG: 1972 return phy_mii_ioctl(dev->phydev, ifr, cmd); 1973 default: 1974 break; 1975 } 1976 1977 return -EOPNOTSUPP; 1978 } 1979 1980 static void mtk_pending_work(struct work_struct *work) 1981 { 1982 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 1983 int err, i; 1984 unsigned long restart = 0; 1985 1986 rtnl_lock(); 1987 1988 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 1989 1990 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 1991 cpu_relax(); 1992 1993 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 1994 /* stop all devices to make sure that dma is properly shut down */ 1995 for (i = 0; i < MTK_MAC_COUNT; i++) { 1996 if (!eth->netdev[i]) 1997 continue; 1998 mtk_stop(eth->netdev[i]); 1999 __set_bit(i, &restart); 2000 } 2001 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2002 2003 /* restart underlying hardware such as power, clock, pin mux 2004 * and the connected phy 2005 */ 2006 mtk_hw_deinit(eth); 2007 2008 if (eth->dev->pins) 2009 pinctrl_select_state(eth->dev->pins->p, 2010 eth->dev->pins->default_state); 2011 mtk_hw_init(eth); 2012 2013 for (i = 0; i < MTK_MAC_COUNT; i++) { 2014 if (!eth->mac[i] || 2015 of_phy_is_fixed_link(eth->mac[i]->of_node)) 2016 continue; 2017 err = phy_init_hw(eth->netdev[i]->phydev); 2018 if (err) 2019 dev_err(eth->dev, "%s: PHY init failed.\n", 2020 eth->netdev[i]->name); 2021 } 2022 2023 /* restart DMA and enable IRQs */ 2024 for (i = 0; i < MTK_MAC_COUNT; i++) { 2025 if (!test_bit(i, &restart)) 2026 continue; 2027 err = mtk_open(eth->netdev[i]); 2028 if (err) { 2029 netif_alert(eth, ifup, eth->netdev[i], 2030 "Driver up/down cycle failed, closing device.\n"); 2031 dev_close(eth->netdev[i]); 2032 } 2033 } 2034 2035 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2036 2037 clear_bit_unlock(MTK_RESETTING, ð->state); 2038 2039 rtnl_unlock(); 2040 } 2041 2042 static int mtk_free_dev(struct mtk_eth *eth) 2043 { 2044 int i; 2045 2046 for (i = 0; i < MTK_MAC_COUNT; i++) { 2047 if (!eth->netdev[i]) 2048 continue; 2049 free_netdev(eth->netdev[i]); 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int mtk_unreg_dev(struct mtk_eth *eth) 2056 { 2057 int i; 2058 2059 for (i = 0; i < MTK_MAC_COUNT; i++) { 2060 if (!eth->netdev[i]) 2061 continue; 2062 unregister_netdev(eth->netdev[i]); 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int mtk_cleanup(struct mtk_eth *eth) 2069 { 2070 mtk_unreg_dev(eth); 2071 mtk_free_dev(eth); 2072 cancel_work_sync(ð->pending_work); 2073 2074 return 0; 2075 } 2076 2077 static int mtk_get_link_ksettings(struct net_device *ndev, 2078 struct ethtool_link_ksettings *cmd) 2079 { 2080 struct mtk_mac *mac = netdev_priv(ndev); 2081 2082 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2083 return -EBUSY; 2084 2085 phy_ethtool_ksettings_get(ndev->phydev, cmd); 2086 2087 return 0; 2088 } 2089 2090 static int mtk_set_link_ksettings(struct net_device *ndev, 2091 const struct ethtool_link_ksettings *cmd) 2092 { 2093 struct mtk_mac *mac = netdev_priv(ndev); 2094 2095 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2096 return -EBUSY; 2097 2098 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2099 } 2100 2101 static void mtk_get_drvinfo(struct net_device *dev, 2102 struct ethtool_drvinfo *info) 2103 { 2104 struct mtk_mac *mac = netdev_priv(dev); 2105 2106 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2107 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2108 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2109 } 2110 2111 static u32 mtk_get_msglevel(struct net_device *dev) 2112 { 2113 struct mtk_mac *mac = netdev_priv(dev); 2114 2115 return mac->hw->msg_enable; 2116 } 2117 2118 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2119 { 2120 struct mtk_mac *mac = netdev_priv(dev); 2121 2122 mac->hw->msg_enable = value; 2123 } 2124 2125 static int mtk_nway_reset(struct net_device *dev) 2126 { 2127 struct mtk_mac *mac = netdev_priv(dev); 2128 2129 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2130 return -EBUSY; 2131 2132 return genphy_restart_aneg(dev->phydev); 2133 } 2134 2135 static u32 mtk_get_link(struct net_device *dev) 2136 { 2137 struct mtk_mac *mac = netdev_priv(dev); 2138 int err; 2139 2140 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2141 return -EBUSY; 2142 2143 err = genphy_update_link(dev->phydev); 2144 if (err) 2145 return ethtool_op_get_link(dev); 2146 2147 return dev->phydev->link; 2148 } 2149 2150 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2151 { 2152 int i; 2153 2154 switch (stringset) { 2155 case ETH_SS_STATS: 2156 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2157 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2158 data += ETH_GSTRING_LEN; 2159 } 2160 break; 2161 } 2162 } 2163 2164 static int mtk_get_sset_count(struct net_device *dev, int sset) 2165 { 2166 switch (sset) { 2167 case ETH_SS_STATS: 2168 return ARRAY_SIZE(mtk_ethtool_stats); 2169 default: 2170 return -EOPNOTSUPP; 2171 } 2172 } 2173 2174 static void mtk_get_ethtool_stats(struct net_device *dev, 2175 struct ethtool_stats *stats, u64 *data) 2176 { 2177 struct mtk_mac *mac = netdev_priv(dev); 2178 struct mtk_hw_stats *hwstats = mac->hw_stats; 2179 u64 *data_src, *data_dst; 2180 unsigned int start; 2181 int i; 2182 2183 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2184 return; 2185 2186 if (netif_running(dev) && netif_device_present(dev)) { 2187 if (spin_trylock_bh(&hwstats->stats_lock)) { 2188 mtk_stats_update_mac(mac); 2189 spin_unlock_bh(&hwstats->stats_lock); 2190 } 2191 } 2192 2193 data_src = (u64 *)hwstats; 2194 2195 do { 2196 data_dst = data; 2197 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2198 2199 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2200 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2201 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2202 } 2203 2204 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2205 u32 *rule_locs) 2206 { 2207 int ret = -EOPNOTSUPP; 2208 2209 switch (cmd->cmd) { 2210 case ETHTOOL_GRXRINGS: 2211 if (dev->features & NETIF_F_LRO) { 2212 cmd->data = MTK_MAX_RX_RING_NUM; 2213 ret = 0; 2214 } 2215 break; 2216 case ETHTOOL_GRXCLSRLCNT: 2217 if (dev->features & NETIF_F_LRO) { 2218 struct mtk_mac *mac = netdev_priv(dev); 2219 2220 cmd->rule_cnt = mac->hwlro_ip_cnt; 2221 ret = 0; 2222 } 2223 break; 2224 case ETHTOOL_GRXCLSRULE: 2225 if (dev->features & NETIF_F_LRO) 2226 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2227 break; 2228 case ETHTOOL_GRXCLSRLALL: 2229 if (dev->features & NETIF_F_LRO) 2230 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2231 rule_locs); 2232 break; 2233 default: 2234 break; 2235 } 2236 2237 return ret; 2238 } 2239 2240 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2241 { 2242 int ret = -EOPNOTSUPP; 2243 2244 switch (cmd->cmd) { 2245 case ETHTOOL_SRXCLSRLINS: 2246 if (dev->features & NETIF_F_LRO) 2247 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2248 break; 2249 case ETHTOOL_SRXCLSRLDEL: 2250 if (dev->features & NETIF_F_LRO) 2251 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2252 break; 2253 default: 2254 break; 2255 } 2256 2257 return ret; 2258 } 2259 2260 static const struct ethtool_ops mtk_ethtool_ops = { 2261 .get_link_ksettings = mtk_get_link_ksettings, 2262 .set_link_ksettings = mtk_set_link_ksettings, 2263 .get_drvinfo = mtk_get_drvinfo, 2264 .get_msglevel = mtk_get_msglevel, 2265 .set_msglevel = mtk_set_msglevel, 2266 .nway_reset = mtk_nway_reset, 2267 .get_link = mtk_get_link, 2268 .get_strings = mtk_get_strings, 2269 .get_sset_count = mtk_get_sset_count, 2270 .get_ethtool_stats = mtk_get_ethtool_stats, 2271 .get_rxnfc = mtk_get_rxnfc, 2272 .set_rxnfc = mtk_set_rxnfc, 2273 }; 2274 2275 static const struct net_device_ops mtk_netdev_ops = { 2276 .ndo_init = mtk_init, 2277 .ndo_uninit = mtk_uninit, 2278 .ndo_open = mtk_open, 2279 .ndo_stop = mtk_stop, 2280 .ndo_start_xmit = mtk_start_xmit, 2281 .ndo_set_mac_address = mtk_set_mac_address, 2282 .ndo_validate_addr = eth_validate_addr, 2283 .ndo_do_ioctl = mtk_do_ioctl, 2284 .ndo_tx_timeout = mtk_tx_timeout, 2285 .ndo_get_stats64 = mtk_get_stats64, 2286 .ndo_fix_features = mtk_fix_features, 2287 .ndo_set_features = mtk_set_features, 2288 #ifdef CONFIG_NET_POLL_CONTROLLER 2289 .ndo_poll_controller = mtk_poll_controller, 2290 #endif 2291 }; 2292 2293 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2294 { 2295 struct mtk_mac *mac; 2296 const __be32 *_id = of_get_property(np, "reg", NULL); 2297 int id, err; 2298 2299 if (!_id) { 2300 dev_err(eth->dev, "missing mac id\n"); 2301 return -EINVAL; 2302 } 2303 2304 id = be32_to_cpup(_id); 2305 if (id >= MTK_MAC_COUNT) { 2306 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2307 return -EINVAL; 2308 } 2309 2310 if (eth->netdev[id]) { 2311 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2312 return -EINVAL; 2313 } 2314 2315 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2316 if (!eth->netdev[id]) { 2317 dev_err(eth->dev, "alloc_etherdev failed\n"); 2318 return -ENOMEM; 2319 } 2320 mac = netdev_priv(eth->netdev[id]); 2321 eth->mac[id] = mac; 2322 mac->id = id; 2323 mac->hw = eth; 2324 mac->of_node = np; 2325 2326 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2327 mac->hwlro_ip_cnt = 0; 2328 2329 mac->hw_stats = devm_kzalloc(eth->dev, 2330 sizeof(*mac->hw_stats), 2331 GFP_KERNEL); 2332 if (!mac->hw_stats) { 2333 dev_err(eth->dev, "failed to allocate counter memory\n"); 2334 err = -ENOMEM; 2335 goto free_netdev; 2336 } 2337 spin_lock_init(&mac->hw_stats->stats_lock); 2338 u64_stats_init(&mac->hw_stats->syncp); 2339 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2340 2341 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2342 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2343 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2344 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2345 2346 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2347 if (eth->hwlro) 2348 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2349 2350 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2351 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2352 eth->netdev[id]->features |= MTK_HW_FEATURES; 2353 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2354 2355 eth->netdev[id]->irq = eth->irq[0]; 2356 eth->netdev[id]->dev.of_node = np; 2357 2358 return 0; 2359 2360 free_netdev: 2361 free_netdev(eth->netdev[id]); 2362 return err; 2363 } 2364 2365 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id) 2366 { 2367 u32 val[2], id[4]; 2368 2369 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]); 2370 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]); 2371 2372 id[3] = ((val[0] >> 16) & 0xff) - '0'; 2373 id[2] = ((val[0] >> 24) & 0xff) - '0'; 2374 id[1] = (val[1] & 0xff) - '0'; 2375 id[0] = ((val[1] >> 8) & 0xff) - '0'; 2376 2377 *chip_id = (id[3] * 1000) + (id[2] * 100) + 2378 (id[1] * 10) + id[0]; 2379 2380 if (!(*chip_id)) { 2381 dev_err(eth->dev, "failed to get chip id\n"); 2382 return -ENODEV; 2383 } 2384 2385 dev_info(eth->dev, "chip id = %d\n", *chip_id); 2386 2387 return 0; 2388 } 2389 2390 static bool mtk_is_hwlro_supported(struct mtk_eth *eth) 2391 { 2392 switch (eth->chip_id) { 2393 case MT7623_ETH: 2394 return true; 2395 } 2396 2397 return false; 2398 } 2399 2400 static int mtk_probe(struct platform_device *pdev) 2401 { 2402 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2403 struct device_node *mac_np; 2404 struct mtk_eth *eth; 2405 int err; 2406 int i; 2407 2408 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2409 if (!eth) 2410 return -ENOMEM; 2411 2412 eth->dev = &pdev->dev; 2413 eth->base = devm_ioremap_resource(&pdev->dev, res); 2414 if (IS_ERR(eth->base)) 2415 return PTR_ERR(eth->base); 2416 2417 spin_lock_init(ð->page_lock); 2418 spin_lock_init(ð->tx_irq_lock); 2419 spin_lock_init(ð->rx_irq_lock); 2420 2421 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2422 "mediatek,ethsys"); 2423 if (IS_ERR(eth->ethsys)) { 2424 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2425 return PTR_ERR(eth->ethsys); 2426 } 2427 2428 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2429 "mediatek,pctl"); 2430 if (IS_ERR(eth->pctl)) { 2431 dev_err(&pdev->dev, "no pctl regmap found\n"); 2432 return PTR_ERR(eth->pctl); 2433 } 2434 2435 for (i = 0; i < 3; i++) { 2436 eth->irq[i] = platform_get_irq(pdev, i); 2437 if (eth->irq[i] < 0) { 2438 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2439 return -ENXIO; 2440 } 2441 } 2442 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2443 eth->clks[i] = devm_clk_get(eth->dev, 2444 mtk_clks_source_name[i]); 2445 if (IS_ERR(eth->clks[i])) { 2446 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2447 return -EPROBE_DEFER; 2448 return -ENODEV; 2449 } 2450 } 2451 2452 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2453 INIT_WORK(ð->pending_work, mtk_pending_work); 2454 2455 err = mtk_hw_init(eth); 2456 if (err) 2457 return err; 2458 2459 err = mtk_get_chip_id(eth, ð->chip_id); 2460 if (err) 2461 return err; 2462 2463 eth->hwlro = mtk_is_hwlro_supported(eth); 2464 2465 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2466 if (!of_device_is_compatible(mac_np, 2467 "mediatek,eth-mac")) 2468 continue; 2469 2470 if (!of_device_is_available(mac_np)) 2471 continue; 2472 2473 err = mtk_add_mac(eth, mac_np); 2474 if (err) 2475 goto err_deinit_hw; 2476 } 2477 2478 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 2479 dev_name(eth->dev), eth); 2480 if (err) 2481 goto err_free_dev; 2482 2483 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 2484 dev_name(eth->dev), eth); 2485 if (err) 2486 goto err_free_dev; 2487 2488 err = mtk_mdio_init(eth); 2489 if (err) 2490 goto err_free_dev; 2491 2492 for (i = 0; i < MTK_MAX_DEVS; i++) { 2493 if (!eth->netdev[i]) 2494 continue; 2495 2496 err = register_netdev(eth->netdev[i]); 2497 if (err) { 2498 dev_err(eth->dev, "error bringing up device\n"); 2499 goto err_deinit_mdio; 2500 } else 2501 netif_info(eth, probe, eth->netdev[i], 2502 "mediatek frame engine at 0x%08lx, irq %d\n", 2503 eth->netdev[i]->base_addr, eth->irq[0]); 2504 } 2505 2506 /* we run 2 devices on the same DMA ring so we need a dummy device 2507 * for NAPI to work 2508 */ 2509 init_dummy_netdev(ð->dummy_dev); 2510 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2511 MTK_NAPI_WEIGHT); 2512 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2513 MTK_NAPI_WEIGHT); 2514 2515 platform_set_drvdata(pdev, eth); 2516 2517 return 0; 2518 2519 err_deinit_mdio: 2520 mtk_mdio_cleanup(eth); 2521 err_free_dev: 2522 mtk_free_dev(eth); 2523 err_deinit_hw: 2524 mtk_hw_deinit(eth); 2525 2526 return err; 2527 } 2528 2529 static int mtk_remove(struct platform_device *pdev) 2530 { 2531 struct mtk_eth *eth = platform_get_drvdata(pdev); 2532 int i; 2533 2534 /* stop all devices to make sure that dma is properly shut down */ 2535 for (i = 0; i < MTK_MAC_COUNT; i++) { 2536 if (!eth->netdev[i]) 2537 continue; 2538 mtk_stop(eth->netdev[i]); 2539 } 2540 2541 mtk_hw_deinit(eth); 2542 2543 netif_napi_del(ð->tx_napi); 2544 netif_napi_del(ð->rx_napi); 2545 mtk_cleanup(eth); 2546 mtk_mdio_cleanup(eth); 2547 2548 return 0; 2549 } 2550 2551 const struct of_device_id of_mtk_match[] = { 2552 { .compatible = "mediatek,mt2701-eth" }, 2553 {}, 2554 }; 2555 MODULE_DEVICE_TABLE(of, of_mtk_match); 2556 2557 static struct platform_driver mtk_driver = { 2558 .probe = mtk_probe, 2559 .remove = mtk_remove, 2560 .driver = { 2561 .name = "mtk_soc_eth", 2562 .of_match_table = of_mtk_match, 2563 }, 2564 }; 2565 2566 module_platform_driver(mtk_driver); 2567 2568 MODULE_LICENSE("GPL"); 2569 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2570 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2571