1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 23 #include "mtk_eth_soc.h" 24 25 static int mtk_msg_level = -1; 26 module_param_named(msg_level, mtk_msg_level, int, 0); 27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 28 29 #define MTK_ETHTOOL_STAT(x) { #x, \ 30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 31 32 /* strings used by ethtool */ 33 static const struct mtk_ethtool_stats { 34 char str[ETH_GSTRING_LEN]; 35 u32 offset; 36 } mtk_ethtool_stats[] = { 37 MTK_ETHTOOL_STAT(tx_bytes), 38 MTK_ETHTOOL_STAT(tx_packets), 39 MTK_ETHTOOL_STAT(tx_skip), 40 MTK_ETHTOOL_STAT(tx_collisions), 41 MTK_ETHTOOL_STAT(rx_bytes), 42 MTK_ETHTOOL_STAT(rx_packets), 43 MTK_ETHTOOL_STAT(rx_overflow), 44 MTK_ETHTOOL_STAT(rx_fcs_errors), 45 MTK_ETHTOOL_STAT(rx_short_errors), 46 MTK_ETHTOOL_STAT(rx_long_errors), 47 MTK_ETHTOOL_STAT(rx_checksum_errors), 48 MTK_ETHTOOL_STAT(rx_flow_control_packets), 49 }; 50 51 static const char * const mtk_clks_source_name[] = { 52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 55 "sgmii_ck", "eth2pll", 56 }; 57 58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 59 { 60 __raw_writel(val, eth->base + reg); 61 } 62 63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 64 { 65 return __raw_readl(eth->base + reg); 66 } 67 68 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 69 { 70 u32 val; 71 72 val = mtk_r32(eth, reg); 73 val &= ~mask; 74 val |= set; 75 mtk_w32(eth, val, reg); 76 return reg; 77 } 78 79 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 80 { 81 unsigned long t_start = jiffies; 82 83 while (1) { 84 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 85 return 0; 86 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 87 break; 88 usleep_range(10, 20); 89 } 90 91 dev_err(eth->dev, "mdio: MDIO timeout\n"); 92 return -1; 93 } 94 95 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 96 u32 phy_register, u32 write_data) 97 { 98 if (mtk_mdio_busy_wait(eth)) 99 return -1; 100 101 write_data &= 0xffff; 102 103 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 104 (phy_register << PHY_IAC_REG_SHIFT) | 105 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 106 MTK_PHY_IAC); 107 108 if (mtk_mdio_busy_wait(eth)) 109 return -1; 110 111 return 0; 112 } 113 114 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 115 { 116 u32 d; 117 118 if (mtk_mdio_busy_wait(eth)) 119 return 0xffff; 120 121 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 122 (phy_reg << PHY_IAC_REG_SHIFT) | 123 (phy_addr << PHY_IAC_ADDR_SHIFT), 124 MTK_PHY_IAC); 125 126 if (mtk_mdio_busy_wait(eth)) 127 return 0xffff; 128 129 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 130 131 return d; 132 } 133 134 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 135 int phy_reg, u16 val) 136 { 137 struct mtk_eth *eth = bus->priv; 138 139 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 140 } 141 142 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 143 { 144 struct mtk_eth *eth = bus->priv; 145 146 return _mtk_mdio_read(eth, phy_addr, phy_reg); 147 } 148 149 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 150 phy_interface_t interface) 151 { 152 u32 val; 153 154 /* Check DDR memory type. 155 * Currently TRGMII mode with DDR2 memory is not supported. 156 */ 157 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 158 if (interface == PHY_INTERFACE_MODE_TRGMII && 159 val & SYSCFG_DRAM_TYPE_DDR2) { 160 dev_err(eth->dev, 161 "TRGMII mode with DDR2 memory is not supported!\n"); 162 return -EOPNOTSUPP; 163 } 164 165 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 166 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 167 168 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 169 ETHSYS_TRGMII_MT7621_MASK, val); 170 171 return 0; 172 } 173 174 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 175 phy_interface_t interface, int speed) 176 { 177 u32 val; 178 int ret; 179 180 if (interface == PHY_INTERFACE_MODE_TRGMII) { 181 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 182 val = 500000000; 183 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 184 if (ret) 185 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 186 return; 187 } 188 189 val = (speed == SPEED_1000) ? 190 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 191 mtk_w32(eth, val, INTF_MODE); 192 193 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 194 ETHSYS_TRGMII_CLK_SEL362_5, 195 ETHSYS_TRGMII_CLK_SEL362_5); 196 197 val = (speed == SPEED_1000) ? 250000000 : 500000000; 198 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 199 if (ret) 200 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 201 202 val = (speed == SPEED_1000) ? 203 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 204 mtk_w32(eth, val, TRGMII_RCK_CTRL); 205 206 val = (speed == SPEED_1000) ? 207 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 208 mtk_w32(eth, val, TRGMII_TCK_CTRL); 209 } 210 211 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 212 const struct phylink_link_state *state) 213 { 214 struct mtk_mac *mac = container_of(config, struct mtk_mac, 215 phylink_config); 216 struct mtk_eth *eth = mac->hw; 217 u32 mcr_cur, mcr_new, sid, i; 218 int val, ge_mode, err; 219 220 /* MT76x8 has no hardware settings between for the MAC */ 221 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 222 mac->interface != state->interface) { 223 /* Setup soc pin functions */ 224 switch (state->interface) { 225 case PHY_INTERFACE_MODE_TRGMII: 226 if (mac->id) 227 goto err_phy; 228 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 229 MTK_GMAC1_TRGMII)) 230 goto err_phy; 231 /* fall through */ 232 case PHY_INTERFACE_MODE_RGMII_TXID: 233 case PHY_INTERFACE_MODE_RGMII_RXID: 234 case PHY_INTERFACE_MODE_RGMII_ID: 235 case PHY_INTERFACE_MODE_RGMII: 236 case PHY_INTERFACE_MODE_MII: 237 case PHY_INTERFACE_MODE_REVMII: 238 case PHY_INTERFACE_MODE_RMII: 239 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 240 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 241 if (err) 242 goto init_err; 243 } 244 break; 245 case PHY_INTERFACE_MODE_1000BASEX: 246 case PHY_INTERFACE_MODE_2500BASEX: 247 case PHY_INTERFACE_MODE_SGMII: 248 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 249 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 250 if (err) 251 goto init_err; 252 } 253 break; 254 case PHY_INTERFACE_MODE_GMII: 255 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 256 err = mtk_gmac_gephy_path_setup(eth, mac->id); 257 if (err) 258 goto init_err; 259 } 260 break; 261 default: 262 goto err_phy; 263 } 264 265 /* Setup clock for 1st gmac */ 266 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 267 !phy_interface_mode_is_8023z(state->interface) && 268 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 269 if (MTK_HAS_CAPS(mac->hw->soc->caps, 270 MTK_TRGMII_MT7621_CLK)) { 271 if (mt7621_gmac0_rgmii_adjust(mac->hw, 272 state->interface)) 273 goto err_phy; 274 } else { 275 mtk_gmac0_rgmii_adjust(mac->hw, 276 state->interface, 277 state->speed); 278 279 /* mt7623_pad_clk_setup */ 280 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 281 mtk_w32(mac->hw, 282 TD_DM_DRVP(8) | TD_DM_DRVN(8), 283 TRGMII_TD_ODT(i)); 284 285 /* Assert/release MT7623 RXC reset */ 286 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 287 TRGMII_RCK_CTRL); 288 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 289 } 290 } 291 292 ge_mode = 0; 293 switch (state->interface) { 294 case PHY_INTERFACE_MODE_MII: 295 case PHY_INTERFACE_MODE_GMII: 296 ge_mode = 1; 297 break; 298 case PHY_INTERFACE_MODE_REVMII: 299 ge_mode = 2; 300 break; 301 case PHY_INTERFACE_MODE_RMII: 302 if (mac->id) 303 goto err_phy; 304 ge_mode = 3; 305 break; 306 default: 307 break; 308 } 309 310 /* put the gmac into the right mode */ 311 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 312 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 313 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 314 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 315 316 mac->interface = state->interface; 317 } 318 319 /* SGMII */ 320 if (state->interface == PHY_INTERFACE_MODE_SGMII || 321 phy_interface_mode_is_8023z(state->interface)) { 322 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 323 * being setup done. 324 */ 325 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 326 327 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 328 SYSCFG0_SGMII_MASK, 329 ~(u32)SYSCFG0_SGMII_MASK); 330 331 /* Decide how GMAC and SGMIISYS be mapped */ 332 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 333 0 : mac->id; 334 335 /* Setup SGMIISYS with the determined property */ 336 if (state->interface != PHY_INTERFACE_MODE_SGMII) 337 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 338 state); 339 else if (phylink_autoneg_inband(mode)) 340 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 341 342 if (err) 343 goto init_err; 344 345 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 346 SYSCFG0_SGMII_MASK, val); 347 } else if (phylink_autoneg_inband(mode)) { 348 dev_err(eth->dev, 349 "In-band mode not supported in non SGMII mode!\n"); 350 return; 351 } 352 353 /* Setup gmac */ 354 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 355 mcr_new = mcr_cur; 356 mcr_new &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 357 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 358 MAC_MCR_FORCE_RX_FC); 359 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 360 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 361 362 switch (state->speed) { 363 case SPEED_2500: 364 case SPEED_1000: 365 mcr_new |= MAC_MCR_SPEED_1000; 366 break; 367 case SPEED_100: 368 mcr_new |= MAC_MCR_SPEED_100; 369 break; 370 } 371 if (state->duplex == DUPLEX_FULL) { 372 mcr_new |= MAC_MCR_FORCE_DPX; 373 if (state->pause & MLO_PAUSE_TX) 374 mcr_new |= MAC_MCR_FORCE_TX_FC; 375 if (state->pause & MLO_PAUSE_RX) 376 mcr_new |= MAC_MCR_FORCE_RX_FC; 377 } 378 379 /* Only update control register when needed! */ 380 if (mcr_new != mcr_cur) 381 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 382 383 return; 384 385 err_phy: 386 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 387 mac->id, phy_modes(state->interface)); 388 return; 389 390 init_err: 391 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 392 mac->id, phy_modes(state->interface), err); 393 } 394 395 static void mtk_mac_pcs_get_state(struct phylink_config *config, 396 struct phylink_link_state *state) 397 { 398 struct mtk_mac *mac = container_of(config, struct mtk_mac, 399 phylink_config); 400 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 401 402 state->link = (pmsr & MAC_MSR_LINK); 403 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 404 405 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 406 case 0: 407 state->speed = SPEED_10; 408 break; 409 case MAC_MSR_SPEED_100: 410 state->speed = SPEED_100; 411 break; 412 case MAC_MSR_SPEED_1000: 413 state->speed = SPEED_1000; 414 break; 415 default: 416 state->speed = SPEED_UNKNOWN; 417 break; 418 } 419 420 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 421 if (pmsr & MAC_MSR_RX_FC) 422 state->pause |= MLO_PAUSE_RX; 423 if (pmsr & MAC_MSR_TX_FC) 424 state->pause |= MLO_PAUSE_TX; 425 } 426 427 static void mtk_mac_an_restart(struct phylink_config *config) 428 { 429 struct mtk_mac *mac = container_of(config, struct mtk_mac, 430 phylink_config); 431 432 mtk_sgmii_restart_an(mac->hw, mac->id); 433 } 434 435 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 436 phy_interface_t interface) 437 { 438 struct mtk_mac *mac = container_of(config, struct mtk_mac, 439 phylink_config); 440 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 441 442 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 443 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 444 } 445 446 static void mtk_mac_link_up(struct phylink_config *config, 447 struct phy_device *phy, 448 unsigned int mode, phy_interface_t interface, 449 int speed, int duplex, bool tx_pause, bool rx_pause) 450 { 451 struct mtk_mac *mac = container_of(config, struct mtk_mac, 452 phylink_config); 453 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 454 455 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 456 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 457 } 458 459 static void mtk_validate(struct phylink_config *config, 460 unsigned long *supported, 461 struct phylink_link_state *state) 462 { 463 struct mtk_mac *mac = container_of(config, struct mtk_mac, 464 phylink_config); 465 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 466 467 if (state->interface != PHY_INTERFACE_MODE_NA && 468 state->interface != PHY_INTERFACE_MODE_MII && 469 state->interface != PHY_INTERFACE_MODE_GMII && 470 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && 471 phy_interface_mode_is_rgmii(state->interface)) && 472 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && 473 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && 474 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && 475 (state->interface == PHY_INTERFACE_MODE_SGMII || 476 phy_interface_mode_is_8023z(state->interface)))) { 477 linkmode_zero(supported); 478 return; 479 } 480 481 phylink_set_port_modes(mask); 482 phylink_set(mask, Autoneg); 483 484 switch (state->interface) { 485 case PHY_INTERFACE_MODE_TRGMII: 486 phylink_set(mask, 1000baseT_Full); 487 break; 488 case PHY_INTERFACE_MODE_1000BASEX: 489 case PHY_INTERFACE_MODE_2500BASEX: 490 phylink_set(mask, 1000baseX_Full); 491 phylink_set(mask, 2500baseX_Full); 492 break; 493 case PHY_INTERFACE_MODE_GMII: 494 case PHY_INTERFACE_MODE_RGMII: 495 case PHY_INTERFACE_MODE_RGMII_ID: 496 case PHY_INTERFACE_MODE_RGMII_RXID: 497 case PHY_INTERFACE_MODE_RGMII_TXID: 498 phylink_set(mask, 1000baseT_Half); 499 /* fall through */ 500 case PHY_INTERFACE_MODE_SGMII: 501 phylink_set(mask, 1000baseT_Full); 502 phylink_set(mask, 1000baseX_Full); 503 /* fall through */ 504 case PHY_INTERFACE_MODE_MII: 505 case PHY_INTERFACE_MODE_RMII: 506 case PHY_INTERFACE_MODE_REVMII: 507 case PHY_INTERFACE_MODE_NA: 508 default: 509 phylink_set(mask, 10baseT_Half); 510 phylink_set(mask, 10baseT_Full); 511 phylink_set(mask, 100baseT_Half); 512 phylink_set(mask, 100baseT_Full); 513 break; 514 } 515 516 if (state->interface == PHY_INTERFACE_MODE_NA) { 517 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 518 phylink_set(mask, 1000baseT_Full); 519 phylink_set(mask, 1000baseX_Full); 520 phylink_set(mask, 2500baseX_Full); 521 } 522 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { 523 phylink_set(mask, 1000baseT_Full); 524 phylink_set(mask, 1000baseT_Half); 525 phylink_set(mask, 1000baseX_Full); 526 } 527 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { 528 phylink_set(mask, 1000baseT_Full); 529 phylink_set(mask, 1000baseT_Half); 530 } 531 } 532 533 phylink_set(mask, Pause); 534 phylink_set(mask, Asym_Pause); 535 536 linkmode_and(supported, supported, mask); 537 linkmode_and(state->advertising, state->advertising, mask); 538 539 /* We can only operate at 2500BaseX or 1000BaseX. If requested 540 * to advertise both, only report advertising at 2500BaseX. 541 */ 542 phylink_helper_basex_speed(state); 543 } 544 545 static const struct phylink_mac_ops mtk_phylink_ops = { 546 .validate = mtk_validate, 547 .mac_pcs_get_state = mtk_mac_pcs_get_state, 548 .mac_an_restart = mtk_mac_an_restart, 549 .mac_config = mtk_mac_config, 550 .mac_link_down = mtk_mac_link_down, 551 .mac_link_up = mtk_mac_link_up, 552 }; 553 554 static int mtk_mdio_init(struct mtk_eth *eth) 555 { 556 struct device_node *mii_np; 557 int ret; 558 559 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 560 if (!mii_np) { 561 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 562 return -ENODEV; 563 } 564 565 if (!of_device_is_available(mii_np)) { 566 ret = -ENODEV; 567 goto err_put_node; 568 } 569 570 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 571 if (!eth->mii_bus) { 572 ret = -ENOMEM; 573 goto err_put_node; 574 } 575 576 eth->mii_bus->name = "mdio"; 577 eth->mii_bus->read = mtk_mdio_read; 578 eth->mii_bus->write = mtk_mdio_write; 579 eth->mii_bus->priv = eth; 580 eth->mii_bus->parent = eth->dev; 581 582 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 583 ret = of_mdiobus_register(eth->mii_bus, mii_np); 584 585 err_put_node: 586 of_node_put(mii_np); 587 return ret; 588 } 589 590 static void mtk_mdio_cleanup(struct mtk_eth *eth) 591 { 592 if (!eth->mii_bus) 593 return; 594 595 mdiobus_unregister(eth->mii_bus); 596 } 597 598 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 599 { 600 unsigned long flags; 601 u32 val; 602 603 spin_lock_irqsave(ð->tx_irq_lock, flags); 604 val = mtk_r32(eth, eth->tx_int_mask_reg); 605 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 606 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 607 } 608 609 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 610 { 611 unsigned long flags; 612 u32 val; 613 614 spin_lock_irqsave(ð->tx_irq_lock, flags); 615 val = mtk_r32(eth, eth->tx_int_mask_reg); 616 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 617 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 618 } 619 620 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 621 { 622 unsigned long flags; 623 u32 val; 624 625 spin_lock_irqsave(ð->rx_irq_lock, flags); 626 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 627 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 628 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 629 } 630 631 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 632 { 633 unsigned long flags; 634 u32 val; 635 636 spin_lock_irqsave(ð->rx_irq_lock, flags); 637 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 638 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 639 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 640 } 641 642 static int mtk_set_mac_address(struct net_device *dev, void *p) 643 { 644 int ret = eth_mac_addr(dev, p); 645 struct mtk_mac *mac = netdev_priv(dev); 646 struct mtk_eth *eth = mac->hw; 647 const char *macaddr = dev->dev_addr; 648 649 if (ret) 650 return ret; 651 652 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 653 return -EBUSY; 654 655 spin_lock_bh(&mac->hw->page_lock); 656 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 657 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 658 MT7628_SDM_MAC_ADRH); 659 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 660 (macaddr[4] << 8) | macaddr[5], 661 MT7628_SDM_MAC_ADRL); 662 } else { 663 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 664 MTK_GDMA_MAC_ADRH(mac->id)); 665 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 666 (macaddr[4] << 8) | macaddr[5], 667 MTK_GDMA_MAC_ADRL(mac->id)); 668 } 669 spin_unlock_bh(&mac->hw->page_lock); 670 671 return 0; 672 } 673 674 void mtk_stats_update_mac(struct mtk_mac *mac) 675 { 676 struct mtk_hw_stats *hw_stats = mac->hw_stats; 677 unsigned int base = MTK_GDM1_TX_GBCNT; 678 u64 stats; 679 680 base += hw_stats->reg_offset; 681 682 u64_stats_update_begin(&hw_stats->syncp); 683 684 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 685 stats = mtk_r32(mac->hw, base + 0x04); 686 if (stats) 687 hw_stats->rx_bytes += (stats << 32); 688 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 689 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 690 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 691 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 692 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 693 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 694 hw_stats->rx_flow_control_packets += 695 mtk_r32(mac->hw, base + 0x24); 696 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 697 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 698 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 699 stats = mtk_r32(mac->hw, base + 0x34); 700 if (stats) 701 hw_stats->tx_bytes += (stats << 32); 702 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 703 u64_stats_update_end(&hw_stats->syncp); 704 } 705 706 static void mtk_stats_update(struct mtk_eth *eth) 707 { 708 int i; 709 710 for (i = 0; i < MTK_MAC_COUNT; i++) { 711 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 712 continue; 713 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 714 mtk_stats_update_mac(eth->mac[i]); 715 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 716 } 717 } 718 } 719 720 static void mtk_get_stats64(struct net_device *dev, 721 struct rtnl_link_stats64 *storage) 722 { 723 struct mtk_mac *mac = netdev_priv(dev); 724 struct mtk_hw_stats *hw_stats = mac->hw_stats; 725 unsigned int start; 726 727 if (netif_running(dev) && netif_device_present(dev)) { 728 if (spin_trylock_bh(&hw_stats->stats_lock)) { 729 mtk_stats_update_mac(mac); 730 spin_unlock_bh(&hw_stats->stats_lock); 731 } 732 } 733 734 do { 735 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 736 storage->rx_packets = hw_stats->rx_packets; 737 storage->tx_packets = hw_stats->tx_packets; 738 storage->rx_bytes = hw_stats->rx_bytes; 739 storage->tx_bytes = hw_stats->tx_bytes; 740 storage->collisions = hw_stats->tx_collisions; 741 storage->rx_length_errors = hw_stats->rx_short_errors + 742 hw_stats->rx_long_errors; 743 storage->rx_over_errors = hw_stats->rx_overflow; 744 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 745 storage->rx_errors = hw_stats->rx_checksum_errors; 746 storage->tx_aborted_errors = hw_stats->tx_skip; 747 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 748 749 storage->tx_errors = dev->stats.tx_errors; 750 storage->rx_dropped = dev->stats.rx_dropped; 751 storage->tx_dropped = dev->stats.tx_dropped; 752 } 753 754 static inline int mtk_max_frag_size(int mtu) 755 { 756 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 757 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 758 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 759 760 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 761 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 762 } 763 764 static inline int mtk_max_buf_size(int frag_size) 765 { 766 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 767 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 768 769 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 770 771 return buf_size; 772 } 773 774 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 775 struct mtk_rx_dma *dma_rxd) 776 { 777 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 778 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 779 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 780 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 781 } 782 783 /* the qdma core needs scratch memory to be setup */ 784 static int mtk_init_fq_dma(struct mtk_eth *eth) 785 { 786 dma_addr_t phy_ring_tail; 787 int cnt = MTK_DMA_SIZE; 788 dma_addr_t dma_addr; 789 int i; 790 791 eth->scratch_ring = dma_alloc_coherent(eth->dev, 792 cnt * sizeof(struct mtk_tx_dma), 793 ð->phy_scratch_ring, 794 GFP_ATOMIC); 795 if (unlikely(!eth->scratch_ring)) 796 return -ENOMEM; 797 798 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 799 GFP_KERNEL); 800 if (unlikely(!eth->scratch_head)) 801 return -ENOMEM; 802 803 dma_addr = dma_map_single(eth->dev, 804 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 805 DMA_FROM_DEVICE); 806 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 807 return -ENOMEM; 808 809 phy_ring_tail = eth->phy_scratch_ring + 810 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 811 812 for (i = 0; i < cnt; i++) { 813 eth->scratch_ring[i].txd1 = 814 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 815 if (i < cnt - 1) 816 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 817 ((i + 1) * sizeof(struct mtk_tx_dma))); 818 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 819 } 820 821 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 822 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 823 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 824 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 825 826 return 0; 827 } 828 829 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 830 { 831 void *ret = ring->dma; 832 833 return ret + (desc - ring->phys); 834 } 835 836 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 837 struct mtk_tx_dma *txd) 838 { 839 int idx = txd - ring->dma; 840 841 return &ring->buf[idx]; 842 } 843 844 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 845 struct mtk_tx_dma *dma) 846 { 847 return ring->dma_pdma - ring->dma + dma; 848 } 849 850 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 851 { 852 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 853 } 854 855 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 856 { 857 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 858 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 859 dma_unmap_single(eth->dev, 860 dma_unmap_addr(tx_buf, dma_addr0), 861 dma_unmap_len(tx_buf, dma_len0), 862 DMA_TO_DEVICE); 863 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 864 dma_unmap_page(eth->dev, 865 dma_unmap_addr(tx_buf, dma_addr0), 866 dma_unmap_len(tx_buf, dma_len0), 867 DMA_TO_DEVICE); 868 } 869 } else { 870 if (dma_unmap_len(tx_buf, dma_len0)) { 871 dma_unmap_page(eth->dev, 872 dma_unmap_addr(tx_buf, dma_addr0), 873 dma_unmap_len(tx_buf, dma_len0), 874 DMA_TO_DEVICE); 875 } 876 877 if (dma_unmap_len(tx_buf, dma_len1)) { 878 dma_unmap_page(eth->dev, 879 dma_unmap_addr(tx_buf, dma_addr1), 880 dma_unmap_len(tx_buf, dma_len1), 881 DMA_TO_DEVICE); 882 } 883 } 884 885 tx_buf->flags = 0; 886 if (tx_buf->skb && 887 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 888 dev_kfree_skb_any(tx_buf->skb); 889 tx_buf->skb = NULL; 890 } 891 892 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 893 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 894 size_t size, int idx) 895 { 896 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 897 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 898 dma_unmap_len_set(tx_buf, dma_len0, size); 899 } else { 900 if (idx & 1) { 901 txd->txd3 = mapped_addr; 902 txd->txd2 |= TX_DMA_PLEN1(size); 903 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 904 dma_unmap_len_set(tx_buf, dma_len1, size); 905 } else { 906 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 907 txd->txd1 = mapped_addr; 908 txd->txd2 = TX_DMA_PLEN0(size); 909 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 910 dma_unmap_len_set(tx_buf, dma_len0, size); 911 } 912 } 913 } 914 915 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 916 int tx_num, struct mtk_tx_ring *ring, bool gso) 917 { 918 struct mtk_mac *mac = netdev_priv(dev); 919 struct mtk_eth *eth = mac->hw; 920 struct mtk_tx_dma *itxd, *txd; 921 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 922 struct mtk_tx_buf *itx_buf, *tx_buf; 923 dma_addr_t mapped_addr; 924 unsigned int nr_frags; 925 int i, n_desc = 1; 926 u32 txd4 = 0, fport; 927 int k = 0; 928 929 itxd = ring->next_free; 930 itxd_pdma = qdma_to_pdma(ring, itxd); 931 if (itxd == ring->last_free) 932 return -ENOMEM; 933 934 /* set the forward port */ 935 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 936 txd4 |= fport; 937 938 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 939 memset(itx_buf, 0, sizeof(*itx_buf)); 940 941 if (gso) 942 txd4 |= TX_DMA_TSO; 943 944 /* TX Checksum offload */ 945 if (skb->ip_summed == CHECKSUM_PARTIAL) 946 txd4 |= TX_DMA_CHKSUM; 947 948 /* VLAN header offload */ 949 if (skb_vlan_tag_present(skb)) 950 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 951 952 mapped_addr = dma_map_single(eth->dev, skb->data, 953 skb_headlen(skb), DMA_TO_DEVICE); 954 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 955 return -ENOMEM; 956 957 WRITE_ONCE(itxd->txd1, mapped_addr); 958 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 959 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 960 MTK_TX_FLAGS_FPORT1; 961 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 962 k++); 963 964 /* TX SG offload */ 965 txd = itxd; 966 txd_pdma = qdma_to_pdma(ring, txd); 967 nr_frags = skb_shinfo(skb)->nr_frags; 968 969 for (i = 0; i < nr_frags; i++) { 970 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 971 unsigned int offset = 0; 972 int frag_size = skb_frag_size(frag); 973 974 while (frag_size) { 975 bool last_frag = false; 976 unsigned int frag_map_size; 977 bool new_desc = true; 978 979 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 980 (i & 0x1)) { 981 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 982 txd_pdma = qdma_to_pdma(ring, txd); 983 if (txd == ring->last_free) 984 goto err_dma; 985 986 n_desc++; 987 } else { 988 new_desc = false; 989 } 990 991 992 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 993 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 994 frag_map_size, 995 DMA_TO_DEVICE); 996 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 997 goto err_dma; 998 999 if (i == nr_frags - 1 && 1000 (frag_size - frag_map_size) == 0) 1001 last_frag = true; 1002 1003 WRITE_ONCE(txd->txd1, mapped_addr); 1004 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 1005 TX_DMA_PLEN0(frag_map_size) | 1006 last_frag * TX_DMA_LS0)); 1007 WRITE_ONCE(txd->txd4, fport); 1008 1009 tx_buf = mtk_desc_to_tx_buf(ring, txd); 1010 if (new_desc) 1011 memset(tx_buf, 0, sizeof(*tx_buf)); 1012 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 1013 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1014 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1015 MTK_TX_FLAGS_FPORT1; 1016 1017 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 1018 frag_map_size, k++); 1019 1020 frag_size -= frag_map_size; 1021 offset += frag_map_size; 1022 } 1023 } 1024 1025 /* store skb to cleanup */ 1026 itx_buf->skb = skb; 1027 1028 WRITE_ONCE(itxd->txd4, txd4); 1029 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 1030 (!nr_frags * TX_DMA_LS0))); 1031 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1032 if (k & 0x1) 1033 txd_pdma->txd2 |= TX_DMA_LS0; 1034 else 1035 txd_pdma->txd2 |= TX_DMA_LS1; 1036 } 1037 1038 netdev_sent_queue(dev, skb->len); 1039 skb_tx_timestamp(skb); 1040 1041 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1042 atomic_sub(n_desc, &ring->free_count); 1043 1044 /* make sure that all changes to the dma ring are flushed before we 1045 * continue 1046 */ 1047 wmb(); 1048 1049 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1050 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1051 !netdev_xmit_more()) 1052 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1053 } else { 1054 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1055 ring->dma_size); 1056 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1057 } 1058 1059 return 0; 1060 1061 err_dma: 1062 do { 1063 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1064 1065 /* unmap dma */ 1066 mtk_tx_unmap(eth, tx_buf); 1067 1068 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1069 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1070 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1071 1072 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1073 itxd_pdma = qdma_to_pdma(ring, itxd); 1074 } while (itxd != txd); 1075 1076 return -ENOMEM; 1077 } 1078 1079 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1080 { 1081 int i, nfrags; 1082 skb_frag_t *frag; 1083 1084 nfrags = 1; 1085 if (skb_is_gso(skb)) { 1086 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1087 frag = &skb_shinfo(skb)->frags[i]; 1088 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1089 MTK_TX_DMA_BUF_LEN); 1090 } 1091 } else { 1092 nfrags += skb_shinfo(skb)->nr_frags; 1093 } 1094 1095 return nfrags; 1096 } 1097 1098 static int mtk_queue_stopped(struct mtk_eth *eth) 1099 { 1100 int i; 1101 1102 for (i = 0; i < MTK_MAC_COUNT; i++) { 1103 if (!eth->netdev[i]) 1104 continue; 1105 if (netif_queue_stopped(eth->netdev[i])) 1106 return 1; 1107 } 1108 1109 return 0; 1110 } 1111 1112 static void mtk_wake_queue(struct mtk_eth *eth) 1113 { 1114 int i; 1115 1116 for (i = 0; i < MTK_MAC_COUNT; i++) { 1117 if (!eth->netdev[i]) 1118 continue; 1119 netif_wake_queue(eth->netdev[i]); 1120 } 1121 } 1122 1123 static void mtk_stop_queue(struct mtk_eth *eth) 1124 { 1125 int i; 1126 1127 for (i = 0; i < MTK_MAC_COUNT; i++) { 1128 if (!eth->netdev[i]) 1129 continue; 1130 netif_stop_queue(eth->netdev[i]); 1131 } 1132 } 1133 1134 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1135 { 1136 struct mtk_mac *mac = netdev_priv(dev); 1137 struct mtk_eth *eth = mac->hw; 1138 struct mtk_tx_ring *ring = ð->tx_ring; 1139 struct net_device_stats *stats = &dev->stats; 1140 bool gso = false; 1141 int tx_num; 1142 1143 /* normally we can rely on the stack not calling this more than once, 1144 * however we have 2 queues running on the same ring so we need to lock 1145 * the ring access 1146 */ 1147 spin_lock(ð->page_lock); 1148 1149 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1150 goto drop; 1151 1152 tx_num = mtk_cal_txd_req(skb); 1153 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1154 mtk_stop_queue(eth); 1155 netif_err(eth, tx_queued, dev, 1156 "Tx Ring full when queue awake!\n"); 1157 spin_unlock(ð->page_lock); 1158 return NETDEV_TX_BUSY; 1159 } 1160 1161 /* TSO: fill MSS info in tcp checksum field */ 1162 if (skb_is_gso(skb)) { 1163 if (skb_cow_head(skb, 0)) { 1164 netif_warn(eth, tx_err, dev, 1165 "GSO expand head fail.\n"); 1166 goto drop; 1167 } 1168 1169 if (skb_shinfo(skb)->gso_type & 1170 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1171 gso = true; 1172 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1173 } 1174 } 1175 1176 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1177 goto drop; 1178 1179 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1180 mtk_stop_queue(eth); 1181 1182 spin_unlock(ð->page_lock); 1183 1184 return NETDEV_TX_OK; 1185 1186 drop: 1187 spin_unlock(ð->page_lock); 1188 stats->tx_dropped++; 1189 dev_kfree_skb_any(skb); 1190 return NETDEV_TX_OK; 1191 } 1192 1193 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1194 { 1195 int i; 1196 struct mtk_rx_ring *ring; 1197 int idx; 1198 1199 if (!eth->hwlro) 1200 return ð->rx_ring[0]; 1201 1202 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1203 ring = ð->rx_ring[i]; 1204 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1205 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1206 ring->calc_idx_update = true; 1207 return ring; 1208 } 1209 } 1210 1211 return NULL; 1212 } 1213 1214 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1215 { 1216 struct mtk_rx_ring *ring; 1217 int i; 1218 1219 if (!eth->hwlro) { 1220 ring = ð->rx_ring[0]; 1221 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1222 } else { 1223 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1224 ring = ð->rx_ring[i]; 1225 if (ring->calc_idx_update) { 1226 ring->calc_idx_update = false; 1227 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1228 } 1229 } 1230 } 1231 } 1232 1233 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1234 struct mtk_eth *eth) 1235 { 1236 struct mtk_rx_ring *ring; 1237 int idx; 1238 struct sk_buff *skb; 1239 u8 *data, *new_data; 1240 struct mtk_rx_dma *rxd, trxd; 1241 int done = 0; 1242 1243 while (done < budget) { 1244 struct net_device *netdev; 1245 unsigned int pktlen; 1246 dma_addr_t dma_addr; 1247 int mac; 1248 1249 ring = mtk_get_rx_ring(eth); 1250 if (unlikely(!ring)) 1251 goto rx_done; 1252 1253 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1254 rxd = &ring->dma[idx]; 1255 data = ring->data[idx]; 1256 1257 mtk_rx_get_desc(&trxd, rxd); 1258 if (!(trxd.rxd2 & RX_DMA_DONE)) 1259 break; 1260 1261 /* find out which mac the packet come from. values start at 1 */ 1262 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1263 mac = 0; 1264 } else { 1265 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1266 RX_DMA_FPORT_MASK; 1267 mac--; 1268 } 1269 1270 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1271 !eth->netdev[mac])) 1272 goto release_desc; 1273 1274 netdev = eth->netdev[mac]; 1275 1276 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1277 goto release_desc; 1278 1279 /* alloc new buffer */ 1280 new_data = napi_alloc_frag(ring->frag_size); 1281 if (unlikely(!new_data)) { 1282 netdev->stats.rx_dropped++; 1283 goto release_desc; 1284 } 1285 dma_addr = dma_map_single(eth->dev, 1286 new_data + NET_SKB_PAD + 1287 eth->ip_align, 1288 ring->buf_size, 1289 DMA_FROM_DEVICE); 1290 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1291 skb_free_frag(new_data); 1292 netdev->stats.rx_dropped++; 1293 goto release_desc; 1294 } 1295 1296 /* receive data */ 1297 skb = build_skb(data, ring->frag_size); 1298 if (unlikely(!skb)) { 1299 skb_free_frag(new_data); 1300 netdev->stats.rx_dropped++; 1301 goto release_desc; 1302 } 1303 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1304 1305 dma_unmap_single(eth->dev, trxd.rxd1, 1306 ring->buf_size, DMA_FROM_DEVICE); 1307 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1308 skb->dev = netdev; 1309 skb_put(skb, pktlen); 1310 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1311 skb->ip_summed = CHECKSUM_UNNECESSARY; 1312 else 1313 skb_checksum_none_assert(skb); 1314 skb->protocol = eth_type_trans(skb, netdev); 1315 1316 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1317 RX_DMA_VID(trxd.rxd3)) 1318 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1319 RX_DMA_VID(trxd.rxd3)); 1320 skb_record_rx_queue(skb, 0); 1321 napi_gro_receive(napi, skb); 1322 1323 ring->data[idx] = new_data; 1324 rxd->rxd1 = (unsigned int)dma_addr; 1325 1326 release_desc: 1327 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1328 rxd->rxd2 = RX_DMA_LSO; 1329 else 1330 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1331 1332 ring->calc_idx = idx; 1333 1334 done++; 1335 } 1336 1337 rx_done: 1338 if (done) { 1339 /* make sure that all changes to the dma ring are flushed before 1340 * we continue 1341 */ 1342 wmb(); 1343 mtk_update_rx_cpu_idx(eth); 1344 } 1345 1346 return done; 1347 } 1348 1349 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1350 unsigned int *done, unsigned int *bytes) 1351 { 1352 struct mtk_tx_ring *ring = ð->tx_ring; 1353 struct mtk_tx_dma *desc; 1354 struct sk_buff *skb; 1355 struct mtk_tx_buf *tx_buf; 1356 u32 cpu, dma; 1357 1358 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1359 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1360 1361 desc = mtk_qdma_phys_to_virt(ring, cpu); 1362 1363 while ((cpu != dma) && budget) { 1364 u32 next_cpu = desc->txd2; 1365 int mac = 0; 1366 1367 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1368 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1369 break; 1370 1371 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1372 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1373 mac = 1; 1374 1375 skb = tx_buf->skb; 1376 if (!skb) 1377 break; 1378 1379 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1380 bytes[mac] += skb->len; 1381 done[mac]++; 1382 budget--; 1383 } 1384 mtk_tx_unmap(eth, tx_buf); 1385 1386 ring->last_free = desc; 1387 atomic_inc(&ring->free_count); 1388 1389 cpu = next_cpu; 1390 } 1391 1392 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1393 1394 return budget; 1395 } 1396 1397 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1398 unsigned int *done, unsigned int *bytes) 1399 { 1400 struct mtk_tx_ring *ring = ð->tx_ring; 1401 struct mtk_tx_dma *desc; 1402 struct sk_buff *skb; 1403 struct mtk_tx_buf *tx_buf; 1404 u32 cpu, dma; 1405 1406 cpu = ring->cpu_idx; 1407 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1408 1409 while ((cpu != dma) && budget) { 1410 tx_buf = &ring->buf[cpu]; 1411 skb = tx_buf->skb; 1412 if (!skb) 1413 break; 1414 1415 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1416 bytes[0] += skb->len; 1417 done[0]++; 1418 budget--; 1419 } 1420 1421 mtk_tx_unmap(eth, tx_buf); 1422 1423 desc = &ring->dma[cpu]; 1424 ring->last_free = desc; 1425 atomic_inc(&ring->free_count); 1426 1427 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1428 } 1429 1430 ring->cpu_idx = cpu; 1431 1432 return budget; 1433 } 1434 1435 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1436 { 1437 struct mtk_tx_ring *ring = ð->tx_ring; 1438 unsigned int done[MTK_MAX_DEVS]; 1439 unsigned int bytes[MTK_MAX_DEVS]; 1440 int total = 0, i; 1441 1442 memset(done, 0, sizeof(done)); 1443 memset(bytes, 0, sizeof(bytes)); 1444 1445 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1446 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1447 else 1448 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1449 1450 for (i = 0; i < MTK_MAC_COUNT; i++) { 1451 if (!eth->netdev[i] || !done[i]) 1452 continue; 1453 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1454 total += done[i]; 1455 } 1456 1457 if (mtk_queue_stopped(eth) && 1458 (atomic_read(&ring->free_count) > ring->thresh)) 1459 mtk_wake_queue(eth); 1460 1461 return total; 1462 } 1463 1464 static void mtk_handle_status_irq(struct mtk_eth *eth) 1465 { 1466 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1467 1468 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1469 mtk_stats_update(eth); 1470 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1471 MTK_INT_STATUS2); 1472 } 1473 } 1474 1475 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1476 { 1477 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1478 u32 status, mask; 1479 int tx_done = 0; 1480 1481 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1482 mtk_handle_status_irq(eth); 1483 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1484 tx_done = mtk_poll_tx(eth, budget); 1485 1486 if (unlikely(netif_msg_intr(eth))) { 1487 status = mtk_r32(eth, eth->tx_int_status_reg); 1488 mask = mtk_r32(eth, eth->tx_int_mask_reg); 1489 dev_info(eth->dev, 1490 "done tx %d, intr 0x%08x/0x%x\n", 1491 tx_done, status, mask); 1492 } 1493 1494 if (tx_done == budget) 1495 return budget; 1496 1497 status = mtk_r32(eth, eth->tx_int_status_reg); 1498 if (status & MTK_TX_DONE_INT) 1499 return budget; 1500 1501 napi_complete(napi); 1502 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1503 1504 return tx_done; 1505 } 1506 1507 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1508 { 1509 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1510 u32 status, mask; 1511 int rx_done = 0; 1512 int remain_budget = budget; 1513 1514 mtk_handle_status_irq(eth); 1515 1516 poll_again: 1517 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1518 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1519 1520 if (unlikely(netif_msg_intr(eth))) { 1521 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1522 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1523 dev_info(eth->dev, 1524 "done rx %d, intr 0x%08x/0x%x\n", 1525 rx_done, status, mask); 1526 } 1527 if (rx_done == remain_budget) 1528 return budget; 1529 1530 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1531 if (status & MTK_RX_DONE_INT) { 1532 remain_budget -= rx_done; 1533 goto poll_again; 1534 } 1535 napi_complete(napi); 1536 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1537 1538 return rx_done + budget - remain_budget; 1539 } 1540 1541 static int mtk_tx_alloc(struct mtk_eth *eth) 1542 { 1543 struct mtk_tx_ring *ring = ð->tx_ring; 1544 int i, sz = sizeof(*ring->dma); 1545 1546 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1547 GFP_KERNEL); 1548 if (!ring->buf) 1549 goto no_tx_mem; 1550 1551 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1552 &ring->phys, GFP_ATOMIC); 1553 if (!ring->dma) 1554 goto no_tx_mem; 1555 1556 for (i = 0; i < MTK_DMA_SIZE; i++) { 1557 int next = (i + 1) % MTK_DMA_SIZE; 1558 u32 next_ptr = ring->phys + next * sz; 1559 1560 ring->dma[i].txd2 = next_ptr; 1561 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1562 } 1563 1564 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1565 * only as the framework. The real HW descriptors are the PDMA 1566 * descriptors in ring->dma_pdma. 1567 */ 1568 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1569 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1570 &ring->phys_pdma, 1571 GFP_ATOMIC); 1572 if (!ring->dma_pdma) 1573 goto no_tx_mem; 1574 1575 for (i = 0; i < MTK_DMA_SIZE; i++) { 1576 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1577 ring->dma_pdma[i].txd4 = 0; 1578 } 1579 } 1580 1581 ring->dma_size = MTK_DMA_SIZE; 1582 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1583 ring->next_free = &ring->dma[0]; 1584 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1585 ring->thresh = MAX_SKB_FRAGS; 1586 1587 /* make sure that all changes to the dma ring are flushed before we 1588 * continue 1589 */ 1590 wmb(); 1591 1592 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1593 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1594 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1595 mtk_w32(eth, 1596 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1597 MTK_QTX_CRX_PTR); 1598 mtk_w32(eth, 1599 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1600 MTK_QTX_DRX_PTR); 1601 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1602 MTK_QTX_CFG(0)); 1603 } else { 1604 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1605 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1606 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1607 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1608 } 1609 1610 return 0; 1611 1612 no_tx_mem: 1613 return -ENOMEM; 1614 } 1615 1616 static void mtk_tx_clean(struct mtk_eth *eth) 1617 { 1618 struct mtk_tx_ring *ring = ð->tx_ring; 1619 int i; 1620 1621 if (ring->buf) { 1622 for (i = 0; i < MTK_DMA_SIZE; i++) 1623 mtk_tx_unmap(eth, &ring->buf[i]); 1624 kfree(ring->buf); 1625 ring->buf = NULL; 1626 } 1627 1628 if (ring->dma) { 1629 dma_free_coherent(eth->dev, 1630 MTK_DMA_SIZE * sizeof(*ring->dma), 1631 ring->dma, 1632 ring->phys); 1633 ring->dma = NULL; 1634 } 1635 1636 if (ring->dma_pdma) { 1637 dma_free_coherent(eth->dev, 1638 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1639 ring->dma_pdma, 1640 ring->phys_pdma); 1641 ring->dma_pdma = NULL; 1642 } 1643 } 1644 1645 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1646 { 1647 struct mtk_rx_ring *ring; 1648 int rx_data_len, rx_dma_size; 1649 int i; 1650 u32 offset = 0; 1651 1652 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1653 if (ring_no) 1654 return -EINVAL; 1655 ring = ð->rx_ring_qdma; 1656 offset = 0x1000; 1657 } else { 1658 ring = ð->rx_ring[ring_no]; 1659 } 1660 1661 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1662 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1663 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1664 } else { 1665 rx_data_len = ETH_DATA_LEN; 1666 rx_dma_size = MTK_DMA_SIZE; 1667 } 1668 1669 ring->frag_size = mtk_max_frag_size(rx_data_len); 1670 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1671 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1672 GFP_KERNEL); 1673 if (!ring->data) 1674 return -ENOMEM; 1675 1676 for (i = 0; i < rx_dma_size; i++) { 1677 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1678 if (!ring->data[i]) 1679 return -ENOMEM; 1680 } 1681 1682 ring->dma = dma_alloc_coherent(eth->dev, 1683 rx_dma_size * sizeof(*ring->dma), 1684 &ring->phys, GFP_ATOMIC); 1685 if (!ring->dma) 1686 return -ENOMEM; 1687 1688 for (i = 0; i < rx_dma_size; i++) { 1689 dma_addr_t dma_addr = dma_map_single(eth->dev, 1690 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1691 ring->buf_size, 1692 DMA_FROM_DEVICE); 1693 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1694 return -ENOMEM; 1695 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1696 1697 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1698 ring->dma[i].rxd2 = RX_DMA_LSO; 1699 else 1700 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1701 } 1702 ring->dma_size = rx_dma_size; 1703 ring->calc_idx_update = false; 1704 ring->calc_idx = rx_dma_size - 1; 1705 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1706 /* make sure that all changes to the dma ring are flushed before we 1707 * continue 1708 */ 1709 wmb(); 1710 1711 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1712 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1713 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1714 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1715 1716 return 0; 1717 } 1718 1719 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1720 { 1721 int i; 1722 1723 if (ring->data && ring->dma) { 1724 for (i = 0; i < ring->dma_size; i++) { 1725 if (!ring->data[i]) 1726 continue; 1727 if (!ring->dma[i].rxd1) 1728 continue; 1729 dma_unmap_single(eth->dev, 1730 ring->dma[i].rxd1, 1731 ring->buf_size, 1732 DMA_FROM_DEVICE); 1733 skb_free_frag(ring->data[i]); 1734 } 1735 kfree(ring->data); 1736 ring->data = NULL; 1737 } 1738 1739 if (ring->dma) { 1740 dma_free_coherent(eth->dev, 1741 ring->dma_size * sizeof(*ring->dma), 1742 ring->dma, 1743 ring->phys); 1744 ring->dma = NULL; 1745 } 1746 } 1747 1748 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1749 { 1750 int i; 1751 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1752 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1753 1754 /* set LRO rings to auto-learn modes */ 1755 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1756 1757 /* validate LRO ring */ 1758 ring_ctrl_dw2 |= MTK_RING_VLD; 1759 1760 /* set AGE timer (unit: 20us) */ 1761 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1762 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1763 1764 /* set max AGG timer (unit: 20us) */ 1765 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1766 1767 /* set max LRO AGG count */ 1768 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1769 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1770 1771 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1772 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1773 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1774 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1775 } 1776 1777 /* IPv4 checksum update enable */ 1778 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1779 1780 /* switch priority comparison to packet count mode */ 1781 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1782 1783 /* bandwidth threshold setting */ 1784 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1785 1786 /* auto-learn score delta setting */ 1787 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1788 1789 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1790 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1791 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1792 1793 /* set HW LRO mode & the max aggregation count for rx packets */ 1794 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1795 1796 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1797 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1798 1799 /* enable HW LRO */ 1800 lro_ctrl_dw0 |= MTK_LRO_EN; 1801 1802 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1803 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1804 1805 return 0; 1806 } 1807 1808 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1809 { 1810 int i; 1811 u32 val; 1812 1813 /* relinquish lro rings, flush aggregated packets */ 1814 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1815 1816 /* wait for relinquishments done */ 1817 for (i = 0; i < 10; i++) { 1818 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1819 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1820 msleep(20); 1821 continue; 1822 } 1823 break; 1824 } 1825 1826 /* invalidate lro rings */ 1827 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1828 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1829 1830 /* disable HW LRO */ 1831 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1832 } 1833 1834 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1835 { 1836 u32 reg_val; 1837 1838 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1839 1840 /* invalidate the IP setting */ 1841 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1842 1843 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1844 1845 /* validate the IP setting */ 1846 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1847 } 1848 1849 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1850 { 1851 u32 reg_val; 1852 1853 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1854 1855 /* invalidate the IP setting */ 1856 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1857 1858 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1859 } 1860 1861 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1862 { 1863 int cnt = 0; 1864 int i; 1865 1866 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1867 if (mac->hwlro_ip[i]) 1868 cnt++; 1869 } 1870 1871 return cnt; 1872 } 1873 1874 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1875 struct ethtool_rxnfc *cmd) 1876 { 1877 struct ethtool_rx_flow_spec *fsp = 1878 (struct ethtool_rx_flow_spec *)&cmd->fs; 1879 struct mtk_mac *mac = netdev_priv(dev); 1880 struct mtk_eth *eth = mac->hw; 1881 int hwlro_idx; 1882 1883 if ((fsp->flow_type != TCP_V4_FLOW) || 1884 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1885 (fsp->location > 1)) 1886 return -EINVAL; 1887 1888 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1889 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1890 1891 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1892 1893 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1894 1895 return 0; 1896 } 1897 1898 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1899 struct ethtool_rxnfc *cmd) 1900 { 1901 struct ethtool_rx_flow_spec *fsp = 1902 (struct ethtool_rx_flow_spec *)&cmd->fs; 1903 struct mtk_mac *mac = netdev_priv(dev); 1904 struct mtk_eth *eth = mac->hw; 1905 int hwlro_idx; 1906 1907 if (fsp->location > 1) 1908 return -EINVAL; 1909 1910 mac->hwlro_ip[fsp->location] = 0; 1911 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1912 1913 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1914 1915 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1916 1917 return 0; 1918 } 1919 1920 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1921 { 1922 struct mtk_mac *mac = netdev_priv(dev); 1923 struct mtk_eth *eth = mac->hw; 1924 int i, hwlro_idx; 1925 1926 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1927 mac->hwlro_ip[i] = 0; 1928 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1929 1930 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1931 } 1932 1933 mac->hwlro_ip_cnt = 0; 1934 } 1935 1936 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1937 struct ethtool_rxnfc *cmd) 1938 { 1939 struct mtk_mac *mac = netdev_priv(dev); 1940 struct ethtool_rx_flow_spec *fsp = 1941 (struct ethtool_rx_flow_spec *)&cmd->fs; 1942 1943 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1944 fsp->flow_type = TCP_V4_FLOW; 1945 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1946 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1947 1948 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1949 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1950 fsp->h_u.tcp_ip4_spec.psrc = 0; 1951 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1952 fsp->h_u.tcp_ip4_spec.pdst = 0; 1953 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1954 fsp->h_u.tcp_ip4_spec.tos = 0; 1955 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1956 1957 return 0; 1958 } 1959 1960 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1961 struct ethtool_rxnfc *cmd, 1962 u32 *rule_locs) 1963 { 1964 struct mtk_mac *mac = netdev_priv(dev); 1965 int cnt = 0; 1966 int i; 1967 1968 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1969 if (mac->hwlro_ip[i]) { 1970 rule_locs[cnt] = i; 1971 cnt++; 1972 } 1973 } 1974 1975 cmd->rule_cnt = cnt; 1976 1977 return 0; 1978 } 1979 1980 static netdev_features_t mtk_fix_features(struct net_device *dev, 1981 netdev_features_t features) 1982 { 1983 if (!(features & NETIF_F_LRO)) { 1984 struct mtk_mac *mac = netdev_priv(dev); 1985 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1986 1987 if (ip_cnt) { 1988 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1989 1990 features |= NETIF_F_LRO; 1991 } 1992 } 1993 1994 return features; 1995 } 1996 1997 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1998 { 1999 int err = 0; 2000 2001 if (!((dev->features ^ features) & NETIF_F_LRO)) 2002 return 0; 2003 2004 if (!(features & NETIF_F_LRO)) 2005 mtk_hwlro_netdev_disable(dev); 2006 2007 return err; 2008 } 2009 2010 /* wait for DMA to finish whatever it is doing before we start using it again */ 2011 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2012 { 2013 unsigned long t_start = jiffies; 2014 2015 while (1) { 2016 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2017 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 2018 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2019 return 0; 2020 } else { 2021 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & 2022 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 2023 return 0; 2024 } 2025 2026 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 2027 break; 2028 } 2029 2030 dev_err(eth->dev, "DMA init timeout\n"); 2031 return -1; 2032 } 2033 2034 static int mtk_dma_init(struct mtk_eth *eth) 2035 { 2036 int err; 2037 u32 i; 2038 2039 if (mtk_dma_busy_wait(eth)) 2040 return -EBUSY; 2041 2042 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2043 /* QDMA needs scratch memory for internal reordering of the 2044 * descriptors 2045 */ 2046 err = mtk_init_fq_dma(eth); 2047 if (err) 2048 return err; 2049 } 2050 2051 err = mtk_tx_alloc(eth); 2052 if (err) 2053 return err; 2054 2055 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2056 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2057 if (err) 2058 return err; 2059 } 2060 2061 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2062 if (err) 2063 return err; 2064 2065 if (eth->hwlro) { 2066 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2067 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2068 if (err) 2069 return err; 2070 } 2071 err = mtk_hwlro_rx_init(eth); 2072 if (err) 2073 return err; 2074 } 2075 2076 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2077 /* Enable random early drop and set drop threshold 2078 * automatically 2079 */ 2080 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2081 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2082 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2083 } 2084 2085 return 0; 2086 } 2087 2088 static void mtk_dma_free(struct mtk_eth *eth) 2089 { 2090 int i; 2091 2092 for (i = 0; i < MTK_MAC_COUNT; i++) 2093 if (eth->netdev[i]) 2094 netdev_reset_queue(eth->netdev[i]); 2095 if (eth->scratch_ring) { 2096 dma_free_coherent(eth->dev, 2097 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2098 eth->scratch_ring, 2099 eth->phy_scratch_ring); 2100 eth->scratch_ring = NULL; 2101 eth->phy_scratch_ring = 0; 2102 } 2103 mtk_tx_clean(eth); 2104 mtk_rx_clean(eth, ð->rx_ring[0]); 2105 mtk_rx_clean(eth, ð->rx_ring_qdma); 2106 2107 if (eth->hwlro) { 2108 mtk_hwlro_rx_uninit(eth); 2109 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2110 mtk_rx_clean(eth, ð->rx_ring[i]); 2111 } 2112 2113 kfree(eth->scratch_head); 2114 } 2115 2116 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2117 { 2118 struct mtk_mac *mac = netdev_priv(dev); 2119 struct mtk_eth *eth = mac->hw; 2120 2121 eth->netdev[mac->id]->stats.tx_errors++; 2122 netif_err(eth, tx_err, dev, 2123 "transmit timed out\n"); 2124 schedule_work(ð->pending_work); 2125 } 2126 2127 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2128 { 2129 struct mtk_eth *eth = _eth; 2130 2131 if (likely(napi_schedule_prep(ð->rx_napi))) { 2132 __napi_schedule(ð->rx_napi); 2133 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2134 } 2135 2136 return IRQ_HANDLED; 2137 } 2138 2139 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2140 { 2141 struct mtk_eth *eth = _eth; 2142 2143 if (likely(napi_schedule_prep(ð->tx_napi))) { 2144 __napi_schedule(ð->tx_napi); 2145 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2146 } 2147 2148 return IRQ_HANDLED; 2149 } 2150 2151 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2152 { 2153 struct mtk_eth *eth = _eth; 2154 2155 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2156 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2157 mtk_handle_irq_rx(irq, _eth); 2158 } 2159 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2160 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2161 mtk_handle_irq_tx(irq, _eth); 2162 } 2163 2164 return IRQ_HANDLED; 2165 } 2166 2167 #ifdef CONFIG_NET_POLL_CONTROLLER 2168 static void mtk_poll_controller(struct net_device *dev) 2169 { 2170 struct mtk_mac *mac = netdev_priv(dev); 2171 struct mtk_eth *eth = mac->hw; 2172 2173 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2174 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2175 mtk_handle_irq_rx(eth->irq[2], dev); 2176 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2177 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2178 } 2179 #endif 2180 2181 static int mtk_start_dma(struct mtk_eth *eth) 2182 { 2183 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2184 int err; 2185 2186 err = mtk_dma_init(eth); 2187 if (err) { 2188 mtk_dma_free(eth); 2189 return err; 2190 } 2191 2192 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2193 mtk_w32(eth, 2194 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2195 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 2196 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2197 MTK_RX_BT_32DWORDS, 2198 MTK_QDMA_GLO_CFG); 2199 2200 mtk_w32(eth, 2201 MTK_RX_DMA_EN | rx_2b_offset | 2202 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2203 MTK_PDMA_GLO_CFG); 2204 } else { 2205 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2206 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2207 MTK_PDMA_GLO_CFG); 2208 } 2209 2210 return 0; 2211 } 2212 2213 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2214 { 2215 int i; 2216 2217 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2218 return; 2219 2220 for (i = 0; i < MTK_MAC_COUNT; i++) { 2221 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2222 2223 /* default setup the forward port to send frame to PDMA */ 2224 val &= ~0xffff; 2225 2226 /* Enable RX checksum */ 2227 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2228 2229 val |= config; 2230 2231 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2232 } 2233 /* Reset and enable PSE */ 2234 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2235 mtk_w32(eth, 0, MTK_RST_GL); 2236 } 2237 2238 static int mtk_open(struct net_device *dev) 2239 { 2240 struct mtk_mac *mac = netdev_priv(dev); 2241 struct mtk_eth *eth = mac->hw; 2242 int err; 2243 2244 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2245 if (err) { 2246 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2247 err); 2248 return err; 2249 } 2250 2251 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2252 if (!refcount_read(ð->dma_refcnt)) { 2253 int err = mtk_start_dma(eth); 2254 2255 if (err) 2256 return err; 2257 2258 mtk_gdm_config(eth, MTK_GDMA_TO_PDMA); 2259 2260 napi_enable(ð->tx_napi); 2261 napi_enable(ð->rx_napi); 2262 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2263 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2264 refcount_set(ð->dma_refcnt, 1); 2265 } 2266 else 2267 refcount_inc(ð->dma_refcnt); 2268 2269 phylink_start(mac->phylink); 2270 netif_start_queue(dev); 2271 return 0; 2272 } 2273 2274 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2275 { 2276 u32 val; 2277 int i; 2278 2279 /* stop the dma engine */ 2280 spin_lock_bh(ð->page_lock); 2281 val = mtk_r32(eth, glo_cfg); 2282 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2283 glo_cfg); 2284 spin_unlock_bh(ð->page_lock); 2285 2286 /* wait for dma stop */ 2287 for (i = 0; i < 10; i++) { 2288 val = mtk_r32(eth, glo_cfg); 2289 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2290 msleep(20); 2291 continue; 2292 } 2293 break; 2294 } 2295 } 2296 2297 static int mtk_stop(struct net_device *dev) 2298 { 2299 struct mtk_mac *mac = netdev_priv(dev); 2300 struct mtk_eth *eth = mac->hw; 2301 2302 phylink_stop(mac->phylink); 2303 2304 netif_tx_disable(dev); 2305 2306 phylink_disconnect_phy(mac->phylink); 2307 2308 /* only shutdown DMA if this is the last user */ 2309 if (!refcount_dec_and_test(ð->dma_refcnt)) 2310 return 0; 2311 2312 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 2313 2314 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2315 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2316 napi_disable(ð->tx_napi); 2317 napi_disable(ð->rx_napi); 2318 2319 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2320 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2321 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2322 2323 mtk_dma_free(eth); 2324 2325 return 0; 2326 } 2327 2328 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2329 { 2330 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2331 reset_bits, 2332 reset_bits); 2333 2334 usleep_range(1000, 1100); 2335 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2336 reset_bits, 2337 ~reset_bits); 2338 mdelay(10); 2339 } 2340 2341 static void mtk_clk_disable(struct mtk_eth *eth) 2342 { 2343 int clk; 2344 2345 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2346 clk_disable_unprepare(eth->clks[clk]); 2347 } 2348 2349 static int mtk_clk_enable(struct mtk_eth *eth) 2350 { 2351 int clk, ret; 2352 2353 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2354 ret = clk_prepare_enable(eth->clks[clk]); 2355 if (ret) 2356 goto err_disable_clks; 2357 } 2358 2359 return 0; 2360 2361 err_disable_clks: 2362 while (--clk >= 0) 2363 clk_disable_unprepare(eth->clks[clk]); 2364 2365 return ret; 2366 } 2367 2368 static int mtk_hw_init(struct mtk_eth *eth) 2369 { 2370 int i, val, ret; 2371 2372 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2373 return 0; 2374 2375 pm_runtime_enable(eth->dev); 2376 pm_runtime_get_sync(eth->dev); 2377 2378 ret = mtk_clk_enable(eth); 2379 if (ret) 2380 goto err_disable_pm; 2381 2382 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2383 ret = device_reset(eth->dev); 2384 if (ret) { 2385 dev_err(eth->dev, "MAC reset failed!\n"); 2386 goto err_disable_pm; 2387 } 2388 2389 /* enable interrupt delay for RX */ 2390 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2391 2392 /* disable delay and normal interrupt */ 2393 mtk_tx_irq_disable(eth, ~0); 2394 mtk_rx_irq_disable(eth, ~0); 2395 2396 return 0; 2397 } 2398 2399 /* Non-MT7628 handling... */ 2400 ethsys_reset(eth, RSTCTRL_FE); 2401 ethsys_reset(eth, RSTCTRL_PPE); 2402 2403 if (eth->pctl) { 2404 /* Set GE2 driving and slew rate */ 2405 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2406 2407 /* set GE2 TDSEL */ 2408 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2409 2410 /* set GE2 TUNE */ 2411 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2412 } 2413 2414 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2415 * up with the more appropriate value when mtk_mac_config call is being 2416 * invoked. 2417 */ 2418 for (i = 0; i < MTK_MAC_COUNT; i++) 2419 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2420 2421 /* Indicates CDM to parse the MTK special tag from CPU 2422 * which also is working out for untag packets. 2423 */ 2424 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2425 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2426 2427 /* Enable RX VLan Offloading */ 2428 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2429 2430 /* enable interrupt delay for RX */ 2431 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2432 2433 /* disable delay and normal interrupt */ 2434 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 2435 mtk_tx_irq_disable(eth, ~0); 2436 mtk_rx_irq_disable(eth, ~0); 2437 2438 /* FE int grouping */ 2439 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2440 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2441 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2442 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2443 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2444 2445 return 0; 2446 2447 err_disable_pm: 2448 pm_runtime_put_sync(eth->dev); 2449 pm_runtime_disable(eth->dev); 2450 2451 return ret; 2452 } 2453 2454 static int mtk_hw_deinit(struct mtk_eth *eth) 2455 { 2456 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2457 return 0; 2458 2459 mtk_clk_disable(eth); 2460 2461 pm_runtime_put_sync(eth->dev); 2462 pm_runtime_disable(eth->dev); 2463 2464 return 0; 2465 } 2466 2467 static int __init mtk_init(struct net_device *dev) 2468 { 2469 struct mtk_mac *mac = netdev_priv(dev); 2470 struct mtk_eth *eth = mac->hw; 2471 const char *mac_addr; 2472 2473 mac_addr = of_get_mac_address(mac->of_node); 2474 if (!IS_ERR(mac_addr)) 2475 ether_addr_copy(dev->dev_addr, mac_addr); 2476 2477 /* If the mac address is invalid, use random mac address */ 2478 if (!is_valid_ether_addr(dev->dev_addr)) { 2479 eth_hw_addr_random(dev); 2480 dev_err(eth->dev, "generated random MAC address %pM\n", 2481 dev->dev_addr); 2482 } 2483 2484 return 0; 2485 } 2486 2487 static void mtk_uninit(struct net_device *dev) 2488 { 2489 struct mtk_mac *mac = netdev_priv(dev); 2490 struct mtk_eth *eth = mac->hw; 2491 2492 phylink_disconnect_phy(mac->phylink); 2493 mtk_tx_irq_disable(eth, ~0); 2494 mtk_rx_irq_disable(eth, ~0); 2495 } 2496 2497 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2498 { 2499 struct mtk_mac *mac = netdev_priv(dev); 2500 2501 switch (cmd) { 2502 case SIOCGMIIPHY: 2503 case SIOCGMIIREG: 2504 case SIOCSMIIREG: 2505 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2506 default: 2507 break; 2508 } 2509 2510 return -EOPNOTSUPP; 2511 } 2512 2513 static void mtk_pending_work(struct work_struct *work) 2514 { 2515 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2516 int err, i; 2517 unsigned long restart = 0; 2518 2519 rtnl_lock(); 2520 2521 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2522 2523 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2524 cpu_relax(); 2525 2526 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2527 /* stop all devices to make sure that dma is properly shut down */ 2528 for (i = 0; i < MTK_MAC_COUNT; i++) { 2529 if (!eth->netdev[i]) 2530 continue; 2531 mtk_stop(eth->netdev[i]); 2532 __set_bit(i, &restart); 2533 } 2534 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2535 2536 /* restart underlying hardware such as power, clock, pin mux 2537 * and the connected phy 2538 */ 2539 mtk_hw_deinit(eth); 2540 2541 if (eth->dev->pins) 2542 pinctrl_select_state(eth->dev->pins->p, 2543 eth->dev->pins->default_state); 2544 mtk_hw_init(eth); 2545 2546 /* restart DMA and enable IRQs */ 2547 for (i = 0; i < MTK_MAC_COUNT; i++) { 2548 if (!test_bit(i, &restart)) 2549 continue; 2550 err = mtk_open(eth->netdev[i]); 2551 if (err) { 2552 netif_alert(eth, ifup, eth->netdev[i], 2553 "Driver up/down cycle failed, closing device.\n"); 2554 dev_close(eth->netdev[i]); 2555 } 2556 } 2557 2558 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2559 2560 clear_bit_unlock(MTK_RESETTING, ð->state); 2561 2562 rtnl_unlock(); 2563 } 2564 2565 static int mtk_free_dev(struct mtk_eth *eth) 2566 { 2567 int i; 2568 2569 for (i = 0; i < MTK_MAC_COUNT; i++) { 2570 if (!eth->netdev[i]) 2571 continue; 2572 free_netdev(eth->netdev[i]); 2573 } 2574 2575 return 0; 2576 } 2577 2578 static int mtk_unreg_dev(struct mtk_eth *eth) 2579 { 2580 int i; 2581 2582 for (i = 0; i < MTK_MAC_COUNT; i++) { 2583 if (!eth->netdev[i]) 2584 continue; 2585 unregister_netdev(eth->netdev[i]); 2586 } 2587 2588 return 0; 2589 } 2590 2591 static int mtk_cleanup(struct mtk_eth *eth) 2592 { 2593 mtk_unreg_dev(eth); 2594 mtk_free_dev(eth); 2595 cancel_work_sync(ð->pending_work); 2596 2597 return 0; 2598 } 2599 2600 static int mtk_get_link_ksettings(struct net_device *ndev, 2601 struct ethtool_link_ksettings *cmd) 2602 { 2603 struct mtk_mac *mac = netdev_priv(ndev); 2604 2605 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2606 return -EBUSY; 2607 2608 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2609 } 2610 2611 static int mtk_set_link_ksettings(struct net_device *ndev, 2612 const struct ethtool_link_ksettings *cmd) 2613 { 2614 struct mtk_mac *mac = netdev_priv(ndev); 2615 2616 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2617 return -EBUSY; 2618 2619 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2620 } 2621 2622 static void mtk_get_drvinfo(struct net_device *dev, 2623 struct ethtool_drvinfo *info) 2624 { 2625 struct mtk_mac *mac = netdev_priv(dev); 2626 2627 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2628 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2629 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2630 } 2631 2632 static u32 mtk_get_msglevel(struct net_device *dev) 2633 { 2634 struct mtk_mac *mac = netdev_priv(dev); 2635 2636 return mac->hw->msg_enable; 2637 } 2638 2639 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2640 { 2641 struct mtk_mac *mac = netdev_priv(dev); 2642 2643 mac->hw->msg_enable = value; 2644 } 2645 2646 static int mtk_nway_reset(struct net_device *dev) 2647 { 2648 struct mtk_mac *mac = netdev_priv(dev); 2649 2650 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2651 return -EBUSY; 2652 2653 if (!mac->phylink) 2654 return -ENOTSUPP; 2655 2656 return phylink_ethtool_nway_reset(mac->phylink); 2657 } 2658 2659 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2660 { 2661 int i; 2662 2663 switch (stringset) { 2664 case ETH_SS_STATS: 2665 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2666 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2667 data += ETH_GSTRING_LEN; 2668 } 2669 break; 2670 } 2671 } 2672 2673 static int mtk_get_sset_count(struct net_device *dev, int sset) 2674 { 2675 switch (sset) { 2676 case ETH_SS_STATS: 2677 return ARRAY_SIZE(mtk_ethtool_stats); 2678 default: 2679 return -EOPNOTSUPP; 2680 } 2681 } 2682 2683 static void mtk_get_ethtool_stats(struct net_device *dev, 2684 struct ethtool_stats *stats, u64 *data) 2685 { 2686 struct mtk_mac *mac = netdev_priv(dev); 2687 struct mtk_hw_stats *hwstats = mac->hw_stats; 2688 u64 *data_src, *data_dst; 2689 unsigned int start; 2690 int i; 2691 2692 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2693 return; 2694 2695 if (netif_running(dev) && netif_device_present(dev)) { 2696 if (spin_trylock_bh(&hwstats->stats_lock)) { 2697 mtk_stats_update_mac(mac); 2698 spin_unlock_bh(&hwstats->stats_lock); 2699 } 2700 } 2701 2702 data_src = (u64 *)hwstats; 2703 2704 do { 2705 data_dst = data; 2706 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2707 2708 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2709 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2710 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2711 } 2712 2713 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2714 u32 *rule_locs) 2715 { 2716 int ret = -EOPNOTSUPP; 2717 2718 switch (cmd->cmd) { 2719 case ETHTOOL_GRXRINGS: 2720 if (dev->hw_features & NETIF_F_LRO) { 2721 cmd->data = MTK_MAX_RX_RING_NUM; 2722 ret = 0; 2723 } 2724 break; 2725 case ETHTOOL_GRXCLSRLCNT: 2726 if (dev->hw_features & NETIF_F_LRO) { 2727 struct mtk_mac *mac = netdev_priv(dev); 2728 2729 cmd->rule_cnt = mac->hwlro_ip_cnt; 2730 ret = 0; 2731 } 2732 break; 2733 case ETHTOOL_GRXCLSRULE: 2734 if (dev->hw_features & NETIF_F_LRO) 2735 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2736 break; 2737 case ETHTOOL_GRXCLSRLALL: 2738 if (dev->hw_features & NETIF_F_LRO) 2739 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2740 rule_locs); 2741 break; 2742 default: 2743 break; 2744 } 2745 2746 return ret; 2747 } 2748 2749 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2750 { 2751 int ret = -EOPNOTSUPP; 2752 2753 switch (cmd->cmd) { 2754 case ETHTOOL_SRXCLSRLINS: 2755 if (dev->hw_features & NETIF_F_LRO) 2756 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2757 break; 2758 case ETHTOOL_SRXCLSRLDEL: 2759 if (dev->hw_features & NETIF_F_LRO) 2760 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2761 break; 2762 default: 2763 break; 2764 } 2765 2766 return ret; 2767 } 2768 2769 static const struct ethtool_ops mtk_ethtool_ops = { 2770 .get_link_ksettings = mtk_get_link_ksettings, 2771 .set_link_ksettings = mtk_set_link_ksettings, 2772 .get_drvinfo = mtk_get_drvinfo, 2773 .get_msglevel = mtk_get_msglevel, 2774 .set_msglevel = mtk_set_msglevel, 2775 .nway_reset = mtk_nway_reset, 2776 .get_link = ethtool_op_get_link, 2777 .get_strings = mtk_get_strings, 2778 .get_sset_count = mtk_get_sset_count, 2779 .get_ethtool_stats = mtk_get_ethtool_stats, 2780 .get_rxnfc = mtk_get_rxnfc, 2781 .set_rxnfc = mtk_set_rxnfc, 2782 }; 2783 2784 static const struct net_device_ops mtk_netdev_ops = { 2785 .ndo_init = mtk_init, 2786 .ndo_uninit = mtk_uninit, 2787 .ndo_open = mtk_open, 2788 .ndo_stop = mtk_stop, 2789 .ndo_start_xmit = mtk_start_xmit, 2790 .ndo_set_mac_address = mtk_set_mac_address, 2791 .ndo_validate_addr = eth_validate_addr, 2792 .ndo_do_ioctl = mtk_do_ioctl, 2793 .ndo_tx_timeout = mtk_tx_timeout, 2794 .ndo_get_stats64 = mtk_get_stats64, 2795 .ndo_fix_features = mtk_fix_features, 2796 .ndo_set_features = mtk_set_features, 2797 #ifdef CONFIG_NET_POLL_CONTROLLER 2798 .ndo_poll_controller = mtk_poll_controller, 2799 #endif 2800 }; 2801 2802 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2803 { 2804 const __be32 *_id = of_get_property(np, "reg", NULL); 2805 phy_interface_t phy_mode; 2806 struct phylink *phylink; 2807 struct mtk_mac *mac; 2808 int id, err; 2809 2810 if (!_id) { 2811 dev_err(eth->dev, "missing mac id\n"); 2812 return -EINVAL; 2813 } 2814 2815 id = be32_to_cpup(_id); 2816 if (id >= MTK_MAC_COUNT) { 2817 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2818 return -EINVAL; 2819 } 2820 2821 if (eth->netdev[id]) { 2822 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2823 return -EINVAL; 2824 } 2825 2826 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2827 if (!eth->netdev[id]) { 2828 dev_err(eth->dev, "alloc_etherdev failed\n"); 2829 return -ENOMEM; 2830 } 2831 mac = netdev_priv(eth->netdev[id]); 2832 eth->mac[id] = mac; 2833 mac->id = id; 2834 mac->hw = eth; 2835 mac->of_node = np; 2836 2837 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2838 mac->hwlro_ip_cnt = 0; 2839 2840 mac->hw_stats = devm_kzalloc(eth->dev, 2841 sizeof(*mac->hw_stats), 2842 GFP_KERNEL); 2843 if (!mac->hw_stats) { 2844 dev_err(eth->dev, "failed to allocate counter memory\n"); 2845 err = -ENOMEM; 2846 goto free_netdev; 2847 } 2848 spin_lock_init(&mac->hw_stats->stats_lock); 2849 u64_stats_init(&mac->hw_stats->syncp); 2850 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2851 2852 /* phylink create */ 2853 err = of_get_phy_mode(np, &phy_mode); 2854 if (err) { 2855 dev_err(eth->dev, "incorrect phy-mode\n"); 2856 goto free_netdev; 2857 } 2858 2859 /* mac config is not set */ 2860 mac->interface = PHY_INTERFACE_MODE_NA; 2861 mac->mode = MLO_AN_PHY; 2862 mac->speed = SPEED_UNKNOWN; 2863 2864 mac->phylink_config.dev = ð->netdev[id]->dev; 2865 mac->phylink_config.type = PHYLINK_NETDEV; 2866 2867 phylink = phylink_create(&mac->phylink_config, 2868 of_fwnode_handle(mac->of_node), 2869 phy_mode, &mtk_phylink_ops); 2870 if (IS_ERR(phylink)) { 2871 err = PTR_ERR(phylink); 2872 goto free_netdev; 2873 } 2874 2875 mac->phylink = phylink; 2876 2877 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2878 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2879 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2880 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2881 2882 eth->netdev[id]->hw_features = eth->soc->hw_features; 2883 if (eth->hwlro) 2884 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2885 2886 eth->netdev[id]->vlan_features = eth->soc->hw_features & 2887 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2888 eth->netdev[id]->features |= eth->soc->hw_features; 2889 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2890 2891 eth->netdev[id]->irq = eth->irq[0]; 2892 eth->netdev[id]->dev.of_node = np; 2893 2894 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 2895 2896 return 0; 2897 2898 free_netdev: 2899 free_netdev(eth->netdev[id]); 2900 return err; 2901 } 2902 2903 static int mtk_probe(struct platform_device *pdev) 2904 { 2905 struct device_node *mac_np; 2906 struct mtk_eth *eth; 2907 int err, i; 2908 2909 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2910 if (!eth) 2911 return -ENOMEM; 2912 2913 eth->soc = of_device_get_match_data(&pdev->dev); 2914 2915 eth->dev = &pdev->dev; 2916 eth->base = devm_platform_ioremap_resource(pdev, 0); 2917 if (IS_ERR(eth->base)) 2918 return PTR_ERR(eth->base); 2919 2920 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2921 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 2922 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 2923 } else { 2924 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 2925 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 2926 } 2927 2928 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2929 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 2930 eth->ip_align = NET_IP_ALIGN; 2931 } else { 2932 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 2933 } 2934 2935 spin_lock_init(ð->page_lock); 2936 spin_lock_init(ð->tx_irq_lock); 2937 spin_lock_init(ð->rx_irq_lock); 2938 2939 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2940 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2941 "mediatek,ethsys"); 2942 if (IS_ERR(eth->ethsys)) { 2943 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2944 return PTR_ERR(eth->ethsys); 2945 } 2946 } 2947 2948 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2949 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2950 "mediatek,infracfg"); 2951 if (IS_ERR(eth->infra)) { 2952 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2953 return PTR_ERR(eth->infra); 2954 } 2955 } 2956 2957 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2958 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2959 GFP_KERNEL); 2960 if (!eth->sgmii) 2961 return -ENOMEM; 2962 2963 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2964 eth->soc->ana_rgc3); 2965 2966 if (err) 2967 return err; 2968 } 2969 2970 if (eth->soc->required_pctl) { 2971 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2972 "mediatek,pctl"); 2973 if (IS_ERR(eth->pctl)) { 2974 dev_err(&pdev->dev, "no pctl regmap found\n"); 2975 return PTR_ERR(eth->pctl); 2976 } 2977 } 2978 2979 for (i = 0; i < 3; i++) { 2980 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2981 eth->irq[i] = eth->irq[0]; 2982 else 2983 eth->irq[i] = platform_get_irq(pdev, i); 2984 if (eth->irq[i] < 0) { 2985 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2986 return -ENXIO; 2987 } 2988 } 2989 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2990 eth->clks[i] = devm_clk_get(eth->dev, 2991 mtk_clks_source_name[i]); 2992 if (IS_ERR(eth->clks[i])) { 2993 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2994 return -EPROBE_DEFER; 2995 if (eth->soc->required_clks & BIT(i)) { 2996 dev_err(&pdev->dev, "clock %s not found\n", 2997 mtk_clks_source_name[i]); 2998 return -EINVAL; 2999 } 3000 eth->clks[i] = NULL; 3001 } 3002 } 3003 3004 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 3005 INIT_WORK(ð->pending_work, mtk_pending_work); 3006 3007 err = mtk_hw_init(eth); 3008 if (err) 3009 return err; 3010 3011 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 3012 3013 for_each_child_of_node(pdev->dev.of_node, mac_np) { 3014 if (!of_device_is_compatible(mac_np, 3015 "mediatek,eth-mac")) 3016 continue; 3017 3018 if (!of_device_is_available(mac_np)) 3019 continue; 3020 3021 err = mtk_add_mac(eth, mac_np); 3022 if (err) { 3023 of_node_put(mac_np); 3024 goto err_deinit_hw; 3025 } 3026 } 3027 3028 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 3029 err = devm_request_irq(eth->dev, eth->irq[0], 3030 mtk_handle_irq, 0, 3031 dev_name(eth->dev), eth); 3032 } else { 3033 err = devm_request_irq(eth->dev, eth->irq[1], 3034 mtk_handle_irq_tx, 0, 3035 dev_name(eth->dev), eth); 3036 if (err) 3037 goto err_free_dev; 3038 3039 err = devm_request_irq(eth->dev, eth->irq[2], 3040 mtk_handle_irq_rx, 0, 3041 dev_name(eth->dev), eth); 3042 } 3043 if (err) 3044 goto err_free_dev; 3045 3046 /* No MT7628/88 support yet */ 3047 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3048 err = mtk_mdio_init(eth); 3049 if (err) 3050 goto err_free_dev; 3051 } 3052 3053 for (i = 0; i < MTK_MAX_DEVS; i++) { 3054 if (!eth->netdev[i]) 3055 continue; 3056 3057 err = register_netdev(eth->netdev[i]); 3058 if (err) { 3059 dev_err(eth->dev, "error bringing up device\n"); 3060 goto err_deinit_mdio; 3061 } else 3062 netif_info(eth, probe, eth->netdev[i], 3063 "mediatek frame engine at 0x%08lx, irq %d\n", 3064 eth->netdev[i]->base_addr, eth->irq[0]); 3065 } 3066 3067 /* we run 2 devices on the same DMA ring so we need a dummy device 3068 * for NAPI to work 3069 */ 3070 init_dummy_netdev(ð->dummy_dev); 3071 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3072 MTK_NAPI_WEIGHT); 3073 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3074 MTK_NAPI_WEIGHT); 3075 3076 platform_set_drvdata(pdev, eth); 3077 3078 return 0; 3079 3080 err_deinit_mdio: 3081 mtk_mdio_cleanup(eth); 3082 err_free_dev: 3083 mtk_free_dev(eth); 3084 err_deinit_hw: 3085 mtk_hw_deinit(eth); 3086 3087 return err; 3088 } 3089 3090 static int mtk_remove(struct platform_device *pdev) 3091 { 3092 struct mtk_eth *eth = platform_get_drvdata(pdev); 3093 struct mtk_mac *mac; 3094 int i; 3095 3096 /* stop all devices to make sure that dma is properly shut down */ 3097 for (i = 0; i < MTK_MAC_COUNT; i++) { 3098 if (!eth->netdev[i]) 3099 continue; 3100 mtk_stop(eth->netdev[i]); 3101 mac = netdev_priv(eth->netdev[i]); 3102 phylink_disconnect_phy(mac->phylink); 3103 } 3104 3105 mtk_hw_deinit(eth); 3106 3107 netif_napi_del(ð->tx_napi); 3108 netif_napi_del(ð->rx_napi); 3109 mtk_cleanup(eth); 3110 mtk_mdio_cleanup(eth); 3111 3112 return 0; 3113 } 3114 3115 static const struct mtk_soc_data mt2701_data = { 3116 .caps = MT7623_CAPS | MTK_HWLRO, 3117 .hw_features = MTK_HW_FEATURES, 3118 .required_clks = MT7623_CLKS_BITMAP, 3119 .required_pctl = true, 3120 }; 3121 3122 static const struct mtk_soc_data mt7621_data = { 3123 .caps = MT7621_CAPS, 3124 .hw_features = MTK_HW_FEATURES, 3125 .required_clks = MT7621_CLKS_BITMAP, 3126 .required_pctl = false, 3127 }; 3128 3129 static const struct mtk_soc_data mt7622_data = { 3130 .ana_rgc3 = 0x2028, 3131 .caps = MT7622_CAPS | MTK_HWLRO, 3132 .hw_features = MTK_HW_FEATURES, 3133 .required_clks = MT7622_CLKS_BITMAP, 3134 .required_pctl = false, 3135 }; 3136 3137 static const struct mtk_soc_data mt7623_data = { 3138 .caps = MT7623_CAPS | MTK_HWLRO, 3139 .hw_features = MTK_HW_FEATURES, 3140 .required_clks = MT7623_CLKS_BITMAP, 3141 .required_pctl = true, 3142 }; 3143 3144 static const struct mtk_soc_data mt7629_data = { 3145 .ana_rgc3 = 0x128, 3146 .caps = MT7629_CAPS | MTK_HWLRO, 3147 .hw_features = MTK_HW_FEATURES, 3148 .required_clks = MT7629_CLKS_BITMAP, 3149 .required_pctl = false, 3150 }; 3151 3152 static const struct mtk_soc_data rt5350_data = { 3153 .caps = MT7628_CAPS, 3154 .hw_features = MTK_HW_FEATURES_MT7628, 3155 .required_clks = MT7628_CLKS_BITMAP, 3156 .required_pctl = false, 3157 }; 3158 3159 const struct of_device_id of_mtk_match[] = { 3160 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3161 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3162 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3163 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3164 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3165 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3166 {}, 3167 }; 3168 MODULE_DEVICE_TABLE(of, of_mtk_match); 3169 3170 static struct platform_driver mtk_driver = { 3171 .probe = mtk_probe, 3172 .remove = mtk_remove, 3173 .driver = { 3174 .name = "mtk_soc_eth", 3175 .of_match_table = of_mtk_match, 3176 }, 3177 }; 3178 3179 module_platform_driver(mtk_driver); 3180 3181 MODULE_LICENSE("GPL"); 3182 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3183 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3184