1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 27 #include "mtk_eth_soc.h" 28 #include "mtk_wed.h" 29 30 static int mtk_msg_level = -1; 31 module_param_named(msg_level, mtk_msg_level, int, 0); 32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 33 34 #define MTK_ETHTOOL_STAT(x) { #x, \ 35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 36 37 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 38 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 39 sizeof(u64) } 40 41 static const struct mtk_reg_map mtk_reg_map = { 42 .tx_irq_mask = 0x1a1c, 43 .tx_irq_status = 0x1a18, 44 .pdma = { 45 .rx_ptr = 0x0900, 46 .rx_cnt_cfg = 0x0904, 47 .pcrx_ptr = 0x0908, 48 .glo_cfg = 0x0a04, 49 .rst_idx = 0x0a08, 50 .delay_irq = 0x0a0c, 51 .irq_status = 0x0a20, 52 .irq_mask = 0x0a28, 53 .int_grp = 0x0a50, 54 }, 55 .qdma = { 56 .qtx_cfg = 0x1800, 57 .rx_ptr = 0x1900, 58 .rx_cnt_cfg = 0x1904, 59 .qcrx_ptr = 0x1908, 60 .glo_cfg = 0x1a04, 61 .rst_idx = 0x1a08, 62 .delay_irq = 0x1a0c, 63 .fc_th = 0x1a10, 64 .int_grp = 0x1a20, 65 .hred = 0x1a44, 66 .ctx_ptr = 0x1b00, 67 .dtx_ptr = 0x1b04, 68 .crx_ptr = 0x1b10, 69 .drx_ptr = 0x1b14, 70 .fq_head = 0x1b20, 71 .fq_tail = 0x1b24, 72 .fq_count = 0x1b28, 73 .fq_blen = 0x1b2c, 74 }, 75 .gdm1_cnt = 0x2400, 76 }; 77 78 static const struct mtk_reg_map mt7628_reg_map = { 79 .tx_irq_mask = 0x0a28, 80 .tx_irq_status = 0x0a20, 81 .pdma = { 82 .rx_ptr = 0x0900, 83 .rx_cnt_cfg = 0x0904, 84 .pcrx_ptr = 0x0908, 85 .glo_cfg = 0x0a04, 86 .rst_idx = 0x0a08, 87 .delay_irq = 0x0a0c, 88 .irq_status = 0x0a20, 89 .irq_mask = 0x0a28, 90 .int_grp = 0x0a50, 91 }, 92 }; 93 94 static const struct mtk_reg_map mt7986_reg_map = { 95 .tx_irq_mask = 0x461c, 96 .tx_irq_status = 0x4618, 97 .pdma = { 98 .rx_ptr = 0x6100, 99 .rx_cnt_cfg = 0x6104, 100 .pcrx_ptr = 0x6108, 101 .glo_cfg = 0x6204, 102 .rst_idx = 0x6208, 103 .delay_irq = 0x620c, 104 .irq_status = 0x6220, 105 .irq_mask = 0x6228, 106 .int_grp = 0x6250, 107 }, 108 .qdma = { 109 .qtx_cfg = 0x4400, 110 .rx_ptr = 0x4500, 111 .rx_cnt_cfg = 0x4504, 112 .qcrx_ptr = 0x4508, 113 .glo_cfg = 0x4604, 114 .rst_idx = 0x4608, 115 .delay_irq = 0x460c, 116 .fc_th = 0x4610, 117 .int_grp = 0x4620, 118 .hred = 0x4644, 119 .ctx_ptr = 0x4700, 120 .dtx_ptr = 0x4704, 121 .crx_ptr = 0x4710, 122 .drx_ptr = 0x4714, 123 .fq_head = 0x4720, 124 .fq_tail = 0x4724, 125 .fq_count = 0x4728, 126 .fq_blen = 0x472c, 127 }, 128 .gdm1_cnt = 0x1c00, 129 }; 130 131 /* strings used by ethtool */ 132 static const struct mtk_ethtool_stats { 133 char str[ETH_GSTRING_LEN]; 134 u32 offset; 135 } mtk_ethtool_stats[] = { 136 MTK_ETHTOOL_STAT(tx_bytes), 137 MTK_ETHTOOL_STAT(tx_packets), 138 MTK_ETHTOOL_STAT(tx_skip), 139 MTK_ETHTOOL_STAT(tx_collisions), 140 MTK_ETHTOOL_STAT(rx_bytes), 141 MTK_ETHTOOL_STAT(rx_packets), 142 MTK_ETHTOOL_STAT(rx_overflow), 143 MTK_ETHTOOL_STAT(rx_fcs_errors), 144 MTK_ETHTOOL_STAT(rx_short_errors), 145 MTK_ETHTOOL_STAT(rx_long_errors), 146 MTK_ETHTOOL_STAT(rx_checksum_errors), 147 MTK_ETHTOOL_STAT(rx_flow_control_packets), 148 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 149 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 150 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 151 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 152 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 153 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 154 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 155 }; 156 157 static const char * const mtk_clks_source_name[] = { 158 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 159 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 160 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 161 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 162 }; 163 164 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 165 { 166 __raw_writel(val, eth->base + reg); 167 } 168 169 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 170 { 171 return __raw_readl(eth->base + reg); 172 } 173 174 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 175 { 176 u32 val; 177 178 val = mtk_r32(eth, reg); 179 val &= ~mask; 180 val |= set; 181 mtk_w32(eth, val, reg); 182 return reg; 183 } 184 185 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 186 { 187 unsigned long t_start = jiffies; 188 189 while (1) { 190 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 191 return 0; 192 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 193 break; 194 cond_resched(); 195 } 196 197 dev_err(eth->dev, "mdio: MDIO timeout\n"); 198 return -ETIMEDOUT; 199 } 200 201 static int _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 202 u32 write_data) 203 { 204 int ret; 205 206 ret = mtk_mdio_busy_wait(eth); 207 if (ret < 0) 208 return ret; 209 210 if (phy_reg & MII_ADDR_C45) { 211 mtk_w32(eth, PHY_IAC_ACCESS | 212 PHY_IAC_START_C45 | 213 PHY_IAC_CMD_C45_ADDR | 214 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 215 PHY_IAC_ADDR(phy_addr) | 216 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 217 MTK_PHY_IAC); 218 219 ret = mtk_mdio_busy_wait(eth); 220 if (ret < 0) 221 return ret; 222 223 mtk_w32(eth, PHY_IAC_ACCESS | 224 PHY_IAC_START_C45 | 225 PHY_IAC_CMD_WRITE | 226 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 227 PHY_IAC_ADDR(phy_addr) | 228 PHY_IAC_DATA(write_data), 229 MTK_PHY_IAC); 230 } else { 231 mtk_w32(eth, PHY_IAC_ACCESS | 232 PHY_IAC_START_C22 | 233 PHY_IAC_CMD_WRITE | 234 PHY_IAC_REG(phy_reg) | 235 PHY_IAC_ADDR(phy_addr) | 236 PHY_IAC_DATA(write_data), 237 MTK_PHY_IAC); 238 } 239 240 ret = mtk_mdio_busy_wait(eth); 241 if (ret < 0) 242 return ret; 243 244 return 0; 245 } 246 247 static int _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 248 { 249 int ret; 250 251 ret = mtk_mdio_busy_wait(eth); 252 if (ret < 0) 253 return ret; 254 255 if (phy_reg & MII_ADDR_C45) { 256 mtk_w32(eth, PHY_IAC_ACCESS | 257 PHY_IAC_START_C45 | 258 PHY_IAC_CMD_C45_ADDR | 259 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 260 PHY_IAC_ADDR(phy_addr) | 261 PHY_IAC_DATA(mdiobus_c45_regad(phy_reg)), 262 MTK_PHY_IAC); 263 264 ret = mtk_mdio_busy_wait(eth); 265 if (ret < 0) 266 return ret; 267 268 mtk_w32(eth, PHY_IAC_ACCESS | 269 PHY_IAC_START_C45 | 270 PHY_IAC_CMD_C45_READ | 271 PHY_IAC_REG(mdiobus_c45_devad(phy_reg)) | 272 PHY_IAC_ADDR(phy_addr), 273 MTK_PHY_IAC); 274 } else { 275 mtk_w32(eth, PHY_IAC_ACCESS | 276 PHY_IAC_START_C22 | 277 PHY_IAC_CMD_C22_READ | 278 PHY_IAC_REG(phy_reg) | 279 PHY_IAC_ADDR(phy_addr), 280 MTK_PHY_IAC); 281 } 282 283 ret = mtk_mdio_busy_wait(eth); 284 if (ret < 0) 285 return ret; 286 287 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 288 } 289 290 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 291 int phy_reg, u16 val) 292 { 293 struct mtk_eth *eth = bus->priv; 294 295 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 296 } 297 298 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 299 { 300 struct mtk_eth *eth = bus->priv; 301 302 return _mtk_mdio_read(eth, phy_addr, phy_reg); 303 } 304 305 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 306 phy_interface_t interface) 307 { 308 u32 val; 309 310 /* Check DDR memory type. 311 * Currently TRGMII mode with DDR2 memory is not supported. 312 */ 313 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 314 if (interface == PHY_INTERFACE_MODE_TRGMII && 315 val & SYSCFG_DRAM_TYPE_DDR2) { 316 dev_err(eth->dev, 317 "TRGMII mode with DDR2 memory is not supported!\n"); 318 return -EOPNOTSUPP; 319 } 320 321 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 322 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 323 324 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 325 ETHSYS_TRGMII_MT7621_MASK, val); 326 327 return 0; 328 } 329 330 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 331 phy_interface_t interface, int speed) 332 { 333 u32 val; 334 int ret; 335 336 if (interface == PHY_INTERFACE_MODE_TRGMII) { 337 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 338 val = 500000000; 339 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 340 if (ret) 341 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 342 return; 343 } 344 345 val = (speed == SPEED_1000) ? 346 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 347 mtk_w32(eth, val, INTF_MODE); 348 349 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 350 ETHSYS_TRGMII_CLK_SEL362_5, 351 ETHSYS_TRGMII_CLK_SEL362_5); 352 353 val = (speed == SPEED_1000) ? 250000000 : 500000000; 354 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 355 if (ret) 356 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 357 358 val = (speed == SPEED_1000) ? 359 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 360 mtk_w32(eth, val, TRGMII_RCK_CTRL); 361 362 val = (speed == SPEED_1000) ? 363 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 364 mtk_w32(eth, val, TRGMII_TCK_CTRL); 365 } 366 367 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 368 phy_interface_t interface) 369 { 370 struct mtk_mac *mac = container_of(config, struct mtk_mac, 371 phylink_config); 372 struct mtk_eth *eth = mac->hw; 373 unsigned int sid; 374 375 if (interface == PHY_INTERFACE_MODE_SGMII || 376 phy_interface_mode_is_8023z(interface)) { 377 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 378 0 : mac->id; 379 380 return mtk_sgmii_select_pcs(eth->sgmii, sid); 381 } 382 383 return NULL; 384 } 385 386 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 387 const struct phylink_link_state *state) 388 { 389 struct mtk_mac *mac = container_of(config, struct mtk_mac, 390 phylink_config); 391 struct mtk_eth *eth = mac->hw; 392 int val, ge_mode, err = 0; 393 u32 i; 394 395 /* MT76x8 has no hardware settings between for the MAC */ 396 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 397 mac->interface != state->interface) { 398 /* Setup soc pin functions */ 399 switch (state->interface) { 400 case PHY_INTERFACE_MODE_TRGMII: 401 if (mac->id) 402 goto err_phy; 403 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 404 MTK_GMAC1_TRGMII)) 405 goto err_phy; 406 fallthrough; 407 case PHY_INTERFACE_MODE_RGMII_TXID: 408 case PHY_INTERFACE_MODE_RGMII_RXID: 409 case PHY_INTERFACE_MODE_RGMII_ID: 410 case PHY_INTERFACE_MODE_RGMII: 411 case PHY_INTERFACE_MODE_MII: 412 case PHY_INTERFACE_MODE_REVMII: 413 case PHY_INTERFACE_MODE_RMII: 414 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 415 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 416 if (err) 417 goto init_err; 418 } 419 break; 420 case PHY_INTERFACE_MODE_1000BASEX: 421 case PHY_INTERFACE_MODE_2500BASEX: 422 case PHY_INTERFACE_MODE_SGMII: 423 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 424 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 425 if (err) 426 goto init_err; 427 } 428 break; 429 case PHY_INTERFACE_MODE_GMII: 430 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 431 err = mtk_gmac_gephy_path_setup(eth, mac->id); 432 if (err) 433 goto init_err; 434 } 435 break; 436 default: 437 goto err_phy; 438 } 439 440 /* Setup clock for 1st gmac */ 441 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 442 !phy_interface_mode_is_8023z(state->interface) && 443 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 444 if (MTK_HAS_CAPS(mac->hw->soc->caps, 445 MTK_TRGMII_MT7621_CLK)) { 446 if (mt7621_gmac0_rgmii_adjust(mac->hw, 447 state->interface)) 448 goto err_phy; 449 } else { 450 /* FIXME: this is incorrect. Not only does it 451 * use state->speed (which is not guaranteed 452 * to be correct) but it also makes use of it 453 * in a code path that will only be reachable 454 * when the PHY interface mode changes, not 455 * when the speed changes. Consequently, RGMII 456 * is probably broken. 457 */ 458 mtk_gmac0_rgmii_adjust(mac->hw, 459 state->interface, 460 state->speed); 461 462 /* mt7623_pad_clk_setup */ 463 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 464 mtk_w32(mac->hw, 465 TD_DM_DRVP(8) | TD_DM_DRVN(8), 466 TRGMII_TD_ODT(i)); 467 468 /* Assert/release MT7623 RXC reset */ 469 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 470 TRGMII_RCK_CTRL); 471 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 472 } 473 } 474 475 ge_mode = 0; 476 switch (state->interface) { 477 case PHY_INTERFACE_MODE_MII: 478 case PHY_INTERFACE_MODE_GMII: 479 ge_mode = 1; 480 break; 481 case PHY_INTERFACE_MODE_REVMII: 482 ge_mode = 2; 483 break; 484 case PHY_INTERFACE_MODE_RMII: 485 if (mac->id) 486 goto err_phy; 487 ge_mode = 3; 488 break; 489 default: 490 break; 491 } 492 493 /* put the gmac into the right mode */ 494 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 495 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 496 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 497 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 498 499 mac->interface = state->interface; 500 } 501 502 /* SGMII */ 503 if (state->interface == PHY_INTERFACE_MODE_SGMII || 504 phy_interface_mode_is_8023z(state->interface)) { 505 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 506 * being setup done. 507 */ 508 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 509 510 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 511 SYSCFG0_SGMII_MASK, 512 ~(u32)SYSCFG0_SGMII_MASK); 513 514 /* Save the syscfg0 value for mac_finish */ 515 mac->syscfg0 = val; 516 } else if (phylink_autoneg_inband(mode)) { 517 dev_err(eth->dev, 518 "In-band mode not supported in non SGMII mode!\n"); 519 return; 520 } 521 522 return; 523 524 err_phy: 525 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 526 mac->id, phy_modes(state->interface)); 527 return; 528 529 init_err: 530 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 531 mac->id, phy_modes(state->interface), err); 532 } 533 534 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 535 phy_interface_t interface) 536 { 537 struct mtk_mac *mac = container_of(config, struct mtk_mac, 538 phylink_config); 539 struct mtk_eth *eth = mac->hw; 540 u32 mcr_cur, mcr_new; 541 542 /* Enable SGMII */ 543 if (interface == PHY_INTERFACE_MODE_SGMII || 544 phy_interface_mode_is_8023z(interface)) 545 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 546 SYSCFG0_SGMII_MASK, mac->syscfg0); 547 548 /* Setup gmac */ 549 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 550 mcr_new = mcr_cur; 551 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 552 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 553 554 /* Only update control register when needed! */ 555 if (mcr_new != mcr_cur) 556 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 557 558 return 0; 559 } 560 561 static void mtk_mac_pcs_get_state(struct phylink_config *config, 562 struct phylink_link_state *state) 563 { 564 struct mtk_mac *mac = container_of(config, struct mtk_mac, 565 phylink_config); 566 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 567 568 state->link = (pmsr & MAC_MSR_LINK); 569 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 570 571 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 572 case 0: 573 state->speed = SPEED_10; 574 break; 575 case MAC_MSR_SPEED_100: 576 state->speed = SPEED_100; 577 break; 578 case MAC_MSR_SPEED_1000: 579 state->speed = SPEED_1000; 580 break; 581 default: 582 state->speed = SPEED_UNKNOWN; 583 break; 584 } 585 586 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 587 if (pmsr & MAC_MSR_RX_FC) 588 state->pause |= MLO_PAUSE_RX; 589 if (pmsr & MAC_MSR_TX_FC) 590 state->pause |= MLO_PAUSE_TX; 591 } 592 593 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 594 phy_interface_t interface) 595 { 596 struct mtk_mac *mac = container_of(config, struct mtk_mac, 597 phylink_config); 598 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 599 600 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 601 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 602 } 603 604 static void mtk_mac_link_up(struct phylink_config *config, 605 struct phy_device *phy, 606 unsigned int mode, phy_interface_t interface, 607 int speed, int duplex, bool tx_pause, bool rx_pause) 608 { 609 struct mtk_mac *mac = container_of(config, struct mtk_mac, 610 phylink_config); 611 u32 mcr; 612 613 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 614 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 615 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 616 MAC_MCR_FORCE_RX_FC); 617 618 /* Configure speed */ 619 switch (speed) { 620 case SPEED_2500: 621 case SPEED_1000: 622 mcr |= MAC_MCR_SPEED_1000; 623 break; 624 case SPEED_100: 625 mcr |= MAC_MCR_SPEED_100; 626 break; 627 } 628 629 /* Configure duplex */ 630 if (duplex == DUPLEX_FULL) 631 mcr |= MAC_MCR_FORCE_DPX; 632 633 /* Configure pause modes - phylink will avoid these for half duplex */ 634 if (tx_pause) 635 mcr |= MAC_MCR_FORCE_TX_FC; 636 if (rx_pause) 637 mcr |= MAC_MCR_FORCE_RX_FC; 638 639 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 640 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 641 } 642 643 static const struct phylink_mac_ops mtk_phylink_ops = { 644 .validate = phylink_generic_validate, 645 .mac_select_pcs = mtk_mac_select_pcs, 646 .mac_pcs_get_state = mtk_mac_pcs_get_state, 647 .mac_config = mtk_mac_config, 648 .mac_finish = mtk_mac_finish, 649 .mac_link_down = mtk_mac_link_down, 650 .mac_link_up = mtk_mac_link_up, 651 }; 652 653 static int mtk_mdio_init(struct mtk_eth *eth) 654 { 655 struct device_node *mii_np; 656 int ret; 657 658 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 659 if (!mii_np) { 660 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 661 return -ENODEV; 662 } 663 664 if (!of_device_is_available(mii_np)) { 665 ret = -ENODEV; 666 goto err_put_node; 667 } 668 669 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 670 if (!eth->mii_bus) { 671 ret = -ENOMEM; 672 goto err_put_node; 673 } 674 675 eth->mii_bus->name = "mdio"; 676 eth->mii_bus->read = mtk_mdio_read; 677 eth->mii_bus->write = mtk_mdio_write; 678 eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45; 679 eth->mii_bus->priv = eth; 680 eth->mii_bus->parent = eth->dev; 681 682 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 683 ret = of_mdiobus_register(eth->mii_bus, mii_np); 684 685 err_put_node: 686 of_node_put(mii_np); 687 return ret; 688 } 689 690 static void mtk_mdio_cleanup(struct mtk_eth *eth) 691 { 692 if (!eth->mii_bus) 693 return; 694 695 mdiobus_unregister(eth->mii_bus); 696 } 697 698 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 699 { 700 unsigned long flags; 701 u32 val; 702 703 spin_lock_irqsave(ð->tx_irq_lock, flags); 704 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 705 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 706 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 707 } 708 709 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 710 { 711 unsigned long flags; 712 u32 val; 713 714 spin_lock_irqsave(ð->tx_irq_lock, flags); 715 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 716 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 717 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 718 } 719 720 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 721 { 722 unsigned long flags; 723 u32 val; 724 725 spin_lock_irqsave(ð->rx_irq_lock, flags); 726 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 727 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 728 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 729 } 730 731 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 732 { 733 unsigned long flags; 734 u32 val; 735 736 spin_lock_irqsave(ð->rx_irq_lock, flags); 737 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 738 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 739 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 740 } 741 742 static int mtk_set_mac_address(struct net_device *dev, void *p) 743 { 744 int ret = eth_mac_addr(dev, p); 745 struct mtk_mac *mac = netdev_priv(dev); 746 struct mtk_eth *eth = mac->hw; 747 const char *macaddr = dev->dev_addr; 748 749 if (ret) 750 return ret; 751 752 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 753 return -EBUSY; 754 755 spin_lock_bh(&mac->hw->page_lock); 756 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 757 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 758 MT7628_SDM_MAC_ADRH); 759 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 760 (macaddr[4] << 8) | macaddr[5], 761 MT7628_SDM_MAC_ADRL); 762 } else { 763 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 764 MTK_GDMA_MAC_ADRH(mac->id)); 765 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 766 (macaddr[4] << 8) | macaddr[5], 767 MTK_GDMA_MAC_ADRL(mac->id)); 768 } 769 spin_unlock_bh(&mac->hw->page_lock); 770 771 return 0; 772 } 773 774 void mtk_stats_update_mac(struct mtk_mac *mac) 775 { 776 struct mtk_hw_stats *hw_stats = mac->hw_stats; 777 struct mtk_eth *eth = mac->hw; 778 779 u64_stats_update_begin(&hw_stats->syncp); 780 781 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 782 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 783 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 784 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 785 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 786 hw_stats->rx_checksum_errors += 787 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 788 } else { 789 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 790 unsigned int offs = hw_stats->reg_offset; 791 u64 stats; 792 793 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 794 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 795 if (stats) 796 hw_stats->rx_bytes += (stats << 32); 797 hw_stats->rx_packets += 798 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 799 hw_stats->rx_overflow += 800 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 801 hw_stats->rx_fcs_errors += 802 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 803 hw_stats->rx_short_errors += 804 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 805 hw_stats->rx_long_errors += 806 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 807 hw_stats->rx_checksum_errors += 808 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 809 hw_stats->rx_flow_control_packets += 810 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 811 hw_stats->tx_skip += 812 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 813 hw_stats->tx_collisions += 814 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 815 hw_stats->tx_bytes += 816 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 817 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 818 if (stats) 819 hw_stats->tx_bytes += (stats << 32); 820 hw_stats->tx_packets += 821 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 822 } 823 824 u64_stats_update_end(&hw_stats->syncp); 825 } 826 827 static void mtk_stats_update(struct mtk_eth *eth) 828 { 829 int i; 830 831 for (i = 0; i < MTK_MAC_COUNT; i++) { 832 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 833 continue; 834 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 835 mtk_stats_update_mac(eth->mac[i]); 836 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 837 } 838 } 839 } 840 841 static void mtk_get_stats64(struct net_device *dev, 842 struct rtnl_link_stats64 *storage) 843 { 844 struct mtk_mac *mac = netdev_priv(dev); 845 struct mtk_hw_stats *hw_stats = mac->hw_stats; 846 unsigned int start; 847 848 if (netif_running(dev) && netif_device_present(dev)) { 849 if (spin_trylock_bh(&hw_stats->stats_lock)) { 850 mtk_stats_update_mac(mac); 851 spin_unlock_bh(&hw_stats->stats_lock); 852 } 853 } 854 855 do { 856 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 857 storage->rx_packets = hw_stats->rx_packets; 858 storage->tx_packets = hw_stats->tx_packets; 859 storage->rx_bytes = hw_stats->rx_bytes; 860 storage->tx_bytes = hw_stats->tx_bytes; 861 storage->collisions = hw_stats->tx_collisions; 862 storage->rx_length_errors = hw_stats->rx_short_errors + 863 hw_stats->rx_long_errors; 864 storage->rx_over_errors = hw_stats->rx_overflow; 865 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 866 storage->rx_errors = hw_stats->rx_checksum_errors; 867 storage->tx_aborted_errors = hw_stats->tx_skip; 868 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 869 870 storage->tx_errors = dev->stats.tx_errors; 871 storage->rx_dropped = dev->stats.rx_dropped; 872 storage->tx_dropped = dev->stats.tx_dropped; 873 } 874 875 static inline int mtk_max_frag_size(int mtu) 876 { 877 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 878 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 879 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 880 881 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 882 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 883 } 884 885 static inline int mtk_max_buf_size(int frag_size) 886 { 887 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 888 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 889 890 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 891 892 return buf_size; 893 } 894 895 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 896 struct mtk_rx_dma_v2 *dma_rxd) 897 { 898 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 899 if (!(rxd->rxd2 & RX_DMA_DONE)) 900 return false; 901 902 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 903 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 904 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 905 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 906 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 907 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 908 } 909 910 return true; 911 } 912 913 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 914 { 915 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 916 unsigned long data; 917 918 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 919 get_order(size)); 920 921 return (void *)data; 922 } 923 924 /* the qdma core needs scratch memory to be setup */ 925 static int mtk_init_fq_dma(struct mtk_eth *eth) 926 { 927 const struct mtk_soc_data *soc = eth->soc; 928 dma_addr_t phy_ring_tail; 929 int cnt = MTK_DMA_SIZE; 930 dma_addr_t dma_addr; 931 int i; 932 933 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 934 cnt * soc->txrx.txd_size, 935 ð->phy_scratch_ring, 936 GFP_KERNEL); 937 if (unlikely(!eth->scratch_ring)) 938 return -ENOMEM; 939 940 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 941 if (unlikely(!eth->scratch_head)) 942 return -ENOMEM; 943 944 dma_addr = dma_map_single(eth->dma_dev, 945 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 946 DMA_FROM_DEVICE); 947 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 948 return -ENOMEM; 949 950 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 951 952 for (i = 0; i < cnt; i++) { 953 struct mtk_tx_dma_v2 *txd; 954 955 txd = eth->scratch_ring + i * soc->txrx.txd_size; 956 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 957 if (i < cnt - 1) 958 txd->txd2 = eth->phy_scratch_ring + 959 (i + 1) * soc->txrx.txd_size; 960 961 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 962 txd->txd4 = 0; 963 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 964 txd->txd5 = 0; 965 txd->txd6 = 0; 966 txd->txd7 = 0; 967 txd->txd8 = 0; 968 } 969 } 970 971 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 972 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 973 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 974 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 975 976 return 0; 977 } 978 979 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 980 { 981 return ring->dma + (desc - ring->phys); 982 } 983 984 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 985 void *txd, u32 txd_size) 986 { 987 int idx = (txd - ring->dma) / txd_size; 988 989 return &ring->buf[idx]; 990 } 991 992 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 993 struct mtk_tx_dma *dma) 994 { 995 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 996 } 997 998 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 999 { 1000 return (dma - ring->dma) / txd_size; 1001 } 1002 1003 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1004 struct xdp_frame_bulk *bq, bool napi) 1005 { 1006 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1007 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1008 dma_unmap_single(eth->dma_dev, 1009 dma_unmap_addr(tx_buf, dma_addr0), 1010 dma_unmap_len(tx_buf, dma_len0), 1011 DMA_TO_DEVICE); 1012 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1013 dma_unmap_page(eth->dma_dev, 1014 dma_unmap_addr(tx_buf, dma_addr0), 1015 dma_unmap_len(tx_buf, dma_len0), 1016 DMA_TO_DEVICE); 1017 } 1018 } else { 1019 if (dma_unmap_len(tx_buf, dma_len0)) { 1020 dma_unmap_page(eth->dma_dev, 1021 dma_unmap_addr(tx_buf, dma_addr0), 1022 dma_unmap_len(tx_buf, dma_len0), 1023 DMA_TO_DEVICE); 1024 } 1025 1026 if (dma_unmap_len(tx_buf, dma_len1)) { 1027 dma_unmap_page(eth->dma_dev, 1028 dma_unmap_addr(tx_buf, dma_addr1), 1029 dma_unmap_len(tx_buf, dma_len1), 1030 DMA_TO_DEVICE); 1031 } 1032 } 1033 1034 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1035 if (tx_buf->type == MTK_TYPE_SKB) { 1036 struct sk_buff *skb = tx_buf->data; 1037 1038 if (napi) 1039 napi_consume_skb(skb, napi); 1040 else 1041 dev_kfree_skb_any(skb); 1042 } else { 1043 struct xdp_frame *xdpf = tx_buf->data; 1044 1045 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1046 xdp_return_frame_rx_napi(xdpf); 1047 else if (bq) 1048 xdp_return_frame_bulk(xdpf, bq); 1049 else 1050 xdp_return_frame(xdpf); 1051 } 1052 } 1053 tx_buf->flags = 0; 1054 tx_buf->data = NULL; 1055 } 1056 1057 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1058 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1059 size_t size, int idx) 1060 { 1061 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1062 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1063 dma_unmap_len_set(tx_buf, dma_len0, size); 1064 } else { 1065 if (idx & 1) { 1066 txd->txd3 = mapped_addr; 1067 txd->txd2 |= TX_DMA_PLEN1(size); 1068 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1069 dma_unmap_len_set(tx_buf, dma_len1, size); 1070 } else { 1071 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1072 txd->txd1 = mapped_addr; 1073 txd->txd2 = TX_DMA_PLEN0(size); 1074 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1075 dma_unmap_len_set(tx_buf, dma_len0, size); 1076 } 1077 } 1078 } 1079 1080 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1081 struct mtk_tx_dma_desc_info *info) 1082 { 1083 struct mtk_mac *mac = netdev_priv(dev); 1084 struct mtk_eth *eth = mac->hw; 1085 struct mtk_tx_dma *desc = txd; 1086 u32 data; 1087 1088 WRITE_ONCE(desc->txd1, info->addr); 1089 1090 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size); 1091 if (info->last) 1092 data |= TX_DMA_LS0; 1093 WRITE_ONCE(desc->txd3, data); 1094 1095 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1096 if (info->first) { 1097 if (info->gso) 1098 data |= TX_DMA_TSO; 1099 /* tx checksum offload */ 1100 if (info->csum) 1101 data |= TX_DMA_CHKSUM; 1102 /* vlan header offload */ 1103 if (info->vlan) 1104 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1105 } 1106 WRITE_ONCE(desc->txd4, data); 1107 } 1108 1109 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1110 struct mtk_tx_dma_desc_info *info) 1111 { 1112 struct mtk_mac *mac = netdev_priv(dev); 1113 struct mtk_tx_dma_v2 *desc = txd; 1114 struct mtk_eth *eth = mac->hw; 1115 u32 data; 1116 1117 WRITE_ONCE(desc->txd1, info->addr); 1118 1119 data = TX_DMA_PLEN0(info->size); 1120 if (info->last) 1121 data |= TX_DMA_LS0; 1122 WRITE_ONCE(desc->txd3, data); 1123 1124 if (!info->qid && mac->id) 1125 info->qid = MTK_QDMA_GMAC2_QID; 1126 1127 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1128 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1129 WRITE_ONCE(desc->txd4, data); 1130 1131 data = 0; 1132 if (info->first) { 1133 if (info->gso) 1134 data |= TX_DMA_TSO_V2; 1135 /* tx checksum offload */ 1136 if (info->csum) 1137 data |= TX_DMA_CHKSUM_V2; 1138 } 1139 WRITE_ONCE(desc->txd5, data); 1140 1141 data = 0; 1142 if (info->first && info->vlan) 1143 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1144 WRITE_ONCE(desc->txd6, data); 1145 1146 WRITE_ONCE(desc->txd7, 0); 1147 WRITE_ONCE(desc->txd8, 0); 1148 } 1149 1150 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1151 struct mtk_tx_dma_desc_info *info) 1152 { 1153 struct mtk_mac *mac = netdev_priv(dev); 1154 struct mtk_eth *eth = mac->hw; 1155 1156 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1157 mtk_tx_set_dma_desc_v2(dev, txd, info); 1158 else 1159 mtk_tx_set_dma_desc_v1(dev, txd, info); 1160 } 1161 1162 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1163 int tx_num, struct mtk_tx_ring *ring, bool gso) 1164 { 1165 struct mtk_tx_dma_desc_info txd_info = { 1166 .size = skb_headlen(skb), 1167 .gso = gso, 1168 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1169 .vlan = skb_vlan_tag_present(skb), 1170 .qid = skb->mark & MTK_QDMA_TX_MASK, 1171 .vlan_tci = skb_vlan_tag_get(skb), 1172 .first = true, 1173 .last = !skb_is_nonlinear(skb), 1174 }; 1175 struct mtk_mac *mac = netdev_priv(dev); 1176 struct mtk_eth *eth = mac->hw; 1177 const struct mtk_soc_data *soc = eth->soc; 1178 struct mtk_tx_dma *itxd, *txd; 1179 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1180 struct mtk_tx_buf *itx_buf, *tx_buf; 1181 int i, n_desc = 1; 1182 int k = 0; 1183 1184 itxd = ring->next_free; 1185 itxd_pdma = qdma_to_pdma(ring, itxd); 1186 if (itxd == ring->last_free) 1187 return -ENOMEM; 1188 1189 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1190 memset(itx_buf, 0, sizeof(*itx_buf)); 1191 1192 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1193 DMA_TO_DEVICE); 1194 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1195 return -ENOMEM; 1196 1197 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1198 1199 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1200 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1201 MTK_TX_FLAGS_FPORT1; 1202 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1203 k++); 1204 1205 /* TX SG offload */ 1206 txd = itxd; 1207 txd_pdma = qdma_to_pdma(ring, txd); 1208 1209 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1210 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1211 unsigned int offset = 0; 1212 int frag_size = skb_frag_size(frag); 1213 1214 while (frag_size) { 1215 bool new_desc = true; 1216 1217 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1218 (i & 0x1)) { 1219 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1220 txd_pdma = qdma_to_pdma(ring, txd); 1221 if (txd == ring->last_free) 1222 goto err_dma; 1223 1224 n_desc++; 1225 } else { 1226 new_desc = false; 1227 } 1228 1229 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1230 txd_info.size = min_t(unsigned int, frag_size, 1231 soc->txrx.dma_max_len); 1232 txd_info.qid = skb->mark & MTK_QDMA_TX_MASK; 1233 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1234 !(frag_size - txd_info.size); 1235 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1236 offset, txd_info.size, 1237 DMA_TO_DEVICE); 1238 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1239 goto err_dma; 1240 1241 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1242 1243 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1244 soc->txrx.txd_size); 1245 if (new_desc) 1246 memset(tx_buf, 0, sizeof(*tx_buf)); 1247 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1248 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1249 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1250 MTK_TX_FLAGS_FPORT1; 1251 1252 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1253 txd_info.size, k++); 1254 1255 frag_size -= txd_info.size; 1256 offset += txd_info.size; 1257 } 1258 } 1259 1260 /* store skb to cleanup */ 1261 itx_buf->type = MTK_TYPE_SKB; 1262 itx_buf->data = skb; 1263 1264 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1265 if (k & 0x1) 1266 txd_pdma->txd2 |= TX_DMA_LS0; 1267 else 1268 txd_pdma->txd2 |= TX_DMA_LS1; 1269 } 1270 1271 netdev_sent_queue(dev, skb->len); 1272 skb_tx_timestamp(skb); 1273 1274 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1275 atomic_sub(n_desc, &ring->free_count); 1276 1277 /* make sure that all changes to the dma ring are flushed before we 1278 * continue 1279 */ 1280 wmb(); 1281 1282 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1283 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1284 !netdev_xmit_more()) 1285 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1286 } else { 1287 int next_idx; 1288 1289 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1290 ring->dma_size); 1291 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1292 } 1293 1294 return 0; 1295 1296 err_dma: 1297 do { 1298 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1299 1300 /* unmap dma */ 1301 mtk_tx_unmap(eth, tx_buf, NULL, false); 1302 1303 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1304 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1305 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1306 1307 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1308 itxd_pdma = qdma_to_pdma(ring, itxd); 1309 } while (itxd != txd); 1310 1311 return -ENOMEM; 1312 } 1313 1314 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1315 { 1316 int i, nfrags = 1; 1317 skb_frag_t *frag; 1318 1319 if (skb_is_gso(skb)) { 1320 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1321 frag = &skb_shinfo(skb)->frags[i]; 1322 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1323 eth->soc->txrx.dma_max_len); 1324 } 1325 } else { 1326 nfrags += skb_shinfo(skb)->nr_frags; 1327 } 1328 1329 return nfrags; 1330 } 1331 1332 static int mtk_queue_stopped(struct mtk_eth *eth) 1333 { 1334 int i; 1335 1336 for (i = 0; i < MTK_MAC_COUNT; i++) { 1337 if (!eth->netdev[i]) 1338 continue; 1339 if (netif_queue_stopped(eth->netdev[i])) 1340 return 1; 1341 } 1342 1343 return 0; 1344 } 1345 1346 static void mtk_wake_queue(struct mtk_eth *eth) 1347 { 1348 int i; 1349 1350 for (i = 0; i < MTK_MAC_COUNT; i++) { 1351 if (!eth->netdev[i]) 1352 continue; 1353 netif_wake_queue(eth->netdev[i]); 1354 } 1355 } 1356 1357 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1358 { 1359 struct mtk_mac *mac = netdev_priv(dev); 1360 struct mtk_eth *eth = mac->hw; 1361 struct mtk_tx_ring *ring = ð->tx_ring; 1362 struct net_device_stats *stats = &dev->stats; 1363 bool gso = false; 1364 int tx_num; 1365 1366 /* normally we can rely on the stack not calling this more than once, 1367 * however we have 2 queues running on the same ring so we need to lock 1368 * the ring access 1369 */ 1370 spin_lock(ð->page_lock); 1371 1372 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1373 goto drop; 1374 1375 tx_num = mtk_cal_txd_req(eth, skb); 1376 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1377 netif_stop_queue(dev); 1378 netif_err(eth, tx_queued, dev, 1379 "Tx Ring full when queue awake!\n"); 1380 spin_unlock(ð->page_lock); 1381 return NETDEV_TX_BUSY; 1382 } 1383 1384 /* TSO: fill MSS info in tcp checksum field */ 1385 if (skb_is_gso(skb)) { 1386 if (skb_cow_head(skb, 0)) { 1387 netif_warn(eth, tx_err, dev, 1388 "GSO expand head fail.\n"); 1389 goto drop; 1390 } 1391 1392 if (skb_shinfo(skb)->gso_type & 1393 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1394 gso = true; 1395 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1396 } 1397 } 1398 1399 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1400 goto drop; 1401 1402 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1403 netif_stop_queue(dev); 1404 1405 spin_unlock(ð->page_lock); 1406 1407 return NETDEV_TX_OK; 1408 1409 drop: 1410 spin_unlock(ð->page_lock); 1411 stats->tx_dropped++; 1412 dev_kfree_skb_any(skb); 1413 return NETDEV_TX_OK; 1414 } 1415 1416 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1417 { 1418 int i; 1419 struct mtk_rx_ring *ring; 1420 int idx; 1421 1422 if (!eth->hwlro) 1423 return ð->rx_ring[0]; 1424 1425 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1426 struct mtk_rx_dma *rxd; 1427 1428 ring = ð->rx_ring[i]; 1429 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1430 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1431 if (rxd->rxd2 & RX_DMA_DONE) { 1432 ring->calc_idx_update = true; 1433 return ring; 1434 } 1435 } 1436 1437 return NULL; 1438 } 1439 1440 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1441 { 1442 struct mtk_rx_ring *ring; 1443 int i; 1444 1445 if (!eth->hwlro) { 1446 ring = ð->rx_ring[0]; 1447 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1448 } else { 1449 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1450 ring = ð->rx_ring[i]; 1451 if (ring->calc_idx_update) { 1452 ring->calc_idx_update = false; 1453 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1454 } 1455 } 1456 } 1457 } 1458 1459 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1460 { 1461 return !eth->hwlro; 1462 } 1463 1464 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1465 struct xdp_rxq_info *xdp_q, 1466 int id, int size) 1467 { 1468 struct page_pool_params pp_params = { 1469 .order = 0, 1470 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1471 .pool_size = size, 1472 .nid = NUMA_NO_NODE, 1473 .dev = eth->dma_dev, 1474 .offset = MTK_PP_HEADROOM, 1475 .max_len = MTK_PP_MAX_BUF_SIZE, 1476 }; 1477 struct page_pool *pp; 1478 int err; 1479 1480 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1481 : DMA_FROM_DEVICE; 1482 pp = page_pool_create(&pp_params); 1483 if (IS_ERR(pp)) 1484 return pp; 1485 1486 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, eth->rx_napi.napi_id, 1487 id, PAGE_SIZE); 1488 if (err < 0) 1489 goto err_free_pp; 1490 1491 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1492 if (err) 1493 goto err_unregister_rxq; 1494 1495 return pp; 1496 1497 err_unregister_rxq: 1498 xdp_rxq_info_unreg(xdp_q); 1499 err_free_pp: 1500 page_pool_destroy(pp); 1501 1502 return ERR_PTR(err); 1503 } 1504 1505 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1506 gfp_t gfp_mask) 1507 { 1508 struct page *page; 1509 1510 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1511 if (!page) 1512 return NULL; 1513 1514 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1515 return page_address(page); 1516 } 1517 1518 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1519 { 1520 if (ring->page_pool) 1521 page_pool_put_full_page(ring->page_pool, 1522 virt_to_head_page(data), napi); 1523 else 1524 skb_free_frag(data); 1525 } 1526 1527 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1528 struct mtk_tx_dma_desc_info *txd_info, 1529 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1530 void *data, u16 headroom, int index, bool dma_map) 1531 { 1532 struct mtk_tx_ring *ring = ð->tx_ring; 1533 struct mtk_mac *mac = netdev_priv(dev); 1534 struct mtk_tx_dma *txd_pdma; 1535 1536 if (dma_map) { /* ndo_xdp_xmit */ 1537 txd_info->addr = dma_map_single(eth->dma_dev, data, 1538 txd_info->size, DMA_TO_DEVICE); 1539 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1540 return -ENOMEM; 1541 1542 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1543 } else { 1544 struct page *page = virt_to_head_page(data); 1545 1546 txd_info->addr = page_pool_get_dma_addr(page) + 1547 sizeof(struct xdp_frame) + headroom; 1548 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1549 txd_info->size, DMA_BIDIRECTIONAL); 1550 } 1551 mtk_tx_set_dma_desc(dev, txd, txd_info); 1552 1553 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1554 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1555 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1556 1557 txd_pdma = qdma_to_pdma(ring, txd); 1558 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1559 index); 1560 1561 return 0; 1562 } 1563 1564 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1565 struct net_device *dev, bool dma_map) 1566 { 1567 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1568 const struct mtk_soc_data *soc = eth->soc; 1569 struct mtk_tx_ring *ring = ð->tx_ring; 1570 struct mtk_tx_dma_desc_info txd_info = { 1571 .size = xdpf->len, 1572 .first = true, 1573 .last = !xdp_frame_has_frags(xdpf), 1574 }; 1575 int err, index = 0, n_desc = 1, nr_frags; 1576 struct mtk_tx_buf *htx_buf, *tx_buf; 1577 struct mtk_tx_dma *htxd, *txd; 1578 void *data = xdpf->data; 1579 1580 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1581 return -EBUSY; 1582 1583 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1584 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1585 return -EBUSY; 1586 1587 spin_lock(ð->page_lock); 1588 1589 txd = ring->next_free; 1590 if (txd == ring->last_free) { 1591 spin_unlock(ð->page_lock); 1592 return -ENOMEM; 1593 } 1594 htxd = txd; 1595 1596 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1597 memset(tx_buf, 0, sizeof(*tx_buf)); 1598 htx_buf = tx_buf; 1599 1600 for (;;) { 1601 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1602 data, xdpf->headroom, index, dma_map); 1603 if (err < 0) 1604 goto unmap; 1605 1606 if (txd_info.last) 1607 break; 1608 1609 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1610 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1611 if (txd == ring->last_free) 1612 goto unmap; 1613 1614 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1615 soc->txrx.txd_size); 1616 memset(tx_buf, 0, sizeof(*tx_buf)); 1617 n_desc++; 1618 } 1619 1620 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1621 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1622 txd_info.last = index + 1 == nr_frags; 1623 data = skb_frag_address(&sinfo->frags[index]); 1624 1625 index++; 1626 } 1627 /* store xdpf for cleanup */ 1628 htx_buf->data = xdpf; 1629 1630 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1631 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1632 1633 if (index & 1) 1634 txd_pdma->txd2 |= TX_DMA_LS0; 1635 else 1636 txd_pdma->txd2 |= TX_DMA_LS1; 1637 } 1638 1639 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1640 atomic_sub(n_desc, &ring->free_count); 1641 1642 /* make sure that all changes to the dma ring are flushed before we 1643 * continue 1644 */ 1645 wmb(); 1646 1647 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1648 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1649 } else { 1650 int idx; 1651 1652 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1653 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1654 MT7628_TX_CTX_IDX0); 1655 } 1656 1657 spin_unlock(ð->page_lock); 1658 1659 return 0; 1660 1661 unmap: 1662 while (htxd != txd) { 1663 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1664 mtk_tx_unmap(eth, tx_buf, NULL, false); 1665 1666 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1667 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1668 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1669 1670 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1671 } 1672 1673 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1674 } 1675 1676 spin_unlock(ð->page_lock); 1677 1678 return err; 1679 } 1680 1681 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1682 struct xdp_frame **frames, u32 flags) 1683 { 1684 struct mtk_mac *mac = netdev_priv(dev); 1685 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1686 struct mtk_eth *eth = mac->hw; 1687 int i, nxmit = 0; 1688 1689 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1690 return -EINVAL; 1691 1692 for (i = 0; i < num_frame; i++) { 1693 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1694 break; 1695 nxmit++; 1696 } 1697 1698 u64_stats_update_begin(&hw_stats->syncp); 1699 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1700 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1701 u64_stats_update_end(&hw_stats->syncp); 1702 1703 return nxmit; 1704 } 1705 1706 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1707 struct xdp_buff *xdp, struct net_device *dev) 1708 { 1709 struct mtk_mac *mac = netdev_priv(dev); 1710 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1711 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1712 struct bpf_prog *prog; 1713 u32 act = XDP_PASS; 1714 1715 rcu_read_lock(); 1716 1717 prog = rcu_dereference(eth->prog); 1718 if (!prog) 1719 goto out; 1720 1721 act = bpf_prog_run_xdp(prog, xdp); 1722 switch (act) { 1723 case XDP_PASS: 1724 count = &hw_stats->xdp_stats.rx_xdp_pass; 1725 goto update_stats; 1726 case XDP_REDIRECT: 1727 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1728 act = XDP_DROP; 1729 break; 1730 } 1731 1732 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1733 goto update_stats; 1734 case XDP_TX: { 1735 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1736 1737 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1738 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1739 act = XDP_DROP; 1740 break; 1741 } 1742 1743 count = &hw_stats->xdp_stats.rx_xdp_tx; 1744 goto update_stats; 1745 } 1746 default: 1747 bpf_warn_invalid_xdp_action(dev, prog, act); 1748 fallthrough; 1749 case XDP_ABORTED: 1750 trace_xdp_exception(dev, prog, act); 1751 fallthrough; 1752 case XDP_DROP: 1753 break; 1754 } 1755 1756 page_pool_put_full_page(ring->page_pool, 1757 virt_to_head_page(xdp->data), true); 1758 1759 update_stats: 1760 u64_stats_update_begin(&hw_stats->syncp); 1761 *count = *count + 1; 1762 u64_stats_update_end(&hw_stats->syncp); 1763 out: 1764 rcu_read_unlock(); 1765 1766 return act; 1767 } 1768 1769 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1770 struct mtk_eth *eth) 1771 { 1772 struct dim_sample dim_sample = {}; 1773 struct mtk_rx_ring *ring; 1774 bool xdp_flush = false; 1775 int idx; 1776 struct sk_buff *skb; 1777 u8 *data, *new_data; 1778 struct mtk_rx_dma_v2 *rxd, trxd; 1779 int done = 0, bytes = 0; 1780 1781 while (done < budget) { 1782 unsigned int pktlen, *rxdcsum; 1783 struct net_device *netdev; 1784 dma_addr_t dma_addr; 1785 u32 hash, reason; 1786 int mac = 0; 1787 1788 ring = mtk_get_rx_ring(eth); 1789 if (unlikely(!ring)) 1790 goto rx_done; 1791 1792 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1793 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1794 data = ring->data[idx]; 1795 1796 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1797 break; 1798 1799 /* find out which mac the packet come from. values start at 1 */ 1800 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1801 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1802 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1803 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1804 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1805 1806 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1807 !eth->netdev[mac])) 1808 goto release_desc; 1809 1810 netdev = eth->netdev[mac]; 1811 1812 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1813 goto release_desc; 1814 1815 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1816 1817 /* alloc new buffer */ 1818 if (ring->page_pool) { 1819 struct page *page = virt_to_head_page(data); 1820 struct xdp_buff xdp; 1821 u32 ret; 1822 1823 new_data = mtk_page_pool_get_buff(ring->page_pool, 1824 &dma_addr, 1825 GFP_ATOMIC); 1826 if (unlikely(!new_data)) { 1827 netdev->stats.rx_dropped++; 1828 goto release_desc; 1829 } 1830 1831 dma_sync_single_for_cpu(eth->dma_dev, 1832 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1833 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1834 1835 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1836 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1837 false); 1838 xdp_buff_clear_frags_flag(&xdp); 1839 1840 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1841 if (ret == XDP_REDIRECT) 1842 xdp_flush = true; 1843 1844 if (ret != XDP_PASS) 1845 goto skip_rx; 1846 1847 skb = build_skb(data, PAGE_SIZE); 1848 if (unlikely(!skb)) { 1849 page_pool_put_full_page(ring->page_pool, 1850 page, true); 1851 netdev->stats.rx_dropped++; 1852 goto skip_rx; 1853 } 1854 1855 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1856 skb_put(skb, xdp.data_end - xdp.data); 1857 skb_mark_for_recycle(skb); 1858 } else { 1859 if (ring->frag_size <= PAGE_SIZE) 1860 new_data = napi_alloc_frag(ring->frag_size); 1861 else 1862 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 1863 1864 if (unlikely(!new_data)) { 1865 netdev->stats.rx_dropped++; 1866 goto release_desc; 1867 } 1868 1869 dma_addr = dma_map_single(eth->dma_dev, 1870 new_data + NET_SKB_PAD + eth->ip_align, 1871 ring->buf_size, DMA_FROM_DEVICE); 1872 if (unlikely(dma_mapping_error(eth->dma_dev, 1873 dma_addr))) { 1874 skb_free_frag(new_data); 1875 netdev->stats.rx_dropped++; 1876 goto release_desc; 1877 } 1878 1879 dma_unmap_single(eth->dma_dev, trxd.rxd1, 1880 ring->buf_size, DMA_FROM_DEVICE); 1881 1882 skb = build_skb(data, ring->frag_size); 1883 if (unlikely(!skb)) { 1884 netdev->stats.rx_dropped++; 1885 skb_free_frag(data); 1886 goto skip_rx; 1887 } 1888 1889 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1890 skb_put(skb, pktlen); 1891 } 1892 1893 skb->dev = netdev; 1894 bytes += skb->len; 1895 1896 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1897 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 1898 if (hash != MTK_RXD5_FOE_ENTRY) 1899 skb_set_hash(skb, jhash_1word(hash, 0), 1900 PKT_HASH_TYPE_L4); 1901 rxdcsum = &trxd.rxd3; 1902 } else { 1903 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 1904 if (hash != MTK_RXD4_FOE_ENTRY) 1905 skb_set_hash(skb, jhash_1word(hash, 0), 1906 PKT_HASH_TYPE_L4); 1907 rxdcsum = &trxd.rxd4; 1908 } 1909 1910 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 1911 skb->ip_summed = CHECKSUM_UNNECESSARY; 1912 else 1913 skb_checksum_none_assert(skb); 1914 skb->protocol = eth_type_trans(skb, netdev); 1915 1916 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 1917 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 1918 mtk_ppe_check_skb(eth->ppe, skb, hash); 1919 1920 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 1921 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1922 if (trxd.rxd3 & RX_DMA_VTAG_V2) 1923 __vlan_hwaccel_put_tag(skb, 1924 htons(RX_DMA_VPID(trxd.rxd4)), 1925 RX_DMA_VID(trxd.rxd4)); 1926 } else if (trxd.rxd2 & RX_DMA_VTAG) { 1927 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1928 RX_DMA_VID(trxd.rxd3)); 1929 } 1930 1931 /* If the device is attached to a dsa switch, the special 1932 * tag inserted in VLAN field by hw switch can * be offloaded 1933 * by RX HW VLAN offload. Clear vlan info. 1934 */ 1935 if (netdev_uses_dsa(netdev)) 1936 __vlan_hwaccel_clear_tag(skb); 1937 } 1938 1939 skb_record_rx_queue(skb, 0); 1940 napi_gro_receive(napi, skb); 1941 1942 skip_rx: 1943 ring->data[idx] = new_data; 1944 rxd->rxd1 = (unsigned int)dma_addr; 1945 release_desc: 1946 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1947 rxd->rxd2 = RX_DMA_LSO; 1948 else 1949 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 1950 1951 ring->calc_idx = idx; 1952 done++; 1953 } 1954 1955 rx_done: 1956 if (done) { 1957 /* make sure that all changes to the dma ring are flushed before 1958 * we continue 1959 */ 1960 wmb(); 1961 mtk_update_rx_cpu_idx(eth); 1962 } 1963 1964 eth->rx_packets += done; 1965 eth->rx_bytes += bytes; 1966 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 1967 &dim_sample); 1968 net_dim(ð->rx_dim, dim_sample); 1969 1970 if (xdp_flush) 1971 xdp_do_flush_map(); 1972 1973 return done; 1974 } 1975 1976 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1977 unsigned int *done, unsigned int *bytes) 1978 { 1979 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 1980 struct mtk_tx_ring *ring = ð->tx_ring; 1981 struct mtk_tx_buf *tx_buf; 1982 struct xdp_frame_bulk bq; 1983 struct mtk_tx_dma *desc; 1984 u32 cpu, dma; 1985 1986 cpu = ring->last_free_ptr; 1987 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 1988 1989 desc = mtk_qdma_phys_to_virt(ring, cpu); 1990 xdp_frame_bulk_init(&bq); 1991 1992 while ((cpu != dma) && budget) { 1993 u32 next_cpu = desc->txd2; 1994 int mac = 0; 1995 1996 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1997 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1998 break; 1999 2000 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2001 eth->soc->txrx.txd_size); 2002 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2003 mac = 1; 2004 2005 if (!tx_buf->data) 2006 break; 2007 2008 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2009 if (tx_buf->type == MTK_TYPE_SKB) { 2010 struct sk_buff *skb = tx_buf->data; 2011 2012 bytes[mac] += skb->len; 2013 done[mac]++; 2014 } 2015 budget--; 2016 } 2017 mtk_tx_unmap(eth, tx_buf, &bq, true); 2018 2019 ring->last_free = desc; 2020 atomic_inc(&ring->free_count); 2021 2022 cpu = next_cpu; 2023 } 2024 xdp_flush_frame_bulk(&bq); 2025 2026 ring->last_free_ptr = cpu; 2027 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2028 2029 return budget; 2030 } 2031 2032 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2033 unsigned int *done, unsigned int *bytes) 2034 { 2035 struct mtk_tx_ring *ring = ð->tx_ring; 2036 struct mtk_tx_buf *tx_buf; 2037 struct xdp_frame_bulk bq; 2038 struct mtk_tx_dma *desc; 2039 u32 cpu, dma; 2040 2041 cpu = ring->cpu_idx; 2042 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2043 xdp_frame_bulk_init(&bq); 2044 2045 while ((cpu != dma) && budget) { 2046 tx_buf = &ring->buf[cpu]; 2047 if (!tx_buf->data) 2048 break; 2049 2050 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2051 if (tx_buf->type == MTK_TYPE_SKB) { 2052 struct sk_buff *skb = tx_buf->data; 2053 2054 bytes[0] += skb->len; 2055 done[0]++; 2056 } 2057 budget--; 2058 } 2059 mtk_tx_unmap(eth, tx_buf, &bq, true); 2060 2061 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2062 ring->last_free = desc; 2063 atomic_inc(&ring->free_count); 2064 2065 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2066 } 2067 xdp_flush_frame_bulk(&bq); 2068 2069 ring->cpu_idx = cpu; 2070 2071 return budget; 2072 } 2073 2074 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2075 { 2076 struct mtk_tx_ring *ring = ð->tx_ring; 2077 struct dim_sample dim_sample = {}; 2078 unsigned int done[MTK_MAX_DEVS]; 2079 unsigned int bytes[MTK_MAX_DEVS]; 2080 int total = 0, i; 2081 2082 memset(done, 0, sizeof(done)); 2083 memset(bytes, 0, sizeof(bytes)); 2084 2085 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2086 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 2087 else 2088 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 2089 2090 for (i = 0; i < MTK_MAC_COUNT; i++) { 2091 if (!eth->netdev[i] || !done[i]) 2092 continue; 2093 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 2094 total += done[i]; 2095 eth->tx_packets += done[i]; 2096 eth->tx_bytes += bytes[i]; 2097 } 2098 2099 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2100 &dim_sample); 2101 net_dim(ð->tx_dim, dim_sample); 2102 2103 if (mtk_queue_stopped(eth) && 2104 (atomic_read(&ring->free_count) > ring->thresh)) 2105 mtk_wake_queue(eth); 2106 2107 return total; 2108 } 2109 2110 static void mtk_handle_status_irq(struct mtk_eth *eth) 2111 { 2112 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2113 2114 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2115 mtk_stats_update(eth); 2116 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2117 MTK_INT_STATUS2); 2118 } 2119 } 2120 2121 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2122 { 2123 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2124 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2125 int tx_done = 0; 2126 2127 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2128 mtk_handle_status_irq(eth); 2129 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2130 tx_done = mtk_poll_tx(eth, budget); 2131 2132 if (unlikely(netif_msg_intr(eth))) { 2133 dev_info(eth->dev, 2134 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2135 mtk_r32(eth, reg_map->tx_irq_status), 2136 mtk_r32(eth, reg_map->tx_irq_mask)); 2137 } 2138 2139 if (tx_done == budget) 2140 return budget; 2141 2142 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2143 return budget; 2144 2145 if (napi_complete_done(napi, tx_done)) 2146 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2147 2148 return tx_done; 2149 } 2150 2151 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2152 { 2153 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2154 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2155 int rx_done_total = 0; 2156 2157 mtk_handle_status_irq(eth); 2158 2159 do { 2160 int rx_done; 2161 2162 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2163 reg_map->pdma.irq_status); 2164 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2165 rx_done_total += rx_done; 2166 2167 if (unlikely(netif_msg_intr(eth))) { 2168 dev_info(eth->dev, 2169 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2170 mtk_r32(eth, reg_map->pdma.irq_status), 2171 mtk_r32(eth, reg_map->pdma.irq_mask)); 2172 } 2173 2174 if (rx_done_total == budget) 2175 return budget; 2176 2177 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2178 eth->soc->txrx.rx_irq_done_mask); 2179 2180 if (napi_complete_done(napi, rx_done_total)) 2181 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2182 2183 return rx_done_total; 2184 } 2185 2186 static int mtk_tx_alloc(struct mtk_eth *eth) 2187 { 2188 const struct mtk_soc_data *soc = eth->soc; 2189 struct mtk_tx_ring *ring = ð->tx_ring; 2190 int i, sz = soc->txrx.txd_size; 2191 struct mtk_tx_dma_v2 *txd; 2192 2193 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 2194 GFP_KERNEL); 2195 if (!ring->buf) 2196 goto no_tx_mem; 2197 2198 ring->dma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 2199 &ring->phys, GFP_KERNEL); 2200 if (!ring->dma) 2201 goto no_tx_mem; 2202 2203 for (i = 0; i < MTK_DMA_SIZE; i++) { 2204 int next = (i + 1) % MTK_DMA_SIZE; 2205 u32 next_ptr = ring->phys + next * sz; 2206 2207 txd = ring->dma + i * sz; 2208 txd->txd2 = next_ptr; 2209 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2210 txd->txd4 = 0; 2211 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2212 txd->txd5 = 0; 2213 txd->txd6 = 0; 2214 txd->txd7 = 0; 2215 txd->txd8 = 0; 2216 } 2217 } 2218 2219 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2220 * only as the framework. The real HW descriptors are the PDMA 2221 * descriptors in ring->dma_pdma. 2222 */ 2223 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2224 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, MTK_DMA_SIZE * sz, 2225 &ring->phys_pdma, GFP_KERNEL); 2226 if (!ring->dma_pdma) 2227 goto no_tx_mem; 2228 2229 for (i = 0; i < MTK_DMA_SIZE; i++) { 2230 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2231 ring->dma_pdma[i].txd4 = 0; 2232 } 2233 } 2234 2235 ring->dma_size = MTK_DMA_SIZE; 2236 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 2237 ring->next_free = ring->dma; 2238 ring->last_free = (void *)txd; 2239 ring->last_free_ptr = (u32)(ring->phys + ((MTK_DMA_SIZE - 1) * sz)); 2240 ring->thresh = MAX_SKB_FRAGS; 2241 2242 /* make sure that all changes to the dma ring are flushed before we 2243 * continue 2244 */ 2245 wmb(); 2246 2247 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2248 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2249 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2250 mtk_w32(eth, 2251 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 2252 soc->reg_map->qdma.crx_ptr); 2253 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2254 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 2255 soc->reg_map->qdma.qtx_cfg); 2256 } else { 2257 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2258 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 2259 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2260 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2261 } 2262 2263 return 0; 2264 2265 no_tx_mem: 2266 return -ENOMEM; 2267 } 2268 2269 static void mtk_tx_clean(struct mtk_eth *eth) 2270 { 2271 const struct mtk_soc_data *soc = eth->soc; 2272 struct mtk_tx_ring *ring = ð->tx_ring; 2273 int i; 2274 2275 if (ring->buf) { 2276 for (i = 0; i < MTK_DMA_SIZE; i++) 2277 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2278 kfree(ring->buf); 2279 ring->buf = NULL; 2280 } 2281 2282 if (ring->dma) { 2283 dma_free_coherent(eth->dma_dev, 2284 MTK_DMA_SIZE * soc->txrx.txd_size, 2285 ring->dma, ring->phys); 2286 ring->dma = NULL; 2287 } 2288 2289 if (ring->dma_pdma) { 2290 dma_free_coherent(eth->dma_dev, 2291 MTK_DMA_SIZE * soc->txrx.txd_size, 2292 ring->dma_pdma, ring->phys_pdma); 2293 ring->dma_pdma = NULL; 2294 } 2295 } 2296 2297 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2298 { 2299 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2300 struct mtk_rx_ring *ring; 2301 int rx_data_len, rx_dma_size; 2302 int i; 2303 2304 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2305 if (ring_no) 2306 return -EINVAL; 2307 ring = ð->rx_ring_qdma; 2308 } else { 2309 ring = ð->rx_ring[ring_no]; 2310 } 2311 2312 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2313 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2314 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2315 } else { 2316 rx_data_len = ETH_DATA_LEN; 2317 rx_dma_size = MTK_DMA_SIZE; 2318 } 2319 2320 ring->frag_size = mtk_max_frag_size(rx_data_len); 2321 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2322 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2323 GFP_KERNEL); 2324 if (!ring->data) 2325 return -ENOMEM; 2326 2327 if (mtk_page_pool_enabled(eth)) { 2328 struct page_pool *pp; 2329 2330 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2331 rx_dma_size); 2332 if (IS_ERR(pp)) 2333 return PTR_ERR(pp); 2334 2335 ring->page_pool = pp; 2336 } 2337 2338 ring->dma = dma_alloc_coherent(eth->dma_dev, 2339 rx_dma_size * eth->soc->txrx.rxd_size, 2340 &ring->phys, GFP_KERNEL); 2341 if (!ring->dma) 2342 return -ENOMEM; 2343 2344 for (i = 0; i < rx_dma_size; i++) { 2345 struct mtk_rx_dma_v2 *rxd; 2346 dma_addr_t dma_addr; 2347 void *data; 2348 2349 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2350 if (ring->page_pool) { 2351 data = mtk_page_pool_get_buff(ring->page_pool, 2352 &dma_addr, GFP_KERNEL); 2353 if (!data) 2354 return -ENOMEM; 2355 } else { 2356 if (ring->frag_size <= PAGE_SIZE) 2357 data = netdev_alloc_frag(ring->frag_size); 2358 else 2359 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2360 2361 if (!data) 2362 return -ENOMEM; 2363 2364 dma_addr = dma_map_single(eth->dma_dev, 2365 data + NET_SKB_PAD + eth->ip_align, 2366 ring->buf_size, DMA_FROM_DEVICE); 2367 if (unlikely(dma_mapping_error(eth->dma_dev, 2368 dma_addr))) 2369 return -ENOMEM; 2370 } 2371 rxd->rxd1 = (unsigned int)dma_addr; 2372 ring->data[i] = data; 2373 2374 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2375 rxd->rxd2 = RX_DMA_LSO; 2376 else 2377 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2378 2379 rxd->rxd3 = 0; 2380 rxd->rxd4 = 0; 2381 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2382 rxd->rxd5 = 0; 2383 rxd->rxd6 = 0; 2384 rxd->rxd7 = 0; 2385 rxd->rxd8 = 0; 2386 } 2387 } 2388 2389 ring->dma_size = rx_dma_size; 2390 ring->calc_idx_update = false; 2391 ring->calc_idx = rx_dma_size - 1; 2392 if (rx_flag == MTK_RX_FLAGS_QDMA) 2393 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2394 ring_no * MTK_QRX_OFFSET; 2395 else 2396 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2397 ring_no * MTK_QRX_OFFSET; 2398 /* make sure that all changes to the dma ring are flushed before we 2399 * continue 2400 */ 2401 wmb(); 2402 2403 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2404 mtk_w32(eth, ring->phys, 2405 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2406 mtk_w32(eth, rx_dma_size, 2407 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2408 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2409 reg_map->qdma.rst_idx); 2410 } else { 2411 mtk_w32(eth, ring->phys, 2412 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2413 mtk_w32(eth, rx_dma_size, 2414 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2415 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2416 reg_map->pdma.rst_idx); 2417 } 2418 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2419 2420 return 0; 2421 } 2422 2423 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2424 { 2425 int i; 2426 2427 if (ring->data && ring->dma) { 2428 for (i = 0; i < ring->dma_size; i++) { 2429 struct mtk_rx_dma *rxd; 2430 2431 if (!ring->data[i]) 2432 continue; 2433 2434 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2435 if (!rxd->rxd1) 2436 continue; 2437 2438 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2439 ring->buf_size, DMA_FROM_DEVICE); 2440 mtk_rx_put_buff(ring, ring->data[i], false); 2441 } 2442 kfree(ring->data); 2443 ring->data = NULL; 2444 } 2445 2446 if (ring->dma) { 2447 dma_free_coherent(eth->dma_dev, 2448 ring->dma_size * eth->soc->txrx.rxd_size, 2449 ring->dma, ring->phys); 2450 ring->dma = NULL; 2451 } 2452 2453 if (ring->page_pool) { 2454 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2455 xdp_rxq_info_unreg(&ring->xdp_q); 2456 page_pool_destroy(ring->page_pool); 2457 ring->page_pool = NULL; 2458 } 2459 } 2460 2461 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2462 { 2463 int i; 2464 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2465 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2466 2467 /* set LRO rings to auto-learn modes */ 2468 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2469 2470 /* validate LRO ring */ 2471 ring_ctrl_dw2 |= MTK_RING_VLD; 2472 2473 /* set AGE timer (unit: 20us) */ 2474 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2475 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2476 2477 /* set max AGG timer (unit: 20us) */ 2478 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2479 2480 /* set max LRO AGG count */ 2481 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2482 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2483 2484 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2485 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2486 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2487 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2488 } 2489 2490 /* IPv4 checksum update enable */ 2491 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2492 2493 /* switch priority comparison to packet count mode */ 2494 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2495 2496 /* bandwidth threshold setting */ 2497 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2498 2499 /* auto-learn score delta setting */ 2500 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2501 2502 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2503 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2504 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2505 2506 /* set HW LRO mode & the max aggregation count for rx packets */ 2507 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2508 2509 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2510 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2511 2512 /* enable HW LRO */ 2513 lro_ctrl_dw0 |= MTK_LRO_EN; 2514 2515 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2516 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2517 2518 return 0; 2519 } 2520 2521 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2522 { 2523 int i; 2524 u32 val; 2525 2526 /* relinquish lro rings, flush aggregated packets */ 2527 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2528 2529 /* wait for relinquishments done */ 2530 for (i = 0; i < 10; i++) { 2531 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2532 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2533 msleep(20); 2534 continue; 2535 } 2536 break; 2537 } 2538 2539 /* invalidate lro rings */ 2540 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2541 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2542 2543 /* disable HW LRO */ 2544 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2545 } 2546 2547 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2548 { 2549 u32 reg_val; 2550 2551 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2552 2553 /* invalidate the IP setting */ 2554 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2555 2556 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2557 2558 /* validate the IP setting */ 2559 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2560 } 2561 2562 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2563 { 2564 u32 reg_val; 2565 2566 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2567 2568 /* invalidate the IP setting */ 2569 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2570 2571 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2572 } 2573 2574 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2575 { 2576 int cnt = 0; 2577 int i; 2578 2579 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2580 if (mac->hwlro_ip[i]) 2581 cnt++; 2582 } 2583 2584 return cnt; 2585 } 2586 2587 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2588 struct ethtool_rxnfc *cmd) 2589 { 2590 struct ethtool_rx_flow_spec *fsp = 2591 (struct ethtool_rx_flow_spec *)&cmd->fs; 2592 struct mtk_mac *mac = netdev_priv(dev); 2593 struct mtk_eth *eth = mac->hw; 2594 int hwlro_idx; 2595 2596 if ((fsp->flow_type != TCP_V4_FLOW) || 2597 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2598 (fsp->location > 1)) 2599 return -EINVAL; 2600 2601 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2602 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2603 2604 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2605 2606 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2607 2608 return 0; 2609 } 2610 2611 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2612 struct ethtool_rxnfc *cmd) 2613 { 2614 struct ethtool_rx_flow_spec *fsp = 2615 (struct ethtool_rx_flow_spec *)&cmd->fs; 2616 struct mtk_mac *mac = netdev_priv(dev); 2617 struct mtk_eth *eth = mac->hw; 2618 int hwlro_idx; 2619 2620 if (fsp->location > 1) 2621 return -EINVAL; 2622 2623 mac->hwlro_ip[fsp->location] = 0; 2624 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2625 2626 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2627 2628 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2629 2630 return 0; 2631 } 2632 2633 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2634 { 2635 struct mtk_mac *mac = netdev_priv(dev); 2636 struct mtk_eth *eth = mac->hw; 2637 int i, hwlro_idx; 2638 2639 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2640 mac->hwlro_ip[i] = 0; 2641 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2642 2643 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2644 } 2645 2646 mac->hwlro_ip_cnt = 0; 2647 } 2648 2649 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2650 struct ethtool_rxnfc *cmd) 2651 { 2652 struct mtk_mac *mac = netdev_priv(dev); 2653 struct ethtool_rx_flow_spec *fsp = 2654 (struct ethtool_rx_flow_spec *)&cmd->fs; 2655 2656 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2657 return -EINVAL; 2658 2659 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2660 fsp->flow_type = TCP_V4_FLOW; 2661 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2662 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2663 2664 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2665 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2666 fsp->h_u.tcp_ip4_spec.psrc = 0; 2667 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2668 fsp->h_u.tcp_ip4_spec.pdst = 0; 2669 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2670 fsp->h_u.tcp_ip4_spec.tos = 0; 2671 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2672 2673 return 0; 2674 } 2675 2676 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2677 struct ethtool_rxnfc *cmd, 2678 u32 *rule_locs) 2679 { 2680 struct mtk_mac *mac = netdev_priv(dev); 2681 int cnt = 0; 2682 int i; 2683 2684 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2685 if (mac->hwlro_ip[i]) { 2686 rule_locs[cnt] = i; 2687 cnt++; 2688 } 2689 } 2690 2691 cmd->rule_cnt = cnt; 2692 2693 return 0; 2694 } 2695 2696 static netdev_features_t mtk_fix_features(struct net_device *dev, 2697 netdev_features_t features) 2698 { 2699 if (!(features & NETIF_F_LRO)) { 2700 struct mtk_mac *mac = netdev_priv(dev); 2701 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2702 2703 if (ip_cnt) { 2704 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2705 2706 features |= NETIF_F_LRO; 2707 } 2708 } 2709 2710 return features; 2711 } 2712 2713 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2714 { 2715 int err = 0; 2716 2717 if (!((dev->features ^ features) & NETIF_F_LRO)) 2718 return 0; 2719 2720 if (!(features & NETIF_F_LRO)) 2721 mtk_hwlro_netdev_disable(dev); 2722 2723 return err; 2724 } 2725 2726 /* wait for DMA to finish whatever it is doing before we start using it again */ 2727 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2728 { 2729 unsigned int reg; 2730 int ret; 2731 u32 val; 2732 2733 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2734 reg = eth->soc->reg_map->qdma.glo_cfg; 2735 else 2736 reg = eth->soc->reg_map->pdma.glo_cfg; 2737 2738 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2739 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2740 5, MTK_DMA_BUSY_TIMEOUT_US); 2741 if (ret) 2742 dev_err(eth->dev, "DMA init timeout\n"); 2743 2744 return ret; 2745 } 2746 2747 static int mtk_dma_init(struct mtk_eth *eth) 2748 { 2749 int err; 2750 u32 i; 2751 2752 if (mtk_dma_busy_wait(eth)) 2753 return -EBUSY; 2754 2755 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2756 /* QDMA needs scratch memory for internal reordering of the 2757 * descriptors 2758 */ 2759 err = mtk_init_fq_dma(eth); 2760 if (err) 2761 return err; 2762 } 2763 2764 err = mtk_tx_alloc(eth); 2765 if (err) 2766 return err; 2767 2768 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2769 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2770 if (err) 2771 return err; 2772 } 2773 2774 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2775 if (err) 2776 return err; 2777 2778 if (eth->hwlro) { 2779 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2780 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2781 if (err) 2782 return err; 2783 } 2784 err = mtk_hwlro_rx_init(eth); 2785 if (err) 2786 return err; 2787 } 2788 2789 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2790 /* Enable random early drop and set drop threshold 2791 * automatically 2792 */ 2793 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2794 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2795 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2796 } 2797 2798 return 0; 2799 } 2800 2801 static void mtk_dma_free(struct mtk_eth *eth) 2802 { 2803 const struct mtk_soc_data *soc = eth->soc; 2804 int i; 2805 2806 for (i = 0; i < MTK_MAC_COUNT; i++) 2807 if (eth->netdev[i]) 2808 netdev_reset_queue(eth->netdev[i]); 2809 if (eth->scratch_ring) { 2810 dma_free_coherent(eth->dma_dev, 2811 MTK_DMA_SIZE * soc->txrx.txd_size, 2812 eth->scratch_ring, eth->phy_scratch_ring); 2813 eth->scratch_ring = NULL; 2814 eth->phy_scratch_ring = 0; 2815 } 2816 mtk_tx_clean(eth); 2817 mtk_rx_clean(eth, ð->rx_ring[0]); 2818 mtk_rx_clean(eth, ð->rx_ring_qdma); 2819 2820 if (eth->hwlro) { 2821 mtk_hwlro_rx_uninit(eth); 2822 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2823 mtk_rx_clean(eth, ð->rx_ring[i]); 2824 } 2825 2826 kfree(eth->scratch_head); 2827 } 2828 2829 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 2830 { 2831 struct mtk_mac *mac = netdev_priv(dev); 2832 struct mtk_eth *eth = mac->hw; 2833 2834 eth->netdev[mac->id]->stats.tx_errors++; 2835 netif_err(eth, tx_err, dev, 2836 "transmit timed out\n"); 2837 schedule_work(ð->pending_work); 2838 } 2839 2840 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2841 { 2842 struct mtk_eth *eth = _eth; 2843 2844 eth->rx_events++; 2845 if (likely(napi_schedule_prep(ð->rx_napi))) { 2846 __napi_schedule(ð->rx_napi); 2847 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2848 } 2849 2850 return IRQ_HANDLED; 2851 } 2852 2853 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2854 { 2855 struct mtk_eth *eth = _eth; 2856 2857 eth->tx_events++; 2858 if (likely(napi_schedule_prep(ð->tx_napi))) { 2859 __napi_schedule(ð->tx_napi); 2860 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2861 } 2862 2863 return IRQ_HANDLED; 2864 } 2865 2866 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2867 { 2868 struct mtk_eth *eth = _eth; 2869 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2870 2871 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 2872 eth->soc->txrx.rx_irq_done_mask) { 2873 if (mtk_r32(eth, reg_map->pdma.irq_status) & 2874 eth->soc->txrx.rx_irq_done_mask) 2875 mtk_handle_irq_rx(irq, _eth); 2876 } 2877 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 2878 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2879 mtk_handle_irq_tx(irq, _eth); 2880 } 2881 2882 return IRQ_HANDLED; 2883 } 2884 2885 #ifdef CONFIG_NET_POLL_CONTROLLER 2886 static void mtk_poll_controller(struct net_device *dev) 2887 { 2888 struct mtk_mac *mac = netdev_priv(dev); 2889 struct mtk_eth *eth = mac->hw; 2890 2891 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2892 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 2893 mtk_handle_irq_rx(eth->irq[2], dev); 2894 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2895 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2896 } 2897 #endif 2898 2899 static int mtk_start_dma(struct mtk_eth *eth) 2900 { 2901 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2902 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2903 int err; 2904 2905 err = mtk_dma_init(eth); 2906 if (err) { 2907 mtk_dma_free(eth); 2908 return err; 2909 } 2910 2911 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2912 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 2913 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2914 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 2915 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 2916 2917 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2918 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 2919 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 2920 MTK_CHK_DDONE_EN; 2921 else 2922 val |= MTK_RX_BT_32DWORDS; 2923 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 2924 2925 mtk_w32(eth, 2926 MTK_RX_DMA_EN | rx_2b_offset | 2927 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2928 reg_map->pdma.glo_cfg); 2929 } else { 2930 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2931 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2932 reg_map->pdma.glo_cfg); 2933 } 2934 2935 return 0; 2936 } 2937 2938 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 2939 { 2940 int i; 2941 2942 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2943 return; 2944 2945 for (i = 0; i < MTK_MAC_COUNT; i++) { 2946 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2947 2948 /* default setup the forward port to send frame to PDMA */ 2949 val &= ~0xffff; 2950 2951 /* Enable RX checksum */ 2952 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2953 2954 val |= config; 2955 2956 if (!i && eth->netdev[0] && netdev_uses_dsa(eth->netdev[0])) 2957 val |= MTK_GDMA_SPECIAL_TAG; 2958 2959 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2960 } 2961 /* Reset and enable PSE */ 2962 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2963 mtk_w32(eth, 0, MTK_RST_GL); 2964 } 2965 2966 static int mtk_open(struct net_device *dev) 2967 { 2968 struct mtk_mac *mac = netdev_priv(dev); 2969 struct mtk_eth *eth = mac->hw; 2970 int err; 2971 2972 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2973 if (err) { 2974 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2975 err); 2976 return err; 2977 } 2978 2979 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2980 if (!refcount_read(ð->dma_refcnt)) { 2981 u32 gdm_config = MTK_GDMA_TO_PDMA; 2982 2983 err = mtk_start_dma(eth); 2984 if (err) 2985 return err; 2986 2987 if (eth->soc->offload_version && mtk_ppe_start(eth->ppe) == 0) 2988 gdm_config = MTK_GDMA_TO_PPE; 2989 2990 mtk_gdm_config(eth, gdm_config); 2991 2992 napi_enable(ð->tx_napi); 2993 napi_enable(ð->rx_napi); 2994 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2995 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2996 refcount_set(ð->dma_refcnt, 1); 2997 } 2998 else 2999 refcount_inc(ð->dma_refcnt); 3000 3001 phylink_start(mac->phylink); 3002 netif_start_queue(dev); 3003 return 0; 3004 } 3005 3006 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3007 { 3008 u32 val; 3009 int i; 3010 3011 /* stop the dma engine */ 3012 spin_lock_bh(ð->page_lock); 3013 val = mtk_r32(eth, glo_cfg); 3014 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3015 glo_cfg); 3016 spin_unlock_bh(ð->page_lock); 3017 3018 /* wait for dma stop */ 3019 for (i = 0; i < 10; i++) { 3020 val = mtk_r32(eth, glo_cfg); 3021 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3022 msleep(20); 3023 continue; 3024 } 3025 break; 3026 } 3027 } 3028 3029 static int mtk_stop(struct net_device *dev) 3030 { 3031 struct mtk_mac *mac = netdev_priv(dev); 3032 struct mtk_eth *eth = mac->hw; 3033 3034 phylink_stop(mac->phylink); 3035 3036 netif_tx_disable(dev); 3037 3038 phylink_disconnect_phy(mac->phylink); 3039 3040 /* only shutdown DMA if this is the last user */ 3041 if (!refcount_dec_and_test(ð->dma_refcnt)) 3042 return 0; 3043 3044 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3045 3046 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3047 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3048 napi_disable(ð->tx_napi); 3049 napi_disable(ð->rx_napi); 3050 3051 cancel_work_sync(ð->rx_dim.work); 3052 cancel_work_sync(ð->tx_dim.work); 3053 3054 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3055 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3056 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3057 3058 mtk_dma_free(eth); 3059 3060 if (eth->soc->offload_version) 3061 mtk_ppe_stop(eth->ppe); 3062 3063 return 0; 3064 } 3065 3066 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3067 struct netlink_ext_ack *extack) 3068 { 3069 struct mtk_mac *mac = netdev_priv(dev); 3070 struct mtk_eth *eth = mac->hw; 3071 struct bpf_prog *old_prog; 3072 bool need_update; 3073 3074 if (eth->hwlro) { 3075 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3076 return -EOPNOTSUPP; 3077 } 3078 3079 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3080 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3081 return -EOPNOTSUPP; 3082 } 3083 3084 need_update = !!eth->prog != !!prog; 3085 if (netif_running(dev) && need_update) 3086 mtk_stop(dev); 3087 3088 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3089 if (old_prog) 3090 bpf_prog_put(old_prog); 3091 3092 if (netif_running(dev) && need_update) 3093 return mtk_open(dev); 3094 3095 return 0; 3096 } 3097 3098 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3099 { 3100 switch (xdp->command) { 3101 case XDP_SETUP_PROG: 3102 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3103 default: 3104 return -EINVAL; 3105 } 3106 } 3107 3108 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3109 { 3110 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3111 reset_bits, 3112 reset_bits); 3113 3114 usleep_range(1000, 1100); 3115 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3116 reset_bits, 3117 ~reset_bits); 3118 mdelay(10); 3119 } 3120 3121 static void mtk_clk_disable(struct mtk_eth *eth) 3122 { 3123 int clk; 3124 3125 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3126 clk_disable_unprepare(eth->clks[clk]); 3127 } 3128 3129 static int mtk_clk_enable(struct mtk_eth *eth) 3130 { 3131 int clk, ret; 3132 3133 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3134 ret = clk_prepare_enable(eth->clks[clk]); 3135 if (ret) 3136 goto err_disable_clks; 3137 } 3138 3139 return 0; 3140 3141 err_disable_clks: 3142 while (--clk >= 0) 3143 clk_disable_unprepare(eth->clks[clk]); 3144 3145 return ret; 3146 } 3147 3148 static void mtk_dim_rx(struct work_struct *work) 3149 { 3150 struct dim *dim = container_of(work, struct dim, work); 3151 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3152 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3153 struct dim_cq_moder cur_profile; 3154 u32 val, cur; 3155 3156 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3157 dim->profile_ix); 3158 spin_lock_bh(ð->dim_lock); 3159 3160 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3161 val &= MTK_PDMA_DELAY_TX_MASK; 3162 val |= MTK_PDMA_DELAY_RX_EN; 3163 3164 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3165 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3166 3167 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3168 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3169 3170 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3171 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3172 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3173 3174 spin_unlock_bh(ð->dim_lock); 3175 3176 dim->state = DIM_START_MEASURE; 3177 } 3178 3179 static void mtk_dim_tx(struct work_struct *work) 3180 { 3181 struct dim *dim = container_of(work, struct dim, work); 3182 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3183 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3184 struct dim_cq_moder cur_profile; 3185 u32 val, cur; 3186 3187 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3188 dim->profile_ix); 3189 spin_lock_bh(ð->dim_lock); 3190 3191 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3192 val &= MTK_PDMA_DELAY_RX_MASK; 3193 val |= MTK_PDMA_DELAY_TX_EN; 3194 3195 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3196 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3197 3198 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3199 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3200 3201 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3203 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3204 3205 spin_unlock_bh(ð->dim_lock); 3206 3207 dim->state = DIM_START_MEASURE; 3208 } 3209 3210 static int mtk_hw_init(struct mtk_eth *eth) 3211 { 3212 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3213 ETHSYS_DMA_AG_MAP_PPE; 3214 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3215 int i, val, ret; 3216 3217 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 3218 return 0; 3219 3220 pm_runtime_enable(eth->dev); 3221 pm_runtime_get_sync(eth->dev); 3222 3223 ret = mtk_clk_enable(eth); 3224 if (ret) 3225 goto err_disable_pm; 3226 3227 if (eth->ethsys) 3228 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3229 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3230 3231 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3232 ret = device_reset(eth->dev); 3233 if (ret) { 3234 dev_err(eth->dev, "MAC reset failed!\n"); 3235 goto err_disable_pm; 3236 } 3237 3238 /* set interrupt delays based on current Net DIM sample */ 3239 mtk_dim_rx(ð->rx_dim.work); 3240 mtk_dim_tx(ð->tx_dim.work); 3241 3242 /* disable delay and normal interrupt */ 3243 mtk_tx_irq_disable(eth, ~0); 3244 mtk_rx_irq_disable(eth, ~0); 3245 3246 return 0; 3247 } 3248 3249 val = RSTCTRL_FE | RSTCTRL_PPE; 3250 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3251 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3252 3253 val |= RSTCTRL_ETH; 3254 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3255 val |= RSTCTRL_PPE1; 3256 } 3257 3258 ethsys_reset(eth, val); 3259 3260 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3261 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3262 0x3ffffff); 3263 3264 /* Set FE to PDMAv2 if necessary */ 3265 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3266 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3267 } 3268 3269 if (eth->pctl) { 3270 /* Set GE2 driving and slew rate */ 3271 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3272 3273 /* set GE2 TDSEL */ 3274 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3275 3276 /* set GE2 TUNE */ 3277 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3278 } 3279 3280 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3281 * up with the more appropriate value when mtk_mac_config call is being 3282 * invoked. 3283 */ 3284 for (i = 0; i < MTK_MAC_COUNT; i++) 3285 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3286 3287 /* Indicates CDM to parse the MTK special tag from CPU 3288 * which also is working out for untag packets. 3289 */ 3290 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3291 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3292 3293 /* Enable RX VLan Offloading */ 3294 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3295 3296 /* set interrupt delays based on current Net DIM sample */ 3297 mtk_dim_rx(ð->rx_dim.work); 3298 mtk_dim_tx(ð->tx_dim.work); 3299 3300 /* disable delay and normal interrupt */ 3301 mtk_tx_irq_disable(eth, ~0); 3302 mtk_rx_irq_disable(eth, ~0); 3303 3304 /* FE int grouping */ 3305 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3306 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3307 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3308 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3309 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3310 3311 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3312 /* PSE should not drop port8 and port9 packets */ 3313 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3314 3315 /* PSE Free Queue Flow Control */ 3316 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3317 3318 /* PSE config input queue threshold */ 3319 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3320 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3321 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3322 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3323 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3324 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3325 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3326 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3327 3328 /* PSE config output queue threshold */ 3329 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3330 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3331 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3332 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3333 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3334 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3335 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3336 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3337 3338 /* GDM and CDM Threshold */ 3339 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3340 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3341 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3342 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3343 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3344 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3345 } 3346 3347 return 0; 3348 3349 err_disable_pm: 3350 pm_runtime_put_sync(eth->dev); 3351 pm_runtime_disable(eth->dev); 3352 3353 return ret; 3354 } 3355 3356 static int mtk_hw_deinit(struct mtk_eth *eth) 3357 { 3358 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3359 return 0; 3360 3361 mtk_clk_disable(eth); 3362 3363 pm_runtime_put_sync(eth->dev); 3364 pm_runtime_disable(eth->dev); 3365 3366 return 0; 3367 } 3368 3369 static int __init mtk_init(struct net_device *dev) 3370 { 3371 struct mtk_mac *mac = netdev_priv(dev); 3372 struct mtk_eth *eth = mac->hw; 3373 int ret; 3374 3375 ret = of_get_ethdev_address(mac->of_node, dev); 3376 if (ret) { 3377 /* If the mac address is invalid, use random mac address */ 3378 eth_hw_addr_random(dev); 3379 dev_err(eth->dev, "generated random MAC address %pM\n", 3380 dev->dev_addr); 3381 } 3382 3383 return 0; 3384 } 3385 3386 static void mtk_uninit(struct net_device *dev) 3387 { 3388 struct mtk_mac *mac = netdev_priv(dev); 3389 struct mtk_eth *eth = mac->hw; 3390 3391 phylink_disconnect_phy(mac->phylink); 3392 mtk_tx_irq_disable(eth, ~0); 3393 mtk_rx_irq_disable(eth, ~0); 3394 } 3395 3396 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3397 { 3398 int length = new_mtu + MTK_RX_ETH_HLEN; 3399 struct mtk_mac *mac = netdev_priv(dev); 3400 struct mtk_eth *eth = mac->hw; 3401 u32 mcr_cur, mcr_new; 3402 3403 if (rcu_access_pointer(eth->prog) && 3404 length > MTK_PP_MAX_BUF_SIZE) { 3405 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3406 return -EINVAL; 3407 } 3408 3409 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3410 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3411 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3412 3413 if (length <= 1518) 3414 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3415 else if (length <= 1536) 3416 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3417 else if (length <= 1552) 3418 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3419 else 3420 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3421 3422 if (mcr_new != mcr_cur) 3423 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3424 } 3425 3426 dev->mtu = new_mtu; 3427 3428 return 0; 3429 } 3430 3431 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3432 { 3433 struct mtk_mac *mac = netdev_priv(dev); 3434 3435 switch (cmd) { 3436 case SIOCGMIIPHY: 3437 case SIOCGMIIREG: 3438 case SIOCSMIIREG: 3439 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3440 default: 3441 break; 3442 } 3443 3444 return -EOPNOTSUPP; 3445 } 3446 3447 static void mtk_pending_work(struct work_struct *work) 3448 { 3449 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3450 int err, i; 3451 unsigned long restart = 0; 3452 3453 rtnl_lock(); 3454 3455 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 3456 3457 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 3458 cpu_relax(); 3459 3460 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 3461 /* stop all devices to make sure that dma is properly shut down */ 3462 for (i = 0; i < MTK_MAC_COUNT; i++) { 3463 if (!eth->netdev[i]) 3464 continue; 3465 mtk_stop(eth->netdev[i]); 3466 __set_bit(i, &restart); 3467 } 3468 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 3469 3470 /* restart underlying hardware such as power, clock, pin mux 3471 * and the connected phy 3472 */ 3473 mtk_hw_deinit(eth); 3474 3475 if (eth->dev->pins) 3476 pinctrl_select_state(eth->dev->pins->p, 3477 eth->dev->pins->default_state); 3478 mtk_hw_init(eth); 3479 3480 /* restart DMA and enable IRQs */ 3481 for (i = 0; i < MTK_MAC_COUNT; i++) { 3482 if (!test_bit(i, &restart)) 3483 continue; 3484 err = mtk_open(eth->netdev[i]); 3485 if (err) { 3486 netif_alert(eth, ifup, eth->netdev[i], 3487 "Driver up/down cycle failed, closing device.\n"); 3488 dev_close(eth->netdev[i]); 3489 } 3490 } 3491 3492 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 3493 3494 clear_bit_unlock(MTK_RESETTING, ð->state); 3495 3496 rtnl_unlock(); 3497 } 3498 3499 static int mtk_free_dev(struct mtk_eth *eth) 3500 { 3501 int i; 3502 3503 for (i = 0; i < MTK_MAC_COUNT; i++) { 3504 if (!eth->netdev[i]) 3505 continue; 3506 free_netdev(eth->netdev[i]); 3507 } 3508 3509 return 0; 3510 } 3511 3512 static int mtk_unreg_dev(struct mtk_eth *eth) 3513 { 3514 int i; 3515 3516 for (i = 0; i < MTK_MAC_COUNT; i++) { 3517 if (!eth->netdev[i]) 3518 continue; 3519 unregister_netdev(eth->netdev[i]); 3520 } 3521 3522 return 0; 3523 } 3524 3525 static int mtk_cleanup(struct mtk_eth *eth) 3526 { 3527 mtk_unreg_dev(eth); 3528 mtk_free_dev(eth); 3529 cancel_work_sync(ð->pending_work); 3530 3531 return 0; 3532 } 3533 3534 static int mtk_get_link_ksettings(struct net_device *ndev, 3535 struct ethtool_link_ksettings *cmd) 3536 { 3537 struct mtk_mac *mac = netdev_priv(ndev); 3538 3539 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3540 return -EBUSY; 3541 3542 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 3543 } 3544 3545 static int mtk_set_link_ksettings(struct net_device *ndev, 3546 const struct ethtool_link_ksettings *cmd) 3547 { 3548 struct mtk_mac *mac = netdev_priv(ndev); 3549 3550 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3551 return -EBUSY; 3552 3553 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 3554 } 3555 3556 static void mtk_get_drvinfo(struct net_device *dev, 3557 struct ethtool_drvinfo *info) 3558 { 3559 struct mtk_mac *mac = netdev_priv(dev); 3560 3561 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 3562 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 3563 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 3564 } 3565 3566 static u32 mtk_get_msglevel(struct net_device *dev) 3567 { 3568 struct mtk_mac *mac = netdev_priv(dev); 3569 3570 return mac->hw->msg_enable; 3571 } 3572 3573 static void mtk_set_msglevel(struct net_device *dev, u32 value) 3574 { 3575 struct mtk_mac *mac = netdev_priv(dev); 3576 3577 mac->hw->msg_enable = value; 3578 } 3579 3580 static int mtk_nway_reset(struct net_device *dev) 3581 { 3582 struct mtk_mac *mac = netdev_priv(dev); 3583 3584 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3585 return -EBUSY; 3586 3587 if (!mac->phylink) 3588 return -ENOTSUPP; 3589 3590 return phylink_ethtool_nway_reset(mac->phylink); 3591 } 3592 3593 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 3594 { 3595 int i; 3596 3597 switch (stringset) { 3598 case ETH_SS_STATS: { 3599 struct mtk_mac *mac = netdev_priv(dev); 3600 3601 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 3602 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 3603 data += ETH_GSTRING_LEN; 3604 } 3605 if (mtk_page_pool_enabled(mac->hw)) 3606 page_pool_ethtool_stats_get_strings(data); 3607 break; 3608 } 3609 default: 3610 break; 3611 } 3612 } 3613 3614 static int mtk_get_sset_count(struct net_device *dev, int sset) 3615 { 3616 switch (sset) { 3617 case ETH_SS_STATS: { 3618 int count = ARRAY_SIZE(mtk_ethtool_stats); 3619 struct mtk_mac *mac = netdev_priv(dev); 3620 3621 if (mtk_page_pool_enabled(mac->hw)) 3622 count += page_pool_ethtool_stats_get_count(); 3623 return count; 3624 } 3625 default: 3626 return -EOPNOTSUPP; 3627 } 3628 } 3629 3630 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 3631 { 3632 struct page_pool_stats stats = {}; 3633 int i; 3634 3635 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 3636 struct mtk_rx_ring *ring = ð->rx_ring[i]; 3637 3638 if (!ring->page_pool) 3639 continue; 3640 3641 page_pool_get_stats(ring->page_pool, &stats); 3642 } 3643 page_pool_ethtool_stats_get(data, &stats); 3644 } 3645 3646 static void mtk_get_ethtool_stats(struct net_device *dev, 3647 struct ethtool_stats *stats, u64 *data) 3648 { 3649 struct mtk_mac *mac = netdev_priv(dev); 3650 struct mtk_hw_stats *hwstats = mac->hw_stats; 3651 u64 *data_src, *data_dst; 3652 unsigned int start; 3653 int i; 3654 3655 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 3656 return; 3657 3658 if (netif_running(dev) && netif_device_present(dev)) { 3659 if (spin_trylock_bh(&hwstats->stats_lock)) { 3660 mtk_stats_update_mac(mac); 3661 spin_unlock_bh(&hwstats->stats_lock); 3662 } 3663 } 3664 3665 data_src = (u64 *)hwstats; 3666 3667 do { 3668 data_dst = data; 3669 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 3670 3671 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 3672 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 3673 if (mtk_page_pool_enabled(mac->hw)) 3674 mtk_ethtool_pp_stats(mac->hw, data_dst); 3675 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 3676 } 3677 3678 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 3679 u32 *rule_locs) 3680 { 3681 int ret = -EOPNOTSUPP; 3682 3683 switch (cmd->cmd) { 3684 case ETHTOOL_GRXRINGS: 3685 if (dev->hw_features & NETIF_F_LRO) { 3686 cmd->data = MTK_MAX_RX_RING_NUM; 3687 ret = 0; 3688 } 3689 break; 3690 case ETHTOOL_GRXCLSRLCNT: 3691 if (dev->hw_features & NETIF_F_LRO) { 3692 struct mtk_mac *mac = netdev_priv(dev); 3693 3694 cmd->rule_cnt = mac->hwlro_ip_cnt; 3695 ret = 0; 3696 } 3697 break; 3698 case ETHTOOL_GRXCLSRULE: 3699 if (dev->hw_features & NETIF_F_LRO) 3700 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 3701 break; 3702 case ETHTOOL_GRXCLSRLALL: 3703 if (dev->hw_features & NETIF_F_LRO) 3704 ret = mtk_hwlro_get_fdir_all(dev, cmd, 3705 rule_locs); 3706 break; 3707 default: 3708 break; 3709 } 3710 3711 return ret; 3712 } 3713 3714 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 3715 { 3716 int ret = -EOPNOTSUPP; 3717 3718 switch (cmd->cmd) { 3719 case ETHTOOL_SRXCLSRLINS: 3720 if (dev->hw_features & NETIF_F_LRO) 3721 ret = mtk_hwlro_add_ipaddr(dev, cmd); 3722 break; 3723 case ETHTOOL_SRXCLSRLDEL: 3724 if (dev->hw_features & NETIF_F_LRO) 3725 ret = mtk_hwlro_del_ipaddr(dev, cmd); 3726 break; 3727 default: 3728 break; 3729 } 3730 3731 return ret; 3732 } 3733 3734 static const struct ethtool_ops mtk_ethtool_ops = { 3735 .get_link_ksettings = mtk_get_link_ksettings, 3736 .set_link_ksettings = mtk_set_link_ksettings, 3737 .get_drvinfo = mtk_get_drvinfo, 3738 .get_msglevel = mtk_get_msglevel, 3739 .set_msglevel = mtk_set_msglevel, 3740 .nway_reset = mtk_nway_reset, 3741 .get_link = ethtool_op_get_link, 3742 .get_strings = mtk_get_strings, 3743 .get_sset_count = mtk_get_sset_count, 3744 .get_ethtool_stats = mtk_get_ethtool_stats, 3745 .get_rxnfc = mtk_get_rxnfc, 3746 .set_rxnfc = mtk_set_rxnfc, 3747 }; 3748 3749 static const struct net_device_ops mtk_netdev_ops = { 3750 .ndo_init = mtk_init, 3751 .ndo_uninit = mtk_uninit, 3752 .ndo_open = mtk_open, 3753 .ndo_stop = mtk_stop, 3754 .ndo_start_xmit = mtk_start_xmit, 3755 .ndo_set_mac_address = mtk_set_mac_address, 3756 .ndo_validate_addr = eth_validate_addr, 3757 .ndo_eth_ioctl = mtk_do_ioctl, 3758 .ndo_change_mtu = mtk_change_mtu, 3759 .ndo_tx_timeout = mtk_tx_timeout, 3760 .ndo_get_stats64 = mtk_get_stats64, 3761 .ndo_fix_features = mtk_fix_features, 3762 .ndo_set_features = mtk_set_features, 3763 #ifdef CONFIG_NET_POLL_CONTROLLER 3764 .ndo_poll_controller = mtk_poll_controller, 3765 #endif 3766 .ndo_setup_tc = mtk_eth_setup_tc, 3767 .ndo_bpf = mtk_xdp, 3768 .ndo_xdp_xmit = mtk_xdp_xmit, 3769 }; 3770 3771 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 3772 { 3773 const __be32 *_id = of_get_property(np, "reg", NULL); 3774 phy_interface_t phy_mode; 3775 struct phylink *phylink; 3776 struct mtk_mac *mac; 3777 int id, err; 3778 3779 if (!_id) { 3780 dev_err(eth->dev, "missing mac id\n"); 3781 return -EINVAL; 3782 } 3783 3784 id = be32_to_cpup(_id); 3785 if (id >= MTK_MAC_COUNT) { 3786 dev_err(eth->dev, "%d is not a valid mac id\n", id); 3787 return -EINVAL; 3788 } 3789 3790 if (eth->netdev[id]) { 3791 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 3792 return -EINVAL; 3793 } 3794 3795 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 3796 if (!eth->netdev[id]) { 3797 dev_err(eth->dev, "alloc_etherdev failed\n"); 3798 return -ENOMEM; 3799 } 3800 mac = netdev_priv(eth->netdev[id]); 3801 eth->mac[id] = mac; 3802 mac->id = id; 3803 mac->hw = eth; 3804 mac->of_node = np; 3805 3806 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 3807 mac->hwlro_ip_cnt = 0; 3808 3809 mac->hw_stats = devm_kzalloc(eth->dev, 3810 sizeof(*mac->hw_stats), 3811 GFP_KERNEL); 3812 if (!mac->hw_stats) { 3813 dev_err(eth->dev, "failed to allocate counter memory\n"); 3814 err = -ENOMEM; 3815 goto free_netdev; 3816 } 3817 spin_lock_init(&mac->hw_stats->stats_lock); 3818 u64_stats_init(&mac->hw_stats->syncp); 3819 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 3820 3821 /* phylink create */ 3822 err = of_get_phy_mode(np, &phy_mode); 3823 if (err) { 3824 dev_err(eth->dev, "incorrect phy-mode\n"); 3825 goto free_netdev; 3826 } 3827 3828 /* mac config is not set */ 3829 mac->interface = PHY_INTERFACE_MODE_NA; 3830 mac->speed = SPEED_UNKNOWN; 3831 3832 mac->phylink_config.dev = ð->netdev[id]->dev; 3833 mac->phylink_config.type = PHYLINK_NETDEV; 3834 /* This driver makes use of state->speed in mac_config */ 3835 mac->phylink_config.legacy_pre_march2020 = true; 3836 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 3837 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 3838 3839 __set_bit(PHY_INTERFACE_MODE_MII, 3840 mac->phylink_config.supported_interfaces); 3841 __set_bit(PHY_INTERFACE_MODE_GMII, 3842 mac->phylink_config.supported_interfaces); 3843 3844 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 3845 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 3846 3847 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 3848 __set_bit(PHY_INTERFACE_MODE_TRGMII, 3849 mac->phylink_config.supported_interfaces); 3850 3851 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 3852 __set_bit(PHY_INTERFACE_MODE_SGMII, 3853 mac->phylink_config.supported_interfaces); 3854 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 3855 mac->phylink_config.supported_interfaces); 3856 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 3857 mac->phylink_config.supported_interfaces); 3858 } 3859 3860 phylink = phylink_create(&mac->phylink_config, 3861 of_fwnode_handle(mac->of_node), 3862 phy_mode, &mtk_phylink_ops); 3863 if (IS_ERR(phylink)) { 3864 err = PTR_ERR(phylink); 3865 goto free_netdev; 3866 } 3867 3868 mac->phylink = phylink; 3869 3870 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 3871 eth->netdev[id]->watchdog_timeo = 5 * HZ; 3872 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 3873 eth->netdev[id]->base_addr = (unsigned long)eth->base; 3874 3875 eth->netdev[id]->hw_features = eth->soc->hw_features; 3876 if (eth->hwlro) 3877 eth->netdev[id]->hw_features |= NETIF_F_LRO; 3878 3879 eth->netdev[id]->vlan_features = eth->soc->hw_features & 3880 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 3881 eth->netdev[id]->features |= eth->soc->hw_features; 3882 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 3883 3884 eth->netdev[id]->irq = eth->irq[0]; 3885 eth->netdev[id]->dev.of_node = np; 3886 3887 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3888 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 3889 else 3890 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 3891 3892 return 0; 3893 3894 free_netdev: 3895 free_netdev(eth->netdev[id]); 3896 return err; 3897 } 3898 3899 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 3900 { 3901 struct net_device *dev, *tmp; 3902 LIST_HEAD(dev_list); 3903 int i; 3904 3905 rtnl_lock(); 3906 3907 for (i = 0; i < MTK_MAC_COUNT; i++) { 3908 dev = eth->netdev[i]; 3909 3910 if (!dev || !(dev->flags & IFF_UP)) 3911 continue; 3912 3913 list_add_tail(&dev->close_list, &dev_list); 3914 } 3915 3916 dev_close_many(&dev_list, false); 3917 3918 eth->dma_dev = dma_dev; 3919 3920 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 3921 list_del_init(&dev->close_list); 3922 dev_open(dev, NULL); 3923 } 3924 3925 rtnl_unlock(); 3926 } 3927 3928 static int mtk_probe(struct platform_device *pdev) 3929 { 3930 struct device_node *mac_np; 3931 struct mtk_eth *eth; 3932 int err, i; 3933 3934 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 3935 if (!eth) 3936 return -ENOMEM; 3937 3938 eth->soc = of_device_get_match_data(&pdev->dev); 3939 3940 eth->dev = &pdev->dev; 3941 eth->dma_dev = &pdev->dev; 3942 eth->base = devm_platform_ioremap_resource(pdev, 0); 3943 if (IS_ERR(eth->base)) 3944 return PTR_ERR(eth->base); 3945 3946 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3947 eth->ip_align = NET_IP_ALIGN; 3948 3949 spin_lock_init(ð->page_lock); 3950 spin_lock_init(ð->tx_irq_lock); 3951 spin_lock_init(ð->rx_irq_lock); 3952 spin_lock_init(ð->dim_lock); 3953 3954 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3955 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 3956 3957 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 3958 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 3959 3960 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3961 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3962 "mediatek,ethsys"); 3963 if (IS_ERR(eth->ethsys)) { 3964 dev_err(&pdev->dev, "no ethsys regmap found\n"); 3965 return PTR_ERR(eth->ethsys); 3966 } 3967 } 3968 3969 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 3970 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3971 "mediatek,infracfg"); 3972 if (IS_ERR(eth->infra)) { 3973 dev_err(&pdev->dev, "no infracfg regmap found\n"); 3974 return PTR_ERR(eth->infra); 3975 } 3976 } 3977 3978 if (of_dma_is_coherent(pdev->dev.of_node)) { 3979 struct regmap *cci; 3980 3981 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 3982 "cci-control-port"); 3983 /* enable CPU/bus coherency */ 3984 if (!IS_ERR(cci)) 3985 regmap_write(cci, 0, 3); 3986 } 3987 3988 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 3989 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 3990 GFP_KERNEL); 3991 if (!eth->sgmii) 3992 return -ENOMEM; 3993 3994 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 3995 eth->soc->ana_rgc3); 3996 3997 if (err) 3998 return err; 3999 } 4000 4001 if (eth->soc->required_pctl) { 4002 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4003 "mediatek,pctl"); 4004 if (IS_ERR(eth->pctl)) { 4005 dev_err(&pdev->dev, "no pctl regmap found\n"); 4006 return PTR_ERR(eth->pctl); 4007 } 4008 } 4009 4010 for (i = 0;; i++) { 4011 struct device_node *np = of_parse_phandle(pdev->dev.of_node, 4012 "mediatek,wed", i); 4013 static const u32 wdma_regs[] = { 4014 MTK_WDMA0_BASE, 4015 MTK_WDMA1_BASE 4016 }; 4017 void __iomem *wdma; 4018 4019 if (!np || i >= ARRAY_SIZE(wdma_regs)) 4020 break; 4021 4022 wdma = eth->base + wdma_regs[i]; 4023 mtk_wed_add_hw(np, eth, wdma, i); 4024 } 4025 4026 for (i = 0; i < 3; i++) { 4027 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4028 eth->irq[i] = eth->irq[0]; 4029 else 4030 eth->irq[i] = platform_get_irq(pdev, i); 4031 if (eth->irq[i] < 0) { 4032 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4033 return -ENXIO; 4034 } 4035 } 4036 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4037 eth->clks[i] = devm_clk_get(eth->dev, 4038 mtk_clks_source_name[i]); 4039 if (IS_ERR(eth->clks[i])) { 4040 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 4041 return -EPROBE_DEFER; 4042 if (eth->soc->required_clks & BIT(i)) { 4043 dev_err(&pdev->dev, "clock %s not found\n", 4044 mtk_clks_source_name[i]); 4045 return -EINVAL; 4046 } 4047 eth->clks[i] = NULL; 4048 } 4049 } 4050 4051 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4052 INIT_WORK(ð->pending_work, mtk_pending_work); 4053 4054 err = mtk_hw_init(eth); 4055 if (err) 4056 return err; 4057 4058 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4059 4060 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4061 if (!of_device_is_compatible(mac_np, 4062 "mediatek,eth-mac")) 4063 continue; 4064 4065 if (!of_device_is_available(mac_np)) 4066 continue; 4067 4068 err = mtk_add_mac(eth, mac_np); 4069 if (err) { 4070 of_node_put(mac_np); 4071 goto err_deinit_hw; 4072 } 4073 } 4074 4075 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4076 err = devm_request_irq(eth->dev, eth->irq[0], 4077 mtk_handle_irq, 0, 4078 dev_name(eth->dev), eth); 4079 } else { 4080 err = devm_request_irq(eth->dev, eth->irq[1], 4081 mtk_handle_irq_tx, 0, 4082 dev_name(eth->dev), eth); 4083 if (err) 4084 goto err_free_dev; 4085 4086 err = devm_request_irq(eth->dev, eth->irq[2], 4087 mtk_handle_irq_rx, 0, 4088 dev_name(eth->dev), eth); 4089 } 4090 if (err) 4091 goto err_free_dev; 4092 4093 /* No MT7628/88 support yet */ 4094 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4095 err = mtk_mdio_init(eth); 4096 if (err) 4097 goto err_free_dev; 4098 } 4099 4100 if (eth->soc->offload_version) { 4101 eth->ppe = mtk_ppe_init(eth, eth->base + MTK_ETH_PPE_BASE, 2); 4102 if (!eth->ppe) { 4103 err = -ENOMEM; 4104 goto err_free_dev; 4105 } 4106 4107 err = mtk_eth_offload_init(eth); 4108 if (err) 4109 goto err_free_dev; 4110 } 4111 4112 for (i = 0; i < MTK_MAX_DEVS; i++) { 4113 if (!eth->netdev[i]) 4114 continue; 4115 4116 err = register_netdev(eth->netdev[i]); 4117 if (err) { 4118 dev_err(eth->dev, "error bringing up device\n"); 4119 goto err_deinit_mdio; 4120 } else 4121 netif_info(eth, probe, eth->netdev[i], 4122 "mediatek frame engine at 0x%08lx, irq %d\n", 4123 eth->netdev[i]->base_addr, eth->irq[0]); 4124 } 4125 4126 /* we run 2 devices on the same DMA ring so we need a dummy device 4127 * for NAPI to work 4128 */ 4129 init_dummy_netdev(ð->dummy_dev); 4130 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 4131 NAPI_POLL_WEIGHT); 4132 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 4133 NAPI_POLL_WEIGHT); 4134 4135 platform_set_drvdata(pdev, eth); 4136 4137 return 0; 4138 4139 err_deinit_mdio: 4140 mtk_mdio_cleanup(eth); 4141 err_free_dev: 4142 mtk_free_dev(eth); 4143 err_deinit_hw: 4144 mtk_hw_deinit(eth); 4145 4146 return err; 4147 } 4148 4149 static int mtk_remove(struct platform_device *pdev) 4150 { 4151 struct mtk_eth *eth = platform_get_drvdata(pdev); 4152 struct mtk_mac *mac; 4153 int i; 4154 4155 /* stop all devices to make sure that dma is properly shut down */ 4156 for (i = 0; i < MTK_MAC_COUNT; i++) { 4157 if (!eth->netdev[i]) 4158 continue; 4159 mtk_stop(eth->netdev[i]); 4160 mac = netdev_priv(eth->netdev[i]); 4161 phylink_disconnect_phy(mac->phylink); 4162 } 4163 4164 mtk_hw_deinit(eth); 4165 4166 netif_napi_del(ð->tx_napi); 4167 netif_napi_del(ð->rx_napi); 4168 mtk_cleanup(eth); 4169 mtk_mdio_cleanup(eth); 4170 4171 return 0; 4172 } 4173 4174 static const struct mtk_soc_data mt2701_data = { 4175 .reg_map = &mtk_reg_map, 4176 .caps = MT7623_CAPS | MTK_HWLRO, 4177 .hw_features = MTK_HW_FEATURES, 4178 .required_clks = MT7623_CLKS_BITMAP, 4179 .required_pctl = true, 4180 .txrx = { 4181 .txd_size = sizeof(struct mtk_tx_dma), 4182 .rxd_size = sizeof(struct mtk_rx_dma), 4183 .rx_irq_done_mask = MTK_RX_DONE_INT, 4184 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4185 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4186 .dma_len_offset = 16, 4187 }, 4188 }; 4189 4190 static const struct mtk_soc_data mt7621_data = { 4191 .reg_map = &mtk_reg_map, 4192 .caps = MT7621_CAPS, 4193 .hw_features = MTK_HW_FEATURES, 4194 .required_clks = MT7621_CLKS_BITMAP, 4195 .required_pctl = false, 4196 .offload_version = 2, 4197 .txrx = { 4198 .txd_size = sizeof(struct mtk_tx_dma), 4199 .rxd_size = sizeof(struct mtk_rx_dma), 4200 .rx_irq_done_mask = MTK_RX_DONE_INT, 4201 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4202 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4203 .dma_len_offset = 16, 4204 }, 4205 }; 4206 4207 static const struct mtk_soc_data mt7622_data = { 4208 .reg_map = &mtk_reg_map, 4209 .ana_rgc3 = 0x2028, 4210 .caps = MT7622_CAPS | MTK_HWLRO, 4211 .hw_features = MTK_HW_FEATURES, 4212 .required_clks = MT7622_CLKS_BITMAP, 4213 .required_pctl = false, 4214 .offload_version = 2, 4215 .txrx = { 4216 .txd_size = sizeof(struct mtk_tx_dma), 4217 .rxd_size = sizeof(struct mtk_rx_dma), 4218 .rx_irq_done_mask = MTK_RX_DONE_INT, 4219 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4220 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4221 .dma_len_offset = 16, 4222 }, 4223 }; 4224 4225 static const struct mtk_soc_data mt7623_data = { 4226 .reg_map = &mtk_reg_map, 4227 .caps = MT7623_CAPS | MTK_HWLRO, 4228 .hw_features = MTK_HW_FEATURES, 4229 .required_clks = MT7623_CLKS_BITMAP, 4230 .required_pctl = true, 4231 .offload_version = 2, 4232 .txrx = { 4233 .txd_size = sizeof(struct mtk_tx_dma), 4234 .rxd_size = sizeof(struct mtk_rx_dma), 4235 .rx_irq_done_mask = MTK_RX_DONE_INT, 4236 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4237 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4238 .dma_len_offset = 16, 4239 }, 4240 }; 4241 4242 static const struct mtk_soc_data mt7629_data = { 4243 .reg_map = &mtk_reg_map, 4244 .ana_rgc3 = 0x128, 4245 .caps = MT7629_CAPS | MTK_HWLRO, 4246 .hw_features = MTK_HW_FEATURES, 4247 .required_clks = MT7629_CLKS_BITMAP, 4248 .required_pctl = false, 4249 .txrx = { 4250 .txd_size = sizeof(struct mtk_tx_dma), 4251 .rxd_size = sizeof(struct mtk_rx_dma), 4252 .rx_irq_done_mask = MTK_RX_DONE_INT, 4253 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4254 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4255 .dma_len_offset = 16, 4256 }, 4257 }; 4258 4259 static const struct mtk_soc_data mt7986_data = { 4260 .reg_map = &mt7986_reg_map, 4261 .ana_rgc3 = 0x128, 4262 .caps = MT7986_CAPS, 4263 .required_clks = MT7986_CLKS_BITMAP, 4264 .required_pctl = false, 4265 .txrx = { 4266 .txd_size = sizeof(struct mtk_tx_dma_v2), 4267 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4268 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4269 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4270 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4271 .dma_len_offset = 8, 4272 }, 4273 }; 4274 4275 static const struct mtk_soc_data rt5350_data = { 4276 .reg_map = &mt7628_reg_map, 4277 .caps = MT7628_CAPS, 4278 .hw_features = MTK_HW_FEATURES_MT7628, 4279 .required_clks = MT7628_CLKS_BITMAP, 4280 .required_pctl = false, 4281 .txrx = { 4282 .txd_size = sizeof(struct mtk_tx_dma), 4283 .rxd_size = sizeof(struct mtk_rx_dma), 4284 .rx_irq_done_mask = MTK_RX_DONE_INT, 4285 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4286 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4287 .dma_len_offset = 16, 4288 }, 4289 }; 4290 4291 const struct of_device_id of_mtk_match[] = { 4292 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4293 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4294 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4295 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4296 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4297 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4298 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4299 {}, 4300 }; 4301 MODULE_DEVICE_TABLE(of, of_mtk_match); 4302 4303 static struct platform_driver mtk_driver = { 4304 .probe = mtk_probe, 4305 .remove = mtk_remove, 4306 .driver = { 4307 .name = "mtk_soc_eth", 4308 .of_match_table = of_mtk_match, 4309 }, 4310 }; 4311 4312 module_platform_driver(mtk_driver); 4313 4314 MODULE_LICENSE("GPL"); 4315 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4316 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4317