1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/jhash.h> 24 #include <linux/bitfield.h> 25 #include <net/dsa.h> 26 #include <net/dst_metadata.h> 27 28 #include "mtk_eth_soc.h" 29 #include "mtk_wed.h" 30 31 static int mtk_msg_level = -1; 32 module_param_named(msg_level, mtk_msg_level, int, 0); 33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 34 35 #define MTK_ETHTOOL_STAT(x) { #x, \ 36 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 37 38 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 39 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 40 sizeof(u64) } 41 42 static const struct mtk_reg_map mtk_reg_map = { 43 .tx_irq_mask = 0x1a1c, 44 .tx_irq_status = 0x1a18, 45 .pdma = { 46 .rx_ptr = 0x0900, 47 .rx_cnt_cfg = 0x0904, 48 .pcrx_ptr = 0x0908, 49 .glo_cfg = 0x0a04, 50 .rst_idx = 0x0a08, 51 .delay_irq = 0x0a0c, 52 .irq_status = 0x0a20, 53 .irq_mask = 0x0a28, 54 .adma_rx_dbg0 = 0x0a38, 55 .int_grp = 0x0a50, 56 }, 57 .qdma = { 58 .qtx_cfg = 0x1800, 59 .qtx_sch = 0x1804, 60 .rx_ptr = 0x1900, 61 .rx_cnt_cfg = 0x1904, 62 .qcrx_ptr = 0x1908, 63 .glo_cfg = 0x1a04, 64 .rst_idx = 0x1a08, 65 .delay_irq = 0x1a0c, 66 .fc_th = 0x1a10, 67 .tx_sch_rate = 0x1a14, 68 .int_grp = 0x1a20, 69 .hred = 0x1a44, 70 .ctx_ptr = 0x1b00, 71 .dtx_ptr = 0x1b04, 72 .crx_ptr = 0x1b10, 73 .drx_ptr = 0x1b14, 74 .fq_head = 0x1b20, 75 .fq_tail = 0x1b24, 76 .fq_count = 0x1b28, 77 .fq_blen = 0x1b2c, 78 }, 79 .gdm1_cnt = 0x2400, 80 .gdma_to_ppe = 0x4444, 81 .ppe_base = 0x0c00, 82 .wdma_base = { 83 [0] = 0x2800, 84 [1] = 0x2c00, 85 }, 86 .pse_iq_sta = 0x0110, 87 .pse_oq_sta = 0x0118, 88 }; 89 90 static const struct mtk_reg_map mt7628_reg_map = { 91 .tx_irq_mask = 0x0a28, 92 .tx_irq_status = 0x0a20, 93 .pdma = { 94 .rx_ptr = 0x0900, 95 .rx_cnt_cfg = 0x0904, 96 .pcrx_ptr = 0x0908, 97 .glo_cfg = 0x0a04, 98 .rst_idx = 0x0a08, 99 .delay_irq = 0x0a0c, 100 .irq_status = 0x0a20, 101 .irq_mask = 0x0a28, 102 .int_grp = 0x0a50, 103 }, 104 }; 105 106 static const struct mtk_reg_map mt7986_reg_map = { 107 .tx_irq_mask = 0x461c, 108 .tx_irq_status = 0x4618, 109 .pdma = { 110 .rx_ptr = 0x6100, 111 .rx_cnt_cfg = 0x6104, 112 .pcrx_ptr = 0x6108, 113 .glo_cfg = 0x6204, 114 .rst_idx = 0x6208, 115 .delay_irq = 0x620c, 116 .irq_status = 0x6220, 117 .irq_mask = 0x6228, 118 .adma_rx_dbg0 = 0x6238, 119 .int_grp = 0x6250, 120 }, 121 .qdma = { 122 .qtx_cfg = 0x4400, 123 .qtx_sch = 0x4404, 124 .rx_ptr = 0x4500, 125 .rx_cnt_cfg = 0x4504, 126 .qcrx_ptr = 0x4508, 127 .glo_cfg = 0x4604, 128 .rst_idx = 0x4608, 129 .delay_irq = 0x460c, 130 .fc_th = 0x4610, 131 .int_grp = 0x4620, 132 .hred = 0x4644, 133 .ctx_ptr = 0x4700, 134 .dtx_ptr = 0x4704, 135 .crx_ptr = 0x4710, 136 .drx_ptr = 0x4714, 137 .fq_head = 0x4720, 138 .fq_tail = 0x4724, 139 .fq_count = 0x4728, 140 .fq_blen = 0x472c, 141 .tx_sch_rate = 0x4798, 142 }, 143 .gdm1_cnt = 0x1c00, 144 .gdma_to_ppe = 0x3333, 145 .ppe_base = 0x2000, 146 .wdma_base = { 147 [0] = 0x4800, 148 [1] = 0x4c00, 149 }, 150 .pse_iq_sta = 0x0180, 151 .pse_oq_sta = 0x01a0, 152 }; 153 154 /* strings used by ethtool */ 155 static const struct mtk_ethtool_stats { 156 char str[ETH_GSTRING_LEN]; 157 u32 offset; 158 } mtk_ethtool_stats[] = { 159 MTK_ETHTOOL_STAT(tx_bytes), 160 MTK_ETHTOOL_STAT(tx_packets), 161 MTK_ETHTOOL_STAT(tx_skip), 162 MTK_ETHTOOL_STAT(tx_collisions), 163 MTK_ETHTOOL_STAT(rx_bytes), 164 MTK_ETHTOOL_STAT(rx_packets), 165 MTK_ETHTOOL_STAT(rx_overflow), 166 MTK_ETHTOOL_STAT(rx_fcs_errors), 167 MTK_ETHTOOL_STAT(rx_short_errors), 168 MTK_ETHTOOL_STAT(rx_long_errors), 169 MTK_ETHTOOL_STAT(rx_checksum_errors), 170 MTK_ETHTOOL_STAT(rx_flow_control_packets), 171 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 172 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 173 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 174 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 175 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 176 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 177 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 178 }; 179 180 static const char * const mtk_clks_source_name[] = { 181 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 182 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 183 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 184 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 185 }; 186 187 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 188 { 189 __raw_writel(val, eth->base + reg); 190 } 191 192 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 193 { 194 return __raw_readl(eth->base + reg); 195 } 196 197 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 198 { 199 u32 val; 200 201 val = mtk_r32(eth, reg); 202 val &= ~mask; 203 val |= set; 204 mtk_w32(eth, val, reg); 205 return reg; 206 } 207 208 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 209 { 210 unsigned long t_start = jiffies; 211 212 while (1) { 213 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 214 return 0; 215 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 216 break; 217 cond_resched(); 218 } 219 220 dev_err(eth->dev, "mdio: MDIO timeout\n"); 221 return -ETIMEDOUT; 222 } 223 224 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 225 u32 write_data) 226 { 227 int ret; 228 229 ret = mtk_mdio_busy_wait(eth); 230 if (ret < 0) 231 return ret; 232 233 mtk_w32(eth, PHY_IAC_ACCESS | 234 PHY_IAC_START_C22 | 235 PHY_IAC_CMD_WRITE | 236 PHY_IAC_REG(phy_reg) | 237 PHY_IAC_ADDR(phy_addr) | 238 PHY_IAC_DATA(write_data), 239 MTK_PHY_IAC); 240 241 ret = mtk_mdio_busy_wait(eth); 242 if (ret < 0) 243 return ret; 244 245 return 0; 246 } 247 248 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 249 u32 devad, u32 phy_reg, u32 write_data) 250 { 251 int ret; 252 253 ret = mtk_mdio_busy_wait(eth); 254 if (ret < 0) 255 return ret; 256 257 mtk_w32(eth, PHY_IAC_ACCESS | 258 PHY_IAC_START_C45 | 259 PHY_IAC_CMD_C45_ADDR | 260 PHY_IAC_REG(devad) | 261 PHY_IAC_ADDR(phy_addr) | 262 PHY_IAC_DATA(phy_reg), 263 MTK_PHY_IAC); 264 265 ret = mtk_mdio_busy_wait(eth); 266 if (ret < 0) 267 return ret; 268 269 mtk_w32(eth, PHY_IAC_ACCESS | 270 PHY_IAC_START_C45 | 271 PHY_IAC_CMD_WRITE | 272 PHY_IAC_REG(devad) | 273 PHY_IAC_ADDR(phy_addr) | 274 PHY_IAC_DATA(write_data), 275 MTK_PHY_IAC); 276 277 ret = mtk_mdio_busy_wait(eth); 278 if (ret < 0) 279 return ret; 280 281 return 0; 282 } 283 284 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 285 { 286 int ret; 287 288 ret = mtk_mdio_busy_wait(eth); 289 if (ret < 0) 290 return ret; 291 292 mtk_w32(eth, PHY_IAC_ACCESS | 293 PHY_IAC_START_C22 | 294 PHY_IAC_CMD_C22_READ | 295 PHY_IAC_REG(phy_reg) | 296 PHY_IAC_ADDR(phy_addr), 297 MTK_PHY_IAC); 298 299 ret = mtk_mdio_busy_wait(eth); 300 if (ret < 0) 301 return ret; 302 303 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 304 } 305 306 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 307 u32 devad, u32 phy_reg) 308 { 309 int ret; 310 311 ret = mtk_mdio_busy_wait(eth); 312 if (ret < 0) 313 return ret; 314 315 mtk_w32(eth, PHY_IAC_ACCESS | 316 PHY_IAC_START_C45 | 317 PHY_IAC_CMD_C45_ADDR | 318 PHY_IAC_REG(devad) | 319 PHY_IAC_ADDR(phy_addr) | 320 PHY_IAC_DATA(phy_reg), 321 MTK_PHY_IAC); 322 323 ret = mtk_mdio_busy_wait(eth); 324 if (ret < 0) 325 return ret; 326 327 mtk_w32(eth, PHY_IAC_ACCESS | 328 PHY_IAC_START_C45 | 329 PHY_IAC_CMD_C45_READ | 330 PHY_IAC_REG(devad) | 331 PHY_IAC_ADDR(phy_addr), 332 MTK_PHY_IAC); 333 334 ret = mtk_mdio_busy_wait(eth); 335 if (ret < 0) 336 return ret; 337 338 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 339 } 340 341 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 342 int phy_reg, u16 val) 343 { 344 struct mtk_eth *eth = bus->priv; 345 346 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 347 } 348 349 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 350 int devad, int phy_reg, u16 val) 351 { 352 struct mtk_eth *eth = bus->priv; 353 354 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 355 } 356 357 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 358 { 359 struct mtk_eth *eth = bus->priv; 360 361 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 362 } 363 364 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 365 int phy_reg) 366 { 367 struct mtk_eth *eth = bus->priv; 368 369 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 370 } 371 372 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 373 phy_interface_t interface) 374 { 375 u32 val; 376 377 /* Check DDR memory type. 378 * Currently TRGMII mode with DDR2 memory is not supported. 379 */ 380 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 381 if (interface == PHY_INTERFACE_MODE_TRGMII && 382 val & SYSCFG_DRAM_TYPE_DDR2) { 383 dev_err(eth->dev, 384 "TRGMII mode with DDR2 memory is not supported!\n"); 385 return -EOPNOTSUPP; 386 } 387 388 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 389 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 390 391 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 392 ETHSYS_TRGMII_MT7621_MASK, val); 393 394 return 0; 395 } 396 397 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 398 phy_interface_t interface, int speed) 399 { 400 u32 val; 401 int ret; 402 403 if (interface == PHY_INTERFACE_MODE_TRGMII) { 404 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 405 val = 500000000; 406 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 407 if (ret) 408 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 409 return; 410 } 411 412 val = (speed == SPEED_1000) ? 413 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 414 mtk_w32(eth, val, INTF_MODE); 415 416 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 417 ETHSYS_TRGMII_CLK_SEL362_5, 418 ETHSYS_TRGMII_CLK_SEL362_5); 419 420 val = (speed == SPEED_1000) ? 250000000 : 500000000; 421 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 422 if (ret) 423 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 424 425 val = (speed == SPEED_1000) ? 426 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 427 mtk_w32(eth, val, TRGMII_RCK_CTRL); 428 429 val = (speed == SPEED_1000) ? 430 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 431 mtk_w32(eth, val, TRGMII_TCK_CTRL); 432 } 433 434 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 435 phy_interface_t interface) 436 { 437 struct mtk_mac *mac = container_of(config, struct mtk_mac, 438 phylink_config); 439 struct mtk_eth *eth = mac->hw; 440 unsigned int sid; 441 442 if (interface == PHY_INTERFACE_MODE_SGMII || 443 phy_interface_mode_is_8023z(interface)) { 444 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 445 0 : mac->id; 446 447 return mtk_sgmii_select_pcs(eth->sgmii, sid); 448 } 449 450 return NULL; 451 } 452 453 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 454 const struct phylink_link_state *state) 455 { 456 struct mtk_mac *mac = container_of(config, struct mtk_mac, 457 phylink_config); 458 struct mtk_eth *eth = mac->hw; 459 int val, ge_mode, err = 0; 460 u32 i; 461 462 /* MT76x8 has no hardware settings between for the MAC */ 463 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 464 mac->interface != state->interface) { 465 /* Setup soc pin functions */ 466 switch (state->interface) { 467 case PHY_INTERFACE_MODE_TRGMII: 468 if (mac->id) 469 goto err_phy; 470 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 471 MTK_GMAC1_TRGMII)) 472 goto err_phy; 473 fallthrough; 474 case PHY_INTERFACE_MODE_RGMII_TXID: 475 case PHY_INTERFACE_MODE_RGMII_RXID: 476 case PHY_INTERFACE_MODE_RGMII_ID: 477 case PHY_INTERFACE_MODE_RGMII: 478 case PHY_INTERFACE_MODE_MII: 479 case PHY_INTERFACE_MODE_REVMII: 480 case PHY_INTERFACE_MODE_RMII: 481 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 482 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 483 if (err) 484 goto init_err; 485 } 486 break; 487 case PHY_INTERFACE_MODE_1000BASEX: 488 case PHY_INTERFACE_MODE_2500BASEX: 489 case PHY_INTERFACE_MODE_SGMII: 490 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 491 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 492 if (err) 493 goto init_err; 494 } 495 break; 496 case PHY_INTERFACE_MODE_GMII: 497 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 498 err = mtk_gmac_gephy_path_setup(eth, mac->id); 499 if (err) 500 goto init_err; 501 } 502 break; 503 default: 504 goto err_phy; 505 } 506 507 /* Setup clock for 1st gmac */ 508 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 509 !phy_interface_mode_is_8023z(state->interface) && 510 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 511 if (MTK_HAS_CAPS(mac->hw->soc->caps, 512 MTK_TRGMII_MT7621_CLK)) { 513 if (mt7621_gmac0_rgmii_adjust(mac->hw, 514 state->interface)) 515 goto err_phy; 516 } else { 517 /* FIXME: this is incorrect. Not only does it 518 * use state->speed (which is not guaranteed 519 * to be correct) but it also makes use of it 520 * in a code path that will only be reachable 521 * when the PHY interface mode changes, not 522 * when the speed changes. Consequently, RGMII 523 * is probably broken. 524 */ 525 mtk_gmac0_rgmii_adjust(mac->hw, 526 state->interface, 527 state->speed); 528 529 /* mt7623_pad_clk_setup */ 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mtk_w32(mac->hw, 532 TD_DM_DRVP(8) | TD_DM_DRVN(8), 533 TRGMII_TD_ODT(i)); 534 535 /* Assert/release MT7623 RXC reset */ 536 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 537 TRGMII_RCK_CTRL); 538 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 539 } 540 } 541 542 ge_mode = 0; 543 switch (state->interface) { 544 case PHY_INTERFACE_MODE_MII: 545 case PHY_INTERFACE_MODE_GMII: 546 ge_mode = 1; 547 break; 548 case PHY_INTERFACE_MODE_REVMII: 549 ge_mode = 2; 550 break; 551 case PHY_INTERFACE_MODE_RMII: 552 if (mac->id) 553 goto err_phy; 554 ge_mode = 3; 555 break; 556 default: 557 break; 558 } 559 560 /* put the gmac into the right mode */ 561 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 562 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 563 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 564 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 565 566 mac->interface = state->interface; 567 } 568 569 /* SGMII */ 570 if (state->interface == PHY_INTERFACE_MODE_SGMII || 571 phy_interface_mode_is_8023z(state->interface)) { 572 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 573 * being setup done. 574 */ 575 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 576 577 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 578 SYSCFG0_SGMII_MASK, 579 ~(u32)SYSCFG0_SGMII_MASK); 580 581 /* Save the syscfg0 value for mac_finish */ 582 mac->syscfg0 = val; 583 } else if (phylink_autoneg_inband(mode)) { 584 dev_err(eth->dev, 585 "In-band mode not supported in non SGMII mode!\n"); 586 return; 587 } 588 589 return; 590 591 err_phy: 592 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 593 mac->id, phy_modes(state->interface)); 594 return; 595 596 init_err: 597 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 598 mac->id, phy_modes(state->interface), err); 599 } 600 601 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 602 phy_interface_t interface) 603 { 604 struct mtk_mac *mac = container_of(config, struct mtk_mac, 605 phylink_config); 606 struct mtk_eth *eth = mac->hw; 607 u32 mcr_cur, mcr_new; 608 609 /* Enable SGMII */ 610 if (interface == PHY_INTERFACE_MODE_SGMII || 611 phy_interface_mode_is_8023z(interface)) 612 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 613 SYSCFG0_SGMII_MASK, mac->syscfg0); 614 615 /* Setup gmac */ 616 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 617 mcr_new = mcr_cur; 618 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 619 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 620 MAC_MCR_RX_FIFO_CLR_DIS; 621 622 /* Only update control register when needed! */ 623 if (mcr_new != mcr_cur) 624 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 625 626 return 0; 627 } 628 629 static void mtk_mac_pcs_get_state(struct phylink_config *config, 630 struct phylink_link_state *state) 631 { 632 struct mtk_mac *mac = container_of(config, struct mtk_mac, 633 phylink_config); 634 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 635 636 state->link = (pmsr & MAC_MSR_LINK); 637 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 638 639 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 640 case 0: 641 state->speed = SPEED_10; 642 break; 643 case MAC_MSR_SPEED_100: 644 state->speed = SPEED_100; 645 break; 646 case MAC_MSR_SPEED_1000: 647 state->speed = SPEED_1000; 648 break; 649 default: 650 state->speed = SPEED_UNKNOWN; 651 break; 652 } 653 654 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 655 if (pmsr & MAC_MSR_RX_FC) 656 state->pause |= MLO_PAUSE_RX; 657 if (pmsr & MAC_MSR_TX_FC) 658 state->pause |= MLO_PAUSE_TX; 659 } 660 661 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 662 phy_interface_t interface) 663 { 664 struct mtk_mac *mac = container_of(config, struct mtk_mac, 665 phylink_config); 666 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 667 668 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 669 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 670 } 671 672 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 673 int speed) 674 { 675 const struct mtk_soc_data *soc = eth->soc; 676 u32 ofs, val; 677 678 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 679 return; 680 681 val = MTK_QTX_SCH_MIN_RATE_EN | 682 /* minimum: 10 Mbps */ 683 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 684 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 685 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 686 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 687 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 688 689 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 690 switch (speed) { 691 case SPEED_10: 692 val |= MTK_QTX_SCH_MAX_RATE_EN | 693 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 694 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 695 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 696 break; 697 case SPEED_100: 698 val |= MTK_QTX_SCH_MAX_RATE_EN | 699 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 700 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 701 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 702 break; 703 case SPEED_1000: 704 val |= MTK_QTX_SCH_MAX_RATE_EN | 705 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 706 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 707 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 708 break; 709 default: 710 break; 711 } 712 } else { 713 switch (speed) { 714 case SPEED_10: 715 val |= MTK_QTX_SCH_MAX_RATE_EN | 716 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 717 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 718 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 719 break; 720 case SPEED_100: 721 val |= MTK_QTX_SCH_MAX_RATE_EN | 722 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 723 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 724 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 725 break; 726 case SPEED_1000: 727 val |= MTK_QTX_SCH_MAX_RATE_EN | 728 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 729 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 730 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 731 break; 732 default: 733 break; 734 } 735 } 736 737 ofs = MTK_QTX_OFFSET * idx; 738 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 739 } 740 741 static void mtk_mac_link_up(struct phylink_config *config, 742 struct phy_device *phy, 743 unsigned int mode, phy_interface_t interface, 744 int speed, int duplex, bool tx_pause, bool rx_pause) 745 { 746 struct mtk_mac *mac = container_of(config, struct mtk_mac, 747 phylink_config); 748 u32 mcr; 749 750 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 751 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 752 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 753 MAC_MCR_FORCE_RX_FC); 754 755 /* Configure speed */ 756 switch (speed) { 757 case SPEED_2500: 758 case SPEED_1000: 759 mcr |= MAC_MCR_SPEED_1000; 760 break; 761 case SPEED_100: 762 mcr |= MAC_MCR_SPEED_100; 763 break; 764 } 765 766 mtk_set_queue_speed(mac->hw, mac->id, speed); 767 768 /* Configure duplex */ 769 if (duplex == DUPLEX_FULL) 770 mcr |= MAC_MCR_FORCE_DPX; 771 772 /* Configure pause modes - phylink will avoid these for half duplex */ 773 if (tx_pause) 774 mcr |= MAC_MCR_FORCE_TX_FC; 775 if (rx_pause) 776 mcr |= MAC_MCR_FORCE_RX_FC; 777 778 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 779 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 780 } 781 782 static const struct phylink_mac_ops mtk_phylink_ops = { 783 .mac_select_pcs = mtk_mac_select_pcs, 784 .mac_pcs_get_state = mtk_mac_pcs_get_state, 785 .mac_config = mtk_mac_config, 786 .mac_finish = mtk_mac_finish, 787 .mac_link_down = mtk_mac_link_down, 788 .mac_link_up = mtk_mac_link_up, 789 }; 790 791 static int mtk_mdio_init(struct mtk_eth *eth) 792 { 793 struct device_node *mii_np; 794 int ret; 795 796 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 797 if (!mii_np) { 798 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 799 return -ENODEV; 800 } 801 802 if (!of_device_is_available(mii_np)) { 803 ret = -ENODEV; 804 goto err_put_node; 805 } 806 807 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 808 if (!eth->mii_bus) { 809 ret = -ENOMEM; 810 goto err_put_node; 811 } 812 813 eth->mii_bus->name = "mdio"; 814 eth->mii_bus->read = mtk_mdio_read_c22; 815 eth->mii_bus->write = mtk_mdio_write_c22; 816 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 817 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 818 eth->mii_bus->priv = eth; 819 eth->mii_bus->parent = eth->dev; 820 821 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 822 ret = of_mdiobus_register(eth->mii_bus, mii_np); 823 824 err_put_node: 825 of_node_put(mii_np); 826 return ret; 827 } 828 829 static void mtk_mdio_cleanup(struct mtk_eth *eth) 830 { 831 if (!eth->mii_bus) 832 return; 833 834 mdiobus_unregister(eth->mii_bus); 835 } 836 837 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 838 { 839 unsigned long flags; 840 u32 val; 841 842 spin_lock_irqsave(ð->tx_irq_lock, flags); 843 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 844 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 845 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 846 } 847 848 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 849 { 850 unsigned long flags; 851 u32 val; 852 853 spin_lock_irqsave(ð->tx_irq_lock, flags); 854 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 855 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 856 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 857 } 858 859 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 860 { 861 unsigned long flags; 862 u32 val; 863 864 spin_lock_irqsave(ð->rx_irq_lock, flags); 865 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 866 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 867 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 868 } 869 870 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 871 { 872 unsigned long flags; 873 u32 val; 874 875 spin_lock_irqsave(ð->rx_irq_lock, flags); 876 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 877 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 878 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 879 } 880 881 static int mtk_set_mac_address(struct net_device *dev, void *p) 882 { 883 int ret = eth_mac_addr(dev, p); 884 struct mtk_mac *mac = netdev_priv(dev); 885 struct mtk_eth *eth = mac->hw; 886 const char *macaddr = dev->dev_addr; 887 888 if (ret) 889 return ret; 890 891 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 892 return -EBUSY; 893 894 spin_lock_bh(&mac->hw->page_lock); 895 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 896 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 897 MT7628_SDM_MAC_ADRH); 898 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 899 (macaddr[4] << 8) | macaddr[5], 900 MT7628_SDM_MAC_ADRL); 901 } else { 902 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 903 MTK_GDMA_MAC_ADRH(mac->id)); 904 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 905 (macaddr[4] << 8) | macaddr[5], 906 MTK_GDMA_MAC_ADRL(mac->id)); 907 } 908 spin_unlock_bh(&mac->hw->page_lock); 909 910 return 0; 911 } 912 913 void mtk_stats_update_mac(struct mtk_mac *mac) 914 { 915 struct mtk_hw_stats *hw_stats = mac->hw_stats; 916 struct mtk_eth *eth = mac->hw; 917 918 u64_stats_update_begin(&hw_stats->syncp); 919 920 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 921 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 922 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 923 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 924 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 925 hw_stats->rx_checksum_errors += 926 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 927 } else { 928 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 929 unsigned int offs = hw_stats->reg_offset; 930 u64 stats; 931 932 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 933 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 934 if (stats) 935 hw_stats->rx_bytes += (stats << 32); 936 hw_stats->rx_packets += 937 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 938 hw_stats->rx_overflow += 939 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 940 hw_stats->rx_fcs_errors += 941 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 942 hw_stats->rx_short_errors += 943 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 944 hw_stats->rx_long_errors += 945 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 946 hw_stats->rx_checksum_errors += 947 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 948 hw_stats->rx_flow_control_packets += 949 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 950 hw_stats->tx_skip += 951 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 952 hw_stats->tx_collisions += 953 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 954 hw_stats->tx_bytes += 955 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 956 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 957 if (stats) 958 hw_stats->tx_bytes += (stats << 32); 959 hw_stats->tx_packets += 960 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 961 } 962 963 u64_stats_update_end(&hw_stats->syncp); 964 } 965 966 static void mtk_stats_update(struct mtk_eth *eth) 967 { 968 int i; 969 970 for (i = 0; i < MTK_MAC_COUNT; i++) { 971 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 972 continue; 973 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 974 mtk_stats_update_mac(eth->mac[i]); 975 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 976 } 977 } 978 } 979 980 static void mtk_get_stats64(struct net_device *dev, 981 struct rtnl_link_stats64 *storage) 982 { 983 struct mtk_mac *mac = netdev_priv(dev); 984 struct mtk_hw_stats *hw_stats = mac->hw_stats; 985 unsigned int start; 986 987 if (netif_running(dev) && netif_device_present(dev)) { 988 if (spin_trylock_bh(&hw_stats->stats_lock)) { 989 mtk_stats_update_mac(mac); 990 spin_unlock_bh(&hw_stats->stats_lock); 991 } 992 } 993 994 do { 995 start = u64_stats_fetch_begin(&hw_stats->syncp); 996 storage->rx_packets = hw_stats->rx_packets; 997 storage->tx_packets = hw_stats->tx_packets; 998 storage->rx_bytes = hw_stats->rx_bytes; 999 storage->tx_bytes = hw_stats->tx_bytes; 1000 storage->collisions = hw_stats->tx_collisions; 1001 storage->rx_length_errors = hw_stats->rx_short_errors + 1002 hw_stats->rx_long_errors; 1003 storage->rx_over_errors = hw_stats->rx_overflow; 1004 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1005 storage->rx_errors = hw_stats->rx_checksum_errors; 1006 storage->tx_aborted_errors = hw_stats->tx_skip; 1007 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1008 1009 storage->tx_errors = dev->stats.tx_errors; 1010 storage->rx_dropped = dev->stats.rx_dropped; 1011 storage->tx_dropped = dev->stats.tx_dropped; 1012 } 1013 1014 static inline int mtk_max_frag_size(int mtu) 1015 { 1016 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1017 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1018 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1019 1020 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1021 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1022 } 1023 1024 static inline int mtk_max_buf_size(int frag_size) 1025 { 1026 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1027 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1028 1029 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1030 1031 return buf_size; 1032 } 1033 1034 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1035 struct mtk_rx_dma_v2 *dma_rxd) 1036 { 1037 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1038 if (!(rxd->rxd2 & RX_DMA_DONE)) 1039 return false; 1040 1041 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1042 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1043 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1044 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1045 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1046 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1047 } 1048 1049 return true; 1050 } 1051 1052 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1053 { 1054 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1055 unsigned long data; 1056 1057 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1058 get_order(size)); 1059 1060 return (void *)data; 1061 } 1062 1063 /* the qdma core needs scratch memory to be setup */ 1064 static int mtk_init_fq_dma(struct mtk_eth *eth) 1065 { 1066 const struct mtk_soc_data *soc = eth->soc; 1067 dma_addr_t phy_ring_tail; 1068 int cnt = MTK_QDMA_RING_SIZE; 1069 dma_addr_t dma_addr; 1070 int i; 1071 1072 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1073 cnt * soc->txrx.txd_size, 1074 ð->phy_scratch_ring, 1075 GFP_KERNEL); 1076 if (unlikely(!eth->scratch_ring)) 1077 return -ENOMEM; 1078 1079 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1080 if (unlikely(!eth->scratch_head)) 1081 return -ENOMEM; 1082 1083 dma_addr = dma_map_single(eth->dma_dev, 1084 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1085 DMA_FROM_DEVICE); 1086 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1087 return -ENOMEM; 1088 1089 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1090 1091 for (i = 0; i < cnt; i++) { 1092 struct mtk_tx_dma_v2 *txd; 1093 1094 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1095 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1096 if (i < cnt - 1) 1097 txd->txd2 = eth->phy_scratch_ring + 1098 (i + 1) * soc->txrx.txd_size; 1099 1100 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1101 txd->txd4 = 0; 1102 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1103 txd->txd5 = 0; 1104 txd->txd6 = 0; 1105 txd->txd7 = 0; 1106 txd->txd8 = 0; 1107 } 1108 } 1109 1110 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1111 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1112 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1113 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1114 1115 return 0; 1116 } 1117 1118 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1119 { 1120 return ring->dma + (desc - ring->phys); 1121 } 1122 1123 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1124 void *txd, u32 txd_size) 1125 { 1126 int idx = (txd - ring->dma) / txd_size; 1127 1128 return &ring->buf[idx]; 1129 } 1130 1131 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1132 struct mtk_tx_dma *dma) 1133 { 1134 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1135 } 1136 1137 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1138 { 1139 return (dma - ring->dma) / txd_size; 1140 } 1141 1142 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1143 struct xdp_frame_bulk *bq, bool napi) 1144 { 1145 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1146 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1147 dma_unmap_single(eth->dma_dev, 1148 dma_unmap_addr(tx_buf, dma_addr0), 1149 dma_unmap_len(tx_buf, dma_len0), 1150 DMA_TO_DEVICE); 1151 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1152 dma_unmap_page(eth->dma_dev, 1153 dma_unmap_addr(tx_buf, dma_addr0), 1154 dma_unmap_len(tx_buf, dma_len0), 1155 DMA_TO_DEVICE); 1156 } 1157 } else { 1158 if (dma_unmap_len(tx_buf, dma_len0)) { 1159 dma_unmap_page(eth->dma_dev, 1160 dma_unmap_addr(tx_buf, dma_addr0), 1161 dma_unmap_len(tx_buf, dma_len0), 1162 DMA_TO_DEVICE); 1163 } 1164 1165 if (dma_unmap_len(tx_buf, dma_len1)) { 1166 dma_unmap_page(eth->dma_dev, 1167 dma_unmap_addr(tx_buf, dma_addr1), 1168 dma_unmap_len(tx_buf, dma_len1), 1169 DMA_TO_DEVICE); 1170 } 1171 } 1172 1173 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1174 if (tx_buf->type == MTK_TYPE_SKB) { 1175 struct sk_buff *skb = tx_buf->data; 1176 1177 if (napi) 1178 napi_consume_skb(skb, napi); 1179 else 1180 dev_kfree_skb_any(skb); 1181 } else { 1182 struct xdp_frame *xdpf = tx_buf->data; 1183 1184 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1185 xdp_return_frame_rx_napi(xdpf); 1186 else if (bq) 1187 xdp_return_frame_bulk(xdpf, bq); 1188 else 1189 xdp_return_frame(xdpf); 1190 } 1191 } 1192 tx_buf->flags = 0; 1193 tx_buf->data = NULL; 1194 } 1195 1196 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1197 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1198 size_t size, int idx) 1199 { 1200 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1201 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1202 dma_unmap_len_set(tx_buf, dma_len0, size); 1203 } else { 1204 if (idx & 1) { 1205 txd->txd3 = mapped_addr; 1206 txd->txd2 |= TX_DMA_PLEN1(size); 1207 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1208 dma_unmap_len_set(tx_buf, dma_len1, size); 1209 } else { 1210 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1211 txd->txd1 = mapped_addr; 1212 txd->txd2 = TX_DMA_PLEN0(size); 1213 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1214 dma_unmap_len_set(tx_buf, dma_len0, size); 1215 } 1216 } 1217 } 1218 1219 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1220 struct mtk_tx_dma_desc_info *info) 1221 { 1222 struct mtk_mac *mac = netdev_priv(dev); 1223 struct mtk_eth *eth = mac->hw; 1224 struct mtk_tx_dma *desc = txd; 1225 u32 data; 1226 1227 WRITE_ONCE(desc->txd1, info->addr); 1228 1229 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1230 FIELD_PREP(TX_DMA_PQID, info->qid); 1231 if (info->last) 1232 data |= TX_DMA_LS0; 1233 WRITE_ONCE(desc->txd3, data); 1234 1235 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1236 if (info->first) { 1237 if (info->gso) 1238 data |= TX_DMA_TSO; 1239 /* tx checksum offload */ 1240 if (info->csum) 1241 data |= TX_DMA_CHKSUM; 1242 /* vlan header offload */ 1243 if (info->vlan) 1244 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1245 } 1246 WRITE_ONCE(desc->txd4, data); 1247 } 1248 1249 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1250 struct mtk_tx_dma_desc_info *info) 1251 { 1252 struct mtk_mac *mac = netdev_priv(dev); 1253 struct mtk_tx_dma_v2 *desc = txd; 1254 struct mtk_eth *eth = mac->hw; 1255 u32 data; 1256 1257 WRITE_ONCE(desc->txd1, info->addr); 1258 1259 data = TX_DMA_PLEN0(info->size); 1260 if (info->last) 1261 data |= TX_DMA_LS0; 1262 WRITE_ONCE(desc->txd3, data); 1263 1264 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1265 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1266 WRITE_ONCE(desc->txd4, data); 1267 1268 data = 0; 1269 if (info->first) { 1270 if (info->gso) 1271 data |= TX_DMA_TSO_V2; 1272 /* tx checksum offload */ 1273 if (info->csum) 1274 data |= TX_DMA_CHKSUM_V2; 1275 } 1276 WRITE_ONCE(desc->txd5, data); 1277 1278 data = 0; 1279 if (info->first && info->vlan) 1280 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1281 WRITE_ONCE(desc->txd6, data); 1282 1283 WRITE_ONCE(desc->txd7, 0); 1284 WRITE_ONCE(desc->txd8, 0); 1285 } 1286 1287 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1288 struct mtk_tx_dma_desc_info *info) 1289 { 1290 struct mtk_mac *mac = netdev_priv(dev); 1291 struct mtk_eth *eth = mac->hw; 1292 1293 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1294 mtk_tx_set_dma_desc_v2(dev, txd, info); 1295 else 1296 mtk_tx_set_dma_desc_v1(dev, txd, info); 1297 } 1298 1299 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1300 int tx_num, struct mtk_tx_ring *ring, bool gso) 1301 { 1302 struct mtk_tx_dma_desc_info txd_info = { 1303 .size = skb_headlen(skb), 1304 .gso = gso, 1305 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1306 .vlan = skb_vlan_tag_present(skb), 1307 .qid = skb_get_queue_mapping(skb), 1308 .vlan_tci = skb_vlan_tag_get(skb), 1309 .first = true, 1310 .last = !skb_is_nonlinear(skb), 1311 }; 1312 struct netdev_queue *txq; 1313 struct mtk_mac *mac = netdev_priv(dev); 1314 struct mtk_eth *eth = mac->hw; 1315 const struct mtk_soc_data *soc = eth->soc; 1316 struct mtk_tx_dma *itxd, *txd; 1317 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1318 struct mtk_tx_buf *itx_buf, *tx_buf; 1319 int i, n_desc = 1; 1320 int queue = skb_get_queue_mapping(skb); 1321 int k = 0; 1322 1323 txq = netdev_get_tx_queue(dev, queue); 1324 itxd = ring->next_free; 1325 itxd_pdma = qdma_to_pdma(ring, itxd); 1326 if (itxd == ring->last_free) 1327 return -ENOMEM; 1328 1329 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1330 memset(itx_buf, 0, sizeof(*itx_buf)); 1331 1332 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1333 DMA_TO_DEVICE); 1334 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1335 return -ENOMEM; 1336 1337 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1338 1339 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1340 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1341 MTK_TX_FLAGS_FPORT1; 1342 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1343 k++); 1344 1345 /* TX SG offload */ 1346 txd = itxd; 1347 txd_pdma = qdma_to_pdma(ring, txd); 1348 1349 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1350 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1351 unsigned int offset = 0; 1352 int frag_size = skb_frag_size(frag); 1353 1354 while (frag_size) { 1355 bool new_desc = true; 1356 1357 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1358 (i & 0x1)) { 1359 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1360 txd_pdma = qdma_to_pdma(ring, txd); 1361 if (txd == ring->last_free) 1362 goto err_dma; 1363 1364 n_desc++; 1365 } else { 1366 new_desc = false; 1367 } 1368 1369 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1370 txd_info.size = min_t(unsigned int, frag_size, 1371 soc->txrx.dma_max_len); 1372 txd_info.qid = queue; 1373 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1374 !(frag_size - txd_info.size); 1375 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1376 offset, txd_info.size, 1377 DMA_TO_DEVICE); 1378 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1379 goto err_dma; 1380 1381 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1382 1383 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1384 soc->txrx.txd_size); 1385 if (new_desc) 1386 memset(tx_buf, 0, sizeof(*tx_buf)); 1387 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1388 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1389 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1390 MTK_TX_FLAGS_FPORT1; 1391 1392 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1393 txd_info.size, k++); 1394 1395 frag_size -= txd_info.size; 1396 offset += txd_info.size; 1397 } 1398 } 1399 1400 /* store skb to cleanup */ 1401 itx_buf->type = MTK_TYPE_SKB; 1402 itx_buf->data = skb; 1403 1404 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1405 if (k & 0x1) 1406 txd_pdma->txd2 |= TX_DMA_LS0; 1407 else 1408 txd_pdma->txd2 |= TX_DMA_LS1; 1409 } 1410 1411 netdev_tx_sent_queue(txq, skb->len); 1412 skb_tx_timestamp(skb); 1413 1414 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1415 atomic_sub(n_desc, &ring->free_count); 1416 1417 /* make sure that all changes to the dma ring are flushed before we 1418 * continue 1419 */ 1420 wmb(); 1421 1422 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1423 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1424 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1425 } else { 1426 int next_idx; 1427 1428 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1429 ring->dma_size); 1430 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1431 } 1432 1433 return 0; 1434 1435 err_dma: 1436 do { 1437 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1438 1439 /* unmap dma */ 1440 mtk_tx_unmap(eth, tx_buf, NULL, false); 1441 1442 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1443 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1444 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1445 1446 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1447 itxd_pdma = qdma_to_pdma(ring, itxd); 1448 } while (itxd != txd); 1449 1450 return -ENOMEM; 1451 } 1452 1453 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1454 { 1455 int i, nfrags = 1; 1456 skb_frag_t *frag; 1457 1458 if (skb_is_gso(skb)) { 1459 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1460 frag = &skb_shinfo(skb)->frags[i]; 1461 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1462 eth->soc->txrx.dma_max_len); 1463 } 1464 } else { 1465 nfrags += skb_shinfo(skb)->nr_frags; 1466 } 1467 1468 return nfrags; 1469 } 1470 1471 static int mtk_queue_stopped(struct mtk_eth *eth) 1472 { 1473 int i; 1474 1475 for (i = 0; i < MTK_MAC_COUNT; i++) { 1476 if (!eth->netdev[i]) 1477 continue; 1478 if (netif_queue_stopped(eth->netdev[i])) 1479 return 1; 1480 } 1481 1482 return 0; 1483 } 1484 1485 static void mtk_wake_queue(struct mtk_eth *eth) 1486 { 1487 int i; 1488 1489 for (i = 0; i < MTK_MAC_COUNT; i++) { 1490 if (!eth->netdev[i]) 1491 continue; 1492 netif_tx_wake_all_queues(eth->netdev[i]); 1493 } 1494 } 1495 1496 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1497 { 1498 struct mtk_mac *mac = netdev_priv(dev); 1499 struct mtk_eth *eth = mac->hw; 1500 struct mtk_tx_ring *ring = ð->tx_ring; 1501 struct net_device_stats *stats = &dev->stats; 1502 bool gso = false; 1503 int tx_num; 1504 1505 /* normally we can rely on the stack not calling this more than once, 1506 * however we have 2 queues running on the same ring so we need to lock 1507 * the ring access 1508 */ 1509 spin_lock(ð->page_lock); 1510 1511 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1512 goto drop; 1513 1514 tx_num = mtk_cal_txd_req(eth, skb); 1515 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1516 netif_tx_stop_all_queues(dev); 1517 netif_err(eth, tx_queued, dev, 1518 "Tx Ring full when queue awake!\n"); 1519 spin_unlock(ð->page_lock); 1520 return NETDEV_TX_BUSY; 1521 } 1522 1523 /* TSO: fill MSS info in tcp checksum field */ 1524 if (skb_is_gso(skb)) { 1525 if (skb_cow_head(skb, 0)) { 1526 netif_warn(eth, tx_err, dev, 1527 "GSO expand head fail.\n"); 1528 goto drop; 1529 } 1530 1531 if (skb_shinfo(skb)->gso_type & 1532 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1533 gso = true; 1534 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1535 } 1536 } 1537 1538 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1539 goto drop; 1540 1541 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1542 netif_tx_stop_all_queues(dev); 1543 1544 spin_unlock(ð->page_lock); 1545 1546 return NETDEV_TX_OK; 1547 1548 drop: 1549 spin_unlock(ð->page_lock); 1550 stats->tx_dropped++; 1551 dev_kfree_skb_any(skb); 1552 return NETDEV_TX_OK; 1553 } 1554 1555 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1556 { 1557 int i; 1558 struct mtk_rx_ring *ring; 1559 int idx; 1560 1561 if (!eth->hwlro) 1562 return ð->rx_ring[0]; 1563 1564 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1565 struct mtk_rx_dma *rxd; 1566 1567 ring = ð->rx_ring[i]; 1568 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1569 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1570 if (rxd->rxd2 & RX_DMA_DONE) { 1571 ring->calc_idx_update = true; 1572 return ring; 1573 } 1574 } 1575 1576 return NULL; 1577 } 1578 1579 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1580 { 1581 struct mtk_rx_ring *ring; 1582 int i; 1583 1584 if (!eth->hwlro) { 1585 ring = ð->rx_ring[0]; 1586 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1587 } else { 1588 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1589 ring = ð->rx_ring[i]; 1590 if (ring->calc_idx_update) { 1591 ring->calc_idx_update = false; 1592 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1593 } 1594 } 1595 } 1596 } 1597 1598 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1599 { 1600 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1601 } 1602 1603 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1604 struct xdp_rxq_info *xdp_q, 1605 int id, int size) 1606 { 1607 struct page_pool_params pp_params = { 1608 .order = 0, 1609 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1610 .pool_size = size, 1611 .nid = NUMA_NO_NODE, 1612 .dev = eth->dma_dev, 1613 .offset = MTK_PP_HEADROOM, 1614 .max_len = MTK_PP_MAX_BUF_SIZE, 1615 }; 1616 struct page_pool *pp; 1617 int err; 1618 1619 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1620 : DMA_FROM_DEVICE; 1621 pp = page_pool_create(&pp_params); 1622 if (IS_ERR(pp)) 1623 return pp; 1624 1625 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1626 eth->rx_napi.napi_id, PAGE_SIZE); 1627 if (err < 0) 1628 goto err_free_pp; 1629 1630 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1631 if (err) 1632 goto err_unregister_rxq; 1633 1634 return pp; 1635 1636 err_unregister_rxq: 1637 xdp_rxq_info_unreg(xdp_q); 1638 err_free_pp: 1639 page_pool_destroy(pp); 1640 1641 return ERR_PTR(err); 1642 } 1643 1644 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1645 gfp_t gfp_mask) 1646 { 1647 struct page *page; 1648 1649 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1650 if (!page) 1651 return NULL; 1652 1653 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1654 return page_address(page); 1655 } 1656 1657 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1658 { 1659 if (ring->page_pool) 1660 page_pool_put_full_page(ring->page_pool, 1661 virt_to_head_page(data), napi); 1662 else 1663 skb_free_frag(data); 1664 } 1665 1666 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1667 struct mtk_tx_dma_desc_info *txd_info, 1668 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1669 void *data, u16 headroom, int index, bool dma_map) 1670 { 1671 struct mtk_tx_ring *ring = ð->tx_ring; 1672 struct mtk_mac *mac = netdev_priv(dev); 1673 struct mtk_tx_dma *txd_pdma; 1674 1675 if (dma_map) { /* ndo_xdp_xmit */ 1676 txd_info->addr = dma_map_single(eth->dma_dev, data, 1677 txd_info->size, DMA_TO_DEVICE); 1678 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1679 return -ENOMEM; 1680 1681 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1682 } else { 1683 struct page *page = virt_to_head_page(data); 1684 1685 txd_info->addr = page_pool_get_dma_addr(page) + 1686 sizeof(struct xdp_frame) + headroom; 1687 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1688 txd_info->size, DMA_BIDIRECTIONAL); 1689 } 1690 mtk_tx_set_dma_desc(dev, txd, txd_info); 1691 1692 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1693 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1694 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1695 1696 txd_pdma = qdma_to_pdma(ring, txd); 1697 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1698 index); 1699 1700 return 0; 1701 } 1702 1703 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1704 struct net_device *dev, bool dma_map) 1705 { 1706 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1707 const struct mtk_soc_data *soc = eth->soc; 1708 struct mtk_tx_ring *ring = ð->tx_ring; 1709 struct mtk_mac *mac = netdev_priv(dev); 1710 struct mtk_tx_dma_desc_info txd_info = { 1711 .size = xdpf->len, 1712 .first = true, 1713 .last = !xdp_frame_has_frags(xdpf), 1714 .qid = mac->id, 1715 }; 1716 int err, index = 0, n_desc = 1, nr_frags; 1717 struct mtk_tx_buf *htx_buf, *tx_buf; 1718 struct mtk_tx_dma *htxd, *txd; 1719 void *data = xdpf->data; 1720 1721 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1722 return -EBUSY; 1723 1724 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1725 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1726 return -EBUSY; 1727 1728 spin_lock(ð->page_lock); 1729 1730 txd = ring->next_free; 1731 if (txd == ring->last_free) { 1732 spin_unlock(ð->page_lock); 1733 return -ENOMEM; 1734 } 1735 htxd = txd; 1736 1737 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1738 memset(tx_buf, 0, sizeof(*tx_buf)); 1739 htx_buf = tx_buf; 1740 1741 for (;;) { 1742 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1743 data, xdpf->headroom, index, dma_map); 1744 if (err < 0) 1745 goto unmap; 1746 1747 if (txd_info.last) 1748 break; 1749 1750 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1751 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1752 if (txd == ring->last_free) 1753 goto unmap; 1754 1755 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1756 soc->txrx.txd_size); 1757 memset(tx_buf, 0, sizeof(*tx_buf)); 1758 n_desc++; 1759 } 1760 1761 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1762 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1763 txd_info.last = index + 1 == nr_frags; 1764 txd_info.qid = mac->id; 1765 data = skb_frag_address(&sinfo->frags[index]); 1766 1767 index++; 1768 } 1769 /* store xdpf for cleanup */ 1770 htx_buf->data = xdpf; 1771 1772 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1773 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1774 1775 if (index & 1) 1776 txd_pdma->txd2 |= TX_DMA_LS0; 1777 else 1778 txd_pdma->txd2 |= TX_DMA_LS1; 1779 } 1780 1781 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1782 atomic_sub(n_desc, &ring->free_count); 1783 1784 /* make sure that all changes to the dma ring are flushed before we 1785 * continue 1786 */ 1787 wmb(); 1788 1789 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1790 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1791 } else { 1792 int idx; 1793 1794 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1795 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1796 MT7628_TX_CTX_IDX0); 1797 } 1798 1799 spin_unlock(ð->page_lock); 1800 1801 return 0; 1802 1803 unmap: 1804 while (htxd != txd) { 1805 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1806 mtk_tx_unmap(eth, tx_buf, NULL, false); 1807 1808 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1809 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1810 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1811 1812 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1813 } 1814 1815 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1816 } 1817 1818 spin_unlock(ð->page_lock); 1819 1820 return err; 1821 } 1822 1823 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1824 struct xdp_frame **frames, u32 flags) 1825 { 1826 struct mtk_mac *mac = netdev_priv(dev); 1827 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1828 struct mtk_eth *eth = mac->hw; 1829 int i, nxmit = 0; 1830 1831 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1832 return -EINVAL; 1833 1834 for (i = 0; i < num_frame; i++) { 1835 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1836 break; 1837 nxmit++; 1838 } 1839 1840 u64_stats_update_begin(&hw_stats->syncp); 1841 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1842 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1843 u64_stats_update_end(&hw_stats->syncp); 1844 1845 return nxmit; 1846 } 1847 1848 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1849 struct xdp_buff *xdp, struct net_device *dev) 1850 { 1851 struct mtk_mac *mac = netdev_priv(dev); 1852 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1853 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1854 struct bpf_prog *prog; 1855 u32 act = XDP_PASS; 1856 1857 rcu_read_lock(); 1858 1859 prog = rcu_dereference(eth->prog); 1860 if (!prog) 1861 goto out; 1862 1863 act = bpf_prog_run_xdp(prog, xdp); 1864 switch (act) { 1865 case XDP_PASS: 1866 count = &hw_stats->xdp_stats.rx_xdp_pass; 1867 goto update_stats; 1868 case XDP_REDIRECT: 1869 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1870 act = XDP_DROP; 1871 break; 1872 } 1873 1874 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1875 goto update_stats; 1876 case XDP_TX: { 1877 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1878 1879 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1880 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1881 act = XDP_DROP; 1882 break; 1883 } 1884 1885 count = &hw_stats->xdp_stats.rx_xdp_tx; 1886 goto update_stats; 1887 } 1888 default: 1889 bpf_warn_invalid_xdp_action(dev, prog, act); 1890 fallthrough; 1891 case XDP_ABORTED: 1892 trace_xdp_exception(dev, prog, act); 1893 fallthrough; 1894 case XDP_DROP: 1895 break; 1896 } 1897 1898 page_pool_put_full_page(ring->page_pool, 1899 virt_to_head_page(xdp->data), true); 1900 1901 update_stats: 1902 u64_stats_update_begin(&hw_stats->syncp); 1903 *count = *count + 1; 1904 u64_stats_update_end(&hw_stats->syncp); 1905 out: 1906 rcu_read_unlock(); 1907 1908 return act; 1909 } 1910 1911 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1912 struct mtk_eth *eth) 1913 { 1914 struct dim_sample dim_sample = {}; 1915 struct mtk_rx_ring *ring; 1916 bool xdp_flush = false; 1917 int idx; 1918 struct sk_buff *skb; 1919 u8 *data, *new_data; 1920 struct mtk_rx_dma_v2 *rxd, trxd; 1921 int done = 0, bytes = 0; 1922 1923 while (done < budget) { 1924 unsigned int pktlen, *rxdcsum; 1925 bool has_hwaccel_tag = false; 1926 struct net_device *netdev; 1927 u16 vlan_proto, vlan_tci; 1928 dma_addr_t dma_addr; 1929 u32 hash, reason; 1930 int mac = 0; 1931 1932 ring = mtk_get_rx_ring(eth); 1933 if (unlikely(!ring)) 1934 goto rx_done; 1935 1936 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1937 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1938 data = ring->data[idx]; 1939 1940 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1941 break; 1942 1943 /* find out which mac the packet come from. values start at 1 */ 1944 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1945 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1946 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1947 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1948 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1949 1950 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1951 !eth->netdev[mac])) 1952 goto release_desc; 1953 1954 netdev = eth->netdev[mac]; 1955 1956 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1957 goto release_desc; 1958 1959 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1960 1961 /* alloc new buffer */ 1962 if (ring->page_pool) { 1963 struct page *page = virt_to_head_page(data); 1964 struct xdp_buff xdp; 1965 u32 ret; 1966 1967 new_data = mtk_page_pool_get_buff(ring->page_pool, 1968 &dma_addr, 1969 GFP_ATOMIC); 1970 if (unlikely(!new_data)) { 1971 netdev->stats.rx_dropped++; 1972 goto release_desc; 1973 } 1974 1975 dma_sync_single_for_cpu(eth->dma_dev, 1976 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1977 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1978 1979 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1980 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1981 false); 1982 xdp_buff_clear_frags_flag(&xdp); 1983 1984 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1985 if (ret == XDP_REDIRECT) 1986 xdp_flush = true; 1987 1988 if (ret != XDP_PASS) 1989 goto skip_rx; 1990 1991 skb = build_skb(data, PAGE_SIZE); 1992 if (unlikely(!skb)) { 1993 page_pool_put_full_page(ring->page_pool, 1994 page, true); 1995 netdev->stats.rx_dropped++; 1996 goto skip_rx; 1997 } 1998 1999 skb_reserve(skb, xdp.data - xdp.data_hard_start); 2000 skb_put(skb, xdp.data_end - xdp.data); 2001 skb_mark_for_recycle(skb); 2002 } else { 2003 if (ring->frag_size <= PAGE_SIZE) 2004 new_data = napi_alloc_frag(ring->frag_size); 2005 else 2006 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2007 2008 if (unlikely(!new_data)) { 2009 netdev->stats.rx_dropped++; 2010 goto release_desc; 2011 } 2012 2013 dma_addr = dma_map_single(eth->dma_dev, 2014 new_data + NET_SKB_PAD + eth->ip_align, 2015 ring->buf_size, DMA_FROM_DEVICE); 2016 if (unlikely(dma_mapping_error(eth->dma_dev, 2017 dma_addr))) { 2018 skb_free_frag(new_data); 2019 netdev->stats.rx_dropped++; 2020 goto release_desc; 2021 } 2022 2023 dma_unmap_single(eth->dma_dev, trxd.rxd1, 2024 ring->buf_size, DMA_FROM_DEVICE); 2025 2026 skb = build_skb(data, ring->frag_size); 2027 if (unlikely(!skb)) { 2028 netdev->stats.rx_dropped++; 2029 skb_free_frag(data); 2030 goto skip_rx; 2031 } 2032 2033 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2034 skb_put(skb, pktlen); 2035 } 2036 2037 skb->dev = netdev; 2038 bytes += skb->len; 2039 2040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2041 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2042 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2043 if (hash != MTK_RXD5_FOE_ENTRY) 2044 skb_set_hash(skb, jhash_1word(hash, 0), 2045 PKT_HASH_TYPE_L4); 2046 rxdcsum = &trxd.rxd3; 2047 } else { 2048 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2049 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2050 if (hash != MTK_RXD4_FOE_ENTRY) 2051 skb_set_hash(skb, jhash_1word(hash, 0), 2052 PKT_HASH_TYPE_L4); 2053 rxdcsum = &trxd.rxd4; 2054 } 2055 2056 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2057 skb->ip_summed = CHECKSUM_UNNECESSARY; 2058 else 2059 skb_checksum_none_assert(skb); 2060 skb->protocol = eth_type_trans(skb, netdev); 2061 2062 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2063 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2064 2065 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) { 2066 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2067 if (trxd.rxd3 & RX_DMA_VTAG_V2) { 2068 vlan_proto = RX_DMA_VPID(trxd.rxd4); 2069 vlan_tci = RX_DMA_VID(trxd.rxd4); 2070 has_hwaccel_tag = true; 2071 } 2072 } else if (trxd.rxd2 & RX_DMA_VTAG) { 2073 vlan_proto = RX_DMA_VPID(trxd.rxd3); 2074 vlan_tci = RX_DMA_VID(trxd.rxd3); 2075 has_hwaccel_tag = true; 2076 } 2077 } 2078 2079 /* When using VLAN untagging in combination with DSA, the 2080 * hardware treats the MTK special tag as a VLAN and untags it. 2081 */ 2082 if (has_hwaccel_tag && netdev_uses_dsa(netdev)) { 2083 unsigned int port = vlan_proto & GENMASK(2, 0); 2084 2085 if (port < ARRAY_SIZE(eth->dsa_meta) && 2086 eth->dsa_meta[port]) 2087 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2088 } else if (has_hwaccel_tag) { 2089 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vlan_tci); 2090 } 2091 2092 skb_record_rx_queue(skb, 0); 2093 napi_gro_receive(napi, skb); 2094 2095 skip_rx: 2096 ring->data[idx] = new_data; 2097 rxd->rxd1 = (unsigned int)dma_addr; 2098 release_desc: 2099 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2100 rxd->rxd2 = RX_DMA_LSO; 2101 else 2102 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2103 2104 ring->calc_idx = idx; 2105 done++; 2106 } 2107 2108 rx_done: 2109 if (done) { 2110 /* make sure that all changes to the dma ring are flushed before 2111 * we continue 2112 */ 2113 wmb(); 2114 mtk_update_rx_cpu_idx(eth); 2115 } 2116 2117 eth->rx_packets += done; 2118 eth->rx_bytes += bytes; 2119 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2120 &dim_sample); 2121 net_dim(ð->rx_dim, dim_sample); 2122 2123 if (xdp_flush) 2124 xdp_do_flush_map(); 2125 2126 return done; 2127 } 2128 2129 struct mtk_poll_state { 2130 struct netdev_queue *txq; 2131 unsigned int total; 2132 unsigned int done; 2133 unsigned int bytes; 2134 }; 2135 2136 static void 2137 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2138 struct sk_buff *skb) 2139 { 2140 struct netdev_queue *txq; 2141 struct net_device *dev; 2142 unsigned int bytes = skb->len; 2143 2144 state->total++; 2145 eth->tx_packets++; 2146 eth->tx_bytes += bytes; 2147 2148 dev = eth->netdev[mac]; 2149 if (!dev) 2150 return; 2151 2152 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2153 if (state->txq == txq) { 2154 state->done++; 2155 state->bytes += bytes; 2156 return; 2157 } 2158 2159 if (state->txq) 2160 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2161 2162 state->txq = txq; 2163 state->done = 1; 2164 state->bytes = bytes; 2165 } 2166 2167 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2168 struct mtk_poll_state *state) 2169 { 2170 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2171 struct mtk_tx_ring *ring = ð->tx_ring; 2172 struct mtk_tx_buf *tx_buf; 2173 struct xdp_frame_bulk bq; 2174 struct mtk_tx_dma *desc; 2175 u32 cpu, dma; 2176 2177 cpu = ring->last_free_ptr; 2178 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2179 2180 desc = mtk_qdma_phys_to_virt(ring, cpu); 2181 xdp_frame_bulk_init(&bq); 2182 2183 while ((cpu != dma) && budget) { 2184 u32 next_cpu = desc->txd2; 2185 int mac = 0; 2186 2187 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2188 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2189 break; 2190 2191 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2192 eth->soc->txrx.txd_size); 2193 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2194 mac = 1; 2195 2196 if (!tx_buf->data) 2197 break; 2198 2199 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2200 if (tx_buf->type == MTK_TYPE_SKB) 2201 mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2202 2203 budget--; 2204 } 2205 mtk_tx_unmap(eth, tx_buf, &bq, true); 2206 2207 ring->last_free = desc; 2208 atomic_inc(&ring->free_count); 2209 2210 cpu = next_cpu; 2211 } 2212 xdp_flush_frame_bulk(&bq); 2213 2214 ring->last_free_ptr = cpu; 2215 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2216 2217 return budget; 2218 } 2219 2220 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2221 struct mtk_poll_state *state) 2222 { 2223 struct mtk_tx_ring *ring = ð->tx_ring; 2224 struct mtk_tx_buf *tx_buf; 2225 struct xdp_frame_bulk bq; 2226 struct mtk_tx_dma *desc; 2227 u32 cpu, dma; 2228 2229 cpu = ring->cpu_idx; 2230 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2231 xdp_frame_bulk_init(&bq); 2232 2233 while ((cpu != dma) && budget) { 2234 tx_buf = &ring->buf[cpu]; 2235 if (!tx_buf->data) 2236 break; 2237 2238 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2239 if (tx_buf->type == MTK_TYPE_SKB) 2240 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2241 budget--; 2242 } 2243 mtk_tx_unmap(eth, tx_buf, &bq, true); 2244 2245 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2246 ring->last_free = desc; 2247 atomic_inc(&ring->free_count); 2248 2249 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2250 } 2251 xdp_flush_frame_bulk(&bq); 2252 2253 ring->cpu_idx = cpu; 2254 2255 return budget; 2256 } 2257 2258 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2259 { 2260 struct mtk_tx_ring *ring = ð->tx_ring; 2261 struct dim_sample dim_sample = {}; 2262 struct mtk_poll_state state = {}; 2263 2264 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2265 budget = mtk_poll_tx_qdma(eth, budget, &state); 2266 else 2267 budget = mtk_poll_tx_pdma(eth, budget, &state); 2268 2269 if (state.txq) 2270 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2271 2272 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2273 &dim_sample); 2274 net_dim(ð->tx_dim, dim_sample); 2275 2276 if (mtk_queue_stopped(eth) && 2277 (atomic_read(&ring->free_count) > ring->thresh)) 2278 mtk_wake_queue(eth); 2279 2280 return state.total; 2281 } 2282 2283 static void mtk_handle_status_irq(struct mtk_eth *eth) 2284 { 2285 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2286 2287 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2288 mtk_stats_update(eth); 2289 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2290 MTK_INT_STATUS2); 2291 } 2292 } 2293 2294 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2295 { 2296 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2297 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2298 int tx_done = 0; 2299 2300 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2301 mtk_handle_status_irq(eth); 2302 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2303 tx_done = mtk_poll_tx(eth, budget); 2304 2305 if (unlikely(netif_msg_intr(eth))) { 2306 dev_info(eth->dev, 2307 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2308 mtk_r32(eth, reg_map->tx_irq_status), 2309 mtk_r32(eth, reg_map->tx_irq_mask)); 2310 } 2311 2312 if (tx_done == budget) 2313 return budget; 2314 2315 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2316 return budget; 2317 2318 if (napi_complete_done(napi, tx_done)) 2319 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2320 2321 return tx_done; 2322 } 2323 2324 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2325 { 2326 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2327 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2328 int rx_done_total = 0; 2329 2330 mtk_handle_status_irq(eth); 2331 2332 do { 2333 int rx_done; 2334 2335 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2336 reg_map->pdma.irq_status); 2337 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2338 rx_done_total += rx_done; 2339 2340 if (unlikely(netif_msg_intr(eth))) { 2341 dev_info(eth->dev, 2342 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2343 mtk_r32(eth, reg_map->pdma.irq_status), 2344 mtk_r32(eth, reg_map->pdma.irq_mask)); 2345 } 2346 2347 if (rx_done_total == budget) 2348 return budget; 2349 2350 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2351 eth->soc->txrx.rx_irq_done_mask); 2352 2353 if (napi_complete_done(napi, rx_done_total)) 2354 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2355 2356 return rx_done_total; 2357 } 2358 2359 static int mtk_tx_alloc(struct mtk_eth *eth) 2360 { 2361 const struct mtk_soc_data *soc = eth->soc; 2362 struct mtk_tx_ring *ring = ð->tx_ring; 2363 int i, sz = soc->txrx.txd_size; 2364 struct mtk_tx_dma_v2 *txd; 2365 int ring_size; 2366 u32 ofs, val; 2367 2368 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2369 ring_size = MTK_QDMA_RING_SIZE; 2370 else 2371 ring_size = MTK_DMA_SIZE; 2372 2373 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2374 GFP_KERNEL); 2375 if (!ring->buf) 2376 goto no_tx_mem; 2377 2378 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2379 &ring->phys, GFP_KERNEL); 2380 if (!ring->dma) 2381 goto no_tx_mem; 2382 2383 for (i = 0; i < ring_size; i++) { 2384 int next = (i + 1) % ring_size; 2385 u32 next_ptr = ring->phys + next * sz; 2386 2387 txd = ring->dma + i * sz; 2388 txd->txd2 = next_ptr; 2389 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2390 txd->txd4 = 0; 2391 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2392 txd->txd5 = 0; 2393 txd->txd6 = 0; 2394 txd->txd7 = 0; 2395 txd->txd8 = 0; 2396 } 2397 } 2398 2399 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2400 * only as the framework. The real HW descriptors are the PDMA 2401 * descriptors in ring->dma_pdma. 2402 */ 2403 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2404 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2405 &ring->phys_pdma, GFP_KERNEL); 2406 if (!ring->dma_pdma) 2407 goto no_tx_mem; 2408 2409 for (i = 0; i < ring_size; i++) { 2410 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2411 ring->dma_pdma[i].txd4 = 0; 2412 } 2413 } 2414 2415 ring->dma_size = ring_size; 2416 atomic_set(&ring->free_count, ring_size - 2); 2417 ring->next_free = ring->dma; 2418 ring->last_free = (void *)txd; 2419 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2420 ring->thresh = MAX_SKB_FRAGS; 2421 2422 /* make sure that all changes to the dma ring are flushed before we 2423 * continue 2424 */ 2425 wmb(); 2426 2427 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2428 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2429 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2430 mtk_w32(eth, 2431 ring->phys + ((ring_size - 1) * sz), 2432 soc->reg_map->qdma.crx_ptr); 2433 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2434 2435 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2436 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2437 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2438 2439 val = MTK_QTX_SCH_MIN_RATE_EN | 2440 /* minimum: 10 Mbps */ 2441 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2442 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2443 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2444 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2445 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2446 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2447 ofs += MTK_QTX_OFFSET; 2448 } 2449 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2450 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2451 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2452 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2453 } else { 2454 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2455 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2456 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2457 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2458 } 2459 2460 return 0; 2461 2462 no_tx_mem: 2463 return -ENOMEM; 2464 } 2465 2466 static void mtk_tx_clean(struct mtk_eth *eth) 2467 { 2468 const struct mtk_soc_data *soc = eth->soc; 2469 struct mtk_tx_ring *ring = ð->tx_ring; 2470 int i; 2471 2472 if (ring->buf) { 2473 for (i = 0; i < ring->dma_size; i++) 2474 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2475 kfree(ring->buf); 2476 ring->buf = NULL; 2477 } 2478 2479 if (ring->dma) { 2480 dma_free_coherent(eth->dma_dev, 2481 ring->dma_size * soc->txrx.txd_size, 2482 ring->dma, ring->phys); 2483 ring->dma = NULL; 2484 } 2485 2486 if (ring->dma_pdma) { 2487 dma_free_coherent(eth->dma_dev, 2488 ring->dma_size * soc->txrx.txd_size, 2489 ring->dma_pdma, ring->phys_pdma); 2490 ring->dma_pdma = NULL; 2491 } 2492 } 2493 2494 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2495 { 2496 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2497 struct mtk_rx_ring *ring; 2498 int rx_data_len, rx_dma_size; 2499 int i; 2500 2501 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2502 if (ring_no) 2503 return -EINVAL; 2504 ring = ð->rx_ring_qdma; 2505 } else { 2506 ring = ð->rx_ring[ring_no]; 2507 } 2508 2509 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2510 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2511 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2512 } else { 2513 rx_data_len = ETH_DATA_LEN; 2514 rx_dma_size = MTK_DMA_SIZE; 2515 } 2516 2517 ring->frag_size = mtk_max_frag_size(rx_data_len); 2518 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2519 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2520 GFP_KERNEL); 2521 if (!ring->data) 2522 return -ENOMEM; 2523 2524 if (mtk_page_pool_enabled(eth)) { 2525 struct page_pool *pp; 2526 2527 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2528 rx_dma_size); 2529 if (IS_ERR(pp)) 2530 return PTR_ERR(pp); 2531 2532 ring->page_pool = pp; 2533 } 2534 2535 ring->dma = dma_alloc_coherent(eth->dma_dev, 2536 rx_dma_size * eth->soc->txrx.rxd_size, 2537 &ring->phys, GFP_KERNEL); 2538 if (!ring->dma) 2539 return -ENOMEM; 2540 2541 for (i = 0; i < rx_dma_size; i++) { 2542 struct mtk_rx_dma_v2 *rxd; 2543 dma_addr_t dma_addr; 2544 void *data; 2545 2546 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2547 if (ring->page_pool) { 2548 data = mtk_page_pool_get_buff(ring->page_pool, 2549 &dma_addr, GFP_KERNEL); 2550 if (!data) 2551 return -ENOMEM; 2552 } else { 2553 if (ring->frag_size <= PAGE_SIZE) 2554 data = netdev_alloc_frag(ring->frag_size); 2555 else 2556 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2557 2558 if (!data) 2559 return -ENOMEM; 2560 2561 dma_addr = dma_map_single(eth->dma_dev, 2562 data + NET_SKB_PAD + eth->ip_align, 2563 ring->buf_size, DMA_FROM_DEVICE); 2564 if (unlikely(dma_mapping_error(eth->dma_dev, 2565 dma_addr))) { 2566 skb_free_frag(data); 2567 return -ENOMEM; 2568 } 2569 } 2570 rxd->rxd1 = (unsigned int)dma_addr; 2571 ring->data[i] = data; 2572 2573 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2574 rxd->rxd2 = RX_DMA_LSO; 2575 else 2576 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2577 2578 rxd->rxd3 = 0; 2579 rxd->rxd4 = 0; 2580 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2581 rxd->rxd5 = 0; 2582 rxd->rxd6 = 0; 2583 rxd->rxd7 = 0; 2584 rxd->rxd8 = 0; 2585 } 2586 } 2587 2588 ring->dma_size = rx_dma_size; 2589 ring->calc_idx_update = false; 2590 ring->calc_idx = rx_dma_size - 1; 2591 if (rx_flag == MTK_RX_FLAGS_QDMA) 2592 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2593 ring_no * MTK_QRX_OFFSET; 2594 else 2595 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2596 ring_no * MTK_QRX_OFFSET; 2597 /* make sure that all changes to the dma ring are flushed before we 2598 * continue 2599 */ 2600 wmb(); 2601 2602 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2603 mtk_w32(eth, ring->phys, 2604 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2605 mtk_w32(eth, rx_dma_size, 2606 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2607 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2608 reg_map->qdma.rst_idx); 2609 } else { 2610 mtk_w32(eth, ring->phys, 2611 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2612 mtk_w32(eth, rx_dma_size, 2613 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2614 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2615 reg_map->pdma.rst_idx); 2616 } 2617 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2618 2619 return 0; 2620 } 2621 2622 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2623 { 2624 int i; 2625 2626 if (ring->data && ring->dma) { 2627 for (i = 0; i < ring->dma_size; i++) { 2628 struct mtk_rx_dma *rxd; 2629 2630 if (!ring->data[i]) 2631 continue; 2632 2633 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2634 if (!rxd->rxd1) 2635 continue; 2636 2637 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2638 ring->buf_size, DMA_FROM_DEVICE); 2639 mtk_rx_put_buff(ring, ring->data[i], false); 2640 } 2641 kfree(ring->data); 2642 ring->data = NULL; 2643 } 2644 2645 if (ring->dma) { 2646 dma_free_coherent(eth->dma_dev, 2647 ring->dma_size * eth->soc->txrx.rxd_size, 2648 ring->dma, ring->phys); 2649 ring->dma = NULL; 2650 } 2651 2652 if (ring->page_pool) { 2653 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2654 xdp_rxq_info_unreg(&ring->xdp_q); 2655 page_pool_destroy(ring->page_pool); 2656 ring->page_pool = NULL; 2657 } 2658 } 2659 2660 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2661 { 2662 int i; 2663 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2664 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2665 2666 /* set LRO rings to auto-learn modes */ 2667 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2668 2669 /* validate LRO ring */ 2670 ring_ctrl_dw2 |= MTK_RING_VLD; 2671 2672 /* set AGE timer (unit: 20us) */ 2673 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2674 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2675 2676 /* set max AGG timer (unit: 20us) */ 2677 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2678 2679 /* set max LRO AGG count */ 2680 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2681 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2682 2683 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2684 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2685 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2686 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2687 } 2688 2689 /* IPv4 checksum update enable */ 2690 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2691 2692 /* switch priority comparison to packet count mode */ 2693 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2694 2695 /* bandwidth threshold setting */ 2696 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2697 2698 /* auto-learn score delta setting */ 2699 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2700 2701 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2702 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2703 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2704 2705 /* set HW LRO mode & the max aggregation count for rx packets */ 2706 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2707 2708 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2709 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2710 2711 /* enable HW LRO */ 2712 lro_ctrl_dw0 |= MTK_LRO_EN; 2713 2714 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2715 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2716 2717 return 0; 2718 } 2719 2720 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2721 { 2722 int i; 2723 u32 val; 2724 2725 /* relinquish lro rings, flush aggregated packets */ 2726 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2727 2728 /* wait for relinquishments done */ 2729 for (i = 0; i < 10; i++) { 2730 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2731 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2732 msleep(20); 2733 continue; 2734 } 2735 break; 2736 } 2737 2738 /* invalidate lro rings */ 2739 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2740 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2741 2742 /* disable HW LRO */ 2743 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2744 } 2745 2746 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2747 { 2748 u32 reg_val; 2749 2750 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2751 2752 /* invalidate the IP setting */ 2753 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2754 2755 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2756 2757 /* validate the IP setting */ 2758 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2759 } 2760 2761 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2762 { 2763 u32 reg_val; 2764 2765 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2766 2767 /* invalidate the IP setting */ 2768 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2769 2770 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2771 } 2772 2773 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2774 { 2775 int cnt = 0; 2776 int i; 2777 2778 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2779 if (mac->hwlro_ip[i]) 2780 cnt++; 2781 } 2782 2783 return cnt; 2784 } 2785 2786 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2787 struct ethtool_rxnfc *cmd) 2788 { 2789 struct ethtool_rx_flow_spec *fsp = 2790 (struct ethtool_rx_flow_spec *)&cmd->fs; 2791 struct mtk_mac *mac = netdev_priv(dev); 2792 struct mtk_eth *eth = mac->hw; 2793 int hwlro_idx; 2794 2795 if ((fsp->flow_type != TCP_V4_FLOW) || 2796 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2797 (fsp->location > 1)) 2798 return -EINVAL; 2799 2800 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2801 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2802 2803 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2804 2805 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2806 2807 return 0; 2808 } 2809 2810 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2811 struct ethtool_rxnfc *cmd) 2812 { 2813 struct ethtool_rx_flow_spec *fsp = 2814 (struct ethtool_rx_flow_spec *)&cmd->fs; 2815 struct mtk_mac *mac = netdev_priv(dev); 2816 struct mtk_eth *eth = mac->hw; 2817 int hwlro_idx; 2818 2819 if (fsp->location > 1) 2820 return -EINVAL; 2821 2822 mac->hwlro_ip[fsp->location] = 0; 2823 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2824 2825 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2826 2827 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2828 2829 return 0; 2830 } 2831 2832 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2833 { 2834 struct mtk_mac *mac = netdev_priv(dev); 2835 struct mtk_eth *eth = mac->hw; 2836 int i, hwlro_idx; 2837 2838 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2839 mac->hwlro_ip[i] = 0; 2840 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2841 2842 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2843 } 2844 2845 mac->hwlro_ip_cnt = 0; 2846 } 2847 2848 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2849 struct ethtool_rxnfc *cmd) 2850 { 2851 struct mtk_mac *mac = netdev_priv(dev); 2852 struct ethtool_rx_flow_spec *fsp = 2853 (struct ethtool_rx_flow_spec *)&cmd->fs; 2854 2855 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2856 return -EINVAL; 2857 2858 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2859 fsp->flow_type = TCP_V4_FLOW; 2860 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2861 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2862 2863 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2864 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2865 fsp->h_u.tcp_ip4_spec.psrc = 0; 2866 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2867 fsp->h_u.tcp_ip4_spec.pdst = 0; 2868 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2869 fsp->h_u.tcp_ip4_spec.tos = 0; 2870 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2871 2872 return 0; 2873 } 2874 2875 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2876 struct ethtool_rxnfc *cmd, 2877 u32 *rule_locs) 2878 { 2879 struct mtk_mac *mac = netdev_priv(dev); 2880 int cnt = 0; 2881 int i; 2882 2883 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2884 if (mac->hwlro_ip[i]) { 2885 rule_locs[cnt] = i; 2886 cnt++; 2887 } 2888 } 2889 2890 cmd->rule_cnt = cnt; 2891 2892 return 0; 2893 } 2894 2895 static netdev_features_t mtk_fix_features(struct net_device *dev, 2896 netdev_features_t features) 2897 { 2898 if (!(features & NETIF_F_LRO)) { 2899 struct mtk_mac *mac = netdev_priv(dev); 2900 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2901 2902 if (ip_cnt) { 2903 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2904 2905 features |= NETIF_F_LRO; 2906 } 2907 } 2908 2909 return features; 2910 } 2911 2912 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2913 { 2914 struct mtk_mac *mac = netdev_priv(dev); 2915 struct mtk_eth *eth = mac->hw; 2916 netdev_features_t diff = dev->features ^ features; 2917 int i; 2918 2919 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2920 mtk_hwlro_netdev_disable(dev); 2921 2922 /* Set RX VLAN offloading */ 2923 if (!(diff & NETIF_F_HW_VLAN_CTAG_RX)) 2924 return 0; 2925 2926 mtk_w32(eth, !!(features & NETIF_F_HW_VLAN_CTAG_RX), 2927 MTK_CDMP_EG_CTRL); 2928 2929 /* sync features with other MAC */ 2930 for (i = 0; i < MTK_MAC_COUNT; i++) { 2931 if (!eth->netdev[i] || eth->netdev[i] == dev) 2932 continue; 2933 eth->netdev[i]->features &= ~NETIF_F_HW_VLAN_CTAG_RX; 2934 eth->netdev[i]->features |= features & NETIF_F_HW_VLAN_CTAG_RX; 2935 } 2936 2937 return 0; 2938 } 2939 2940 /* wait for DMA to finish whatever it is doing before we start using it again */ 2941 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2942 { 2943 unsigned int reg; 2944 int ret; 2945 u32 val; 2946 2947 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2948 reg = eth->soc->reg_map->qdma.glo_cfg; 2949 else 2950 reg = eth->soc->reg_map->pdma.glo_cfg; 2951 2952 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2953 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2954 5, MTK_DMA_BUSY_TIMEOUT_US); 2955 if (ret) 2956 dev_err(eth->dev, "DMA init timeout\n"); 2957 2958 return ret; 2959 } 2960 2961 static int mtk_dma_init(struct mtk_eth *eth) 2962 { 2963 int err; 2964 u32 i; 2965 2966 if (mtk_dma_busy_wait(eth)) 2967 return -EBUSY; 2968 2969 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2970 /* QDMA needs scratch memory for internal reordering of the 2971 * descriptors 2972 */ 2973 err = mtk_init_fq_dma(eth); 2974 if (err) 2975 return err; 2976 } 2977 2978 err = mtk_tx_alloc(eth); 2979 if (err) 2980 return err; 2981 2982 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2983 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2984 if (err) 2985 return err; 2986 } 2987 2988 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2989 if (err) 2990 return err; 2991 2992 if (eth->hwlro) { 2993 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2994 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2995 if (err) 2996 return err; 2997 } 2998 err = mtk_hwlro_rx_init(eth); 2999 if (err) 3000 return err; 3001 } 3002 3003 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3004 /* Enable random early drop and set drop threshold 3005 * automatically 3006 */ 3007 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 3008 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 3009 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 3010 } 3011 3012 return 0; 3013 } 3014 3015 static void mtk_dma_free(struct mtk_eth *eth) 3016 { 3017 const struct mtk_soc_data *soc = eth->soc; 3018 int i; 3019 3020 for (i = 0; i < MTK_MAC_COUNT; i++) 3021 if (eth->netdev[i]) 3022 netdev_reset_queue(eth->netdev[i]); 3023 if (eth->scratch_ring) { 3024 dma_free_coherent(eth->dma_dev, 3025 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 3026 eth->scratch_ring, eth->phy_scratch_ring); 3027 eth->scratch_ring = NULL; 3028 eth->phy_scratch_ring = 0; 3029 } 3030 mtk_tx_clean(eth); 3031 mtk_rx_clean(eth, ð->rx_ring[0]); 3032 mtk_rx_clean(eth, ð->rx_ring_qdma); 3033 3034 if (eth->hwlro) { 3035 mtk_hwlro_rx_uninit(eth); 3036 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 3037 mtk_rx_clean(eth, ð->rx_ring[i]); 3038 } 3039 3040 kfree(eth->scratch_head); 3041 } 3042 3043 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3044 { 3045 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3046 3047 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3048 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3049 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3050 } 3051 3052 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3053 { 3054 struct mtk_mac *mac = netdev_priv(dev); 3055 struct mtk_eth *eth = mac->hw; 3056 3057 if (test_bit(MTK_RESETTING, ð->state)) 3058 return; 3059 3060 if (!mtk_hw_reset_check(eth)) 3061 return; 3062 3063 eth->netdev[mac->id]->stats.tx_errors++; 3064 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3065 3066 schedule_work(ð->pending_work); 3067 } 3068 3069 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3070 { 3071 struct mtk_eth *eth = _eth; 3072 3073 eth->rx_events++; 3074 if (likely(napi_schedule_prep(ð->rx_napi))) { 3075 __napi_schedule(ð->rx_napi); 3076 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3077 } 3078 3079 return IRQ_HANDLED; 3080 } 3081 3082 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3083 { 3084 struct mtk_eth *eth = _eth; 3085 3086 eth->tx_events++; 3087 if (likely(napi_schedule_prep(ð->tx_napi))) { 3088 __napi_schedule(ð->tx_napi); 3089 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3090 } 3091 3092 return IRQ_HANDLED; 3093 } 3094 3095 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3096 { 3097 struct mtk_eth *eth = _eth; 3098 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3099 3100 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3101 eth->soc->txrx.rx_irq_done_mask) { 3102 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3103 eth->soc->txrx.rx_irq_done_mask) 3104 mtk_handle_irq_rx(irq, _eth); 3105 } 3106 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3107 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3108 mtk_handle_irq_tx(irq, _eth); 3109 } 3110 3111 return IRQ_HANDLED; 3112 } 3113 3114 #ifdef CONFIG_NET_POLL_CONTROLLER 3115 static void mtk_poll_controller(struct net_device *dev) 3116 { 3117 struct mtk_mac *mac = netdev_priv(dev); 3118 struct mtk_eth *eth = mac->hw; 3119 3120 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3121 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3122 mtk_handle_irq_rx(eth->irq[2], dev); 3123 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3124 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3125 } 3126 #endif 3127 3128 static int mtk_start_dma(struct mtk_eth *eth) 3129 { 3130 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3131 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3132 int err; 3133 3134 err = mtk_dma_init(eth); 3135 if (err) { 3136 mtk_dma_free(eth); 3137 return err; 3138 } 3139 3140 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3141 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3142 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3143 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3144 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3145 3146 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3147 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3148 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3149 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3150 else 3151 val |= MTK_RX_BT_32DWORDS; 3152 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3153 3154 mtk_w32(eth, 3155 MTK_RX_DMA_EN | rx_2b_offset | 3156 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3157 reg_map->pdma.glo_cfg); 3158 } else { 3159 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3160 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3161 reg_map->pdma.glo_cfg); 3162 } 3163 3164 return 0; 3165 } 3166 3167 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3168 { 3169 int i; 3170 3171 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3172 return; 3173 3174 for (i = 0; i < MTK_MAC_COUNT; i++) { 3175 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3176 3177 /* default setup the forward port to send frame to PDMA */ 3178 val &= ~0xffff; 3179 3180 /* Enable RX checksum */ 3181 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3182 3183 val |= config; 3184 3185 if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) 3186 val |= MTK_GDMA_SPECIAL_TAG; 3187 3188 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3189 } 3190 /* Reset and enable PSE */ 3191 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3192 mtk_w32(eth, 0, MTK_RST_GL); 3193 } 3194 3195 3196 static bool mtk_uses_dsa(struct net_device *dev) 3197 { 3198 #if IS_ENABLED(CONFIG_NET_DSA) 3199 return netdev_uses_dsa(dev) && 3200 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3201 #else 3202 return false; 3203 #endif 3204 } 3205 3206 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3207 { 3208 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3209 struct mtk_eth *eth = mac->hw; 3210 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3211 struct ethtool_link_ksettings s; 3212 struct net_device *ldev; 3213 struct list_head *iter; 3214 struct dsa_port *dp; 3215 3216 if (event != NETDEV_CHANGE) 3217 return NOTIFY_DONE; 3218 3219 netdev_for_each_lower_dev(dev, ldev, iter) { 3220 if (netdev_priv(ldev) == mac) 3221 goto found; 3222 } 3223 3224 return NOTIFY_DONE; 3225 3226 found: 3227 if (!dsa_slave_dev_check(dev)) 3228 return NOTIFY_DONE; 3229 3230 if (__ethtool_get_link_ksettings(dev, &s)) 3231 return NOTIFY_DONE; 3232 3233 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3234 return NOTIFY_DONE; 3235 3236 dp = dsa_port_from_netdev(dev); 3237 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3238 return NOTIFY_DONE; 3239 3240 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3241 3242 return NOTIFY_DONE; 3243 } 3244 3245 static int mtk_open(struct net_device *dev) 3246 { 3247 struct mtk_mac *mac = netdev_priv(dev); 3248 struct mtk_eth *eth = mac->hw; 3249 int i, err; 3250 3251 if (mtk_uses_dsa(dev) && !eth->prog) { 3252 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3253 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3254 3255 if (md_dst) 3256 continue; 3257 3258 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3259 GFP_KERNEL); 3260 if (!md_dst) 3261 return -ENOMEM; 3262 3263 md_dst->u.port_info.port_id = i; 3264 eth->dsa_meta[i] = md_dst; 3265 } 3266 } else { 3267 /* Hardware special tag parsing needs to be disabled if at least 3268 * one MAC does not use DSA. 3269 */ 3270 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3271 val &= ~MTK_CDMP_STAG_EN; 3272 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3273 } 3274 3275 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3276 if (err) { 3277 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3278 err); 3279 return err; 3280 } 3281 3282 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3283 if (!refcount_read(ð->dma_refcnt)) { 3284 const struct mtk_soc_data *soc = eth->soc; 3285 u32 gdm_config; 3286 int i; 3287 3288 err = mtk_start_dma(eth); 3289 if (err) { 3290 phylink_disconnect_phy(mac->phylink); 3291 return err; 3292 } 3293 3294 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3295 mtk_ppe_start(eth->ppe[i]); 3296 3297 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3298 : MTK_GDMA_TO_PDMA; 3299 mtk_gdm_config(eth, gdm_config); 3300 3301 napi_enable(ð->tx_napi); 3302 napi_enable(ð->rx_napi); 3303 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3304 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3305 refcount_set(ð->dma_refcnt, 1); 3306 } 3307 else 3308 refcount_inc(ð->dma_refcnt); 3309 3310 phylink_start(mac->phylink); 3311 netif_tx_start_all_queues(dev); 3312 3313 return 0; 3314 } 3315 3316 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3317 { 3318 u32 val; 3319 int i; 3320 3321 /* stop the dma engine */ 3322 spin_lock_bh(ð->page_lock); 3323 val = mtk_r32(eth, glo_cfg); 3324 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3325 glo_cfg); 3326 spin_unlock_bh(ð->page_lock); 3327 3328 /* wait for dma stop */ 3329 for (i = 0; i < 10; i++) { 3330 val = mtk_r32(eth, glo_cfg); 3331 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3332 msleep(20); 3333 continue; 3334 } 3335 break; 3336 } 3337 } 3338 3339 static int mtk_stop(struct net_device *dev) 3340 { 3341 struct mtk_mac *mac = netdev_priv(dev); 3342 struct mtk_eth *eth = mac->hw; 3343 int i; 3344 3345 phylink_stop(mac->phylink); 3346 3347 netif_tx_disable(dev); 3348 3349 phylink_disconnect_phy(mac->phylink); 3350 3351 /* only shutdown DMA if this is the last user */ 3352 if (!refcount_dec_and_test(ð->dma_refcnt)) 3353 return 0; 3354 3355 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3356 3357 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3358 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3359 napi_disable(ð->tx_napi); 3360 napi_disable(ð->rx_napi); 3361 3362 cancel_work_sync(ð->rx_dim.work); 3363 cancel_work_sync(ð->tx_dim.work); 3364 3365 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3366 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3367 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3368 3369 mtk_dma_free(eth); 3370 3371 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3372 mtk_ppe_stop(eth->ppe[i]); 3373 3374 return 0; 3375 } 3376 3377 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3378 struct netlink_ext_ack *extack) 3379 { 3380 struct mtk_mac *mac = netdev_priv(dev); 3381 struct mtk_eth *eth = mac->hw; 3382 struct bpf_prog *old_prog; 3383 bool need_update; 3384 3385 if (eth->hwlro) { 3386 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3387 return -EOPNOTSUPP; 3388 } 3389 3390 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3391 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3392 return -EOPNOTSUPP; 3393 } 3394 3395 need_update = !!eth->prog != !!prog; 3396 if (netif_running(dev) && need_update) 3397 mtk_stop(dev); 3398 3399 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3400 if (old_prog) 3401 bpf_prog_put(old_prog); 3402 3403 if (netif_running(dev) && need_update) 3404 return mtk_open(dev); 3405 3406 return 0; 3407 } 3408 3409 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3410 { 3411 switch (xdp->command) { 3412 case XDP_SETUP_PROG: 3413 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3414 default: 3415 return -EINVAL; 3416 } 3417 } 3418 3419 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3420 { 3421 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3422 reset_bits, 3423 reset_bits); 3424 3425 usleep_range(1000, 1100); 3426 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3427 reset_bits, 3428 ~reset_bits); 3429 mdelay(10); 3430 } 3431 3432 static void mtk_clk_disable(struct mtk_eth *eth) 3433 { 3434 int clk; 3435 3436 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3437 clk_disable_unprepare(eth->clks[clk]); 3438 } 3439 3440 static int mtk_clk_enable(struct mtk_eth *eth) 3441 { 3442 int clk, ret; 3443 3444 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3445 ret = clk_prepare_enable(eth->clks[clk]); 3446 if (ret) 3447 goto err_disable_clks; 3448 } 3449 3450 return 0; 3451 3452 err_disable_clks: 3453 while (--clk >= 0) 3454 clk_disable_unprepare(eth->clks[clk]); 3455 3456 return ret; 3457 } 3458 3459 static void mtk_dim_rx(struct work_struct *work) 3460 { 3461 struct dim *dim = container_of(work, struct dim, work); 3462 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3463 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3464 struct dim_cq_moder cur_profile; 3465 u32 val, cur; 3466 3467 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3468 dim->profile_ix); 3469 spin_lock_bh(ð->dim_lock); 3470 3471 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3472 val &= MTK_PDMA_DELAY_TX_MASK; 3473 val |= MTK_PDMA_DELAY_RX_EN; 3474 3475 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3476 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3477 3478 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3479 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3480 3481 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3482 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3483 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3484 3485 spin_unlock_bh(ð->dim_lock); 3486 3487 dim->state = DIM_START_MEASURE; 3488 } 3489 3490 static void mtk_dim_tx(struct work_struct *work) 3491 { 3492 struct dim *dim = container_of(work, struct dim, work); 3493 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3494 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3495 struct dim_cq_moder cur_profile; 3496 u32 val, cur; 3497 3498 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3499 dim->profile_ix); 3500 spin_lock_bh(ð->dim_lock); 3501 3502 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3503 val &= MTK_PDMA_DELAY_RX_MASK; 3504 val |= MTK_PDMA_DELAY_TX_EN; 3505 3506 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3507 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3508 3509 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3510 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3511 3512 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3513 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3514 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3515 3516 spin_unlock_bh(ð->dim_lock); 3517 3518 dim->state = DIM_START_MEASURE; 3519 } 3520 3521 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3522 { 3523 struct mtk_eth *eth = mac->hw; 3524 u32 mcr_cur, mcr_new; 3525 3526 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3527 return; 3528 3529 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3530 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3531 3532 if (val <= 1518) 3533 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3534 else if (val <= 1536) 3535 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3536 else if (val <= 1552) 3537 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3538 else 3539 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3540 3541 if (mcr_new != mcr_cur) 3542 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3543 } 3544 3545 static void mtk_hw_reset(struct mtk_eth *eth) 3546 { 3547 u32 val; 3548 3549 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3550 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3551 val = RSTCTRL_PPE0_V2; 3552 } else { 3553 val = RSTCTRL_PPE0; 3554 } 3555 3556 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3557 val |= RSTCTRL_PPE1; 3558 3559 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3560 3561 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3562 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3563 0x3ffffff); 3564 } 3565 3566 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3567 { 3568 u32 val; 3569 3570 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3571 return val; 3572 } 3573 3574 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3575 { 3576 u32 rst_mask, val; 3577 3578 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3579 RSTCTRL_FE); 3580 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3581 val & RSTCTRL_FE, 1, 1000)) { 3582 dev_err(eth->dev, "warm reset failed\n"); 3583 mtk_hw_reset(eth); 3584 return; 3585 } 3586 3587 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3588 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3589 else 3590 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3591 3592 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3593 rst_mask |= RSTCTRL_PPE1; 3594 3595 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3596 3597 udelay(1); 3598 val = mtk_hw_reset_read(eth); 3599 if (!(val & rst_mask)) 3600 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3601 val, rst_mask); 3602 3603 rst_mask |= RSTCTRL_FE; 3604 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3605 3606 udelay(1); 3607 val = mtk_hw_reset_read(eth); 3608 if (val & rst_mask) 3609 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3610 val, rst_mask); 3611 } 3612 3613 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3614 { 3615 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3616 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3617 bool oq_hang, cdm1_busy, adma_busy; 3618 bool wtx_busy, cdm_full, oq_free; 3619 u32 wdidx, val, gdm1_fc, gdm2_fc; 3620 bool qfsm_hang, qfwd_hang; 3621 bool ret = false; 3622 3623 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3624 return false; 3625 3626 /* WDMA sanity checks */ 3627 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3628 3629 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3630 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3631 3632 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3633 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3634 3635 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3636 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3637 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3638 3639 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3640 if (++eth->reset.wdma_hang_count > 2) { 3641 eth->reset.wdma_hang_count = 0; 3642 ret = true; 3643 } 3644 goto out; 3645 } 3646 3647 /* QDMA sanity checks */ 3648 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3649 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3650 3651 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3652 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3653 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3654 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3655 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3656 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3657 3658 if (qfsm_hang && qfwd_hang && 3659 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3660 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3661 if (++eth->reset.qdma_hang_count > 2) { 3662 eth->reset.qdma_hang_count = 0; 3663 ret = true; 3664 } 3665 goto out; 3666 } 3667 3668 /* ADMA sanity checks */ 3669 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3670 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3671 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3672 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3673 3674 if (oq_hang && cdm1_busy && adma_busy) { 3675 if (++eth->reset.adma_hang_count > 2) { 3676 eth->reset.adma_hang_count = 0; 3677 ret = true; 3678 } 3679 goto out; 3680 } 3681 3682 eth->reset.wdma_hang_count = 0; 3683 eth->reset.qdma_hang_count = 0; 3684 eth->reset.adma_hang_count = 0; 3685 out: 3686 eth->reset.wdidx = wdidx; 3687 3688 return ret; 3689 } 3690 3691 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3692 { 3693 struct delayed_work *del_work = to_delayed_work(work); 3694 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3695 reset.monitor_work); 3696 3697 if (test_bit(MTK_RESETTING, ð->state)) 3698 goto out; 3699 3700 /* DMA stuck checks */ 3701 if (mtk_hw_check_dma_hang(eth)) 3702 schedule_work(ð->pending_work); 3703 3704 out: 3705 schedule_delayed_work(ð->reset.monitor_work, 3706 MTK_DMA_MONITOR_TIMEOUT); 3707 } 3708 3709 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3710 { 3711 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3712 ETHSYS_DMA_AG_MAP_PPE; 3713 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3714 int i, val, ret; 3715 3716 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3717 return 0; 3718 3719 if (!reset) { 3720 pm_runtime_enable(eth->dev); 3721 pm_runtime_get_sync(eth->dev); 3722 3723 ret = mtk_clk_enable(eth); 3724 if (ret) 3725 goto err_disable_pm; 3726 } 3727 3728 if (eth->ethsys) 3729 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3730 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3731 3732 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3733 ret = device_reset(eth->dev); 3734 if (ret) { 3735 dev_err(eth->dev, "MAC reset failed!\n"); 3736 goto err_disable_pm; 3737 } 3738 3739 /* set interrupt delays based on current Net DIM sample */ 3740 mtk_dim_rx(ð->rx_dim.work); 3741 mtk_dim_tx(ð->tx_dim.work); 3742 3743 /* disable delay and normal interrupt */ 3744 mtk_tx_irq_disable(eth, ~0); 3745 mtk_rx_irq_disable(eth, ~0); 3746 3747 return 0; 3748 } 3749 3750 msleep(100); 3751 3752 if (reset) 3753 mtk_hw_warm_reset(eth); 3754 else 3755 mtk_hw_reset(eth); 3756 3757 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3758 /* Set FE to PDMAv2 if necessary */ 3759 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3760 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3761 } 3762 3763 if (eth->pctl) { 3764 /* Set GE2 driving and slew rate */ 3765 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3766 3767 /* set GE2 TDSEL */ 3768 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3769 3770 /* set GE2 TUNE */ 3771 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3772 } 3773 3774 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3775 * up with the more appropriate value when mtk_mac_config call is being 3776 * invoked. 3777 */ 3778 for (i = 0; i < MTK_MAC_COUNT; i++) { 3779 struct net_device *dev = eth->netdev[i]; 3780 3781 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3782 if (dev) { 3783 struct mtk_mac *mac = netdev_priv(dev); 3784 3785 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3786 } 3787 } 3788 3789 /* Indicates CDM to parse the MTK special tag from CPU 3790 * which also is working out for untag packets. 3791 */ 3792 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3793 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3794 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3795 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3796 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3797 } 3798 3799 /* Enable RX VLan Offloading */ 3800 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3801 3802 /* set interrupt delays based on current Net DIM sample */ 3803 mtk_dim_rx(ð->rx_dim.work); 3804 mtk_dim_tx(ð->tx_dim.work); 3805 3806 /* disable delay and normal interrupt */ 3807 mtk_tx_irq_disable(eth, ~0); 3808 mtk_rx_irq_disable(eth, ~0); 3809 3810 /* FE int grouping */ 3811 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3812 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3813 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3814 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3815 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3816 3817 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3818 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3819 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3820 3821 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3822 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3823 3824 /* PSE Free Queue Flow Control */ 3825 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3826 3827 /* PSE config input queue threshold */ 3828 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3829 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3830 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3831 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3832 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3833 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3834 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3835 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3836 3837 /* PSE config output queue threshold */ 3838 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3839 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3840 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3841 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3842 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3843 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3844 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3845 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3846 3847 /* GDM and CDM Threshold */ 3848 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3849 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3850 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3851 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3852 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3853 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3854 } 3855 3856 return 0; 3857 3858 err_disable_pm: 3859 if (!reset) { 3860 pm_runtime_put_sync(eth->dev); 3861 pm_runtime_disable(eth->dev); 3862 } 3863 3864 return ret; 3865 } 3866 3867 static int mtk_hw_deinit(struct mtk_eth *eth) 3868 { 3869 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3870 return 0; 3871 3872 mtk_clk_disable(eth); 3873 3874 pm_runtime_put_sync(eth->dev); 3875 pm_runtime_disable(eth->dev); 3876 3877 return 0; 3878 } 3879 3880 static int __init mtk_init(struct net_device *dev) 3881 { 3882 struct mtk_mac *mac = netdev_priv(dev); 3883 struct mtk_eth *eth = mac->hw; 3884 int ret; 3885 3886 ret = of_get_ethdev_address(mac->of_node, dev); 3887 if (ret) { 3888 /* If the mac address is invalid, use random mac address */ 3889 eth_hw_addr_random(dev); 3890 dev_err(eth->dev, "generated random MAC address %pM\n", 3891 dev->dev_addr); 3892 } 3893 3894 return 0; 3895 } 3896 3897 static void mtk_uninit(struct net_device *dev) 3898 { 3899 struct mtk_mac *mac = netdev_priv(dev); 3900 struct mtk_eth *eth = mac->hw; 3901 3902 phylink_disconnect_phy(mac->phylink); 3903 mtk_tx_irq_disable(eth, ~0); 3904 mtk_rx_irq_disable(eth, ~0); 3905 } 3906 3907 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3908 { 3909 int length = new_mtu + MTK_RX_ETH_HLEN; 3910 struct mtk_mac *mac = netdev_priv(dev); 3911 struct mtk_eth *eth = mac->hw; 3912 3913 if (rcu_access_pointer(eth->prog) && 3914 length > MTK_PP_MAX_BUF_SIZE) { 3915 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3916 return -EINVAL; 3917 } 3918 3919 mtk_set_mcr_max_rx(mac, length); 3920 dev->mtu = new_mtu; 3921 3922 return 0; 3923 } 3924 3925 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3926 { 3927 struct mtk_mac *mac = netdev_priv(dev); 3928 3929 switch (cmd) { 3930 case SIOCGMIIPHY: 3931 case SIOCGMIIREG: 3932 case SIOCSMIIREG: 3933 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3934 default: 3935 break; 3936 } 3937 3938 return -EOPNOTSUPP; 3939 } 3940 3941 static void mtk_prepare_for_reset(struct mtk_eth *eth) 3942 { 3943 u32 val; 3944 int i; 3945 3946 /* disabe FE P3 and P4 */ 3947 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; 3948 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3949 val |= MTK_FE_LINK_DOWN_P4; 3950 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3951 3952 /* adjust PPE configurations to prepare for reset */ 3953 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3954 mtk_ppe_prepare_reset(eth->ppe[i]); 3955 3956 /* disable NETSYS interrupts */ 3957 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 3958 3959 /* force link down GMAC */ 3960 for (i = 0; i < 2; i++) { 3961 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 3962 mtk_w32(eth, val, MTK_MAC_MCR(i)); 3963 } 3964 } 3965 3966 static void mtk_pending_work(struct work_struct *work) 3967 { 3968 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3969 unsigned long restart = 0; 3970 u32 val; 3971 int i; 3972 3973 rtnl_lock(); 3974 set_bit(MTK_RESETTING, ð->state); 3975 3976 mtk_prepare_for_reset(eth); 3977 mtk_wed_fe_reset(); 3978 /* Run again reset preliminary configuration in order to avoid any 3979 * possible race during FE reset since it can run releasing RTNL lock. 3980 */ 3981 mtk_prepare_for_reset(eth); 3982 3983 /* stop all devices to make sure that dma is properly shut down */ 3984 for (i = 0; i < MTK_MAC_COUNT; i++) { 3985 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 3986 continue; 3987 3988 mtk_stop(eth->netdev[i]); 3989 __set_bit(i, &restart); 3990 } 3991 3992 usleep_range(15000, 16000); 3993 3994 if (eth->dev->pins) 3995 pinctrl_select_state(eth->dev->pins->p, 3996 eth->dev->pins->default_state); 3997 mtk_hw_init(eth, true); 3998 3999 /* restart DMA and enable IRQs */ 4000 for (i = 0; i < MTK_MAC_COUNT; i++) { 4001 if (!test_bit(i, &restart)) 4002 continue; 4003 4004 if (mtk_open(eth->netdev[i])) { 4005 netif_alert(eth, ifup, eth->netdev[i], 4006 "Driver up/down cycle failed\n"); 4007 dev_close(eth->netdev[i]); 4008 } 4009 } 4010 4011 /* enabe FE P3 and P4 */ 4012 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; 4013 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 4014 val &= ~MTK_FE_LINK_DOWN_P4; 4015 mtk_w32(eth, val, MTK_FE_GLO_CFG); 4016 4017 clear_bit(MTK_RESETTING, ð->state); 4018 4019 mtk_wed_fe_reset_complete(); 4020 4021 rtnl_unlock(); 4022 } 4023 4024 static int mtk_free_dev(struct mtk_eth *eth) 4025 { 4026 int i; 4027 4028 for (i = 0; i < MTK_MAC_COUNT; i++) { 4029 if (!eth->netdev[i]) 4030 continue; 4031 free_netdev(eth->netdev[i]); 4032 } 4033 4034 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4035 if (!eth->dsa_meta[i]) 4036 break; 4037 metadata_dst_free(eth->dsa_meta[i]); 4038 } 4039 4040 return 0; 4041 } 4042 4043 static int mtk_unreg_dev(struct mtk_eth *eth) 4044 { 4045 int i; 4046 4047 for (i = 0; i < MTK_MAC_COUNT; i++) { 4048 struct mtk_mac *mac; 4049 if (!eth->netdev[i]) 4050 continue; 4051 mac = netdev_priv(eth->netdev[i]); 4052 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4053 unregister_netdevice_notifier(&mac->device_notifier); 4054 unregister_netdev(eth->netdev[i]); 4055 } 4056 4057 return 0; 4058 } 4059 4060 static int mtk_cleanup(struct mtk_eth *eth) 4061 { 4062 mtk_unreg_dev(eth); 4063 mtk_free_dev(eth); 4064 cancel_work_sync(ð->pending_work); 4065 cancel_delayed_work_sync(ð->reset.monitor_work); 4066 4067 return 0; 4068 } 4069 4070 static int mtk_get_link_ksettings(struct net_device *ndev, 4071 struct ethtool_link_ksettings *cmd) 4072 { 4073 struct mtk_mac *mac = netdev_priv(ndev); 4074 4075 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4076 return -EBUSY; 4077 4078 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4079 } 4080 4081 static int mtk_set_link_ksettings(struct net_device *ndev, 4082 const struct ethtool_link_ksettings *cmd) 4083 { 4084 struct mtk_mac *mac = netdev_priv(ndev); 4085 4086 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4087 return -EBUSY; 4088 4089 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4090 } 4091 4092 static void mtk_get_drvinfo(struct net_device *dev, 4093 struct ethtool_drvinfo *info) 4094 { 4095 struct mtk_mac *mac = netdev_priv(dev); 4096 4097 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4098 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4099 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4100 } 4101 4102 static u32 mtk_get_msglevel(struct net_device *dev) 4103 { 4104 struct mtk_mac *mac = netdev_priv(dev); 4105 4106 return mac->hw->msg_enable; 4107 } 4108 4109 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4110 { 4111 struct mtk_mac *mac = netdev_priv(dev); 4112 4113 mac->hw->msg_enable = value; 4114 } 4115 4116 static int mtk_nway_reset(struct net_device *dev) 4117 { 4118 struct mtk_mac *mac = netdev_priv(dev); 4119 4120 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4121 return -EBUSY; 4122 4123 if (!mac->phylink) 4124 return -ENOTSUPP; 4125 4126 return phylink_ethtool_nway_reset(mac->phylink); 4127 } 4128 4129 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4130 { 4131 int i; 4132 4133 switch (stringset) { 4134 case ETH_SS_STATS: { 4135 struct mtk_mac *mac = netdev_priv(dev); 4136 4137 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4138 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4139 data += ETH_GSTRING_LEN; 4140 } 4141 if (mtk_page_pool_enabled(mac->hw)) 4142 page_pool_ethtool_stats_get_strings(data); 4143 break; 4144 } 4145 default: 4146 break; 4147 } 4148 } 4149 4150 static int mtk_get_sset_count(struct net_device *dev, int sset) 4151 { 4152 switch (sset) { 4153 case ETH_SS_STATS: { 4154 int count = ARRAY_SIZE(mtk_ethtool_stats); 4155 struct mtk_mac *mac = netdev_priv(dev); 4156 4157 if (mtk_page_pool_enabled(mac->hw)) 4158 count += page_pool_ethtool_stats_get_count(); 4159 return count; 4160 } 4161 default: 4162 return -EOPNOTSUPP; 4163 } 4164 } 4165 4166 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4167 { 4168 struct page_pool_stats stats = {}; 4169 int i; 4170 4171 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4172 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4173 4174 if (!ring->page_pool) 4175 continue; 4176 4177 page_pool_get_stats(ring->page_pool, &stats); 4178 } 4179 page_pool_ethtool_stats_get(data, &stats); 4180 } 4181 4182 static void mtk_get_ethtool_stats(struct net_device *dev, 4183 struct ethtool_stats *stats, u64 *data) 4184 { 4185 struct mtk_mac *mac = netdev_priv(dev); 4186 struct mtk_hw_stats *hwstats = mac->hw_stats; 4187 u64 *data_src, *data_dst; 4188 unsigned int start; 4189 int i; 4190 4191 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4192 return; 4193 4194 if (netif_running(dev) && netif_device_present(dev)) { 4195 if (spin_trylock_bh(&hwstats->stats_lock)) { 4196 mtk_stats_update_mac(mac); 4197 spin_unlock_bh(&hwstats->stats_lock); 4198 } 4199 } 4200 4201 data_src = (u64 *)hwstats; 4202 4203 do { 4204 data_dst = data; 4205 start = u64_stats_fetch_begin(&hwstats->syncp); 4206 4207 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4208 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4209 if (mtk_page_pool_enabled(mac->hw)) 4210 mtk_ethtool_pp_stats(mac->hw, data_dst); 4211 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4212 } 4213 4214 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4215 u32 *rule_locs) 4216 { 4217 int ret = -EOPNOTSUPP; 4218 4219 switch (cmd->cmd) { 4220 case ETHTOOL_GRXRINGS: 4221 if (dev->hw_features & NETIF_F_LRO) { 4222 cmd->data = MTK_MAX_RX_RING_NUM; 4223 ret = 0; 4224 } 4225 break; 4226 case ETHTOOL_GRXCLSRLCNT: 4227 if (dev->hw_features & NETIF_F_LRO) { 4228 struct mtk_mac *mac = netdev_priv(dev); 4229 4230 cmd->rule_cnt = mac->hwlro_ip_cnt; 4231 ret = 0; 4232 } 4233 break; 4234 case ETHTOOL_GRXCLSRULE: 4235 if (dev->hw_features & NETIF_F_LRO) 4236 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4237 break; 4238 case ETHTOOL_GRXCLSRLALL: 4239 if (dev->hw_features & NETIF_F_LRO) 4240 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4241 rule_locs); 4242 break; 4243 default: 4244 break; 4245 } 4246 4247 return ret; 4248 } 4249 4250 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4251 { 4252 int ret = -EOPNOTSUPP; 4253 4254 switch (cmd->cmd) { 4255 case ETHTOOL_SRXCLSRLINS: 4256 if (dev->hw_features & NETIF_F_LRO) 4257 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4258 break; 4259 case ETHTOOL_SRXCLSRLDEL: 4260 if (dev->hw_features & NETIF_F_LRO) 4261 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4262 break; 4263 default: 4264 break; 4265 } 4266 4267 return ret; 4268 } 4269 4270 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4271 struct net_device *sb_dev) 4272 { 4273 struct mtk_mac *mac = netdev_priv(dev); 4274 unsigned int queue = 0; 4275 4276 if (netdev_uses_dsa(dev)) 4277 queue = skb_get_queue_mapping(skb) + 3; 4278 else 4279 queue = mac->id; 4280 4281 if (queue >= dev->num_tx_queues) 4282 queue = 0; 4283 4284 return queue; 4285 } 4286 4287 static const struct ethtool_ops mtk_ethtool_ops = { 4288 .get_link_ksettings = mtk_get_link_ksettings, 4289 .set_link_ksettings = mtk_set_link_ksettings, 4290 .get_drvinfo = mtk_get_drvinfo, 4291 .get_msglevel = mtk_get_msglevel, 4292 .set_msglevel = mtk_set_msglevel, 4293 .nway_reset = mtk_nway_reset, 4294 .get_link = ethtool_op_get_link, 4295 .get_strings = mtk_get_strings, 4296 .get_sset_count = mtk_get_sset_count, 4297 .get_ethtool_stats = mtk_get_ethtool_stats, 4298 .get_rxnfc = mtk_get_rxnfc, 4299 .set_rxnfc = mtk_set_rxnfc, 4300 }; 4301 4302 static const struct net_device_ops mtk_netdev_ops = { 4303 .ndo_init = mtk_init, 4304 .ndo_uninit = mtk_uninit, 4305 .ndo_open = mtk_open, 4306 .ndo_stop = mtk_stop, 4307 .ndo_start_xmit = mtk_start_xmit, 4308 .ndo_set_mac_address = mtk_set_mac_address, 4309 .ndo_validate_addr = eth_validate_addr, 4310 .ndo_eth_ioctl = mtk_do_ioctl, 4311 .ndo_change_mtu = mtk_change_mtu, 4312 .ndo_tx_timeout = mtk_tx_timeout, 4313 .ndo_get_stats64 = mtk_get_stats64, 4314 .ndo_fix_features = mtk_fix_features, 4315 .ndo_set_features = mtk_set_features, 4316 #ifdef CONFIG_NET_POLL_CONTROLLER 4317 .ndo_poll_controller = mtk_poll_controller, 4318 #endif 4319 .ndo_setup_tc = mtk_eth_setup_tc, 4320 .ndo_bpf = mtk_xdp, 4321 .ndo_xdp_xmit = mtk_xdp_xmit, 4322 .ndo_select_queue = mtk_select_queue, 4323 }; 4324 4325 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4326 { 4327 const __be32 *_id = of_get_property(np, "reg", NULL); 4328 phy_interface_t phy_mode; 4329 struct phylink *phylink; 4330 struct mtk_mac *mac; 4331 int id, err; 4332 int txqs = 1; 4333 4334 if (!_id) { 4335 dev_err(eth->dev, "missing mac id\n"); 4336 return -EINVAL; 4337 } 4338 4339 id = be32_to_cpup(_id); 4340 if (id >= MTK_MAC_COUNT) { 4341 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4342 return -EINVAL; 4343 } 4344 4345 if (eth->netdev[id]) { 4346 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4347 return -EINVAL; 4348 } 4349 4350 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4351 txqs = MTK_QDMA_NUM_QUEUES; 4352 4353 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4354 if (!eth->netdev[id]) { 4355 dev_err(eth->dev, "alloc_etherdev failed\n"); 4356 return -ENOMEM; 4357 } 4358 mac = netdev_priv(eth->netdev[id]); 4359 eth->mac[id] = mac; 4360 mac->id = id; 4361 mac->hw = eth; 4362 mac->of_node = np; 4363 4364 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4365 mac->hwlro_ip_cnt = 0; 4366 4367 mac->hw_stats = devm_kzalloc(eth->dev, 4368 sizeof(*mac->hw_stats), 4369 GFP_KERNEL); 4370 if (!mac->hw_stats) { 4371 dev_err(eth->dev, "failed to allocate counter memory\n"); 4372 err = -ENOMEM; 4373 goto free_netdev; 4374 } 4375 spin_lock_init(&mac->hw_stats->stats_lock); 4376 u64_stats_init(&mac->hw_stats->syncp); 4377 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4378 4379 /* phylink create */ 4380 err = of_get_phy_mode(np, &phy_mode); 4381 if (err) { 4382 dev_err(eth->dev, "incorrect phy-mode\n"); 4383 goto free_netdev; 4384 } 4385 4386 /* mac config is not set */ 4387 mac->interface = PHY_INTERFACE_MODE_NA; 4388 mac->speed = SPEED_UNKNOWN; 4389 4390 mac->phylink_config.dev = ð->netdev[id]->dev; 4391 mac->phylink_config.type = PHYLINK_NETDEV; 4392 /* This driver makes use of state->speed in mac_config */ 4393 mac->phylink_config.legacy_pre_march2020 = true; 4394 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4395 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4396 4397 __set_bit(PHY_INTERFACE_MODE_MII, 4398 mac->phylink_config.supported_interfaces); 4399 __set_bit(PHY_INTERFACE_MODE_GMII, 4400 mac->phylink_config.supported_interfaces); 4401 4402 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4403 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4404 4405 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4406 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4407 mac->phylink_config.supported_interfaces); 4408 4409 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4410 __set_bit(PHY_INTERFACE_MODE_SGMII, 4411 mac->phylink_config.supported_interfaces); 4412 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4413 mac->phylink_config.supported_interfaces); 4414 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4415 mac->phylink_config.supported_interfaces); 4416 } 4417 4418 phylink = phylink_create(&mac->phylink_config, 4419 of_fwnode_handle(mac->of_node), 4420 phy_mode, &mtk_phylink_ops); 4421 if (IS_ERR(phylink)) { 4422 err = PTR_ERR(phylink); 4423 goto free_netdev; 4424 } 4425 4426 mac->phylink = phylink; 4427 4428 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4429 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4430 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4431 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4432 4433 eth->netdev[id]->hw_features = eth->soc->hw_features; 4434 if (eth->hwlro) 4435 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4436 4437 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4438 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 4439 eth->netdev[id]->features |= eth->soc->hw_features; 4440 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4441 4442 eth->netdev[id]->irq = eth->irq[0]; 4443 eth->netdev[id]->dev.of_node = np; 4444 4445 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4446 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4447 else 4448 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4449 4450 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4451 mac->device_notifier.notifier_call = mtk_device_event; 4452 register_netdevice_notifier(&mac->device_notifier); 4453 } 4454 4455 if (mtk_page_pool_enabled(eth)) 4456 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4457 NETDEV_XDP_ACT_REDIRECT | 4458 NETDEV_XDP_ACT_NDO_XMIT | 4459 NETDEV_XDP_ACT_NDO_XMIT_SG; 4460 4461 return 0; 4462 4463 free_netdev: 4464 free_netdev(eth->netdev[id]); 4465 return err; 4466 } 4467 4468 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4469 { 4470 struct net_device *dev, *tmp; 4471 LIST_HEAD(dev_list); 4472 int i; 4473 4474 rtnl_lock(); 4475 4476 for (i = 0; i < MTK_MAC_COUNT; i++) { 4477 dev = eth->netdev[i]; 4478 4479 if (!dev || !(dev->flags & IFF_UP)) 4480 continue; 4481 4482 list_add_tail(&dev->close_list, &dev_list); 4483 } 4484 4485 dev_close_many(&dev_list, false); 4486 4487 eth->dma_dev = dma_dev; 4488 4489 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4490 list_del_init(&dev->close_list); 4491 dev_open(dev, NULL); 4492 } 4493 4494 rtnl_unlock(); 4495 } 4496 4497 static int mtk_probe(struct platform_device *pdev) 4498 { 4499 struct resource *res = NULL; 4500 struct device_node *mac_np; 4501 struct mtk_eth *eth; 4502 int err, i; 4503 4504 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4505 if (!eth) 4506 return -ENOMEM; 4507 4508 eth->soc = of_device_get_match_data(&pdev->dev); 4509 4510 eth->dev = &pdev->dev; 4511 eth->dma_dev = &pdev->dev; 4512 eth->base = devm_platform_ioremap_resource(pdev, 0); 4513 if (IS_ERR(eth->base)) 4514 return PTR_ERR(eth->base); 4515 4516 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4517 eth->ip_align = NET_IP_ALIGN; 4518 4519 spin_lock_init(ð->page_lock); 4520 spin_lock_init(ð->tx_irq_lock); 4521 spin_lock_init(ð->rx_irq_lock); 4522 spin_lock_init(ð->dim_lock); 4523 4524 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4525 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4526 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4527 4528 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4529 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4530 4531 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4532 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4533 "mediatek,ethsys"); 4534 if (IS_ERR(eth->ethsys)) { 4535 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4536 return PTR_ERR(eth->ethsys); 4537 } 4538 } 4539 4540 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4541 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4542 "mediatek,infracfg"); 4543 if (IS_ERR(eth->infra)) { 4544 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4545 return PTR_ERR(eth->infra); 4546 } 4547 } 4548 4549 if (of_dma_is_coherent(pdev->dev.of_node)) { 4550 struct regmap *cci; 4551 4552 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4553 "cci-control-port"); 4554 /* enable CPU/bus coherency */ 4555 if (!IS_ERR(cci)) 4556 regmap_write(cci, 0, 3); 4557 } 4558 4559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4560 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 4561 GFP_KERNEL); 4562 if (!eth->sgmii) 4563 return -ENOMEM; 4564 4565 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 4566 eth->soc->ana_rgc3); 4567 4568 if (err) 4569 return err; 4570 } 4571 4572 if (eth->soc->required_pctl) { 4573 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4574 "mediatek,pctl"); 4575 if (IS_ERR(eth->pctl)) { 4576 dev_err(&pdev->dev, "no pctl regmap found\n"); 4577 return PTR_ERR(eth->pctl); 4578 } 4579 } 4580 4581 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4582 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4583 if (!res) 4584 return -EINVAL; 4585 } 4586 4587 if (eth->soc->offload_version) { 4588 for (i = 0;; i++) { 4589 struct device_node *np; 4590 phys_addr_t wdma_phy; 4591 u32 wdma_base; 4592 4593 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4594 break; 4595 4596 np = of_parse_phandle(pdev->dev.of_node, 4597 "mediatek,wed", i); 4598 if (!np) 4599 break; 4600 4601 wdma_base = eth->soc->reg_map->wdma_base[i]; 4602 wdma_phy = res ? res->start + wdma_base : 0; 4603 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4604 wdma_phy, i); 4605 } 4606 } 4607 4608 for (i = 0; i < 3; i++) { 4609 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4610 eth->irq[i] = eth->irq[0]; 4611 else 4612 eth->irq[i] = platform_get_irq(pdev, i); 4613 if (eth->irq[i] < 0) { 4614 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4615 err = -ENXIO; 4616 goto err_wed_exit; 4617 } 4618 } 4619 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4620 eth->clks[i] = devm_clk_get(eth->dev, 4621 mtk_clks_source_name[i]); 4622 if (IS_ERR(eth->clks[i])) { 4623 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4624 err = -EPROBE_DEFER; 4625 goto err_wed_exit; 4626 } 4627 if (eth->soc->required_clks & BIT(i)) { 4628 dev_err(&pdev->dev, "clock %s not found\n", 4629 mtk_clks_source_name[i]); 4630 err = -EINVAL; 4631 goto err_wed_exit; 4632 } 4633 eth->clks[i] = NULL; 4634 } 4635 } 4636 4637 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4638 INIT_WORK(ð->pending_work, mtk_pending_work); 4639 4640 err = mtk_hw_init(eth, false); 4641 if (err) 4642 goto err_wed_exit; 4643 4644 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4645 4646 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4647 if (!of_device_is_compatible(mac_np, 4648 "mediatek,eth-mac")) 4649 continue; 4650 4651 if (!of_device_is_available(mac_np)) 4652 continue; 4653 4654 err = mtk_add_mac(eth, mac_np); 4655 if (err) { 4656 of_node_put(mac_np); 4657 goto err_deinit_hw; 4658 } 4659 } 4660 4661 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4662 err = devm_request_irq(eth->dev, eth->irq[0], 4663 mtk_handle_irq, 0, 4664 dev_name(eth->dev), eth); 4665 } else { 4666 err = devm_request_irq(eth->dev, eth->irq[1], 4667 mtk_handle_irq_tx, 0, 4668 dev_name(eth->dev), eth); 4669 if (err) 4670 goto err_free_dev; 4671 4672 err = devm_request_irq(eth->dev, eth->irq[2], 4673 mtk_handle_irq_rx, 0, 4674 dev_name(eth->dev), eth); 4675 } 4676 if (err) 4677 goto err_free_dev; 4678 4679 /* No MT7628/88 support yet */ 4680 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4681 err = mtk_mdio_init(eth); 4682 if (err) 4683 goto err_free_dev; 4684 } 4685 4686 if (eth->soc->offload_version) { 4687 u32 num_ppe; 4688 4689 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4690 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4691 for (i = 0; i < num_ppe; i++) { 4692 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4693 4694 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, 4695 eth->soc->offload_version, i); 4696 if (!eth->ppe[i]) { 4697 err = -ENOMEM; 4698 goto err_deinit_ppe; 4699 } 4700 } 4701 4702 err = mtk_eth_offload_init(eth); 4703 if (err) 4704 goto err_deinit_ppe; 4705 } 4706 4707 for (i = 0; i < MTK_MAX_DEVS; i++) { 4708 if (!eth->netdev[i]) 4709 continue; 4710 4711 err = register_netdev(eth->netdev[i]); 4712 if (err) { 4713 dev_err(eth->dev, "error bringing up device\n"); 4714 goto err_deinit_ppe; 4715 } else 4716 netif_info(eth, probe, eth->netdev[i], 4717 "mediatek frame engine at 0x%08lx, irq %d\n", 4718 eth->netdev[i]->base_addr, eth->irq[0]); 4719 } 4720 4721 /* we run 2 devices on the same DMA ring so we need a dummy device 4722 * for NAPI to work 4723 */ 4724 init_dummy_netdev(ð->dummy_dev); 4725 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4726 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4727 4728 platform_set_drvdata(pdev, eth); 4729 schedule_delayed_work(ð->reset.monitor_work, 4730 MTK_DMA_MONITOR_TIMEOUT); 4731 4732 return 0; 4733 4734 err_deinit_ppe: 4735 mtk_ppe_deinit(eth); 4736 mtk_mdio_cleanup(eth); 4737 err_free_dev: 4738 mtk_free_dev(eth); 4739 err_deinit_hw: 4740 mtk_hw_deinit(eth); 4741 err_wed_exit: 4742 mtk_wed_exit(); 4743 4744 return err; 4745 } 4746 4747 static int mtk_remove(struct platform_device *pdev) 4748 { 4749 struct mtk_eth *eth = platform_get_drvdata(pdev); 4750 struct mtk_mac *mac; 4751 int i; 4752 4753 /* stop all devices to make sure that dma is properly shut down */ 4754 for (i = 0; i < MTK_MAC_COUNT; i++) { 4755 if (!eth->netdev[i]) 4756 continue; 4757 mtk_stop(eth->netdev[i]); 4758 mac = netdev_priv(eth->netdev[i]); 4759 phylink_disconnect_phy(mac->phylink); 4760 } 4761 4762 mtk_wed_exit(); 4763 mtk_hw_deinit(eth); 4764 4765 netif_napi_del(ð->tx_napi); 4766 netif_napi_del(ð->rx_napi); 4767 mtk_cleanup(eth); 4768 mtk_mdio_cleanup(eth); 4769 4770 return 0; 4771 } 4772 4773 static const struct mtk_soc_data mt2701_data = { 4774 .reg_map = &mtk_reg_map, 4775 .caps = MT7623_CAPS | MTK_HWLRO, 4776 .hw_features = MTK_HW_FEATURES, 4777 .required_clks = MT7623_CLKS_BITMAP, 4778 .required_pctl = true, 4779 .txrx = { 4780 .txd_size = sizeof(struct mtk_tx_dma), 4781 .rxd_size = sizeof(struct mtk_rx_dma), 4782 .rx_irq_done_mask = MTK_RX_DONE_INT, 4783 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4784 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4785 .dma_len_offset = 16, 4786 }, 4787 }; 4788 4789 static const struct mtk_soc_data mt7621_data = { 4790 .reg_map = &mtk_reg_map, 4791 .caps = MT7621_CAPS, 4792 .hw_features = MTK_HW_FEATURES, 4793 .required_clks = MT7621_CLKS_BITMAP, 4794 .required_pctl = false, 4795 .offload_version = 1, 4796 .hash_offset = 2, 4797 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4798 .txrx = { 4799 .txd_size = sizeof(struct mtk_tx_dma), 4800 .rxd_size = sizeof(struct mtk_rx_dma), 4801 .rx_irq_done_mask = MTK_RX_DONE_INT, 4802 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4803 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4804 .dma_len_offset = 16, 4805 }, 4806 }; 4807 4808 static const struct mtk_soc_data mt7622_data = { 4809 .reg_map = &mtk_reg_map, 4810 .ana_rgc3 = 0x2028, 4811 .caps = MT7622_CAPS | MTK_HWLRO, 4812 .hw_features = MTK_HW_FEATURES, 4813 .required_clks = MT7622_CLKS_BITMAP, 4814 .required_pctl = false, 4815 .offload_version = 2, 4816 .hash_offset = 2, 4817 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4818 .txrx = { 4819 .txd_size = sizeof(struct mtk_tx_dma), 4820 .rxd_size = sizeof(struct mtk_rx_dma), 4821 .rx_irq_done_mask = MTK_RX_DONE_INT, 4822 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4823 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4824 .dma_len_offset = 16, 4825 }, 4826 }; 4827 4828 static const struct mtk_soc_data mt7623_data = { 4829 .reg_map = &mtk_reg_map, 4830 .caps = MT7623_CAPS | MTK_HWLRO, 4831 .hw_features = MTK_HW_FEATURES, 4832 .required_clks = MT7623_CLKS_BITMAP, 4833 .required_pctl = true, 4834 .offload_version = 1, 4835 .hash_offset = 2, 4836 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4837 .txrx = { 4838 .txd_size = sizeof(struct mtk_tx_dma), 4839 .rxd_size = sizeof(struct mtk_rx_dma), 4840 .rx_irq_done_mask = MTK_RX_DONE_INT, 4841 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4842 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4843 .dma_len_offset = 16, 4844 }, 4845 }; 4846 4847 static const struct mtk_soc_data mt7629_data = { 4848 .reg_map = &mtk_reg_map, 4849 .ana_rgc3 = 0x128, 4850 .caps = MT7629_CAPS | MTK_HWLRO, 4851 .hw_features = MTK_HW_FEATURES, 4852 .required_clks = MT7629_CLKS_BITMAP, 4853 .required_pctl = false, 4854 .txrx = { 4855 .txd_size = sizeof(struct mtk_tx_dma), 4856 .rxd_size = sizeof(struct mtk_rx_dma), 4857 .rx_irq_done_mask = MTK_RX_DONE_INT, 4858 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4859 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4860 .dma_len_offset = 16, 4861 }, 4862 }; 4863 4864 static const struct mtk_soc_data mt7986_data = { 4865 .reg_map = &mt7986_reg_map, 4866 .ana_rgc3 = 0x128, 4867 .caps = MT7986_CAPS, 4868 .hw_features = MTK_HW_FEATURES, 4869 .required_clks = MT7986_CLKS_BITMAP, 4870 .required_pctl = false, 4871 .offload_version = 2, 4872 .hash_offset = 4, 4873 .foe_entry_size = sizeof(struct mtk_foe_entry), 4874 .txrx = { 4875 .txd_size = sizeof(struct mtk_tx_dma_v2), 4876 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4877 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4878 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4879 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4880 .dma_len_offset = 8, 4881 }, 4882 }; 4883 4884 static const struct mtk_soc_data rt5350_data = { 4885 .reg_map = &mt7628_reg_map, 4886 .caps = MT7628_CAPS, 4887 .hw_features = MTK_HW_FEATURES_MT7628, 4888 .required_clks = MT7628_CLKS_BITMAP, 4889 .required_pctl = false, 4890 .txrx = { 4891 .txd_size = sizeof(struct mtk_tx_dma), 4892 .rxd_size = sizeof(struct mtk_rx_dma), 4893 .rx_irq_done_mask = MTK_RX_DONE_INT, 4894 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4895 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4896 .dma_len_offset = 16, 4897 }, 4898 }; 4899 4900 const struct of_device_id of_mtk_match[] = { 4901 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4902 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4903 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4904 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4905 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4906 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4907 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4908 {}, 4909 }; 4910 MODULE_DEVICE_TABLE(of, of_mtk_match); 4911 4912 static struct platform_driver mtk_driver = { 4913 .probe = mtk_probe, 4914 .remove = mtk_remove, 4915 .driver = { 4916 .name = "mtk_soc_eth", 4917 .of_match_table = of_mtk_match, 4918 }, 4919 }; 4920 4921 module_platform_driver(mtk_driver); 4922 4923 MODULE_LICENSE("GPL"); 4924 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4925 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4926