1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/if_vlan.h> 23 #include <linux/reset.h> 24 #include <linux/tcp.h> 25 26 #include "mtk_eth_soc.h" 27 28 static int mtk_msg_level = -1; 29 module_param_named(msg_level, mtk_msg_level, int, 0); 30 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 31 32 #define MTK_ETHTOOL_STAT(x) { #x, \ 33 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 34 35 /* strings used by ethtool */ 36 static const struct mtk_ethtool_stats { 37 char str[ETH_GSTRING_LEN]; 38 u32 offset; 39 } mtk_ethtool_stats[] = { 40 MTK_ETHTOOL_STAT(tx_bytes), 41 MTK_ETHTOOL_STAT(tx_packets), 42 MTK_ETHTOOL_STAT(tx_skip), 43 MTK_ETHTOOL_STAT(tx_collisions), 44 MTK_ETHTOOL_STAT(rx_bytes), 45 MTK_ETHTOOL_STAT(rx_packets), 46 MTK_ETHTOOL_STAT(rx_overflow), 47 MTK_ETHTOOL_STAT(rx_fcs_errors), 48 MTK_ETHTOOL_STAT(rx_short_errors), 49 MTK_ETHTOOL_STAT(rx_long_errors), 50 MTK_ETHTOOL_STAT(rx_checksum_errors), 51 MTK_ETHTOOL_STAT(rx_flow_control_packets), 52 }; 53 54 static const char * const mtk_clks_source_name[] = { 55 "ethif", "esw", "gp1", "gp2", "trgpll" 56 }; 57 58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 59 { 60 __raw_writel(val, eth->base + reg); 61 } 62 63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 64 { 65 return __raw_readl(eth->base + reg); 66 } 67 68 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 69 { 70 unsigned long t_start = jiffies; 71 72 while (1) { 73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 74 return 0; 75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 76 break; 77 usleep_range(10, 20); 78 } 79 80 dev_err(eth->dev, "mdio: MDIO timeout\n"); 81 return -1; 82 } 83 84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 85 u32 phy_register, u32 write_data) 86 { 87 if (mtk_mdio_busy_wait(eth)) 88 return -1; 89 90 write_data &= 0xffff; 91 92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 93 (phy_register << PHY_IAC_REG_SHIFT) | 94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 95 MTK_PHY_IAC); 96 97 if (mtk_mdio_busy_wait(eth)) 98 return -1; 99 100 return 0; 101 } 102 103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 104 { 105 u32 d; 106 107 if (mtk_mdio_busy_wait(eth)) 108 return 0xffff; 109 110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 111 (phy_reg << PHY_IAC_REG_SHIFT) | 112 (phy_addr << PHY_IAC_ADDR_SHIFT), 113 MTK_PHY_IAC); 114 115 if (mtk_mdio_busy_wait(eth)) 116 return 0xffff; 117 118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 119 120 return d; 121 } 122 123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 124 int phy_reg, u16 val) 125 { 126 struct mtk_eth *eth = bus->priv; 127 128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 129 } 130 131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 132 { 133 struct mtk_eth *eth = bus->priv; 134 135 return _mtk_mdio_read(eth, phy_addr, phy_reg); 136 } 137 138 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 139 { 140 u32 val; 141 int ret; 142 143 val = (speed == SPEED_1000) ? 144 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 145 mtk_w32(eth, val, INTF_MODE); 146 147 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 148 ETHSYS_TRGMII_CLK_SEL362_5, 149 ETHSYS_TRGMII_CLK_SEL362_5); 150 151 val = (speed == SPEED_1000) ? 250000000 : 500000000; 152 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 153 if (ret) 154 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 155 156 val = (speed == SPEED_1000) ? 157 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 158 mtk_w32(eth, val, TRGMII_RCK_CTRL); 159 160 val = (speed == SPEED_1000) ? 161 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 162 mtk_w32(eth, val, TRGMII_TCK_CTRL); 163 } 164 165 static void mtk_phy_link_adjust(struct net_device *dev) 166 { 167 struct mtk_mac *mac = netdev_priv(dev); 168 u16 lcl_adv = 0, rmt_adv = 0; 169 u8 flowctrl; 170 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 171 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 172 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 173 MAC_MCR_BACKPR_EN; 174 175 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 176 return; 177 178 switch (dev->phydev->speed) { 179 case SPEED_1000: 180 mcr |= MAC_MCR_SPEED_1000; 181 break; 182 case SPEED_100: 183 mcr |= MAC_MCR_SPEED_100; 184 break; 185 }; 186 187 if (mac->id == 0 && !mac->trgmii) 188 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed); 189 190 if (dev->phydev->link) 191 mcr |= MAC_MCR_FORCE_LINK; 192 193 if (dev->phydev->duplex) { 194 mcr |= MAC_MCR_FORCE_DPX; 195 196 if (dev->phydev->pause) 197 rmt_adv = LPA_PAUSE_CAP; 198 if (dev->phydev->asym_pause) 199 rmt_adv |= LPA_PAUSE_ASYM; 200 201 if (dev->phydev->advertising & ADVERTISED_Pause) 202 lcl_adv |= ADVERTISE_PAUSE_CAP; 203 if (dev->phydev->advertising & ADVERTISED_Asym_Pause) 204 lcl_adv |= ADVERTISE_PAUSE_ASYM; 205 206 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 207 208 if (flowctrl & FLOW_CTRL_TX) 209 mcr |= MAC_MCR_FORCE_TX_FC; 210 if (flowctrl & FLOW_CTRL_RX) 211 mcr |= MAC_MCR_FORCE_RX_FC; 212 213 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 214 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 215 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 216 } 217 218 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 219 220 if (dev->phydev->link) 221 netif_carrier_on(dev); 222 else 223 netif_carrier_off(dev); 224 } 225 226 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 227 struct device_node *phy_node) 228 { 229 struct phy_device *phydev; 230 int phy_mode; 231 232 phy_mode = of_get_phy_mode(phy_node); 233 if (phy_mode < 0) { 234 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 235 return -EINVAL; 236 } 237 238 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 239 mtk_phy_link_adjust, 0, phy_mode); 240 if (!phydev) { 241 dev_err(eth->dev, "could not connect to PHY\n"); 242 return -ENODEV; 243 } 244 245 dev_info(eth->dev, 246 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 247 mac->id, phydev_name(phydev), phydev->phy_id, 248 phydev->drv->name); 249 250 return 0; 251 } 252 253 static int mtk_phy_connect(struct net_device *dev) 254 { 255 struct mtk_mac *mac = netdev_priv(dev); 256 struct mtk_eth *eth; 257 struct device_node *np; 258 u32 val; 259 260 eth = mac->hw; 261 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 262 if (!np && of_phy_is_fixed_link(mac->of_node)) 263 if (!of_phy_register_fixed_link(mac->of_node)) 264 np = of_node_get(mac->of_node); 265 if (!np) 266 return -ENODEV; 267 268 switch (of_get_phy_mode(np)) { 269 case PHY_INTERFACE_MODE_TRGMII: 270 mac->trgmii = true; 271 case PHY_INTERFACE_MODE_RGMII_TXID: 272 case PHY_INTERFACE_MODE_RGMII_RXID: 273 case PHY_INTERFACE_MODE_RGMII_ID: 274 case PHY_INTERFACE_MODE_RGMII: 275 mac->ge_mode = 0; 276 break; 277 case PHY_INTERFACE_MODE_MII: 278 mac->ge_mode = 1; 279 break; 280 case PHY_INTERFACE_MODE_REVMII: 281 mac->ge_mode = 2; 282 break; 283 case PHY_INTERFACE_MODE_RMII: 284 if (!mac->id) 285 goto err_phy; 286 mac->ge_mode = 3; 287 break; 288 default: 289 goto err_phy; 290 } 291 292 /* put the gmac into the right mode */ 293 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 294 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 295 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id); 296 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 297 298 /* couple phydev to net_device */ 299 if (mtk_phy_connect_node(eth, mac, np)) 300 goto err_phy; 301 302 dev->phydev->autoneg = AUTONEG_ENABLE; 303 dev->phydev->speed = 0; 304 dev->phydev->duplex = 0; 305 306 if (of_phy_is_fixed_link(mac->of_node)) 307 dev->phydev->supported |= 308 SUPPORTED_Pause | SUPPORTED_Asym_Pause; 309 310 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 311 SUPPORTED_Asym_Pause; 312 dev->phydev->advertising = dev->phydev->supported | 313 ADVERTISED_Autoneg; 314 phy_start_aneg(dev->phydev); 315 316 of_node_put(np); 317 318 return 0; 319 320 err_phy: 321 if (of_phy_is_fixed_link(mac->of_node)) 322 of_phy_deregister_fixed_link(mac->of_node); 323 of_node_put(np); 324 dev_err(eth->dev, "%s: invalid phy\n", __func__); 325 return -EINVAL; 326 } 327 328 static int mtk_mdio_init(struct mtk_eth *eth) 329 { 330 struct device_node *mii_np; 331 int ret; 332 333 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 334 if (!mii_np) { 335 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 336 return -ENODEV; 337 } 338 339 if (!of_device_is_available(mii_np)) { 340 ret = -ENODEV; 341 goto err_put_node; 342 } 343 344 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 345 if (!eth->mii_bus) { 346 ret = -ENOMEM; 347 goto err_put_node; 348 } 349 350 eth->mii_bus->name = "mdio"; 351 eth->mii_bus->read = mtk_mdio_read; 352 eth->mii_bus->write = mtk_mdio_write; 353 eth->mii_bus->priv = eth; 354 eth->mii_bus->parent = eth->dev; 355 356 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 357 ret = of_mdiobus_register(eth->mii_bus, mii_np); 358 359 err_put_node: 360 of_node_put(mii_np); 361 return ret; 362 } 363 364 static void mtk_mdio_cleanup(struct mtk_eth *eth) 365 { 366 if (!eth->mii_bus) 367 return; 368 369 mdiobus_unregister(eth->mii_bus); 370 } 371 372 static inline void mtk_irq_disable(struct mtk_eth *eth, 373 unsigned reg, u32 mask) 374 { 375 unsigned long flags; 376 u32 val; 377 378 spin_lock_irqsave(ð->irq_lock, flags); 379 val = mtk_r32(eth, reg); 380 mtk_w32(eth, val & ~mask, reg); 381 spin_unlock_irqrestore(ð->irq_lock, flags); 382 } 383 384 static inline void mtk_irq_enable(struct mtk_eth *eth, 385 unsigned reg, u32 mask) 386 { 387 unsigned long flags; 388 u32 val; 389 390 spin_lock_irqsave(ð->irq_lock, flags); 391 val = mtk_r32(eth, reg); 392 mtk_w32(eth, val | mask, reg); 393 spin_unlock_irqrestore(ð->irq_lock, flags); 394 } 395 396 static int mtk_set_mac_address(struct net_device *dev, void *p) 397 { 398 int ret = eth_mac_addr(dev, p); 399 struct mtk_mac *mac = netdev_priv(dev); 400 const char *macaddr = dev->dev_addr; 401 402 if (ret) 403 return ret; 404 405 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 406 return -EBUSY; 407 408 spin_lock_bh(&mac->hw->page_lock); 409 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 410 MTK_GDMA_MAC_ADRH(mac->id)); 411 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 412 (macaddr[4] << 8) | macaddr[5], 413 MTK_GDMA_MAC_ADRL(mac->id)); 414 spin_unlock_bh(&mac->hw->page_lock); 415 416 return 0; 417 } 418 419 void mtk_stats_update_mac(struct mtk_mac *mac) 420 { 421 struct mtk_hw_stats *hw_stats = mac->hw_stats; 422 unsigned int base = MTK_GDM1_TX_GBCNT; 423 u64 stats; 424 425 base += hw_stats->reg_offset; 426 427 u64_stats_update_begin(&hw_stats->syncp); 428 429 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 430 stats = mtk_r32(mac->hw, base + 0x04); 431 if (stats) 432 hw_stats->rx_bytes += (stats << 32); 433 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 434 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 435 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 436 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 437 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 438 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 439 hw_stats->rx_flow_control_packets += 440 mtk_r32(mac->hw, base + 0x24); 441 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 442 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 443 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 444 stats = mtk_r32(mac->hw, base + 0x34); 445 if (stats) 446 hw_stats->tx_bytes += (stats << 32); 447 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 448 u64_stats_update_end(&hw_stats->syncp); 449 } 450 451 static void mtk_stats_update(struct mtk_eth *eth) 452 { 453 int i; 454 455 for (i = 0; i < MTK_MAC_COUNT; i++) { 456 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 457 continue; 458 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 459 mtk_stats_update_mac(eth->mac[i]); 460 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 461 } 462 } 463 } 464 465 static void mtk_get_stats64(struct net_device *dev, 466 struct rtnl_link_stats64 *storage) 467 { 468 struct mtk_mac *mac = netdev_priv(dev); 469 struct mtk_hw_stats *hw_stats = mac->hw_stats; 470 unsigned int start; 471 472 if (netif_running(dev) && netif_device_present(dev)) { 473 if (spin_trylock(&hw_stats->stats_lock)) { 474 mtk_stats_update_mac(mac); 475 spin_unlock(&hw_stats->stats_lock); 476 } 477 } 478 479 do { 480 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 481 storage->rx_packets = hw_stats->rx_packets; 482 storage->tx_packets = hw_stats->tx_packets; 483 storage->rx_bytes = hw_stats->rx_bytes; 484 storage->tx_bytes = hw_stats->tx_bytes; 485 storage->collisions = hw_stats->tx_collisions; 486 storage->rx_length_errors = hw_stats->rx_short_errors + 487 hw_stats->rx_long_errors; 488 storage->rx_over_errors = hw_stats->rx_overflow; 489 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 490 storage->rx_errors = hw_stats->rx_checksum_errors; 491 storage->tx_aborted_errors = hw_stats->tx_skip; 492 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 493 494 storage->tx_errors = dev->stats.tx_errors; 495 storage->rx_dropped = dev->stats.rx_dropped; 496 storage->tx_dropped = dev->stats.tx_dropped; 497 } 498 499 static inline int mtk_max_frag_size(int mtu) 500 { 501 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 502 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 503 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 504 505 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 506 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 507 } 508 509 static inline int mtk_max_buf_size(int frag_size) 510 { 511 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 512 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 513 514 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 515 516 return buf_size; 517 } 518 519 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 520 struct mtk_rx_dma *dma_rxd) 521 { 522 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 523 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 524 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 525 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 526 } 527 528 /* the qdma core needs scratch memory to be setup */ 529 static int mtk_init_fq_dma(struct mtk_eth *eth) 530 { 531 dma_addr_t phy_ring_tail; 532 int cnt = MTK_DMA_SIZE; 533 dma_addr_t dma_addr; 534 int i; 535 536 eth->scratch_ring = dma_alloc_coherent(eth->dev, 537 cnt * sizeof(struct mtk_tx_dma), 538 ð->phy_scratch_ring, 539 GFP_ATOMIC | __GFP_ZERO); 540 if (unlikely(!eth->scratch_ring)) 541 return -ENOMEM; 542 543 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 544 GFP_KERNEL); 545 if (unlikely(!eth->scratch_head)) 546 return -ENOMEM; 547 548 dma_addr = dma_map_single(eth->dev, 549 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 550 DMA_FROM_DEVICE); 551 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 552 return -ENOMEM; 553 554 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 555 phy_ring_tail = eth->phy_scratch_ring + 556 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 557 558 for (i = 0; i < cnt; i++) { 559 eth->scratch_ring[i].txd1 = 560 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 561 if (i < cnt - 1) 562 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 563 ((i + 1) * sizeof(struct mtk_tx_dma))); 564 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 565 } 566 567 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 568 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 569 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 570 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 571 572 return 0; 573 } 574 575 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 576 { 577 void *ret = ring->dma; 578 579 return ret + (desc - ring->phys); 580 } 581 582 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 583 struct mtk_tx_dma *txd) 584 { 585 int idx = txd - ring->dma; 586 587 return &ring->buf[idx]; 588 } 589 590 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 591 { 592 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 593 dma_unmap_single(eth->dev, 594 dma_unmap_addr(tx_buf, dma_addr0), 595 dma_unmap_len(tx_buf, dma_len0), 596 DMA_TO_DEVICE); 597 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 598 dma_unmap_page(eth->dev, 599 dma_unmap_addr(tx_buf, dma_addr0), 600 dma_unmap_len(tx_buf, dma_len0), 601 DMA_TO_DEVICE); 602 } 603 tx_buf->flags = 0; 604 if (tx_buf->skb && 605 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 606 dev_kfree_skb_any(tx_buf->skb); 607 tx_buf->skb = NULL; 608 } 609 610 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 611 int tx_num, struct mtk_tx_ring *ring, bool gso) 612 { 613 struct mtk_mac *mac = netdev_priv(dev); 614 struct mtk_eth *eth = mac->hw; 615 struct mtk_tx_dma *itxd, *txd; 616 struct mtk_tx_buf *tx_buf; 617 dma_addr_t mapped_addr; 618 unsigned int nr_frags; 619 int i, n_desc = 1; 620 u32 txd4 = 0, fport; 621 622 itxd = ring->next_free; 623 if (itxd == ring->last_free) 624 return -ENOMEM; 625 626 /* set the forward port */ 627 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 628 txd4 |= fport; 629 630 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 631 memset(tx_buf, 0, sizeof(*tx_buf)); 632 633 if (gso) 634 txd4 |= TX_DMA_TSO; 635 636 /* TX Checksum offload */ 637 if (skb->ip_summed == CHECKSUM_PARTIAL) 638 txd4 |= TX_DMA_CHKSUM; 639 640 /* VLAN header offload */ 641 if (skb_vlan_tag_present(skb)) 642 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 643 644 mapped_addr = dma_map_single(eth->dev, skb->data, 645 skb_headlen(skb), DMA_TO_DEVICE); 646 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 647 return -ENOMEM; 648 649 WRITE_ONCE(itxd->txd1, mapped_addr); 650 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 651 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 652 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb)); 653 654 /* TX SG offload */ 655 txd = itxd; 656 nr_frags = skb_shinfo(skb)->nr_frags; 657 for (i = 0; i < nr_frags; i++) { 658 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 659 unsigned int offset = 0; 660 int frag_size = skb_frag_size(frag); 661 662 while (frag_size) { 663 bool last_frag = false; 664 unsigned int frag_map_size; 665 666 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 667 if (txd == ring->last_free) 668 goto err_dma; 669 670 n_desc++; 671 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 672 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 673 frag_map_size, 674 DMA_TO_DEVICE); 675 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 676 goto err_dma; 677 678 if (i == nr_frags - 1 && 679 (frag_size - frag_map_size) == 0) 680 last_frag = true; 681 682 WRITE_ONCE(txd->txd1, mapped_addr); 683 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 684 TX_DMA_PLEN0(frag_map_size) | 685 last_frag * TX_DMA_LS0)); 686 WRITE_ONCE(txd->txd4, fport); 687 688 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 689 tx_buf = mtk_desc_to_tx_buf(ring, txd); 690 memset(tx_buf, 0, sizeof(*tx_buf)); 691 692 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 693 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 694 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 695 frag_size -= frag_map_size; 696 offset += frag_map_size; 697 } 698 } 699 700 /* store skb to cleanup */ 701 tx_buf->skb = skb; 702 703 WRITE_ONCE(itxd->txd4, txd4); 704 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 705 (!nr_frags * TX_DMA_LS0))); 706 707 netdev_sent_queue(dev, skb->len); 708 skb_tx_timestamp(skb); 709 710 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 711 atomic_sub(n_desc, &ring->free_count); 712 713 /* make sure that all changes to the dma ring are flushed before we 714 * continue 715 */ 716 wmb(); 717 718 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 719 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 720 721 return 0; 722 723 err_dma: 724 do { 725 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 726 727 /* unmap dma */ 728 mtk_tx_unmap(eth, tx_buf); 729 730 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 731 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 732 } while (itxd != txd); 733 734 return -ENOMEM; 735 } 736 737 static inline int mtk_cal_txd_req(struct sk_buff *skb) 738 { 739 int i, nfrags; 740 struct skb_frag_struct *frag; 741 742 nfrags = 1; 743 if (skb_is_gso(skb)) { 744 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 745 frag = &skb_shinfo(skb)->frags[i]; 746 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 747 } 748 } else { 749 nfrags += skb_shinfo(skb)->nr_frags; 750 } 751 752 return nfrags; 753 } 754 755 static int mtk_queue_stopped(struct mtk_eth *eth) 756 { 757 int i; 758 759 for (i = 0; i < MTK_MAC_COUNT; i++) { 760 if (!eth->netdev[i]) 761 continue; 762 if (netif_queue_stopped(eth->netdev[i])) 763 return 1; 764 } 765 766 return 0; 767 } 768 769 static void mtk_wake_queue(struct mtk_eth *eth) 770 { 771 int i; 772 773 for (i = 0; i < MTK_MAC_COUNT; i++) { 774 if (!eth->netdev[i]) 775 continue; 776 netif_wake_queue(eth->netdev[i]); 777 } 778 } 779 780 static void mtk_stop_queue(struct mtk_eth *eth) 781 { 782 int i; 783 784 for (i = 0; i < MTK_MAC_COUNT; i++) { 785 if (!eth->netdev[i]) 786 continue; 787 netif_stop_queue(eth->netdev[i]); 788 } 789 } 790 791 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 792 { 793 struct mtk_mac *mac = netdev_priv(dev); 794 struct mtk_eth *eth = mac->hw; 795 struct mtk_tx_ring *ring = ð->tx_ring; 796 struct net_device_stats *stats = &dev->stats; 797 bool gso = false; 798 int tx_num; 799 800 /* normally we can rely on the stack not calling this more than once, 801 * however we have 2 queues running on the same ring so we need to lock 802 * the ring access 803 */ 804 spin_lock(ð->page_lock); 805 806 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 807 goto drop; 808 809 tx_num = mtk_cal_txd_req(skb); 810 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 811 mtk_stop_queue(eth); 812 netif_err(eth, tx_queued, dev, 813 "Tx Ring full when queue awake!\n"); 814 spin_unlock(ð->page_lock); 815 return NETDEV_TX_BUSY; 816 } 817 818 /* TSO: fill MSS info in tcp checksum field */ 819 if (skb_is_gso(skb)) { 820 if (skb_cow_head(skb, 0)) { 821 netif_warn(eth, tx_err, dev, 822 "GSO expand head fail.\n"); 823 goto drop; 824 } 825 826 if (skb_shinfo(skb)->gso_type & 827 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 828 gso = true; 829 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 830 } 831 } 832 833 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 834 goto drop; 835 836 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 837 mtk_stop_queue(eth); 838 839 spin_unlock(ð->page_lock); 840 841 return NETDEV_TX_OK; 842 843 drop: 844 spin_unlock(ð->page_lock); 845 stats->tx_dropped++; 846 dev_kfree_skb_any(skb); 847 return NETDEV_TX_OK; 848 } 849 850 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 851 { 852 int i; 853 struct mtk_rx_ring *ring; 854 int idx; 855 856 if (!eth->hwlro) 857 return ð->rx_ring[0]; 858 859 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 860 ring = ð->rx_ring[i]; 861 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 862 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 863 ring->calc_idx_update = true; 864 return ring; 865 } 866 } 867 868 return NULL; 869 } 870 871 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 872 { 873 struct mtk_rx_ring *ring; 874 int i; 875 876 if (!eth->hwlro) { 877 ring = ð->rx_ring[0]; 878 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 879 } else { 880 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 881 ring = ð->rx_ring[i]; 882 if (ring->calc_idx_update) { 883 ring->calc_idx_update = false; 884 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 885 } 886 } 887 } 888 } 889 890 static int mtk_poll_rx(struct napi_struct *napi, int budget, 891 struct mtk_eth *eth) 892 { 893 struct mtk_rx_ring *ring; 894 int idx; 895 struct sk_buff *skb; 896 u8 *data, *new_data; 897 struct mtk_rx_dma *rxd, trxd; 898 int done = 0; 899 900 while (done < budget) { 901 struct net_device *netdev; 902 unsigned int pktlen; 903 dma_addr_t dma_addr; 904 int mac = 0; 905 906 ring = mtk_get_rx_ring(eth); 907 if (unlikely(!ring)) 908 goto rx_done; 909 910 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size); 911 rxd = &ring->dma[idx]; 912 data = ring->data[idx]; 913 914 mtk_rx_get_desc(&trxd, rxd); 915 if (!(trxd.rxd2 & RX_DMA_DONE)) 916 break; 917 918 /* find out which mac the packet come from. values start at 1 */ 919 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 920 RX_DMA_FPORT_MASK; 921 mac--; 922 923 netdev = eth->netdev[mac]; 924 925 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 926 goto release_desc; 927 928 /* alloc new buffer */ 929 new_data = napi_alloc_frag(ring->frag_size); 930 if (unlikely(!new_data)) { 931 netdev->stats.rx_dropped++; 932 goto release_desc; 933 } 934 dma_addr = dma_map_single(eth->dev, 935 new_data + NET_SKB_PAD, 936 ring->buf_size, 937 DMA_FROM_DEVICE); 938 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 939 skb_free_frag(new_data); 940 netdev->stats.rx_dropped++; 941 goto release_desc; 942 } 943 944 /* receive data */ 945 skb = build_skb(data, ring->frag_size); 946 if (unlikely(!skb)) { 947 skb_free_frag(new_data); 948 netdev->stats.rx_dropped++; 949 goto release_desc; 950 } 951 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 952 953 dma_unmap_single(eth->dev, trxd.rxd1, 954 ring->buf_size, DMA_FROM_DEVICE); 955 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 956 skb->dev = netdev; 957 skb_put(skb, pktlen); 958 if (trxd.rxd4 & RX_DMA_L4_VALID) 959 skb->ip_summed = CHECKSUM_UNNECESSARY; 960 else 961 skb_checksum_none_assert(skb); 962 skb->protocol = eth_type_trans(skb, netdev); 963 964 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 965 RX_DMA_VID(trxd.rxd3)) 966 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 967 RX_DMA_VID(trxd.rxd3)); 968 napi_gro_receive(napi, skb); 969 970 ring->data[idx] = new_data; 971 rxd->rxd1 = (unsigned int)dma_addr; 972 973 release_desc: 974 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 975 976 ring->calc_idx = idx; 977 978 done++; 979 } 980 981 rx_done: 982 if (done) { 983 /* make sure that all changes to the dma ring are flushed before 984 * we continue 985 */ 986 wmb(); 987 mtk_update_rx_cpu_idx(eth); 988 } 989 990 return done; 991 } 992 993 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 994 { 995 struct mtk_tx_ring *ring = ð->tx_ring; 996 struct mtk_tx_dma *desc; 997 struct sk_buff *skb; 998 struct mtk_tx_buf *tx_buf; 999 unsigned int done[MTK_MAX_DEVS]; 1000 unsigned int bytes[MTK_MAX_DEVS]; 1001 u32 cpu, dma; 1002 static int condition; 1003 int total = 0, i; 1004 1005 memset(done, 0, sizeof(done)); 1006 memset(bytes, 0, sizeof(bytes)); 1007 1008 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1009 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1010 1011 desc = mtk_qdma_phys_to_virt(ring, cpu); 1012 1013 while ((cpu != dma) && budget) { 1014 u32 next_cpu = desc->txd2; 1015 int mac; 1016 1017 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1018 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1019 break; 1020 1021 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) & 1022 TX_DMA_FPORT_MASK; 1023 mac--; 1024 1025 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1026 skb = tx_buf->skb; 1027 if (!skb) { 1028 condition = 1; 1029 break; 1030 } 1031 1032 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1033 bytes[mac] += skb->len; 1034 done[mac]++; 1035 budget--; 1036 } 1037 mtk_tx_unmap(eth, tx_buf); 1038 1039 ring->last_free = desc; 1040 atomic_inc(&ring->free_count); 1041 1042 cpu = next_cpu; 1043 } 1044 1045 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1046 1047 for (i = 0; i < MTK_MAC_COUNT; i++) { 1048 if (!eth->netdev[i] || !done[i]) 1049 continue; 1050 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1051 total += done[i]; 1052 } 1053 1054 if (mtk_queue_stopped(eth) && 1055 (atomic_read(&ring->free_count) > ring->thresh)) 1056 mtk_wake_queue(eth); 1057 1058 return total; 1059 } 1060 1061 static void mtk_handle_status_irq(struct mtk_eth *eth) 1062 { 1063 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1064 1065 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1066 mtk_stats_update(eth); 1067 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1068 MTK_INT_STATUS2); 1069 } 1070 } 1071 1072 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1073 { 1074 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1075 u32 status, mask; 1076 int tx_done = 0; 1077 1078 mtk_handle_status_irq(eth); 1079 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 1080 tx_done = mtk_poll_tx(eth, budget); 1081 1082 if (unlikely(netif_msg_intr(eth))) { 1083 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1084 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1085 dev_info(eth->dev, 1086 "done tx %d, intr 0x%08x/0x%x\n", 1087 tx_done, status, mask); 1088 } 1089 1090 if (tx_done == budget) 1091 return budget; 1092 1093 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1094 if (status & MTK_TX_DONE_INT) 1095 return budget; 1096 1097 napi_complete(napi); 1098 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1099 1100 return tx_done; 1101 } 1102 1103 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1104 { 1105 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1106 u32 status, mask; 1107 int rx_done = 0; 1108 int remain_budget = budget; 1109 1110 mtk_handle_status_irq(eth); 1111 1112 poll_again: 1113 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1114 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1115 1116 if (unlikely(netif_msg_intr(eth))) { 1117 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1118 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1119 dev_info(eth->dev, 1120 "done rx %d, intr 0x%08x/0x%x\n", 1121 rx_done, status, mask); 1122 } 1123 if (rx_done == remain_budget) 1124 return budget; 1125 1126 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1127 if (status & MTK_RX_DONE_INT) { 1128 remain_budget -= rx_done; 1129 goto poll_again; 1130 } 1131 napi_complete(napi); 1132 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1133 1134 return rx_done + budget - remain_budget; 1135 } 1136 1137 static int mtk_tx_alloc(struct mtk_eth *eth) 1138 { 1139 struct mtk_tx_ring *ring = ð->tx_ring; 1140 int i, sz = sizeof(*ring->dma); 1141 1142 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1143 GFP_KERNEL); 1144 if (!ring->buf) 1145 goto no_tx_mem; 1146 1147 ring->dma = dma_alloc_coherent(eth->dev, 1148 MTK_DMA_SIZE * sz, 1149 &ring->phys, 1150 GFP_ATOMIC | __GFP_ZERO); 1151 if (!ring->dma) 1152 goto no_tx_mem; 1153 1154 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1155 for (i = 0; i < MTK_DMA_SIZE; i++) { 1156 int next = (i + 1) % MTK_DMA_SIZE; 1157 u32 next_ptr = ring->phys + next * sz; 1158 1159 ring->dma[i].txd2 = next_ptr; 1160 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1161 } 1162 1163 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1164 ring->next_free = &ring->dma[0]; 1165 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1166 ring->thresh = MAX_SKB_FRAGS; 1167 1168 /* make sure that all changes to the dma ring are flushed before we 1169 * continue 1170 */ 1171 wmb(); 1172 1173 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1174 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1175 mtk_w32(eth, 1176 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1177 MTK_QTX_CRX_PTR); 1178 mtk_w32(eth, 1179 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1180 MTK_QTX_DRX_PTR); 1181 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1182 1183 return 0; 1184 1185 no_tx_mem: 1186 return -ENOMEM; 1187 } 1188 1189 static void mtk_tx_clean(struct mtk_eth *eth) 1190 { 1191 struct mtk_tx_ring *ring = ð->tx_ring; 1192 int i; 1193 1194 if (ring->buf) { 1195 for (i = 0; i < MTK_DMA_SIZE; i++) 1196 mtk_tx_unmap(eth, &ring->buf[i]); 1197 kfree(ring->buf); 1198 ring->buf = NULL; 1199 } 1200 1201 if (ring->dma) { 1202 dma_free_coherent(eth->dev, 1203 MTK_DMA_SIZE * sizeof(*ring->dma), 1204 ring->dma, 1205 ring->phys); 1206 ring->dma = NULL; 1207 } 1208 } 1209 1210 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1211 { 1212 struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; 1213 int rx_data_len, rx_dma_size; 1214 int i; 1215 1216 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1217 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1218 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1219 } else { 1220 rx_data_len = ETH_DATA_LEN; 1221 rx_dma_size = MTK_DMA_SIZE; 1222 } 1223 1224 ring->frag_size = mtk_max_frag_size(rx_data_len); 1225 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1226 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1227 GFP_KERNEL); 1228 if (!ring->data) 1229 return -ENOMEM; 1230 1231 for (i = 0; i < rx_dma_size; i++) { 1232 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1233 if (!ring->data[i]) 1234 return -ENOMEM; 1235 } 1236 1237 ring->dma = dma_alloc_coherent(eth->dev, 1238 rx_dma_size * sizeof(*ring->dma), 1239 &ring->phys, 1240 GFP_ATOMIC | __GFP_ZERO); 1241 if (!ring->dma) 1242 return -ENOMEM; 1243 1244 for (i = 0; i < rx_dma_size; i++) { 1245 dma_addr_t dma_addr = dma_map_single(eth->dev, 1246 ring->data[i] + NET_SKB_PAD, 1247 ring->buf_size, 1248 DMA_FROM_DEVICE); 1249 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1250 return -ENOMEM; 1251 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1252 1253 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1254 } 1255 ring->dma_size = rx_dma_size; 1256 ring->calc_idx_update = false; 1257 ring->calc_idx = rx_dma_size - 1; 1258 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1259 /* make sure that all changes to the dma ring are flushed before we 1260 * continue 1261 */ 1262 wmb(); 1263 1264 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no)); 1265 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no)); 1266 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1267 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX); 1268 1269 return 0; 1270 } 1271 1272 static void mtk_rx_clean(struct mtk_eth *eth, int ring_no) 1273 { 1274 struct mtk_rx_ring *ring = ð->rx_ring[ring_no]; 1275 int i; 1276 1277 if (ring->data && ring->dma) { 1278 for (i = 0; i < ring->dma_size; i++) { 1279 if (!ring->data[i]) 1280 continue; 1281 if (!ring->dma[i].rxd1) 1282 continue; 1283 dma_unmap_single(eth->dev, 1284 ring->dma[i].rxd1, 1285 ring->buf_size, 1286 DMA_FROM_DEVICE); 1287 skb_free_frag(ring->data[i]); 1288 } 1289 kfree(ring->data); 1290 ring->data = NULL; 1291 } 1292 1293 if (ring->dma) { 1294 dma_free_coherent(eth->dev, 1295 ring->dma_size * sizeof(*ring->dma), 1296 ring->dma, 1297 ring->phys); 1298 ring->dma = NULL; 1299 } 1300 } 1301 1302 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1303 { 1304 int i; 1305 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1306 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1307 1308 /* set LRO rings to auto-learn modes */ 1309 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1310 1311 /* validate LRO ring */ 1312 ring_ctrl_dw2 |= MTK_RING_VLD; 1313 1314 /* set AGE timer (unit: 20us) */ 1315 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1316 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1317 1318 /* set max AGG timer (unit: 20us) */ 1319 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1320 1321 /* set max LRO AGG count */ 1322 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1323 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1324 1325 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1326 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1327 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1328 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1329 } 1330 1331 /* IPv4 checksum update enable */ 1332 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1333 1334 /* switch priority comparison to packet count mode */ 1335 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1336 1337 /* bandwidth threshold setting */ 1338 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1339 1340 /* auto-learn score delta setting */ 1341 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1342 1343 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1344 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1345 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1346 1347 /* set HW LRO mode & the max aggregation count for rx packets */ 1348 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1349 1350 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1351 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1352 1353 /* enable HW LRO */ 1354 lro_ctrl_dw0 |= MTK_LRO_EN; 1355 1356 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1357 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1358 1359 return 0; 1360 } 1361 1362 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1363 { 1364 int i; 1365 u32 val; 1366 1367 /* relinquish lro rings, flush aggregated packets */ 1368 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1369 1370 /* wait for relinquishments done */ 1371 for (i = 0; i < 10; i++) { 1372 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1373 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1374 msleep(20); 1375 continue; 1376 } 1377 break; 1378 } 1379 1380 /* invalidate lro rings */ 1381 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1382 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1383 1384 /* disable HW LRO */ 1385 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1386 } 1387 1388 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1389 { 1390 u32 reg_val; 1391 1392 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1393 1394 /* invalidate the IP setting */ 1395 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1396 1397 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1398 1399 /* validate the IP setting */ 1400 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1401 } 1402 1403 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1404 { 1405 u32 reg_val; 1406 1407 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1408 1409 /* invalidate the IP setting */ 1410 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1411 1412 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1413 } 1414 1415 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1416 { 1417 int cnt = 0; 1418 int i; 1419 1420 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1421 if (mac->hwlro_ip[i]) 1422 cnt++; 1423 } 1424 1425 return cnt; 1426 } 1427 1428 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1429 struct ethtool_rxnfc *cmd) 1430 { 1431 struct ethtool_rx_flow_spec *fsp = 1432 (struct ethtool_rx_flow_spec *)&cmd->fs; 1433 struct mtk_mac *mac = netdev_priv(dev); 1434 struct mtk_eth *eth = mac->hw; 1435 int hwlro_idx; 1436 1437 if ((fsp->flow_type != TCP_V4_FLOW) || 1438 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1439 (fsp->location > 1)) 1440 return -EINVAL; 1441 1442 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1443 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1444 1445 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1446 1447 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1448 1449 return 0; 1450 } 1451 1452 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1453 struct ethtool_rxnfc *cmd) 1454 { 1455 struct ethtool_rx_flow_spec *fsp = 1456 (struct ethtool_rx_flow_spec *)&cmd->fs; 1457 struct mtk_mac *mac = netdev_priv(dev); 1458 struct mtk_eth *eth = mac->hw; 1459 int hwlro_idx; 1460 1461 if (fsp->location > 1) 1462 return -EINVAL; 1463 1464 mac->hwlro_ip[fsp->location] = 0; 1465 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1466 1467 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1468 1469 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1470 1471 return 0; 1472 } 1473 1474 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1475 { 1476 struct mtk_mac *mac = netdev_priv(dev); 1477 struct mtk_eth *eth = mac->hw; 1478 int i, hwlro_idx; 1479 1480 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1481 mac->hwlro_ip[i] = 0; 1482 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1483 1484 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1485 } 1486 1487 mac->hwlro_ip_cnt = 0; 1488 } 1489 1490 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1491 struct ethtool_rxnfc *cmd) 1492 { 1493 struct mtk_mac *mac = netdev_priv(dev); 1494 struct ethtool_rx_flow_spec *fsp = 1495 (struct ethtool_rx_flow_spec *)&cmd->fs; 1496 1497 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1498 fsp->flow_type = TCP_V4_FLOW; 1499 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1500 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1501 1502 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1503 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1504 fsp->h_u.tcp_ip4_spec.psrc = 0; 1505 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1506 fsp->h_u.tcp_ip4_spec.pdst = 0; 1507 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1508 fsp->h_u.tcp_ip4_spec.tos = 0; 1509 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1510 1511 return 0; 1512 } 1513 1514 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1515 struct ethtool_rxnfc *cmd, 1516 u32 *rule_locs) 1517 { 1518 struct mtk_mac *mac = netdev_priv(dev); 1519 int cnt = 0; 1520 int i; 1521 1522 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1523 if (mac->hwlro_ip[i]) { 1524 rule_locs[cnt] = i; 1525 cnt++; 1526 } 1527 } 1528 1529 cmd->rule_cnt = cnt; 1530 1531 return 0; 1532 } 1533 1534 static netdev_features_t mtk_fix_features(struct net_device *dev, 1535 netdev_features_t features) 1536 { 1537 if (!(features & NETIF_F_LRO)) { 1538 struct mtk_mac *mac = netdev_priv(dev); 1539 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1540 1541 if (ip_cnt) { 1542 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1543 1544 features |= NETIF_F_LRO; 1545 } 1546 } 1547 1548 return features; 1549 } 1550 1551 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1552 { 1553 int err = 0; 1554 1555 if (!((dev->features ^ features) & NETIF_F_LRO)) 1556 return 0; 1557 1558 if (!(features & NETIF_F_LRO)) 1559 mtk_hwlro_netdev_disable(dev); 1560 1561 return err; 1562 } 1563 1564 /* wait for DMA to finish whatever it is doing before we start using it again */ 1565 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1566 { 1567 unsigned long t_start = jiffies; 1568 1569 while (1) { 1570 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1571 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1572 return 0; 1573 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1574 break; 1575 } 1576 1577 dev_err(eth->dev, "DMA init timeout\n"); 1578 return -1; 1579 } 1580 1581 static int mtk_dma_init(struct mtk_eth *eth) 1582 { 1583 int err; 1584 u32 i; 1585 1586 if (mtk_dma_busy_wait(eth)) 1587 return -EBUSY; 1588 1589 /* QDMA needs scratch memory for internal reordering of the 1590 * descriptors 1591 */ 1592 err = mtk_init_fq_dma(eth); 1593 if (err) 1594 return err; 1595 1596 err = mtk_tx_alloc(eth); 1597 if (err) 1598 return err; 1599 1600 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 1601 if (err) 1602 return err; 1603 1604 if (eth->hwlro) { 1605 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1606 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 1607 if (err) 1608 return err; 1609 } 1610 err = mtk_hwlro_rx_init(eth); 1611 if (err) 1612 return err; 1613 } 1614 1615 /* Enable random early drop and set drop threshold automatically */ 1616 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1617 MTK_QDMA_FC_THRES); 1618 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1619 1620 return 0; 1621 } 1622 1623 static void mtk_dma_free(struct mtk_eth *eth) 1624 { 1625 int i; 1626 1627 for (i = 0; i < MTK_MAC_COUNT; i++) 1628 if (eth->netdev[i]) 1629 netdev_reset_queue(eth->netdev[i]); 1630 if (eth->scratch_ring) { 1631 dma_free_coherent(eth->dev, 1632 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1633 eth->scratch_ring, 1634 eth->phy_scratch_ring); 1635 eth->scratch_ring = NULL; 1636 eth->phy_scratch_ring = 0; 1637 } 1638 mtk_tx_clean(eth); 1639 mtk_rx_clean(eth, 0); 1640 1641 if (eth->hwlro) { 1642 mtk_hwlro_rx_uninit(eth); 1643 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1644 mtk_rx_clean(eth, i); 1645 } 1646 1647 kfree(eth->scratch_head); 1648 } 1649 1650 static void mtk_tx_timeout(struct net_device *dev) 1651 { 1652 struct mtk_mac *mac = netdev_priv(dev); 1653 struct mtk_eth *eth = mac->hw; 1654 1655 eth->netdev[mac->id]->stats.tx_errors++; 1656 netif_err(eth, tx_err, dev, 1657 "transmit timed out\n"); 1658 schedule_work(ð->pending_work); 1659 } 1660 1661 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 1662 { 1663 struct mtk_eth *eth = _eth; 1664 1665 if (likely(napi_schedule_prep(ð->rx_napi))) { 1666 __napi_schedule(ð->rx_napi); 1667 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1668 } 1669 1670 return IRQ_HANDLED; 1671 } 1672 1673 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 1674 { 1675 struct mtk_eth *eth = _eth; 1676 1677 if (likely(napi_schedule_prep(ð->tx_napi))) { 1678 __napi_schedule(ð->tx_napi); 1679 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1680 } 1681 1682 return IRQ_HANDLED; 1683 } 1684 1685 #ifdef CONFIG_NET_POLL_CONTROLLER 1686 static void mtk_poll_controller(struct net_device *dev) 1687 { 1688 struct mtk_mac *mac = netdev_priv(dev); 1689 struct mtk_eth *eth = mac->hw; 1690 1691 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1692 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1693 mtk_handle_irq_rx(eth->irq[2], dev); 1694 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1695 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1696 } 1697 #endif 1698 1699 static int mtk_start_dma(struct mtk_eth *eth) 1700 { 1701 int err; 1702 1703 err = mtk_dma_init(eth); 1704 if (err) { 1705 mtk_dma_free(eth); 1706 return err; 1707 } 1708 1709 mtk_w32(eth, 1710 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 1711 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO, 1712 MTK_QDMA_GLO_CFG); 1713 1714 mtk_w32(eth, 1715 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 1716 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 1717 MTK_PDMA_GLO_CFG); 1718 1719 return 0; 1720 } 1721 1722 static int mtk_open(struct net_device *dev) 1723 { 1724 struct mtk_mac *mac = netdev_priv(dev); 1725 struct mtk_eth *eth = mac->hw; 1726 1727 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1728 if (!atomic_read(ð->dma_refcnt)) { 1729 int err = mtk_start_dma(eth); 1730 1731 if (err) 1732 return err; 1733 1734 napi_enable(ð->tx_napi); 1735 napi_enable(ð->rx_napi); 1736 mtk_irq_enable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1737 mtk_irq_enable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1738 } 1739 atomic_inc(ð->dma_refcnt); 1740 1741 phy_start(dev->phydev); 1742 netif_start_queue(dev); 1743 1744 return 0; 1745 } 1746 1747 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1748 { 1749 u32 val; 1750 int i; 1751 1752 /* stop the dma engine */ 1753 spin_lock_bh(ð->page_lock); 1754 val = mtk_r32(eth, glo_cfg); 1755 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1756 glo_cfg); 1757 spin_unlock_bh(ð->page_lock); 1758 1759 /* wait for dma stop */ 1760 for (i = 0; i < 10; i++) { 1761 val = mtk_r32(eth, glo_cfg); 1762 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1763 msleep(20); 1764 continue; 1765 } 1766 break; 1767 } 1768 } 1769 1770 static int mtk_stop(struct net_device *dev) 1771 { 1772 struct mtk_mac *mac = netdev_priv(dev); 1773 struct mtk_eth *eth = mac->hw; 1774 1775 netif_tx_disable(dev); 1776 phy_stop(dev->phydev); 1777 1778 /* only shutdown DMA if this is the last user */ 1779 if (!atomic_dec_and_test(ð->dma_refcnt)) 1780 return 0; 1781 1782 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, MTK_TX_DONE_INT); 1783 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, MTK_RX_DONE_INT); 1784 napi_disable(ð->tx_napi); 1785 napi_disable(ð->rx_napi); 1786 1787 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1788 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 1789 1790 mtk_dma_free(eth); 1791 1792 return 0; 1793 } 1794 1795 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 1796 { 1797 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1798 reset_bits, 1799 reset_bits); 1800 1801 usleep_range(1000, 1100); 1802 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 1803 reset_bits, 1804 ~reset_bits); 1805 mdelay(10); 1806 } 1807 1808 static int mtk_hw_init(struct mtk_eth *eth) 1809 { 1810 int i, val; 1811 1812 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 1813 return 0; 1814 1815 pm_runtime_enable(eth->dev); 1816 pm_runtime_get_sync(eth->dev); 1817 1818 clk_prepare_enable(eth->clks[MTK_CLK_ETHIF]); 1819 clk_prepare_enable(eth->clks[MTK_CLK_ESW]); 1820 clk_prepare_enable(eth->clks[MTK_CLK_GP1]); 1821 clk_prepare_enable(eth->clks[MTK_CLK_GP2]); 1822 ethsys_reset(eth, RSTCTRL_FE); 1823 ethsys_reset(eth, RSTCTRL_PPE); 1824 1825 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 1826 for (i = 0; i < MTK_MAC_COUNT; i++) { 1827 if (!eth->mac[i]) 1828 continue; 1829 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id); 1830 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id); 1831 } 1832 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 1833 1834 /* Set GE2 driving and slew rate */ 1835 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1836 1837 /* set GE2 TDSEL */ 1838 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1839 1840 /* set GE2 TUNE */ 1841 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1842 1843 /* GE1, Force 1000M/FD, FC ON */ 1844 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1845 1846 /* GE2, Force 1000M/FD, FC ON */ 1847 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1848 1849 /* Enable RX VLan Offloading */ 1850 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1851 1852 /* disable delay and normal interrupt */ 1853 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1854 mtk_w32(eth, 0, MTK_PDMA_DELAY_INT); 1855 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0); 1856 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0); 1857 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1858 mtk_w32(eth, 0, MTK_RST_GL); 1859 1860 /* FE int grouping */ 1861 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 1862 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 1863 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 1864 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 1865 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 1866 1867 for (i = 0; i < 2; i++) { 1868 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1869 1870 /* setup the forward port to send frame to PDMA */ 1871 val &= ~0xffff; 1872 1873 /* Enable RX checksum */ 1874 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1875 1876 /* setup the mac dma */ 1877 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1878 } 1879 1880 return 0; 1881 } 1882 1883 static int mtk_hw_deinit(struct mtk_eth *eth) 1884 { 1885 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 1886 return 0; 1887 1888 clk_disable_unprepare(eth->clks[MTK_CLK_GP2]); 1889 clk_disable_unprepare(eth->clks[MTK_CLK_GP1]); 1890 clk_disable_unprepare(eth->clks[MTK_CLK_ESW]); 1891 clk_disable_unprepare(eth->clks[MTK_CLK_ETHIF]); 1892 1893 pm_runtime_put_sync(eth->dev); 1894 pm_runtime_disable(eth->dev); 1895 1896 return 0; 1897 } 1898 1899 static int __init mtk_init(struct net_device *dev) 1900 { 1901 struct mtk_mac *mac = netdev_priv(dev); 1902 struct mtk_eth *eth = mac->hw; 1903 const char *mac_addr; 1904 1905 mac_addr = of_get_mac_address(mac->of_node); 1906 if (mac_addr) 1907 ether_addr_copy(dev->dev_addr, mac_addr); 1908 1909 /* If the mac address is invalid, use random mac address */ 1910 if (!is_valid_ether_addr(dev->dev_addr)) { 1911 random_ether_addr(dev->dev_addr); 1912 dev_err(eth->dev, "generated random MAC address %pM\n", 1913 dev->dev_addr); 1914 dev->addr_assign_type = NET_ADDR_RANDOM; 1915 } 1916 1917 return mtk_phy_connect(dev); 1918 } 1919 1920 static void mtk_uninit(struct net_device *dev) 1921 { 1922 struct mtk_mac *mac = netdev_priv(dev); 1923 struct mtk_eth *eth = mac->hw; 1924 1925 phy_disconnect(dev->phydev); 1926 if (of_phy_is_fixed_link(mac->of_node)) 1927 of_phy_deregister_fixed_link(mac->of_node); 1928 mtk_irq_disable(eth, MTK_QDMA_INT_MASK, ~0); 1929 mtk_irq_disable(eth, MTK_PDMA_INT_MASK, ~0); 1930 } 1931 1932 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1933 { 1934 switch (cmd) { 1935 case SIOCGMIIPHY: 1936 case SIOCGMIIREG: 1937 case SIOCSMIIREG: 1938 return phy_mii_ioctl(dev->phydev, ifr, cmd); 1939 default: 1940 break; 1941 } 1942 1943 return -EOPNOTSUPP; 1944 } 1945 1946 static void mtk_pending_work(struct work_struct *work) 1947 { 1948 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 1949 int err, i; 1950 unsigned long restart = 0; 1951 1952 rtnl_lock(); 1953 1954 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 1955 1956 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 1957 cpu_relax(); 1958 1959 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 1960 /* stop all devices to make sure that dma is properly shut down */ 1961 for (i = 0; i < MTK_MAC_COUNT; i++) { 1962 if (!eth->netdev[i]) 1963 continue; 1964 mtk_stop(eth->netdev[i]); 1965 __set_bit(i, &restart); 1966 } 1967 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 1968 1969 /* restart underlying hardware such as power, clock, pin mux 1970 * and the connected phy 1971 */ 1972 mtk_hw_deinit(eth); 1973 1974 if (eth->dev->pins) 1975 pinctrl_select_state(eth->dev->pins->p, 1976 eth->dev->pins->default_state); 1977 mtk_hw_init(eth); 1978 1979 for (i = 0; i < MTK_MAC_COUNT; i++) { 1980 if (!eth->mac[i] || 1981 of_phy_is_fixed_link(eth->mac[i]->of_node)) 1982 continue; 1983 err = phy_init_hw(eth->netdev[i]->phydev); 1984 if (err) 1985 dev_err(eth->dev, "%s: PHY init failed.\n", 1986 eth->netdev[i]->name); 1987 } 1988 1989 /* restart DMA and enable IRQs */ 1990 for (i = 0; i < MTK_MAC_COUNT; i++) { 1991 if (!test_bit(i, &restart)) 1992 continue; 1993 err = mtk_open(eth->netdev[i]); 1994 if (err) { 1995 netif_alert(eth, ifup, eth->netdev[i], 1996 "Driver up/down cycle failed, closing device.\n"); 1997 dev_close(eth->netdev[i]); 1998 } 1999 } 2000 2001 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2002 2003 clear_bit_unlock(MTK_RESETTING, ð->state); 2004 2005 rtnl_unlock(); 2006 } 2007 2008 static int mtk_free_dev(struct mtk_eth *eth) 2009 { 2010 int i; 2011 2012 for (i = 0; i < MTK_MAC_COUNT; i++) { 2013 if (!eth->netdev[i]) 2014 continue; 2015 free_netdev(eth->netdev[i]); 2016 } 2017 2018 return 0; 2019 } 2020 2021 static int mtk_unreg_dev(struct mtk_eth *eth) 2022 { 2023 int i; 2024 2025 for (i = 0; i < MTK_MAC_COUNT; i++) { 2026 if (!eth->netdev[i]) 2027 continue; 2028 unregister_netdev(eth->netdev[i]); 2029 } 2030 2031 return 0; 2032 } 2033 2034 static int mtk_cleanup(struct mtk_eth *eth) 2035 { 2036 mtk_unreg_dev(eth); 2037 mtk_free_dev(eth); 2038 cancel_work_sync(ð->pending_work); 2039 2040 return 0; 2041 } 2042 2043 static int mtk_get_link_ksettings(struct net_device *ndev, 2044 struct ethtool_link_ksettings *cmd) 2045 { 2046 struct mtk_mac *mac = netdev_priv(ndev); 2047 2048 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2049 return -EBUSY; 2050 2051 return phy_ethtool_ksettings_get(ndev->phydev, cmd); 2052 } 2053 2054 static int mtk_set_link_ksettings(struct net_device *ndev, 2055 const struct ethtool_link_ksettings *cmd) 2056 { 2057 struct mtk_mac *mac = netdev_priv(ndev); 2058 2059 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2060 return -EBUSY; 2061 2062 return phy_ethtool_ksettings_set(ndev->phydev, cmd); 2063 } 2064 2065 static void mtk_get_drvinfo(struct net_device *dev, 2066 struct ethtool_drvinfo *info) 2067 { 2068 struct mtk_mac *mac = netdev_priv(dev); 2069 2070 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2071 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2072 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2073 } 2074 2075 static u32 mtk_get_msglevel(struct net_device *dev) 2076 { 2077 struct mtk_mac *mac = netdev_priv(dev); 2078 2079 return mac->hw->msg_enable; 2080 } 2081 2082 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2083 { 2084 struct mtk_mac *mac = netdev_priv(dev); 2085 2086 mac->hw->msg_enable = value; 2087 } 2088 2089 static int mtk_nway_reset(struct net_device *dev) 2090 { 2091 struct mtk_mac *mac = netdev_priv(dev); 2092 2093 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2094 return -EBUSY; 2095 2096 return genphy_restart_aneg(dev->phydev); 2097 } 2098 2099 static u32 mtk_get_link(struct net_device *dev) 2100 { 2101 struct mtk_mac *mac = netdev_priv(dev); 2102 int err; 2103 2104 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2105 return -EBUSY; 2106 2107 err = genphy_update_link(dev->phydev); 2108 if (err) 2109 return ethtool_op_get_link(dev); 2110 2111 return dev->phydev->link; 2112 } 2113 2114 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2115 { 2116 int i; 2117 2118 switch (stringset) { 2119 case ETH_SS_STATS: 2120 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2121 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2122 data += ETH_GSTRING_LEN; 2123 } 2124 break; 2125 } 2126 } 2127 2128 static int mtk_get_sset_count(struct net_device *dev, int sset) 2129 { 2130 switch (sset) { 2131 case ETH_SS_STATS: 2132 return ARRAY_SIZE(mtk_ethtool_stats); 2133 default: 2134 return -EOPNOTSUPP; 2135 } 2136 } 2137 2138 static void mtk_get_ethtool_stats(struct net_device *dev, 2139 struct ethtool_stats *stats, u64 *data) 2140 { 2141 struct mtk_mac *mac = netdev_priv(dev); 2142 struct mtk_hw_stats *hwstats = mac->hw_stats; 2143 u64 *data_src, *data_dst; 2144 unsigned int start; 2145 int i; 2146 2147 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2148 return; 2149 2150 if (netif_running(dev) && netif_device_present(dev)) { 2151 if (spin_trylock(&hwstats->stats_lock)) { 2152 mtk_stats_update_mac(mac); 2153 spin_unlock(&hwstats->stats_lock); 2154 } 2155 } 2156 2157 data_src = (u64 *)hwstats; 2158 2159 do { 2160 data_dst = data; 2161 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2162 2163 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2164 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2165 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2166 } 2167 2168 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2169 u32 *rule_locs) 2170 { 2171 int ret = -EOPNOTSUPP; 2172 2173 switch (cmd->cmd) { 2174 case ETHTOOL_GRXRINGS: 2175 if (dev->features & NETIF_F_LRO) { 2176 cmd->data = MTK_MAX_RX_RING_NUM; 2177 ret = 0; 2178 } 2179 break; 2180 case ETHTOOL_GRXCLSRLCNT: 2181 if (dev->features & NETIF_F_LRO) { 2182 struct mtk_mac *mac = netdev_priv(dev); 2183 2184 cmd->rule_cnt = mac->hwlro_ip_cnt; 2185 ret = 0; 2186 } 2187 break; 2188 case ETHTOOL_GRXCLSRULE: 2189 if (dev->features & NETIF_F_LRO) 2190 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2191 break; 2192 case ETHTOOL_GRXCLSRLALL: 2193 if (dev->features & NETIF_F_LRO) 2194 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2195 rule_locs); 2196 break; 2197 default: 2198 break; 2199 } 2200 2201 return ret; 2202 } 2203 2204 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2205 { 2206 int ret = -EOPNOTSUPP; 2207 2208 switch (cmd->cmd) { 2209 case ETHTOOL_SRXCLSRLINS: 2210 if (dev->features & NETIF_F_LRO) 2211 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2212 break; 2213 case ETHTOOL_SRXCLSRLDEL: 2214 if (dev->features & NETIF_F_LRO) 2215 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2216 break; 2217 default: 2218 break; 2219 } 2220 2221 return ret; 2222 } 2223 2224 static const struct ethtool_ops mtk_ethtool_ops = { 2225 .get_link_ksettings = mtk_get_link_ksettings, 2226 .set_link_ksettings = mtk_set_link_ksettings, 2227 .get_drvinfo = mtk_get_drvinfo, 2228 .get_msglevel = mtk_get_msglevel, 2229 .set_msglevel = mtk_set_msglevel, 2230 .nway_reset = mtk_nway_reset, 2231 .get_link = mtk_get_link, 2232 .get_strings = mtk_get_strings, 2233 .get_sset_count = mtk_get_sset_count, 2234 .get_ethtool_stats = mtk_get_ethtool_stats, 2235 .get_rxnfc = mtk_get_rxnfc, 2236 .set_rxnfc = mtk_set_rxnfc, 2237 }; 2238 2239 static const struct net_device_ops mtk_netdev_ops = { 2240 .ndo_init = mtk_init, 2241 .ndo_uninit = mtk_uninit, 2242 .ndo_open = mtk_open, 2243 .ndo_stop = mtk_stop, 2244 .ndo_start_xmit = mtk_start_xmit, 2245 .ndo_set_mac_address = mtk_set_mac_address, 2246 .ndo_validate_addr = eth_validate_addr, 2247 .ndo_do_ioctl = mtk_do_ioctl, 2248 .ndo_tx_timeout = mtk_tx_timeout, 2249 .ndo_get_stats64 = mtk_get_stats64, 2250 .ndo_fix_features = mtk_fix_features, 2251 .ndo_set_features = mtk_set_features, 2252 #ifdef CONFIG_NET_POLL_CONTROLLER 2253 .ndo_poll_controller = mtk_poll_controller, 2254 #endif 2255 }; 2256 2257 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2258 { 2259 struct mtk_mac *mac; 2260 const __be32 *_id = of_get_property(np, "reg", NULL); 2261 int id, err; 2262 2263 if (!_id) { 2264 dev_err(eth->dev, "missing mac id\n"); 2265 return -EINVAL; 2266 } 2267 2268 id = be32_to_cpup(_id); 2269 if (id >= MTK_MAC_COUNT) { 2270 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2271 return -EINVAL; 2272 } 2273 2274 if (eth->netdev[id]) { 2275 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2276 return -EINVAL; 2277 } 2278 2279 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2280 if (!eth->netdev[id]) { 2281 dev_err(eth->dev, "alloc_etherdev failed\n"); 2282 return -ENOMEM; 2283 } 2284 mac = netdev_priv(eth->netdev[id]); 2285 eth->mac[id] = mac; 2286 mac->id = id; 2287 mac->hw = eth; 2288 mac->of_node = np; 2289 2290 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2291 mac->hwlro_ip_cnt = 0; 2292 2293 mac->hw_stats = devm_kzalloc(eth->dev, 2294 sizeof(*mac->hw_stats), 2295 GFP_KERNEL); 2296 if (!mac->hw_stats) { 2297 dev_err(eth->dev, "failed to allocate counter memory\n"); 2298 err = -ENOMEM; 2299 goto free_netdev; 2300 } 2301 spin_lock_init(&mac->hw_stats->stats_lock); 2302 u64_stats_init(&mac->hw_stats->syncp); 2303 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2304 2305 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2306 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2307 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2308 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2309 2310 eth->netdev[id]->hw_features = MTK_HW_FEATURES; 2311 if (eth->hwlro) 2312 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2313 2314 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 2315 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2316 eth->netdev[id]->features |= MTK_HW_FEATURES; 2317 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2318 2319 eth->netdev[id]->irq = eth->irq[0]; 2320 return 0; 2321 2322 free_netdev: 2323 free_netdev(eth->netdev[id]); 2324 return err; 2325 } 2326 2327 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id) 2328 { 2329 u32 val[2], id[4]; 2330 2331 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]); 2332 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]); 2333 2334 id[3] = ((val[0] >> 16) & 0xff) - '0'; 2335 id[2] = ((val[0] >> 24) & 0xff) - '0'; 2336 id[1] = (val[1] & 0xff) - '0'; 2337 id[0] = ((val[1] >> 8) & 0xff) - '0'; 2338 2339 *chip_id = (id[3] * 1000) + (id[2] * 100) + 2340 (id[1] * 10) + id[0]; 2341 2342 if (!(*chip_id)) { 2343 dev_err(eth->dev, "failed to get chip id\n"); 2344 return -ENODEV; 2345 } 2346 2347 dev_info(eth->dev, "chip id = %d\n", *chip_id); 2348 2349 return 0; 2350 } 2351 2352 static bool mtk_is_hwlro_supported(struct mtk_eth *eth) 2353 { 2354 switch (eth->chip_id) { 2355 case MT7623_ETH: 2356 return true; 2357 } 2358 2359 return false; 2360 } 2361 2362 static int mtk_probe(struct platform_device *pdev) 2363 { 2364 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2365 struct device_node *mac_np; 2366 const struct of_device_id *match; 2367 struct mtk_soc_data *soc; 2368 struct mtk_eth *eth; 2369 int err; 2370 int i; 2371 2372 match = of_match_device(of_mtk_match, &pdev->dev); 2373 soc = (struct mtk_soc_data *)match->data; 2374 2375 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2376 if (!eth) 2377 return -ENOMEM; 2378 2379 eth->dev = &pdev->dev; 2380 eth->base = devm_ioremap_resource(&pdev->dev, res); 2381 if (IS_ERR(eth->base)) 2382 return PTR_ERR(eth->base); 2383 2384 spin_lock_init(ð->page_lock); 2385 spin_lock_init(ð->irq_lock); 2386 2387 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2388 "mediatek,ethsys"); 2389 if (IS_ERR(eth->ethsys)) { 2390 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2391 return PTR_ERR(eth->ethsys); 2392 } 2393 2394 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2395 "mediatek,pctl"); 2396 if (IS_ERR(eth->pctl)) { 2397 dev_err(&pdev->dev, "no pctl regmap found\n"); 2398 return PTR_ERR(eth->pctl); 2399 } 2400 2401 for (i = 0; i < 3; i++) { 2402 eth->irq[i] = platform_get_irq(pdev, i); 2403 if (eth->irq[i] < 0) { 2404 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2405 return -ENXIO; 2406 } 2407 } 2408 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2409 eth->clks[i] = devm_clk_get(eth->dev, 2410 mtk_clks_source_name[i]); 2411 if (IS_ERR(eth->clks[i])) { 2412 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2413 return -EPROBE_DEFER; 2414 return -ENODEV; 2415 } 2416 } 2417 2418 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2419 INIT_WORK(ð->pending_work, mtk_pending_work); 2420 2421 err = mtk_hw_init(eth); 2422 if (err) 2423 return err; 2424 2425 err = mtk_get_chip_id(eth, ð->chip_id); 2426 if (err) 2427 return err; 2428 2429 eth->hwlro = mtk_is_hwlro_supported(eth); 2430 2431 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2432 if (!of_device_is_compatible(mac_np, 2433 "mediatek,eth-mac")) 2434 continue; 2435 2436 if (!of_device_is_available(mac_np)) 2437 continue; 2438 2439 err = mtk_add_mac(eth, mac_np); 2440 if (err) 2441 goto err_deinit_hw; 2442 } 2443 2444 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0, 2445 dev_name(eth->dev), eth); 2446 if (err) 2447 goto err_free_dev; 2448 2449 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0, 2450 dev_name(eth->dev), eth); 2451 if (err) 2452 goto err_free_dev; 2453 2454 err = mtk_mdio_init(eth); 2455 if (err) 2456 goto err_free_dev; 2457 2458 for (i = 0; i < MTK_MAX_DEVS; i++) { 2459 if (!eth->netdev[i]) 2460 continue; 2461 2462 err = register_netdev(eth->netdev[i]); 2463 if (err) { 2464 dev_err(eth->dev, "error bringing up device\n"); 2465 goto err_deinit_mdio; 2466 } else 2467 netif_info(eth, probe, eth->netdev[i], 2468 "mediatek frame engine at 0x%08lx, irq %d\n", 2469 eth->netdev[i]->base_addr, eth->irq[0]); 2470 } 2471 2472 /* we run 2 devices on the same DMA ring so we need a dummy device 2473 * for NAPI to work 2474 */ 2475 init_dummy_netdev(ð->dummy_dev); 2476 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 2477 MTK_NAPI_WEIGHT); 2478 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 2479 MTK_NAPI_WEIGHT); 2480 2481 platform_set_drvdata(pdev, eth); 2482 2483 return 0; 2484 2485 err_deinit_mdio: 2486 mtk_mdio_cleanup(eth); 2487 err_free_dev: 2488 mtk_free_dev(eth); 2489 err_deinit_hw: 2490 mtk_hw_deinit(eth); 2491 2492 return err; 2493 } 2494 2495 static int mtk_remove(struct platform_device *pdev) 2496 { 2497 struct mtk_eth *eth = platform_get_drvdata(pdev); 2498 int i; 2499 2500 /* stop all devices to make sure that dma is properly shut down */ 2501 for (i = 0; i < MTK_MAC_COUNT; i++) { 2502 if (!eth->netdev[i]) 2503 continue; 2504 mtk_stop(eth->netdev[i]); 2505 } 2506 2507 mtk_hw_deinit(eth); 2508 2509 netif_napi_del(ð->tx_napi); 2510 netif_napi_del(ð->rx_napi); 2511 mtk_cleanup(eth); 2512 mtk_mdio_cleanup(eth); 2513 2514 return 0; 2515 } 2516 2517 const struct of_device_id of_mtk_match[] = { 2518 { .compatible = "mediatek,mt2701-eth" }, 2519 {}, 2520 }; 2521 MODULE_DEVICE_TABLE(of, of_mtk_match); 2522 2523 static struct platform_driver mtk_driver = { 2524 .probe = mtk_probe, 2525 .remove = mtk_remove, 2526 .driver = { 2527 .name = "mtk_soc_eth", 2528 .of_match_table = of_mtk_match, 2529 }, 2530 }; 2531 2532 module_platform_driver(mtk_driver); 2533 2534 MODULE_LICENSE("GPL"); 2535 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 2536 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 2537