1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/regmap.h> 14 #include <linux/clk.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/if_vlan.h> 17 #include <linux/reset.h> 18 #include <linux/tcp.h> 19 #include <linux/interrupt.h> 20 #include <linux/pinctrl/devinfo.h> 21 #include <linux/phylink.h> 22 23 #include "mtk_eth_soc.h" 24 25 static int mtk_msg_level = -1; 26 module_param_named(msg_level, mtk_msg_level, int, 0); 27 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 28 29 #define MTK_ETHTOOL_STAT(x) { #x, \ 30 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 31 32 /* strings used by ethtool */ 33 static const struct mtk_ethtool_stats { 34 char str[ETH_GSTRING_LEN]; 35 u32 offset; 36 } mtk_ethtool_stats[] = { 37 MTK_ETHTOOL_STAT(tx_bytes), 38 MTK_ETHTOOL_STAT(tx_packets), 39 MTK_ETHTOOL_STAT(tx_skip), 40 MTK_ETHTOOL_STAT(tx_collisions), 41 MTK_ETHTOOL_STAT(rx_bytes), 42 MTK_ETHTOOL_STAT(rx_packets), 43 MTK_ETHTOOL_STAT(rx_overflow), 44 MTK_ETHTOOL_STAT(rx_fcs_errors), 45 MTK_ETHTOOL_STAT(rx_short_errors), 46 MTK_ETHTOOL_STAT(rx_long_errors), 47 MTK_ETHTOOL_STAT(rx_checksum_errors), 48 MTK_ETHTOOL_STAT(rx_flow_control_packets), 49 }; 50 51 static const char * const mtk_clks_source_name[] = { 52 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 53 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 54 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 55 "sgmii_ck", "eth2pll", 56 }; 57 58 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 59 { 60 __raw_writel(val, eth->base + reg); 61 } 62 63 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 64 { 65 return __raw_readl(eth->base + reg); 66 } 67 68 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 69 { 70 unsigned long t_start = jiffies; 71 72 while (1) { 73 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 74 return 0; 75 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 76 break; 77 usleep_range(10, 20); 78 } 79 80 dev_err(eth->dev, "mdio: MDIO timeout\n"); 81 return -1; 82 } 83 84 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 85 u32 phy_register, u32 write_data) 86 { 87 if (mtk_mdio_busy_wait(eth)) 88 return -1; 89 90 write_data &= 0xffff; 91 92 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 93 (phy_register << PHY_IAC_REG_SHIFT) | 94 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 95 MTK_PHY_IAC); 96 97 if (mtk_mdio_busy_wait(eth)) 98 return -1; 99 100 return 0; 101 } 102 103 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 104 { 105 u32 d; 106 107 if (mtk_mdio_busy_wait(eth)) 108 return 0xffff; 109 110 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 111 (phy_reg << PHY_IAC_REG_SHIFT) | 112 (phy_addr << PHY_IAC_ADDR_SHIFT), 113 MTK_PHY_IAC); 114 115 if (mtk_mdio_busy_wait(eth)) 116 return 0xffff; 117 118 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 119 120 return d; 121 } 122 123 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 124 int phy_reg, u16 val) 125 { 126 struct mtk_eth *eth = bus->priv; 127 128 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 129 } 130 131 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 132 { 133 struct mtk_eth *eth = bus->priv; 134 135 return _mtk_mdio_read(eth, phy_addr, phy_reg); 136 } 137 138 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 139 phy_interface_t interface) 140 { 141 u32 val; 142 143 /* Check DDR memory type. 144 * Currently TRGMII mode with DDR2 memory is not supported. 145 */ 146 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 147 if (interface == PHY_INTERFACE_MODE_TRGMII && 148 val & SYSCFG_DRAM_TYPE_DDR2) { 149 dev_err(eth->dev, 150 "TRGMII mode with DDR2 memory is not supported!\n"); 151 return -EOPNOTSUPP; 152 } 153 154 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 155 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 156 157 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 158 ETHSYS_TRGMII_MT7621_MASK, val); 159 160 return 0; 161 } 162 163 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed) 164 { 165 u32 val; 166 int ret; 167 168 val = (speed == SPEED_1000) ? 169 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100; 170 mtk_w32(eth, val, INTF_MODE); 171 172 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 173 ETHSYS_TRGMII_CLK_SEL362_5, 174 ETHSYS_TRGMII_CLK_SEL362_5); 175 176 val = (speed == SPEED_1000) ? 250000000 : 500000000; 177 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val); 178 if (ret) 179 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 180 181 val = (speed == SPEED_1000) ? 182 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100; 183 mtk_w32(eth, val, TRGMII_RCK_CTRL); 184 185 val = (speed == SPEED_1000) ? 186 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100; 187 mtk_w32(eth, val, TRGMII_TCK_CTRL); 188 } 189 190 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 191 const struct phylink_link_state *state) 192 { 193 struct mtk_mac *mac = container_of(config, struct mtk_mac, 194 phylink_config); 195 struct mtk_eth *eth = mac->hw; 196 u32 mcr_cur, mcr_new, sid; 197 int val, ge_mode, err; 198 199 /* MT76x8 has no hardware settings between for the MAC */ 200 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 201 mac->interface != state->interface) { 202 /* Setup soc pin functions */ 203 switch (state->interface) { 204 case PHY_INTERFACE_MODE_TRGMII: 205 if (mac->id) 206 goto err_phy; 207 if (!MTK_HAS_CAPS(mac->hw->soc->caps, 208 MTK_GMAC1_TRGMII)) 209 goto err_phy; 210 /* fall through */ 211 case PHY_INTERFACE_MODE_RGMII_TXID: 212 case PHY_INTERFACE_MODE_RGMII_RXID: 213 case PHY_INTERFACE_MODE_RGMII_ID: 214 case PHY_INTERFACE_MODE_RGMII: 215 case PHY_INTERFACE_MODE_MII: 216 case PHY_INTERFACE_MODE_REVMII: 217 case PHY_INTERFACE_MODE_RMII: 218 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 219 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 220 if (err) 221 goto init_err; 222 } 223 break; 224 case PHY_INTERFACE_MODE_1000BASEX: 225 case PHY_INTERFACE_MODE_2500BASEX: 226 case PHY_INTERFACE_MODE_SGMII: 227 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 228 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 229 if (err) 230 goto init_err; 231 } 232 break; 233 case PHY_INTERFACE_MODE_GMII: 234 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 235 err = mtk_gmac_gephy_path_setup(eth, mac->id); 236 if (err) 237 goto init_err; 238 } 239 break; 240 default: 241 goto err_phy; 242 } 243 244 /* Setup clock for 1st gmac */ 245 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 246 !phy_interface_mode_is_8023z(state->interface) && 247 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 248 if (MTK_HAS_CAPS(mac->hw->soc->caps, 249 MTK_TRGMII_MT7621_CLK)) { 250 if (mt7621_gmac0_rgmii_adjust(mac->hw, 251 state->interface)) 252 goto err_phy; 253 } else { 254 if (state->interface != 255 PHY_INTERFACE_MODE_TRGMII) 256 mtk_gmac0_rgmii_adjust(mac->hw, 257 state->speed); 258 } 259 } 260 261 ge_mode = 0; 262 switch (state->interface) { 263 case PHY_INTERFACE_MODE_MII: 264 ge_mode = 1; 265 break; 266 case PHY_INTERFACE_MODE_REVMII: 267 ge_mode = 2; 268 break; 269 case PHY_INTERFACE_MODE_RMII: 270 if (mac->id) 271 goto err_phy; 272 ge_mode = 3; 273 break; 274 default: 275 break; 276 } 277 278 /* put the gmac into the right mode */ 279 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 280 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 281 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 282 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 283 284 mac->interface = state->interface; 285 } 286 287 /* SGMII */ 288 if (state->interface == PHY_INTERFACE_MODE_SGMII || 289 phy_interface_mode_is_8023z(state->interface)) { 290 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 291 * being setup done. 292 */ 293 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 294 295 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 296 SYSCFG0_SGMII_MASK, 297 ~(u32)SYSCFG0_SGMII_MASK); 298 299 /* Decide how GMAC and SGMIISYS be mapped */ 300 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 301 0 : mac->id; 302 303 /* Setup SGMIISYS with the determined property */ 304 if (state->interface != PHY_INTERFACE_MODE_SGMII) 305 err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, 306 state); 307 else if (phylink_autoneg_inband(mode)) 308 err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); 309 310 if (err) 311 goto init_err; 312 313 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 314 SYSCFG0_SGMII_MASK, val); 315 } else if (phylink_autoneg_inband(mode)) { 316 dev_err(eth->dev, 317 "In-band mode not supported in non SGMII mode!\n"); 318 return; 319 } 320 321 /* Setup gmac */ 322 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 323 mcr_new = mcr_cur; 324 mcr_new &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 325 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 326 MAC_MCR_FORCE_RX_FC); 327 mcr_new |= MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 328 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; 329 330 switch (state->speed) { 331 case SPEED_2500: 332 case SPEED_1000: 333 mcr_new |= MAC_MCR_SPEED_1000; 334 break; 335 case SPEED_100: 336 mcr_new |= MAC_MCR_SPEED_100; 337 break; 338 } 339 if (state->duplex == DUPLEX_FULL) { 340 mcr_new |= MAC_MCR_FORCE_DPX; 341 if (state->pause & MLO_PAUSE_TX) 342 mcr_new |= MAC_MCR_FORCE_TX_FC; 343 if (state->pause & MLO_PAUSE_RX) 344 mcr_new |= MAC_MCR_FORCE_RX_FC; 345 } 346 347 /* Only update control register when needed! */ 348 if (mcr_new != mcr_cur) 349 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 350 351 return; 352 353 err_phy: 354 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 355 mac->id, phy_modes(state->interface)); 356 return; 357 358 init_err: 359 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 360 mac->id, phy_modes(state->interface), err); 361 } 362 363 static int mtk_mac_link_state(struct phylink_config *config, 364 struct phylink_link_state *state) 365 { 366 struct mtk_mac *mac = container_of(config, struct mtk_mac, 367 phylink_config); 368 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 369 370 state->link = (pmsr & MAC_MSR_LINK); 371 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 372 373 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 374 case 0: 375 state->speed = SPEED_10; 376 break; 377 case MAC_MSR_SPEED_100: 378 state->speed = SPEED_100; 379 break; 380 case MAC_MSR_SPEED_1000: 381 state->speed = SPEED_1000; 382 break; 383 default: 384 state->speed = SPEED_UNKNOWN; 385 break; 386 } 387 388 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 389 if (pmsr & MAC_MSR_RX_FC) 390 state->pause |= MLO_PAUSE_RX; 391 if (pmsr & MAC_MSR_TX_FC) 392 state->pause |= MLO_PAUSE_TX; 393 394 return 1; 395 } 396 397 static void mtk_mac_an_restart(struct phylink_config *config) 398 { 399 struct mtk_mac *mac = container_of(config, struct mtk_mac, 400 phylink_config); 401 402 mtk_sgmii_restart_an(mac->hw, mac->id); 403 } 404 405 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 406 phy_interface_t interface) 407 { 408 struct mtk_mac *mac = container_of(config, struct mtk_mac, 409 phylink_config); 410 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 411 412 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 413 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 414 } 415 416 static void mtk_mac_link_up(struct phylink_config *config, unsigned int mode, 417 phy_interface_t interface, 418 struct phy_device *phy) 419 { 420 struct mtk_mac *mac = container_of(config, struct mtk_mac, 421 phylink_config); 422 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 423 424 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 425 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 426 } 427 428 static void mtk_validate(struct phylink_config *config, 429 unsigned long *supported, 430 struct phylink_link_state *state) 431 { 432 struct mtk_mac *mac = container_of(config, struct mtk_mac, 433 phylink_config); 434 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 435 436 if (state->interface != PHY_INTERFACE_MODE_NA && 437 state->interface != PHY_INTERFACE_MODE_MII && 438 state->interface != PHY_INTERFACE_MODE_GMII && 439 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && 440 phy_interface_mode_is_rgmii(state->interface)) && 441 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && 442 !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && 443 !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && 444 (state->interface == PHY_INTERFACE_MODE_SGMII || 445 phy_interface_mode_is_8023z(state->interface)))) { 446 linkmode_zero(supported); 447 return; 448 } 449 450 phylink_set_port_modes(mask); 451 phylink_set(mask, Autoneg); 452 453 switch (state->interface) { 454 case PHY_INTERFACE_MODE_TRGMII: 455 phylink_set(mask, 1000baseT_Full); 456 break; 457 case PHY_INTERFACE_MODE_1000BASEX: 458 case PHY_INTERFACE_MODE_2500BASEX: 459 phylink_set(mask, 1000baseX_Full); 460 phylink_set(mask, 2500baseX_Full); 461 break; 462 case PHY_INTERFACE_MODE_GMII: 463 case PHY_INTERFACE_MODE_RGMII: 464 case PHY_INTERFACE_MODE_RGMII_ID: 465 case PHY_INTERFACE_MODE_RGMII_RXID: 466 case PHY_INTERFACE_MODE_RGMII_TXID: 467 phylink_set(mask, 1000baseT_Half); 468 /* fall through */ 469 case PHY_INTERFACE_MODE_SGMII: 470 phylink_set(mask, 1000baseT_Full); 471 phylink_set(mask, 1000baseX_Full); 472 /* fall through */ 473 case PHY_INTERFACE_MODE_MII: 474 case PHY_INTERFACE_MODE_RMII: 475 case PHY_INTERFACE_MODE_REVMII: 476 case PHY_INTERFACE_MODE_NA: 477 default: 478 phylink_set(mask, 10baseT_Half); 479 phylink_set(mask, 10baseT_Full); 480 phylink_set(mask, 100baseT_Half); 481 phylink_set(mask, 100baseT_Full); 482 break; 483 } 484 485 if (state->interface == PHY_INTERFACE_MODE_NA) { 486 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 487 phylink_set(mask, 1000baseT_Full); 488 phylink_set(mask, 1000baseX_Full); 489 phylink_set(mask, 2500baseX_Full); 490 } 491 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { 492 phylink_set(mask, 1000baseT_Full); 493 phylink_set(mask, 1000baseT_Half); 494 phylink_set(mask, 1000baseX_Full); 495 } 496 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { 497 phylink_set(mask, 1000baseT_Full); 498 phylink_set(mask, 1000baseT_Half); 499 } 500 } 501 502 phylink_set(mask, Pause); 503 phylink_set(mask, Asym_Pause); 504 505 linkmode_and(supported, supported, mask); 506 linkmode_and(state->advertising, state->advertising, mask); 507 508 /* We can only operate at 2500BaseX or 1000BaseX. If requested 509 * to advertise both, only report advertising at 2500BaseX. 510 */ 511 phylink_helper_basex_speed(state); 512 } 513 514 static const struct phylink_mac_ops mtk_phylink_ops = { 515 .validate = mtk_validate, 516 .mac_link_state = mtk_mac_link_state, 517 .mac_an_restart = mtk_mac_an_restart, 518 .mac_config = mtk_mac_config, 519 .mac_link_down = mtk_mac_link_down, 520 .mac_link_up = mtk_mac_link_up, 521 }; 522 523 static int mtk_mdio_init(struct mtk_eth *eth) 524 { 525 struct device_node *mii_np; 526 int ret; 527 528 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 529 if (!mii_np) { 530 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 531 return -ENODEV; 532 } 533 534 if (!of_device_is_available(mii_np)) { 535 ret = -ENODEV; 536 goto err_put_node; 537 } 538 539 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 540 if (!eth->mii_bus) { 541 ret = -ENOMEM; 542 goto err_put_node; 543 } 544 545 eth->mii_bus->name = "mdio"; 546 eth->mii_bus->read = mtk_mdio_read; 547 eth->mii_bus->write = mtk_mdio_write; 548 eth->mii_bus->priv = eth; 549 eth->mii_bus->parent = eth->dev; 550 551 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 552 ret = of_mdiobus_register(eth->mii_bus, mii_np); 553 554 err_put_node: 555 of_node_put(mii_np); 556 return ret; 557 } 558 559 static void mtk_mdio_cleanup(struct mtk_eth *eth) 560 { 561 if (!eth->mii_bus) 562 return; 563 564 mdiobus_unregister(eth->mii_bus); 565 } 566 567 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 568 { 569 unsigned long flags; 570 u32 val; 571 572 spin_lock_irqsave(ð->tx_irq_lock, flags); 573 val = mtk_r32(eth, eth->tx_int_mask_reg); 574 mtk_w32(eth, val & ~mask, eth->tx_int_mask_reg); 575 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 576 } 577 578 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 579 { 580 unsigned long flags; 581 u32 val; 582 583 spin_lock_irqsave(ð->tx_irq_lock, flags); 584 val = mtk_r32(eth, eth->tx_int_mask_reg); 585 mtk_w32(eth, val | mask, eth->tx_int_mask_reg); 586 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 587 } 588 589 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 590 { 591 unsigned long flags; 592 u32 val; 593 594 spin_lock_irqsave(ð->rx_irq_lock, flags); 595 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 596 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK); 597 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 598 } 599 600 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 601 { 602 unsigned long flags; 603 u32 val; 604 605 spin_lock_irqsave(ð->rx_irq_lock, flags); 606 val = mtk_r32(eth, MTK_PDMA_INT_MASK); 607 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK); 608 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 609 } 610 611 static int mtk_set_mac_address(struct net_device *dev, void *p) 612 { 613 int ret = eth_mac_addr(dev, p); 614 struct mtk_mac *mac = netdev_priv(dev); 615 struct mtk_eth *eth = mac->hw; 616 const char *macaddr = dev->dev_addr; 617 618 if (ret) 619 return ret; 620 621 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 622 return -EBUSY; 623 624 spin_lock_bh(&mac->hw->page_lock); 625 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 626 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 627 MT7628_SDM_MAC_ADRH); 628 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 629 (macaddr[4] << 8) | macaddr[5], 630 MT7628_SDM_MAC_ADRL); 631 } else { 632 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 633 MTK_GDMA_MAC_ADRH(mac->id)); 634 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 635 (macaddr[4] << 8) | macaddr[5], 636 MTK_GDMA_MAC_ADRL(mac->id)); 637 } 638 spin_unlock_bh(&mac->hw->page_lock); 639 640 return 0; 641 } 642 643 void mtk_stats_update_mac(struct mtk_mac *mac) 644 { 645 struct mtk_hw_stats *hw_stats = mac->hw_stats; 646 unsigned int base = MTK_GDM1_TX_GBCNT; 647 u64 stats; 648 649 base += hw_stats->reg_offset; 650 651 u64_stats_update_begin(&hw_stats->syncp); 652 653 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 654 stats = mtk_r32(mac->hw, base + 0x04); 655 if (stats) 656 hw_stats->rx_bytes += (stats << 32); 657 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 658 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 659 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 660 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 661 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 662 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 663 hw_stats->rx_flow_control_packets += 664 mtk_r32(mac->hw, base + 0x24); 665 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 666 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 667 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 668 stats = mtk_r32(mac->hw, base + 0x34); 669 if (stats) 670 hw_stats->tx_bytes += (stats << 32); 671 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 672 u64_stats_update_end(&hw_stats->syncp); 673 } 674 675 static void mtk_stats_update(struct mtk_eth *eth) 676 { 677 int i; 678 679 for (i = 0; i < MTK_MAC_COUNT; i++) { 680 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 681 continue; 682 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 683 mtk_stats_update_mac(eth->mac[i]); 684 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 685 } 686 } 687 } 688 689 static void mtk_get_stats64(struct net_device *dev, 690 struct rtnl_link_stats64 *storage) 691 { 692 struct mtk_mac *mac = netdev_priv(dev); 693 struct mtk_hw_stats *hw_stats = mac->hw_stats; 694 unsigned int start; 695 696 if (netif_running(dev) && netif_device_present(dev)) { 697 if (spin_trylock_bh(&hw_stats->stats_lock)) { 698 mtk_stats_update_mac(mac); 699 spin_unlock_bh(&hw_stats->stats_lock); 700 } 701 } 702 703 do { 704 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 705 storage->rx_packets = hw_stats->rx_packets; 706 storage->tx_packets = hw_stats->tx_packets; 707 storage->rx_bytes = hw_stats->rx_bytes; 708 storage->tx_bytes = hw_stats->tx_bytes; 709 storage->collisions = hw_stats->tx_collisions; 710 storage->rx_length_errors = hw_stats->rx_short_errors + 711 hw_stats->rx_long_errors; 712 storage->rx_over_errors = hw_stats->rx_overflow; 713 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 714 storage->rx_errors = hw_stats->rx_checksum_errors; 715 storage->tx_aborted_errors = hw_stats->tx_skip; 716 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 717 718 storage->tx_errors = dev->stats.tx_errors; 719 storage->rx_dropped = dev->stats.rx_dropped; 720 storage->tx_dropped = dev->stats.tx_dropped; 721 } 722 723 static inline int mtk_max_frag_size(int mtu) 724 { 725 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 726 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 727 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 728 729 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 730 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 731 } 732 733 static inline int mtk_max_buf_size(int frag_size) 734 { 735 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 736 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 737 738 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 739 740 return buf_size; 741 } 742 743 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 744 struct mtk_rx_dma *dma_rxd) 745 { 746 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 747 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 748 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 749 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 750 } 751 752 /* the qdma core needs scratch memory to be setup */ 753 static int mtk_init_fq_dma(struct mtk_eth *eth) 754 { 755 dma_addr_t phy_ring_tail; 756 int cnt = MTK_DMA_SIZE; 757 dma_addr_t dma_addr; 758 int i; 759 760 eth->scratch_ring = dma_alloc_coherent(eth->dev, 761 cnt * sizeof(struct mtk_tx_dma), 762 ð->phy_scratch_ring, 763 GFP_ATOMIC); 764 if (unlikely(!eth->scratch_ring)) 765 return -ENOMEM; 766 767 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 768 GFP_KERNEL); 769 if (unlikely(!eth->scratch_head)) 770 return -ENOMEM; 771 772 dma_addr = dma_map_single(eth->dev, 773 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 774 DMA_FROM_DEVICE); 775 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 776 return -ENOMEM; 777 778 phy_ring_tail = eth->phy_scratch_ring + 779 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 780 781 for (i = 0; i < cnt; i++) { 782 eth->scratch_ring[i].txd1 = 783 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 784 if (i < cnt - 1) 785 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 786 ((i + 1) * sizeof(struct mtk_tx_dma))); 787 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 788 } 789 790 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 791 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 792 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 793 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 794 795 return 0; 796 } 797 798 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 799 { 800 void *ret = ring->dma; 801 802 return ret + (desc - ring->phys); 803 } 804 805 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 806 struct mtk_tx_dma *txd) 807 { 808 int idx = txd - ring->dma; 809 810 return &ring->buf[idx]; 811 } 812 813 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 814 struct mtk_tx_dma *dma) 815 { 816 return ring->dma_pdma - ring->dma + dma; 817 } 818 819 static int txd_to_idx(struct mtk_tx_ring *ring, struct mtk_tx_dma *dma) 820 { 821 return ((void *)dma - (void *)ring->dma) / sizeof(*dma); 822 } 823 824 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf) 825 { 826 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 827 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 828 dma_unmap_single(eth->dev, 829 dma_unmap_addr(tx_buf, dma_addr0), 830 dma_unmap_len(tx_buf, dma_len0), 831 DMA_TO_DEVICE); 832 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 833 dma_unmap_page(eth->dev, 834 dma_unmap_addr(tx_buf, dma_addr0), 835 dma_unmap_len(tx_buf, dma_len0), 836 DMA_TO_DEVICE); 837 } 838 } else { 839 if (dma_unmap_len(tx_buf, dma_len0)) { 840 dma_unmap_page(eth->dev, 841 dma_unmap_addr(tx_buf, dma_addr0), 842 dma_unmap_len(tx_buf, dma_len0), 843 DMA_TO_DEVICE); 844 } 845 846 if (dma_unmap_len(tx_buf, dma_len1)) { 847 dma_unmap_page(eth->dev, 848 dma_unmap_addr(tx_buf, dma_addr1), 849 dma_unmap_len(tx_buf, dma_len1), 850 DMA_TO_DEVICE); 851 } 852 } 853 854 tx_buf->flags = 0; 855 if (tx_buf->skb && 856 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 857 dev_kfree_skb_any(tx_buf->skb); 858 tx_buf->skb = NULL; 859 } 860 861 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 862 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 863 size_t size, int idx) 864 { 865 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 866 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 867 dma_unmap_len_set(tx_buf, dma_len0, size); 868 } else { 869 if (idx & 1) { 870 txd->txd3 = mapped_addr; 871 txd->txd2 |= TX_DMA_PLEN1(size); 872 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 873 dma_unmap_len_set(tx_buf, dma_len1, size); 874 } else { 875 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 876 txd->txd1 = mapped_addr; 877 txd->txd2 = TX_DMA_PLEN0(size); 878 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 879 dma_unmap_len_set(tx_buf, dma_len0, size); 880 } 881 } 882 } 883 884 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 885 int tx_num, struct mtk_tx_ring *ring, bool gso) 886 { 887 struct mtk_mac *mac = netdev_priv(dev); 888 struct mtk_eth *eth = mac->hw; 889 struct mtk_tx_dma *itxd, *txd; 890 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 891 struct mtk_tx_buf *itx_buf, *tx_buf; 892 dma_addr_t mapped_addr; 893 unsigned int nr_frags; 894 int i, n_desc = 1; 895 u32 txd4 = 0, fport; 896 int k = 0; 897 898 itxd = ring->next_free; 899 itxd_pdma = qdma_to_pdma(ring, itxd); 900 if (itxd == ring->last_free) 901 return -ENOMEM; 902 903 /* set the forward port */ 904 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT; 905 txd4 |= fport; 906 907 itx_buf = mtk_desc_to_tx_buf(ring, itxd); 908 memset(itx_buf, 0, sizeof(*itx_buf)); 909 910 if (gso) 911 txd4 |= TX_DMA_TSO; 912 913 /* TX Checksum offload */ 914 if (skb->ip_summed == CHECKSUM_PARTIAL) 915 txd4 |= TX_DMA_CHKSUM; 916 917 /* VLAN header offload */ 918 if (skb_vlan_tag_present(skb)) 919 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 920 921 mapped_addr = dma_map_single(eth->dev, skb->data, 922 skb_headlen(skb), DMA_TO_DEVICE); 923 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 924 return -ENOMEM; 925 926 WRITE_ONCE(itxd->txd1, mapped_addr); 927 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 928 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 929 MTK_TX_FLAGS_FPORT1; 930 setup_tx_buf(eth, itx_buf, itxd_pdma, mapped_addr, skb_headlen(skb), 931 k++); 932 933 /* TX SG offload */ 934 txd = itxd; 935 txd_pdma = qdma_to_pdma(ring, txd); 936 nr_frags = skb_shinfo(skb)->nr_frags; 937 938 for (i = 0; i < nr_frags; i++) { 939 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 940 unsigned int offset = 0; 941 int frag_size = skb_frag_size(frag); 942 943 while (frag_size) { 944 bool last_frag = false; 945 unsigned int frag_map_size; 946 bool new_desc = true; 947 948 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA) || 949 (i & 0x1)) { 950 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 951 txd_pdma = qdma_to_pdma(ring, txd); 952 if (txd == ring->last_free) 953 goto err_dma; 954 955 n_desc++; 956 } else { 957 new_desc = false; 958 } 959 960 961 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 962 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset, 963 frag_map_size, 964 DMA_TO_DEVICE); 965 if (unlikely(dma_mapping_error(eth->dev, mapped_addr))) 966 goto err_dma; 967 968 if (i == nr_frags - 1 && 969 (frag_size - frag_map_size) == 0) 970 last_frag = true; 971 972 WRITE_ONCE(txd->txd1, mapped_addr); 973 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 974 TX_DMA_PLEN0(frag_map_size) | 975 last_frag * TX_DMA_LS0)); 976 WRITE_ONCE(txd->txd4, fport); 977 978 tx_buf = mtk_desc_to_tx_buf(ring, txd); 979 if (new_desc) 980 memset(tx_buf, 0, sizeof(*tx_buf)); 981 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 982 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 983 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 984 MTK_TX_FLAGS_FPORT1; 985 986 setup_tx_buf(eth, tx_buf, txd_pdma, mapped_addr, 987 frag_map_size, k++); 988 989 frag_size -= frag_map_size; 990 offset += frag_map_size; 991 } 992 } 993 994 /* store skb to cleanup */ 995 itx_buf->skb = skb; 996 997 WRITE_ONCE(itxd->txd4, txd4); 998 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 999 (!nr_frags * TX_DMA_LS0))); 1000 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1001 if (k & 0x1) 1002 txd_pdma->txd2 |= TX_DMA_LS0; 1003 else 1004 txd_pdma->txd2 |= TX_DMA_LS1; 1005 } 1006 1007 netdev_sent_queue(dev, skb->len); 1008 skb_tx_timestamp(skb); 1009 1010 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1011 atomic_sub(n_desc, &ring->free_count); 1012 1013 /* make sure that all changes to the dma ring are flushed before we 1014 * continue 1015 */ 1016 wmb(); 1017 1018 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1019 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || 1020 !netdev_xmit_more()) 1021 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 1022 } else { 1023 int next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd), 1024 ring->dma_size); 1025 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1026 } 1027 1028 return 0; 1029 1030 err_dma: 1031 do { 1032 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 1033 1034 /* unmap dma */ 1035 mtk_tx_unmap(eth, tx_buf); 1036 1037 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1038 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1039 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1040 1041 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1042 itxd_pdma = qdma_to_pdma(ring, itxd); 1043 } while (itxd != txd); 1044 1045 return -ENOMEM; 1046 } 1047 1048 static inline int mtk_cal_txd_req(struct sk_buff *skb) 1049 { 1050 int i, nfrags; 1051 skb_frag_t *frag; 1052 1053 nfrags = 1; 1054 if (skb_is_gso(skb)) { 1055 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1056 frag = &skb_shinfo(skb)->frags[i]; 1057 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1058 MTK_TX_DMA_BUF_LEN); 1059 } 1060 } else { 1061 nfrags += skb_shinfo(skb)->nr_frags; 1062 } 1063 1064 return nfrags; 1065 } 1066 1067 static int mtk_queue_stopped(struct mtk_eth *eth) 1068 { 1069 int i; 1070 1071 for (i = 0; i < MTK_MAC_COUNT; i++) { 1072 if (!eth->netdev[i]) 1073 continue; 1074 if (netif_queue_stopped(eth->netdev[i])) 1075 return 1; 1076 } 1077 1078 return 0; 1079 } 1080 1081 static void mtk_wake_queue(struct mtk_eth *eth) 1082 { 1083 int i; 1084 1085 for (i = 0; i < MTK_MAC_COUNT; i++) { 1086 if (!eth->netdev[i]) 1087 continue; 1088 netif_wake_queue(eth->netdev[i]); 1089 } 1090 } 1091 1092 static void mtk_stop_queue(struct mtk_eth *eth) 1093 { 1094 int i; 1095 1096 for (i = 0; i < MTK_MAC_COUNT; i++) { 1097 if (!eth->netdev[i]) 1098 continue; 1099 netif_stop_queue(eth->netdev[i]); 1100 } 1101 } 1102 1103 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1104 { 1105 struct mtk_mac *mac = netdev_priv(dev); 1106 struct mtk_eth *eth = mac->hw; 1107 struct mtk_tx_ring *ring = ð->tx_ring; 1108 struct net_device_stats *stats = &dev->stats; 1109 bool gso = false; 1110 int tx_num; 1111 1112 /* normally we can rely on the stack not calling this more than once, 1113 * however we have 2 queues running on the same ring so we need to lock 1114 * the ring access 1115 */ 1116 spin_lock(ð->page_lock); 1117 1118 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1119 goto drop; 1120 1121 tx_num = mtk_cal_txd_req(skb); 1122 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1123 mtk_stop_queue(eth); 1124 netif_err(eth, tx_queued, dev, 1125 "Tx Ring full when queue awake!\n"); 1126 spin_unlock(ð->page_lock); 1127 return NETDEV_TX_BUSY; 1128 } 1129 1130 /* TSO: fill MSS info in tcp checksum field */ 1131 if (skb_is_gso(skb)) { 1132 if (skb_cow_head(skb, 0)) { 1133 netif_warn(eth, tx_err, dev, 1134 "GSO expand head fail.\n"); 1135 goto drop; 1136 } 1137 1138 if (skb_shinfo(skb)->gso_type & 1139 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1140 gso = true; 1141 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1142 } 1143 } 1144 1145 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1146 goto drop; 1147 1148 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1149 mtk_stop_queue(eth); 1150 1151 spin_unlock(ð->page_lock); 1152 1153 return NETDEV_TX_OK; 1154 1155 drop: 1156 spin_unlock(ð->page_lock); 1157 stats->tx_dropped++; 1158 dev_kfree_skb_any(skb); 1159 return NETDEV_TX_OK; 1160 } 1161 1162 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1163 { 1164 int i; 1165 struct mtk_rx_ring *ring; 1166 int idx; 1167 1168 if (!eth->hwlro) 1169 return ð->rx_ring[0]; 1170 1171 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1172 ring = ð->rx_ring[i]; 1173 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1174 if (ring->dma[idx].rxd2 & RX_DMA_DONE) { 1175 ring->calc_idx_update = true; 1176 return ring; 1177 } 1178 } 1179 1180 return NULL; 1181 } 1182 1183 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1184 { 1185 struct mtk_rx_ring *ring; 1186 int i; 1187 1188 if (!eth->hwlro) { 1189 ring = ð->rx_ring[0]; 1190 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1191 } else { 1192 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1193 ring = ð->rx_ring[i]; 1194 if (ring->calc_idx_update) { 1195 ring->calc_idx_update = false; 1196 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1197 } 1198 } 1199 } 1200 } 1201 1202 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1203 struct mtk_eth *eth) 1204 { 1205 struct mtk_rx_ring *ring; 1206 int idx; 1207 struct sk_buff *skb; 1208 u8 *data, *new_data; 1209 struct mtk_rx_dma *rxd, trxd; 1210 int done = 0; 1211 1212 while (done < budget) { 1213 struct net_device *netdev; 1214 unsigned int pktlen; 1215 dma_addr_t dma_addr; 1216 int mac; 1217 1218 ring = mtk_get_rx_ring(eth); 1219 if (unlikely(!ring)) 1220 goto rx_done; 1221 1222 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1223 rxd = &ring->dma[idx]; 1224 data = ring->data[idx]; 1225 1226 mtk_rx_get_desc(&trxd, rxd); 1227 if (!(trxd.rxd2 & RX_DMA_DONE)) 1228 break; 1229 1230 /* find out which mac the packet come from. values start at 1 */ 1231 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 1232 mac = 0; 1233 } else { 1234 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 1235 RX_DMA_FPORT_MASK; 1236 mac--; 1237 } 1238 1239 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1240 !eth->netdev[mac])) 1241 goto release_desc; 1242 1243 netdev = eth->netdev[mac]; 1244 1245 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1246 goto release_desc; 1247 1248 /* alloc new buffer */ 1249 new_data = napi_alloc_frag(ring->frag_size); 1250 if (unlikely(!new_data)) { 1251 netdev->stats.rx_dropped++; 1252 goto release_desc; 1253 } 1254 dma_addr = dma_map_single(eth->dev, 1255 new_data + NET_SKB_PAD + 1256 eth->ip_align, 1257 ring->buf_size, 1258 DMA_FROM_DEVICE); 1259 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) { 1260 skb_free_frag(new_data); 1261 netdev->stats.rx_dropped++; 1262 goto release_desc; 1263 } 1264 1265 /* receive data */ 1266 skb = build_skb(data, ring->frag_size); 1267 if (unlikely(!skb)) { 1268 skb_free_frag(new_data); 1269 netdev->stats.rx_dropped++; 1270 goto release_desc; 1271 } 1272 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 1273 1274 dma_unmap_single(eth->dev, trxd.rxd1, 1275 ring->buf_size, DMA_FROM_DEVICE); 1276 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1277 skb->dev = netdev; 1278 skb_put(skb, pktlen); 1279 if (trxd.rxd4 & eth->rx_dma_l4_valid) 1280 skb->ip_summed = CHECKSUM_UNNECESSARY; 1281 else 1282 skb_checksum_none_assert(skb); 1283 skb->protocol = eth_type_trans(skb, netdev); 1284 1285 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 1286 RX_DMA_VID(trxd.rxd3)) 1287 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 1288 RX_DMA_VID(trxd.rxd3)); 1289 skb_record_rx_queue(skb, 0); 1290 napi_gro_receive(napi, skb); 1291 1292 ring->data[idx] = new_data; 1293 rxd->rxd1 = (unsigned int)dma_addr; 1294 1295 release_desc: 1296 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1297 rxd->rxd2 = RX_DMA_LSO; 1298 else 1299 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 1300 1301 ring->calc_idx = idx; 1302 1303 done++; 1304 } 1305 1306 rx_done: 1307 if (done) { 1308 /* make sure that all changes to the dma ring are flushed before 1309 * we continue 1310 */ 1311 wmb(); 1312 mtk_update_rx_cpu_idx(eth); 1313 } 1314 1315 return done; 1316 } 1317 1318 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 1319 unsigned int *done, unsigned int *bytes) 1320 { 1321 struct mtk_tx_ring *ring = ð->tx_ring; 1322 struct mtk_tx_dma *desc; 1323 struct sk_buff *skb; 1324 struct mtk_tx_buf *tx_buf; 1325 u32 cpu, dma; 1326 1327 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 1328 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 1329 1330 desc = mtk_qdma_phys_to_virt(ring, cpu); 1331 1332 while ((cpu != dma) && budget) { 1333 u32 next_cpu = desc->txd2; 1334 int mac = 0; 1335 1336 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 1337 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 1338 break; 1339 1340 tx_buf = mtk_desc_to_tx_buf(ring, desc); 1341 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 1342 mac = 1; 1343 1344 skb = tx_buf->skb; 1345 if (!skb) 1346 break; 1347 1348 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1349 bytes[mac] += skb->len; 1350 done[mac]++; 1351 budget--; 1352 } 1353 mtk_tx_unmap(eth, tx_buf); 1354 1355 ring->last_free = desc; 1356 atomic_inc(&ring->free_count); 1357 1358 cpu = next_cpu; 1359 } 1360 1361 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 1362 1363 return budget; 1364 } 1365 1366 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 1367 unsigned int *done, unsigned int *bytes) 1368 { 1369 struct mtk_tx_ring *ring = ð->tx_ring; 1370 struct mtk_tx_dma *desc; 1371 struct sk_buff *skb; 1372 struct mtk_tx_buf *tx_buf; 1373 u32 cpu, dma; 1374 1375 cpu = ring->cpu_idx; 1376 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 1377 1378 while ((cpu != dma) && budget) { 1379 tx_buf = &ring->buf[cpu]; 1380 skb = tx_buf->skb; 1381 if (!skb) 1382 break; 1383 1384 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 1385 bytes[0] += skb->len; 1386 done[0]++; 1387 budget--; 1388 } 1389 1390 mtk_tx_unmap(eth, tx_buf); 1391 1392 desc = &ring->dma[cpu]; 1393 ring->last_free = desc; 1394 atomic_inc(&ring->free_count); 1395 1396 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 1397 } 1398 1399 ring->cpu_idx = cpu; 1400 1401 return budget; 1402 } 1403 1404 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 1405 { 1406 struct mtk_tx_ring *ring = ð->tx_ring; 1407 unsigned int done[MTK_MAX_DEVS]; 1408 unsigned int bytes[MTK_MAX_DEVS]; 1409 int total = 0, i; 1410 1411 memset(done, 0, sizeof(done)); 1412 memset(bytes, 0, sizeof(bytes)); 1413 1414 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1415 budget = mtk_poll_tx_qdma(eth, budget, done, bytes); 1416 else 1417 budget = mtk_poll_tx_pdma(eth, budget, done, bytes); 1418 1419 for (i = 0; i < MTK_MAC_COUNT; i++) { 1420 if (!eth->netdev[i] || !done[i]) 1421 continue; 1422 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 1423 total += done[i]; 1424 } 1425 1426 if (mtk_queue_stopped(eth) && 1427 (atomic_read(&ring->free_count) > ring->thresh)) 1428 mtk_wake_queue(eth); 1429 1430 return total; 1431 } 1432 1433 static void mtk_handle_status_irq(struct mtk_eth *eth) 1434 { 1435 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 1436 1437 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 1438 mtk_stats_update(eth); 1439 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 1440 MTK_INT_STATUS2); 1441 } 1442 } 1443 1444 static int mtk_napi_tx(struct napi_struct *napi, int budget) 1445 { 1446 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 1447 u32 status, mask; 1448 int tx_done = 0; 1449 1450 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 1451 mtk_handle_status_irq(eth); 1452 mtk_w32(eth, MTK_TX_DONE_INT, eth->tx_int_status_reg); 1453 tx_done = mtk_poll_tx(eth, budget); 1454 1455 if (unlikely(netif_msg_intr(eth))) { 1456 status = mtk_r32(eth, eth->tx_int_status_reg); 1457 mask = mtk_r32(eth, eth->tx_int_mask_reg); 1458 dev_info(eth->dev, 1459 "done tx %d, intr 0x%08x/0x%x\n", 1460 tx_done, status, mask); 1461 } 1462 1463 if (tx_done == budget) 1464 return budget; 1465 1466 status = mtk_r32(eth, eth->tx_int_status_reg); 1467 if (status & MTK_TX_DONE_INT) 1468 return budget; 1469 1470 napi_complete(napi); 1471 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 1472 1473 return tx_done; 1474 } 1475 1476 static int mtk_napi_rx(struct napi_struct *napi, int budget) 1477 { 1478 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 1479 u32 status, mask; 1480 int rx_done = 0; 1481 int remain_budget = budget; 1482 1483 mtk_handle_status_irq(eth); 1484 1485 poll_again: 1486 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS); 1487 rx_done = mtk_poll_rx(napi, remain_budget, eth); 1488 1489 if (unlikely(netif_msg_intr(eth))) { 1490 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1491 mask = mtk_r32(eth, MTK_PDMA_INT_MASK); 1492 dev_info(eth->dev, 1493 "done rx %d, intr 0x%08x/0x%x\n", 1494 rx_done, status, mask); 1495 } 1496 if (rx_done == remain_budget) 1497 return budget; 1498 1499 status = mtk_r32(eth, MTK_PDMA_INT_STATUS); 1500 if (status & MTK_RX_DONE_INT) { 1501 remain_budget -= rx_done; 1502 goto poll_again; 1503 } 1504 napi_complete(napi); 1505 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 1506 1507 return rx_done + budget - remain_budget; 1508 } 1509 1510 static int mtk_tx_alloc(struct mtk_eth *eth) 1511 { 1512 struct mtk_tx_ring *ring = ð->tx_ring; 1513 int i, sz = sizeof(*ring->dma); 1514 1515 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1516 GFP_KERNEL); 1517 if (!ring->buf) 1518 goto no_tx_mem; 1519 1520 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1521 &ring->phys, GFP_ATOMIC); 1522 if (!ring->dma) 1523 goto no_tx_mem; 1524 1525 for (i = 0; i < MTK_DMA_SIZE; i++) { 1526 int next = (i + 1) % MTK_DMA_SIZE; 1527 u32 next_ptr = ring->phys + next * sz; 1528 1529 ring->dma[i].txd2 = next_ptr; 1530 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1531 } 1532 1533 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 1534 * only as the framework. The real HW descriptors are the PDMA 1535 * descriptors in ring->dma_pdma. 1536 */ 1537 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1538 ring->dma_pdma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz, 1539 &ring->phys_pdma, 1540 GFP_ATOMIC); 1541 if (!ring->dma_pdma) 1542 goto no_tx_mem; 1543 1544 for (i = 0; i < MTK_DMA_SIZE; i++) { 1545 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 1546 ring->dma_pdma[i].txd4 = 0; 1547 } 1548 } 1549 1550 ring->dma_size = MTK_DMA_SIZE; 1551 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1552 ring->next_free = &ring->dma[0]; 1553 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1554 ring->thresh = MAX_SKB_FRAGS; 1555 1556 /* make sure that all changes to the dma ring are flushed before we 1557 * continue 1558 */ 1559 wmb(); 1560 1561 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1562 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1563 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1564 mtk_w32(eth, 1565 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1566 MTK_QTX_CRX_PTR); 1567 mtk_w32(eth, 1568 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1569 MTK_QTX_DRX_PTR); 1570 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, 1571 MTK_QTX_CFG(0)); 1572 } else { 1573 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 1574 mtk_w32(eth, MTK_DMA_SIZE, MT7628_TX_MAX_CNT0); 1575 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 1576 mtk_w32(eth, MT7628_PST_DTX_IDX0, MTK_PDMA_RST_IDX); 1577 } 1578 1579 return 0; 1580 1581 no_tx_mem: 1582 return -ENOMEM; 1583 } 1584 1585 static void mtk_tx_clean(struct mtk_eth *eth) 1586 { 1587 struct mtk_tx_ring *ring = ð->tx_ring; 1588 int i; 1589 1590 if (ring->buf) { 1591 for (i = 0; i < MTK_DMA_SIZE; i++) 1592 mtk_tx_unmap(eth, &ring->buf[i]); 1593 kfree(ring->buf); 1594 ring->buf = NULL; 1595 } 1596 1597 if (ring->dma) { 1598 dma_free_coherent(eth->dev, 1599 MTK_DMA_SIZE * sizeof(*ring->dma), 1600 ring->dma, 1601 ring->phys); 1602 ring->dma = NULL; 1603 } 1604 1605 if (ring->dma_pdma) { 1606 dma_free_coherent(eth->dev, 1607 MTK_DMA_SIZE * sizeof(*ring->dma_pdma), 1608 ring->dma_pdma, 1609 ring->phys_pdma); 1610 ring->dma_pdma = NULL; 1611 } 1612 } 1613 1614 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 1615 { 1616 struct mtk_rx_ring *ring; 1617 int rx_data_len, rx_dma_size; 1618 int i; 1619 u32 offset = 0; 1620 1621 if (rx_flag == MTK_RX_FLAGS_QDMA) { 1622 if (ring_no) 1623 return -EINVAL; 1624 ring = ð->rx_ring_qdma; 1625 offset = 0x1000; 1626 } else { 1627 ring = ð->rx_ring[ring_no]; 1628 } 1629 1630 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 1631 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 1632 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 1633 } else { 1634 rx_data_len = ETH_DATA_LEN; 1635 rx_dma_size = MTK_DMA_SIZE; 1636 } 1637 1638 ring->frag_size = mtk_max_frag_size(rx_data_len); 1639 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1640 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 1641 GFP_KERNEL); 1642 if (!ring->data) 1643 return -ENOMEM; 1644 1645 for (i = 0; i < rx_dma_size; i++) { 1646 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1647 if (!ring->data[i]) 1648 return -ENOMEM; 1649 } 1650 1651 ring->dma = dma_alloc_coherent(eth->dev, 1652 rx_dma_size * sizeof(*ring->dma), 1653 &ring->phys, GFP_ATOMIC); 1654 if (!ring->dma) 1655 return -ENOMEM; 1656 1657 for (i = 0; i < rx_dma_size; i++) { 1658 dma_addr_t dma_addr = dma_map_single(eth->dev, 1659 ring->data[i] + NET_SKB_PAD + eth->ip_align, 1660 ring->buf_size, 1661 DMA_FROM_DEVICE); 1662 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1663 return -ENOMEM; 1664 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1665 1666 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 1667 ring->dma[i].rxd2 = RX_DMA_LSO; 1668 else 1669 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1670 } 1671 ring->dma_size = rx_dma_size; 1672 ring->calc_idx_update = false; 1673 ring->calc_idx = rx_dma_size - 1; 1674 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no); 1675 /* make sure that all changes to the dma ring are flushed before we 1676 * continue 1677 */ 1678 wmb(); 1679 1680 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset); 1681 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset); 1682 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset); 1683 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset); 1684 1685 return 0; 1686 } 1687 1688 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 1689 { 1690 int i; 1691 1692 if (ring->data && ring->dma) { 1693 for (i = 0; i < ring->dma_size; i++) { 1694 if (!ring->data[i]) 1695 continue; 1696 if (!ring->dma[i].rxd1) 1697 continue; 1698 dma_unmap_single(eth->dev, 1699 ring->dma[i].rxd1, 1700 ring->buf_size, 1701 DMA_FROM_DEVICE); 1702 skb_free_frag(ring->data[i]); 1703 } 1704 kfree(ring->data); 1705 ring->data = NULL; 1706 } 1707 1708 if (ring->dma) { 1709 dma_free_coherent(eth->dev, 1710 ring->dma_size * sizeof(*ring->dma), 1711 ring->dma, 1712 ring->phys); 1713 ring->dma = NULL; 1714 } 1715 } 1716 1717 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 1718 { 1719 int i; 1720 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 1721 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 1722 1723 /* set LRO rings to auto-learn modes */ 1724 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 1725 1726 /* validate LRO ring */ 1727 ring_ctrl_dw2 |= MTK_RING_VLD; 1728 1729 /* set AGE timer (unit: 20us) */ 1730 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 1731 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 1732 1733 /* set max AGG timer (unit: 20us) */ 1734 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 1735 1736 /* set max LRO AGG count */ 1737 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 1738 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 1739 1740 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 1741 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 1742 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 1743 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 1744 } 1745 1746 /* IPv4 checksum update enable */ 1747 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 1748 1749 /* switch priority comparison to packet count mode */ 1750 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 1751 1752 /* bandwidth threshold setting */ 1753 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 1754 1755 /* auto-learn score delta setting */ 1756 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 1757 1758 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 1759 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 1760 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 1761 1762 /* set HW LRO mode & the max aggregation count for rx packets */ 1763 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 1764 1765 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 1766 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 1767 1768 /* enable HW LRO */ 1769 lro_ctrl_dw0 |= MTK_LRO_EN; 1770 1771 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 1772 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 1773 1774 return 0; 1775 } 1776 1777 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 1778 { 1779 int i; 1780 u32 val; 1781 1782 /* relinquish lro rings, flush aggregated packets */ 1783 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 1784 1785 /* wait for relinquishments done */ 1786 for (i = 0; i < 10; i++) { 1787 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 1788 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 1789 msleep(20); 1790 continue; 1791 } 1792 break; 1793 } 1794 1795 /* invalidate lro rings */ 1796 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 1797 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 1798 1799 /* disable HW LRO */ 1800 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 1801 } 1802 1803 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 1804 { 1805 u32 reg_val; 1806 1807 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1808 1809 /* invalidate the IP setting */ 1810 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1811 1812 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 1813 1814 /* validate the IP setting */ 1815 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1816 } 1817 1818 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 1819 { 1820 u32 reg_val; 1821 1822 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 1823 1824 /* invalidate the IP setting */ 1825 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 1826 1827 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 1828 } 1829 1830 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 1831 { 1832 int cnt = 0; 1833 int i; 1834 1835 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1836 if (mac->hwlro_ip[i]) 1837 cnt++; 1838 } 1839 1840 return cnt; 1841 } 1842 1843 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 1844 struct ethtool_rxnfc *cmd) 1845 { 1846 struct ethtool_rx_flow_spec *fsp = 1847 (struct ethtool_rx_flow_spec *)&cmd->fs; 1848 struct mtk_mac *mac = netdev_priv(dev); 1849 struct mtk_eth *eth = mac->hw; 1850 int hwlro_idx; 1851 1852 if ((fsp->flow_type != TCP_V4_FLOW) || 1853 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 1854 (fsp->location > 1)) 1855 return -EINVAL; 1856 1857 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 1858 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1859 1860 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1861 1862 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 1863 1864 return 0; 1865 } 1866 1867 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 1868 struct ethtool_rxnfc *cmd) 1869 { 1870 struct ethtool_rx_flow_spec *fsp = 1871 (struct ethtool_rx_flow_spec *)&cmd->fs; 1872 struct mtk_mac *mac = netdev_priv(dev); 1873 struct mtk_eth *eth = mac->hw; 1874 int hwlro_idx; 1875 1876 if (fsp->location > 1) 1877 return -EINVAL; 1878 1879 mac->hwlro_ip[fsp->location] = 0; 1880 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 1881 1882 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1883 1884 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1885 1886 return 0; 1887 } 1888 1889 static void mtk_hwlro_netdev_disable(struct net_device *dev) 1890 { 1891 struct mtk_mac *mac = netdev_priv(dev); 1892 struct mtk_eth *eth = mac->hw; 1893 int i, hwlro_idx; 1894 1895 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1896 mac->hwlro_ip[i] = 0; 1897 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 1898 1899 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 1900 } 1901 1902 mac->hwlro_ip_cnt = 0; 1903 } 1904 1905 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 1906 struct ethtool_rxnfc *cmd) 1907 { 1908 struct mtk_mac *mac = netdev_priv(dev); 1909 struct ethtool_rx_flow_spec *fsp = 1910 (struct ethtool_rx_flow_spec *)&cmd->fs; 1911 1912 /* only tcp dst ipv4 is meaningful, others are meaningless */ 1913 fsp->flow_type = TCP_V4_FLOW; 1914 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 1915 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 1916 1917 fsp->h_u.tcp_ip4_spec.ip4src = 0; 1918 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 1919 fsp->h_u.tcp_ip4_spec.psrc = 0; 1920 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 1921 fsp->h_u.tcp_ip4_spec.pdst = 0; 1922 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 1923 fsp->h_u.tcp_ip4_spec.tos = 0; 1924 fsp->m_u.tcp_ip4_spec.tos = 0xff; 1925 1926 return 0; 1927 } 1928 1929 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 1930 struct ethtool_rxnfc *cmd, 1931 u32 *rule_locs) 1932 { 1933 struct mtk_mac *mac = netdev_priv(dev); 1934 int cnt = 0; 1935 int i; 1936 1937 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 1938 if (mac->hwlro_ip[i]) { 1939 rule_locs[cnt] = i; 1940 cnt++; 1941 } 1942 } 1943 1944 cmd->rule_cnt = cnt; 1945 1946 return 0; 1947 } 1948 1949 static netdev_features_t mtk_fix_features(struct net_device *dev, 1950 netdev_features_t features) 1951 { 1952 if (!(features & NETIF_F_LRO)) { 1953 struct mtk_mac *mac = netdev_priv(dev); 1954 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 1955 1956 if (ip_cnt) { 1957 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 1958 1959 features |= NETIF_F_LRO; 1960 } 1961 } 1962 1963 return features; 1964 } 1965 1966 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 1967 { 1968 int err = 0; 1969 1970 if (!((dev->features ^ features) & NETIF_F_LRO)) 1971 return 0; 1972 1973 if (!(features & NETIF_F_LRO)) 1974 mtk_hwlro_netdev_disable(dev); 1975 1976 return err; 1977 } 1978 1979 /* wait for DMA to finish whatever it is doing before we start using it again */ 1980 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1981 { 1982 unsigned long t_start = jiffies; 1983 1984 while (1) { 1985 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1986 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1987 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1988 return 0; 1989 } else { 1990 if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) & 1991 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1992 return 0; 1993 } 1994 1995 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1996 break; 1997 } 1998 1999 dev_err(eth->dev, "DMA init timeout\n"); 2000 return -1; 2001 } 2002 2003 static int mtk_dma_init(struct mtk_eth *eth) 2004 { 2005 int err; 2006 u32 i; 2007 2008 if (mtk_dma_busy_wait(eth)) 2009 return -EBUSY; 2010 2011 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2012 /* QDMA needs scratch memory for internal reordering of the 2013 * descriptors 2014 */ 2015 err = mtk_init_fq_dma(eth); 2016 if (err) 2017 return err; 2018 } 2019 2020 err = mtk_tx_alloc(eth); 2021 if (err) 2022 return err; 2023 2024 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2025 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2026 if (err) 2027 return err; 2028 } 2029 2030 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2031 if (err) 2032 return err; 2033 2034 if (eth->hwlro) { 2035 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2036 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2037 if (err) 2038 return err; 2039 } 2040 err = mtk_hwlro_rx_init(eth); 2041 if (err) 2042 return err; 2043 } 2044 2045 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2046 /* Enable random early drop and set drop threshold 2047 * automatically 2048 */ 2049 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2050 FC_THRES_MIN, MTK_QDMA_FC_THRES); 2051 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 2052 } 2053 2054 return 0; 2055 } 2056 2057 static void mtk_dma_free(struct mtk_eth *eth) 2058 { 2059 int i; 2060 2061 for (i = 0; i < MTK_MAC_COUNT; i++) 2062 if (eth->netdev[i]) 2063 netdev_reset_queue(eth->netdev[i]); 2064 if (eth->scratch_ring) { 2065 dma_free_coherent(eth->dev, 2066 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 2067 eth->scratch_ring, 2068 eth->phy_scratch_ring); 2069 eth->scratch_ring = NULL; 2070 eth->phy_scratch_ring = 0; 2071 } 2072 mtk_tx_clean(eth); 2073 mtk_rx_clean(eth, ð->rx_ring[0]); 2074 mtk_rx_clean(eth, ð->rx_ring_qdma); 2075 2076 if (eth->hwlro) { 2077 mtk_hwlro_rx_uninit(eth); 2078 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2079 mtk_rx_clean(eth, ð->rx_ring[i]); 2080 } 2081 2082 kfree(eth->scratch_head); 2083 } 2084 2085 static void mtk_tx_timeout(struct net_device *dev) 2086 { 2087 struct mtk_mac *mac = netdev_priv(dev); 2088 struct mtk_eth *eth = mac->hw; 2089 2090 eth->netdev[mac->id]->stats.tx_errors++; 2091 netif_err(eth, tx_err, dev, 2092 "transmit timed out\n"); 2093 schedule_work(ð->pending_work); 2094 } 2095 2096 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 2097 { 2098 struct mtk_eth *eth = _eth; 2099 2100 if (likely(napi_schedule_prep(ð->rx_napi))) { 2101 __napi_schedule(ð->rx_napi); 2102 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2103 } 2104 2105 return IRQ_HANDLED; 2106 } 2107 2108 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 2109 { 2110 struct mtk_eth *eth = _eth; 2111 2112 if (likely(napi_schedule_prep(ð->tx_napi))) { 2113 __napi_schedule(ð->tx_napi); 2114 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2115 } 2116 2117 return IRQ_HANDLED; 2118 } 2119 2120 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 2121 { 2122 struct mtk_eth *eth = _eth; 2123 2124 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) { 2125 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT) 2126 mtk_handle_irq_rx(irq, _eth); 2127 } 2128 if (mtk_r32(eth, eth->tx_int_mask_reg) & MTK_TX_DONE_INT) { 2129 if (mtk_r32(eth, eth->tx_int_status_reg) & MTK_TX_DONE_INT) 2130 mtk_handle_irq_tx(irq, _eth); 2131 } 2132 2133 return IRQ_HANDLED; 2134 } 2135 2136 #ifdef CONFIG_NET_POLL_CONTROLLER 2137 static void mtk_poll_controller(struct net_device *dev) 2138 { 2139 struct mtk_mac *mac = netdev_priv(dev); 2140 struct mtk_eth *eth = mac->hw; 2141 2142 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2143 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2144 mtk_handle_irq_rx(eth->irq[2], dev); 2145 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2146 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2147 } 2148 #endif 2149 2150 static int mtk_start_dma(struct mtk_eth *eth) 2151 { 2152 u32 rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 2153 int err; 2154 2155 err = mtk_dma_init(eth); 2156 if (err) { 2157 mtk_dma_free(eth); 2158 return err; 2159 } 2160 2161 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2162 mtk_w32(eth, 2163 MTK_TX_WB_DDONE | MTK_TX_DMA_EN | 2164 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO | 2165 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET | 2166 MTK_RX_BT_32DWORDS, 2167 MTK_QDMA_GLO_CFG); 2168 2169 mtk_w32(eth, 2170 MTK_RX_DMA_EN | rx_2b_offset | 2171 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 2172 MTK_PDMA_GLO_CFG); 2173 } else { 2174 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 2175 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 2176 MTK_PDMA_GLO_CFG); 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int mtk_open(struct net_device *dev) 2183 { 2184 struct mtk_mac *mac = netdev_priv(dev); 2185 struct mtk_eth *eth = mac->hw; 2186 int err; 2187 2188 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 2189 if (err) { 2190 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 2191 err); 2192 return err; 2193 } 2194 2195 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 2196 if (!refcount_read(ð->dma_refcnt)) { 2197 int err = mtk_start_dma(eth); 2198 2199 if (err) 2200 return err; 2201 2202 napi_enable(ð->tx_napi); 2203 napi_enable(ð->rx_napi); 2204 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2205 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT); 2206 refcount_set(ð->dma_refcnt, 1); 2207 } 2208 else 2209 refcount_inc(ð->dma_refcnt); 2210 2211 phylink_start(mac->phylink); 2212 netif_start_queue(dev); 2213 return 0; 2214 } 2215 2216 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 2217 { 2218 u32 val; 2219 int i; 2220 2221 /* stop the dma engine */ 2222 spin_lock_bh(ð->page_lock); 2223 val = mtk_r32(eth, glo_cfg); 2224 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 2225 glo_cfg); 2226 spin_unlock_bh(ð->page_lock); 2227 2228 /* wait for dma stop */ 2229 for (i = 0; i < 10; i++) { 2230 val = mtk_r32(eth, glo_cfg); 2231 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 2232 msleep(20); 2233 continue; 2234 } 2235 break; 2236 } 2237 } 2238 2239 static int mtk_stop(struct net_device *dev) 2240 { 2241 struct mtk_mac *mac = netdev_priv(dev); 2242 struct mtk_eth *eth = mac->hw; 2243 2244 phylink_stop(mac->phylink); 2245 2246 netif_tx_disable(dev); 2247 2248 phylink_disconnect_phy(mac->phylink); 2249 2250 /* only shutdown DMA if this is the last user */ 2251 if (!refcount_dec_and_test(ð->dma_refcnt)) 2252 return 0; 2253 2254 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 2255 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT); 2256 napi_disable(ð->tx_napi); 2257 napi_disable(ð->rx_napi); 2258 2259 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2260 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 2261 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG); 2262 2263 mtk_dma_free(eth); 2264 2265 return 0; 2266 } 2267 2268 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 2269 { 2270 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2271 reset_bits, 2272 reset_bits); 2273 2274 usleep_range(1000, 1100); 2275 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 2276 reset_bits, 2277 ~reset_bits); 2278 mdelay(10); 2279 } 2280 2281 static void mtk_clk_disable(struct mtk_eth *eth) 2282 { 2283 int clk; 2284 2285 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 2286 clk_disable_unprepare(eth->clks[clk]); 2287 } 2288 2289 static int mtk_clk_enable(struct mtk_eth *eth) 2290 { 2291 int clk, ret; 2292 2293 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 2294 ret = clk_prepare_enable(eth->clks[clk]); 2295 if (ret) 2296 goto err_disable_clks; 2297 } 2298 2299 return 0; 2300 2301 err_disable_clks: 2302 while (--clk >= 0) 2303 clk_disable_unprepare(eth->clks[clk]); 2304 2305 return ret; 2306 } 2307 2308 static int mtk_hw_init(struct mtk_eth *eth) 2309 { 2310 int i, val, ret; 2311 2312 if (test_and_set_bit(MTK_HW_INIT, ð->state)) 2313 return 0; 2314 2315 pm_runtime_enable(eth->dev); 2316 pm_runtime_get_sync(eth->dev); 2317 2318 ret = mtk_clk_enable(eth); 2319 if (ret) 2320 goto err_disable_pm; 2321 2322 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2323 ret = device_reset(eth->dev); 2324 if (ret) { 2325 dev_err(eth->dev, "MAC reset failed!\n"); 2326 goto err_disable_pm; 2327 } 2328 2329 /* enable interrupt delay for RX */ 2330 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2331 2332 /* disable delay and normal interrupt */ 2333 mtk_tx_irq_disable(eth, ~0); 2334 mtk_rx_irq_disable(eth, ~0); 2335 2336 return 0; 2337 } 2338 2339 /* Non-MT7628 handling... */ 2340 ethsys_reset(eth, RSTCTRL_FE); 2341 ethsys_reset(eth, RSTCTRL_PPE); 2342 2343 if (eth->pctl) { 2344 /* Set GE2 driving and slew rate */ 2345 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 2346 2347 /* set GE2 TDSEL */ 2348 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 2349 2350 /* set GE2 TUNE */ 2351 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 2352 } 2353 2354 /* Set linkdown as the default for each GMAC. Its own MCR would be set 2355 * up with the more appropriate value when mtk_mac_config call is being 2356 * invoked. 2357 */ 2358 for (i = 0; i < MTK_MAC_COUNT; i++) 2359 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 2360 2361 /* Indicates CDM to parse the MTK special tag from CPU 2362 * which also is working out for untag packets. 2363 */ 2364 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 2365 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 2366 2367 /* Enable RX VLan Offloading */ 2368 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 2369 2370 /* enable interrupt delay for RX */ 2371 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT); 2372 2373 /* disable delay and normal interrupt */ 2374 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 2375 mtk_tx_irq_disable(eth, ~0); 2376 mtk_rx_irq_disable(eth, ~0); 2377 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 2378 mtk_w32(eth, 0, MTK_RST_GL); 2379 2380 /* FE int grouping */ 2381 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1); 2382 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2); 2383 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1); 2384 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2); 2385 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 2386 2387 for (i = 0; i < MTK_MAC_COUNT; i++) { 2388 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 2389 2390 /* setup the forward port to send frame to PDMA */ 2391 val &= ~0xffff; 2392 2393 /* Enable RX checksum */ 2394 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 2395 2396 /* setup the mac dma */ 2397 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 2398 } 2399 2400 return 0; 2401 2402 err_disable_pm: 2403 pm_runtime_put_sync(eth->dev); 2404 pm_runtime_disable(eth->dev); 2405 2406 return ret; 2407 } 2408 2409 static int mtk_hw_deinit(struct mtk_eth *eth) 2410 { 2411 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 2412 return 0; 2413 2414 mtk_clk_disable(eth); 2415 2416 pm_runtime_put_sync(eth->dev); 2417 pm_runtime_disable(eth->dev); 2418 2419 return 0; 2420 } 2421 2422 static int __init mtk_init(struct net_device *dev) 2423 { 2424 struct mtk_mac *mac = netdev_priv(dev); 2425 struct mtk_eth *eth = mac->hw; 2426 const char *mac_addr; 2427 2428 mac_addr = of_get_mac_address(mac->of_node); 2429 if (!IS_ERR(mac_addr)) 2430 ether_addr_copy(dev->dev_addr, mac_addr); 2431 2432 /* If the mac address is invalid, use random mac address */ 2433 if (!is_valid_ether_addr(dev->dev_addr)) { 2434 eth_hw_addr_random(dev); 2435 dev_err(eth->dev, "generated random MAC address %pM\n", 2436 dev->dev_addr); 2437 } 2438 2439 return 0; 2440 } 2441 2442 static void mtk_uninit(struct net_device *dev) 2443 { 2444 struct mtk_mac *mac = netdev_priv(dev); 2445 struct mtk_eth *eth = mac->hw; 2446 2447 phylink_disconnect_phy(mac->phylink); 2448 mtk_tx_irq_disable(eth, ~0); 2449 mtk_rx_irq_disable(eth, ~0); 2450 } 2451 2452 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2453 { 2454 struct mtk_mac *mac = netdev_priv(dev); 2455 2456 switch (cmd) { 2457 case SIOCGMIIPHY: 2458 case SIOCGMIIREG: 2459 case SIOCSMIIREG: 2460 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 2461 default: 2462 break; 2463 } 2464 2465 return -EOPNOTSUPP; 2466 } 2467 2468 static void mtk_pending_work(struct work_struct *work) 2469 { 2470 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 2471 int err, i; 2472 unsigned long restart = 0; 2473 2474 rtnl_lock(); 2475 2476 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__); 2477 2478 while (test_and_set_bit_lock(MTK_RESETTING, ð->state)) 2479 cpu_relax(); 2480 2481 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__); 2482 /* stop all devices to make sure that dma is properly shut down */ 2483 for (i = 0; i < MTK_MAC_COUNT; i++) { 2484 if (!eth->netdev[i]) 2485 continue; 2486 mtk_stop(eth->netdev[i]); 2487 __set_bit(i, &restart); 2488 } 2489 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__); 2490 2491 /* restart underlying hardware such as power, clock, pin mux 2492 * and the connected phy 2493 */ 2494 mtk_hw_deinit(eth); 2495 2496 if (eth->dev->pins) 2497 pinctrl_select_state(eth->dev->pins->p, 2498 eth->dev->pins->default_state); 2499 mtk_hw_init(eth); 2500 2501 /* restart DMA and enable IRQs */ 2502 for (i = 0; i < MTK_MAC_COUNT; i++) { 2503 if (!test_bit(i, &restart)) 2504 continue; 2505 err = mtk_open(eth->netdev[i]); 2506 if (err) { 2507 netif_alert(eth, ifup, eth->netdev[i], 2508 "Driver up/down cycle failed, closing device.\n"); 2509 dev_close(eth->netdev[i]); 2510 } 2511 } 2512 2513 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__); 2514 2515 clear_bit_unlock(MTK_RESETTING, ð->state); 2516 2517 rtnl_unlock(); 2518 } 2519 2520 static int mtk_free_dev(struct mtk_eth *eth) 2521 { 2522 int i; 2523 2524 for (i = 0; i < MTK_MAC_COUNT; i++) { 2525 if (!eth->netdev[i]) 2526 continue; 2527 free_netdev(eth->netdev[i]); 2528 } 2529 2530 return 0; 2531 } 2532 2533 static int mtk_unreg_dev(struct mtk_eth *eth) 2534 { 2535 int i; 2536 2537 for (i = 0; i < MTK_MAC_COUNT; i++) { 2538 if (!eth->netdev[i]) 2539 continue; 2540 unregister_netdev(eth->netdev[i]); 2541 } 2542 2543 return 0; 2544 } 2545 2546 static int mtk_cleanup(struct mtk_eth *eth) 2547 { 2548 mtk_unreg_dev(eth); 2549 mtk_free_dev(eth); 2550 cancel_work_sync(ð->pending_work); 2551 2552 return 0; 2553 } 2554 2555 static int mtk_get_link_ksettings(struct net_device *ndev, 2556 struct ethtool_link_ksettings *cmd) 2557 { 2558 struct mtk_mac *mac = netdev_priv(ndev); 2559 2560 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2561 return -EBUSY; 2562 2563 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 2564 } 2565 2566 static int mtk_set_link_ksettings(struct net_device *ndev, 2567 const struct ethtool_link_ksettings *cmd) 2568 { 2569 struct mtk_mac *mac = netdev_priv(ndev); 2570 2571 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2572 return -EBUSY; 2573 2574 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 2575 } 2576 2577 static void mtk_get_drvinfo(struct net_device *dev, 2578 struct ethtool_drvinfo *info) 2579 { 2580 struct mtk_mac *mac = netdev_priv(dev); 2581 2582 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 2583 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 2584 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 2585 } 2586 2587 static u32 mtk_get_msglevel(struct net_device *dev) 2588 { 2589 struct mtk_mac *mac = netdev_priv(dev); 2590 2591 return mac->hw->msg_enable; 2592 } 2593 2594 static void mtk_set_msglevel(struct net_device *dev, u32 value) 2595 { 2596 struct mtk_mac *mac = netdev_priv(dev); 2597 2598 mac->hw->msg_enable = value; 2599 } 2600 2601 static int mtk_nway_reset(struct net_device *dev) 2602 { 2603 struct mtk_mac *mac = netdev_priv(dev); 2604 2605 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2606 return -EBUSY; 2607 2608 if (!mac->phylink) 2609 return -ENOTSUPP; 2610 2611 return phylink_ethtool_nway_reset(mac->phylink); 2612 } 2613 2614 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2615 { 2616 int i; 2617 2618 switch (stringset) { 2619 case ETH_SS_STATS: 2620 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 2621 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 2622 data += ETH_GSTRING_LEN; 2623 } 2624 break; 2625 } 2626 } 2627 2628 static int mtk_get_sset_count(struct net_device *dev, int sset) 2629 { 2630 switch (sset) { 2631 case ETH_SS_STATS: 2632 return ARRAY_SIZE(mtk_ethtool_stats); 2633 default: 2634 return -EOPNOTSUPP; 2635 } 2636 } 2637 2638 static void mtk_get_ethtool_stats(struct net_device *dev, 2639 struct ethtool_stats *stats, u64 *data) 2640 { 2641 struct mtk_mac *mac = netdev_priv(dev); 2642 struct mtk_hw_stats *hwstats = mac->hw_stats; 2643 u64 *data_src, *data_dst; 2644 unsigned int start; 2645 int i; 2646 2647 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 2648 return; 2649 2650 if (netif_running(dev) && netif_device_present(dev)) { 2651 if (spin_trylock_bh(&hwstats->stats_lock)) { 2652 mtk_stats_update_mac(mac); 2653 spin_unlock_bh(&hwstats->stats_lock); 2654 } 2655 } 2656 2657 data_src = (u64 *)hwstats; 2658 2659 do { 2660 data_dst = data; 2661 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 2662 2663 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 2664 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 2665 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 2666 } 2667 2668 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2669 u32 *rule_locs) 2670 { 2671 int ret = -EOPNOTSUPP; 2672 2673 switch (cmd->cmd) { 2674 case ETHTOOL_GRXRINGS: 2675 if (dev->hw_features & NETIF_F_LRO) { 2676 cmd->data = MTK_MAX_RX_RING_NUM; 2677 ret = 0; 2678 } 2679 break; 2680 case ETHTOOL_GRXCLSRLCNT: 2681 if (dev->hw_features & NETIF_F_LRO) { 2682 struct mtk_mac *mac = netdev_priv(dev); 2683 2684 cmd->rule_cnt = mac->hwlro_ip_cnt; 2685 ret = 0; 2686 } 2687 break; 2688 case ETHTOOL_GRXCLSRULE: 2689 if (dev->hw_features & NETIF_F_LRO) 2690 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 2691 break; 2692 case ETHTOOL_GRXCLSRLALL: 2693 if (dev->hw_features & NETIF_F_LRO) 2694 ret = mtk_hwlro_get_fdir_all(dev, cmd, 2695 rule_locs); 2696 break; 2697 default: 2698 break; 2699 } 2700 2701 return ret; 2702 } 2703 2704 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2705 { 2706 int ret = -EOPNOTSUPP; 2707 2708 switch (cmd->cmd) { 2709 case ETHTOOL_SRXCLSRLINS: 2710 if (dev->hw_features & NETIF_F_LRO) 2711 ret = mtk_hwlro_add_ipaddr(dev, cmd); 2712 break; 2713 case ETHTOOL_SRXCLSRLDEL: 2714 if (dev->hw_features & NETIF_F_LRO) 2715 ret = mtk_hwlro_del_ipaddr(dev, cmd); 2716 break; 2717 default: 2718 break; 2719 } 2720 2721 return ret; 2722 } 2723 2724 static const struct ethtool_ops mtk_ethtool_ops = { 2725 .get_link_ksettings = mtk_get_link_ksettings, 2726 .set_link_ksettings = mtk_set_link_ksettings, 2727 .get_drvinfo = mtk_get_drvinfo, 2728 .get_msglevel = mtk_get_msglevel, 2729 .set_msglevel = mtk_set_msglevel, 2730 .nway_reset = mtk_nway_reset, 2731 .get_link = ethtool_op_get_link, 2732 .get_strings = mtk_get_strings, 2733 .get_sset_count = mtk_get_sset_count, 2734 .get_ethtool_stats = mtk_get_ethtool_stats, 2735 .get_rxnfc = mtk_get_rxnfc, 2736 .set_rxnfc = mtk_set_rxnfc, 2737 }; 2738 2739 static const struct net_device_ops mtk_netdev_ops = { 2740 .ndo_init = mtk_init, 2741 .ndo_uninit = mtk_uninit, 2742 .ndo_open = mtk_open, 2743 .ndo_stop = mtk_stop, 2744 .ndo_start_xmit = mtk_start_xmit, 2745 .ndo_set_mac_address = mtk_set_mac_address, 2746 .ndo_validate_addr = eth_validate_addr, 2747 .ndo_do_ioctl = mtk_do_ioctl, 2748 .ndo_tx_timeout = mtk_tx_timeout, 2749 .ndo_get_stats64 = mtk_get_stats64, 2750 .ndo_fix_features = mtk_fix_features, 2751 .ndo_set_features = mtk_set_features, 2752 #ifdef CONFIG_NET_POLL_CONTROLLER 2753 .ndo_poll_controller = mtk_poll_controller, 2754 #endif 2755 }; 2756 2757 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 2758 { 2759 const __be32 *_id = of_get_property(np, "reg", NULL); 2760 struct phylink *phylink; 2761 int phy_mode, id, err; 2762 struct mtk_mac *mac; 2763 2764 if (!_id) { 2765 dev_err(eth->dev, "missing mac id\n"); 2766 return -EINVAL; 2767 } 2768 2769 id = be32_to_cpup(_id); 2770 if (id >= MTK_MAC_COUNT) { 2771 dev_err(eth->dev, "%d is not a valid mac id\n", id); 2772 return -EINVAL; 2773 } 2774 2775 if (eth->netdev[id]) { 2776 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 2777 return -EINVAL; 2778 } 2779 2780 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 2781 if (!eth->netdev[id]) { 2782 dev_err(eth->dev, "alloc_etherdev failed\n"); 2783 return -ENOMEM; 2784 } 2785 mac = netdev_priv(eth->netdev[id]); 2786 eth->mac[id] = mac; 2787 mac->id = id; 2788 mac->hw = eth; 2789 mac->of_node = np; 2790 2791 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 2792 mac->hwlro_ip_cnt = 0; 2793 2794 mac->hw_stats = devm_kzalloc(eth->dev, 2795 sizeof(*mac->hw_stats), 2796 GFP_KERNEL); 2797 if (!mac->hw_stats) { 2798 dev_err(eth->dev, "failed to allocate counter memory\n"); 2799 err = -ENOMEM; 2800 goto free_netdev; 2801 } 2802 spin_lock_init(&mac->hw_stats->stats_lock); 2803 u64_stats_init(&mac->hw_stats->syncp); 2804 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 2805 2806 /* phylink create */ 2807 phy_mode = of_get_phy_mode(np); 2808 if (phy_mode < 0) { 2809 dev_err(eth->dev, "incorrect phy-mode\n"); 2810 err = -EINVAL; 2811 goto free_netdev; 2812 } 2813 2814 /* mac config is not set */ 2815 mac->interface = PHY_INTERFACE_MODE_NA; 2816 mac->mode = MLO_AN_PHY; 2817 mac->speed = SPEED_UNKNOWN; 2818 2819 mac->phylink_config.dev = ð->netdev[id]->dev; 2820 mac->phylink_config.type = PHYLINK_NETDEV; 2821 2822 phylink = phylink_create(&mac->phylink_config, 2823 of_fwnode_handle(mac->of_node), 2824 phy_mode, &mtk_phylink_ops); 2825 if (IS_ERR(phylink)) { 2826 err = PTR_ERR(phylink); 2827 goto free_netdev; 2828 } 2829 2830 mac->phylink = phylink; 2831 2832 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 2833 eth->netdev[id]->watchdog_timeo = 5 * HZ; 2834 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 2835 eth->netdev[id]->base_addr = (unsigned long)eth->base; 2836 2837 eth->netdev[id]->hw_features = eth->soc->hw_features; 2838 if (eth->hwlro) 2839 eth->netdev[id]->hw_features |= NETIF_F_LRO; 2840 2841 eth->netdev[id]->vlan_features = eth->soc->hw_features & 2842 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 2843 eth->netdev[id]->features |= eth->soc->hw_features; 2844 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 2845 2846 eth->netdev[id]->irq = eth->irq[0]; 2847 eth->netdev[id]->dev.of_node = np; 2848 2849 return 0; 2850 2851 free_netdev: 2852 free_netdev(eth->netdev[id]); 2853 return err; 2854 } 2855 2856 static int mtk_probe(struct platform_device *pdev) 2857 { 2858 struct device_node *mac_np; 2859 struct mtk_eth *eth; 2860 int err, i; 2861 2862 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2863 if (!eth) 2864 return -ENOMEM; 2865 2866 eth->soc = of_device_get_match_data(&pdev->dev); 2867 2868 eth->dev = &pdev->dev; 2869 eth->base = devm_platform_ioremap_resource(pdev, 0); 2870 if (IS_ERR(eth->base)) 2871 return PTR_ERR(eth->base); 2872 2873 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2874 eth->tx_int_mask_reg = MTK_QDMA_INT_MASK; 2875 eth->tx_int_status_reg = MTK_QDMA_INT_STATUS; 2876 } else { 2877 eth->tx_int_mask_reg = MTK_PDMA_INT_MASK; 2878 eth->tx_int_status_reg = MTK_PDMA_INT_STATUS; 2879 } 2880 2881 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2882 eth->rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA; 2883 eth->ip_align = NET_IP_ALIGN; 2884 } else { 2885 eth->rx_dma_l4_valid = RX_DMA_L4_VALID; 2886 } 2887 2888 spin_lock_init(ð->page_lock); 2889 spin_lock_init(ð->tx_irq_lock); 2890 spin_lock_init(ð->rx_irq_lock); 2891 2892 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 2893 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2894 "mediatek,ethsys"); 2895 if (IS_ERR(eth->ethsys)) { 2896 dev_err(&pdev->dev, "no ethsys regmap found\n"); 2897 return PTR_ERR(eth->ethsys); 2898 } 2899 } 2900 2901 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 2902 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2903 "mediatek,infracfg"); 2904 if (IS_ERR(eth->infra)) { 2905 dev_err(&pdev->dev, "no infracfg regmap found\n"); 2906 return PTR_ERR(eth->infra); 2907 } 2908 } 2909 2910 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 2911 eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii), 2912 GFP_KERNEL); 2913 if (!eth->sgmii) 2914 return -ENOMEM; 2915 2916 err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node, 2917 eth->soc->ana_rgc3); 2918 2919 if (err) 2920 return err; 2921 } 2922 2923 if (eth->soc->required_pctl) { 2924 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2925 "mediatek,pctl"); 2926 if (IS_ERR(eth->pctl)) { 2927 dev_err(&pdev->dev, "no pctl regmap found\n"); 2928 return PTR_ERR(eth->pctl); 2929 } 2930 } 2931 2932 for (i = 0; i < 3; i++) { 2933 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 2934 eth->irq[i] = eth->irq[0]; 2935 else 2936 eth->irq[i] = platform_get_irq(pdev, i); 2937 if (eth->irq[i] < 0) { 2938 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 2939 return -ENXIO; 2940 } 2941 } 2942 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 2943 eth->clks[i] = devm_clk_get(eth->dev, 2944 mtk_clks_source_name[i]); 2945 if (IS_ERR(eth->clks[i])) { 2946 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) 2947 return -EPROBE_DEFER; 2948 if (eth->soc->required_clks & BIT(i)) { 2949 dev_err(&pdev->dev, "clock %s not found\n", 2950 mtk_clks_source_name[i]); 2951 return -EINVAL; 2952 } 2953 eth->clks[i] = NULL; 2954 } 2955 } 2956 2957 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 2958 INIT_WORK(ð->pending_work, mtk_pending_work); 2959 2960 err = mtk_hw_init(eth); 2961 if (err) 2962 return err; 2963 2964 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 2965 2966 for_each_child_of_node(pdev->dev.of_node, mac_np) { 2967 if (!of_device_is_compatible(mac_np, 2968 "mediatek,eth-mac")) 2969 continue; 2970 2971 if (!of_device_is_available(mac_np)) 2972 continue; 2973 2974 err = mtk_add_mac(eth, mac_np); 2975 if (err) { 2976 of_node_put(mac_np); 2977 goto err_deinit_hw; 2978 } 2979 } 2980 2981 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 2982 err = devm_request_irq(eth->dev, eth->irq[0], 2983 mtk_handle_irq, 0, 2984 dev_name(eth->dev), eth); 2985 } else { 2986 err = devm_request_irq(eth->dev, eth->irq[1], 2987 mtk_handle_irq_tx, 0, 2988 dev_name(eth->dev), eth); 2989 if (err) 2990 goto err_free_dev; 2991 2992 err = devm_request_irq(eth->dev, eth->irq[2], 2993 mtk_handle_irq_rx, 0, 2994 dev_name(eth->dev), eth); 2995 } 2996 if (err) 2997 goto err_free_dev; 2998 2999 /* No MT7628/88 support yet */ 3000 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3001 err = mtk_mdio_init(eth); 3002 if (err) 3003 goto err_free_dev; 3004 } 3005 3006 for (i = 0; i < MTK_MAX_DEVS; i++) { 3007 if (!eth->netdev[i]) 3008 continue; 3009 3010 err = register_netdev(eth->netdev[i]); 3011 if (err) { 3012 dev_err(eth->dev, "error bringing up device\n"); 3013 goto err_deinit_mdio; 3014 } else 3015 netif_info(eth, probe, eth->netdev[i], 3016 "mediatek frame engine at 0x%08lx, irq %d\n", 3017 eth->netdev[i]->base_addr, eth->irq[0]); 3018 } 3019 3020 /* we run 2 devices on the same DMA ring so we need a dummy device 3021 * for NAPI to work 3022 */ 3023 init_dummy_netdev(ð->dummy_dev); 3024 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx, 3025 MTK_NAPI_WEIGHT); 3026 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx, 3027 MTK_NAPI_WEIGHT); 3028 3029 platform_set_drvdata(pdev, eth); 3030 3031 return 0; 3032 3033 err_deinit_mdio: 3034 mtk_mdio_cleanup(eth); 3035 err_free_dev: 3036 mtk_free_dev(eth); 3037 err_deinit_hw: 3038 mtk_hw_deinit(eth); 3039 3040 return err; 3041 } 3042 3043 static int mtk_remove(struct platform_device *pdev) 3044 { 3045 struct mtk_eth *eth = platform_get_drvdata(pdev); 3046 struct mtk_mac *mac; 3047 int i; 3048 3049 /* stop all devices to make sure that dma is properly shut down */ 3050 for (i = 0; i < MTK_MAC_COUNT; i++) { 3051 if (!eth->netdev[i]) 3052 continue; 3053 mtk_stop(eth->netdev[i]); 3054 mac = netdev_priv(eth->netdev[i]); 3055 phylink_disconnect_phy(mac->phylink); 3056 } 3057 3058 mtk_hw_deinit(eth); 3059 3060 netif_napi_del(ð->tx_napi); 3061 netif_napi_del(ð->rx_napi); 3062 mtk_cleanup(eth); 3063 mtk_mdio_cleanup(eth); 3064 3065 return 0; 3066 } 3067 3068 static const struct mtk_soc_data mt2701_data = { 3069 .caps = MT7623_CAPS | MTK_HWLRO, 3070 .hw_features = MTK_HW_FEATURES, 3071 .required_clks = MT7623_CLKS_BITMAP, 3072 .required_pctl = true, 3073 }; 3074 3075 static const struct mtk_soc_data mt7621_data = { 3076 .caps = MT7621_CAPS, 3077 .hw_features = MTK_HW_FEATURES, 3078 .required_clks = MT7621_CLKS_BITMAP, 3079 .required_pctl = false, 3080 }; 3081 3082 static const struct mtk_soc_data mt7622_data = { 3083 .ana_rgc3 = 0x2028, 3084 .caps = MT7622_CAPS | MTK_HWLRO, 3085 .hw_features = MTK_HW_FEATURES, 3086 .required_clks = MT7622_CLKS_BITMAP, 3087 .required_pctl = false, 3088 }; 3089 3090 static const struct mtk_soc_data mt7623_data = { 3091 .caps = MT7623_CAPS | MTK_HWLRO, 3092 .hw_features = MTK_HW_FEATURES, 3093 .required_clks = MT7623_CLKS_BITMAP, 3094 .required_pctl = true, 3095 }; 3096 3097 static const struct mtk_soc_data mt7629_data = { 3098 .ana_rgc3 = 0x128, 3099 .caps = MT7629_CAPS | MTK_HWLRO, 3100 .hw_features = MTK_HW_FEATURES, 3101 .required_clks = MT7629_CLKS_BITMAP, 3102 .required_pctl = false, 3103 }; 3104 3105 static const struct mtk_soc_data rt5350_data = { 3106 .caps = MT7628_CAPS, 3107 .hw_features = MTK_HW_FEATURES_MT7628, 3108 .required_clks = MT7628_CLKS_BITMAP, 3109 .required_pctl = false, 3110 }; 3111 3112 const struct of_device_id of_mtk_match[] = { 3113 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 3114 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 3115 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 3116 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 3117 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 3118 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 3119 {}, 3120 }; 3121 MODULE_DEVICE_TABLE(of, of_mtk_match); 3122 3123 static struct platform_driver mtk_driver = { 3124 .probe = mtk_probe, 3125 .remove = mtk_remove, 3126 .driver = { 3127 .name = "mtk_soc_eth", 3128 .of_match_table = of_mtk_match, 3129 }, 3130 }; 3131 3132 module_platform_driver(mtk_driver); 3133 3134 MODULE_LICENSE("GPL"); 3135 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 3136 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 3137