1 /* This program is free software; you can redistribute it and/or modify 2 * it under the terms of the GNU General Public License as published by 3 * the Free Software Foundation; version 2 of the License 4 * 5 * This program is distributed in the hope that it will be useful, 6 * but WITHOUT ANY WARRANTY; without even the implied warranty of 7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8 * GNU General Public License for more details. 9 * 10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 13 */ 14 15 #include <linux/of_device.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_net.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/regmap.h> 20 #include <linux/clk.h> 21 #include <linux/if_vlan.h> 22 #include <linux/reset.h> 23 #include <linux/tcp.h> 24 25 #include "mtk_eth_soc.h" 26 27 static int mtk_msg_level = -1; 28 module_param_named(msg_level, mtk_msg_level, int, 0); 29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 30 31 #define MTK_ETHTOOL_STAT(x) { #x, \ 32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 33 34 /* strings used by ethtool */ 35 static const struct mtk_ethtool_stats { 36 char str[ETH_GSTRING_LEN]; 37 u32 offset; 38 } mtk_ethtool_stats[] = { 39 MTK_ETHTOOL_STAT(tx_bytes), 40 MTK_ETHTOOL_STAT(tx_packets), 41 MTK_ETHTOOL_STAT(tx_skip), 42 MTK_ETHTOOL_STAT(tx_collisions), 43 MTK_ETHTOOL_STAT(rx_bytes), 44 MTK_ETHTOOL_STAT(rx_packets), 45 MTK_ETHTOOL_STAT(rx_overflow), 46 MTK_ETHTOOL_STAT(rx_fcs_errors), 47 MTK_ETHTOOL_STAT(rx_short_errors), 48 MTK_ETHTOOL_STAT(rx_long_errors), 49 MTK_ETHTOOL_STAT(rx_checksum_errors), 50 MTK_ETHTOOL_STAT(rx_flow_control_packets), 51 }; 52 53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 54 { 55 __raw_writel(val, eth->base + reg); 56 } 57 58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 59 { 60 return __raw_readl(eth->base + reg); 61 } 62 63 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 64 { 65 unsigned long t_start = jiffies; 66 67 while (1) { 68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 69 return 0; 70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 71 break; 72 usleep_range(10, 20); 73 } 74 75 dev_err(eth->dev, "mdio: MDIO timeout\n"); 76 return -1; 77 } 78 79 u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, 80 u32 phy_register, u32 write_data) 81 { 82 if (mtk_mdio_busy_wait(eth)) 83 return -1; 84 85 write_data &= 0xffff; 86 87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE | 88 (phy_register << PHY_IAC_REG_SHIFT) | 89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data, 90 MTK_PHY_IAC); 91 92 if (mtk_mdio_busy_wait(eth)) 93 return -1; 94 95 return 0; 96 } 97 98 u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg) 99 { 100 u32 d; 101 102 if (mtk_mdio_busy_wait(eth)) 103 return 0xffff; 104 105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ | 106 (phy_reg << PHY_IAC_REG_SHIFT) | 107 (phy_addr << PHY_IAC_ADDR_SHIFT), 108 MTK_PHY_IAC); 109 110 if (mtk_mdio_busy_wait(eth)) 111 return 0xffff; 112 113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff; 114 115 return d; 116 } 117 118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr, 119 int phy_reg, u16 val) 120 { 121 struct mtk_eth *eth = bus->priv; 122 123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val); 124 } 125 126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg) 127 { 128 struct mtk_eth *eth = bus->priv; 129 130 return _mtk_mdio_read(eth, phy_addr, phy_reg); 131 } 132 133 static void mtk_phy_link_adjust(struct net_device *dev) 134 { 135 struct mtk_mac *mac = netdev_priv(dev); 136 u16 lcl_adv = 0, rmt_adv = 0; 137 u8 flowctrl; 138 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | 139 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | 140 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | 141 MAC_MCR_BACKPR_EN; 142 143 switch (mac->phy_dev->speed) { 144 case SPEED_1000: 145 mcr |= MAC_MCR_SPEED_1000; 146 break; 147 case SPEED_100: 148 mcr |= MAC_MCR_SPEED_100; 149 break; 150 }; 151 152 if (mac->phy_dev->link) 153 mcr |= MAC_MCR_FORCE_LINK; 154 155 if (mac->phy_dev->duplex) { 156 mcr |= MAC_MCR_FORCE_DPX; 157 158 if (mac->phy_dev->pause) 159 rmt_adv = LPA_PAUSE_CAP; 160 if (mac->phy_dev->asym_pause) 161 rmt_adv |= LPA_PAUSE_ASYM; 162 163 if (mac->phy_dev->advertising & ADVERTISED_Pause) 164 lcl_adv |= ADVERTISE_PAUSE_CAP; 165 if (mac->phy_dev->advertising & ADVERTISED_Asym_Pause) 166 lcl_adv |= ADVERTISE_PAUSE_ASYM; 167 168 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 169 170 if (flowctrl & FLOW_CTRL_TX) 171 mcr |= MAC_MCR_FORCE_TX_FC; 172 if (flowctrl & FLOW_CTRL_RX) 173 mcr |= MAC_MCR_FORCE_RX_FC; 174 175 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n", 176 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled", 177 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled"); 178 } 179 180 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 181 182 if (mac->phy_dev->link) 183 netif_carrier_on(dev); 184 else 185 netif_carrier_off(dev); 186 } 187 188 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac, 189 struct device_node *phy_node) 190 { 191 const __be32 *_addr = NULL; 192 struct phy_device *phydev; 193 int phy_mode, addr; 194 195 _addr = of_get_property(phy_node, "reg", NULL); 196 197 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) { 198 pr_err("%s: invalid phy address\n", phy_node->name); 199 return -EINVAL; 200 } 201 addr = be32_to_cpu(*_addr); 202 phy_mode = of_get_phy_mode(phy_node); 203 if (phy_mode < 0) { 204 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode); 205 return -EINVAL; 206 } 207 208 phydev = of_phy_connect(eth->netdev[mac->id], phy_node, 209 mtk_phy_link_adjust, 0, phy_mode); 210 if (!phydev) { 211 dev_err(eth->dev, "could not connect to PHY\n"); 212 return -ENODEV; 213 } 214 215 dev_info(eth->dev, 216 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n", 217 mac->id, phydev_name(phydev), phydev->phy_id, 218 phydev->drv->name); 219 220 mac->phy_dev = phydev; 221 222 return 0; 223 } 224 225 static int mtk_phy_connect(struct mtk_mac *mac) 226 { 227 struct mtk_eth *eth = mac->hw; 228 struct device_node *np; 229 u32 val, ge_mode; 230 231 np = of_parse_phandle(mac->of_node, "phy-handle", 0); 232 if (!np && of_phy_is_fixed_link(mac->of_node)) 233 if (!of_phy_register_fixed_link(mac->of_node)) 234 np = of_node_get(mac->of_node); 235 if (!np) 236 return -ENODEV; 237 238 switch (of_get_phy_mode(np)) { 239 case PHY_INTERFACE_MODE_RGMII_TXID: 240 case PHY_INTERFACE_MODE_RGMII_RXID: 241 case PHY_INTERFACE_MODE_RGMII_ID: 242 case PHY_INTERFACE_MODE_RGMII: 243 ge_mode = 0; 244 break; 245 case PHY_INTERFACE_MODE_MII: 246 ge_mode = 1; 247 break; 248 case PHY_INTERFACE_MODE_RMII: 249 ge_mode = 2; 250 break; 251 default: 252 dev_err(eth->dev, "invalid phy_mode\n"); 253 return -1; 254 } 255 256 /* put the gmac into the right mode */ 257 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 258 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 259 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 260 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 261 262 mtk_phy_connect_node(eth, mac, np); 263 mac->phy_dev->autoneg = AUTONEG_ENABLE; 264 mac->phy_dev->speed = 0; 265 mac->phy_dev->duplex = 0; 266 mac->phy_dev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause | 267 SUPPORTED_Asym_Pause; 268 mac->phy_dev->advertising = mac->phy_dev->supported | 269 ADVERTISED_Autoneg; 270 phy_start_aneg(mac->phy_dev); 271 272 return 0; 273 } 274 275 static int mtk_mdio_init(struct mtk_eth *eth) 276 { 277 struct device_node *mii_np; 278 int err; 279 280 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 281 if (!mii_np) { 282 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 283 return -ENODEV; 284 } 285 286 if (!of_device_is_available(mii_np)) { 287 err = 0; 288 goto err_put_node; 289 } 290 291 eth->mii_bus = mdiobus_alloc(); 292 if (!eth->mii_bus) { 293 err = -ENOMEM; 294 goto err_put_node; 295 } 296 297 eth->mii_bus->name = "mdio"; 298 eth->mii_bus->read = mtk_mdio_read; 299 eth->mii_bus->write = mtk_mdio_write; 300 eth->mii_bus->priv = eth; 301 eth->mii_bus->parent = eth->dev; 302 303 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name); 304 err = of_mdiobus_register(eth->mii_bus, mii_np); 305 if (err) 306 goto err_free_bus; 307 308 return 0; 309 310 err_free_bus: 311 mdiobus_free(eth->mii_bus); 312 313 err_put_node: 314 of_node_put(mii_np); 315 eth->mii_bus = NULL; 316 return err; 317 } 318 319 static void mtk_mdio_cleanup(struct mtk_eth *eth) 320 { 321 if (!eth->mii_bus) 322 return; 323 324 mdiobus_unregister(eth->mii_bus); 325 of_node_put(eth->mii_bus->dev.of_node); 326 mdiobus_free(eth->mii_bus); 327 } 328 329 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask) 330 { 331 u32 val; 332 333 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 334 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK); 335 /* flush write */ 336 mtk_r32(eth, MTK_QDMA_INT_MASK); 337 } 338 339 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask) 340 { 341 u32 val; 342 343 val = mtk_r32(eth, MTK_QDMA_INT_MASK); 344 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK); 345 /* flush write */ 346 mtk_r32(eth, MTK_QDMA_INT_MASK); 347 } 348 349 static int mtk_set_mac_address(struct net_device *dev, void *p) 350 { 351 int ret = eth_mac_addr(dev, p); 352 struct mtk_mac *mac = netdev_priv(dev); 353 const char *macaddr = dev->dev_addr; 354 unsigned long flags; 355 356 if (ret) 357 return ret; 358 359 spin_lock_irqsave(&mac->hw->page_lock, flags); 360 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 361 MTK_GDMA_MAC_ADRH(mac->id)); 362 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 363 (macaddr[4] << 8) | macaddr[5], 364 MTK_GDMA_MAC_ADRL(mac->id)); 365 spin_unlock_irqrestore(&mac->hw->page_lock, flags); 366 367 return 0; 368 } 369 370 void mtk_stats_update_mac(struct mtk_mac *mac) 371 { 372 struct mtk_hw_stats *hw_stats = mac->hw_stats; 373 unsigned int base = MTK_GDM1_TX_GBCNT; 374 u64 stats; 375 376 base += hw_stats->reg_offset; 377 378 u64_stats_update_begin(&hw_stats->syncp); 379 380 hw_stats->rx_bytes += mtk_r32(mac->hw, base); 381 stats = mtk_r32(mac->hw, base + 0x04); 382 if (stats) 383 hw_stats->rx_bytes += (stats << 32); 384 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08); 385 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10); 386 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14); 387 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18); 388 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c); 389 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20); 390 hw_stats->rx_flow_control_packets += 391 mtk_r32(mac->hw, base + 0x24); 392 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28); 393 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c); 394 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30); 395 stats = mtk_r32(mac->hw, base + 0x34); 396 if (stats) 397 hw_stats->tx_bytes += (stats << 32); 398 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38); 399 u64_stats_update_end(&hw_stats->syncp); 400 } 401 402 static void mtk_stats_update(struct mtk_eth *eth) 403 { 404 int i; 405 406 for (i = 0; i < MTK_MAC_COUNT; i++) { 407 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 408 continue; 409 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 410 mtk_stats_update_mac(eth->mac[i]); 411 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 412 } 413 } 414 } 415 416 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev, 417 struct rtnl_link_stats64 *storage) 418 { 419 struct mtk_mac *mac = netdev_priv(dev); 420 struct mtk_hw_stats *hw_stats = mac->hw_stats; 421 unsigned int start; 422 423 if (netif_running(dev) && netif_device_present(dev)) { 424 if (spin_trylock(&hw_stats->stats_lock)) { 425 mtk_stats_update_mac(mac); 426 spin_unlock(&hw_stats->stats_lock); 427 } 428 } 429 430 do { 431 start = u64_stats_fetch_begin_irq(&hw_stats->syncp); 432 storage->rx_packets = hw_stats->rx_packets; 433 storage->tx_packets = hw_stats->tx_packets; 434 storage->rx_bytes = hw_stats->rx_bytes; 435 storage->tx_bytes = hw_stats->tx_bytes; 436 storage->collisions = hw_stats->tx_collisions; 437 storage->rx_length_errors = hw_stats->rx_short_errors + 438 hw_stats->rx_long_errors; 439 storage->rx_over_errors = hw_stats->rx_overflow; 440 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 441 storage->rx_errors = hw_stats->rx_checksum_errors; 442 storage->tx_aborted_errors = hw_stats->tx_skip; 443 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start)); 444 445 storage->tx_errors = dev->stats.tx_errors; 446 storage->rx_dropped = dev->stats.rx_dropped; 447 storage->tx_dropped = dev->stats.tx_dropped; 448 449 return storage; 450 } 451 452 static inline int mtk_max_frag_size(int mtu) 453 { 454 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 455 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH) 456 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 457 458 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 459 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 460 } 461 462 static inline int mtk_max_buf_size(int frag_size) 463 { 464 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 465 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 466 467 WARN_ON(buf_size < MTK_MAX_RX_LENGTH); 468 469 return buf_size; 470 } 471 472 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd, 473 struct mtk_rx_dma *dma_rxd) 474 { 475 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 476 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 477 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 478 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 479 } 480 481 /* the qdma core needs scratch memory to be setup */ 482 static int mtk_init_fq_dma(struct mtk_eth *eth) 483 { 484 dma_addr_t phy_ring_tail; 485 int cnt = MTK_DMA_SIZE; 486 dma_addr_t dma_addr; 487 int i; 488 489 eth->scratch_ring = dma_alloc_coherent(eth->dev, 490 cnt * sizeof(struct mtk_tx_dma), 491 ð->phy_scratch_ring, 492 GFP_ATOMIC | __GFP_ZERO); 493 if (unlikely(!eth->scratch_ring)) 494 return -ENOMEM; 495 496 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, 497 GFP_KERNEL); 498 if (unlikely(!eth->scratch_head)) 499 return -ENOMEM; 500 501 dma_addr = dma_map_single(eth->dev, 502 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 503 DMA_FROM_DEVICE); 504 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 505 return -ENOMEM; 506 507 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt); 508 phy_ring_tail = eth->phy_scratch_ring + 509 (sizeof(struct mtk_tx_dma) * (cnt - 1)); 510 511 for (i = 0; i < cnt; i++) { 512 eth->scratch_ring[i].txd1 = 513 (dma_addr + (i * MTK_QDMA_PAGE_SIZE)); 514 if (i < cnt - 1) 515 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring + 516 ((i + 1) * sizeof(struct mtk_tx_dma))); 517 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE); 518 } 519 520 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD); 521 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL); 522 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT); 523 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN); 524 525 return 0; 526 } 527 528 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 529 { 530 void *ret = ring->dma; 531 532 return ret + (desc - ring->phys); 533 } 534 535 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 536 struct mtk_tx_dma *txd) 537 { 538 int idx = txd - ring->dma; 539 540 return &ring->buf[idx]; 541 } 542 543 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf) 544 { 545 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 546 dma_unmap_single(dev, 547 dma_unmap_addr(tx_buf, dma_addr0), 548 dma_unmap_len(tx_buf, dma_len0), 549 DMA_TO_DEVICE); 550 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 551 dma_unmap_page(dev, 552 dma_unmap_addr(tx_buf, dma_addr0), 553 dma_unmap_len(tx_buf, dma_len0), 554 DMA_TO_DEVICE); 555 } 556 tx_buf->flags = 0; 557 if (tx_buf->skb && 558 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC)) 559 dev_kfree_skb_any(tx_buf->skb); 560 tx_buf->skb = NULL; 561 } 562 563 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 564 int tx_num, struct mtk_tx_ring *ring, bool gso) 565 { 566 struct mtk_mac *mac = netdev_priv(dev); 567 struct mtk_eth *eth = mac->hw; 568 struct mtk_tx_dma *itxd, *txd; 569 struct mtk_tx_buf *tx_buf; 570 dma_addr_t mapped_addr; 571 unsigned int nr_frags; 572 int i, n_desc = 1; 573 u32 txd4 = 0; 574 575 itxd = ring->next_free; 576 if (itxd == ring->last_free) 577 return -ENOMEM; 578 579 /* set the forward port */ 580 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT; 581 582 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 583 memset(tx_buf, 0, sizeof(*tx_buf)); 584 585 if (gso) 586 txd4 |= TX_DMA_TSO; 587 588 /* TX Checksum offload */ 589 if (skb->ip_summed == CHECKSUM_PARTIAL) 590 txd4 |= TX_DMA_CHKSUM; 591 592 /* VLAN header offload */ 593 if (skb_vlan_tag_present(skb)) 594 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb); 595 596 mapped_addr = dma_map_single(&dev->dev, skb->data, 597 skb_headlen(skb), DMA_TO_DEVICE); 598 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 599 return -ENOMEM; 600 601 WRITE_ONCE(itxd->txd1, mapped_addr); 602 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 603 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 604 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb)); 605 606 /* TX SG offload */ 607 txd = itxd; 608 nr_frags = skb_shinfo(skb)->nr_frags; 609 for (i = 0; i < nr_frags; i++) { 610 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; 611 unsigned int offset = 0; 612 int frag_size = skb_frag_size(frag); 613 614 while (frag_size) { 615 bool last_frag = false; 616 unsigned int frag_map_size; 617 618 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 619 if (txd == ring->last_free) 620 goto err_dma; 621 622 n_desc++; 623 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN); 624 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset, 625 frag_map_size, 626 DMA_TO_DEVICE); 627 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr))) 628 goto err_dma; 629 630 if (i == nr_frags - 1 && 631 (frag_size - frag_map_size) == 0) 632 last_frag = true; 633 634 WRITE_ONCE(txd->txd1, mapped_addr); 635 WRITE_ONCE(txd->txd3, (TX_DMA_SWC | 636 TX_DMA_PLEN0(frag_map_size) | 637 last_frag * TX_DMA_LS0)); 638 WRITE_ONCE(txd->txd4, 0); 639 640 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC; 641 tx_buf = mtk_desc_to_tx_buf(ring, txd); 642 memset(tx_buf, 0, sizeof(*tx_buf)); 643 644 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 645 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 646 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size); 647 frag_size -= frag_map_size; 648 offset += frag_map_size; 649 } 650 } 651 652 /* store skb to cleanup */ 653 tx_buf->skb = skb; 654 655 WRITE_ONCE(itxd->txd4, txd4); 656 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) | 657 (!nr_frags * TX_DMA_LS0))); 658 659 netdev_sent_queue(dev, skb->len); 660 skb_tx_timestamp(skb); 661 662 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 663 atomic_sub(n_desc, &ring->free_count); 664 665 /* make sure that all changes to the dma ring are flushed before we 666 * continue 667 */ 668 wmb(); 669 670 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more) 671 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR); 672 673 return 0; 674 675 err_dma: 676 do { 677 tx_buf = mtk_desc_to_tx_buf(ring, itxd); 678 679 /* unmap dma */ 680 mtk_tx_unmap(&dev->dev, tx_buf); 681 682 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 683 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 684 } while (itxd != txd); 685 686 return -ENOMEM; 687 } 688 689 static inline int mtk_cal_txd_req(struct sk_buff *skb) 690 { 691 int i, nfrags; 692 struct skb_frag_struct *frag; 693 694 nfrags = 1; 695 if (skb_is_gso(skb)) { 696 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 697 frag = &skb_shinfo(skb)->frags[i]; 698 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN); 699 } 700 } else { 701 nfrags += skb_shinfo(skb)->nr_frags; 702 } 703 704 return nfrags; 705 } 706 707 static int mtk_queue_stopped(struct mtk_eth *eth) 708 { 709 int i; 710 711 for (i = 0; i < MTK_MAC_COUNT; i++) { 712 if (!eth->netdev[i]) 713 continue; 714 if (netif_queue_stopped(eth->netdev[i])) 715 return 1; 716 } 717 718 return 0; 719 } 720 721 static void mtk_wake_queue(struct mtk_eth *eth) 722 { 723 int i; 724 725 for (i = 0; i < MTK_MAC_COUNT; i++) { 726 if (!eth->netdev[i]) 727 continue; 728 netif_wake_queue(eth->netdev[i]); 729 } 730 } 731 732 static void mtk_stop_queue(struct mtk_eth *eth) 733 { 734 int i; 735 736 for (i = 0; i < MTK_MAC_COUNT; i++) { 737 if (!eth->netdev[i]) 738 continue; 739 netif_stop_queue(eth->netdev[i]); 740 } 741 } 742 743 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 744 { 745 struct mtk_mac *mac = netdev_priv(dev); 746 struct mtk_eth *eth = mac->hw; 747 struct mtk_tx_ring *ring = ð->tx_ring; 748 struct net_device_stats *stats = &dev->stats; 749 unsigned long flags; 750 bool gso = false; 751 int tx_num; 752 753 /* normally we can rely on the stack not calling this more than once, 754 * however we have 2 queues running on the same ring so we need to lock 755 * the ring access 756 */ 757 spin_lock_irqsave(ð->page_lock, flags); 758 759 tx_num = mtk_cal_txd_req(skb); 760 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 761 mtk_stop_queue(eth); 762 netif_err(eth, tx_queued, dev, 763 "Tx Ring full when queue awake!\n"); 764 spin_unlock_irqrestore(ð->page_lock, flags); 765 return NETDEV_TX_BUSY; 766 } 767 768 /* TSO: fill MSS info in tcp checksum field */ 769 if (skb_is_gso(skb)) { 770 if (skb_cow_head(skb, 0)) { 771 netif_warn(eth, tx_err, dev, 772 "GSO expand head fail.\n"); 773 goto drop; 774 } 775 776 if (skb_shinfo(skb)->gso_type & 777 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 778 gso = true; 779 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 780 } 781 } 782 783 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 784 goto drop; 785 786 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 787 mtk_stop_queue(eth); 788 789 spin_unlock_irqrestore(ð->page_lock, flags); 790 791 return NETDEV_TX_OK; 792 793 drop: 794 spin_unlock_irqrestore(ð->page_lock, flags); 795 stats->tx_dropped++; 796 dev_kfree_skb(skb); 797 return NETDEV_TX_OK; 798 } 799 800 static int mtk_poll_rx(struct napi_struct *napi, int budget, 801 struct mtk_eth *eth, u32 rx_intr) 802 { 803 struct mtk_rx_ring *ring = ð->rx_ring; 804 int idx = ring->calc_idx; 805 struct sk_buff *skb; 806 u8 *data, *new_data; 807 struct mtk_rx_dma *rxd, trxd; 808 int done = 0; 809 810 while (done < budget) { 811 struct net_device *netdev; 812 unsigned int pktlen; 813 dma_addr_t dma_addr; 814 int mac = 0; 815 816 idx = NEXT_RX_DESP_IDX(idx); 817 rxd = &ring->dma[idx]; 818 data = ring->data[idx]; 819 820 mtk_rx_get_desc(&trxd, rxd); 821 if (!(trxd.rxd2 & RX_DMA_DONE)) 822 break; 823 824 /* find out which mac the packet come from. values start at 1 */ 825 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) & 826 RX_DMA_FPORT_MASK; 827 mac--; 828 829 netdev = eth->netdev[mac]; 830 831 /* alloc new buffer */ 832 new_data = napi_alloc_frag(ring->frag_size); 833 if (unlikely(!new_data)) { 834 netdev->stats.rx_dropped++; 835 goto release_desc; 836 } 837 dma_addr = dma_map_single(ð->netdev[mac]->dev, 838 new_data + NET_SKB_PAD, 839 ring->buf_size, 840 DMA_FROM_DEVICE); 841 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) { 842 skb_free_frag(new_data); 843 netdev->stats.rx_dropped++; 844 goto release_desc; 845 } 846 847 /* receive data */ 848 skb = build_skb(data, ring->frag_size); 849 if (unlikely(!skb)) { 850 put_page(virt_to_head_page(new_data)); 851 netdev->stats.rx_dropped++; 852 goto release_desc; 853 } 854 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 855 856 dma_unmap_single(&netdev->dev, trxd.rxd1, 857 ring->buf_size, DMA_FROM_DEVICE); 858 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 859 skb->dev = netdev; 860 skb_put(skb, pktlen); 861 if (trxd.rxd4 & RX_DMA_L4_VALID) 862 skb->ip_summed = CHECKSUM_UNNECESSARY; 863 else 864 skb_checksum_none_assert(skb); 865 skb->protocol = eth_type_trans(skb, netdev); 866 867 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX && 868 RX_DMA_VID(trxd.rxd3)) 869 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 870 RX_DMA_VID(trxd.rxd3)); 871 napi_gro_receive(napi, skb); 872 873 ring->data[idx] = new_data; 874 rxd->rxd1 = (unsigned int)dma_addr; 875 876 release_desc: 877 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size); 878 879 ring->calc_idx = idx; 880 /* make sure that all changes to the dma ring are flushed before 881 * we continue 882 */ 883 wmb(); 884 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0); 885 done++; 886 } 887 888 if (done < budget) 889 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS); 890 891 return done; 892 } 893 894 static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again) 895 { 896 struct mtk_tx_ring *ring = ð->tx_ring; 897 struct mtk_tx_dma *desc; 898 struct sk_buff *skb; 899 struct mtk_tx_buf *tx_buf; 900 int total = 0, done[MTK_MAX_DEVS]; 901 unsigned int bytes[MTK_MAX_DEVS]; 902 u32 cpu, dma; 903 static int condition; 904 int i; 905 906 memset(done, 0, sizeof(done)); 907 memset(bytes, 0, sizeof(bytes)); 908 909 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR); 910 dma = mtk_r32(eth, MTK_QTX_DRX_PTR); 911 912 desc = mtk_qdma_phys_to_virt(ring, cpu); 913 914 while ((cpu != dma) && budget) { 915 u32 next_cpu = desc->txd2; 916 int mac; 917 918 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 919 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 920 break; 921 922 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) & 923 TX_DMA_FPORT_MASK; 924 mac--; 925 926 tx_buf = mtk_desc_to_tx_buf(ring, desc); 927 skb = tx_buf->skb; 928 if (!skb) { 929 condition = 1; 930 break; 931 } 932 933 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) { 934 bytes[mac] += skb->len; 935 done[mac]++; 936 budget--; 937 } 938 mtk_tx_unmap(eth->dev, tx_buf); 939 940 ring->last_free = desc; 941 atomic_inc(&ring->free_count); 942 943 cpu = next_cpu; 944 } 945 946 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR); 947 948 for (i = 0; i < MTK_MAC_COUNT; i++) { 949 if (!eth->netdev[i] || !done[i]) 950 continue; 951 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]); 952 total += done[i]; 953 } 954 955 /* read hw index again make sure no new tx packet */ 956 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR)) 957 *tx_again = true; 958 else 959 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS); 960 961 if (!total) 962 return 0; 963 964 if (mtk_queue_stopped(eth) && 965 (atomic_read(&ring->free_count) > ring->thresh)) 966 mtk_wake_queue(eth); 967 968 return total; 969 } 970 971 static int mtk_poll(struct napi_struct *napi, int budget) 972 { 973 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 974 u32 status, status2, mask, tx_intr, rx_intr, status_intr; 975 int tx_done, rx_done; 976 bool tx_again = false; 977 978 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 979 status2 = mtk_r32(eth, MTK_INT_STATUS2); 980 tx_intr = MTK_TX_DONE_INT; 981 rx_intr = MTK_RX_DONE_INT; 982 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF); 983 tx_done = 0; 984 rx_done = 0; 985 tx_again = 0; 986 987 if (status & tx_intr) 988 tx_done = mtk_poll_tx(eth, budget, &tx_again); 989 990 if (status & rx_intr) 991 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr); 992 993 if (unlikely(status2 & status_intr)) { 994 mtk_stats_update(eth); 995 mtk_w32(eth, status_intr, MTK_INT_STATUS2); 996 } 997 998 if (unlikely(netif_msg_intr(eth))) { 999 mask = mtk_r32(eth, MTK_QDMA_INT_MASK); 1000 netdev_info(eth->netdev[0], 1001 "done tx %d, rx %d, intr 0x%08x/0x%x\n", 1002 tx_done, rx_done, status, mask); 1003 } 1004 1005 if (tx_again || rx_done == budget) 1006 return budget; 1007 1008 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1009 if (status & (tx_intr | rx_intr)) 1010 return budget; 1011 1012 napi_complete(napi); 1013 mtk_irq_enable(eth, tx_intr | rx_intr); 1014 1015 return rx_done; 1016 } 1017 1018 static int mtk_tx_alloc(struct mtk_eth *eth) 1019 { 1020 struct mtk_tx_ring *ring = ð->tx_ring; 1021 int i, sz = sizeof(*ring->dma); 1022 1023 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf), 1024 GFP_KERNEL); 1025 if (!ring->buf) 1026 goto no_tx_mem; 1027 1028 ring->dma = dma_alloc_coherent(eth->dev, 1029 MTK_DMA_SIZE * sz, 1030 &ring->phys, 1031 GFP_ATOMIC | __GFP_ZERO); 1032 if (!ring->dma) 1033 goto no_tx_mem; 1034 1035 memset(ring->dma, 0, MTK_DMA_SIZE * sz); 1036 for (i = 0; i < MTK_DMA_SIZE; i++) { 1037 int next = (i + 1) % MTK_DMA_SIZE; 1038 u32 next_ptr = ring->phys + next * sz; 1039 1040 ring->dma[i].txd2 = next_ptr; 1041 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1042 } 1043 1044 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2); 1045 ring->next_free = &ring->dma[0]; 1046 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1]; 1047 ring->thresh = MAX_SKB_FRAGS; 1048 1049 /* make sure that all changes to the dma ring are flushed before we 1050 * continue 1051 */ 1052 wmb(); 1053 1054 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR); 1055 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR); 1056 mtk_w32(eth, 1057 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1058 MTK_QTX_CRX_PTR); 1059 mtk_w32(eth, 1060 ring->phys + ((MTK_DMA_SIZE - 1) * sz), 1061 MTK_QTX_DRX_PTR); 1062 1063 return 0; 1064 1065 no_tx_mem: 1066 return -ENOMEM; 1067 } 1068 1069 static void mtk_tx_clean(struct mtk_eth *eth) 1070 { 1071 struct mtk_tx_ring *ring = ð->tx_ring; 1072 int i; 1073 1074 if (ring->buf) { 1075 for (i = 0; i < MTK_DMA_SIZE; i++) 1076 mtk_tx_unmap(eth->dev, &ring->buf[i]); 1077 kfree(ring->buf); 1078 ring->buf = NULL; 1079 } 1080 1081 if (ring->dma) { 1082 dma_free_coherent(eth->dev, 1083 MTK_DMA_SIZE * sizeof(*ring->dma), 1084 ring->dma, 1085 ring->phys); 1086 ring->dma = NULL; 1087 } 1088 } 1089 1090 static int mtk_rx_alloc(struct mtk_eth *eth) 1091 { 1092 struct mtk_rx_ring *ring = ð->rx_ring; 1093 int i; 1094 1095 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN); 1096 ring->buf_size = mtk_max_buf_size(ring->frag_size); 1097 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data), 1098 GFP_KERNEL); 1099 if (!ring->data) 1100 return -ENOMEM; 1101 1102 for (i = 0; i < MTK_DMA_SIZE; i++) { 1103 ring->data[i] = netdev_alloc_frag(ring->frag_size); 1104 if (!ring->data[i]) 1105 return -ENOMEM; 1106 } 1107 1108 ring->dma = dma_alloc_coherent(eth->dev, 1109 MTK_DMA_SIZE * sizeof(*ring->dma), 1110 &ring->phys, 1111 GFP_ATOMIC | __GFP_ZERO); 1112 if (!ring->dma) 1113 return -ENOMEM; 1114 1115 for (i = 0; i < MTK_DMA_SIZE; i++) { 1116 dma_addr_t dma_addr = dma_map_single(eth->dev, 1117 ring->data[i] + NET_SKB_PAD, 1118 ring->buf_size, 1119 DMA_FROM_DEVICE); 1120 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) 1121 return -ENOMEM; 1122 ring->dma[i].rxd1 = (unsigned int)dma_addr; 1123 1124 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size); 1125 } 1126 ring->calc_idx = MTK_DMA_SIZE - 1; 1127 /* make sure that all changes to the dma ring are flushed before we 1128 * continue 1129 */ 1130 wmb(); 1131 1132 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0); 1133 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0); 1134 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0); 1135 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX); 1136 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0)); 1137 1138 return 0; 1139 } 1140 1141 static void mtk_rx_clean(struct mtk_eth *eth) 1142 { 1143 struct mtk_rx_ring *ring = ð->rx_ring; 1144 int i; 1145 1146 if (ring->data && ring->dma) { 1147 for (i = 0; i < MTK_DMA_SIZE; i++) { 1148 if (!ring->data[i]) 1149 continue; 1150 if (!ring->dma[i].rxd1) 1151 continue; 1152 dma_unmap_single(eth->dev, 1153 ring->dma[i].rxd1, 1154 ring->buf_size, 1155 DMA_FROM_DEVICE); 1156 skb_free_frag(ring->data[i]); 1157 } 1158 kfree(ring->data); 1159 ring->data = NULL; 1160 } 1161 1162 if (ring->dma) { 1163 dma_free_coherent(eth->dev, 1164 MTK_DMA_SIZE * sizeof(*ring->dma), 1165 ring->dma, 1166 ring->phys); 1167 ring->dma = NULL; 1168 } 1169 } 1170 1171 /* wait for DMA to finish whatever it is doing before we start using it again */ 1172 static int mtk_dma_busy_wait(struct mtk_eth *eth) 1173 { 1174 unsigned long t_start = jiffies; 1175 1176 while (1) { 1177 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) & 1178 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY))) 1179 return 0; 1180 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT)) 1181 break; 1182 } 1183 1184 dev_err(eth->dev, "DMA init timeout\n"); 1185 return -1; 1186 } 1187 1188 static int mtk_dma_init(struct mtk_eth *eth) 1189 { 1190 int err; 1191 1192 if (mtk_dma_busy_wait(eth)) 1193 return -EBUSY; 1194 1195 /* QDMA needs scratch memory for internal reordering of the 1196 * descriptors 1197 */ 1198 err = mtk_init_fq_dma(eth); 1199 if (err) 1200 return err; 1201 1202 err = mtk_tx_alloc(eth); 1203 if (err) 1204 return err; 1205 1206 err = mtk_rx_alloc(eth); 1207 if (err) 1208 return err; 1209 1210 /* Enable random early drop and set drop threshold automatically */ 1211 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN, 1212 MTK_QDMA_FC_THRES); 1213 mtk_w32(eth, 0x0, MTK_QDMA_HRED2); 1214 1215 return 0; 1216 } 1217 1218 static void mtk_dma_free(struct mtk_eth *eth) 1219 { 1220 int i; 1221 1222 for (i = 0; i < MTK_MAC_COUNT; i++) 1223 if (eth->netdev[i]) 1224 netdev_reset_queue(eth->netdev[i]); 1225 if (eth->scratch_ring) { 1226 dma_free_coherent(eth->dev, 1227 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma), 1228 eth->scratch_ring, 1229 eth->phy_scratch_ring); 1230 eth->scratch_ring = NULL; 1231 eth->phy_scratch_ring = 0; 1232 } 1233 mtk_tx_clean(eth); 1234 mtk_rx_clean(eth); 1235 kfree(eth->scratch_head); 1236 } 1237 1238 static void mtk_tx_timeout(struct net_device *dev) 1239 { 1240 struct mtk_mac *mac = netdev_priv(dev); 1241 struct mtk_eth *eth = mac->hw; 1242 1243 eth->netdev[mac->id]->stats.tx_errors++; 1244 netif_err(eth, tx_err, dev, 1245 "transmit timed out\n"); 1246 schedule_work(ð->pending_work); 1247 } 1248 1249 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 1250 { 1251 struct mtk_eth *eth = _eth; 1252 u32 status; 1253 1254 status = mtk_r32(eth, MTK_QMTK_INT_STATUS); 1255 if (unlikely(!status)) 1256 return IRQ_NONE; 1257 1258 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) { 1259 if (likely(napi_schedule_prep(ð->rx_napi))) 1260 __napi_schedule(ð->rx_napi); 1261 } else { 1262 mtk_w32(eth, status, MTK_QMTK_INT_STATUS); 1263 } 1264 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT)); 1265 1266 return IRQ_HANDLED; 1267 } 1268 1269 #ifdef CONFIG_NET_POLL_CONTROLLER 1270 static void mtk_poll_controller(struct net_device *dev) 1271 { 1272 struct mtk_mac *mac = netdev_priv(dev); 1273 struct mtk_eth *eth = mac->hw; 1274 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT; 1275 1276 mtk_irq_disable(eth, int_mask); 1277 mtk_handle_irq(dev->irq, dev); 1278 mtk_irq_enable(eth, int_mask); 1279 } 1280 #endif 1281 1282 static int mtk_start_dma(struct mtk_eth *eth) 1283 { 1284 int err; 1285 1286 err = mtk_dma_init(eth); 1287 if (err) { 1288 mtk_dma_free(eth); 1289 return err; 1290 } 1291 1292 mtk_w32(eth, 1293 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN | 1294 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS | 1295 MTK_RX_BT_32DWORDS | MTK_NDP_CO_PRO, 1296 MTK_QDMA_GLO_CFG); 1297 1298 return 0; 1299 } 1300 1301 static int mtk_open(struct net_device *dev) 1302 { 1303 struct mtk_mac *mac = netdev_priv(dev); 1304 struct mtk_eth *eth = mac->hw; 1305 1306 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 1307 if (!atomic_read(ð->dma_refcnt)) { 1308 int err = mtk_start_dma(eth); 1309 1310 if (err) 1311 return err; 1312 1313 napi_enable(ð->rx_napi); 1314 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1315 } 1316 atomic_inc(ð->dma_refcnt); 1317 1318 phy_start(mac->phy_dev); 1319 netif_start_queue(dev); 1320 1321 return 0; 1322 } 1323 1324 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 1325 { 1326 unsigned long flags; 1327 u32 val; 1328 int i; 1329 1330 /* stop the dma engine */ 1331 spin_lock_irqsave(ð->page_lock, flags); 1332 val = mtk_r32(eth, glo_cfg); 1333 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 1334 glo_cfg); 1335 spin_unlock_irqrestore(ð->page_lock, flags); 1336 1337 /* wait for dma stop */ 1338 for (i = 0; i < 10; i++) { 1339 val = mtk_r32(eth, glo_cfg); 1340 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 1341 msleep(20); 1342 continue; 1343 } 1344 break; 1345 } 1346 } 1347 1348 static int mtk_stop(struct net_device *dev) 1349 { 1350 struct mtk_mac *mac = netdev_priv(dev); 1351 struct mtk_eth *eth = mac->hw; 1352 1353 netif_tx_disable(dev); 1354 phy_stop(mac->phy_dev); 1355 1356 /* only shutdown DMA if this is the last user */ 1357 if (!atomic_dec_and_test(ð->dma_refcnt)) 1358 return 0; 1359 1360 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT); 1361 napi_disable(ð->rx_napi); 1362 1363 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG); 1364 1365 mtk_dma_free(eth); 1366 1367 return 0; 1368 } 1369 1370 static int __init mtk_hw_init(struct mtk_eth *eth) 1371 { 1372 int err, i; 1373 1374 /* reset the frame engine */ 1375 reset_control_assert(eth->rstc); 1376 usleep_range(10, 20); 1377 reset_control_deassert(eth->rstc); 1378 usleep_range(10, 20); 1379 1380 /* Set GE2 driving and slew rate */ 1381 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 1382 1383 /* set GE2 TDSEL */ 1384 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 1385 1386 /* set GE2 TUNE */ 1387 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 1388 1389 /* GE1, Force 1000M/FD, FC ON */ 1390 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0)); 1391 1392 /* GE2, Force 1000M/FD, FC ON */ 1393 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1)); 1394 1395 /* Enable RX VLan Offloading */ 1396 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 1397 1398 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0, 1399 dev_name(eth->dev), eth); 1400 if (err) 1401 return err; 1402 1403 err = mtk_mdio_init(eth); 1404 if (err) 1405 return err; 1406 1407 /* disable delay and normal interrupt */ 1408 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT); 1409 mtk_irq_disable(eth, ~0); 1410 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 1411 mtk_w32(eth, 0, MTK_RST_GL); 1412 1413 /* FE int grouping */ 1414 mtk_w32(eth, 0, MTK_FE_INT_GRP); 1415 1416 for (i = 0; i < 2; i++) { 1417 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 1418 1419 /* setup the forward port to send frame to QDMA */ 1420 val &= ~0xffff; 1421 val |= 0x5555; 1422 1423 /* Enable RX checksum */ 1424 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 1425 1426 /* setup the mac dma */ 1427 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 1428 } 1429 1430 return 0; 1431 } 1432 1433 static int __init mtk_init(struct net_device *dev) 1434 { 1435 struct mtk_mac *mac = netdev_priv(dev); 1436 struct mtk_eth *eth = mac->hw; 1437 const char *mac_addr; 1438 1439 mac_addr = of_get_mac_address(mac->of_node); 1440 if (mac_addr) 1441 ether_addr_copy(dev->dev_addr, mac_addr); 1442 1443 /* If the mac address is invalid, use random mac address */ 1444 if (!is_valid_ether_addr(dev->dev_addr)) { 1445 random_ether_addr(dev->dev_addr); 1446 dev_err(eth->dev, "generated random MAC address %pM\n", 1447 dev->dev_addr); 1448 dev->addr_assign_type = NET_ADDR_RANDOM; 1449 } 1450 1451 return mtk_phy_connect(mac); 1452 } 1453 1454 static void mtk_uninit(struct net_device *dev) 1455 { 1456 struct mtk_mac *mac = netdev_priv(dev); 1457 struct mtk_eth *eth = mac->hw; 1458 1459 phy_disconnect(mac->phy_dev); 1460 mtk_mdio_cleanup(eth); 1461 mtk_irq_disable(eth, ~0); 1462 free_irq(dev->irq, dev); 1463 } 1464 1465 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1466 { 1467 struct mtk_mac *mac = netdev_priv(dev); 1468 1469 switch (cmd) { 1470 case SIOCGMIIPHY: 1471 case SIOCGMIIREG: 1472 case SIOCSMIIREG: 1473 return phy_mii_ioctl(mac->phy_dev, ifr, cmd); 1474 default: 1475 break; 1476 } 1477 1478 return -EOPNOTSUPP; 1479 } 1480 1481 static void mtk_pending_work(struct work_struct *work) 1482 { 1483 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 1484 int err, i; 1485 unsigned long restart = 0; 1486 1487 rtnl_lock(); 1488 1489 /* stop all devices to make sure that dma is properly shut down */ 1490 for (i = 0; i < MTK_MAC_COUNT; i++) { 1491 if (!eth->netdev[i]) 1492 continue; 1493 mtk_stop(eth->netdev[i]); 1494 __set_bit(i, &restart); 1495 } 1496 1497 /* restart DMA and enable IRQs */ 1498 for (i = 0; i < MTK_MAC_COUNT; i++) { 1499 if (!test_bit(i, &restart)) 1500 continue; 1501 err = mtk_open(eth->netdev[i]); 1502 if (err) { 1503 netif_alert(eth, ifup, eth->netdev[i], 1504 "Driver up/down cycle failed, closing device.\n"); 1505 dev_close(eth->netdev[i]); 1506 } 1507 } 1508 rtnl_unlock(); 1509 } 1510 1511 static int mtk_cleanup(struct mtk_eth *eth) 1512 { 1513 int i; 1514 1515 for (i = 0; i < MTK_MAC_COUNT; i++) { 1516 if (!eth->netdev[i]) 1517 continue; 1518 1519 unregister_netdev(eth->netdev[i]); 1520 free_netdev(eth->netdev[i]); 1521 } 1522 cancel_work_sync(ð->pending_work); 1523 1524 return 0; 1525 } 1526 1527 static int mtk_get_settings(struct net_device *dev, 1528 struct ethtool_cmd *cmd) 1529 { 1530 struct mtk_mac *mac = netdev_priv(dev); 1531 int err; 1532 1533 err = phy_read_status(mac->phy_dev); 1534 if (err) 1535 return -ENODEV; 1536 1537 return phy_ethtool_gset(mac->phy_dev, cmd); 1538 } 1539 1540 static int mtk_set_settings(struct net_device *dev, 1541 struct ethtool_cmd *cmd) 1542 { 1543 struct mtk_mac *mac = netdev_priv(dev); 1544 1545 if (cmd->phy_address != mac->phy_dev->mdio.addr) { 1546 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus, 1547 cmd->phy_address); 1548 if (!mac->phy_dev) 1549 return -ENODEV; 1550 } 1551 1552 return phy_ethtool_sset(mac->phy_dev, cmd); 1553 } 1554 1555 static void mtk_get_drvinfo(struct net_device *dev, 1556 struct ethtool_drvinfo *info) 1557 { 1558 struct mtk_mac *mac = netdev_priv(dev); 1559 1560 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 1561 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 1562 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 1563 } 1564 1565 static u32 mtk_get_msglevel(struct net_device *dev) 1566 { 1567 struct mtk_mac *mac = netdev_priv(dev); 1568 1569 return mac->hw->msg_enable; 1570 } 1571 1572 static void mtk_set_msglevel(struct net_device *dev, u32 value) 1573 { 1574 struct mtk_mac *mac = netdev_priv(dev); 1575 1576 mac->hw->msg_enable = value; 1577 } 1578 1579 static int mtk_nway_reset(struct net_device *dev) 1580 { 1581 struct mtk_mac *mac = netdev_priv(dev); 1582 1583 return genphy_restart_aneg(mac->phy_dev); 1584 } 1585 1586 static u32 mtk_get_link(struct net_device *dev) 1587 { 1588 struct mtk_mac *mac = netdev_priv(dev); 1589 int err; 1590 1591 err = genphy_update_link(mac->phy_dev); 1592 if (err) 1593 return ethtool_op_get_link(dev); 1594 1595 return mac->phy_dev->link; 1596 } 1597 1598 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1599 { 1600 int i; 1601 1602 switch (stringset) { 1603 case ETH_SS_STATS: 1604 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 1605 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 1606 data += ETH_GSTRING_LEN; 1607 } 1608 break; 1609 } 1610 } 1611 1612 static int mtk_get_sset_count(struct net_device *dev, int sset) 1613 { 1614 switch (sset) { 1615 case ETH_SS_STATS: 1616 return ARRAY_SIZE(mtk_ethtool_stats); 1617 default: 1618 return -EOPNOTSUPP; 1619 } 1620 } 1621 1622 static void mtk_get_ethtool_stats(struct net_device *dev, 1623 struct ethtool_stats *stats, u64 *data) 1624 { 1625 struct mtk_mac *mac = netdev_priv(dev); 1626 struct mtk_hw_stats *hwstats = mac->hw_stats; 1627 u64 *data_src, *data_dst; 1628 unsigned int start; 1629 int i; 1630 1631 if (netif_running(dev) && netif_device_present(dev)) { 1632 if (spin_trylock(&hwstats->stats_lock)) { 1633 mtk_stats_update_mac(mac); 1634 spin_unlock(&hwstats->stats_lock); 1635 } 1636 } 1637 1638 do { 1639 data_src = (u64*)hwstats; 1640 data_dst = data; 1641 start = u64_stats_fetch_begin_irq(&hwstats->syncp); 1642 1643 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 1644 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 1645 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start)); 1646 } 1647 1648 static struct ethtool_ops mtk_ethtool_ops = { 1649 .get_settings = mtk_get_settings, 1650 .set_settings = mtk_set_settings, 1651 .get_drvinfo = mtk_get_drvinfo, 1652 .get_msglevel = mtk_get_msglevel, 1653 .set_msglevel = mtk_set_msglevel, 1654 .nway_reset = mtk_nway_reset, 1655 .get_link = mtk_get_link, 1656 .get_strings = mtk_get_strings, 1657 .get_sset_count = mtk_get_sset_count, 1658 .get_ethtool_stats = mtk_get_ethtool_stats, 1659 }; 1660 1661 static const struct net_device_ops mtk_netdev_ops = { 1662 .ndo_init = mtk_init, 1663 .ndo_uninit = mtk_uninit, 1664 .ndo_open = mtk_open, 1665 .ndo_stop = mtk_stop, 1666 .ndo_start_xmit = mtk_start_xmit, 1667 .ndo_set_mac_address = mtk_set_mac_address, 1668 .ndo_validate_addr = eth_validate_addr, 1669 .ndo_do_ioctl = mtk_do_ioctl, 1670 .ndo_change_mtu = eth_change_mtu, 1671 .ndo_tx_timeout = mtk_tx_timeout, 1672 .ndo_get_stats64 = mtk_get_stats64, 1673 #ifdef CONFIG_NET_POLL_CONTROLLER 1674 .ndo_poll_controller = mtk_poll_controller, 1675 #endif 1676 }; 1677 1678 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 1679 { 1680 struct mtk_mac *mac; 1681 const __be32 *_id = of_get_property(np, "reg", NULL); 1682 int id, err; 1683 1684 if (!_id) { 1685 dev_err(eth->dev, "missing mac id\n"); 1686 return -EINVAL; 1687 } 1688 1689 id = be32_to_cpup(_id); 1690 if (id >= MTK_MAC_COUNT) { 1691 dev_err(eth->dev, "%d is not a valid mac id\n", id); 1692 return -EINVAL; 1693 } 1694 1695 if (eth->netdev[id]) { 1696 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 1697 return -EINVAL; 1698 } 1699 1700 eth->netdev[id] = alloc_etherdev(sizeof(*mac)); 1701 if (!eth->netdev[id]) { 1702 dev_err(eth->dev, "alloc_etherdev failed\n"); 1703 return -ENOMEM; 1704 } 1705 mac = netdev_priv(eth->netdev[id]); 1706 eth->mac[id] = mac; 1707 mac->id = id; 1708 mac->hw = eth; 1709 mac->of_node = np; 1710 1711 mac->hw_stats = devm_kzalloc(eth->dev, 1712 sizeof(*mac->hw_stats), 1713 GFP_KERNEL); 1714 if (!mac->hw_stats) { 1715 dev_err(eth->dev, "failed to allocate counter memory\n"); 1716 err = -ENOMEM; 1717 goto free_netdev; 1718 } 1719 spin_lock_init(&mac->hw_stats->stats_lock); 1720 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 1721 1722 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 1723 eth->netdev[id]->watchdog_timeo = 5 * HZ; 1724 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 1725 eth->netdev[id]->base_addr = (unsigned long)eth->base; 1726 eth->netdev[id]->vlan_features = MTK_HW_FEATURES & 1727 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); 1728 eth->netdev[id]->features |= MTK_HW_FEATURES; 1729 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 1730 1731 err = register_netdev(eth->netdev[id]); 1732 if (err) { 1733 dev_err(eth->dev, "error bringing up device\n"); 1734 goto free_netdev; 1735 } 1736 eth->netdev[id]->irq = eth->irq; 1737 netif_info(eth, probe, eth->netdev[id], 1738 "mediatek frame engine at 0x%08lx, irq %d\n", 1739 eth->netdev[id]->base_addr, eth->netdev[id]->irq); 1740 1741 return 0; 1742 1743 free_netdev: 1744 free_netdev(eth->netdev[id]); 1745 return err; 1746 } 1747 1748 static int mtk_probe(struct platform_device *pdev) 1749 { 1750 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1751 struct device_node *mac_np; 1752 const struct of_device_id *match; 1753 struct mtk_soc_data *soc; 1754 struct mtk_eth *eth; 1755 int err; 1756 1757 match = of_match_device(of_mtk_match, &pdev->dev); 1758 soc = (struct mtk_soc_data *)match->data; 1759 1760 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 1761 if (!eth) 1762 return -ENOMEM; 1763 1764 eth->base = devm_ioremap_resource(&pdev->dev, res); 1765 if (IS_ERR(eth->base)) 1766 return PTR_ERR(eth->base); 1767 1768 spin_lock_init(ð->page_lock); 1769 1770 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1771 "mediatek,ethsys"); 1772 if (IS_ERR(eth->ethsys)) { 1773 dev_err(&pdev->dev, "no ethsys regmap found\n"); 1774 return PTR_ERR(eth->ethsys); 1775 } 1776 1777 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 1778 "mediatek,pctl"); 1779 if (IS_ERR(eth->pctl)) { 1780 dev_err(&pdev->dev, "no pctl regmap found\n"); 1781 return PTR_ERR(eth->pctl); 1782 } 1783 1784 eth->rstc = devm_reset_control_get(&pdev->dev, "eth"); 1785 if (IS_ERR(eth->rstc)) { 1786 dev_err(&pdev->dev, "no eth reset found\n"); 1787 return PTR_ERR(eth->rstc); 1788 } 1789 1790 eth->irq = platform_get_irq(pdev, 0); 1791 if (eth->irq < 0) { 1792 dev_err(&pdev->dev, "no IRQ resource found\n"); 1793 return -ENXIO; 1794 } 1795 1796 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif"); 1797 eth->clk_esw = devm_clk_get(&pdev->dev, "esw"); 1798 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1"); 1799 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2"); 1800 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) || 1801 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif)) 1802 return -ENODEV; 1803 1804 clk_prepare_enable(eth->clk_ethif); 1805 clk_prepare_enable(eth->clk_esw); 1806 clk_prepare_enable(eth->clk_gp1); 1807 clk_prepare_enable(eth->clk_gp2); 1808 1809 eth->dev = &pdev->dev; 1810 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 1811 INIT_WORK(ð->pending_work, mtk_pending_work); 1812 1813 err = mtk_hw_init(eth); 1814 if (err) 1815 return err; 1816 1817 for_each_child_of_node(pdev->dev.of_node, mac_np) { 1818 if (!of_device_is_compatible(mac_np, 1819 "mediatek,eth-mac")) 1820 continue; 1821 1822 if (!of_device_is_available(mac_np)) 1823 continue; 1824 1825 err = mtk_add_mac(eth, mac_np); 1826 if (err) 1827 goto err_free_dev; 1828 } 1829 1830 /* we run 2 devices on the same DMA ring so we need a dummy device 1831 * for NAPI to work 1832 */ 1833 init_dummy_netdev(ð->dummy_dev); 1834 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_poll, 1835 MTK_NAPI_WEIGHT); 1836 1837 platform_set_drvdata(pdev, eth); 1838 1839 return 0; 1840 1841 err_free_dev: 1842 mtk_cleanup(eth); 1843 return err; 1844 } 1845 1846 static int mtk_remove(struct platform_device *pdev) 1847 { 1848 struct mtk_eth *eth = platform_get_drvdata(pdev); 1849 1850 clk_disable_unprepare(eth->clk_ethif); 1851 clk_disable_unprepare(eth->clk_esw); 1852 clk_disable_unprepare(eth->clk_gp1); 1853 clk_disable_unprepare(eth->clk_gp2); 1854 1855 netif_napi_del(ð->rx_napi); 1856 mtk_cleanup(eth); 1857 platform_set_drvdata(pdev, NULL); 1858 1859 return 0; 1860 } 1861 1862 const struct of_device_id of_mtk_match[] = { 1863 { .compatible = "mediatek,mt7623-eth" }, 1864 {}, 1865 }; 1866 1867 static struct platform_driver mtk_driver = { 1868 .probe = mtk_probe, 1869 .remove = mtk_remove, 1870 .driver = { 1871 .name = "mtk_soc_eth", 1872 .owner = THIS_MODULE, 1873 .of_match_table = of_mtk_match, 1874 }, 1875 }; 1876 1877 module_platform_driver(mtk_driver); 1878 1879 MODULE_LICENSE("GPL"); 1880 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 1881 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 1882