1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> 5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> 6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> 7 */ 8 9 #include <linux/of_device.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/of_address.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/regmap.h> 15 #include <linux/clk.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/if_vlan.h> 18 #include <linux/reset.h> 19 #include <linux/tcp.h> 20 #include <linux/interrupt.h> 21 #include <linux/pinctrl/devinfo.h> 22 #include <linux/phylink.h> 23 #include <linux/pcs/pcs-mtk-lynxi.h> 24 #include <linux/jhash.h> 25 #include <linux/bitfield.h> 26 #include <net/dsa.h> 27 #include <net/dst_metadata.h> 28 29 #include "mtk_eth_soc.h" 30 #include "mtk_wed.h" 31 32 static int mtk_msg_level = -1; 33 module_param_named(msg_level, mtk_msg_level, int, 0); 34 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); 35 36 #define MTK_ETHTOOL_STAT(x) { #x, \ 37 offsetof(struct mtk_hw_stats, x) / sizeof(u64) } 38 39 #define MTK_ETHTOOL_XDP_STAT(x) { #x, \ 40 offsetof(struct mtk_hw_stats, xdp_stats.x) / \ 41 sizeof(u64) } 42 43 static const struct mtk_reg_map mtk_reg_map = { 44 .tx_irq_mask = 0x1a1c, 45 .tx_irq_status = 0x1a18, 46 .pdma = { 47 .rx_ptr = 0x0900, 48 .rx_cnt_cfg = 0x0904, 49 .pcrx_ptr = 0x0908, 50 .glo_cfg = 0x0a04, 51 .rst_idx = 0x0a08, 52 .delay_irq = 0x0a0c, 53 .irq_status = 0x0a20, 54 .irq_mask = 0x0a28, 55 .adma_rx_dbg0 = 0x0a38, 56 .int_grp = 0x0a50, 57 }, 58 .qdma = { 59 .qtx_cfg = 0x1800, 60 .qtx_sch = 0x1804, 61 .rx_ptr = 0x1900, 62 .rx_cnt_cfg = 0x1904, 63 .qcrx_ptr = 0x1908, 64 .glo_cfg = 0x1a04, 65 .rst_idx = 0x1a08, 66 .delay_irq = 0x1a0c, 67 .fc_th = 0x1a10, 68 .tx_sch_rate = 0x1a14, 69 .int_grp = 0x1a20, 70 .hred = 0x1a44, 71 .ctx_ptr = 0x1b00, 72 .dtx_ptr = 0x1b04, 73 .crx_ptr = 0x1b10, 74 .drx_ptr = 0x1b14, 75 .fq_head = 0x1b20, 76 .fq_tail = 0x1b24, 77 .fq_count = 0x1b28, 78 .fq_blen = 0x1b2c, 79 }, 80 .gdm1_cnt = 0x2400, 81 .gdma_to_ppe = 0x4444, 82 .ppe_base = 0x0c00, 83 .wdma_base = { 84 [0] = 0x2800, 85 [1] = 0x2c00, 86 }, 87 .pse_iq_sta = 0x0110, 88 .pse_oq_sta = 0x0118, 89 }; 90 91 static const struct mtk_reg_map mt7628_reg_map = { 92 .tx_irq_mask = 0x0a28, 93 .tx_irq_status = 0x0a20, 94 .pdma = { 95 .rx_ptr = 0x0900, 96 .rx_cnt_cfg = 0x0904, 97 .pcrx_ptr = 0x0908, 98 .glo_cfg = 0x0a04, 99 .rst_idx = 0x0a08, 100 .delay_irq = 0x0a0c, 101 .irq_status = 0x0a20, 102 .irq_mask = 0x0a28, 103 .int_grp = 0x0a50, 104 }, 105 }; 106 107 static const struct mtk_reg_map mt7986_reg_map = { 108 .tx_irq_mask = 0x461c, 109 .tx_irq_status = 0x4618, 110 .pdma = { 111 .rx_ptr = 0x6100, 112 .rx_cnt_cfg = 0x6104, 113 .pcrx_ptr = 0x6108, 114 .glo_cfg = 0x6204, 115 .rst_idx = 0x6208, 116 .delay_irq = 0x620c, 117 .irq_status = 0x6220, 118 .irq_mask = 0x6228, 119 .adma_rx_dbg0 = 0x6238, 120 .int_grp = 0x6250, 121 }, 122 .qdma = { 123 .qtx_cfg = 0x4400, 124 .qtx_sch = 0x4404, 125 .rx_ptr = 0x4500, 126 .rx_cnt_cfg = 0x4504, 127 .qcrx_ptr = 0x4508, 128 .glo_cfg = 0x4604, 129 .rst_idx = 0x4608, 130 .delay_irq = 0x460c, 131 .fc_th = 0x4610, 132 .int_grp = 0x4620, 133 .hred = 0x4644, 134 .ctx_ptr = 0x4700, 135 .dtx_ptr = 0x4704, 136 .crx_ptr = 0x4710, 137 .drx_ptr = 0x4714, 138 .fq_head = 0x4720, 139 .fq_tail = 0x4724, 140 .fq_count = 0x4728, 141 .fq_blen = 0x472c, 142 .tx_sch_rate = 0x4798, 143 }, 144 .gdm1_cnt = 0x1c00, 145 .gdma_to_ppe = 0x3333, 146 .ppe_base = 0x2000, 147 .wdma_base = { 148 [0] = 0x4800, 149 [1] = 0x4c00, 150 }, 151 .pse_iq_sta = 0x0180, 152 .pse_oq_sta = 0x01a0, 153 }; 154 155 /* strings used by ethtool */ 156 static const struct mtk_ethtool_stats { 157 char str[ETH_GSTRING_LEN]; 158 u32 offset; 159 } mtk_ethtool_stats[] = { 160 MTK_ETHTOOL_STAT(tx_bytes), 161 MTK_ETHTOOL_STAT(tx_packets), 162 MTK_ETHTOOL_STAT(tx_skip), 163 MTK_ETHTOOL_STAT(tx_collisions), 164 MTK_ETHTOOL_STAT(rx_bytes), 165 MTK_ETHTOOL_STAT(rx_packets), 166 MTK_ETHTOOL_STAT(rx_overflow), 167 MTK_ETHTOOL_STAT(rx_fcs_errors), 168 MTK_ETHTOOL_STAT(rx_short_errors), 169 MTK_ETHTOOL_STAT(rx_long_errors), 170 MTK_ETHTOOL_STAT(rx_checksum_errors), 171 MTK_ETHTOOL_STAT(rx_flow_control_packets), 172 MTK_ETHTOOL_XDP_STAT(rx_xdp_redirect), 173 MTK_ETHTOOL_XDP_STAT(rx_xdp_pass), 174 MTK_ETHTOOL_XDP_STAT(rx_xdp_drop), 175 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx), 176 MTK_ETHTOOL_XDP_STAT(rx_xdp_tx_errors), 177 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit), 178 MTK_ETHTOOL_XDP_STAT(tx_xdp_xmit_errors), 179 }; 180 181 static const char * const mtk_clks_source_name[] = { 182 "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 183 "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 184 "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 185 "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 186 }; 187 188 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) 189 { 190 __raw_writel(val, eth->base + reg); 191 } 192 193 u32 mtk_r32(struct mtk_eth *eth, unsigned reg) 194 { 195 return __raw_readl(eth->base + reg); 196 } 197 198 static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 199 { 200 u32 val; 201 202 val = mtk_r32(eth, reg); 203 val &= ~mask; 204 val |= set; 205 mtk_w32(eth, val, reg); 206 return reg; 207 } 208 209 static int mtk_mdio_busy_wait(struct mtk_eth *eth) 210 { 211 unsigned long t_start = jiffies; 212 213 while (1) { 214 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS)) 215 return 0; 216 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT)) 217 break; 218 cond_resched(); 219 } 220 221 dev_err(eth->dev, "mdio: MDIO timeout\n"); 222 return -ETIMEDOUT; 223 } 224 225 static int _mtk_mdio_write_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg, 226 u32 write_data) 227 { 228 int ret; 229 230 ret = mtk_mdio_busy_wait(eth); 231 if (ret < 0) 232 return ret; 233 234 mtk_w32(eth, PHY_IAC_ACCESS | 235 PHY_IAC_START_C22 | 236 PHY_IAC_CMD_WRITE | 237 PHY_IAC_REG(phy_reg) | 238 PHY_IAC_ADDR(phy_addr) | 239 PHY_IAC_DATA(write_data), 240 MTK_PHY_IAC); 241 242 ret = mtk_mdio_busy_wait(eth); 243 if (ret < 0) 244 return ret; 245 246 return 0; 247 } 248 249 static int _mtk_mdio_write_c45(struct mtk_eth *eth, u32 phy_addr, 250 u32 devad, u32 phy_reg, u32 write_data) 251 { 252 int ret; 253 254 ret = mtk_mdio_busy_wait(eth); 255 if (ret < 0) 256 return ret; 257 258 mtk_w32(eth, PHY_IAC_ACCESS | 259 PHY_IAC_START_C45 | 260 PHY_IAC_CMD_C45_ADDR | 261 PHY_IAC_REG(devad) | 262 PHY_IAC_ADDR(phy_addr) | 263 PHY_IAC_DATA(phy_reg), 264 MTK_PHY_IAC); 265 266 ret = mtk_mdio_busy_wait(eth); 267 if (ret < 0) 268 return ret; 269 270 mtk_w32(eth, PHY_IAC_ACCESS | 271 PHY_IAC_START_C45 | 272 PHY_IAC_CMD_WRITE | 273 PHY_IAC_REG(devad) | 274 PHY_IAC_ADDR(phy_addr) | 275 PHY_IAC_DATA(write_data), 276 MTK_PHY_IAC); 277 278 ret = mtk_mdio_busy_wait(eth); 279 if (ret < 0) 280 return ret; 281 282 return 0; 283 } 284 285 static int _mtk_mdio_read_c22(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg) 286 { 287 int ret; 288 289 ret = mtk_mdio_busy_wait(eth); 290 if (ret < 0) 291 return ret; 292 293 mtk_w32(eth, PHY_IAC_ACCESS | 294 PHY_IAC_START_C22 | 295 PHY_IAC_CMD_C22_READ | 296 PHY_IAC_REG(phy_reg) | 297 PHY_IAC_ADDR(phy_addr), 298 MTK_PHY_IAC); 299 300 ret = mtk_mdio_busy_wait(eth); 301 if (ret < 0) 302 return ret; 303 304 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 305 } 306 307 static int _mtk_mdio_read_c45(struct mtk_eth *eth, u32 phy_addr, 308 u32 devad, u32 phy_reg) 309 { 310 int ret; 311 312 ret = mtk_mdio_busy_wait(eth); 313 if (ret < 0) 314 return ret; 315 316 mtk_w32(eth, PHY_IAC_ACCESS | 317 PHY_IAC_START_C45 | 318 PHY_IAC_CMD_C45_ADDR | 319 PHY_IAC_REG(devad) | 320 PHY_IAC_ADDR(phy_addr) | 321 PHY_IAC_DATA(phy_reg), 322 MTK_PHY_IAC); 323 324 ret = mtk_mdio_busy_wait(eth); 325 if (ret < 0) 326 return ret; 327 328 mtk_w32(eth, PHY_IAC_ACCESS | 329 PHY_IAC_START_C45 | 330 PHY_IAC_CMD_C45_READ | 331 PHY_IAC_REG(devad) | 332 PHY_IAC_ADDR(phy_addr), 333 MTK_PHY_IAC); 334 335 ret = mtk_mdio_busy_wait(eth); 336 if (ret < 0) 337 return ret; 338 339 return mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_DATA_MASK; 340 } 341 342 static int mtk_mdio_write_c22(struct mii_bus *bus, int phy_addr, 343 int phy_reg, u16 val) 344 { 345 struct mtk_eth *eth = bus->priv; 346 347 return _mtk_mdio_write_c22(eth, phy_addr, phy_reg, val); 348 } 349 350 static int mtk_mdio_write_c45(struct mii_bus *bus, int phy_addr, 351 int devad, int phy_reg, u16 val) 352 { 353 struct mtk_eth *eth = bus->priv; 354 355 return _mtk_mdio_write_c45(eth, phy_addr, devad, phy_reg, val); 356 } 357 358 static int mtk_mdio_read_c22(struct mii_bus *bus, int phy_addr, int phy_reg) 359 { 360 struct mtk_eth *eth = bus->priv; 361 362 return _mtk_mdio_read_c22(eth, phy_addr, phy_reg); 363 } 364 365 static int mtk_mdio_read_c45(struct mii_bus *bus, int phy_addr, int devad, 366 int phy_reg) 367 { 368 struct mtk_eth *eth = bus->priv; 369 370 return _mtk_mdio_read_c45(eth, phy_addr, devad, phy_reg); 371 } 372 373 static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth, 374 phy_interface_t interface) 375 { 376 u32 val; 377 378 val = (interface == PHY_INTERFACE_MODE_TRGMII) ? 379 ETHSYS_TRGMII_MT7621_DDR_PLL : 0; 380 381 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 382 ETHSYS_TRGMII_MT7621_MASK, val); 383 384 return 0; 385 } 386 387 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, 388 phy_interface_t interface, int speed) 389 { 390 unsigned long rate; 391 u32 tck, rck, intf; 392 int ret; 393 394 if (interface == PHY_INTERFACE_MODE_TRGMII) { 395 mtk_w32(eth, TRGMII_MODE, INTF_MODE); 396 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], 500000000); 397 if (ret) 398 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 399 return; 400 } 401 402 if (speed == SPEED_1000) { 403 intf = INTF_MODE_RGMII_1000; 404 rate = 250000000; 405 rck = RCK_CTRL_RGMII_1000; 406 tck = TCK_CTRL_RGMII_1000; 407 } else { 408 intf = INTF_MODE_RGMII_10_100; 409 rate = 500000000; 410 rck = RCK_CTRL_RGMII_10_100; 411 tck = TCK_CTRL_RGMII_10_100; 412 } 413 414 mtk_w32(eth, intf, INTF_MODE); 415 416 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0, 417 ETHSYS_TRGMII_CLK_SEL362_5, 418 ETHSYS_TRGMII_CLK_SEL362_5); 419 420 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], rate); 421 if (ret) 422 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret); 423 424 mtk_w32(eth, rck, TRGMII_RCK_CTRL); 425 mtk_w32(eth, tck, TRGMII_TCK_CTRL); 426 } 427 428 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 429 phy_interface_t interface) 430 { 431 struct mtk_mac *mac = container_of(config, struct mtk_mac, 432 phylink_config); 433 struct mtk_eth *eth = mac->hw; 434 unsigned int sid; 435 436 if (interface == PHY_INTERFACE_MODE_SGMII || 437 phy_interface_mode_is_8023z(interface)) { 438 sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 439 0 : mac->id; 440 441 return eth->sgmii_pcs[sid]; 442 } 443 444 return NULL; 445 } 446 447 static void mtk_mac_config(struct phylink_config *config, unsigned int mode, 448 const struct phylink_link_state *state) 449 { 450 struct mtk_mac *mac = container_of(config, struct mtk_mac, 451 phylink_config); 452 struct mtk_eth *eth = mac->hw; 453 int val, ge_mode, err = 0; 454 u32 i; 455 456 /* MT76x8 has no hardware settings between for the MAC */ 457 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 458 mac->interface != state->interface) { 459 /* Setup soc pin functions */ 460 switch (state->interface) { 461 case PHY_INTERFACE_MODE_TRGMII: 462 case PHY_INTERFACE_MODE_RGMII_TXID: 463 case PHY_INTERFACE_MODE_RGMII_RXID: 464 case PHY_INTERFACE_MODE_RGMII_ID: 465 case PHY_INTERFACE_MODE_RGMII: 466 case PHY_INTERFACE_MODE_MII: 467 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { 468 err = mtk_gmac_rgmii_path_setup(eth, mac->id); 469 if (err) 470 goto init_err; 471 } 472 break; 473 case PHY_INTERFACE_MODE_1000BASEX: 474 case PHY_INTERFACE_MODE_2500BASEX: 475 case PHY_INTERFACE_MODE_SGMII: 476 err = mtk_gmac_sgmii_path_setup(eth, mac->id); 477 if (err) 478 goto init_err; 479 break; 480 case PHY_INTERFACE_MODE_GMII: 481 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { 482 err = mtk_gmac_gephy_path_setup(eth, mac->id); 483 if (err) 484 goto init_err; 485 } 486 break; 487 default: 488 goto err_phy; 489 } 490 491 /* Setup clock for 1st gmac */ 492 if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && 493 !phy_interface_mode_is_8023z(state->interface) && 494 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { 495 if (MTK_HAS_CAPS(mac->hw->soc->caps, 496 MTK_TRGMII_MT7621_CLK)) { 497 if (mt7621_gmac0_rgmii_adjust(mac->hw, 498 state->interface)) 499 goto err_phy; 500 } else { 501 /* FIXME: this is incorrect. Not only does it 502 * use state->speed (which is not guaranteed 503 * to be correct) but it also makes use of it 504 * in a code path that will only be reachable 505 * when the PHY interface mode changes, not 506 * when the speed changes. Consequently, RGMII 507 * is probably broken. 508 */ 509 mtk_gmac0_rgmii_adjust(mac->hw, 510 state->interface, 511 state->speed); 512 513 /* mt7623_pad_clk_setup */ 514 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 515 mtk_w32(mac->hw, 516 TD_DM_DRVP(8) | TD_DM_DRVN(8), 517 TRGMII_TD_ODT(i)); 518 519 /* Assert/release MT7623 RXC reset */ 520 mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL, 521 TRGMII_RCK_CTRL); 522 mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL); 523 } 524 } 525 526 switch (state->interface) { 527 case PHY_INTERFACE_MODE_MII: 528 case PHY_INTERFACE_MODE_GMII: 529 ge_mode = 1; 530 break; 531 default: 532 ge_mode = 0; 533 break; 534 } 535 536 /* put the gmac into the right mode */ 537 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 538 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); 539 val |= SYSCFG0_GE_MODE(ge_mode, mac->id); 540 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val); 541 542 mac->interface = state->interface; 543 } 544 545 /* SGMII */ 546 if (state->interface == PHY_INTERFACE_MODE_SGMII || 547 phy_interface_mode_is_8023z(state->interface)) { 548 /* The path GMAC to SGMII will be enabled once the SGMIISYS is 549 * being setup done. 550 */ 551 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); 552 553 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 554 SYSCFG0_SGMII_MASK, 555 ~(u32)SYSCFG0_SGMII_MASK); 556 557 /* Save the syscfg0 value for mac_finish */ 558 mac->syscfg0 = val; 559 } else if (phylink_autoneg_inband(mode)) { 560 dev_err(eth->dev, 561 "In-band mode not supported in non SGMII mode!\n"); 562 return; 563 } 564 565 return; 566 567 err_phy: 568 dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, 569 mac->id, phy_modes(state->interface)); 570 return; 571 572 init_err: 573 dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, 574 mac->id, phy_modes(state->interface), err); 575 } 576 577 static int mtk_mac_finish(struct phylink_config *config, unsigned int mode, 578 phy_interface_t interface) 579 { 580 struct mtk_mac *mac = container_of(config, struct mtk_mac, 581 phylink_config); 582 struct mtk_eth *eth = mac->hw; 583 u32 mcr_cur, mcr_new; 584 585 /* Enable SGMII */ 586 if (interface == PHY_INTERFACE_MODE_SGMII || 587 phy_interface_mode_is_8023z(interface)) 588 regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, 589 SYSCFG0_SGMII_MASK, mac->syscfg0); 590 591 /* Setup gmac */ 592 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 593 mcr_new = mcr_cur; 594 mcr_new |= MAC_MCR_IPG_CFG | MAC_MCR_FORCE_MODE | 595 MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK | 596 MAC_MCR_RX_FIFO_CLR_DIS; 597 598 /* Only update control register when needed! */ 599 if (mcr_new != mcr_cur) 600 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 601 602 return 0; 603 } 604 605 static void mtk_mac_pcs_get_state(struct phylink_config *config, 606 struct phylink_link_state *state) 607 { 608 struct mtk_mac *mac = container_of(config, struct mtk_mac, 609 phylink_config); 610 u32 pmsr = mtk_r32(mac->hw, MTK_MAC_MSR(mac->id)); 611 612 state->link = (pmsr & MAC_MSR_LINK); 613 state->duplex = (pmsr & MAC_MSR_DPX) >> 1; 614 615 switch (pmsr & (MAC_MSR_SPEED_1000 | MAC_MSR_SPEED_100)) { 616 case 0: 617 state->speed = SPEED_10; 618 break; 619 case MAC_MSR_SPEED_100: 620 state->speed = SPEED_100; 621 break; 622 case MAC_MSR_SPEED_1000: 623 state->speed = SPEED_1000; 624 break; 625 default: 626 state->speed = SPEED_UNKNOWN; 627 break; 628 } 629 630 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); 631 if (pmsr & MAC_MSR_RX_FC) 632 state->pause |= MLO_PAUSE_RX; 633 if (pmsr & MAC_MSR_TX_FC) 634 state->pause |= MLO_PAUSE_TX; 635 } 636 637 static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, 638 phy_interface_t interface) 639 { 640 struct mtk_mac *mac = container_of(config, struct mtk_mac, 641 phylink_config); 642 u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 643 644 mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN); 645 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 646 } 647 648 static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx, 649 int speed) 650 { 651 const struct mtk_soc_data *soc = eth->soc; 652 u32 ofs, val; 653 654 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 655 return; 656 657 val = MTK_QTX_SCH_MIN_RATE_EN | 658 /* minimum: 10 Mbps */ 659 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 660 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 661 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 662 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 663 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 664 665 if (IS_ENABLED(CONFIG_SOC_MT7621)) { 666 switch (speed) { 667 case SPEED_10: 668 val |= MTK_QTX_SCH_MAX_RATE_EN | 669 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 670 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 2) | 671 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 672 break; 673 case SPEED_100: 674 val |= MTK_QTX_SCH_MAX_RATE_EN | 675 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 103) | 676 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 3); 677 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 678 break; 679 case SPEED_1000: 680 val |= MTK_QTX_SCH_MAX_RATE_EN | 681 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 105) | 682 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 683 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 684 break; 685 default: 686 break; 687 } 688 } else { 689 switch (speed) { 690 case SPEED_10: 691 val |= MTK_QTX_SCH_MAX_RATE_EN | 692 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 693 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 4) | 694 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 695 break; 696 case SPEED_100: 697 val |= MTK_QTX_SCH_MAX_RATE_EN | 698 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 1) | 699 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5); 700 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 1); 701 break; 702 case SPEED_1000: 703 val |= MTK_QTX_SCH_MAX_RATE_EN | 704 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 10) | 705 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | 706 FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WEIGHT, 10); 707 break; 708 default: 709 break; 710 } 711 } 712 713 ofs = MTK_QTX_OFFSET * idx; 714 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 715 } 716 717 static void mtk_mac_link_up(struct phylink_config *config, 718 struct phy_device *phy, 719 unsigned int mode, phy_interface_t interface, 720 int speed, int duplex, bool tx_pause, bool rx_pause) 721 { 722 struct mtk_mac *mac = container_of(config, struct mtk_mac, 723 phylink_config); 724 u32 mcr; 725 726 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 727 mcr &= ~(MAC_MCR_SPEED_100 | MAC_MCR_SPEED_1000 | 728 MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_TX_FC | 729 MAC_MCR_FORCE_RX_FC); 730 731 /* Configure speed */ 732 mac->speed = speed; 733 switch (speed) { 734 case SPEED_2500: 735 case SPEED_1000: 736 mcr |= MAC_MCR_SPEED_1000; 737 break; 738 case SPEED_100: 739 mcr |= MAC_MCR_SPEED_100; 740 break; 741 } 742 743 /* Configure duplex */ 744 if (duplex == DUPLEX_FULL) 745 mcr |= MAC_MCR_FORCE_DPX; 746 747 /* Configure pause modes - phylink will avoid these for half duplex */ 748 if (tx_pause) 749 mcr |= MAC_MCR_FORCE_TX_FC; 750 if (rx_pause) 751 mcr |= MAC_MCR_FORCE_RX_FC; 752 753 mcr |= MAC_MCR_TX_EN | MAC_MCR_RX_EN; 754 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id)); 755 } 756 757 static const struct phylink_mac_ops mtk_phylink_ops = { 758 .mac_select_pcs = mtk_mac_select_pcs, 759 .mac_pcs_get_state = mtk_mac_pcs_get_state, 760 .mac_config = mtk_mac_config, 761 .mac_finish = mtk_mac_finish, 762 .mac_link_down = mtk_mac_link_down, 763 .mac_link_up = mtk_mac_link_up, 764 }; 765 766 static int mtk_mdio_init(struct mtk_eth *eth) 767 { 768 unsigned int max_clk = 2500000, divider; 769 struct device_node *mii_np; 770 int ret; 771 u32 val; 772 773 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus"); 774 if (!mii_np) { 775 dev_err(eth->dev, "no %s child node found", "mdio-bus"); 776 return -ENODEV; 777 } 778 779 if (!of_device_is_available(mii_np)) { 780 ret = -ENODEV; 781 goto err_put_node; 782 } 783 784 eth->mii_bus = devm_mdiobus_alloc(eth->dev); 785 if (!eth->mii_bus) { 786 ret = -ENOMEM; 787 goto err_put_node; 788 } 789 790 eth->mii_bus->name = "mdio"; 791 eth->mii_bus->read = mtk_mdio_read_c22; 792 eth->mii_bus->write = mtk_mdio_write_c22; 793 eth->mii_bus->read_c45 = mtk_mdio_read_c45; 794 eth->mii_bus->write_c45 = mtk_mdio_write_c45; 795 eth->mii_bus->priv = eth; 796 eth->mii_bus->parent = eth->dev; 797 798 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np); 799 800 if (!of_property_read_u32(mii_np, "clock-frequency", &val)) { 801 if (val > MDC_MAX_FREQ || val < MDC_MAX_FREQ / MDC_MAX_DIVIDER) { 802 dev_err(eth->dev, "MDIO clock frequency out of range"); 803 ret = -EINVAL; 804 goto err_put_node; 805 } 806 max_clk = val; 807 } 808 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 809 810 /* Configure MDC Divider */ 811 val = mtk_r32(eth, MTK_PPSC); 812 val &= ~PPSC_MDC_CFG; 813 val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; 814 mtk_w32(eth, val, MTK_PPSC); 815 816 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 817 818 ret = of_mdiobus_register(eth->mii_bus, mii_np); 819 820 err_put_node: 821 of_node_put(mii_np); 822 return ret; 823 } 824 825 static void mtk_mdio_cleanup(struct mtk_eth *eth) 826 { 827 if (!eth->mii_bus) 828 return; 829 830 mdiobus_unregister(eth->mii_bus); 831 } 832 833 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask) 834 { 835 unsigned long flags; 836 u32 val; 837 838 spin_lock_irqsave(ð->tx_irq_lock, flags); 839 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 840 mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask); 841 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 842 } 843 844 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask) 845 { 846 unsigned long flags; 847 u32 val; 848 849 spin_lock_irqsave(ð->tx_irq_lock, flags); 850 val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask); 851 mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask); 852 spin_unlock_irqrestore(ð->tx_irq_lock, flags); 853 } 854 855 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask) 856 { 857 unsigned long flags; 858 u32 val; 859 860 spin_lock_irqsave(ð->rx_irq_lock, flags); 861 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 862 mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask); 863 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 864 } 865 866 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask) 867 { 868 unsigned long flags; 869 u32 val; 870 871 spin_lock_irqsave(ð->rx_irq_lock, flags); 872 val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask); 873 mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask); 874 spin_unlock_irqrestore(ð->rx_irq_lock, flags); 875 } 876 877 static int mtk_set_mac_address(struct net_device *dev, void *p) 878 { 879 int ret = eth_mac_addr(dev, p); 880 struct mtk_mac *mac = netdev_priv(dev); 881 struct mtk_eth *eth = mac->hw; 882 const char *macaddr = dev->dev_addr; 883 884 if (ret) 885 return ret; 886 887 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 888 return -EBUSY; 889 890 spin_lock_bh(&mac->hw->page_lock); 891 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 892 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 893 MT7628_SDM_MAC_ADRH); 894 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 895 (macaddr[4] << 8) | macaddr[5], 896 MT7628_SDM_MAC_ADRL); 897 } else { 898 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1], 899 MTK_GDMA_MAC_ADRH(mac->id)); 900 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) | 901 (macaddr[4] << 8) | macaddr[5], 902 MTK_GDMA_MAC_ADRL(mac->id)); 903 } 904 spin_unlock_bh(&mac->hw->page_lock); 905 906 return 0; 907 } 908 909 void mtk_stats_update_mac(struct mtk_mac *mac) 910 { 911 struct mtk_hw_stats *hw_stats = mac->hw_stats; 912 struct mtk_eth *eth = mac->hw; 913 914 u64_stats_update_begin(&hw_stats->syncp); 915 916 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 917 hw_stats->tx_packets += mtk_r32(mac->hw, MT7628_SDM_TPCNT); 918 hw_stats->tx_bytes += mtk_r32(mac->hw, MT7628_SDM_TBCNT); 919 hw_stats->rx_packets += mtk_r32(mac->hw, MT7628_SDM_RPCNT); 920 hw_stats->rx_bytes += mtk_r32(mac->hw, MT7628_SDM_RBCNT); 921 hw_stats->rx_checksum_errors += 922 mtk_r32(mac->hw, MT7628_SDM_CS_ERR); 923 } else { 924 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 925 unsigned int offs = hw_stats->reg_offset; 926 u64 stats; 927 928 hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs); 929 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs); 930 if (stats) 931 hw_stats->rx_bytes += (stats << 32); 932 hw_stats->rx_packets += 933 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs); 934 hw_stats->rx_overflow += 935 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs); 936 hw_stats->rx_fcs_errors += 937 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs); 938 hw_stats->rx_short_errors += 939 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs); 940 hw_stats->rx_long_errors += 941 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs); 942 hw_stats->rx_checksum_errors += 943 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 944 hw_stats->rx_flow_control_packets += 945 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 946 hw_stats->tx_skip += 947 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 948 hw_stats->tx_collisions += 949 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 950 hw_stats->tx_bytes += 951 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 952 stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 953 if (stats) 954 hw_stats->tx_bytes += (stats << 32); 955 hw_stats->tx_packets += 956 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 957 } 958 959 u64_stats_update_end(&hw_stats->syncp); 960 } 961 962 static void mtk_stats_update(struct mtk_eth *eth) 963 { 964 int i; 965 966 for (i = 0; i < MTK_MAC_COUNT; i++) { 967 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 968 continue; 969 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { 970 mtk_stats_update_mac(eth->mac[i]); 971 spin_unlock(ð->mac[i]->hw_stats->stats_lock); 972 } 973 } 974 } 975 976 static void mtk_get_stats64(struct net_device *dev, 977 struct rtnl_link_stats64 *storage) 978 { 979 struct mtk_mac *mac = netdev_priv(dev); 980 struct mtk_hw_stats *hw_stats = mac->hw_stats; 981 unsigned int start; 982 983 if (netif_running(dev) && netif_device_present(dev)) { 984 if (spin_trylock_bh(&hw_stats->stats_lock)) { 985 mtk_stats_update_mac(mac); 986 spin_unlock_bh(&hw_stats->stats_lock); 987 } 988 } 989 990 do { 991 start = u64_stats_fetch_begin(&hw_stats->syncp); 992 storage->rx_packets = hw_stats->rx_packets; 993 storage->tx_packets = hw_stats->tx_packets; 994 storage->rx_bytes = hw_stats->rx_bytes; 995 storage->tx_bytes = hw_stats->tx_bytes; 996 storage->collisions = hw_stats->tx_collisions; 997 storage->rx_length_errors = hw_stats->rx_short_errors + 998 hw_stats->rx_long_errors; 999 storage->rx_over_errors = hw_stats->rx_overflow; 1000 storage->rx_crc_errors = hw_stats->rx_fcs_errors; 1001 storage->rx_errors = hw_stats->rx_checksum_errors; 1002 storage->tx_aborted_errors = hw_stats->tx_skip; 1003 } while (u64_stats_fetch_retry(&hw_stats->syncp, start)); 1004 1005 storage->tx_errors = dev->stats.tx_errors; 1006 storage->rx_dropped = dev->stats.rx_dropped; 1007 storage->tx_dropped = dev->stats.tx_dropped; 1008 } 1009 1010 static inline int mtk_max_frag_size(int mtu) 1011 { 1012 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */ 1013 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH_2K) 1014 mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 1015 1016 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) + 1017 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1018 } 1019 1020 static inline int mtk_max_buf_size(int frag_size) 1021 { 1022 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN - 1023 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); 1024 1025 WARN_ON(buf_size < MTK_MAX_RX_LENGTH_2K); 1026 1027 return buf_size; 1028 } 1029 1030 static bool mtk_rx_get_desc(struct mtk_eth *eth, struct mtk_rx_dma_v2 *rxd, 1031 struct mtk_rx_dma_v2 *dma_rxd) 1032 { 1033 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2); 1034 if (!(rxd->rxd2 & RX_DMA_DONE)) 1035 return false; 1036 1037 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1038 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1039 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1040 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1041 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1042 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1043 } 1044 1045 return true; 1046 } 1047 1048 static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask) 1049 { 1050 unsigned int size = mtk_max_frag_size(MTK_MAX_LRO_RX_LENGTH); 1051 unsigned long data; 1052 1053 data = __get_free_pages(gfp_mask | __GFP_COMP | __GFP_NOWARN, 1054 get_order(size)); 1055 1056 return (void *)data; 1057 } 1058 1059 /* the qdma core needs scratch memory to be setup */ 1060 static int mtk_init_fq_dma(struct mtk_eth *eth) 1061 { 1062 const struct mtk_soc_data *soc = eth->soc; 1063 dma_addr_t phy_ring_tail; 1064 int cnt = MTK_QDMA_RING_SIZE; 1065 dma_addr_t dma_addr; 1066 int i; 1067 1068 eth->scratch_ring = dma_alloc_coherent(eth->dma_dev, 1069 cnt * soc->txrx.txd_size, 1070 ð->phy_scratch_ring, 1071 GFP_KERNEL); 1072 if (unlikely(!eth->scratch_ring)) 1073 return -ENOMEM; 1074 1075 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE, GFP_KERNEL); 1076 if (unlikely(!eth->scratch_head)) 1077 return -ENOMEM; 1078 1079 dma_addr = dma_map_single(eth->dma_dev, 1080 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE, 1081 DMA_FROM_DEVICE); 1082 if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr))) 1083 return -ENOMEM; 1084 1085 phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1); 1086 1087 for (i = 0; i < cnt; i++) { 1088 struct mtk_tx_dma_v2 *txd; 1089 1090 txd = eth->scratch_ring + i * soc->txrx.txd_size; 1091 txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE; 1092 if (i < cnt - 1) 1093 txd->txd2 = eth->phy_scratch_ring + 1094 (i + 1) * soc->txrx.txd_size; 1095 1096 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1097 txd->txd4 = 0; 1098 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1099 txd->txd5 = 0; 1100 txd->txd6 = 0; 1101 txd->txd7 = 0; 1102 txd->txd8 = 0; 1103 } 1104 } 1105 1106 mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head); 1107 mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail); 1108 mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count); 1109 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen); 1110 1111 return 0; 1112 } 1113 1114 static void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc) 1115 { 1116 return ring->dma + (desc - ring->phys); 1117 } 1118 1119 static struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring, 1120 void *txd, u32 txd_size) 1121 { 1122 int idx = (txd - ring->dma) / txd_size; 1123 1124 return &ring->buf[idx]; 1125 } 1126 1127 static struct mtk_tx_dma *qdma_to_pdma(struct mtk_tx_ring *ring, 1128 struct mtk_tx_dma *dma) 1129 { 1130 return ring->dma_pdma - (struct mtk_tx_dma *)ring->dma + dma; 1131 } 1132 1133 static int txd_to_idx(struct mtk_tx_ring *ring, void *dma, u32 txd_size) 1134 { 1135 return (dma - ring->dma) / txd_size; 1136 } 1137 1138 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1139 struct xdp_frame_bulk *bq, bool napi) 1140 { 1141 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1142 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) { 1143 dma_unmap_single(eth->dma_dev, 1144 dma_unmap_addr(tx_buf, dma_addr0), 1145 dma_unmap_len(tx_buf, dma_len0), 1146 DMA_TO_DEVICE); 1147 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) { 1148 dma_unmap_page(eth->dma_dev, 1149 dma_unmap_addr(tx_buf, dma_addr0), 1150 dma_unmap_len(tx_buf, dma_len0), 1151 DMA_TO_DEVICE); 1152 } 1153 } else { 1154 if (dma_unmap_len(tx_buf, dma_len0)) { 1155 dma_unmap_page(eth->dma_dev, 1156 dma_unmap_addr(tx_buf, dma_addr0), 1157 dma_unmap_len(tx_buf, dma_len0), 1158 DMA_TO_DEVICE); 1159 } 1160 1161 if (dma_unmap_len(tx_buf, dma_len1)) { 1162 dma_unmap_page(eth->dma_dev, 1163 dma_unmap_addr(tx_buf, dma_addr1), 1164 dma_unmap_len(tx_buf, dma_len1), 1165 DMA_TO_DEVICE); 1166 } 1167 } 1168 1169 if (tx_buf->data && tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 1170 if (tx_buf->type == MTK_TYPE_SKB) { 1171 struct sk_buff *skb = tx_buf->data; 1172 1173 if (napi) 1174 napi_consume_skb(skb, napi); 1175 else 1176 dev_kfree_skb_any(skb); 1177 } else { 1178 struct xdp_frame *xdpf = tx_buf->data; 1179 1180 if (napi && tx_buf->type == MTK_TYPE_XDP_TX) 1181 xdp_return_frame_rx_napi(xdpf); 1182 else if (bq) 1183 xdp_return_frame_bulk(xdpf, bq); 1184 else 1185 xdp_return_frame(xdpf); 1186 } 1187 } 1188 tx_buf->flags = 0; 1189 tx_buf->data = NULL; 1190 } 1191 1192 static void setup_tx_buf(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf, 1193 struct mtk_tx_dma *txd, dma_addr_t mapped_addr, 1194 size_t size, int idx) 1195 { 1196 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 1197 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1198 dma_unmap_len_set(tx_buf, dma_len0, size); 1199 } else { 1200 if (idx & 1) { 1201 txd->txd3 = mapped_addr; 1202 txd->txd2 |= TX_DMA_PLEN1(size); 1203 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr); 1204 dma_unmap_len_set(tx_buf, dma_len1, size); 1205 } else { 1206 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1207 txd->txd1 = mapped_addr; 1208 txd->txd2 = TX_DMA_PLEN0(size); 1209 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr); 1210 dma_unmap_len_set(tx_buf, dma_len0, size); 1211 } 1212 } 1213 } 1214 1215 static void mtk_tx_set_dma_desc_v1(struct net_device *dev, void *txd, 1216 struct mtk_tx_dma_desc_info *info) 1217 { 1218 struct mtk_mac *mac = netdev_priv(dev); 1219 struct mtk_eth *eth = mac->hw; 1220 struct mtk_tx_dma *desc = txd; 1221 u32 data; 1222 1223 WRITE_ONCE(desc->txd1, info->addr); 1224 1225 data = TX_DMA_SWC | TX_DMA_PLEN0(info->size) | 1226 FIELD_PREP(TX_DMA_PQID, info->qid); 1227 if (info->last) 1228 data |= TX_DMA_LS0; 1229 WRITE_ONCE(desc->txd3, data); 1230 1231 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT; /* forward port */ 1232 if (info->first) { 1233 if (info->gso) 1234 data |= TX_DMA_TSO; 1235 /* tx checksum offload */ 1236 if (info->csum) 1237 data |= TX_DMA_CHKSUM; 1238 /* vlan header offload */ 1239 if (info->vlan) 1240 data |= TX_DMA_INS_VLAN | info->vlan_tci; 1241 } 1242 WRITE_ONCE(desc->txd4, data); 1243 } 1244 1245 static void mtk_tx_set_dma_desc_v2(struct net_device *dev, void *txd, 1246 struct mtk_tx_dma_desc_info *info) 1247 { 1248 struct mtk_mac *mac = netdev_priv(dev); 1249 struct mtk_tx_dma_v2 *desc = txd; 1250 struct mtk_eth *eth = mac->hw; 1251 u32 data; 1252 1253 WRITE_ONCE(desc->txd1, info->addr); 1254 1255 data = TX_DMA_PLEN0(info->size); 1256 if (info->last) 1257 data |= TX_DMA_LS0; 1258 WRITE_ONCE(desc->txd3, data); 1259 1260 data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1261 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1262 WRITE_ONCE(desc->txd4, data); 1263 1264 data = 0; 1265 if (info->first) { 1266 if (info->gso) 1267 data |= TX_DMA_TSO_V2; 1268 /* tx checksum offload */ 1269 if (info->csum) 1270 data |= TX_DMA_CHKSUM_V2; 1271 } 1272 WRITE_ONCE(desc->txd5, data); 1273 1274 data = 0; 1275 if (info->first && info->vlan) 1276 data |= TX_DMA_INS_VLAN_V2 | info->vlan_tci; 1277 WRITE_ONCE(desc->txd6, data); 1278 1279 WRITE_ONCE(desc->txd7, 0); 1280 WRITE_ONCE(desc->txd8, 0); 1281 } 1282 1283 static void mtk_tx_set_dma_desc(struct net_device *dev, void *txd, 1284 struct mtk_tx_dma_desc_info *info) 1285 { 1286 struct mtk_mac *mac = netdev_priv(dev); 1287 struct mtk_eth *eth = mac->hw; 1288 1289 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1290 mtk_tx_set_dma_desc_v2(dev, txd, info); 1291 else 1292 mtk_tx_set_dma_desc_v1(dev, txd, info); 1293 } 1294 1295 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev, 1296 int tx_num, struct mtk_tx_ring *ring, bool gso) 1297 { 1298 struct mtk_tx_dma_desc_info txd_info = { 1299 .size = skb_headlen(skb), 1300 .gso = gso, 1301 .csum = skb->ip_summed == CHECKSUM_PARTIAL, 1302 .vlan = skb_vlan_tag_present(skb), 1303 .qid = skb_get_queue_mapping(skb), 1304 .vlan_tci = skb_vlan_tag_get(skb), 1305 .first = true, 1306 .last = !skb_is_nonlinear(skb), 1307 }; 1308 struct netdev_queue *txq; 1309 struct mtk_mac *mac = netdev_priv(dev); 1310 struct mtk_eth *eth = mac->hw; 1311 const struct mtk_soc_data *soc = eth->soc; 1312 struct mtk_tx_dma *itxd, *txd; 1313 struct mtk_tx_dma *itxd_pdma, *txd_pdma; 1314 struct mtk_tx_buf *itx_buf, *tx_buf; 1315 int i, n_desc = 1; 1316 int queue = skb_get_queue_mapping(skb); 1317 int k = 0; 1318 1319 txq = netdev_get_tx_queue(dev, queue); 1320 itxd = ring->next_free; 1321 itxd_pdma = qdma_to_pdma(ring, itxd); 1322 if (itxd == ring->last_free) 1323 return -ENOMEM; 1324 1325 itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1326 memset(itx_buf, 0, sizeof(*itx_buf)); 1327 1328 txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size, 1329 DMA_TO_DEVICE); 1330 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1331 return -ENOMEM; 1332 1333 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1334 1335 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1336 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1337 MTK_TX_FLAGS_FPORT1; 1338 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1339 k++); 1340 1341 /* TX SG offload */ 1342 txd = itxd; 1343 txd_pdma = qdma_to_pdma(ring, txd); 1344 1345 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1346 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1347 unsigned int offset = 0; 1348 int frag_size = skb_frag_size(frag); 1349 1350 while (frag_size) { 1351 bool new_desc = true; 1352 1353 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || 1354 (i & 0x1)) { 1355 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1356 txd_pdma = qdma_to_pdma(ring, txd); 1357 if (txd == ring->last_free) 1358 goto err_dma; 1359 1360 n_desc++; 1361 } else { 1362 new_desc = false; 1363 } 1364 1365 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1366 txd_info.size = min_t(unsigned int, frag_size, 1367 soc->txrx.dma_max_len); 1368 txd_info.qid = queue; 1369 txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 && 1370 !(frag_size - txd_info.size); 1371 txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag, 1372 offset, txd_info.size, 1373 DMA_TO_DEVICE); 1374 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info.addr))) 1375 goto err_dma; 1376 1377 mtk_tx_set_dma_desc(dev, txd, &txd_info); 1378 1379 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1380 soc->txrx.txd_size); 1381 if (new_desc) 1382 memset(tx_buf, 0, sizeof(*tx_buf)); 1383 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1384 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1385 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1386 MTK_TX_FLAGS_FPORT1; 1387 1388 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1389 txd_info.size, k++); 1390 1391 frag_size -= txd_info.size; 1392 offset += txd_info.size; 1393 } 1394 } 1395 1396 /* store skb to cleanup */ 1397 itx_buf->type = MTK_TYPE_SKB; 1398 itx_buf->data = skb; 1399 1400 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1401 if (k & 0x1) 1402 txd_pdma->txd2 |= TX_DMA_LS0; 1403 else 1404 txd_pdma->txd2 |= TX_DMA_LS1; 1405 } 1406 1407 netdev_tx_sent_queue(txq, skb->len); 1408 skb_tx_timestamp(skb); 1409 1410 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1411 atomic_sub(n_desc, &ring->free_count); 1412 1413 /* make sure that all changes to the dma ring are flushed before we 1414 * continue 1415 */ 1416 wmb(); 1417 1418 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1419 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1420 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1421 } else { 1422 int next_idx; 1423 1424 next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size), 1425 ring->dma_size); 1426 mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0); 1427 } 1428 1429 return 0; 1430 1431 err_dma: 1432 do { 1433 tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size); 1434 1435 /* unmap dma */ 1436 mtk_tx_unmap(eth, tx_buf, NULL, false); 1437 1438 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1439 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 1440 itxd_pdma->txd2 = TX_DMA_DESP2_DEF; 1441 1442 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2); 1443 itxd_pdma = qdma_to_pdma(ring, itxd); 1444 } while (itxd != txd); 1445 1446 return -ENOMEM; 1447 } 1448 1449 static int mtk_cal_txd_req(struct mtk_eth *eth, struct sk_buff *skb) 1450 { 1451 int i, nfrags = 1; 1452 skb_frag_t *frag; 1453 1454 if (skb_is_gso(skb)) { 1455 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1456 frag = &skb_shinfo(skb)->frags[i]; 1457 nfrags += DIV_ROUND_UP(skb_frag_size(frag), 1458 eth->soc->txrx.dma_max_len); 1459 } 1460 } else { 1461 nfrags += skb_shinfo(skb)->nr_frags; 1462 } 1463 1464 return nfrags; 1465 } 1466 1467 static int mtk_queue_stopped(struct mtk_eth *eth) 1468 { 1469 int i; 1470 1471 for (i = 0; i < MTK_MAC_COUNT; i++) { 1472 if (!eth->netdev[i]) 1473 continue; 1474 if (netif_queue_stopped(eth->netdev[i])) 1475 return 1; 1476 } 1477 1478 return 0; 1479 } 1480 1481 static void mtk_wake_queue(struct mtk_eth *eth) 1482 { 1483 int i; 1484 1485 for (i = 0; i < MTK_MAC_COUNT; i++) { 1486 if (!eth->netdev[i]) 1487 continue; 1488 netif_tx_wake_all_queues(eth->netdev[i]); 1489 } 1490 } 1491 1492 static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev) 1493 { 1494 struct mtk_mac *mac = netdev_priv(dev); 1495 struct mtk_eth *eth = mac->hw; 1496 struct mtk_tx_ring *ring = ð->tx_ring; 1497 struct net_device_stats *stats = &dev->stats; 1498 bool gso = false; 1499 int tx_num; 1500 1501 /* normally we can rely on the stack not calling this more than once, 1502 * however we have 2 queues running on the same ring so we need to lock 1503 * the ring access 1504 */ 1505 spin_lock(ð->page_lock); 1506 1507 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1508 goto drop; 1509 1510 tx_num = mtk_cal_txd_req(eth, skb); 1511 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) { 1512 netif_tx_stop_all_queues(dev); 1513 netif_err(eth, tx_queued, dev, 1514 "Tx Ring full when queue awake!\n"); 1515 spin_unlock(ð->page_lock); 1516 return NETDEV_TX_BUSY; 1517 } 1518 1519 /* TSO: fill MSS info in tcp checksum field */ 1520 if (skb_is_gso(skb)) { 1521 if (skb_cow_head(skb, 0)) { 1522 netif_warn(eth, tx_err, dev, 1523 "GSO expand head fail.\n"); 1524 goto drop; 1525 } 1526 1527 if (skb_shinfo(skb)->gso_type & 1528 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 1529 gso = true; 1530 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size); 1531 } 1532 } 1533 1534 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) 1535 goto drop; 1536 1537 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) 1538 netif_tx_stop_all_queues(dev); 1539 1540 spin_unlock(ð->page_lock); 1541 1542 return NETDEV_TX_OK; 1543 1544 drop: 1545 spin_unlock(ð->page_lock); 1546 stats->tx_dropped++; 1547 dev_kfree_skb_any(skb); 1548 return NETDEV_TX_OK; 1549 } 1550 1551 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth) 1552 { 1553 int i; 1554 struct mtk_rx_ring *ring; 1555 int idx; 1556 1557 if (!eth->hwlro) 1558 return ð->rx_ring[0]; 1559 1560 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1561 struct mtk_rx_dma *rxd; 1562 1563 ring = ð->rx_ring[i]; 1564 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1565 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1566 if (rxd->rxd2 & RX_DMA_DONE) { 1567 ring->calc_idx_update = true; 1568 return ring; 1569 } 1570 } 1571 1572 return NULL; 1573 } 1574 1575 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth) 1576 { 1577 struct mtk_rx_ring *ring; 1578 int i; 1579 1580 if (!eth->hwlro) { 1581 ring = ð->rx_ring[0]; 1582 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1583 } else { 1584 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) { 1585 ring = ð->rx_ring[i]; 1586 if (ring->calc_idx_update) { 1587 ring->calc_idx_update = false; 1588 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 1589 } 1590 } 1591 } 1592 } 1593 1594 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1595 { 1596 return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1597 } 1598 1599 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, 1600 struct xdp_rxq_info *xdp_q, 1601 int id, int size) 1602 { 1603 struct page_pool_params pp_params = { 1604 .order = 0, 1605 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 1606 .pool_size = size, 1607 .nid = NUMA_NO_NODE, 1608 .dev = eth->dma_dev, 1609 .offset = MTK_PP_HEADROOM, 1610 .max_len = MTK_PP_MAX_BUF_SIZE, 1611 }; 1612 struct page_pool *pp; 1613 int err; 1614 1615 pp_params.dma_dir = rcu_access_pointer(eth->prog) ? DMA_BIDIRECTIONAL 1616 : DMA_FROM_DEVICE; 1617 pp = page_pool_create(&pp_params); 1618 if (IS_ERR(pp)) 1619 return pp; 1620 1621 err = __xdp_rxq_info_reg(xdp_q, ð->dummy_dev, id, 1622 eth->rx_napi.napi_id, PAGE_SIZE); 1623 if (err < 0) 1624 goto err_free_pp; 1625 1626 err = xdp_rxq_info_reg_mem_model(xdp_q, MEM_TYPE_PAGE_POOL, pp); 1627 if (err) 1628 goto err_unregister_rxq; 1629 1630 return pp; 1631 1632 err_unregister_rxq: 1633 xdp_rxq_info_unreg(xdp_q); 1634 err_free_pp: 1635 page_pool_destroy(pp); 1636 1637 return ERR_PTR(err); 1638 } 1639 1640 static void *mtk_page_pool_get_buff(struct page_pool *pp, dma_addr_t *dma_addr, 1641 gfp_t gfp_mask) 1642 { 1643 struct page *page; 1644 1645 page = page_pool_alloc_pages(pp, gfp_mask | __GFP_NOWARN); 1646 if (!page) 1647 return NULL; 1648 1649 *dma_addr = page_pool_get_dma_addr(page) + MTK_PP_HEADROOM; 1650 return page_address(page); 1651 } 1652 1653 static void mtk_rx_put_buff(struct mtk_rx_ring *ring, void *data, bool napi) 1654 { 1655 if (ring->page_pool) 1656 page_pool_put_full_page(ring->page_pool, 1657 virt_to_head_page(data), napi); 1658 else 1659 skb_free_frag(data); 1660 } 1661 1662 static int mtk_xdp_frame_map(struct mtk_eth *eth, struct net_device *dev, 1663 struct mtk_tx_dma_desc_info *txd_info, 1664 struct mtk_tx_dma *txd, struct mtk_tx_buf *tx_buf, 1665 void *data, u16 headroom, int index, bool dma_map) 1666 { 1667 struct mtk_tx_ring *ring = ð->tx_ring; 1668 struct mtk_mac *mac = netdev_priv(dev); 1669 struct mtk_tx_dma *txd_pdma; 1670 1671 if (dma_map) { /* ndo_xdp_xmit */ 1672 txd_info->addr = dma_map_single(eth->dma_dev, data, 1673 txd_info->size, DMA_TO_DEVICE); 1674 if (unlikely(dma_mapping_error(eth->dma_dev, txd_info->addr))) 1675 return -ENOMEM; 1676 1677 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1678 } else { 1679 struct page *page = virt_to_head_page(data); 1680 1681 txd_info->addr = page_pool_get_dma_addr(page) + 1682 sizeof(struct xdp_frame) + headroom; 1683 dma_sync_single_for_device(eth->dma_dev, txd_info->addr, 1684 txd_info->size, DMA_BIDIRECTIONAL); 1685 } 1686 mtk_tx_set_dma_desc(dev, txd, txd_info); 1687 1688 tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1689 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1690 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1691 1692 txd_pdma = qdma_to_pdma(ring, txd); 1693 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info->addr, txd_info->size, 1694 index); 1695 1696 return 0; 1697 } 1698 1699 static int mtk_xdp_submit_frame(struct mtk_eth *eth, struct xdp_frame *xdpf, 1700 struct net_device *dev, bool dma_map) 1701 { 1702 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf); 1703 const struct mtk_soc_data *soc = eth->soc; 1704 struct mtk_tx_ring *ring = ð->tx_ring; 1705 struct mtk_mac *mac = netdev_priv(dev); 1706 struct mtk_tx_dma_desc_info txd_info = { 1707 .size = xdpf->len, 1708 .first = true, 1709 .last = !xdp_frame_has_frags(xdpf), 1710 .qid = mac->id, 1711 }; 1712 int err, index = 0, n_desc = 1, nr_frags; 1713 struct mtk_tx_buf *htx_buf, *tx_buf; 1714 struct mtk_tx_dma *htxd, *txd; 1715 void *data = xdpf->data; 1716 1717 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1718 return -EBUSY; 1719 1720 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0; 1721 if (unlikely(atomic_read(&ring->free_count) <= 1 + nr_frags)) 1722 return -EBUSY; 1723 1724 spin_lock(ð->page_lock); 1725 1726 txd = ring->next_free; 1727 if (txd == ring->last_free) { 1728 spin_unlock(ð->page_lock); 1729 return -ENOMEM; 1730 } 1731 htxd = txd; 1732 1733 tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size); 1734 memset(tx_buf, 0, sizeof(*tx_buf)); 1735 htx_buf = tx_buf; 1736 1737 for (;;) { 1738 err = mtk_xdp_frame_map(eth, dev, &txd_info, txd, tx_buf, 1739 data, xdpf->headroom, index, dma_map); 1740 if (err < 0) 1741 goto unmap; 1742 1743 if (txd_info.last) 1744 break; 1745 1746 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA) || (index & 0x1)) { 1747 txd = mtk_qdma_phys_to_virt(ring, txd->txd2); 1748 if (txd == ring->last_free) 1749 goto unmap; 1750 1751 tx_buf = mtk_desc_to_tx_buf(ring, txd, 1752 soc->txrx.txd_size); 1753 memset(tx_buf, 0, sizeof(*tx_buf)); 1754 n_desc++; 1755 } 1756 1757 memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info)); 1758 txd_info.size = skb_frag_size(&sinfo->frags[index]); 1759 txd_info.last = index + 1 == nr_frags; 1760 txd_info.qid = mac->id; 1761 data = skb_frag_address(&sinfo->frags[index]); 1762 1763 index++; 1764 } 1765 /* store xdpf for cleanup */ 1766 htx_buf->data = xdpf; 1767 1768 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1769 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, txd); 1770 1771 if (index & 1) 1772 txd_pdma->txd2 |= TX_DMA_LS0; 1773 else 1774 txd_pdma->txd2 |= TX_DMA_LS1; 1775 } 1776 1777 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2); 1778 atomic_sub(n_desc, &ring->free_count); 1779 1780 /* make sure that all changes to the dma ring are flushed before we 1781 * continue 1782 */ 1783 wmb(); 1784 1785 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1786 mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr); 1787 } else { 1788 int idx; 1789 1790 idx = txd_to_idx(ring, txd, soc->txrx.txd_size); 1791 mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size), 1792 MT7628_TX_CTX_IDX0); 1793 } 1794 1795 spin_unlock(ð->page_lock); 1796 1797 return 0; 1798 1799 unmap: 1800 while (htxd != txd) { 1801 tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size); 1802 mtk_tx_unmap(eth, tx_buf, NULL, false); 1803 1804 htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 1805 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 1806 struct mtk_tx_dma *txd_pdma = qdma_to_pdma(ring, htxd); 1807 1808 txd_pdma->txd2 = TX_DMA_DESP2_DEF; 1809 } 1810 1811 htxd = mtk_qdma_phys_to_virt(ring, htxd->txd2); 1812 } 1813 1814 spin_unlock(ð->page_lock); 1815 1816 return err; 1817 } 1818 1819 static int mtk_xdp_xmit(struct net_device *dev, int num_frame, 1820 struct xdp_frame **frames, u32 flags) 1821 { 1822 struct mtk_mac *mac = netdev_priv(dev); 1823 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1824 struct mtk_eth *eth = mac->hw; 1825 int i, nxmit = 0; 1826 1827 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 1828 return -EINVAL; 1829 1830 for (i = 0; i < num_frame; i++) { 1831 if (mtk_xdp_submit_frame(eth, frames[i], dev, true)) 1832 break; 1833 nxmit++; 1834 } 1835 1836 u64_stats_update_begin(&hw_stats->syncp); 1837 hw_stats->xdp_stats.tx_xdp_xmit += nxmit; 1838 hw_stats->xdp_stats.tx_xdp_xmit_errors += num_frame - nxmit; 1839 u64_stats_update_end(&hw_stats->syncp); 1840 1841 return nxmit; 1842 } 1843 1844 static u32 mtk_xdp_run(struct mtk_eth *eth, struct mtk_rx_ring *ring, 1845 struct xdp_buff *xdp, struct net_device *dev) 1846 { 1847 struct mtk_mac *mac = netdev_priv(dev); 1848 struct mtk_hw_stats *hw_stats = mac->hw_stats; 1849 u64 *count = &hw_stats->xdp_stats.rx_xdp_drop; 1850 struct bpf_prog *prog; 1851 u32 act = XDP_PASS; 1852 1853 rcu_read_lock(); 1854 1855 prog = rcu_dereference(eth->prog); 1856 if (!prog) 1857 goto out; 1858 1859 act = bpf_prog_run_xdp(prog, xdp); 1860 switch (act) { 1861 case XDP_PASS: 1862 count = &hw_stats->xdp_stats.rx_xdp_pass; 1863 goto update_stats; 1864 case XDP_REDIRECT: 1865 if (unlikely(xdp_do_redirect(dev, xdp, prog))) { 1866 act = XDP_DROP; 1867 break; 1868 } 1869 1870 count = &hw_stats->xdp_stats.rx_xdp_redirect; 1871 goto update_stats; 1872 case XDP_TX: { 1873 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 1874 1875 if (!xdpf || mtk_xdp_submit_frame(eth, xdpf, dev, false)) { 1876 count = &hw_stats->xdp_stats.rx_xdp_tx_errors; 1877 act = XDP_DROP; 1878 break; 1879 } 1880 1881 count = &hw_stats->xdp_stats.rx_xdp_tx; 1882 goto update_stats; 1883 } 1884 default: 1885 bpf_warn_invalid_xdp_action(dev, prog, act); 1886 fallthrough; 1887 case XDP_ABORTED: 1888 trace_xdp_exception(dev, prog, act); 1889 fallthrough; 1890 case XDP_DROP: 1891 break; 1892 } 1893 1894 page_pool_put_full_page(ring->page_pool, 1895 virt_to_head_page(xdp->data), true); 1896 1897 update_stats: 1898 u64_stats_update_begin(&hw_stats->syncp); 1899 *count = *count + 1; 1900 u64_stats_update_end(&hw_stats->syncp); 1901 out: 1902 rcu_read_unlock(); 1903 1904 return act; 1905 } 1906 1907 static int mtk_poll_rx(struct napi_struct *napi, int budget, 1908 struct mtk_eth *eth) 1909 { 1910 struct dim_sample dim_sample = {}; 1911 struct mtk_rx_ring *ring; 1912 bool xdp_flush = false; 1913 int idx; 1914 struct sk_buff *skb; 1915 u8 *data, *new_data; 1916 struct mtk_rx_dma_v2 *rxd, trxd; 1917 int done = 0, bytes = 0; 1918 1919 while (done < budget) { 1920 unsigned int pktlen, *rxdcsum; 1921 struct net_device *netdev; 1922 dma_addr_t dma_addr; 1923 u32 hash, reason; 1924 int mac = 0; 1925 1926 ring = mtk_get_rx_ring(eth); 1927 if (unlikely(!ring)) 1928 goto rx_done; 1929 1930 idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size); 1931 rxd = ring->dma + idx * eth->soc->txrx.rxd_size; 1932 data = ring->data[idx]; 1933 1934 if (!mtk_rx_get_desc(eth, &trxd, rxd)) 1935 break; 1936 1937 /* find out which mac the packet come from. values start at 1 */ 1938 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1939 mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 1940 else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1941 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 1942 mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1943 1944 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1945 !eth->netdev[mac])) 1946 goto release_desc; 1947 1948 netdev = eth->netdev[mac]; 1949 1950 if (unlikely(test_bit(MTK_RESETTING, ð->state))) 1951 goto release_desc; 1952 1953 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2); 1954 1955 /* alloc new buffer */ 1956 if (ring->page_pool) { 1957 struct page *page = virt_to_head_page(data); 1958 struct xdp_buff xdp; 1959 u32 ret; 1960 1961 new_data = mtk_page_pool_get_buff(ring->page_pool, 1962 &dma_addr, 1963 GFP_ATOMIC); 1964 if (unlikely(!new_data)) { 1965 netdev->stats.rx_dropped++; 1966 goto release_desc; 1967 } 1968 1969 dma_sync_single_for_cpu(eth->dma_dev, 1970 page_pool_get_dma_addr(page) + MTK_PP_HEADROOM, 1971 pktlen, page_pool_get_dma_dir(ring->page_pool)); 1972 1973 xdp_init_buff(&xdp, PAGE_SIZE, &ring->xdp_q); 1974 xdp_prepare_buff(&xdp, data, MTK_PP_HEADROOM, pktlen, 1975 false); 1976 xdp_buff_clear_frags_flag(&xdp); 1977 1978 ret = mtk_xdp_run(eth, ring, &xdp, netdev); 1979 if (ret == XDP_REDIRECT) 1980 xdp_flush = true; 1981 1982 if (ret != XDP_PASS) 1983 goto skip_rx; 1984 1985 skb = build_skb(data, PAGE_SIZE); 1986 if (unlikely(!skb)) { 1987 page_pool_put_full_page(ring->page_pool, 1988 page, true); 1989 netdev->stats.rx_dropped++; 1990 goto skip_rx; 1991 } 1992 1993 skb_reserve(skb, xdp.data - xdp.data_hard_start); 1994 skb_put(skb, xdp.data_end - xdp.data); 1995 skb_mark_for_recycle(skb); 1996 } else { 1997 if (ring->frag_size <= PAGE_SIZE) 1998 new_data = napi_alloc_frag(ring->frag_size); 1999 else 2000 new_data = mtk_max_lro_buf_alloc(GFP_ATOMIC); 2001 2002 if (unlikely(!new_data)) { 2003 netdev->stats.rx_dropped++; 2004 goto release_desc; 2005 } 2006 2007 dma_addr = dma_map_single(eth->dma_dev, 2008 new_data + NET_SKB_PAD + eth->ip_align, 2009 ring->buf_size, DMA_FROM_DEVICE); 2010 if (unlikely(dma_mapping_error(eth->dma_dev, 2011 dma_addr))) { 2012 skb_free_frag(new_data); 2013 netdev->stats.rx_dropped++; 2014 goto release_desc; 2015 } 2016 2017 dma_unmap_single(eth->dma_dev, trxd.rxd1, 2018 ring->buf_size, DMA_FROM_DEVICE); 2019 2020 skb = build_skb(data, ring->frag_size); 2021 if (unlikely(!skb)) { 2022 netdev->stats.rx_dropped++; 2023 skb_free_frag(data); 2024 goto skip_rx; 2025 } 2026 2027 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN); 2028 skb_put(skb, pktlen); 2029 } 2030 2031 skb->dev = netdev; 2032 bytes += skb->len; 2033 2034 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2035 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2036 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2037 if (hash != MTK_RXD5_FOE_ENTRY) 2038 skb_set_hash(skb, jhash_1word(hash, 0), 2039 PKT_HASH_TYPE_L4); 2040 rxdcsum = &trxd.rxd3; 2041 } else { 2042 reason = FIELD_GET(MTK_RXD4_PPE_CPU_REASON, trxd.rxd4); 2043 hash = trxd.rxd4 & MTK_RXD4_FOE_ENTRY; 2044 if (hash != MTK_RXD4_FOE_ENTRY) 2045 skb_set_hash(skb, jhash_1word(hash, 0), 2046 PKT_HASH_TYPE_L4); 2047 rxdcsum = &trxd.rxd4; 2048 } 2049 2050 if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid) 2051 skb->ip_summed = CHECKSUM_UNNECESSARY; 2052 else 2053 skb_checksum_none_assert(skb); 2054 skb->protocol = eth_type_trans(skb, netdev); 2055 2056 /* When using VLAN untagging in combination with DSA, the 2057 * hardware treats the MTK special tag as a VLAN and untags it. 2058 */ 2059 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && 2060 (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { 2061 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2062 2063 if (port < ARRAY_SIZE(eth->dsa_meta) && 2064 eth->dsa_meta[port]) 2065 skb_dst_set_noref(skb, ð->dsa_meta[port]->dst); 2066 } 2067 2068 if (reason == MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 2069 mtk_ppe_check_skb(eth->ppe[0], skb, hash); 2070 2071 skb_record_rx_queue(skb, 0); 2072 napi_gro_receive(napi, skb); 2073 2074 skip_rx: 2075 ring->data[idx] = new_data; 2076 rxd->rxd1 = (unsigned int)dma_addr; 2077 release_desc: 2078 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2079 rxd->rxd2 = RX_DMA_LSO; 2080 else 2081 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2082 2083 ring->calc_idx = idx; 2084 done++; 2085 } 2086 2087 rx_done: 2088 if (done) { 2089 /* make sure that all changes to the dma ring are flushed before 2090 * we continue 2091 */ 2092 wmb(); 2093 mtk_update_rx_cpu_idx(eth); 2094 } 2095 2096 eth->rx_packets += done; 2097 eth->rx_bytes += bytes; 2098 dim_update_sample(eth->rx_events, eth->rx_packets, eth->rx_bytes, 2099 &dim_sample); 2100 net_dim(ð->rx_dim, dim_sample); 2101 2102 if (xdp_flush) 2103 xdp_do_flush_map(); 2104 2105 return done; 2106 } 2107 2108 struct mtk_poll_state { 2109 struct netdev_queue *txq; 2110 unsigned int total; 2111 unsigned int done; 2112 unsigned int bytes; 2113 }; 2114 2115 static void 2116 mtk_poll_tx_done(struct mtk_eth *eth, struct mtk_poll_state *state, u8 mac, 2117 struct sk_buff *skb) 2118 { 2119 struct netdev_queue *txq; 2120 struct net_device *dev; 2121 unsigned int bytes = skb->len; 2122 2123 state->total++; 2124 eth->tx_packets++; 2125 eth->tx_bytes += bytes; 2126 2127 dev = eth->netdev[mac]; 2128 if (!dev) 2129 return; 2130 2131 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); 2132 if (state->txq == txq) { 2133 state->done++; 2134 state->bytes += bytes; 2135 return; 2136 } 2137 2138 if (state->txq) 2139 netdev_tx_completed_queue(state->txq, state->done, state->bytes); 2140 2141 state->txq = txq; 2142 state->done = 1; 2143 state->bytes = bytes; 2144 } 2145 2146 static int mtk_poll_tx_qdma(struct mtk_eth *eth, int budget, 2147 struct mtk_poll_state *state) 2148 { 2149 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2150 struct mtk_tx_ring *ring = ð->tx_ring; 2151 struct mtk_tx_buf *tx_buf; 2152 struct xdp_frame_bulk bq; 2153 struct mtk_tx_dma *desc; 2154 u32 cpu, dma; 2155 2156 cpu = ring->last_free_ptr; 2157 dma = mtk_r32(eth, reg_map->qdma.drx_ptr); 2158 2159 desc = mtk_qdma_phys_to_virt(ring, cpu); 2160 xdp_frame_bulk_init(&bq); 2161 2162 while ((cpu != dma) && budget) { 2163 u32 next_cpu = desc->txd2; 2164 int mac = 0; 2165 2166 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2167 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) 2168 break; 2169 2170 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2171 eth->soc->txrx.txd_size); 2172 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2173 mac = 1; 2174 2175 if (!tx_buf->data) 2176 break; 2177 2178 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2179 if (tx_buf->type == MTK_TYPE_SKB) 2180 mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2181 2182 budget--; 2183 } 2184 mtk_tx_unmap(eth, tx_buf, &bq, true); 2185 2186 ring->last_free = desc; 2187 atomic_inc(&ring->free_count); 2188 2189 cpu = next_cpu; 2190 } 2191 xdp_flush_frame_bulk(&bq); 2192 2193 ring->last_free_ptr = cpu; 2194 mtk_w32(eth, cpu, reg_map->qdma.crx_ptr); 2195 2196 return budget; 2197 } 2198 2199 static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget, 2200 struct mtk_poll_state *state) 2201 { 2202 struct mtk_tx_ring *ring = ð->tx_ring; 2203 struct mtk_tx_buf *tx_buf; 2204 struct xdp_frame_bulk bq; 2205 struct mtk_tx_dma *desc; 2206 u32 cpu, dma; 2207 2208 cpu = ring->cpu_idx; 2209 dma = mtk_r32(eth, MT7628_TX_DTX_IDX0); 2210 xdp_frame_bulk_init(&bq); 2211 2212 while ((cpu != dma) && budget) { 2213 tx_buf = &ring->buf[cpu]; 2214 if (!tx_buf->data) 2215 break; 2216 2217 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2218 if (tx_buf->type == MTK_TYPE_SKB) 2219 mtk_poll_tx_done(eth, state, 0, tx_buf->data); 2220 budget--; 2221 } 2222 mtk_tx_unmap(eth, tx_buf, &bq, true); 2223 2224 desc = ring->dma + cpu * eth->soc->txrx.txd_size; 2225 ring->last_free = desc; 2226 atomic_inc(&ring->free_count); 2227 2228 cpu = NEXT_DESP_IDX(cpu, ring->dma_size); 2229 } 2230 xdp_flush_frame_bulk(&bq); 2231 2232 ring->cpu_idx = cpu; 2233 2234 return budget; 2235 } 2236 2237 static int mtk_poll_tx(struct mtk_eth *eth, int budget) 2238 { 2239 struct mtk_tx_ring *ring = ð->tx_ring; 2240 struct dim_sample dim_sample = {}; 2241 struct mtk_poll_state state = {}; 2242 2243 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2244 budget = mtk_poll_tx_qdma(eth, budget, &state); 2245 else 2246 budget = mtk_poll_tx_pdma(eth, budget, &state); 2247 2248 if (state.txq) 2249 netdev_tx_completed_queue(state.txq, state.done, state.bytes); 2250 2251 dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes, 2252 &dim_sample); 2253 net_dim(ð->tx_dim, dim_sample); 2254 2255 if (mtk_queue_stopped(eth) && 2256 (atomic_read(&ring->free_count) > ring->thresh)) 2257 mtk_wake_queue(eth); 2258 2259 return state.total; 2260 } 2261 2262 static void mtk_handle_status_irq(struct mtk_eth *eth) 2263 { 2264 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2); 2265 2266 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) { 2267 mtk_stats_update(eth); 2268 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF), 2269 MTK_INT_STATUS2); 2270 } 2271 } 2272 2273 static int mtk_napi_tx(struct napi_struct *napi, int budget) 2274 { 2275 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi); 2276 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2277 int tx_done = 0; 2278 2279 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2280 mtk_handle_status_irq(eth); 2281 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status); 2282 tx_done = mtk_poll_tx(eth, budget); 2283 2284 if (unlikely(netif_msg_intr(eth))) { 2285 dev_info(eth->dev, 2286 "done tx %d, intr 0x%08x/0x%x\n", tx_done, 2287 mtk_r32(eth, reg_map->tx_irq_status), 2288 mtk_r32(eth, reg_map->tx_irq_mask)); 2289 } 2290 2291 if (tx_done == budget) 2292 return budget; 2293 2294 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 2295 return budget; 2296 2297 if (napi_complete_done(napi, tx_done)) 2298 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 2299 2300 return tx_done; 2301 } 2302 2303 static int mtk_napi_rx(struct napi_struct *napi, int budget) 2304 { 2305 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi); 2306 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2307 int rx_done_total = 0; 2308 2309 mtk_handle_status_irq(eth); 2310 2311 do { 2312 int rx_done; 2313 2314 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, 2315 reg_map->pdma.irq_status); 2316 rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth); 2317 rx_done_total += rx_done; 2318 2319 if (unlikely(netif_msg_intr(eth))) { 2320 dev_info(eth->dev, 2321 "done rx %d, intr 0x%08x/0x%x\n", rx_done, 2322 mtk_r32(eth, reg_map->pdma.irq_status), 2323 mtk_r32(eth, reg_map->pdma.irq_mask)); 2324 } 2325 2326 if (rx_done_total == budget) 2327 return budget; 2328 2329 } while (mtk_r32(eth, reg_map->pdma.irq_status) & 2330 eth->soc->txrx.rx_irq_done_mask); 2331 2332 if (napi_complete_done(napi, rx_done_total)) 2333 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 2334 2335 return rx_done_total; 2336 } 2337 2338 static int mtk_tx_alloc(struct mtk_eth *eth) 2339 { 2340 const struct mtk_soc_data *soc = eth->soc; 2341 struct mtk_tx_ring *ring = ð->tx_ring; 2342 int i, sz = soc->txrx.txd_size; 2343 struct mtk_tx_dma_v2 *txd; 2344 int ring_size; 2345 u32 ofs, val; 2346 2347 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) 2348 ring_size = MTK_QDMA_RING_SIZE; 2349 else 2350 ring_size = MTK_DMA_SIZE; 2351 2352 ring->buf = kcalloc(ring_size, sizeof(*ring->buf), 2353 GFP_KERNEL); 2354 if (!ring->buf) 2355 goto no_tx_mem; 2356 2357 ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2358 &ring->phys, GFP_KERNEL); 2359 if (!ring->dma) 2360 goto no_tx_mem; 2361 2362 for (i = 0; i < ring_size; i++) { 2363 int next = (i + 1) % ring_size; 2364 u32 next_ptr = ring->phys + next * sz; 2365 2366 txd = ring->dma + i * sz; 2367 txd->txd2 = next_ptr; 2368 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2369 txd->txd4 = 0; 2370 if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2371 txd->txd5 = 0; 2372 txd->txd6 = 0; 2373 txd->txd7 = 0; 2374 txd->txd8 = 0; 2375 } 2376 } 2377 2378 /* On MT7688 (PDMA only) this driver uses the ring->dma structs 2379 * only as the framework. The real HW descriptors are the PDMA 2380 * descriptors in ring->dma_pdma. 2381 */ 2382 if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2383 ring->dma_pdma = dma_alloc_coherent(eth->dma_dev, ring_size * sz, 2384 &ring->phys_pdma, GFP_KERNEL); 2385 if (!ring->dma_pdma) 2386 goto no_tx_mem; 2387 2388 for (i = 0; i < ring_size; i++) { 2389 ring->dma_pdma[i].txd2 = TX_DMA_DESP2_DEF; 2390 ring->dma_pdma[i].txd4 = 0; 2391 } 2392 } 2393 2394 ring->dma_size = ring_size; 2395 atomic_set(&ring->free_count, ring_size - 2); 2396 ring->next_free = ring->dma; 2397 ring->last_free = (void *)txd; 2398 ring->last_free_ptr = (u32)(ring->phys + ((ring_size - 1) * sz)); 2399 ring->thresh = MAX_SKB_FRAGS; 2400 2401 /* make sure that all changes to the dma ring are flushed before we 2402 * continue 2403 */ 2404 wmb(); 2405 2406 if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) { 2407 mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr); 2408 mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr); 2409 mtk_w32(eth, 2410 ring->phys + ((ring_size - 1) * sz), 2411 soc->reg_map->qdma.crx_ptr); 2412 mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr); 2413 2414 for (i = 0, ofs = 0; i < MTK_QDMA_NUM_QUEUES; i++) { 2415 val = (QDMA_RES_THRES << 8) | QDMA_RES_THRES; 2416 mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs); 2417 2418 val = MTK_QTX_SCH_MIN_RATE_EN | 2419 /* minimum: 10 Mbps */ 2420 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2421 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2422 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2423 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2424 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2425 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2426 ofs += MTK_QTX_OFFSET; 2427 } 2428 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2429 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2430 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2431 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2432 } else { 2433 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); 2434 mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0); 2435 mtk_w32(eth, 0, MT7628_TX_CTX_IDX0); 2436 mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx); 2437 } 2438 2439 return 0; 2440 2441 no_tx_mem: 2442 return -ENOMEM; 2443 } 2444 2445 static void mtk_tx_clean(struct mtk_eth *eth) 2446 { 2447 const struct mtk_soc_data *soc = eth->soc; 2448 struct mtk_tx_ring *ring = ð->tx_ring; 2449 int i; 2450 2451 if (ring->buf) { 2452 for (i = 0; i < ring->dma_size; i++) 2453 mtk_tx_unmap(eth, &ring->buf[i], NULL, false); 2454 kfree(ring->buf); 2455 ring->buf = NULL; 2456 } 2457 2458 if (ring->dma) { 2459 dma_free_coherent(eth->dma_dev, 2460 ring->dma_size * soc->txrx.txd_size, 2461 ring->dma, ring->phys); 2462 ring->dma = NULL; 2463 } 2464 2465 if (ring->dma_pdma) { 2466 dma_free_coherent(eth->dma_dev, 2467 ring->dma_size * soc->txrx.txd_size, 2468 ring->dma_pdma, ring->phys_pdma); 2469 ring->dma_pdma = NULL; 2470 } 2471 } 2472 2473 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag) 2474 { 2475 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 2476 struct mtk_rx_ring *ring; 2477 int rx_data_len, rx_dma_size; 2478 int i; 2479 2480 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2481 if (ring_no) 2482 return -EINVAL; 2483 ring = ð->rx_ring_qdma; 2484 } else { 2485 ring = ð->rx_ring[ring_no]; 2486 } 2487 2488 if (rx_flag == MTK_RX_FLAGS_HWLRO) { 2489 rx_data_len = MTK_MAX_LRO_RX_LENGTH; 2490 rx_dma_size = MTK_HW_LRO_DMA_SIZE; 2491 } else { 2492 rx_data_len = ETH_DATA_LEN; 2493 rx_dma_size = MTK_DMA_SIZE; 2494 } 2495 2496 ring->frag_size = mtk_max_frag_size(rx_data_len); 2497 ring->buf_size = mtk_max_buf_size(ring->frag_size); 2498 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data), 2499 GFP_KERNEL); 2500 if (!ring->data) 2501 return -ENOMEM; 2502 2503 if (mtk_page_pool_enabled(eth)) { 2504 struct page_pool *pp; 2505 2506 pp = mtk_create_page_pool(eth, &ring->xdp_q, ring_no, 2507 rx_dma_size); 2508 if (IS_ERR(pp)) 2509 return PTR_ERR(pp); 2510 2511 ring->page_pool = pp; 2512 } 2513 2514 ring->dma = dma_alloc_coherent(eth->dma_dev, 2515 rx_dma_size * eth->soc->txrx.rxd_size, 2516 &ring->phys, GFP_KERNEL); 2517 if (!ring->dma) 2518 return -ENOMEM; 2519 2520 for (i = 0; i < rx_dma_size; i++) { 2521 struct mtk_rx_dma_v2 *rxd; 2522 dma_addr_t dma_addr; 2523 void *data; 2524 2525 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2526 if (ring->page_pool) { 2527 data = mtk_page_pool_get_buff(ring->page_pool, 2528 &dma_addr, GFP_KERNEL); 2529 if (!data) 2530 return -ENOMEM; 2531 } else { 2532 if (ring->frag_size <= PAGE_SIZE) 2533 data = netdev_alloc_frag(ring->frag_size); 2534 else 2535 data = mtk_max_lro_buf_alloc(GFP_KERNEL); 2536 2537 if (!data) 2538 return -ENOMEM; 2539 2540 dma_addr = dma_map_single(eth->dma_dev, 2541 data + NET_SKB_PAD + eth->ip_align, 2542 ring->buf_size, DMA_FROM_DEVICE); 2543 if (unlikely(dma_mapping_error(eth->dma_dev, 2544 dma_addr))) { 2545 skb_free_frag(data); 2546 return -ENOMEM; 2547 } 2548 } 2549 rxd->rxd1 = (unsigned int)dma_addr; 2550 ring->data[i] = data; 2551 2552 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 2553 rxd->rxd2 = RX_DMA_LSO; 2554 else 2555 rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size); 2556 2557 rxd->rxd3 = 0; 2558 rxd->rxd4 = 0; 2559 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2560 rxd->rxd5 = 0; 2561 rxd->rxd6 = 0; 2562 rxd->rxd7 = 0; 2563 rxd->rxd8 = 0; 2564 } 2565 } 2566 2567 ring->dma_size = rx_dma_size; 2568 ring->calc_idx_update = false; 2569 ring->calc_idx = rx_dma_size - 1; 2570 if (rx_flag == MTK_RX_FLAGS_QDMA) 2571 ring->crx_idx_reg = reg_map->qdma.qcrx_ptr + 2572 ring_no * MTK_QRX_OFFSET; 2573 else 2574 ring->crx_idx_reg = reg_map->pdma.pcrx_ptr + 2575 ring_no * MTK_QRX_OFFSET; 2576 /* make sure that all changes to the dma ring are flushed before we 2577 * continue 2578 */ 2579 wmb(); 2580 2581 if (rx_flag == MTK_RX_FLAGS_QDMA) { 2582 mtk_w32(eth, ring->phys, 2583 reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2584 mtk_w32(eth, rx_dma_size, 2585 reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2586 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2587 reg_map->qdma.rst_idx); 2588 } else { 2589 mtk_w32(eth, ring->phys, 2590 reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET); 2591 mtk_w32(eth, rx_dma_size, 2592 reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET); 2593 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), 2594 reg_map->pdma.rst_idx); 2595 } 2596 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg); 2597 2598 return 0; 2599 } 2600 2601 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring) 2602 { 2603 int i; 2604 2605 if (ring->data && ring->dma) { 2606 for (i = 0; i < ring->dma_size; i++) { 2607 struct mtk_rx_dma *rxd; 2608 2609 if (!ring->data[i]) 2610 continue; 2611 2612 rxd = ring->dma + i * eth->soc->txrx.rxd_size; 2613 if (!rxd->rxd1) 2614 continue; 2615 2616 dma_unmap_single(eth->dma_dev, rxd->rxd1, 2617 ring->buf_size, DMA_FROM_DEVICE); 2618 mtk_rx_put_buff(ring, ring->data[i], false); 2619 } 2620 kfree(ring->data); 2621 ring->data = NULL; 2622 } 2623 2624 if (ring->dma) { 2625 dma_free_coherent(eth->dma_dev, 2626 ring->dma_size * eth->soc->txrx.rxd_size, 2627 ring->dma, ring->phys); 2628 ring->dma = NULL; 2629 } 2630 2631 if (ring->page_pool) { 2632 if (xdp_rxq_info_is_reg(&ring->xdp_q)) 2633 xdp_rxq_info_unreg(&ring->xdp_q); 2634 page_pool_destroy(ring->page_pool); 2635 ring->page_pool = NULL; 2636 } 2637 } 2638 2639 static int mtk_hwlro_rx_init(struct mtk_eth *eth) 2640 { 2641 int i; 2642 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0; 2643 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0; 2644 2645 /* set LRO rings to auto-learn modes */ 2646 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE; 2647 2648 /* validate LRO ring */ 2649 ring_ctrl_dw2 |= MTK_RING_VLD; 2650 2651 /* set AGE timer (unit: 20us) */ 2652 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H; 2653 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L; 2654 2655 /* set max AGG timer (unit: 20us) */ 2656 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME; 2657 2658 /* set max LRO AGG count */ 2659 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L; 2660 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H; 2661 2662 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2663 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i)); 2664 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i)); 2665 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i)); 2666 } 2667 2668 /* IPv4 checksum update enable */ 2669 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN; 2670 2671 /* switch priority comparison to packet count mode */ 2672 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE; 2673 2674 /* bandwidth threshold setting */ 2675 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2); 2676 2677 /* auto-learn score delta setting */ 2678 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA); 2679 2680 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */ 2681 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME, 2682 MTK_PDMA_LRO_ALT_REFRESH_TIMER); 2683 2684 /* set HW LRO mode & the max aggregation count for rx packets */ 2685 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff); 2686 2687 /* the minimal remaining room of SDL0 in RXD for lro aggregation */ 2688 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL; 2689 2690 /* enable HW LRO */ 2691 lro_ctrl_dw0 |= MTK_LRO_EN; 2692 2693 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3); 2694 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0); 2695 2696 return 0; 2697 } 2698 2699 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth) 2700 { 2701 int i; 2702 u32 val; 2703 2704 /* relinquish lro rings, flush aggregated packets */ 2705 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0); 2706 2707 /* wait for relinquishments done */ 2708 for (i = 0; i < 10; i++) { 2709 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0); 2710 if (val & MTK_LRO_RING_RELINQUISH_DONE) { 2711 msleep(20); 2712 continue; 2713 } 2714 break; 2715 } 2716 2717 /* invalidate lro rings */ 2718 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2719 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i)); 2720 2721 /* disable HW LRO */ 2722 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0); 2723 } 2724 2725 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip) 2726 { 2727 u32 reg_val; 2728 2729 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2730 2731 /* invalidate the IP setting */ 2732 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2733 2734 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx)); 2735 2736 /* validate the IP setting */ 2737 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2738 } 2739 2740 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx) 2741 { 2742 u32 reg_val; 2743 2744 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx)); 2745 2746 /* invalidate the IP setting */ 2747 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx)); 2748 2749 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx)); 2750 } 2751 2752 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac) 2753 { 2754 int cnt = 0; 2755 int i; 2756 2757 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2758 if (mac->hwlro_ip[i]) 2759 cnt++; 2760 } 2761 2762 return cnt; 2763 } 2764 2765 static int mtk_hwlro_add_ipaddr(struct net_device *dev, 2766 struct ethtool_rxnfc *cmd) 2767 { 2768 struct ethtool_rx_flow_spec *fsp = 2769 (struct ethtool_rx_flow_spec *)&cmd->fs; 2770 struct mtk_mac *mac = netdev_priv(dev); 2771 struct mtk_eth *eth = mac->hw; 2772 int hwlro_idx; 2773 2774 if ((fsp->flow_type != TCP_V4_FLOW) || 2775 (!fsp->h_u.tcp_ip4_spec.ip4dst) || 2776 (fsp->location > 1)) 2777 return -EINVAL; 2778 2779 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst); 2780 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2781 2782 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2783 2784 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]); 2785 2786 return 0; 2787 } 2788 2789 static int mtk_hwlro_del_ipaddr(struct net_device *dev, 2790 struct ethtool_rxnfc *cmd) 2791 { 2792 struct ethtool_rx_flow_spec *fsp = 2793 (struct ethtool_rx_flow_spec *)&cmd->fs; 2794 struct mtk_mac *mac = netdev_priv(dev); 2795 struct mtk_eth *eth = mac->hw; 2796 int hwlro_idx; 2797 2798 if (fsp->location > 1) 2799 return -EINVAL; 2800 2801 mac->hwlro_ip[fsp->location] = 0; 2802 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location; 2803 2804 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2805 2806 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2807 2808 return 0; 2809 } 2810 2811 static void mtk_hwlro_netdev_disable(struct net_device *dev) 2812 { 2813 struct mtk_mac *mac = netdev_priv(dev); 2814 struct mtk_eth *eth = mac->hw; 2815 int i, hwlro_idx; 2816 2817 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2818 mac->hwlro_ip[i] = 0; 2819 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i; 2820 2821 mtk_hwlro_inval_ipaddr(eth, hwlro_idx); 2822 } 2823 2824 mac->hwlro_ip_cnt = 0; 2825 } 2826 2827 static int mtk_hwlro_get_fdir_entry(struct net_device *dev, 2828 struct ethtool_rxnfc *cmd) 2829 { 2830 struct mtk_mac *mac = netdev_priv(dev); 2831 struct ethtool_rx_flow_spec *fsp = 2832 (struct ethtool_rx_flow_spec *)&cmd->fs; 2833 2834 if (fsp->location >= ARRAY_SIZE(mac->hwlro_ip)) 2835 return -EINVAL; 2836 2837 /* only tcp dst ipv4 is meaningful, others are meaningless */ 2838 fsp->flow_type = TCP_V4_FLOW; 2839 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]); 2840 fsp->m_u.tcp_ip4_spec.ip4dst = 0; 2841 2842 fsp->h_u.tcp_ip4_spec.ip4src = 0; 2843 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff; 2844 fsp->h_u.tcp_ip4_spec.psrc = 0; 2845 fsp->m_u.tcp_ip4_spec.psrc = 0xffff; 2846 fsp->h_u.tcp_ip4_spec.pdst = 0; 2847 fsp->m_u.tcp_ip4_spec.pdst = 0xffff; 2848 fsp->h_u.tcp_ip4_spec.tos = 0; 2849 fsp->m_u.tcp_ip4_spec.tos = 0xff; 2850 2851 return 0; 2852 } 2853 2854 static int mtk_hwlro_get_fdir_all(struct net_device *dev, 2855 struct ethtool_rxnfc *cmd, 2856 u32 *rule_locs) 2857 { 2858 struct mtk_mac *mac = netdev_priv(dev); 2859 int cnt = 0; 2860 int i; 2861 2862 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { 2863 if (mac->hwlro_ip[i]) { 2864 rule_locs[cnt] = i; 2865 cnt++; 2866 } 2867 } 2868 2869 cmd->rule_cnt = cnt; 2870 2871 return 0; 2872 } 2873 2874 static netdev_features_t mtk_fix_features(struct net_device *dev, 2875 netdev_features_t features) 2876 { 2877 if (!(features & NETIF_F_LRO)) { 2878 struct mtk_mac *mac = netdev_priv(dev); 2879 int ip_cnt = mtk_hwlro_get_ip_cnt(mac); 2880 2881 if (ip_cnt) { 2882 netdev_info(dev, "RX flow is programmed, LRO should keep on\n"); 2883 2884 features |= NETIF_F_LRO; 2885 } 2886 } 2887 2888 return features; 2889 } 2890 2891 static int mtk_set_features(struct net_device *dev, netdev_features_t features) 2892 { 2893 netdev_features_t diff = dev->features ^ features; 2894 2895 if ((diff & NETIF_F_LRO) && !(features & NETIF_F_LRO)) 2896 mtk_hwlro_netdev_disable(dev); 2897 2898 return 0; 2899 } 2900 2901 /* wait for DMA to finish whatever it is doing before we start using it again */ 2902 static int mtk_dma_busy_wait(struct mtk_eth *eth) 2903 { 2904 unsigned int reg; 2905 int ret; 2906 u32 val; 2907 2908 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 2909 reg = eth->soc->reg_map->qdma.glo_cfg; 2910 else 2911 reg = eth->soc->reg_map->pdma.glo_cfg; 2912 2913 ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val, 2914 !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)), 2915 5, MTK_DMA_BUSY_TIMEOUT_US); 2916 if (ret) 2917 dev_err(eth->dev, "DMA init timeout\n"); 2918 2919 return ret; 2920 } 2921 2922 static int mtk_dma_init(struct mtk_eth *eth) 2923 { 2924 int err; 2925 u32 i; 2926 2927 if (mtk_dma_busy_wait(eth)) 2928 return -EBUSY; 2929 2930 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2931 /* QDMA needs scratch memory for internal reordering of the 2932 * descriptors 2933 */ 2934 err = mtk_init_fq_dma(eth); 2935 if (err) 2936 return err; 2937 } 2938 2939 err = mtk_tx_alloc(eth); 2940 if (err) 2941 return err; 2942 2943 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2944 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA); 2945 if (err) 2946 return err; 2947 } 2948 2949 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL); 2950 if (err) 2951 return err; 2952 2953 if (eth->hwlro) { 2954 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) { 2955 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO); 2956 if (err) 2957 return err; 2958 } 2959 err = mtk_hwlro_rx_init(eth); 2960 if (err) 2961 return err; 2962 } 2963 2964 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 2965 /* Enable random early drop and set drop threshold 2966 * automatically 2967 */ 2968 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | 2969 FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th); 2970 mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred); 2971 } 2972 2973 return 0; 2974 } 2975 2976 static void mtk_dma_free(struct mtk_eth *eth) 2977 { 2978 const struct mtk_soc_data *soc = eth->soc; 2979 int i; 2980 2981 for (i = 0; i < MTK_MAC_COUNT; i++) 2982 if (eth->netdev[i]) 2983 netdev_reset_queue(eth->netdev[i]); 2984 if (eth->scratch_ring) { 2985 dma_free_coherent(eth->dma_dev, 2986 MTK_QDMA_RING_SIZE * soc->txrx.txd_size, 2987 eth->scratch_ring, eth->phy_scratch_ring); 2988 eth->scratch_ring = NULL; 2989 eth->phy_scratch_ring = 0; 2990 } 2991 mtk_tx_clean(eth); 2992 mtk_rx_clean(eth, ð->rx_ring[0]); 2993 mtk_rx_clean(eth, ð->rx_ring_qdma); 2994 2995 if (eth->hwlro) { 2996 mtk_hwlro_rx_uninit(eth); 2997 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) 2998 mtk_rx_clean(eth, ð->rx_ring[i]); 2999 } 3000 3001 kfree(eth->scratch_head); 3002 } 3003 3004 static bool mtk_hw_reset_check(struct mtk_eth *eth) 3005 { 3006 u32 val = mtk_r32(eth, MTK_INT_STATUS2); 3007 3008 return (val & MTK_FE_INT_FQ_EMPTY) || (val & MTK_FE_INT_RFIFO_UF) || 3009 (val & MTK_FE_INT_RFIFO_OV) || (val & MTK_FE_INT_TSO_FAIL) || 3010 (val & MTK_FE_INT_TSO_ALIGN) || (val & MTK_FE_INT_TSO_ILLEGAL); 3011 } 3012 3013 static void mtk_tx_timeout(struct net_device *dev, unsigned int txqueue) 3014 { 3015 struct mtk_mac *mac = netdev_priv(dev); 3016 struct mtk_eth *eth = mac->hw; 3017 3018 if (test_bit(MTK_RESETTING, ð->state)) 3019 return; 3020 3021 if (!mtk_hw_reset_check(eth)) 3022 return; 3023 3024 eth->netdev[mac->id]->stats.tx_errors++; 3025 netif_err(eth, tx_err, dev, "transmit timed out\n"); 3026 3027 schedule_work(ð->pending_work); 3028 } 3029 3030 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth) 3031 { 3032 struct mtk_eth *eth = _eth; 3033 3034 eth->rx_events++; 3035 if (likely(napi_schedule_prep(ð->rx_napi))) { 3036 __napi_schedule(ð->rx_napi); 3037 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3038 } 3039 3040 return IRQ_HANDLED; 3041 } 3042 3043 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth) 3044 { 3045 struct mtk_eth *eth = _eth; 3046 3047 eth->tx_events++; 3048 if (likely(napi_schedule_prep(ð->tx_napi))) { 3049 __napi_schedule(ð->tx_napi); 3050 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3051 } 3052 3053 return IRQ_HANDLED; 3054 } 3055 3056 static irqreturn_t mtk_handle_irq(int irq, void *_eth) 3057 { 3058 struct mtk_eth *eth = _eth; 3059 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3060 3061 if (mtk_r32(eth, reg_map->pdma.irq_mask) & 3062 eth->soc->txrx.rx_irq_done_mask) { 3063 if (mtk_r32(eth, reg_map->pdma.irq_status) & 3064 eth->soc->txrx.rx_irq_done_mask) 3065 mtk_handle_irq_rx(irq, _eth); 3066 } 3067 if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) { 3068 if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT) 3069 mtk_handle_irq_tx(irq, _eth); 3070 } 3071 3072 return IRQ_HANDLED; 3073 } 3074 3075 #ifdef CONFIG_NET_POLL_CONTROLLER 3076 static void mtk_poll_controller(struct net_device *dev) 3077 { 3078 struct mtk_mac *mac = netdev_priv(dev); 3079 struct mtk_eth *eth = mac->hw; 3080 3081 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3082 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3083 mtk_handle_irq_rx(eth->irq[2], dev); 3084 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3085 mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask); 3086 } 3087 #endif 3088 3089 static int mtk_start_dma(struct mtk_eth *eth) 3090 { 3091 u32 val, rx_2b_offset = (NET_IP_ALIGN == 2) ? MTK_RX_2B_OFFSET : 0; 3092 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3093 int err; 3094 3095 err = mtk_dma_init(eth); 3096 if (err) { 3097 mtk_dma_free(eth); 3098 return err; 3099 } 3100 3101 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 3102 val = mtk_r32(eth, reg_map->qdma.glo_cfg); 3103 val |= MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3104 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3105 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3106 3107 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3108 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3109 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3110 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; 3111 else 3112 val |= MTK_RX_BT_32DWORDS; 3113 mtk_w32(eth, val, reg_map->qdma.glo_cfg); 3114 3115 mtk_w32(eth, 3116 MTK_RX_DMA_EN | rx_2b_offset | 3117 MTK_RX_BT_32DWORDS | MTK_MULTI_EN, 3118 reg_map->pdma.glo_cfg); 3119 } else { 3120 mtk_w32(eth, MTK_TX_WB_DDONE | MTK_TX_DMA_EN | MTK_RX_DMA_EN | 3121 MTK_MULTI_EN | MTK_PDMA_SIZE_8DWORDS, 3122 reg_map->pdma.glo_cfg); 3123 } 3124 3125 return 0; 3126 } 3127 3128 static void mtk_gdm_config(struct mtk_eth *eth, u32 config) 3129 { 3130 int i; 3131 3132 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3133 return; 3134 3135 for (i = 0; i < MTK_MAC_COUNT; i++) { 3136 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3137 3138 /* default setup the forward port to send frame to PDMA */ 3139 val &= ~0xffff; 3140 3141 /* Enable RX checksum */ 3142 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN; 3143 3144 val |= config; 3145 3146 if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) 3147 val |= MTK_GDMA_SPECIAL_TAG; 3148 3149 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); 3150 } 3151 /* Reset and enable PSE */ 3152 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL); 3153 mtk_w32(eth, 0, MTK_RST_GL); 3154 } 3155 3156 3157 static bool mtk_uses_dsa(struct net_device *dev) 3158 { 3159 #if IS_ENABLED(CONFIG_NET_DSA) 3160 return netdev_uses_dsa(dev) && 3161 dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK; 3162 #else 3163 return false; 3164 #endif 3165 } 3166 3167 static int mtk_device_event(struct notifier_block *n, unsigned long event, void *ptr) 3168 { 3169 struct mtk_mac *mac = container_of(n, struct mtk_mac, device_notifier); 3170 struct mtk_eth *eth = mac->hw; 3171 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3172 struct ethtool_link_ksettings s; 3173 struct net_device *ldev; 3174 struct list_head *iter; 3175 struct dsa_port *dp; 3176 3177 if (event != NETDEV_CHANGE) 3178 return NOTIFY_DONE; 3179 3180 netdev_for_each_lower_dev(dev, ldev, iter) { 3181 if (netdev_priv(ldev) == mac) 3182 goto found; 3183 } 3184 3185 return NOTIFY_DONE; 3186 3187 found: 3188 if (!dsa_slave_dev_check(dev)) 3189 return NOTIFY_DONE; 3190 3191 if (__ethtool_get_link_ksettings(dev, &s)) 3192 return NOTIFY_DONE; 3193 3194 if (s.base.speed == 0 || s.base.speed == ((__u32)-1)) 3195 return NOTIFY_DONE; 3196 3197 dp = dsa_port_from_netdev(dev); 3198 if (dp->index >= MTK_QDMA_NUM_QUEUES) 3199 return NOTIFY_DONE; 3200 3201 if (mac->speed > 0 && mac->speed <= s.base.speed) 3202 s.base.speed = 0; 3203 3204 mtk_set_queue_speed(eth, dp->index + 3, s.base.speed); 3205 3206 return NOTIFY_DONE; 3207 } 3208 3209 static int mtk_open(struct net_device *dev) 3210 { 3211 struct mtk_mac *mac = netdev_priv(dev); 3212 struct mtk_eth *eth = mac->hw; 3213 int i, err; 3214 3215 err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0); 3216 if (err) { 3217 netdev_err(dev, "%s: could not attach PHY: %d\n", __func__, 3218 err); 3219 return err; 3220 } 3221 3222 /* we run 2 netdevs on the same dma ring so we only bring it up once */ 3223 if (!refcount_read(ð->dma_refcnt)) { 3224 const struct mtk_soc_data *soc = eth->soc; 3225 u32 gdm_config; 3226 int i; 3227 3228 err = mtk_start_dma(eth); 3229 if (err) { 3230 phylink_disconnect_phy(mac->phylink); 3231 return err; 3232 } 3233 3234 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3235 mtk_ppe_start(eth->ppe[i]); 3236 3237 gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe 3238 : MTK_GDMA_TO_PDMA; 3239 mtk_gdm_config(eth, gdm_config); 3240 3241 napi_enable(ð->tx_napi); 3242 napi_enable(ð->rx_napi); 3243 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT); 3244 mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask); 3245 refcount_set(ð->dma_refcnt, 1); 3246 } 3247 else 3248 refcount_inc(ð->dma_refcnt); 3249 3250 phylink_start(mac->phylink); 3251 netif_tx_start_all_queues(dev); 3252 3253 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3254 return 0; 3255 3256 if (mtk_uses_dsa(dev) && !eth->prog) { 3257 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 3258 struct metadata_dst *md_dst = eth->dsa_meta[i]; 3259 3260 if (md_dst) 3261 continue; 3262 3263 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 3264 GFP_KERNEL); 3265 if (!md_dst) 3266 return -ENOMEM; 3267 3268 md_dst->u.port_info.port_id = i; 3269 eth->dsa_meta[i] = md_dst; 3270 } 3271 } else { 3272 /* Hardware special tag parsing needs to be disabled if at least 3273 * one MAC does not use DSA. 3274 */ 3275 u32 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3276 3277 val &= ~MTK_CDMP_STAG_EN; 3278 mtk_w32(eth, val, MTK_CDMP_IG_CTRL); 3279 3280 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3281 val &= ~MTK_CDMQ_STAG_EN; 3282 mtk_w32(eth, val, MTK_CDMQ_IG_CTRL); 3283 3284 mtk_w32(eth, 0, MTK_CDMP_EG_CTRL); 3285 } 3286 3287 return 0; 3288 } 3289 3290 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg) 3291 { 3292 u32 val; 3293 int i; 3294 3295 /* stop the dma engine */ 3296 spin_lock_bh(ð->page_lock); 3297 val = mtk_r32(eth, glo_cfg); 3298 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN), 3299 glo_cfg); 3300 spin_unlock_bh(ð->page_lock); 3301 3302 /* wait for dma stop */ 3303 for (i = 0; i < 10; i++) { 3304 val = mtk_r32(eth, glo_cfg); 3305 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) { 3306 msleep(20); 3307 continue; 3308 } 3309 break; 3310 } 3311 } 3312 3313 static int mtk_stop(struct net_device *dev) 3314 { 3315 struct mtk_mac *mac = netdev_priv(dev); 3316 struct mtk_eth *eth = mac->hw; 3317 int i; 3318 3319 phylink_stop(mac->phylink); 3320 3321 netif_tx_disable(dev); 3322 3323 phylink_disconnect_phy(mac->phylink); 3324 3325 /* only shutdown DMA if this is the last user */ 3326 if (!refcount_dec_and_test(ð->dma_refcnt)) 3327 return 0; 3328 3329 mtk_gdm_config(eth, MTK_GDMA_DROP_ALL); 3330 3331 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT); 3332 mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask); 3333 napi_disable(ð->tx_napi); 3334 napi_disable(ð->rx_napi); 3335 3336 cancel_work_sync(ð->rx_dim.work); 3337 cancel_work_sync(ð->tx_dim.work); 3338 3339 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3340 mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg); 3341 mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg); 3342 3343 mtk_dma_free(eth); 3344 3345 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3346 mtk_ppe_stop(eth->ppe[i]); 3347 3348 return 0; 3349 } 3350 3351 static int mtk_xdp_setup(struct net_device *dev, struct bpf_prog *prog, 3352 struct netlink_ext_ack *extack) 3353 { 3354 struct mtk_mac *mac = netdev_priv(dev); 3355 struct mtk_eth *eth = mac->hw; 3356 struct bpf_prog *old_prog; 3357 bool need_update; 3358 3359 if (eth->hwlro) { 3360 NL_SET_ERR_MSG_MOD(extack, "XDP not supported with HWLRO"); 3361 return -EOPNOTSUPP; 3362 } 3363 3364 if (dev->mtu > MTK_PP_MAX_BUF_SIZE) { 3365 NL_SET_ERR_MSG_MOD(extack, "MTU too large for XDP"); 3366 return -EOPNOTSUPP; 3367 } 3368 3369 need_update = !!eth->prog != !!prog; 3370 if (netif_running(dev) && need_update) 3371 mtk_stop(dev); 3372 3373 old_prog = rcu_replace_pointer(eth->prog, prog, lockdep_rtnl_is_held()); 3374 if (old_prog) 3375 bpf_prog_put(old_prog); 3376 3377 if (netif_running(dev) && need_update) 3378 return mtk_open(dev); 3379 3380 return 0; 3381 } 3382 3383 static int mtk_xdp(struct net_device *dev, struct netdev_bpf *xdp) 3384 { 3385 switch (xdp->command) { 3386 case XDP_SETUP_PROG: 3387 return mtk_xdp_setup(dev, xdp->prog, xdp->extack); 3388 default: 3389 return -EINVAL; 3390 } 3391 } 3392 3393 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits) 3394 { 3395 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3396 reset_bits, 3397 reset_bits); 3398 3399 usleep_range(1000, 1100); 3400 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, 3401 reset_bits, 3402 ~reset_bits); 3403 mdelay(10); 3404 } 3405 3406 static void mtk_clk_disable(struct mtk_eth *eth) 3407 { 3408 int clk; 3409 3410 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--) 3411 clk_disable_unprepare(eth->clks[clk]); 3412 } 3413 3414 static int mtk_clk_enable(struct mtk_eth *eth) 3415 { 3416 int clk, ret; 3417 3418 for (clk = 0; clk < MTK_CLK_MAX ; clk++) { 3419 ret = clk_prepare_enable(eth->clks[clk]); 3420 if (ret) 3421 goto err_disable_clks; 3422 } 3423 3424 return 0; 3425 3426 err_disable_clks: 3427 while (--clk >= 0) 3428 clk_disable_unprepare(eth->clks[clk]); 3429 3430 return ret; 3431 } 3432 3433 static void mtk_dim_rx(struct work_struct *work) 3434 { 3435 struct dim *dim = container_of(work, struct dim, work); 3436 struct mtk_eth *eth = container_of(dim, struct mtk_eth, rx_dim); 3437 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3438 struct dim_cq_moder cur_profile; 3439 u32 val, cur; 3440 3441 cur_profile = net_dim_get_rx_moderation(eth->rx_dim.mode, 3442 dim->profile_ix); 3443 spin_lock_bh(ð->dim_lock); 3444 3445 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3446 val &= MTK_PDMA_DELAY_TX_MASK; 3447 val |= MTK_PDMA_DELAY_RX_EN; 3448 3449 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3450 val |= cur << MTK_PDMA_DELAY_RX_PTIME_SHIFT; 3451 3452 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3453 val |= cur << MTK_PDMA_DELAY_RX_PINT_SHIFT; 3454 3455 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3456 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3457 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3458 3459 spin_unlock_bh(ð->dim_lock); 3460 3461 dim->state = DIM_START_MEASURE; 3462 } 3463 3464 static void mtk_dim_tx(struct work_struct *work) 3465 { 3466 struct dim *dim = container_of(work, struct dim, work); 3467 struct mtk_eth *eth = container_of(dim, struct mtk_eth, tx_dim); 3468 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3469 struct dim_cq_moder cur_profile; 3470 u32 val, cur; 3471 3472 cur_profile = net_dim_get_tx_moderation(eth->tx_dim.mode, 3473 dim->profile_ix); 3474 spin_lock_bh(ð->dim_lock); 3475 3476 val = mtk_r32(eth, reg_map->pdma.delay_irq); 3477 val &= MTK_PDMA_DELAY_RX_MASK; 3478 val |= MTK_PDMA_DELAY_TX_EN; 3479 3480 cur = min_t(u32, DIV_ROUND_UP(cur_profile.usec, 20), MTK_PDMA_DELAY_PTIME_MASK); 3481 val |= cur << MTK_PDMA_DELAY_TX_PTIME_SHIFT; 3482 3483 cur = min_t(u32, cur_profile.pkts, MTK_PDMA_DELAY_PINT_MASK); 3484 val |= cur << MTK_PDMA_DELAY_TX_PINT_SHIFT; 3485 3486 mtk_w32(eth, val, reg_map->pdma.delay_irq); 3487 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 3488 mtk_w32(eth, val, reg_map->qdma.delay_irq); 3489 3490 spin_unlock_bh(ð->dim_lock); 3491 3492 dim->state = DIM_START_MEASURE; 3493 } 3494 3495 static void mtk_set_mcr_max_rx(struct mtk_mac *mac, u32 val) 3496 { 3497 struct mtk_eth *eth = mac->hw; 3498 u32 mcr_cur, mcr_new; 3499 3500 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3501 return; 3502 3503 mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); 3504 mcr_new = mcr_cur & ~MAC_MCR_MAX_RX_MASK; 3505 3506 if (val <= 1518) 3507 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1518); 3508 else if (val <= 1536) 3509 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1536); 3510 else if (val <= 1552) 3511 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_1552); 3512 else 3513 mcr_new |= MAC_MCR_MAX_RX(MAC_MCR_MAX_RX_2048); 3514 3515 if (mcr_new != mcr_cur) 3516 mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id)); 3517 } 3518 3519 static void mtk_hw_reset(struct mtk_eth *eth) 3520 { 3521 u32 val; 3522 3523 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3524 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3525 val = RSTCTRL_PPE0_V2; 3526 } else { 3527 val = RSTCTRL_PPE0; 3528 } 3529 3530 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3531 val |= RSTCTRL_PPE1; 3532 3533 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3534 3535 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3536 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3537 0x3ffffff); 3538 } 3539 3540 static u32 mtk_hw_reset_read(struct mtk_eth *eth) 3541 { 3542 u32 val; 3543 3544 regmap_read(eth->ethsys, ETHSYS_RSTCTRL, &val); 3545 return val; 3546 } 3547 3548 static void mtk_hw_warm_reset(struct mtk_eth *eth) 3549 { 3550 u32 rst_mask, val; 3551 3552 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, RSTCTRL_FE, 3553 RSTCTRL_FE); 3554 if (readx_poll_timeout_atomic(mtk_hw_reset_read, eth, val, 3555 val & RSTCTRL_FE, 1, 1000)) { 3556 dev_err(eth->dev, "warm reset failed\n"); 3557 mtk_hw_reset(eth); 3558 return; 3559 } 3560 3561 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3562 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3563 else 3564 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; 3565 3566 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3567 rst_mask |= RSTCTRL_PPE1; 3568 3569 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask); 3570 3571 udelay(1); 3572 val = mtk_hw_reset_read(eth); 3573 if (!(val & rst_mask)) 3574 dev_err(eth->dev, "warm reset stage0 failed %08x (%08x)\n", 3575 val, rst_mask); 3576 3577 rst_mask |= RSTCTRL_FE; 3578 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, ~rst_mask); 3579 3580 udelay(1); 3581 val = mtk_hw_reset_read(eth); 3582 if (val & rst_mask) 3583 dev_err(eth->dev, "warm reset stage1 failed %08x (%08x)\n", 3584 val, rst_mask); 3585 } 3586 3587 static bool mtk_hw_check_dma_hang(struct mtk_eth *eth) 3588 { 3589 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3590 bool gmac1_tx, gmac2_tx, gdm1_tx, gdm2_tx; 3591 bool oq_hang, cdm1_busy, adma_busy; 3592 bool wtx_busy, cdm_full, oq_free; 3593 u32 wdidx, val, gdm1_fc, gdm2_fc; 3594 bool qfsm_hang, qfwd_hang; 3595 bool ret = false; 3596 3597 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3598 return false; 3599 3600 /* WDMA sanity checks */ 3601 wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc); 3602 3603 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204); 3604 wtx_busy = FIELD_GET(MTK_TX_DMA_BUSY, val); 3605 3606 val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230); 3607 cdm_full = !FIELD_GET(MTK_CDM_TXFIFO_RDY, val); 3608 3609 oq_free = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) && 3610 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) && 3611 !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16))); 3612 3613 if (wdidx == eth->reset.wdidx && wtx_busy && cdm_full && oq_free) { 3614 if (++eth->reset.wdma_hang_count > 2) { 3615 eth->reset.wdma_hang_count = 0; 3616 ret = true; 3617 } 3618 goto out; 3619 } 3620 3621 /* QDMA sanity checks */ 3622 qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234); 3623 qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308); 3624 3625 gdm1_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM1_FSM)) > 0; 3626 gdm2_tx = FIELD_GET(GENMASK(31, 16), mtk_r32(eth, MTK_FE_GDM2_FSM)) > 0; 3627 gmac1_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(0))) != 1; 3628 gmac2_tx = FIELD_GET(GENMASK(31, 24), mtk_r32(eth, MTK_MAC_FSM(1))) != 1; 3629 gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24); 3630 gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64); 3631 3632 if (qfsm_hang && qfwd_hang && 3633 ((gdm1_tx && gmac1_tx && gdm1_fc < 1) || 3634 (gdm2_tx && gmac2_tx && gdm2_fc < 1))) { 3635 if (++eth->reset.qdma_hang_count > 2) { 3636 eth->reset.qdma_hang_count = 0; 3637 ret = true; 3638 } 3639 goto out; 3640 } 3641 3642 /* ADMA sanity checks */ 3643 oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0)); 3644 cdm1_busy = !!(mtk_r32(eth, MTK_FE_CDM1_FSM) & GENMASK(31, 16)); 3645 adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) && 3646 !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6)); 3647 3648 if (oq_hang && cdm1_busy && adma_busy) { 3649 if (++eth->reset.adma_hang_count > 2) { 3650 eth->reset.adma_hang_count = 0; 3651 ret = true; 3652 } 3653 goto out; 3654 } 3655 3656 eth->reset.wdma_hang_count = 0; 3657 eth->reset.qdma_hang_count = 0; 3658 eth->reset.adma_hang_count = 0; 3659 out: 3660 eth->reset.wdidx = wdidx; 3661 3662 return ret; 3663 } 3664 3665 static void mtk_hw_reset_monitor_work(struct work_struct *work) 3666 { 3667 struct delayed_work *del_work = to_delayed_work(work); 3668 struct mtk_eth *eth = container_of(del_work, struct mtk_eth, 3669 reset.monitor_work); 3670 3671 if (test_bit(MTK_RESETTING, ð->state)) 3672 goto out; 3673 3674 /* DMA stuck checks */ 3675 if (mtk_hw_check_dma_hang(eth)) 3676 schedule_work(ð->pending_work); 3677 3678 out: 3679 schedule_delayed_work(ð->reset.monitor_work, 3680 MTK_DMA_MONITOR_TIMEOUT); 3681 } 3682 3683 static int mtk_hw_init(struct mtk_eth *eth, bool reset) 3684 { 3685 u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA | 3686 ETHSYS_DMA_AG_MAP_PPE; 3687 const struct mtk_reg_map *reg_map = eth->soc->reg_map; 3688 int i, val, ret; 3689 3690 if (!reset && test_and_set_bit(MTK_HW_INIT, ð->state)) 3691 return 0; 3692 3693 if (!reset) { 3694 pm_runtime_enable(eth->dev); 3695 pm_runtime_get_sync(eth->dev); 3696 3697 ret = mtk_clk_enable(eth); 3698 if (ret) 3699 goto err_disable_pm; 3700 } 3701 3702 if (eth->ethsys) 3703 regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask, 3704 of_dma_is_coherent(eth->dma_dev->of_node) * dma_mask); 3705 3706 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 3707 ret = device_reset(eth->dev); 3708 if (ret) { 3709 dev_err(eth->dev, "MAC reset failed!\n"); 3710 goto err_disable_pm; 3711 } 3712 3713 /* set interrupt delays based on current Net DIM sample */ 3714 mtk_dim_rx(ð->rx_dim.work); 3715 mtk_dim_tx(ð->tx_dim.work); 3716 3717 /* disable delay and normal interrupt */ 3718 mtk_tx_irq_disable(eth, ~0); 3719 mtk_rx_irq_disable(eth, ~0); 3720 3721 return 0; 3722 } 3723 3724 msleep(100); 3725 3726 if (reset) 3727 mtk_hw_warm_reset(eth); 3728 else 3729 mtk_hw_reset(eth); 3730 3731 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3732 /* Set FE to PDMAv2 if necessary */ 3733 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3734 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); 3735 } 3736 3737 if (eth->pctl) { 3738 /* Set GE2 driving and slew rate */ 3739 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00); 3740 3741 /* set GE2 TDSEL */ 3742 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5); 3743 3744 /* set GE2 TUNE */ 3745 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0); 3746 } 3747 3748 /* Set linkdown as the default for each GMAC. Its own MCR would be set 3749 * up with the more appropriate value when mtk_mac_config call is being 3750 * invoked. 3751 */ 3752 for (i = 0; i < MTK_MAC_COUNT; i++) { 3753 struct net_device *dev = eth->netdev[i]; 3754 3755 mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3756 if (dev) { 3757 struct mtk_mac *mac = netdev_priv(dev); 3758 3759 mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3760 } 3761 } 3762 3763 /* Indicates CDM to parse the MTK special tag from CPU 3764 * which also is working out for untag packets. 3765 */ 3766 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3767 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3768 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3769 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3770 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3771 3772 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL); 3773 } 3774 3775 /* set interrupt delays based on current Net DIM sample */ 3776 mtk_dim_rx(ð->rx_dim.work); 3777 mtk_dim_tx(ð->tx_dim.work); 3778 3779 /* disable delay and normal interrupt */ 3780 mtk_tx_irq_disable(eth, ~0); 3781 mtk_rx_irq_disable(eth, ~0); 3782 3783 /* FE int grouping */ 3784 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp); 3785 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4); 3786 mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp); 3787 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3788 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3789 3790 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3791 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3792 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3793 3794 /* PSE should drop packets to port 8/9 on WDMA Rx ring full */ 3795 mtk_w32(eth, 0x00000300, PSE_PPE0_DROP); 3796 3797 /* PSE Free Queue Flow Control */ 3798 mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2); 3799 3800 /* PSE config input queue threshold */ 3801 mtk_w32(eth, 0x001a000e, PSE_IQ_REV(1)); 3802 mtk_w32(eth, 0x01ff001a, PSE_IQ_REV(2)); 3803 mtk_w32(eth, 0x000e01ff, PSE_IQ_REV(3)); 3804 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(4)); 3805 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(5)); 3806 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(6)); 3807 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(7)); 3808 mtk_w32(eth, 0x000e000e, PSE_IQ_REV(8)); 3809 3810 /* PSE config output queue threshold */ 3811 mtk_w32(eth, 0x000f000a, PSE_OQ_TH(1)); 3812 mtk_w32(eth, 0x001a000f, PSE_OQ_TH(2)); 3813 mtk_w32(eth, 0x000f001a, PSE_OQ_TH(3)); 3814 mtk_w32(eth, 0x01ff000f, PSE_OQ_TH(4)); 3815 mtk_w32(eth, 0x000f000f, PSE_OQ_TH(5)); 3816 mtk_w32(eth, 0x0006000f, PSE_OQ_TH(6)); 3817 mtk_w32(eth, 0x00060006, PSE_OQ_TH(7)); 3818 mtk_w32(eth, 0x00060006, PSE_OQ_TH(8)); 3819 3820 /* GDM and CDM Threshold */ 3821 mtk_w32(eth, 0x00000004, MTK_GDM2_THRES); 3822 mtk_w32(eth, 0x00000004, MTK_CDMW0_THRES); 3823 mtk_w32(eth, 0x00000004, MTK_CDMW1_THRES); 3824 mtk_w32(eth, 0x00000004, MTK_CDME0_THRES); 3825 mtk_w32(eth, 0x00000004, MTK_CDME1_THRES); 3826 mtk_w32(eth, 0x00000004, MTK_CDMM_THRES); 3827 } 3828 3829 return 0; 3830 3831 err_disable_pm: 3832 if (!reset) { 3833 pm_runtime_put_sync(eth->dev); 3834 pm_runtime_disable(eth->dev); 3835 } 3836 3837 return ret; 3838 } 3839 3840 static int mtk_hw_deinit(struct mtk_eth *eth) 3841 { 3842 if (!test_and_clear_bit(MTK_HW_INIT, ð->state)) 3843 return 0; 3844 3845 mtk_clk_disable(eth); 3846 3847 pm_runtime_put_sync(eth->dev); 3848 pm_runtime_disable(eth->dev); 3849 3850 return 0; 3851 } 3852 3853 static int __init mtk_init(struct net_device *dev) 3854 { 3855 struct mtk_mac *mac = netdev_priv(dev); 3856 struct mtk_eth *eth = mac->hw; 3857 int ret; 3858 3859 ret = of_get_ethdev_address(mac->of_node, dev); 3860 if (ret) { 3861 /* If the mac address is invalid, use random mac address */ 3862 eth_hw_addr_random(dev); 3863 dev_err(eth->dev, "generated random MAC address %pM\n", 3864 dev->dev_addr); 3865 } 3866 3867 return 0; 3868 } 3869 3870 static void mtk_uninit(struct net_device *dev) 3871 { 3872 struct mtk_mac *mac = netdev_priv(dev); 3873 struct mtk_eth *eth = mac->hw; 3874 3875 phylink_disconnect_phy(mac->phylink); 3876 mtk_tx_irq_disable(eth, ~0); 3877 mtk_rx_irq_disable(eth, ~0); 3878 } 3879 3880 static int mtk_change_mtu(struct net_device *dev, int new_mtu) 3881 { 3882 int length = new_mtu + MTK_RX_ETH_HLEN; 3883 struct mtk_mac *mac = netdev_priv(dev); 3884 struct mtk_eth *eth = mac->hw; 3885 3886 if (rcu_access_pointer(eth->prog) && 3887 length > MTK_PP_MAX_BUF_SIZE) { 3888 netdev_err(dev, "Invalid MTU for XDP mode\n"); 3889 return -EINVAL; 3890 } 3891 3892 mtk_set_mcr_max_rx(mac, length); 3893 dev->mtu = new_mtu; 3894 3895 return 0; 3896 } 3897 3898 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 3899 { 3900 struct mtk_mac *mac = netdev_priv(dev); 3901 3902 switch (cmd) { 3903 case SIOCGMIIPHY: 3904 case SIOCGMIIREG: 3905 case SIOCSMIIREG: 3906 return phylink_mii_ioctl(mac->phylink, ifr, cmd); 3907 default: 3908 break; 3909 } 3910 3911 return -EOPNOTSUPP; 3912 } 3913 3914 static void mtk_prepare_for_reset(struct mtk_eth *eth) 3915 { 3916 u32 val; 3917 int i; 3918 3919 /* disabe FE P3 and P4 */ 3920 val = mtk_r32(eth, MTK_FE_GLO_CFG) | MTK_FE_LINK_DOWN_P3; 3921 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3922 val |= MTK_FE_LINK_DOWN_P4; 3923 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3924 3925 /* adjust PPE configurations to prepare for reset */ 3926 for (i = 0; i < ARRAY_SIZE(eth->ppe); i++) 3927 mtk_ppe_prepare_reset(eth->ppe[i]); 3928 3929 /* disable NETSYS interrupts */ 3930 mtk_w32(eth, 0, MTK_FE_INT_ENABLE); 3931 3932 /* force link down GMAC */ 3933 for (i = 0; i < 2; i++) { 3934 val = mtk_r32(eth, MTK_MAC_MCR(i)) & ~MAC_MCR_FORCE_LINK; 3935 mtk_w32(eth, val, MTK_MAC_MCR(i)); 3936 } 3937 } 3938 3939 static void mtk_pending_work(struct work_struct *work) 3940 { 3941 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work); 3942 unsigned long restart = 0; 3943 u32 val; 3944 int i; 3945 3946 rtnl_lock(); 3947 set_bit(MTK_RESETTING, ð->state); 3948 3949 mtk_prepare_for_reset(eth); 3950 mtk_wed_fe_reset(); 3951 /* Run again reset preliminary configuration in order to avoid any 3952 * possible race during FE reset since it can run releasing RTNL lock. 3953 */ 3954 mtk_prepare_for_reset(eth); 3955 3956 /* stop all devices to make sure that dma is properly shut down */ 3957 for (i = 0; i < MTK_MAC_COUNT; i++) { 3958 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 3959 continue; 3960 3961 mtk_stop(eth->netdev[i]); 3962 __set_bit(i, &restart); 3963 } 3964 3965 usleep_range(15000, 16000); 3966 3967 if (eth->dev->pins) 3968 pinctrl_select_state(eth->dev->pins->p, 3969 eth->dev->pins->default_state); 3970 mtk_hw_init(eth, true); 3971 3972 /* restart DMA and enable IRQs */ 3973 for (i = 0; i < MTK_MAC_COUNT; i++) { 3974 if (!test_bit(i, &restart)) 3975 continue; 3976 3977 if (mtk_open(eth->netdev[i])) { 3978 netif_alert(eth, ifup, eth->netdev[i], 3979 "Driver up/down cycle failed\n"); 3980 dev_close(eth->netdev[i]); 3981 } 3982 } 3983 3984 /* enabe FE P3 and P4 */ 3985 val = mtk_r32(eth, MTK_FE_GLO_CFG) & ~MTK_FE_LINK_DOWN_P3; 3986 if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1)) 3987 val &= ~MTK_FE_LINK_DOWN_P4; 3988 mtk_w32(eth, val, MTK_FE_GLO_CFG); 3989 3990 clear_bit(MTK_RESETTING, ð->state); 3991 3992 mtk_wed_fe_reset_complete(); 3993 3994 rtnl_unlock(); 3995 } 3996 3997 static int mtk_free_dev(struct mtk_eth *eth) 3998 { 3999 int i; 4000 4001 for (i = 0; i < MTK_MAC_COUNT; i++) { 4002 if (!eth->netdev[i]) 4003 continue; 4004 free_netdev(eth->netdev[i]); 4005 } 4006 4007 for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) { 4008 if (!eth->dsa_meta[i]) 4009 break; 4010 metadata_dst_free(eth->dsa_meta[i]); 4011 } 4012 4013 return 0; 4014 } 4015 4016 static int mtk_unreg_dev(struct mtk_eth *eth) 4017 { 4018 int i; 4019 4020 for (i = 0; i < MTK_MAC_COUNT; i++) { 4021 struct mtk_mac *mac; 4022 if (!eth->netdev[i]) 4023 continue; 4024 mac = netdev_priv(eth->netdev[i]); 4025 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4026 unregister_netdevice_notifier(&mac->device_notifier); 4027 unregister_netdev(eth->netdev[i]); 4028 } 4029 4030 return 0; 4031 } 4032 4033 static void mtk_sgmii_destroy(struct mtk_eth *eth) 4034 { 4035 int i; 4036 4037 for (i = 0; i < MTK_MAX_DEVS; i++) 4038 mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); 4039 } 4040 4041 static int mtk_cleanup(struct mtk_eth *eth) 4042 { 4043 mtk_sgmii_destroy(eth); 4044 mtk_unreg_dev(eth); 4045 mtk_free_dev(eth); 4046 cancel_work_sync(ð->pending_work); 4047 cancel_delayed_work_sync(ð->reset.monitor_work); 4048 4049 return 0; 4050 } 4051 4052 static int mtk_get_link_ksettings(struct net_device *ndev, 4053 struct ethtool_link_ksettings *cmd) 4054 { 4055 struct mtk_mac *mac = netdev_priv(ndev); 4056 4057 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4058 return -EBUSY; 4059 4060 return phylink_ethtool_ksettings_get(mac->phylink, cmd); 4061 } 4062 4063 static int mtk_set_link_ksettings(struct net_device *ndev, 4064 const struct ethtool_link_ksettings *cmd) 4065 { 4066 struct mtk_mac *mac = netdev_priv(ndev); 4067 4068 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4069 return -EBUSY; 4070 4071 return phylink_ethtool_ksettings_set(mac->phylink, cmd); 4072 } 4073 4074 static void mtk_get_drvinfo(struct net_device *dev, 4075 struct ethtool_drvinfo *info) 4076 { 4077 struct mtk_mac *mac = netdev_priv(dev); 4078 4079 strscpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver)); 4080 strscpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info)); 4081 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats); 4082 } 4083 4084 static u32 mtk_get_msglevel(struct net_device *dev) 4085 { 4086 struct mtk_mac *mac = netdev_priv(dev); 4087 4088 return mac->hw->msg_enable; 4089 } 4090 4091 static void mtk_set_msglevel(struct net_device *dev, u32 value) 4092 { 4093 struct mtk_mac *mac = netdev_priv(dev); 4094 4095 mac->hw->msg_enable = value; 4096 } 4097 4098 static int mtk_nway_reset(struct net_device *dev) 4099 { 4100 struct mtk_mac *mac = netdev_priv(dev); 4101 4102 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4103 return -EBUSY; 4104 4105 if (!mac->phylink) 4106 return -ENOTSUPP; 4107 4108 return phylink_ethtool_nway_reset(mac->phylink); 4109 } 4110 4111 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4112 { 4113 int i; 4114 4115 switch (stringset) { 4116 case ETH_SS_STATS: { 4117 struct mtk_mac *mac = netdev_priv(dev); 4118 4119 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) { 4120 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN); 4121 data += ETH_GSTRING_LEN; 4122 } 4123 if (mtk_page_pool_enabled(mac->hw)) 4124 page_pool_ethtool_stats_get_strings(data); 4125 break; 4126 } 4127 default: 4128 break; 4129 } 4130 } 4131 4132 static int mtk_get_sset_count(struct net_device *dev, int sset) 4133 { 4134 switch (sset) { 4135 case ETH_SS_STATS: { 4136 int count = ARRAY_SIZE(mtk_ethtool_stats); 4137 struct mtk_mac *mac = netdev_priv(dev); 4138 4139 if (mtk_page_pool_enabled(mac->hw)) 4140 count += page_pool_ethtool_stats_get_count(); 4141 return count; 4142 } 4143 default: 4144 return -EOPNOTSUPP; 4145 } 4146 } 4147 4148 static void mtk_ethtool_pp_stats(struct mtk_eth *eth, u64 *data) 4149 { 4150 struct page_pool_stats stats = {}; 4151 int i; 4152 4153 for (i = 0; i < ARRAY_SIZE(eth->rx_ring); i++) { 4154 struct mtk_rx_ring *ring = ð->rx_ring[i]; 4155 4156 if (!ring->page_pool) 4157 continue; 4158 4159 page_pool_get_stats(ring->page_pool, &stats); 4160 } 4161 page_pool_ethtool_stats_get(data, &stats); 4162 } 4163 4164 static void mtk_get_ethtool_stats(struct net_device *dev, 4165 struct ethtool_stats *stats, u64 *data) 4166 { 4167 struct mtk_mac *mac = netdev_priv(dev); 4168 struct mtk_hw_stats *hwstats = mac->hw_stats; 4169 u64 *data_src, *data_dst; 4170 unsigned int start; 4171 int i; 4172 4173 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state))) 4174 return; 4175 4176 if (netif_running(dev) && netif_device_present(dev)) { 4177 if (spin_trylock_bh(&hwstats->stats_lock)) { 4178 mtk_stats_update_mac(mac); 4179 spin_unlock_bh(&hwstats->stats_lock); 4180 } 4181 } 4182 4183 data_src = (u64 *)hwstats; 4184 4185 do { 4186 data_dst = data; 4187 start = u64_stats_fetch_begin(&hwstats->syncp); 4188 4189 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) 4190 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset); 4191 if (mtk_page_pool_enabled(mac->hw)) 4192 mtk_ethtool_pp_stats(mac->hw, data_dst); 4193 } while (u64_stats_fetch_retry(&hwstats->syncp, start)); 4194 } 4195 4196 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 4197 u32 *rule_locs) 4198 { 4199 int ret = -EOPNOTSUPP; 4200 4201 switch (cmd->cmd) { 4202 case ETHTOOL_GRXRINGS: 4203 if (dev->hw_features & NETIF_F_LRO) { 4204 cmd->data = MTK_MAX_RX_RING_NUM; 4205 ret = 0; 4206 } 4207 break; 4208 case ETHTOOL_GRXCLSRLCNT: 4209 if (dev->hw_features & NETIF_F_LRO) { 4210 struct mtk_mac *mac = netdev_priv(dev); 4211 4212 cmd->rule_cnt = mac->hwlro_ip_cnt; 4213 ret = 0; 4214 } 4215 break; 4216 case ETHTOOL_GRXCLSRULE: 4217 if (dev->hw_features & NETIF_F_LRO) 4218 ret = mtk_hwlro_get_fdir_entry(dev, cmd); 4219 break; 4220 case ETHTOOL_GRXCLSRLALL: 4221 if (dev->hw_features & NETIF_F_LRO) 4222 ret = mtk_hwlro_get_fdir_all(dev, cmd, 4223 rule_locs); 4224 break; 4225 default: 4226 break; 4227 } 4228 4229 return ret; 4230 } 4231 4232 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 4233 { 4234 int ret = -EOPNOTSUPP; 4235 4236 switch (cmd->cmd) { 4237 case ETHTOOL_SRXCLSRLINS: 4238 if (dev->hw_features & NETIF_F_LRO) 4239 ret = mtk_hwlro_add_ipaddr(dev, cmd); 4240 break; 4241 case ETHTOOL_SRXCLSRLDEL: 4242 if (dev->hw_features & NETIF_F_LRO) 4243 ret = mtk_hwlro_del_ipaddr(dev, cmd); 4244 break; 4245 default: 4246 break; 4247 } 4248 4249 return ret; 4250 } 4251 4252 static u16 mtk_select_queue(struct net_device *dev, struct sk_buff *skb, 4253 struct net_device *sb_dev) 4254 { 4255 struct mtk_mac *mac = netdev_priv(dev); 4256 unsigned int queue = 0; 4257 4258 if (netdev_uses_dsa(dev)) 4259 queue = skb_get_queue_mapping(skb) + 3; 4260 else 4261 queue = mac->id; 4262 4263 if (queue >= dev->num_tx_queues) 4264 queue = 0; 4265 4266 return queue; 4267 } 4268 4269 static const struct ethtool_ops mtk_ethtool_ops = { 4270 .get_link_ksettings = mtk_get_link_ksettings, 4271 .set_link_ksettings = mtk_set_link_ksettings, 4272 .get_drvinfo = mtk_get_drvinfo, 4273 .get_msglevel = mtk_get_msglevel, 4274 .set_msglevel = mtk_set_msglevel, 4275 .nway_reset = mtk_nway_reset, 4276 .get_link = ethtool_op_get_link, 4277 .get_strings = mtk_get_strings, 4278 .get_sset_count = mtk_get_sset_count, 4279 .get_ethtool_stats = mtk_get_ethtool_stats, 4280 .get_rxnfc = mtk_get_rxnfc, 4281 .set_rxnfc = mtk_set_rxnfc, 4282 }; 4283 4284 static const struct net_device_ops mtk_netdev_ops = { 4285 .ndo_init = mtk_init, 4286 .ndo_uninit = mtk_uninit, 4287 .ndo_open = mtk_open, 4288 .ndo_stop = mtk_stop, 4289 .ndo_start_xmit = mtk_start_xmit, 4290 .ndo_set_mac_address = mtk_set_mac_address, 4291 .ndo_validate_addr = eth_validate_addr, 4292 .ndo_eth_ioctl = mtk_do_ioctl, 4293 .ndo_change_mtu = mtk_change_mtu, 4294 .ndo_tx_timeout = mtk_tx_timeout, 4295 .ndo_get_stats64 = mtk_get_stats64, 4296 .ndo_fix_features = mtk_fix_features, 4297 .ndo_set_features = mtk_set_features, 4298 #ifdef CONFIG_NET_POLL_CONTROLLER 4299 .ndo_poll_controller = mtk_poll_controller, 4300 #endif 4301 .ndo_setup_tc = mtk_eth_setup_tc, 4302 .ndo_bpf = mtk_xdp, 4303 .ndo_xdp_xmit = mtk_xdp_xmit, 4304 .ndo_select_queue = mtk_select_queue, 4305 }; 4306 4307 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np) 4308 { 4309 const __be32 *_id = of_get_property(np, "reg", NULL); 4310 phy_interface_t phy_mode; 4311 struct phylink *phylink; 4312 struct mtk_mac *mac; 4313 int id, err; 4314 int txqs = 1; 4315 u32 val; 4316 4317 if (!_id) { 4318 dev_err(eth->dev, "missing mac id\n"); 4319 return -EINVAL; 4320 } 4321 4322 id = be32_to_cpup(_id); 4323 if (id >= MTK_MAC_COUNT) { 4324 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4325 return -EINVAL; 4326 } 4327 4328 if (eth->netdev[id]) { 4329 dev_err(eth->dev, "duplicate mac id found: %d\n", id); 4330 return -EINVAL; 4331 } 4332 4333 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) 4334 txqs = MTK_QDMA_NUM_QUEUES; 4335 4336 eth->netdev[id] = alloc_etherdev_mqs(sizeof(*mac), txqs, 1); 4337 if (!eth->netdev[id]) { 4338 dev_err(eth->dev, "alloc_etherdev failed\n"); 4339 return -ENOMEM; 4340 } 4341 mac = netdev_priv(eth->netdev[id]); 4342 eth->mac[id] = mac; 4343 mac->id = id; 4344 mac->hw = eth; 4345 mac->of_node = np; 4346 4347 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip)); 4348 mac->hwlro_ip_cnt = 0; 4349 4350 mac->hw_stats = devm_kzalloc(eth->dev, 4351 sizeof(*mac->hw_stats), 4352 GFP_KERNEL); 4353 if (!mac->hw_stats) { 4354 dev_err(eth->dev, "failed to allocate counter memory\n"); 4355 err = -ENOMEM; 4356 goto free_netdev; 4357 } 4358 spin_lock_init(&mac->hw_stats->stats_lock); 4359 u64_stats_init(&mac->hw_stats->syncp); 4360 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4361 4362 /* phylink create */ 4363 err = of_get_phy_mode(np, &phy_mode); 4364 if (err) { 4365 dev_err(eth->dev, "incorrect phy-mode\n"); 4366 goto free_netdev; 4367 } 4368 4369 /* mac config is not set */ 4370 mac->interface = PHY_INTERFACE_MODE_NA; 4371 mac->speed = SPEED_UNKNOWN; 4372 4373 mac->phylink_config.dev = ð->netdev[id]->dev; 4374 mac->phylink_config.type = PHYLINK_NETDEV; 4375 /* This driver makes use of state->speed in mac_config */ 4376 mac->phylink_config.legacy_pre_march2020 = true; 4377 mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 4378 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; 4379 4380 __set_bit(PHY_INTERFACE_MODE_MII, 4381 mac->phylink_config.supported_interfaces); 4382 __set_bit(PHY_INTERFACE_MODE_GMII, 4383 mac->phylink_config.supported_interfaces); 4384 4385 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) 4386 phy_interface_set_rgmii(mac->phylink_config.supported_interfaces); 4387 4388 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id) 4389 __set_bit(PHY_INTERFACE_MODE_TRGMII, 4390 mac->phylink_config.supported_interfaces); 4391 4392 /* TRGMII is not permitted on MT7621 if using DDR2 */ 4393 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) && 4394 MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { 4395 regmap_read(eth->ethsys, ETHSYS_SYSCFG, &val); 4396 if (val & SYSCFG_DRAM_TYPE_DDR2) 4397 __clear_bit(PHY_INTERFACE_MODE_TRGMII, 4398 mac->phylink_config.supported_interfaces); 4399 } 4400 4401 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { 4402 __set_bit(PHY_INTERFACE_MODE_SGMII, 4403 mac->phylink_config.supported_interfaces); 4404 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4405 mac->phylink_config.supported_interfaces); 4406 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4407 mac->phylink_config.supported_interfaces); 4408 } 4409 4410 phylink = phylink_create(&mac->phylink_config, 4411 of_fwnode_handle(mac->of_node), 4412 phy_mode, &mtk_phylink_ops); 4413 if (IS_ERR(phylink)) { 4414 err = PTR_ERR(phylink); 4415 goto free_netdev; 4416 } 4417 4418 mac->phylink = phylink; 4419 4420 SET_NETDEV_DEV(eth->netdev[id], eth->dev); 4421 eth->netdev[id]->watchdog_timeo = 5 * HZ; 4422 eth->netdev[id]->netdev_ops = &mtk_netdev_ops; 4423 eth->netdev[id]->base_addr = (unsigned long)eth->base; 4424 4425 eth->netdev[id]->hw_features = eth->soc->hw_features; 4426 if (eth->hwlro) 4427 eth->netdev[id]->hw_features |= NETIF_F_LRO; 4428 4429 eth->netdev[id]->vlan_features = eth->soc->hw_features & 4430 ~NETIF_F_HW_VLAN_CTAG_TX; 4431 eth->netdev[id]->features |= eth->soc->hw_features; 4432 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops; 4433 4434 eth->netdev[id]->irq = eth->irq[0]; 4435 eth->netdev[id]->dev.of_node = np; 4436 4437 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4438 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN; 4439 else 4440 eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN; 4441 4442 if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) { 4443 mac->device_notifier.notifier_call = mtk_device_event; 4444 register_netdevice_notifier(&mac->device_notifier); 4445 } 4446 4447 if (mtk_page_pool_enabled(eth)) 4448 eth->netdev[id]->xdp_features = NETDEV_XDP_ACT_BASIC | 4449 NETDEV_XDP_ACT_REDIRECT | 4450 NETDEV_XDP_ACT_NDO_XMIT | 4451 NETDEV_XDP_ACT_NDO_XMIT_SG; 4452 4453 return 0; 4454 4455 free_netdev: 4456 free_netdev(eth->netdev[id]); 4457 return err; 4458 } 4459 4460 void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev) 4461 { 4462 struct net_device *dev, *tmp; 4463 LIST_HEAD(dev_list); 4464 int i; 4465 4466 rtnl_lock(); 4467 4468 for (i = 0; i < MTK_MAC_COUNT; i++) { 4469 dev = eth->netdev[i]; 4470 4471 if (!dev || !(dev->flags & IFF_UP)) 4472 continue; 4473 4474 list_add_tail(&dev->close_list, &dev_list); 4475 } 4476 4477 dev_close_many(&dev_list, false); 4478 4479 eth->dma_dev = dma_dev; 4480 4481 list_for_each_entry_safe(dev, tmp, &dev_list, close_list) { 4482 list_del_init(&dev->close_list); 4483 dev_open(dev, NULL); 4484 } 4485 4486 rtnl_unlock(); 4487 } 4488 4489 static int mtk_sgmii_init(struct mtk_eth *eth) 4490 { 4491 struct device_node *np; 4492 struct regmap *regmap; 4493 u32 flags; 4494 int i; 4495 4496 for (i = 0; i < MTK_MAX_DEVS; i++) { 4497 np = of_parse_phandle(eth->dev->of_node, "mediatek,sgmiisys", i); 4498 if (!np) 4499 break; 4500 4501 regmap = syscon_node_to_regmap(np); 4502 flags = 0; 4503 if (of_property_read_bool(np, "mediatek,pnswap")) 4504 flags |= MTK_SGMII_FLAG_PN_SWAP; 4505 4506 of_node_put(np); 4507 4508 if (IS_ERR(regmap)) 4509 return PTR_ERR(regmap); 4510 4511 eth->sgmii_pcs[i] = mtk_pcs_lynxi_create(eth->dev, regmap, 4512 eth->soc->ana_rgc3, 4513 flags); 4514 } 4515 4516 return 0; 4517 } 4518 4519 static int mtk_probe(struct platform_device *pdev) 4520 { 4521 struct resource *res = NULL; 4522 struct device_node *mac_np; 4523 struct mtk_eth *eth; 4524 int err, i; 4525 4526 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 4527 if (!eth) 4528 return -ENOMEM; 4529 4530 eth->soc = of_device_get_match_data(&pdev->dev); 4531 4532 eth->dev = &pdev->dev; 4533 eth->dma_dev = &pdev->dev; 4534 eth->base = devm_platform_ioremap_resource(pdev, 0); 4535 if (IS_ERR(eth->base)) 4536 return PTR_ERR(eth->base); 4537 4538 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 4539 eth->ip_align = NET_IP_ALIGN; 4540 4541 spin_lock_init(ð->page_lock); 4542 spin_lock_init(ð->tx_irq_lock); 4543 spin_lock_init(ð->rx_irq_lock); 4544 spin_lock_init(ð->dim_lock); 4545 4546 eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4547 INIT_WORK(ð->rx_dim.work, mtk_dim_rx); 4548 INIT_DELAYED_WORK(ð->reset.monitor_work, mtk_hw_reset_monitor_work); 4549 4550 eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 4551 INIT_WORK(ð->tx_dim.work, mtk_dim_tx); 4552 4553 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4554 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4555 "mediatek,ethsys"); 4556 if (IS_ERR(eth->ethsys)) { 4557 dev_err(&pdev->dev, "no ethsys regmap found\n"); 4558 return PTR_ERR(eth->ethsys); 4559 } 4560 } 4561 4562 if (MTK_HAS_CAPS(eth->soc->caps, MTK_INFRA)) { 4563 eth->infra = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4564 "mediatek,infracfg"); 4565 if (IS_ERR(eth->infra)) { 4566 dev_err(&pdev->dev, "no infracfg regmap found\n"); 4567 return PTR_ERR(eth->infra); 4568 } 4569 } 4570 4571 if (of_dma_is_coherent(pdev->dev.of_node)) { 4572 struct regmap *cci; 4573 4574 cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4575 "cci-control-port"); 4576 /* enable CPU/bus coherency */ 4577 if (!IS_ERR(cci)) 4578 regmap_write(cci, 0, 3); 4579 } 4580 4581 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { 4582 err = mtk_sgmii_init(eth); 4583 4584 if (err) 4585 return err; 4586 } 4587 4588 if (eth->soc->required_pctl) { 4589 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 4590 "mediatek,pctl"); 4591 if (IS_ERR(eth->pctl)) { 4592 dev_err(&pdev->dev, "no pctl regmap found\n"); 4593 err = PTR_ERR(eth->pctl); 4594 goto err_destroy_sgmii; 4595 } 4596 } 4597 4598 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4599 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4600 if (!res) { 4601 err = -EINVAL; 4602 goto err_destroy_sgmii; 4603 } 4604 } 4605 4606 if (eth->soc->offload_version) { 4607 for (i = 0;; i++) { 4608 struct device_node *np; 4609 phys_addr_t wdma_phy; 4610 u32 wdma_base; 4611 4612 if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base)) 4613 break; 4614 4615 np = of_parse_phandle(pdev->dev.of_node, 4616 "mediatek,wed", i); 4617 if (!np) 4618 break; 4619 4620 wdma_base = eth->soc->reg_map->wdma_base[i]; 4621 wdma_phy = res ? res->start + wdma_base : 0; 4622 mtk_wed_add_hw(np, eth, eth->base + wdma_base, 4623 wdma_phy, i); 4624 } 4625 } 4626 4627 for (i = 0; i < 3; i++) { 4628 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0) 4629 eth->irq[i] = eth->irq[0]; 4630 else 4631 eth->irq[i] = platform_get_irq(pdev, i); 4632 if (eth->irq[i] < 0) { 4633 dev_err(&pdev->dev, "no IRQ%d resource found\n", i); 4634 err = -ENXIO; 4635 goto err_wed_exit; 4636 } 4637 } 4638 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) { 4639 eth->clks[i] = devm_clk_get(eth->dev, 4640 mtk_clks_source_name[i]); 4641 if (IS_ERR(eth->clks[i])) { 4642 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER) { 4643 err = -EPROBE_DEFER; 4644 goto err_wed_exit; 4645 } 4646 if (eth->soc->required_clks & BIT(i)) { 4647 dev_err(&pdev->dev, "clock %s not found\n", 4648 mtk_clks_source_name[i]); 4649 err = -EINVAL; 4650 goto err_wed_exit; 4651 } 4652 eth->clks[i] = NULL; 4653 } 4654 } 4655 4656 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE); 4657 INIT_WORK(ð->pending_work, mtk_pending_work); 4658 4659 err = mtk_hw_init(eth, false); 4660 if (err) 4661 goto err_wed_exit; 4662 4663 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO); 4664 4665 for_each_child_of_node(pdev->dev.of_node, mac_np) { 4666 if (!of_device_is_compatible(mac_np, 4667 "mediatek,eth-mac")) 4668 continue; 4669 4670 if (!of_device_is_available(mac_np)) 4671 continue; 4672 4673 err = mtk_add_mac(eth, mac_np); 4674 if (err) { 4675 of_node_put(mac_np); 4676 goto err_deinit_hw; 4677 } 4678 } 4679 4680 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) { 4681 err = devm_request_irq(eth->dev, eth->irq[0], 4682 mtk_handle_irq, 0, 4683 dev_name(eth->dev), eth); 4684 } else { 4685 err = devm_request_irq(eth->dev, eth->irq[1], 4686 mtk_handle_irq_tx, 0, 4687 dev_name(eth->dev), eth); 4688 if (err) 4689 goto err_free_dev; 4690 4691 err = devm_request_irq(eth->dev, eth->irq[2], 4692 mtk_handle_irq_rx, 0, 4693 dev_name(eth->dev), eth); 4694 } 4695 if (err) 4696 goto err_free_dev; 4697 4698 /* No MT7628/88 support yet */ 4699 if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) { 4700 err = mtk_mdio_init(eth); 4701 if (err) 4702 goto err_free_dev; 4703 } 4704 4705 if (eth->soc->offload_version) { 4706 u32 num_ppe; 4707 4708 num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4709 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4710 for (i = 0; i < num_ppe; i++) { 4711 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; 4712 4713 eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i); 4714 4715 if (!eth->ppe[i]) { 4716 err = -ENOMEM; 4717 goto err_deinit_ppe; 4718 } 4719 } 4720 4721 err = mtk_eth_offload_init(eth); 4722 if (err) 4723 goto err_deinit_ppe; 4724 } 4725 4726 for (i = 0; i < MTK_MAX_DEVS; i++) { 4727 if (!eth->netdev[i]) 4728 continue; 4729 4730 err = register_netdev(eth->netdev[i]); 4731 if (err) { 4732 dev_err(eth->dev, "error bringing up device\n"); 4733 goto err_deinit_ppe; 4734 } else 4735 netif_info(eth, probe, eth->netdev[i], 4736 "mediatek frame engine at 0x%08lx, irq %d\n", 4737 eth->netdev[i]->base_addr, eth->irq[0]); 4738 } 4739 4740 /* we run 2 devices on the same DMA ring so we need a dummy device 4741 * for NAPI to work 4742 */ 4743 init_dummy_netdev(ð->dummy_dev); 4744 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx); 4745 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx); 4746 4747 platform_set_drvdata(pdev, eth); 4748 schedule_delayed_work(ð->reset.monitor_work, 4749 MTK_DMA_MONITOR_TIMEOUT); 4750 4751 return 0; 4752 4753 err_deinit_ppe: 4754 mtk_ppe_deinit(eth); 4755 mtk_mdio_cleanup(eth); 4756 err_free_dev: 4757 mtk_free_dev(eth); 4758 err_deinit_hw: 4759 mtk_hw_deinit(eth); 4760 err_wed_exit: 4761 mtk_wed_exit(); 4762 err_destroy_sgmii: 4763 mtk_sgmii_destroy(eth); 4764 4765 return err; 4766 } 4767 4768 static int mtk_remove(struct platform_device *pdev) 4769 { 4770 struct mtk_eth *eth = platform_get_drvdata(pdev); 4771 struct mtk_mac *mac; 4772 int i; 4773 4774 /* stop all devices to make sure that dma is properly shut down */ 4775 for (i = 0; i < MTK_MAC_COUNT; i++) { 4776 if (!eth->netdev[i]) 4777 continue; 4778 mtk_stop(eth->netdev[i]); 4779 mac = netdev_priv(eth->netdev[i]); 4780 phylink_disconnect_phy(mac->phylink); 4781 } 4782 4783 mtk_wed_exit(); 4784 mtk_hw_deinit(eth); 4785 4786 netif_napi_del(ð->tx_napi); 4787 netif_napi_del(ð->rx_napi); 4788 mtk_cleanup(eth); 4789 mtk_mdio_cleanup(eth); 4790 4791 return 0; 4792 } 4793 4794 static const struct mtk_soc_data mt2701_data = { 4795 .reg_map = &mtk_reg_map, 4796 .caps = MT7623_CAPS | MTK_HWLRO, 4797 .hw_features = MTK_HW_FEATURES, 4798 .required_clks = MT7623_CLKS_BITMAP, 4799 .required_pctl = true, 4800 .txrx = { 4801 .txd_size = sizeof(struct mtk_tx_dma), 4802 .rxd_size = sizeof(struct mtk_rx_dma), 4803 .rx_irq_done_mask = MTK_RX_DONE_INT, 4804 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4805 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4806 .dma_len_offset = 16, 4807 }, 4808 }; 4809 4810 static const struct mtk_soc_data mt7621_data = { 4811 .reg_map = &mtk_reg_map, 4812 .caps = MT7621_CAPS, 4813 .hw_features = MTK_HW_FEATURES, 4814 .required_clks = MT7621_CLKS_BITMAP, 4815 .required_pctl = false, 4816 .offload_version = 1, 4817 .hash_offset = 2, 4818 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4819 .txrx = { 4820 .txd_size = sizeof(struct mtk_tx_dma), 4821 .rxd_size = sizeof(struct mtk_rx_dma), 4822 .rx_irq_done_mask = MTK_RX_DONE_INT, 4823 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4824 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4825 .dma_len_offset = 16, 4826 }, 4827 }; 4828 4829 static const struct mtk_soc_data mt7622_data = { 4830 .reg_map = &mtk_reg_map, 4831 .ana_rgc3 = 0x2028, 4832 .caps = MT7622_CAPS | MTK_HWLRO, 4833 .hw_features = MTK_HW_FEATURES, 4834 .required_clks = MT7622_CLKS_BITMAP, 4835 .required_pctl = false, 4836 .offload_version = 2, 4837 .hash_offset = 2, 4838 .has_accounting = true, 4839 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4840 .txrx = { 4841 .txd_size = sizeof(struct mtk_tx_dma), 4842 .rxd_size = sizeof(struct mtk_rx_dma), 4843 .rx_irq_done_mask = MTK_RX_DONE_INT, 4844 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4845 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4846 .dma_len_offset = 16, 4847 }, 4848 }; 4849 4850 static const struct mtk_soc_data mt7623_data = { 4851 .reg_map = &mtk_reg_map, 4852 .caps = MT7623_CAPS | MTK_HWLRO, 4853 .hw_features = MTK_HW_FEATURES, 4854 .required_clks = MT7623_CLKS_BITMAP, 4855 .required_pctl = true, 4856 .offload_version = 1, 4857 .hash_offset = 2, 4858 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16, 4859 .txrx = { 4860 .txd_size = sizeof(struct mtk_tx_dma), 4861 .rxd_size = sizeof(struct mtk_rx_dma), 4862 .rx_irq_done_mask = MTK_RX_DONE_INT, 4863 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4864 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4865 .dma_len_offset = 16, 4866 }, 4867 }; 4868 4869 static const struct mtk_soc_data mt7629_data = { 4870 .reg_map = &mtk_reg_map, 4871 .ana_rgc3 = 0x128, 4872 .caps = MT7629_CAPS | MTK_HWLRO, 4873 .hw_features = MTK_HW_FEATURES, 4874 .required_clks = MT7629_CLKS_BITMAP, 4875 .required_pctl = false, 4876 .has_accounting = true, 4877 .txrx = { 4878 .txd_size = sizeof(struct mtk_tx_dma), 4879 .rxd_size = sizeof(struct mtk_rx_dma), 4880 .rx_irq_done_mask = MTK_RX_DONE_INT, 4881 .rx_dma_l4_valid = RX_DMA_L4_VALID, 4882 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4883 .dma_len_offset = 16, 4884 }, 4885 }; 4886 4887 static const struct mtk_soc_data mt7981_data = { 4888 .reg_map = &mt7986_reg_map, 4889 .ana_rgc3 = 0x128, 4890 .caps = MT7981_CAPS, 4891 .hw_features = MTK_HW_FEATURES, 4892 .required_clks = MT7981_CLKS_BITMAP, 4893 .required_pctl = false, 4894 .offload_version = 2, 4895 .hash_offset = 4, 4896 .foe_entry_size = sizeof(struct mtk_foe_entry), 4897 .has_accounting = true, 4898 .txrx = { 4899 .txd_size = sizeof(struct mtk_tx_dma_v2), 4900 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4901 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4902 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4903 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4904 .dma_len_offset = 8, 4905 }, 4906 }; 4907 4908 static const struct mtk_soc_data mt7986_data = { 4909 .reg_map = &mt7986_reg_map, 4910 .ana_rgc3 = 0x128, 4911 .caps = MT7986_CAPS, 4912 .hw_features = MTK_HW_FEATURES, 4913 .required_clks = MT7986_CLKS_BITMAP, 4914 .required_pctl = false, 4915 .offload_version = 2, 4916 .hash_offset = 4, 4917 .foe_entry_size = sizeof(struct mtk_foe_entry), 4918 .has_accounting = true, 4919 .txrx = { 4920 .txd_size = sizeof(struct mtk_tx_dma_v2), 4921 .rxd_size = sizeof(struct mtk_rx_dma_v2), 4922 .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4923 .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4924 .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4925 .dma_len_offset = 8, 4926 }, 4927 }; 4928 4929 static const struct mtk_soc_data rt5350_data = { 4930 .reg_map = &mt7628_reg_map, 4931 .caps = MT7628_CAPS, 4932 .hw_features = MTK_HW_FEATURES_MT7628, 4933 .required_clks = MT7628_CLKS_BITMAP, 4934 .required_pctl = false, 4935 .txrx = { 4936 .txd_size = sizeof(struct mtk_tx_dma), 4937 .rxd_size = sizeof(struct mtk_rx_dma), 4938 .rx_irq_done_mask = MTK_RX_DONE_INT, 4939 .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, 4940 .dma_max_len = MTK_TX_DMA_BUF_LEN, 4941 .dma_len_offset = 16, 4942 }, 4943 }; 4944 4945 const struct of_device_id of_mtk_match[] = { 4946 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 4947 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 4948 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 4949 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 4950 { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 4951 { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, 4952 { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 4953 { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4954 {}, 4955 }; 4956 MODULE_DEVICE_TABLE(of, of_mtk_match); 4957 4958 static struct platform_driver mtk_driver = { 4959 .probe = mtk_probe, 4960 .remove = mtk_remove, 4961 .driver = { 4962 .name = "mtk_soc_eth", 4963 .of_match_table = of_mtk_match, 4964 }, 4965 }; 4966 4967 module_platform_driver(mtk_driver); 4968 4969 MODULE_LICENSE("GPL"); 4970 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 4971 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC"); 4972