1527a6266SJeff Kirsher /* 2527a6266SJeff Kirsher * Definitions for the new Marvell Yukon 2 driver. 3527a6266SJeff Kirsher */ 4527a6266SJeff Kirsher #ifndef _SKY2_H 5527a6266SJeff Kirsher #define _SKY2_H 6527a6266SJeff Kirsher 7527a6266SJeff Kirsher #define ETH_JUMBO_MTU 9000 /* Maximum MTU supported */ 8527a6266SJeff Kirsher 9527a6266SJeff Kirsher /* PCI config registers */ 10527a6266SJeff Kirsher enum { 11527a6266SJeff Kirsher PCI_DEV_REG1 = 0x40, 12527a6266SJeff Kirsher PCI_DEV_REG2 = 0x44, 13527a6266SJeff Kirsher PCI_DEV_STATUS = 0x7c, 14527a6266SJeff Kirsher PCI_DEV_REG3 = 0x80, 15527a6266SJeff Kirsher PCI_DEV_REG4 = 0x84, 16527a6266SJeff Kirsher PCI_DEV_REG5 = 0x88, 17527a6266SJeff Kirsher PCI_CFG_REG_0 = 0x90, 18527a6266SJeff Kirsher PCI_CFG_REG_1 = 0x94, 19527a6266SJeff Kirsher 20527a6266SJeff Kirsher PSM_CONFIG_REG0 = 0x98, 21527a6266SJeff Kirsher PSM_CONFIG_REG1 = 0x9C, 22527a6266SJeff Kirsher PSM_CONFIG_REG2 = 0x160, 23527a6266SJeff Kirsher PSM_CONFIG_REG3 = 0x164, 24527a6266SJeff Kirsher PSM_CONFIG_REG4 = 0x168, 25527a6266SJeff Kirsher 260e767324SMirko Lindner PCI_LDO_CTRL = 0xbc, 27527a6266SJeff Kirsher }; 28527a6266SJeff Kirsher 29527a6266SJeff Kirsher /* Yukon-2 */ 30527a6266SJeff Kirsher enum pci_dev_reg_1 { 31527a6266SJeff Kirsher PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */ 32527a6266SJeff Kirsher PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */ 33527a6266SJeff Kirsher PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */ 34527a6266SJeff Kirsher PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */ 35527a6266SJeff Kirsher PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */ 36527a6266SJeff Kirsher PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */ 37527a6266SJeff Kirsher PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */ 38527a6266SJeff Kirsher PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */ 39527a6266SJeff Kirsher 40527a6266SJeff Kirsher PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */ 41527a6266SJeff Kirsher PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */ 42527a6266SJeff Kirsher PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */ 43527a6266SJeff Kirsher PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */ 44527a6266SJeff Kirsher }; 45527a6266SJeff Kirsher 46527a6266SJeff Kirsher enum pci_dev_reg_2 { 47527a6266SJeff Kirsher PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */ 48527a6266SJeff Kirsher PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */ 49527a6266SJeff Kirsher PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */ 50527a6266SJeff Kirsher 51527a6266SJeff Kirsher PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */ 52527a6266SJeff Kirsher PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */ 53527a6266SJeff Kirsher PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */ 54527a6266SJeff Kirsher PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */ 55527a6266SJeff Kirsher 56527a6266SJeff Kirsher PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */ 57527a6266SJeff Kirsher }; 58527a6266SJeff Kirsher 59527a6266SJeff Kirsher /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ 60527a6266SJeff Kirsher enum pci_dev_reg_3 { 61527a6266SJeff Kirsher P_CLK_ASF_REGS_DIS = 1<<18,/* Disable Clock ASF (Yukon-Ext.) */ 62527a6266SJeff Kirsher P_CLK_COR_REGS_D0_DIS = 1<<17,/* Disable Clock Core Regs D0 */ 63527a6266SJeff Kirsher P_CLK_MACSEC_DIS = 1<<17,/* Disable Clock MACSec (Yukon-Ext.) */ 64527a6266SJeff Kirsher P_CLK_PCI_REGS_D0_DIS = 1<<16,/* Disable Clock PCI Regs D0 */ 65527a6266SJeff Kirsher P_CLK_COR_YTB_ARB_DIS = 1<<15,/* Disable Clock YTB Arbiter */ 66527a6266SJeff Kirsher P_CLK_MAC_LNK1_D3_DIS = 1<<14,/* Disable Clock MAC Link1 D3 */ 67527a6266SJeff Kirsher P_CLK_COR_LNK1_D0_DIS = 1<<13,/* Disable Clock Core Link1 D0 */ 68527a6266SJeff Kirsher P_CLK_MAC_LNK1_D0_DIS = 1<<12,/* Disable Clock MAC Link1 D0 */ 69527a6266SJeff Kirsher P_CLK_COR_LNK1_D3_DIS = 1<<11,/* Disable Clock Core Link1 D3 */ 70527a6266SJeff Kirsher P_CLK_PCI_MST_ARB_DIS = 1<<10,/* Disable Clock PCI Master Arb. */ 71527a6266SJeff Kirsher P_CLK_COR_REGS_D3_DIS = 1<<9, /* Disable Clock Core Regs D3 */ 72527a6266SJeff Kirsher P_CLK_PCI_REGS_D3_DIS = 1<<8, /* Disable Clock PCI Regs D3 */ 73527a6266SJeff Kirsher P_CLK_REF_LNK1_GM_DIS = 1<<7, /* Disable Clock Ref. Link1 GMAC */ 74527a6266SJeff Kirsher P_CLK_COR_LNK1_GM_DIS = 1<<6, /* Disable Clock Core Link1 GMAC */ 75527a6266SJeff Kirsher P_CLK_PCI_COMMON_DIS = 1<<5, /* Disable Clock PCI Common */ 76527a6266SJeff Kirsher P_CLK_COR_COMMON_DIS = 1<<4, /* Disable Clock Core Common */ 77527a6266SJeff Kirsher P_CLK_PCI_LNK1_BMU_DIS = 1<<3, /* Disable Clock PCI Link1 BMU */ 78527a6266SJeff Kirsher P_CLK_COR_LNK1_BMU_DIS = 1<<2, /* Disable Clock Core Link1 BMU */ 79527a6266SJeff Kirsher P_CLK_PCI_LNK1_BIU_DIS = 1<<1, /* Disable Clock PCI Link1 BIU */ 80527a6266SJeff Kirsher P_CLK_COR_LNK1_BIU_DIS = 1<<0, /* Disable Clock Core Link1 BIU */ 81527a6266SJeff Kirsher PCIE_OUR3_WOL_D3_COLD_SET = P_CLK_ASF_REGS_DIS | 82527a6266SJeff Kirsher P_CLK_COR_REGS_D0_DIS | 83527a6266SJeff Kirsher P_CLK_COR_LNK1_D0_DIS | 84527a6266SJeff Kirsher P_CLK_MAC_LNK1_D0_DIS | 85527a6266SJeff Kirsher P_CLK_PCI_MST_ARB_DIS | 86527a6266SJeff Kirsher P_CLK_COR_COMMON_DIS | 87527a6266SJeff Kirsher P_CLK_COR_LNK1_BMU_DIS, 88527a6266SJeff Kirsher }; 89527a6266SJeff Kirsher 90527a6266SJeff Kirsher /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 91527a6266SJeff Kirsher enum pci_dev_reg_4 { 92527a6266SJeff Kirsher /* (Link Training & Status State Machine) */ 93527a6266SJeff Kirsher P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */ 94527a6266SJeff Kirsher #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK) 95527a6266SJeff Kirsher P_PEX_LTSSM_L1_STAT = 0x34, 96527a6266SJeff Kirsher P_PEX_LTSSM_DET_STAT = 0x01, 97527a6266SJeff Kirsher P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */ 98527a6266SJeff Kirsher /* (Active State Power Management) */ 99527a6266SJeff Kirsher P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */ 100527a6266SJeff Kirsher P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */ 101527a6266SJeff Kirsher P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */ 102527a6266SJeff Kirsher P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */ 103527a6266SJeff Kirsher 104527a6266SJeff Kirsher P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */ 105527a6266SJeff Kirsher P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */ 106527a6266SJeff Kirsher P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */ 107527a6266SJeff Kirsher P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */ 108527a6266SJeff Kirsher P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */ 109527a6266SJeff Kirsher P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN 110527a6266SJeff Kirsher | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY, 111527a6266SJeff Kirsher }; 112527a6266SJeff Kirsher 113527a6266SJeff Kirsher /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 114527a6266SJeff Kirsher enum pci_dev_reg_5 { 115527a6266SJeff Kirsher /* Bit 31..27: for A3 & later */ 116527a6266SJeff Kirsher P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */ 117527a6266SJeff Kirsher P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */ 118527a6266SJeff Kirsher P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */ 119527a6266SJeff Kirsher P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */ 120527a6266SJeff Kirsher /* Bit 26..16: Release Clock on Event */ 121527a6266SJeff Kirsher P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */ 122527a6266SJeff Kirsher P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */ 123527a6266SJeff Kirsher P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */ 124527a6266SJeff Kirsher P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */ 125527a6266SJeff Kirsher P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */ 126527a6266SJeff Kirsher P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */ 127527a6266SJeff Kirsher P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */ 128527a6266SJeff Kirsher P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */ 129527a6266SJeff Kirsher P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */ 130527a6266SJeff Kirsher P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */ 131527a6266SJeff Kirsher P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */ 132527a6266SJeff Kirsher 133527a6266SJeff Kirsher /* Bit 10.. 0: Mask for Gate Clock */ 134527a6266SJeff Kirsher P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */ 135527a6266SJeff Kirsher P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */ 136527a6266SJeff Kirsher P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */ 137527a6266SJeff Kirsher P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */ 138527a6266SJeff Kirsher P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */ 139527a6266SJeff Kirsher P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */ 140527a6266SJeff Kirsher P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */ 141527a6266SJeff Kirsher P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */ 142527a6266SJeff Kirsher P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */ 143527a6266SJeff Kirsher P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */ 144527a6266SJeff Kirsher P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */ 145527a6266SJeff Kirsher 146527a6266SJeff Kirsher PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET | 147527a6266SJeff Kirsher P_REL_INT_FIFO_N_EMPTY | 148527a6266SJeff Kirsher P_REL_PCIE_EXIT_L1_ST | 149527a6266SJeff Kirsher P_REL_PCIE_RX_EX_IDLE | 150527a6266SJeff Kirsher P_GAT_GPHY_N_REC_PACKET | 151527a6266SJeff Kirsher P_GAT_INT_FIFO_EMPTY | 152527a6266SJeff Kirsher P_GAT_PCIE_ENTER_L1_ST | 153527a6266SJeff Kirsher P_GAT_PCIE_RX_EL_IDLE, 154527a6266SJeff Kirsher }; 155527a6266SJeff Kirsher 156527a6266SJeff Kirsher /* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */ 157527a6266SJeff Kirsher enum pci_cfg_reg1 { 158527a6266SJeff Kirsher P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */ 159527a6266SJeff Kirsher /* Bit 23..21: Release Clock on Event */ 160527a6266SJeff Kirsher P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */ 161527a6266SJeff Kirsher P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */ 162527a6266SJeff Kirsher P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */ 163527a6266SJeff Kirsher /* Bit 20..18: Gate Clock on Event */ 164527a6266SJeff Kirsher P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */ 165527a6266SJeff Kirsher P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */ 166527a6266SJeff Kirsher P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */ 167527a6266SJeff Kirsher P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 168527a6266SJeff Kirsher P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */ 169527a6266SJeff Kirsher 170527a6266SJeff Kirsher P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */ 171527a6266SJeff Kirsher 172527a6266SJeff Kirsher P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */ 173527a6266SJeff Kirsher P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */ 174527a6266SJeff Kirsher 175527a6266SJeff Kirsher PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST | 176527a6266SJeff Kirsher P_CF1_REL_LDR_NOT_FIN | 177527a6266SJeff Kirsher P_CF1_REL_VMAIN_AVLBL | 178527a6266SJeff Kirsher P_CF1_REL_PCIE_RESET | 179527a6266SJeff Kirsher P_CF1_GAT_LDR_NOT_FIN | 180527a6266SJeff Kirsher P_CF1_GAT_PCIE_RESET | 181527a6266SJeff Kirsher P_CF1_PRST_PHY_CLKREQ | 182527a6266SJeff Kirsher P_CF1_ENA_CFG_LDR_DONE | 183527a6266SJeff Kirsher P_CF1_ENA_TXBMU_RD_IDLE | 184527a6266SJeff Kirsher P_CF1_ENA_TXBMU_WR_IDLE, 185527a6266SJeff Kirsher }; 186527a6266SJeff Kirsher 187527a6266SJeff Kirsher /* Yukon-Optima */ 188527a6266SJeff Kirsher enum { 189527a6266SJeff Kirsher PSM_CONFIG_REG1_AC_PRESENT_STATUS = 1<<31, /* AC Present Status */ 190527a6266SJeff Kirsher 191527a6266SJeff Kirsher PSM_CONFIG_REG1_PTP_CLK_SEL = 1<<29, /* PTP Clock Select */ 192527a6266SJeff Kirsher PSM_CONFIG_REG1_PTP_MODE = 1<<28, /* PTP Mode */ 193527a6266SJeff Kirsher 194527a6266SJeff Kirsher PSM_CONFIG_REG1_MUX_PHY_LINK = 1<<27, /* PHY Energy Detect Event */ 195527a6266SJeff Kirsher 196527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PIN63_AC_PRESENT = 1<<26, /* Enable LED_DUPLEX for ac_present */ 197527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PCIE_TIMER = 1<<25, /* Enable PCIe Timer */ 198527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_SPU_TIMER = 1<<24, /* Enable SPU Timer */ 199527a6266SJeff Kirsher PSM_CONFIG_REG1_POLARITY_AC_PRESENT = 1<<23, /* AC Present Polarity */ 200527a6266SJeff Kirsher 201527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_AC_PRESENT = 1<<21, /* Enable AC Present */ 202527a6266SJeff Kirsher 203527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_GPHY_INT_PSM = 1<<20, /* Enable GPHY INT for PSM */ 204527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_PSM_TIMER = 1<<19, /* Disable PSM Timer */ 205527a6266SJeff Kirsher }; 206527a6266SJeff Kirsher 207527a6266SJeff Kirsher /* Yukon-Supreme */ 208527a6266SJeff Kirsher enum { 209527a6266SJeff Kirsher PSM_CONFIG_REG1_GPHY_ENERGY_STS = 1<<31, /* GPHY Energy Detect Status */ 210527a6266SJeff Kirsher 211527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_MODE_MSK = 3<<29, /* UART_Mode */ 212527a6266SJeff Kirsher PSM_CONFIG_REG1_CLK_RUN_ASF = 1<<28, /* Enable Clock Free Running for ASF Subsystem */ 213527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_CLK_DISABLE= 1<<27, /* Disable UART clock */ 214527a6266SJeff Kirsher PSM_CONFIG_REG1_VAUX_ONE = 1<<26, /* Tie internal Vaux to 1'b1 */ 215527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_FC_RI_VAL = 1<<25, /* Default value for UART_RI_n */ 216527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_FC_DCD_VAL = 1<<24, /* Default value for UART_DCD_n */ 217527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_FC_DSR_VAL = 1<<23, /* Default value for UART_DSR_n */ 218527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_FC_CTS_VAL = 1<<22, /* Default value for UART_CTS_n */ 219527a6266SJeff Kirsher PSM_CONFIG_REG1_LATCH_VAUX = 1<<21, /* Enable Latch current Vaux_avlbl */ 220527a6266SJeff Kirsher PSM_CONFIG_REG1_FORCE_TESTMODE_INPUT= 1<<20, /* Force Testmode pin as input PAD */ 221527a6266SJeff Kirsher PSM_CONFIG_REG1_UART_RST = 1<<19, /* UART_RST */ 222527a6266SJeff Kirsher PSM_CONFIG_REG1_PSM_PCIE_L1_POL = 1<<18, /* PCIE L1 Event Polarity for PSM */ 223527a6266SJeff Kirsher PSM_CONFIG_REG1_TIMER_STAT = 1<<17, /* PSM Timer Status */ 224527a6266SJeff Kirsher PSM_CONFIG_REG1_GPHY_INT = 1<<16, /* GPHY INT Status */ 225527a6266SJeff Kirsher PSM_CONFIG_REG1_FORCE_TESTMODE_ZERO= 1<<15, /* Force internal Testmode as 1'b0 */ 226527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_INT_ASPM_CLKREQ = 1<<14, /* ENABLE INT for CLKRUN on ASPM and CLKREQ */ 227527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_SND_TASK_ASPM_CLKREQ = 1<<13, /* ENABLE Snd_task for CLKRUN on ASPM and CLKREQ */ 228527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_CLK_GATE_SND_TASK = 1<<12, /* Disable CLK_GATE control snd_task */ 229527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_FF_CHIAN_SND_INTA = 1<<11, /* Disable flip-flop chain for sndmsg_inta */ 230527a6266SJeff Kirsher 231527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_LOADER = 1<<9, /* Disable Loader SM after PSM Goes back to IDLE */ 232527a6266SJeff Kirsher PSM_CONFIG_REG1_DO_PWDN = 1<<8, /* Do Power Down, Start PSM Scheme */ 233527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_PIG = 1<<7, /* Disable Plug-in-Go SM after PSM Goes back to IDLE */ 234527a6266SJeff Kirsher PSM_CONFIG_REG1_DIS_PERST = 1<<6, /* Disable Internal PCIe Reset after PSM Goes back to IDLE */ 235527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_REG18_PD = 1<<5, /* Enable REG18 Power Down for PSM */ 236527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PSM_LOAD = 1<<4, /* Disable EEPROM Loader after PSM Goes back to IDLE */ 237527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PSM_HOT_RST = 1<<3, /* Enable PCIe Hot Reset for PSM */ 238527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PSM_PERST = 1<<2, /* Enable PCIe Reset Event for PSM */ 239527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PSM_PCIE_L1 = 1<<1, /* Enable PCIe L1 Event for PSM */ 240527a6266SJeff Kirsher PSM_CONFIG_REG1_EN_PSM = 1<<0, /* Enable PSM Scheme */ 241527a6266SJeff Kirsher }; 242527a6266SJeff Kirsher 243527a6266SJeff Kirsher /* PSM_CONFIG_REG4 0x0168 PSM Config Register 4 */ 244527a6266SJeff Kirsher enum { 245527a6266SJeff Kirsher /* PHY Link Detect Timer */ 246527a6266SJeff Kirsher PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_MSK = 0xf<<4, 247527a6266SJeff Kirsher PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE = 4, 248527a6266SJeff Kirsher 249527a6266SJeff Kirsher PSM_CONFIG_REG4_DEBUG_TIMER = 1<<1, /* Debug Timer */ 250527a6266SJeff Kirsher PSM_CONFIG_REG4_RST_PHY_LINK_DETECT = 1<<0, /* Reset GPHY Link Detect */ 251527a6266SJeff Kirsher }; 252527a6266SJeff Kirsher 253527a6266SJeff Kirsher 254527a6266SJeff Kirsher #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ 255527a6266SJeff Kirsher PCI_STATUS_SIG_SYSTEM_ERROR | \ 256527a6266SJeff Kirsher PCI_STATUS_REC_MASTER_ABORT | \ 257527a6266SJeff Kirsher PCI_STATUS_REC_TARGET_ABORT | \ 258527a6266SJeff Kirsher PCI_STATUS_PARITY) 259527a6266SJeff Kirsher 260527a6266SJeff Kirsher enum csr_regs { 261527a6266SJeff Kirsher B0_RAP = 0x0000, 262527a6266SJeff Kirsher B0_CTST = 0x0004, 263527a6266SJeff Kirsher 264527a6266SJeff Kirsher B0_POWER_CTRL = 0x0007, 265527a6266SJeff Kirsher B0_ISRC = 0x0008, 266527a6266SJeff Kirsher B0_IMSK = 0x000c, 267527a6266SJeff Kirsher B0_HWE_ISRC = 0x0010, 268527a6266SJeff Kirsher B0_HWE_IMSK = 0x0014, 269527a6266SJeff Kirsher 270527a6266SJeff Kirsher /* Special ISR registers (Yukon-2 only) */ 271527a6266SJeff Kirsher B0_Y2_SP_ISRC2 = 0x001c, 272527a6266SJeff Kirsher B0_Y2_SP_ISRC3 = 0x0020, 273527a6266SJeff Kirsher B0_Y2_SP_EISR = 0x0024, 274527a6266SJeff Kirsher B0_Y2_SP_LISR = 0x0028, 275527a6266SJeff Kirsher B0_Y2_SP_ICR = 0x002c, 276527a6266SJeff Kirsher 277527a6266SJeff Kirsher B2_MAC_1 = 0x0100, 278527a6266SJeff Kirsher B2_MAC_2 = 0x0108, 279527a6266SJeff Kirsher B2_MAC_3 = 0x0110, 280527a6266SJeff Kirsher B2_CONN_TYP = 0x0118, 281527a6266SJeff Kirsher B2_PMD_TYP = 0x0119, 282527a6266SJeff Kirsher B2_MAC_CFG = 0x011a, 283527a6266SJeff Kirsher B2_CHIP_ID = 0x011b, 284527a6266SJeff Kirsher B2_E_0 = 0x011c, 285527a6266SJeff Kirsher 286527a6266SJeff Kirsher B2_Y2_CLK_GATE = 0x011d, 287527a6266SJeff Kirsher B2_Y2_HW_RES = 0x011e, 288527a6266SJeff Kirsher B2_E_3 = 0x011f, 289527a6266SJeff Kirsher B2_Y2_CLK_CTRL = 0x0120, 290527a6266SJeff Kirsher 291527a6266SJeff Kirsher B2_TI_INI = 0x0130, 292527a6266SJeff Kirsher B2_TI_VAL = 0x0134, 293527a6266SJeff Kirsher B2_TI_CTRL = 0x0138, 294527a6266SJeff Kirsher B2_TI_TEST = 0x0139, 295527a6266SJeff Kirsher 296527a6266SJeff Kirsher B2_TST_CTRL1 = 0x0158, 297527a6266SJeff Kirsher B2_TST_CTRL2 = 0x0159, 298527a6266SJeff Kirsher B2_GP_IO = 0x015c, 299527a6266SJeff Kirsher 300527a6266SJeff Kirsher B2_I2C_CTRL = 0x0160, 301527a6266SJeff Kirsher B2_I2C_DATA = 0x0164, 302527a6266SJeff Kirsher B2_I2C_IRQ = 0x0168, 303527a6266SJeff Kirsher B2_I2C_SW = 0x016c, 304527a6266SJeff Kirsher 305527a6266SJeff Kirsher Y2_PEX_PHY_DATA = 0x0170, 306527a6266SJeff Kirsher Y2_PEX_PHY_ADDR = 0x0172, 307527a6266SJeff Kirsher 308527a6266SJeff Kirsher B3_RAM_ADDR = 0x0180, 309527a6266SJeff Kirsher B3_RAM_DATA_LO = 0x0184, 310527a6266SJeff Kirsher B3_RAM_DATA_HI = 0x0188, 311527a6266SJeff Kirsher 312527a6266SJeff Kirsher /* RAM Interface Registers */ 313527a6266SJeff Kirsher /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */ 314527a6266SJeff Kirsher /* 315527a6266SJeff Kirsher * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 316527a6266SJeff Kirsher * not usable in SW. Please notice these are NOT real timeouts, these are 317527a6266SJeff Kirsher * the number of qWords transferred continuously. 318527a6266SJeff Kirsher */ 319527a6266SJeff Kirsher #define RAM_BUFFER(port, reg) (reg | (port <<6)) 320527a6266SJeff Kirsher 321527a6266SJeff Kirsher B3_RI_WTO_R1 = 0x0190, 322527a6266SJeff Kirsher B3_RI_WTO_XA1 = 0x0191, 323527a6266SJeff Kirsher B3_RI_WTO_XS1 = 0x0192, 324527a6266SJeff Kirsher B3_RI_RTO_R1 = 0x0193, 325527a6266SJeff Kirsher B3_RI_RTO_XA1 = 0x0194, 326527a6266SJeff Kirsher B3_RI_RTO_XS1 = 0x0195, 327527a6266SJeff Kirsher B3_RI_WTO_R2 = 0x0196, 328527a6266SJeff Kirsher B3_RI_WTO_XA2 = 0x0197, 329527a6266SJeff Kirsher B3_RI_WTO_XS2 = 0x0198, 330527a6266SJeff Kirsher B3_RI_RTO_R2 = 0x0199, 331527a6266SJeff Kirsher B3_RI_RTO_XA2 = 0x019a, 332527a6266SJeff Kirsher B3_RI_RTO_XS2 = 0x019b, 333527a6266SJeff Kirsher B3_RI_TO_VAL = 0x019c, 334527a6266SJeff Kirsher B3_RI_CTRL = 0x01a0, 335527a6266SJeff Kirsher B3_RI_TEST = 0x01a2, 336527a6266SJeff Kirsher B3_MA_TOINI_RX1 = 0x01b0, 337527a6266SJeff Kirsher B3_MA_TOINI_RX2 = 0x01b1, 338527a6266SJeff Kirsher B3_MA_TOINI_TX1 = 0x01b2, 339527a6266SJeff Kirsher B3_MA_TOINI_TX2 = 0x01b3, 340527a6266SJeff Kirsher B3_MA_TOVAL_RX1 = 0x01b4, 341527a6266SJeff Kirsher B3_MA_TOVAL_RX2 = 0x01b5, 342527a6266SJeff Kirsher B3_MA_TOVAL_TX1 = 0x01b6, 343527a6266SJeff Kirsher B3_MA_TOVAL_TX2 = 0x01b7, 344527a6266SJeff Kirsher B3_MA_TO_CTRL = 0x01b8, 345527a6266SJeff Kirsher B3_MA_TO_TEST = 0x01ba, 346527a6266SJeff Kirsher B3_MA_RCINI_RX1 = 0x01c0, 347527a6266SJeff Kirsher B3_MA_RCINI_RX2 = 0x01c1, 348527a6266SJeff Kirsher B3_MA_RCINI_TX1 = 0x01c2, 349527a6266SJeff Kirsher B3_MA_RCINI_TX2 = 0x01c3, 350527a6266SJeff Kirsher B3_MA_RCVAL_RX1 = 0x01c4, 351527a6266SJeff Kirsher B3_MA_RCVAL_RX2 = 0x01c5, 352527a6266SJeff Kirsher B3_MA_RCVAL_TX1 = 0x01c6, 353527a6266SJeff Kirsher B3_MA_RCVAL_TX2 = 0x01c7, 354527a6266SJeff Kirsher B3_MA_RC_CTRL = 0x01c8, 355527a6266SJeff Kirsher B3_MA_RC_TEST = 0x01ca, 356527a6266SJeff Kirsher B3_PA_TOINI_RX1 = 0x01d0, 357527a6266SJeff Kirsher B3_PA_TOINI_RX2 = 0x01d4, 358527a6266SJeff Kirsher B3_PA_TOINI_TX1 = 0x01d8, 359527a6266SJeff Kirsher B3_PA_TOINI_TX2 = 0x01dc, 360527a6266SJeff Kirsher B3_PA_TOVAL_RX1 = 0x01e0, 361527a6266SJeff Kirsher B3_PA_TOVAL_RX2 = 0x01e4, 362527a6266SJeff Kirsher B3_PA_TOVAL_TX1 = 0x01e8, 363527a6266SJeff Kirsher B3_PA_TOVAL_TX2 = 0x01ec, 364527a6266SJeff Kirsher B3_PA_CTRL = 0x01f0, 365527a6266SJeff Kirsher B3_PA_TEST = 0x01f2, 366527a6266SJeff Kirsher 367527a6266SJeff Kirsher Y2_CFG_SPC = 0x1c00, /* PCI config space region */ 368527a6266SJeff Kirsher Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */ 369527a6266SJeff Kirsher }; 370527a6266SJeff Kirsher 371527a6266SJeff Kirsher /* B0_CTST 24 bit Control/Status register */ 372527a6266SJeff Kirsher enum { 373527a6266SJeff Kirsher Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */ 374527a6266SJeff Kirsher Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */ 375527a6266SJeff Kirsher Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */ 376527a6266SJeff Kirsher Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */ 377527a6266SJeff Kirsher Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */ 378527a6266SJeff Kirsher Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */ 379527a6266SJeff Kirsher Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */ 380527a6266SJeff Kirsher Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */ 381527a6266SJeff Kirsher Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */ 382527a6266SJeff Kirsher Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */ 383527a6266SJeff Kirsher 384527a6266SJeff Kirsher CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */ 385527a6266SJeff Kirsher CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */ 386527a6266SJeff Kirsher CS_STOP_DONE = 1<<5, /* Stop Master is finished */ 387527a6266SJeff Kirsher CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */ 388527a6266SJeff Kirsher CS_MRST_CLR = 1<<3, /* Clear Master reset */ 389527a6266SJeff Kirsher CS_MRST_SET = 1<<2, /* Set Master reset */ 390527a6266SJeff Kirsher CS_RST_CLR = 1<<1, /* Clear Software reset */ 391527a6266SJeff Kirsher CS_RST_SET = 1, /* Set Software reset */ 392527a6266SJeff Kirsher }; 393527a6266SJeff Kirsher 394527a6266SJeff Kirsher /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 395527a6266SJeff Kirsher enum { 396527a6266SJeff Kirsher PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */ 397527a6266SJeff Kirsher PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */ 398527a6266SJeff Kirsher PC_VCC_ENA = 1<<5, /* Switch VCC Enable */ 399527a6266SJeff Kirsher PC_VCC_DIS = 1<<4, /* Switch VCC Disable */ 400527a6266SJeff Kirsher PC_VAUX_ON = 1<<3, /* Switch VAUX On */ 401527a6266SJeff Kirsher PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */ 402527a6266SJeff Kirsher PC_VCC_ON = 1<<1, /* Switch VCC On */ 403527a6266SJeff Kirsher PC_VCC_OFF = 1<<0, /* Switch VCC Off */ 404527a6266SJeff Kirsher }; 405527a6266SJeff Kirsher 406527a6266SJeff Kirsher /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 407527a6266SJeff Kirsher 408527a6266SJeff Kirsher /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 409527a6266SJeff Kirsher /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 410527a6266SJeff Kirsher /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 411527a6266SJeff Kirsher /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 412527a6266SJeff Kirsher enum { 413527a6266SJeff Kirsher Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */ 414527a6266SJeff Kirsher Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */ 415527a6266SJeff Kirsher Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */ 416527a6266SJeff Kirsher Y2_IS_CPU_TO = 1<<28, /* CPU Timeout */ 417527a6266SJeff Kirsher Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */ 418527a6266SJeff Kirsher Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */ 419527a6266SJeff Kirsher Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */ 420527a6266SJeff Kirsher Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */ 421527a6266SJeff Kirsher 422527a6266SJeff Kirsher Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */ 423527a6266SJeff Kirsher Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */ 424527a6266SJeff Kirsher Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */ 425527a6266SJeff Kirsher Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */ 426527a6266SJeff Kirsher Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */ 427527a6266SJeff Kirsher 428527a6266SJeff Kirsher Y2_IS_PSM_ACK = 1<<7, /* PSM Acknowledge (Yukon-Optima only) */ 429527a6266SJeff Kirsher Y2_IS_PTP_TIST = 1<<6, /* PTP Time Stamp (Yukon-Optima only) */ 430527a6266SJeff Kirsher Y2_IS_PHY_QLNK = 1<<5, /* PHY Quick Link (Yukon-Optima only) */ 431527a6266SJeff Kirsher 432527a6266SJeff Kirsher Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */ 433527a6266SJeff Kirsher Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */ 434527a6266SJeff Kirsher Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */ 435527a6266SJeff Kirsher Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */ 436527a6266SJeff Kirsher Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */ 437527a6266SJeff Kirsher 438527a6266SJeff Kirsher Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, 439527a6266SJeff Kirsher Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 440527a6266SJeff Kirsher | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1, 441527a6266SJeff Kirsher Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 442527a6266SJeff Kirsher | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 443527a6266SJeff Kirsher Y2_IS_ERROR = Y2_IS_HW_ERR | 444527a6266SJeff Kirsher Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 | 445527a6266SJeff Kirsher Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2, 446527a6266SJeff Kirsher }; 447527a6266SJeff Kirsher 448527a6266SJeff Kirsher /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 449527a6266SJeff Kirsher enum { 450527a6266SJeff Kirsher IS_ERR_MSK = 0x00003fff,/* All Error bits */ 451527a6266SJeff Kirsher 452527a6266SJeff Kirsher IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */ 453527a6266SJeff Kirsher IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */ 454527a6266SJeff Kirsher IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */ 455527a6266SJeff Kirsher IS_IRQ_STAT = 1<<10, /* IRQ status exception */ 456527a6266SJeff Kirsher IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */ 457527a6266SJeff Kirsher IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */ 458527a6266SJeff Kirsher IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */ 459527a6266SJeff Kirsher IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */ 460527a6266SJeff Kirsher IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */ 461527a6266SJeff Kirsher IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */ 462527a6266SJeff Kirsher IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */ 463527a6266SJeff Kirsher IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */ 464527a6266SJeff Kirsher IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */ 465527a6266SJeff Kirsher IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */ 466527a6266SJeff Kirsher }; 467527a6266SJeff Kirsher 468527a6266SJeff Kirsher /* Hardware error interrupt mask for Yukon 2 */ 469527a6266SJeff Kirsher enum { 470527a6266SJeff Kirsher Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */ 471527a6266SJeff Kirsher Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */ 472527a6266SJeff Kirsher Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */ 473527a6266SJeff Kirsher Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */ 474527a6266SJeff Kirsher Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */ 475527a6266SJeff Kirsher Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */ 476527a6266SJeff Kirsher /* Link 2 */ 477527a6266SJeff Kirsher Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */ 478527a6266SJeff Kirsher Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */ 479527a6266SJeff Kirsher Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */ 480527a6266SJeff Kirsher Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */ 481527a6266SJeff Kirsher Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */ 482527a6266SJeff Kirsher Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */ 483527a6266SJeff Kirsher /* Link 1 */ 484527a6266SJeff Kirsher Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */ 485527a6266SJeff Kirsher Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */ 486527a6266SJeff Kirsher Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */ 487527a6266SJeff Kirsher Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */ 488527a6266SJeff Kirsher Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */ 489527a6266SJeff Kirsher Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */ 490527a6266SJeff Kirsher 491527a6266SJeff Kirsher Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 | 492527a6266SJeff Kirsher Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1, 493527a6266SJeff Kirsher Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 | 494527a6266SJeff Kirsher Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2, 495527a6266SJeff Kirsher 496527a6266SJeff Kirsher Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | 497527a6266SJeff Kirsher Y2_HWE_L1_MASK | Y2_HWE_L2_MASK, 498527a6266SJeff Kirsher }; 499527a6266SJeff Kirsher 500527a6266SJeff Kirsher /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 501527a6266SJeff Kirsher enum { 502527a6266SJeff Kirsher DPT_START = 1<<1, 503527a6266SJeff Kirsher DPT_STOP = 1<<0, 504527a6266SJeff Kirsher }; 505527a6266SJeff Kirsher 506527a6266SJeff Kirsher /* B2_TST_CTRL1 8 bit Test Control Register 1 */ 507527a6266SJeff Kirsher enum { 508527a6266SJeff Kirsher TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */ 509527a6266SJeff Kirsher TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */ 510527a6266SJeff Kirsher TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */ 511527a6266SJeff Kirsher TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */ 512527a6266SJeff Kirsher TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */ 513527a6266SJeff Kirsher TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */ 514527a6266SJeff Kirsher TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */ 515527a6266SJeff Kirsher TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ 516527a6266SJeff Kirsher }; 517527a6266SJeff Kirsher 518527a6266SJeff Kirsher /* B2_GPIO */ 519527a6266SJeff Kirsher enum { 520527a6266SJeff Kirsher GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */ 521527a6266SJeff Kirsher GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */ 522527a6266SJeff Kirsher 523527a6266SJeff Kirsher GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */ 524527a6266SJeff Kirsher GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */ 525527a6266SJeff Kirsher GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */ 526527a6266SJeff Kirsher GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */ 527527a6266SJeff Kirsher GLB_GPIO_TEST_SEL_BASE = 1<<11, 528527a6266SJeff Kirsher GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */ 529527a6266SJeff Kirsher GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */ 530527a6266SJeff Kirsher }; 531527a6266SJeff Kirsher 532527a6266SJeff Kirsher /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 533527a6266SJeff Kirsher enum { 534527a6266SJeff Kirsher CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ 535527a6266SJeff Kirsher /* Bit 3.. 2: reserved */ 536527a6266SJeff Kirsher CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */ 537527a6266SJeff Kirsher CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/ 538527a6266SJeff Kirsher }; 539527a6266SJeff Kirsher 540527a6266SJeff Kirsher /* B2_CHIP_ID 8 bit Chip Identification Number */ 541527a6266SJeff Kirsher enum { 542527a6266SJeff Kirsher CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */ 543527a6266SJeff Kirsher CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */ 544527a6266SJeff Kirsher CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */ 545527a6266SJeff Kirsher CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */ 546527a6266SJeff Kirsher CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */ 547527a6266SJeff Kirsher CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */ 548527a6266SJeff Kirsher CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */ 549527a6266SJeff Kirsher CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */ 550527a6266SJeff Kirsher CHIP_ID_YUKON_OPT = 0xbc, /* YUKON-2 Optima */ 551527a6266SJeff Kirsher CHIP_ID_YUKON_PRM = 0xbd, /* YUKON-2 Optima Prime */ 552527a6266SJeff Kirsher CHIP_ID_YUKON_OP_2 = 0xbe, /* YUKON-2 Optima 2 */ 553527a6266SJeff Kirsher }; 554527a6266SJeff Kirsher 555527a6266SJeff Kirsher enum yukon_xl_rev { 556527a6266SJeff Kirsher CHIP_REV_YU_XL_A0 = 0, 557527a6266SJeff Kirsher CHIP_REV_YU_XL_A1 = 1, 558527a6266SJeff Kirsher CHIP_REV_YU_XL_A2 = 2, 559527a6266SJeff Kirsher CHIP_REV_YU_XL_A3 = 3, 560527a6266SJeff Kirsher }; 561527a6266SJeff Kirsher 562527a6266SJeff Kirsher enum yukon_ec_rev { 563527a6266SJeff Kirsher CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */ 564527a6266SJeff Kirsher CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */ 565527a6266SJeff Kirsher CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */ 566527a6266SJeff Kirsher }; 567527a6266SJeff Kirsher enum yukon_ec_u_rev { 568527a6266SJeff Kirsher CHIP_REV_YU_EC_U_A0 = 1, 569527a6266SJeff Kirsher CHIP_REV_YU_EC_U_A1 = 2, 570527a6266SJeff Kirsher CHIP_REV_YU_EC_U_B0 = 3, 571527a6266SJeff Kirsher CHIP_REV_YU_EC_U_B1 = 5, 572527a6266SJeff Kirsher }; 573527a6266SJeff Kirsher enum yukon_fe_rev { 574527a6266SJeff Kirsher CHIP_REV_YU_FE_A1 = 1, 575527a6266SJeff Kirsher CHIP_REV_YU_FE_A2 = 2, 576527a6266SJeff Kirsher }; 577527a6266SJeff Kirsher enum yukon_fe_p_rev { 578527a6266SJeff Kirsher CHIP_REV_YU_FE2_A0 = 0, 579527a6266SJeff Kirsher }; 580527a6266SJeff Kirsher enum yukon_ex_rev { 581527a6266SJeff Kirsher CHIP_REV_YU_EX_A0 = 1, 582527a6266SJeff Kirsher CHIP_REV_YU_EX_B0 = 2, 583527a6266SJeff Kirsher }; 584527a6266SJeff Kirsher enum yukon_supr_rev { 585527a6266SJeff Kirsher CHIP_REV_YU_SU_A0 = 0, 586527a6266SJeff Kirsher CHIP_REV_YU_SU_B0 = 1, 587527a6266SJeff Kirsher CHIP_REV_YU_SU_B1 = 3, 588527a6266SJeff Kirsher }; 589527a6266SJeff Kirsher 5900e767324SMirko Lindner enum yukon_prm_rev { 5910e767324SMirko Lindner CHIP_REV_YU_PRM_Z1 = 1, 5920e767324SMirko Lindner CHIP_REV_YU_PRM_A0 = 2, 5930e767324SMirko Lindner }; 594527a6266SJeff Kirsher 595527a6266SJeff Kirsher /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 596527a6266SJeff Kirsher enum { 597527a6266SJeff Kirsher Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */ 598527a6266SJeff Kirsher Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */ 599527a6266SJeff Kirsher Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */ 600527a6266SJeff Kirsher Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */ 601527a6266SJeff Kirsher Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */ 602527a6266SJeff Kirsher Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */ 603527a6266SJeff Kirsher Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */ 604527a6266SJeff Kirsher Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */ 605527a6266SJeff Kirsher }; 606527a6266SJeff Kirsher 607527a6266SJeff Kirsher /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 608527a6266SJeff Kirsher enum { 609527a6266SJeff Kirsher CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */ 610527a6266SJeff Kirsher CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */ 611527a6266SJeff Kirsher CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */ 612527a6266SJeff Kirsher }; 613527a6266SJeff Kirsher #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 614527a6266SJeff Kirsher #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 615527a6266SJeff Kirsher 616527a6266SJeff Kirsher 617527a6266SJeff Kirsher /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */ 618527a6266SJeff Kirsher enum { 619527a6266SJeff Kirsher Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */ 620527a6266SJeff Kirsher #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK) 621527a6266SJeff Kirsher Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */ 622527a6266SJeff Kirsher Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */ 623527a6266SJeff Kirsher #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK) 624527a6266SJeff Kirsher #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK) 625527a6266SJeff Kirsher Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */ 626527a6266SJeff Kirsher Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */ 627527a6266SJeff Kirsher }; 628527a6266SJeff Kirsher 629527a6266SJeff Kirsher /* B2_TI_CTRL 8 bit Timer control */ 630527a6266SJeff Kirsher /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 631527a6266SJeff Kirsher enum { 632527a6266SJeff Kirsher TIM_START = 1<<2, /* Start Timer */ 633527a6266SJeff Kirsher TIM_STOP = 1<<1, /* Stop Timer */ 634527a6266SJeff Kirsher TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */ 635527a6266SJeff Kirsher }; 636527a6266SJeff Kirsher 637527a6266SJeff Kirsher /* B2_TI_TEST 8 Bit Timer Test */ 638527a6266SJeff Kirsher /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 639527a6266SJeff Kirsher /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 640527a6266SJeff Kirsher enum { 641527a6266SJeff Kirsher TIM_T_ON = 1<<2, /* Test mode on */ 642527a6266SJeff Kirsher TIM_T_OFF = 1<<1, /* Test mode off */ 643527a6266SJeff Kirsher TIM_T_STEP = 1<<0, /* Test step */ 644527a6266SJeff Kirsher }; 645527a6266SJeff Kirsher 646527a6266SJeff Kirsher /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 647527a6266SJeff Kirsher enum { 648527a6266SJeff Kirsher PEX_RD_ACCESS = 1<<31, /* Access Mode Read = 1, Write = 0 */ 649527a6266SJeff Kirsher PEX_DB_ACCESS = 1<<30, /* Access to debug register */ 650527a6266SJeff Kirsher }; 651527a6266SJeff Kirsher 652527a6266SJeff Kirsher /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 653527a6266SJeff Kirsher /* Bit 31..19: reserved */ 654527a6266SJeff Kirsher #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */ 655527a6266SJeff Kirsher /* RAM Interface Registers */ 656527a6266SJeff Kirsher 657527a6266SJeff Kirsher /* B3_RI_CTRL 16 bit RAM Interface Control Register */ 658527a6266SJeff Kirsher enum { 659527a6266SJeff Kirsher RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */ 660527a6266SJeff Kirsher RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/ 661527a6266SJeff Kirsher 662527a6266SJeff Kirsher RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */ 663527a6266SJeff Kirsher RI_RST_SET = 1<<0, /* Set RAM Interface Reset */ 664527a6266SJeff Kirsher }; 665527a6266SJeff Kirsher 666527a6266SJeff Kirsher #define SK_RI_TO_53 36 /* RAM interface timeout */ 667527a6266SJeff Kirsher 668527a6266SJeff Kirsher 669527a6266SJeff Kirsher /* Port related registers FIFO, and Arbiter */ 670527a6266SJeff Kirsher #define SK_REG(port,reg) (((port)<<7)+(reg)) 671527a6266SJeff Kirsher 672527a6266SJeff Kirsher /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 673527a6266SJeff Kirsher /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 674527a6266SJeff Kirsher /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 675527a6266SJeff Kirsher /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 676527a6266SJeff Kirsher /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 677527a6266SJeff Kirsher 678527a6266SJeff Kirsher #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */ 679527a6266SJeff Kirsher 680527a6266SJeff Kirsher /* TXA_CTRL 8 bit Tx Arbiter Control Register */ 681527a6266SJeff Kirsher enum { 682527a6266SJeff Kirsher TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */ 683527a6266SJeff Kirsher TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */ 684527a6266SJeff Kirsher TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */ 685527a6266SJeff Kirsher TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */ 686527a6266SJeff Kirsher TXA_START_RC = 1<<3, /* Start sync Rate Control */ 687527a6266SJeff Kirsher TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */ 688527a6266SJeff Kirsher TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */ 689527a6266SJeff Kirsher TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */ 690527a6266SJeff Kirsher }; 691527a6266SJeff Kirsher 692527a6266SJeff Kirsher /* 693527a6266SJeff Kirsher * Bank 4 - 5 694527a6266SJeff Kirsher */ 695527a6266SJeff Kirsher /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */ 696527a6266SJeff Kirsher enum { 697527a6266SJeff Kirsher TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/ 698527a6266SJeff Kirsher TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */ 699527a6266SJeff Kirsher TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */ 700527a6266SJeff Kirsher TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */ 701527a6266SJeff Kirsher TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */ 702527a6266SJeff Kirsher TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */ 703527a6266SJeff Kirsher TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */ 704527a6266SJeff Kirsher 705527a6266SJeff Kirsher RSS_KEY = 0x0220, /* RSS Key setup */ 706527a6266SJeff Kirsher RSS_CFG = 0x0248, /* RSS Configuration */ 707527a6266SJeff Kirsher }; 708527a6266SJeff Kirsher 709527a6266SJeff Kirsher enum { 710527a6266SJeff Kirsher HASH_TCP_IPV6_EX_CTRL = 1<<5, 711527a6266SJeff Kirsher HASH_IPV6_EX_CTRL = 1<<4, 712527a6266SJeff Kirsher HASH_TCP_IPV6_CTRL = 1<<3, 713527a6266SJeff Kirsher HASH_IPV6_CTRL = 1<<2, 714527a6266SJeff Kirsher HASH_TCP_IPV4_CTRL = 1<<1, 715527a6266SJeff Kirsher HASH_IPV4_CTRL = 1<<0, 716527a6266SJeff Kirsher 717527a6266SJeff Kirsher HASH_ALL = 0x3f, 718527a6266SJeff Kirsher }; 719527a6266SJeff Kirsher 720527a6266SJeff Kirsher enum { 721527a6266SJeff Kirsher B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */ 722527a6266SJeff Kirsher B7_CFG_SPC = 0x0380,/* copy of the Configuration register */ 723527a6266SJeff Kirsher B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */ 724527a6266SJeff Kirsher B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */ 725527a6266SJeff Kirsher B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */ 726527a6266SJeff Kirsher B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */ 727527a6266SJeff Kirsher B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */ 728527a6266SJeff Kirsher B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */ 729527a6266SJeff Kirsher B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */ 730527a6266SJeff Kirsher }; 731527a6266SJeff Kirsher 732527a6266SJeff Kirsher /* Queue Register Offsets, use Q_ADDR() to access */ 733527a6266SJeff Kirsher enum { 734527a6266SJeff Kirsher B8_Q_REGS = 0x0400, /* base of Queue registers */ 735527a6266SJeff Kirsher Q_D = 0x00, /* 8*32 bit Current Descriptor */ 736527a6266SJeff Kirsher Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */ 737527a6266SJeff Kirsher Q_DONE = 0x24, /* 16 bit Done Index */ 738527a6266SJeff Kirsher Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */ 739527a6266SJeff Kirsher Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */ 740527a6266SJeff Kirsher Q_BC = 0x30, /* 32 bit Current Byte Counter */ 741527a6266SJeff Kirsher Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */ 742527a6266SJeff Kirsher Q_TEST = 0x38, /* 32 bit Test/Control Register */ 743527a6266SJeff Kirsher 744527a6266SJeff Kirsher /* Yukon-2 */ 745527a6266SJeff Kirsher Q_WM = 0x40, /* 16 bit FIFO Watermark */ 746527a6266SJeff Kirsher Q_AL = 0x42, /* 8 bit FIFO Alignment */ 747527a6266SJeff Kirsher Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */ 748527a6266SJeff Kirsher Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */ 749527a6266SJeff Kirsher Q_RP = 0x48, /* 8 bit FIFO Read Pointer */ 750527a6266SJeff Kirsher Q_RL = 0x4a, /* 8 bit FIFO Read Level */ 751527a6266SJeff Kirsher Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */ 752527a6266SJeff Kirsher Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */ 753527a6266SJeff Kirsher Q_WL = 0x4e, /* 8 bit FIFO Write Level */ 754527a6266SJeff Kirsher Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */ 755527a6266SJeff Kirsher }; 756527a6266SJeff Kirsher #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs)) 757527a6266SJeff Kirsher 758527a6266SJeff Kirsher /* Q_TEST 32 bit Test Register */ 759527a6266SJeff Kirsher enum { 760527a6266SJeff Kirsher /* Transmit */ 761527a6266SJeff Kirsher F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */ 762527a6266SJeff Kirsher F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */ 763527a6266SJeff Kirsher 764527a6266SJeff Kirsher /* Receive */ 765527a6266SJeff Kirsher F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */ 766527a6266SJeff Kirsher 767527a6266SJeff Kirsher /* Hardware testbits not used */ 768527a6266SJeff Kirsher }; 769527a6266SJeff Kirsher 770527a6266SJeff Kirsher /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 771527a6266SJeff Kirsher enum { 772527a6266SJeff Kirsher Y2_B8_PREF_REGS = 0x0450, 773527a6266SJeff Kirsher 774527a6266SJeff Kirsher PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */ 775527a6266SJeff Kirsher PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */ 776527a6266SJeff Kirsher PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */ 777527a6266SJeff Kirsher PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/ 778527a6266SJeff Kirsher PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */ 779527a6266SJeff Kirsher PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */ 780527a6266SJeff Kirsher PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */ 781527a6266SJeff Kirsher PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */ 782527a6266SJeff Kirsher PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */ 783527a6266SJeff Kirsher PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */ 784527a6266SJeff Kirsher 785527a6266SJeff Kirsher PREF_UNIT_MASK_IDX = 0x0fff, 786527a6266SJeff Kirsher }; 787527a6266SJeff Kirsher #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg)) 788527a6266SJeff Kirsher 789527a6266SJeff Kirsher /* RAM Buffer Register Offsets */ 790527a6266SJeff Kirsher enum { 791527a6266SJeff Kirsher 792527a6266SJeff Kirsher RB_START = 0x00,/* 32 bit RAM Buffer Start Address */ 793527a6266SJeff Kirsher RB_END = 0x04,/* 32 bit RAM Buffer End Address */ 794527a6266SJeff Kirsher RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */ 795527a6266SJeff Kirsher RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */ 796527a6266SJeff Kirsher RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */ 797527a6266SJeff Kirsher RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */ 798527a6266SJeff Kirsher RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */ 799527a6266SJeff Kirsher RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */ 800527a6266SJeff Kirsher /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */ 801527a6266SJeff Kirsher RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */ 802527a6266SJeff Kirsher RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */ 803527a6266SJeff Kirsher RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */ 804527a6266SJeff Kirsher RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */ 805527a6266SJeff Kirsher RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */ 806527a6266SJeff Kirsher }; 807527a6266SJeff Kirsher 808527a6266SJeff Kirsher /* Receive and Transmit Queues */ 809527a6266SJeff Kirsher enum { 810527a6266SJeff Kirsher Q_R1 = 0x0000, /* Receive Queue 1 */ 811527a6266SJeff Kirsher Q_R2 = 0x0080, /* Receive Queue 2 */ 812527a6266SJeff Kirsher Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */ 813527a6266SJeff Kirsher Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */ 814527a6266SJeff Kirsher Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */ 815527a6266SJeff Kirsher Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */ 816527a6266SJeff Kirsher }; 817527a6266SJeff Kirsher 818527a6266SJeff Kirsher /* Different PHY Types */ 819527a6266SJeff Kirsher enum { 820527a6266SJeff Kirsher PHY_ADDR_MARV = 0, 821527a6266SJeff Kirsher }; 822527a6266SJeff Kirsher 823527a6266SJeff Kirsher #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs)) 824527a6266SJeff Kirsher 825527a6266SJeff Kirsher 826527a6266SJeff Kirsher enum { 827527a6266SJeff Kirsher LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */ 828527a6266SJeff Kirsher LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */ 829527a6266SJeff Kirsher LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */ 830527a6266SJeff Kirsher LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */ 831527a6266SJeff Kirsher 832527a6266SJeff Kirsher LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */ 833527a6266SJeff Kirsher 834527a6266SJeff Kirsher /* Receive GMAC FIFO (YUKON and Yukon-2) */ 835527a6266SJeff Kirsher 836527a6266SJeff Kirsher RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */ 837527a6266SJeff Kirsher RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 838527a6266SJeff Kirsher RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */ 839527a6266SJeff Kirsher RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */ 840527a6266SJeff Kirsher RX_GMF_FL_THR = 0x0c50,/* 16 bit Rx GMAC FIFO Flush Threshold */ 841527a6266SJeff Kirsher RX_GMF_FL_CTRL = 0x0c52,/* 16 bit Rx GMAC FIFO Flush Control */ 842527a6266SJeff Kirsher RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */ 843527a6266SJeff Kirsher RX_GMF_UP_THR = 0x0c58,/* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ 844527a6266SJeff Kirsher RX_GMF_LP_THR = 0x0c5a,/* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ 845527a6266SJeff Kirsher RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */ 846527a6266SJeff Kirsher RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */ 847527a6266SJeff Kirsher 848527a6266SJeff Kirsher RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */ 849527a6266SJeff Kirsher 850527a6266SJeff Kirsher RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */ 851527a6266SJeff Kirsher 852527a6266SJeff Kirsher RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */ 853527a6266SJeff Kirsher }; 854527a6266SJeff Kirsher 855527a6266SJeff Kirsher 856527a6266SJeff Kirsher /* Q_BC 32 bit Current Byte Counter */ 857527a6266SJeff Kirsher 858527a6266SJeff Kirsher /* BMU Control Status Registers */ 859527a6266SJeff Kirsher /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */ 860527a6266SJeff Kirsher /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */ 861527a6266SJeff Kirsher /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */ 862527a6266SJeff Kirsher /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */ 863527a6266SJeff Kirsher /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */ 864527a6266SJeff Kirsher /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */ 865527a6266SJeff Kirsher /* Q_CSR 32 bit BMU Control/Status Register */ 866527a6266SJeff Kirsher 867527a6266SJeff Kirsher /* Rx BMU Control / Status Registers (Yukon-2) */ 868527a6266SJeff Kirsher enum { 869527a6266SJeff Kirsher BMU_IDLE = 1<<31, /* BMU Idle State */ 870527a6266SJeff Kirsher BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */ 871527a6266SJeff Kirsher BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */ 872527a6266SJeff Kirsher 873527a6266SJeff Kirsher BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */ 874527a6266SJeff Kirsher BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */ 875527a6266SJeff Kirsher BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */ 876527a6266SJeff Kirsher BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */ 877527a6266SJeff Kirsher BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */ 878527a6266SJeff Kirsher BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */ 879527a6266SJeff Kirsher BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */ 880527a6266SJeff Kirsher BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */ 881527a6266SJeff Kirsher BMU_START = 1<<8, /* Start Rx/Tx Queue */ 882527a6266SJeff Kirsher BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */ 883527a6266SJeff Kirsher BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */ 884527a6266SJeff Kirsher BMU_FIFO_ENA = 1<<5, /* Enable FIFO */ 885527a6266SJeff Kirsher BMU_FIFO_RST = 1<<4, /* Reset FIFO */ 886527a6266SJeff Kirsher BMU_OP_ON = 1<<3, /* BMU Operational On */ 887527a6266SJeff Kirsher BMU_OP_OFF = 1<<2, /* BMU Operational Off */ 888527a6266SJeff Kirsher BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */ 889527a6266SJeff Kirsher BMU_RST_SET = 1<<0, /* Set BMU Reset */ 890527a6266SJeff Kirsher 891527a6266SJeff Kirsher BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, 892527a6266SJeff Kirsher BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | 893527a6266SJeff Kirsher BMU_FIFO_ENA | BMU_OP_ON, 894527a6266SJeff Kirsher 895527a6266SJeff Kirsher BMU_WM_DEFAULT = 0x600, 896527a6266SJeff Kirsher BMU_WM_PEX = 0x80, 897527a6266SJeff Kirsher }; 898527a6266SJeff Kirsher 899527a6266SJeff Kirsher /* Tx BMU Control / Status Registers (Yukon-2) */ 900527a6266SJeff Kirsher /* Bit 31: same as for Rx */ 901527a6266SJeff Kirsher enum { 902527a6266SJeff Kirsher BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */ 903527a6266SJeff Kirsher BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */ 904527a6266SJeff Kirsher BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */ 905527a6266SJeff Kirsher }; 906527a6266SJeff Kirsher 907527a6266SJeff Kirsher /* TBMU_TEST 0x06B8 Transmit BMU Test Register */ 908527a6266SJeff Kirsher enum { 909527a6266SJeff Kirsher TBMU_TEST_BMU_TX_CHK_AUTO_OFF = 1<<31, /* BMU Tx Checksum Auto Calculation Disable */ 910527a6266SJeff Kirsher TBMU_TEST_BMU_TX_CHK_AUTO_ON = 1<<30, /* BMU Tx Checksum Auto Calculation Enable */ 911527a6266SJeff Kirsher TBMU_TEST_HOME_ADD_PAD_FIX1_EN = 1<<29, /* Home Address Paddiing FIX1 Enable */ 912527a6266SJeff Kirsher TBMU_TEST_HOME_ADD_PAD_FIX1_DIS = 1<<28, /* Home Address Paddiing FIX1 Disable */ 913527a6266SJeff Kirsher TBMU_TEST_ROUTING_ADD_FIX_EN = 1<<27, /* Routing Address Fix Enable */ 914527a6266SJeff Kirsher TBMU_TEST_ROUTING_ADD_FIX_DIS = 1<<26, /* Routing Address Fix Disable */ 915527a6266SJeff Kirsher TBMU_TEST_HOME_ADD_FIX_EN = 1<<25, /* Home address checksum fix enable */ 916527a6266SJeff Kirsher TBMU_TEST_HOME_ADD_FIX_DIS = 1<<24, /* Home address checksum fix disable */ 917527a6266SJeff Kirsher 918527a6266SJeff Kirsher TBMU_TEST_TEST_RSPTR_ON = 1<<22, /* Testmode Shadow Read Ptr On */ 919527a6266SJeff Kirsher TBMU_TEST_TEST_RSPTR_OFF = 1<<21, /* Testmode Shadow Read Ptr Off */ 920527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_RSPTR = 1<<20, /* Teststep Shadow Read Ptr */ 921527a6266SJeff Kirsher 922527a6266SJeff Kirsher TBMU_TEST_TEST_RPTR_ON = 1<<18, /* Testmode Read Ptr On */ 923527a6266SJeff Kirsher TBMU_TEST_TEST_RPTR_OFF = 1<<17, /* Testmode Read Ptr Off */ 924527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_RPTR = 1<<16, /* Teststep Read Ptr */ 925527a6266SJeff Kirsher 926527a6266SJeff Kirsher TBMU_TEST_TEST_WSPTR_ON = 1<<14, /* Testmode Shadow Write Ptr On */ 927527a6266SJeff Kirsher TBMU_TEST_TEST_WSPTR_OFF = 1<<13, /* Testmode Shadow Write Ptr Off */ 928527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_WSPTR = 1<<12, /* Teststep Shadow Write Ptr */ 929527a6266SJeff Kirsher 930527a6266SJeff Kirsher TBMU_TEST_TEST_WPTR_ON = 1<<10, /* Testmode Write Ptr On */ 931527a6266SJeff Kirsher TBMU_TEST_TEST_WPTR_OFF = 1<<9, /* Testmode Write Ptr Off */ 932527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_WPTR = 1<<8, /* Teststep Write Ptr */ 933527a6266SJeff Kirsher 934527a6266SJeff Kirsher TBMU_TEST_TEST_REQ_NB_ON = 1<<6, /* Testmode Req Nbytes/Addr On */ 935527a6266SJeff Kirsher TBMU_TEST_TEST_REQ_NB_OFF = 1<<5, /* Testmode Req Nbytes/Addr Off */ 936527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_REQ_NB = 1<<4, /* Teststep Req Nbytes/Addr */ 937527a6266SJeff Kirsher 938527a6266SJeff Kirsher TBMU_TEST_TEST_DONE_IDX_ON = 1<<2, /* Testmode Done Index On */ 939527a6266SJeff Kirsher TBMU_TEST_TEST_DONE_IDX_OFF = 1<<1, /* Testmode Done Index Off */ 940527a6266SJeff Kirsher TBMU_TEST_TESTSTEP_DONE_IDX = 1<<0, /* Teststep Done Index */ 941527a6266SJeff Kirsher }; 942527a6266SJeff Kirsher 943527a6266SJeff Kirsher /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/ 944527a6266SJeff Kirsher /* PREF_UNIT_CTRL 32 bit Prefetch Control register */ 945527a6266SJeff Kirsher enum { 946527a6266SJeff Kirsher PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */ 947527a6266SJeff Kirsher PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */ 948527a6266SJeff Kirsher PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */ 949527a6266SJeff Kirsher PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */ 950527a6266SJeff Kirsher }; 951527a6266SJeff Kirsher 952527a6266SJeff Kirsher /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 953527a6266SJeff Kirsher /* RB_START 32 bit RAM Buffer Start Address */ 954527a6266SJeff Kirsher /* RB_END 32 bit RAM Buffer End Address */ 955527a6266SJeff Kirsher /* RB_WP 32 bit RAM Buffer Write Pointer */ 956527a6266SJeff Kirsher /* RB_RP 32 bit RAM Buffer Read Pointer */ 957527a6266SJeff Kirsher /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 958527a6266SJeff Kirsher /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 959527a6266SJeff Kirsher /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 960527a6266SJeff Kirsher /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 961527a6266SJeff Kirsher /* RB_PC 32 bit RAM Buffer Packet Counter */ 962527a6266SJeff Kirsher /* RB_LEV 32 bit RAM Buffer Level Register */ 963527a6266SJeff Kirsher 964527a6266SJeff Kirsher #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 965527a6266SJeff Kirsher /* RB_TST2 8 bit RAM Buffer Test Register 2 */ 966527a6266SJeff Kirsher /* RB_TST1 8 bit RAM Buffer Test Register 1 */ 967527a6266SJeff Kirsher 968527a6266SJeff Kirsher /* RB_CTRL 8 bit RAM Buffer Control Register */ 969527a6266SJeff Kirsher enum { 970527a6266SJeff Kirsher RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */ 971527a6266SJeff Kirsher RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */ 972527a6266SJeff Kirsher RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */ 973527a6266SJeff Kirsher RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */ 974527a6266SJeff Kirsher RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */ 975527a6266SJeff Kirsher RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */ 976527a6266SJeff Kirsher }; 977527a6266SJeff Kirsher 978527a6266SJeff Kirsher 979527a6266SJeff Kirsher /* Transmit GMAC FIFO (YUKON only) */ 980527a6266SJeff Kirsher enum { 981527a6266SJeff Kirsher TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */ 982527a6266SJeff Kirsher TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 983527a6266SJeff Kirsher TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */ 984527a6266SJeff Kirsher 985527a6266SJeff Kirsher TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */ 986527a6266SJeff Kirsher TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */ 987527a6266SJeff Kirsher TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */ 988527a6266SJeff Kirsher 989527a6266SJeff Kirsher TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */ 990527a6266SJeff Kirsher TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */ 991527a6266SJeff Kirsher TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */ 992527a6266SJeff Kirsher 993527a6266SJeff Kirsher /* Threshold values for Yukon-EC Ultra and Extreme */ 994527a6266SJeff Kirsher ECU_AE_THR = 0x0070, /* Almost Empty Threshold */ 995527a6266SJeff Kirsher ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */ 996527a6266SJeff Kirsher ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */ 997527a6266SJeff Kirsher }; 998527a6266SJeff Kirsher 999527a6266SJeff Kirsher /* Descriptor Poll Timer Registers */ 1000527a6266SJeff Kirsher enum { 1001527a6266SJeff Kirsher B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */ 1002527a6266SJeff Kirsher B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */ 1003527a6266SJeff Kirsher B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */ 1004527a6266SJeff Kirsher 1005527a6266SJeff Kirsher B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */ 1006527a6266SJeff Kirsher }; 1007527a6266SJeff Kirsher 1008527a6266SJeff Kirsher /* Time Stamp Timer Registers (YUKON only) */ 1009527a6266SJeff Kirsher enum { 1010527a6266SJeff Kirsher GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */ 1011527a6266SJeff Kirsher GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */ 1012527a6266SJeff Kirsher GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */ 1013527a6266SJeff Kirsher }; 1014527a6266SJeff Kirsher 1015527a6266SJeff Kirsher /* Polling Unit Registers (Yukon-2 only) */ 1016527a6266SJeff Kirsher enum { 1017527a6266SJeff Kirsher POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */ 1018527a6266SJeff Kirsher POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */ 1019527a6266SJeff Kirsher 1020527a6266SJeff Kirsher POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */ 1021527a6266SJeff Kirsher POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ 1022527a6266SJeff Kirsher }; 1023527a6266SJeff Kirsher 1024527a6266SJeff Kirsher enum { 1025527a6266SJeff Kirsher SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */ 1026527a6266SJeff Kirsher SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */ 1027527a6266SJeff Kirsher }; 1028527a6266SJeff Kirsher 1029527a6266SJeff Kirsher enum { 1030527a6266SJeff Kirsher CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */ 1031527a6266SJeff Kirsher CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */ 1032527a6266SJeff Kirsher CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */ 1033527a6266SJeff Kirsher CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */ 1034527a6266SJeff Kirsher CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */ 1035527a6266SJeff Kirsher CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */ 1036527a6266SJeff Kirsher HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */ 1037527a6266SJeff Kirsher CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */ 1038527a6266SJeff Kirsher HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */ 1039527a6266SJeff Kirsher HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */ 1040527a6266SJeff Kirsher }; 1041527a6266SJeff Kirsher 1042527a6266SJeff Kirsher /* ASF Subsystem Registers (Yukon-2 only) */ 1043527a6266SJeff Kirsher enum { 1044527a6266SJeff Kirsher B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ 1045527a6266SJeff Kirsher B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */ 1046527a6266SJeff Kirsher B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */ 1047527a6266SJeff Kirsher 1048527a6266SJeff Kirsher B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */ 1049527a6266SJeff Kirsher B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */ 1050527a6266SJeff Kirsher B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */ 1051527a6266SJeff Kirsher B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */ 1052527a6266SJeff Kirsher B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */ 1053527a6266SJeff Kirsher B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */ 1054527a6266SJeff Kirsher }; 1055527a6266SJeff Kirsher 1056527a6266SJeff Kirsher /* Status BMU Registers (Yukon-2 only)*/ 1057527a6266SJeff Kirsher enum { 1058527a6266SJeff Kirsher STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */ 1059527a6266SJeff Kirsher STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */ 1060527a6266SJeff Kirsher 1061527a6266SJeff Kirsher STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */ 1062527a6266SJeff Kirsher STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */ 1063527a6266SJeff Kirsher STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */ 1064527a6266SJeff Kirsher STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */ 1065527a6266SJeff Kirsher STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */ 1066527a6266SJeff Kirsher STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */ 1067527a6266SJeff Kirsher STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */ 1068527a6266SJeff Kirsher STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */ 1069527a6266SJeff Kirsher 1070527a6266SJeff Kirsher /* FIFO Control/Status Registers (Yukon-2 only)*/ 1071527a6266SJeff Kirsher STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */ 1072527a6266SJeff Kirsher STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */ 1073527a6266SJeff Kirsher STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */ 1074527a6266SJeff Kirsher STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */ 1075527a6266SJeff Kirsher STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */ 1076527a6266SJeff Kirsher STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */ 1077527a6266SJeff Kirsher STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */ 1078527a6266SJeff Kirsher 1079527a6266SJeff Kirsher /* Level and ISR Timer Registers (Yukon-2 only)*/ 1080527a6266SJeff Kirsher STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */ 1081527a6266SJeff Kirsher STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */ 1082527a6266SJeff Kirsher STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */ 1083527a6266SJeff Kirsher STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */ 1084527a6266SJeff Kirsher STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */ 1085527a6266SJeff Kirsher STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */ 1086527a6266SJeff Kirsher STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */ 1087527a6266SJeff Kirsher STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */ 1088527a6266SJeff Kirsher STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */ 1089527a6266SJeff Kirsher STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */ 1090527a6266SJeff Kirsher STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */ 1091527a6266SJeff Kirsher STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */ 1092527a6266SJeff Kirsher }; 1093527a6266SJeff Kirsher 1094527a6266SJeff Kirsher enum { 1095527a6266SJeff Kirsher LINKLED_OFF = 0x01, 1096527a6266SJeff Kirsher LINKLED_ON = 0x02, 1097527a6266SJeff Kirsher LINKLED_LINKSYNC_OFF = 0x04, 1098527a6266SJeff Kirsher LINKLED_LINKSYNC_ON = 0x08, 1099527a6266SJeff Kirsher LINKLED_BLINK_OFF = 0x10, 1100527a6266SJeff Kirsher LINKLED_BLINK_ON = 0x20, 1101527a6266SJeff Kirsher }; 1102527a6266SJeff Kirsher 1103527a6266SJeff Kirsher /* GMAC and GPHY Control Registers (YUKON only) */ 1104527a6266SJeff Kirsher enum { 1105527a6266SJeff Kirsher GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */ 1106527a6266SJeff Kirsher GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */ 1107527a6266SJeff Kirsher GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */ 1108527a6266SJeff Kirsher GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */ 1109527a6266SJeff Kirsher GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */ 1110527a6266SJeff Kirsher 1111527a6266SJeff Kirsher /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 1112527a6266SJeff Kirsher WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */ 1113527a6266SJeff Kirsher WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */ 1114527a6266SJeff Kirsher WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */ 1115527a6266SJeff Kirsher WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */ 1116527a6266SJeff Kirsher WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */ 1117527a6266SJeff Kirsher 1118527a6266SJeff Kirsher /* WOL Pattern Length Registers (YUKON only) */ 1119527a6266SJeff Kirsher WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */ 1120527a6266SJeff Kirsher WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */ 1121527a6266SJeff Kirsher 1122527a6266SJeff Kirsher /* WOL Pattern Counter Registers (YUKON only) */ 1123527a6266SJeff Kirsher WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */ 1124527a6266SJeff Kirsher WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */ 1125527a6266SJeff Kirsher }; 1126527a6266SJeff Kirsher #define WOL_REGS(port, x) (x + (port)*0x80) 1127527a6266SJeff Kirsher 1128527a6266SJeff Kirsher enum { 1129527a6266SJeff Kirsher WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */ 1130527a6266SJeff Kirsher WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */ 1131527a6266SJeff Kirsher }; 1132527a6266SJeff Kirsher #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400) 1133527a6266SJeff Kirsher 1134527a6266SJeff Kirsher enum { 1135527a6266SJeff Kirsher BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */ 1136527a6266SJeff Kirsher BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */ 1137527a6266SJeff Kirsher }; 1138527a6266SJeff Kirsher 1139527a6266SJeff Kirsher /* 1140527a6266SJeff Kirsher * Marvel-PHY Registers, indirect addressed over GMAC 1141527a6266SJeff Kirsher */ 1142527a6266SJeff Kirsher enum { 1143527a6266SJeff Kirsher PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */ 1144527a6266SJeff Kirsher PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */ 1145527a6266SJeff Kirsher PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */ 1146527a6266SJeff Kirsher PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */ 1147527a6266SJeff Kirsher PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */ 1148527a6266SJeff Kirsher PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */ 1149527a6266SJeff Kirsher PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */ 1150527a6266SJeff Kirsher PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */ 1151527a6266SJeff Kirsher PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */ 1152527a6266SJeff Kirsher /* Marvel-specific registers */ 1153527a6266SJeff Kirsher PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */ 1154527a6266SJeff Kirsher PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */ 1155527a6266SJeff Kirsher PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */ 1156527a6266SJeff Kirsher PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */ 1157527a6266SJeff Kirsher PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */ 1158527a6266SJeff Kirsher PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */ 1159527a6266SJeff Kirsher PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */ 1160527a6266SJeff Kirsher PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */ 1161527a6266SJeff Kirsher PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */ 1162527a6266SJeff Kirsher PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */ 1163527a6266SJeff Kirsher PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1164527a6266SJeff Kirsher PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */ 1165527a6266SJeff Kirsher PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */ 1166527a6266SJeff Kirsher PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1167527a6266SJeff Kirsher PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1168527a6266SJeff Kirsher PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */ 1169527a6266SJeff Kirsher PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */ 1170527a6266SJeff Kirsher PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */ 1171527a6266SJeff Kirsher 1172527a6266SJeff Kirsher /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1173527a6266SJeff Kirsher PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */ 1174527a6266SJeff Kirsher PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */ 1175527a6266SJeff Kirsher PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */ 1176527a6266SJeff Kirsher PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */ 1177527a6266SJeff Kirsher PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */ 1178527a6266SJeff Kirsher }; 1179527a6266SJeff Kirsher 1180527a6266SJeff Kirsher enum { 1181527a6266SJeff Kirsher PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */ 1182527a6266SJeff Kirsher PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */ 1183527a6266SJeff Kirsher PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */ 1184527a6266SJeff Kirsher PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */ 1185527a6266SJeff Kirsher PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */ 1186527a6266SJeff Kirsher PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */ 1187527a6266SJeff Kirsher PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */ 1188527a6266SJeff Kirsher PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */ 1189527a6266SJeff Kirsher PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */ 1190527a6266SJeff Kirsher PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */ 1191527a6266SJeff Kirsher }; 1192527a6266SJeff Kirsher 1193527a6266SJeff Kirsher enum { 1194527a6266SJeff Kirsher PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */ 1195527a6266SJeff Kirsher PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */ 1196527a6266SJeff Kirsher PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */ 1197527a6266SJeff Kirsher }; 1198527a6266SJeff Kirsher 1199527a6266SJeff Kirsher enum { 1200527a6266SJeff Kirsher PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */ 1201527a6266SJeff Kirsher 1202527a6266SJeff Kirsher PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */ 1203527a6266SJeff Kirsher PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */ 1204527a6266SJeff Kirsher PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occurred */ 1205527a6266SJeff Kirsher PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */ 1206527a6266SJeff Kirsher PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */ 1207527a6266SJeff Kirsher PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */ 1208527a6266SJeff Kirsher PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */ 1209527a6266SJeff Kirsher }; 1210527a6266SJeff Kirsher 1211527a6266SJeff Kirsher enum { 1212527a6266SJeff Kirsher PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */ 1213527a6266SJeff Kirsher PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */ 1214527a6266SJeff Kirsher PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */ 1215527a6266SJeff Kirsher }; 1216527a6266SJeff Kirsher 1217527a6266SJeff Kirsher /* different Marvell PHY Ids */ 1218527a6266SJeff Kirsher enum { 1219527a6266SJeff Kirsher PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */ 1220527a6266SJeff Kirsher 1221527a6266SJeff Kirsher PHY_BCOM_ID1_A1 = 0x6041, 1222527a6266SJeff Kirsher PHY_BCOM_ID1_B2 = 0x6043, 1223527a6266SJeff Kirsher PHY_BCOM_ID1_C0 = 0x6044, 1224527a6266SJeff Kirsher PHY_BCOM_ID1_C5 = 0x6047, 1225527a6266SJeff Kirsher 1226527a6266SJeff Kirsher PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */ 1227527a6266SJeff Kirsher PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */ 1228527a6266SJeff Kirsher PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */ 1229527a6266SJeff Kirsher PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */ 1230527a6266SJeff Kirsher PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1231527a6266SJeff Kirsher PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */ 1232527a6266SJeff Kirsher }; 1233527a6266SJeff Kirsher 1234527a6266SJeff Kirsher /* Advertisement register bits */ 1235527a6266SJeff Kirsher enum { 1236527a6266SJeff Kirsher PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */ 1237527a6266SJeff Kirsher PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */ 1238527a6266SJeff Kirsher PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */ 1239527a6266SJeff Kirsher 1240527a6266SJeff Kirsher PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */ 1241527a6266SJeff Kirsher PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */ 1242527a6266SJeff Kirsher PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */ 1243527a6266SJeff Kirsher PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */ 1244527a6266SJeff Kirsher PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */ 1245527a6266SJeff Kirsher PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */ 1246527a6266SJeff Kirsher PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */ 1247527a6266SJeff Kirsher PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */ 1248527a6266SJeff Kirsher PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/ 1249527a6266SJeff Kirsher PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, 1250527a6266SJeff Kirsher PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL | 1251527a6266SJeff Kirsher PHY_AN_100HALF | PHY_AN_100FULL, 1252527a6266SJeff Kirsher }; 1253527a6266SJeff Kirsher 1254527a6266SJeff Kirsher /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1255527a6266SJeff Kirsher /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1256527a6266SJeff Kirsher enum { 1257527a6266SJeff Kirsher PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */ 1258527a6266SJeff Kirsher PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */ 1259527a6266SJeff Kirsher PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */ 1260527a6266SJeff Kirsher PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */ 1261527a6266SJeff Kirsher PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */ 1262527a6266SJeff Kirsher PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */ 1263527a6266SJeff Kirsher /* Bit 9..8: reserved */ 1264527a6266SJeff Kirsher PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */ 1265527a6266SJeff Kirsher }; 1266527a6266SJeff Kirsher 1267527a6266SJeff Kirsher /** Marvell-Specific */ 1268527a6266SJeff Kirsher enum { 1269527a6266SJeff Kirsher PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */ 1270527a6266SJeff Kirsher PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */ 1271527a6266SJeff Kirsher PHY_M_AN_RF = 1<<13, /* Remote Fault */ 1272527a6266SJeff Kirsher 1273527a6266SJeff Kirsher PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */ 1274527a6266SJeff Kirsher PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */ 1275527a6266SJeff Kirsher PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */ 1276527a6266SJeff Kirsher PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */ 1277527a6266SJeff Kirsher PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */ 1278527a6266SJeff Kirsher PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */ 1279527a6266SJeff Kirsher PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */ 1280527a6266SJeff Kirsher PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */ 1281527a6266SJeff Kirsher }; 1282527a6266SJeff Kirsher 1283527a6266SJeff Kirsher /* special defines for FIBER (88E1011S only) */ 1284527a6266SJeff Kirsher enum { 1285527a6266SJeff Kirsher PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */ 1286527a6266SJeff Kirsher PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */ 1287527a6266SJeff Kirsher PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */ 1288527a6266SJeff Kirsher PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */ 1289527a6266SJeff Kirsher }; 1290527a6266SJeff Kirsher 1291527a6266SJeff Kirsher /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1292527a6266SJeff Kirsher enum { 1293527a6266SJeff Kirsher PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */ 1294527a6266SJeff Kirsher PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */ 1295527a6266SJeff Kirsher PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */ 1296527a6266SJeff Kirsher PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */ 1297527a6266SJeff Kirsher }; 1298527a6266SJeff Kirsher 1299527a6266SJeff Kirsher /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1300527a6266SJeff Kirsher enum { 1301527a6266SJeff Kirsher PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */ 1302527a6266SJeff Kirsher PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */ 1303527a6266SJeff Kirsher PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */ 1304527a6266SJeff Kirsher PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */ 1305527a6266SJeff Kirsher PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */ 1306527a6266SJeff Kirsher PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */ 1307527a6266SJeff Kirsher }; 1308527a6266SJeff Kirsher 1309527a6266SJeff Kirsher /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1310527a6266SJeff Kirsher enum { 1311527a6266SJeff Kirsher PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */ 1312527a6266SJeff Kirsher PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */ 1313527a6266SJeff Kirsher PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */ 1314527a6266SJeff Kirsher PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */ 1315527a6266SJeff Kirsher PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */ 1316527a6266SJeff Kirsher PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */ 1317527a6266SJeff Kirsher PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */ 1318527a6266SJeff Kirsher PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */ 1319527a6266SJeff Kirsher PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */ 1320527a6266SJeff Kirsher PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */ 1321527a6266SJeff Kirsher PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */ 1322527a6266SJeff Kirsher PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */ 1323527a6266SJeff Kirsher }; 1324527a6266SJeff Kirsher 1325527a6266SJeff Kirsher enum { 1326527a6266SJeff Kirsher PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */ 1327527a6266SJeff Kirsher PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */ 1328527a6266SJeff Kirsher }; 1329527a6266SJeff Kirsher 1330527a6266SJeff Kirsher #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK) 1331527a6266SJeff Kirsher 1332527a6266SJeff Kirsher enum { 1333527a6266SJeff Kirsher PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */ 1334527a6266SJeff Kirsher PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */ 1335527a6266SJeff Kirsher PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */ 1336527a6266SJeff Kirsher }; 1337527a6266SJeff Kirsher 1338527a6266SJeff Kirsher /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */ 1339527a6266SJeff Kirsher enum { 1340527a6266SJeff Kirsher PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */ 1341527a6266SJeff Kirsher PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */ 1342527a6266SJeff Kirsher }; 1343527a6266SJeff Kirsher 1344527a6266SJeff Kirsher /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1345527a6266SJeff Kirsher enum { 1346527a6266SJeff Kirsher PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */ 1347527a6266SJeff Kirsher PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */ 1348527a6266SJeff Kirsher PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */ 1349527a6266SJeff Kirsher PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */ 1350527a6266SJeff Kirsher PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */ 1351527a6266SJeff Kirsher 1352527a6266SJeff Kirsher PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */ 1353527a6266SJeff Kirsher PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */ 1354527a6266SJeff Kirsher 1355527a6266SJeff Kirsher PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */ 1356527a6266SJeff Kirsher PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */ 1357527a6266SJeff Kirsher }; 1358527a6266SJeff Kirsher 1359527a6266SJeff Kirsher /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1360527a6266SJeff Kirsher enum { 1361527a6266SJeff Kirsher PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */ 1362527a6266SJeff Kirsher PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */ 1363527a6266SJeff Kirsher PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */ 1364527a6266SJeff Kirsher PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */ 1365527a6266SJeff Kirsher PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */ 1366527a6266SJeff Kirsher PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */ 1367527a6266SJeff Kirsher PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */ 1368527a6266SJeff Kirsher PHY_M_PS_LINK_UP = 1<<10, /* Link Up */ 1369527a6266SJeff Kirsher PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */ 1370527a6266SJeff Kirsher PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */ 1371527a6266SJeff Kirsher PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */ 1372527a6266SJeff Kirsher PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */ 1373527a6266SJeff Kirsher PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */ 1374527a6266SJeff Kirsher PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */ 1375527a6266SJeff Kirsher PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */ 1376527a6266SJeff Kirsher PHY_M_PS_JABBER = 1<<0, /* Jabber */ 1377527a6266SJeff Kirsher }; 1378527a6266SJeff Kirsher 1379527a6266SJeff Kirsher #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1380527a6266SJeff Kirsher 1381527a6266SJeff Kirsher /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1382527a6266SJeff Kirsher enum { 1383527a6266SJeff Kirsher PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */ 1384527a6266SJeff Kirsher PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1385527a6266SJeff Kirsher }; 1386527a6266SJeff Kirsher 1387527a6266SJeff Kirsher enum { 1388527a6266SJeff Kirsher PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */ 1389527a6266SJeff Kirsher PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */ 1390527a6266SJeff Kirsher PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */ 1391527a6266SJeff Kirsher PHY_M_IS_AN_PR = 1<<12, /* Page Received */ 1392527a6266SJeff Kirsher PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */ 1393527a6266SJeff Kirsher PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */ 1394527a6266SJeff Kirsher PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */ 1395527a6266SJeff Kirsher PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */ 1396527a6266SJeff Kirsher PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */ 1397527a6266SJeff Kirsher PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */ 1398527a6266SJeff Kirsher PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */ 1399527a6266SJeff Kirsher PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */ 1400527a6266SJeff Kirsher 1401527a6266SJeff Kirsher PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */ 1402527a6266SJeff Kirsher PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */ 1403527a6266SJeff Kirsher PHY_M_IS_JABBER = 1<<0, /* Jabber */ 1404527a6266SJeff Kirsher 1405527a6266SJeff Kirsher PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE 1406527a6266SJeff Kirsher | PHY_M_IS_DUP_CHANGE, 1407527a6266SJeff Kirsher PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL, 1408527a6266SJeff Kirsher }; 1409527a6266SJeff Kirsher 1410527a6266SJeff Kirsher 1411527a6266SJeff Kirsher /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1412527a6266SJeff Kirsher enum { 1413527a6266SJeff Kirsher PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */ 1414527a6266SJeff Kirsher PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */ 1415527a6266SJeff Kirsher 1416527a6266SJeff Kirsher PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */ 1417527a6266SJeff Kirsher PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */ 1418527a6266SJeff Kirsher /* (88E1011 only) */ 1419527a6266SJeff Kirsher PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */ 1420527a6266SJeff Kirsher /* (88E1011 only) */ 1421527a6266SJeff Kirsher PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */ 1422527a6266SJeff Kirsher /* (88E1111 only) */ 1423527a6266SJeff Kirsher PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */ 1424527a6266SJeff Kirsher /* !!! Errata in spec. (1 = disable) */ 1425527a6266SJeff Kirsher PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/ 1426527a6266SJeff Kirsher PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */ 1427527a6266SJeff Kirsher PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */ 1428527a6266SJeff Kirsher PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */ 1429527a6266SJeff Kirsher PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */ 1430527a6266SJeff Kirsher PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */ 1431527a6266SJeff Kirsher 1432527a6266SJeff Kirsher PHY_M_10B_TE_ENABLE = 1<<7, /* 10Base-Te Enable (88E8079 and above) */ 1433527a6266SJeff Kirsher }; 1434527a6266SJeff Kirsher #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK) 1435527a6266SJeff Kirsher /* 00=1x; 01=2x; 10=3x; 11=4x */ 1436527a6266SJeff Kirsher #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK) 1437527a6266SJeff Kirsher /* 00=dis; 01=1x; 10=2x; 11=3x */ 1438527a6266SJeff Kirsher #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2) 1439527a6266SJeff Kirsher /* 000=1x; 001=2x; 010=3x; 011=4x */ 1440527a6266SJeff Kirsher #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK) 1441527a6266SJeff Kirsher /* 01X=0; 110=2.5; 111=25 (MHz) */ 1442527a6266SJeff Kirsher 1443527a6266SJeff Kirsher /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1444527a6266SJeff Kirsher enum { 1445527a6266SJeff Kirsher PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */ 1446527a6266SJeff Kirsher PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */ 1447527a6266SJeff Kirsher PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */ 1448527a6266SJeff Kirsher }; 1449527a6266SJeff Kirsher /* !!! Errata in spec. (1 = disable) */ 1450527a6266SJeff Kirsher 1451527a6266SJeff Kirsher #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK) 1452527a6266SJeff Kirsher /* 100=5x; 101=6x; 110=7x; 111=8x */ 1453527a6266SJeff Kirsher enum { 1454527a6266SJeff Kirsher MAC_TX_CLK_0_MHZ = 2, 1455527a6266SJeff Kirsher MAC_TX_CLK_2_5_MHZ = 6, 1456527a6266SJeff Kirsher MAC_TX_CLK_25_MHZ = 7, 1457527a6266SJeff Kirsher }; 1458527a6266SJeff Kirsher 1459527a6266SJeff Kirsher /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1460527a6266SJeff Kirsher enum { 1461527a6266SJeff Kirsher PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */ 1462527a6266SJeff Kirsher PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */ 1463527a6266SJeff Kirsher PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */ 1464527a6266SJeff Kirsher PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */ 1465527a6266SJeff Kirsher PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */ 1466527a6266SJeff Kirsher PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */ 1467527a6266SJeff Kirsher PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */ 1468527a6266SJeff Kirsher /* (88E1111 only) */ 1469527a6266SJeff Kirsher }; 1470527a6266SJeff Kirsher 1471527a6266SJeff Kirsher enum { 1472527a6266SJeff Kirsher PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */ 1473527a6266SJeff Kirsher /* (88E1011 only) */ 1474527a6266SJeff Kirsher PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */ 1475527a6266SJeff Kirsher PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */ 1476527a6266SJeff Kirsher PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */ 1477527a6266SJeff Kirsher PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */ 1478527a6266SJeff Kirsher PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ 1479527a6266SJeff Kirsher }; 1480527a6266SJeff Kirsher 1481527a6266SJeff Kirsher #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK) 1482527a6266SJeff Kirsher 1483527a6266SJeff Kirsher /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/ 1484527a6266SJeff Kirsher enum { 1485527a6266SJeff Kirsher PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1486527a6266SJeff Kirsher PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1487527a6266SJeff Kirsher PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1488527a6266SJeff Kirsher PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1489527a6266SJeff Kirsher PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1490527a6266SJeff Kirsher PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1491527a6266SJeff Kirsher }; 1492527a6266SJeff Kirsher 1493527a6266SJeff Kirsher #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK) 1494527a6266SJeff Kirsher #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK) 1495527a6266SJeff Kirsher #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK) 1496527a6266SJeff Kirsher #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK) 1497527a6266SJeff Kirsher #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK) 1498527a6266SJeff Kirsher #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK) 1499527a6266SJeff Kirsher 1500527a6266SJeff Kirsher enum { 1501527a6266SJeff Kirsher PULS_NO_STR = 0,/* no pulse stretching */ 1502527a6266SJeff Kirsher PULS_21MS = 1,/* 21 ms to 42 ms */ 1503527a6266SJeff Kirsher PULS_42MS = 2,/* 42 ms to 84 ms */ 1504527a6266SJeff Kirsher PULS_84MS = 3,/* 84 ms to 170 ms */ 1505527a6266SJeff Kirsher PULS_170MS = 4,/* 170 ms to 340 ms */ 1506527a6266SJeff Kirsher PULS_340MS = 5,/* 340 ms to 670 ms */ 1507527a6266SJeff Kirsher PULS_670MS = 6,/* 670 ms to 1.3 s */ 1508527a6266SJeff Kirsher PULS_1300MS = 7,/* 1.3 s to 2.7 s */ 1509527a6266SJeff Kirsher }; 1510527a6266SJeff Kirsher 1511527a6266SJeff Kirsher #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK) 1512527a6266SJeff Kirsher 1513527a6266SJeff Kirsher enum { 1514527a6266SJeff Kirsher BLINK_42MS = 0,/* 42 ms */ 1515527a6266SJeff Kirsher BLINK_84MS = 1,/* 84 ms */ 1516527a6266SJeff Kirsher BLINK_170MS = 2,/* 170 ms */ 1517527a6266SJeff Kirsher BLINK_340MS = 3,/* 340 ms */ 1518527a6266SJeff Kirsher BLINK_670MS = 4,/* 670 ms */ 1519527a6266SJeff Kirsher }; 1520527a6266SJeff Kirsher 1521527a6266SJeff Kirsher /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1522527a6266SJeff Kirsher #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */ 1523527a6266SJeff Kirsher 1524527a6266SJeff Kirsher #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */ 1525527a6266SJeff Kirsher #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */ 1526527a6266SJeff Kirsher #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */ 1527527a6266SJeff Kirsher #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */ 1528527a6266SJeff Kirsher #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */ 1529527a6266SJeff Kirsher #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */ 1530527a6266SJeff Kirsher 1531527a6266SJeff Kirsher enum led_mode { 1532527a6266SJeff Kirsher MO_LED_NORM = 0, 1533527a6266SJeff Kirsher MO_LED_BLINK = 1, 1534527a6266SJeff Kirsher MO_LED_OFF = 2, 1535527a6266SJeff Kirsher MO_LED_ON = 3, 1536527a6266SJeff Kirsher }; 1537527a6266SJeff Kirsher 1538527a6266SJeff Kirsher /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1539527a6266SJeff Kirsher enum { 1540527a6266SJeff Kirsher PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */ 1541527a6266SJeff Kirsher PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */ 1542527a6266SJeff Kirsher PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */ 1543527a6266SJeff Kirsher PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */ 1544527a6266SJeff Kirsher PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */ 1545527a6266SJeff Kirsher }; 1546527a6266SJeff Kirsher 1547527a6266SJeff Kirsher /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1548527a6266SJeff Kirsher enum { 1549527a6266SJeff Kirsher PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */ 1550527a6266SJeff Kirsher PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */ 1551527a6266SJeff Kirsher PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */ 1552527a6266SJeff Kirsher PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */ 1553527a6266SJeff Kirsher PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */ 1554527a6266SJeff Kirsher PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */ 1555527a6266SJeff Kirsher PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */ 1556527a6266SJeff Kirsher /* (88E1111 only) */ 1557527a6266SJeff Kirsher 1558527a6266SJeff Kirsher PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */ 1559527a6266SJeff Kirsher PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */ 1560527a6266SJeff Kirsher PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1561527a6266SJeff Kirsher }; 1562527a6266SJeff Kirsher 1563527a6266SJeff Kirsher /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1564527a6266SJeff Kirsher /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1565527a6266SJeff Kirsher /* Bit 15..12: reserved (used internally) */ 1566527a6266SJeff Kirsher enum { 1567527a6266SJeff Kirsher PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */ 1568527a6266SJeff Kirsher PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */ 1569527a6266SJeff Kirsher PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ 1570527a6266SJeff Kirsher }; 1571527a6266SJeff Kirsher 1572527a6266SJeff Kirsher #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK) 1573527a6266SJeff Kirsher #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK) 1574527a6266SJeff Kirsher #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK) 1575527a6266SJeff Kirsher 1576527a6266SJeff Kirsher enum { 1577527a6266SJeff Kirsher LED_PAR_CTRL_COLX = 0x00, 1578527a6266SJeff Kirsher LED_PAR_CTRL_ERROR = 0x01, 1579527a6266SJeff Kirsher LED_PAR_CTRL_DUPLEX = 0x02, 1580527a6266SJeff Kirsher LED_PAR_CTRL_DP_COL = 0x03, 1581527a6266SJeff Kirsher LED_PAR_CTRL_SPEED = 0x04, 1582527a6266SJeff Kirsher LED_PAR_CTRL_LINK = 0x05, 1583527a6266SJeff Kirsher LED_PAR_CTRL_TX = 0x06, 1584527a6266SJeff Kirsher LED_PAR_CTRL_RX = 0x07, 1585527a6266SJeff Kirsher LED_PAR_CTRL_ACT = 0x08, 1586527a6266SJeff Kirsher LED_PAR_CTRL_LNK_RX = 0x09, 1587527a6266SJeff Kirsher LED_PAR_CTRL_LNK_AC = 0x0a, 1588527a6266SJeff Kirsher LED_PAR_CTRL_ACT_BL = 0x0b, 1589527a6266SJeff Kirsher LED_PAR_CTRL_TX_BL = 0x0c, 1590527a6266SJeff Kirsher LED_PAR_CTRL_RX_BL = 0x0d, 1591527a6266SJeff Kirsher LED_PAR_CTRL_COL_BL = 0x0e, 1592527a6266SJeff Kirsher LED_PAR_CTRL_INACT = 0x0f 1593527a6266SJeff Kirsher }; 1594527a6266SJeff Kirsher 1595527a6266SJeff Kirsher /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1596527a6266SJeff Kirsher enum { 1597527a6266SJeff Kirsher PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */ 1598527a6266SJeff Kirsher PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */ 1599527a6266SJeff Kirsher PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */ 1600527a6266SJeff Kirsher }; 1601527a6266SJeff Kirsher 1602527a6266SJeff Kirsher /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1603527a6266SJeff Kirsher /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1604527a6266SJeff Kirsher enum { 1605527a6266SJeff Kirsher PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */ 1606527a6266SJeff Kirsher PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */ 1607527a6266SJeff Kirsher PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */ 1608527a6266SJeff Kirsher }; 1609527a6266SJeff Kirsher 1610527a6266SJeff Kirsher /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1611527a6266SJeff Kirsher /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1612527a6266SJeff Kirsher enum { 1613527a6266SJeff Kirsher PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */ 1614527a6266SJeff Kirsher PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */ 1615527a6266SJeff Kirsher PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */ 1616527a6266SJeff Kirsher PHY_M_MAC_MD_COPPER = 5,/* Copper only */ 1617527a6266SJeff Kirsher PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ 1618527a6266SJeff Kirsher }; 1619527a6266SJeff Kirsher #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) 1620527a6266SJeff Kirsher 1621527a6266SJeff Kirsher /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1622527a6266SJeff Kirsher enum { 1623527a6266SJeff Kirsher PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */ 1624527a6266SJeff Kirsher PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1625527a6266SJeff Kirsher PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1626527a6266SJeff Kirsher PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1627527a6266SJeff Kirsher }; 1628527a6266SJeff Kirsher 1629527a6266SJeff Kirsher #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) 1630527a6266SJeff Kirsher #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) 1631527a6266SJeff Kirsher #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) 1632527a6266SJeff Kirsher #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) 1633527a6266SJeff Kirsher 1634527a6266SJeff Kirsher /* GMAC registers */ 1635527a6266SJeff Kirsher /* Port Registers */ 1636527a6266SJeff Kirsher enum { 1637527a6266SJeff Kirsher GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */ 1638527a6266SJeff Kirsher GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */ 1639527a6266SJeff Kirsher GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */ 1640527a6266SJeff Kirsher GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */ 1641527a6266SJeff Kirsher GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */ 1642527a6266SJeff Kirsher GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */ 1643527a6266SJeff Kirsher GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */ 1644527a6266SJeff Kirsher /* Source Address Registers */ 1645527a6266SJeff Kirsher GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */ 1646527a6266SJeff Kirsher GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */ 1647527a6266SJeff Kirsher GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */ 1648527a6266SJeff Kirsher GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */ 1649527a6266SJeff Kirsher GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */ 1650527a6266SJeff Kirsher GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */ 1651527a6266SJeff Kirsher 1652527a6266SJeff Kirsher /* Multicast Address Hash Registers */ 1653527a6266SJeff Kirsher GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */ 1654527a6266SJeff Kirsher GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */ 1655527a6266SJeff Kirsher GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */ 1656527a6266SJeff Kirsher GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */ 1657527a6266SJeff Kirsher 1658527a6266SJeff Kirsher /* Interrupt Source Registers */ 1659527a6266SJeff Kirsher GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */ 1660527a6266SJeff Kirsher GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */ 1661527a6266SJeff Kirsher GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1662527a6266SJeff Kirsher 1663527a6266SJeff Kirsher /* Interrupt Mask Registers */ 1664527a6266SJeff Kirsher GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */ 1665527a6266SJeff Kirsher GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */ 1666527a6266SJeff Kirsher GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1667527a6266SJeff Kirsher 1668527a6266SJeff Kirsher /* Serial Management Interface (SMI) Registers */ 1669527a6266SJeff Kirsher GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ 1670527a6266SJeff Kirsher GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ 1671527a6266SJeff Kirsher GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ 1672527a6266SJeff Kirsher /* MIB Counters */ 1673527a6266SJeff Kirsher GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ 1674527a6266SJeff Kirsher GM_MIB_CNT_END = 0x025C, /* Last MIB counter */ 1675527a6266SJeff Kirsher }; 1676527a6266SJeff Kirsher 1677527a6266SJeff Kirsher 1678527a6266SJeff Kirsher /* 1679527a6266SJeff Kirsher * MIB Counters base address definitions (low word) - 1680527a6266SJeff Kirsher * use offset 4 for access to high word (32 bit r/o) 1681527a6266SJeff Kirsher */ 1682527a6266SJeff Kirsher enum { 1683527a6266SJeff Kirsher GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ 1684527a6266SJeff Kirsher GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ 1685527a6266SJeff Kirsher GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ 1686527a6266SJeff Kirsher GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ 1687527a6266SJeff Kirsher GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ 1688527a6266SJeff Kirsher 1689527a6266SJeff Kirsher GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ 1690527a6266SJeff Kirsher GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ 1691527a6266SJeff Kirsher GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ 1692527a6266SJeff Kirsher GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */ 1693527a6266SJeff Kirsher GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ 1694527a6266SJeff Kirsher GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ 1695527a6266SJeff Kirsher GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ 1696527a6266SJeff Kirsher GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */ 1697527a6266SJeff Kirsher GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */ 1698527a6266SJeff Kirsher GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */ 1699527a6266SJeff Kirsher GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */ 1700527a6266SJeff Kirsher GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */ 1701527a6266SJeff Kirsher GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */ 1702527a6266SJeff Kirsher GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */ 1703527a6266SJeff Kirsher GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */ 1704527a6266SJeff Kirsher 1705527a6266SJeff Kirsher GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */ 1706527a6266SJeff Kirsher GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */ 1707527a6266SJeff Kirsher GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */ 1708527a6266SJeff Kirsher GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */ 1709527a6266SJeff Kirsher GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */ 1710527a6266SJeff Kirsher GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */ 1711527a6266SJeff Kirsher GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */ 1712527a6266SJeff Kirsher GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */ 1713527a6266SJeff Kirsher GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */ 1714527a6266SJeff Kirsher GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */ 1715527a6266SJeff Kirsher GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */ 1716527a6266SJeff Kirsher GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */ 1717527a6266SJeff Kirsher GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */ 1718527a6266SJeff Kirsher GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */ 1719527a6266SJeff Kirsher 1720527a6266SJeff Kirsher GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */ 1721527a6266SJeff Kirsher GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */ 1722527a6266SJeff Kirsher GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */ 1723527a6266SJeff Kirsher GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */ 1724527a6266SJeff Kirsher GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */ 1725527a6266SJeff Kirsher GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */ 1726527a6266SJeff Kirsher }; 1727527a6266SJeff Kirsher 1728527a6266SJeff Kirsher /* GMAC Bit Definitions */ 1729527a6266SJeff Kirsher /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1730527a6266SJeff Kirsher enum { 1731527a6266SJeff Kirsher GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */ 1732527a6266SJeff Kirsher GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */ 1733527a6266SJeff Kirsher GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */ 1734527a6266SJeff Kirsher GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */ 1735527a6266SJeff Kirsher GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */ 1736527a6266SJeff Kirsher GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */ 1737527a6266SJeff Kirsher GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occurred */ 1738527a6266SJeff Kirsher GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occurred */ 1739527a6266SJeff Kirsher 1740527a6266SJeff Kirsher GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */ 1741527a6266SJeff Kirsher GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */ 1742527a6266SJeff Kirsher GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */ 1743527a6266SJeff Kirsher GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */ 1744527a6266SJeff Kirsher GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */ 1745527a6266SJeff Kirsher }; 1746527a6266SJeff Kirsher 1747527a6266SJeff Kirsher /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1748527a6266SJeff Kirsher enum { 1749527a6266SJeff Kirsher GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */ 1750527a6266SJeff Kirsher GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */ 1751527a6266SJeff Kirsher GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */ 1752527a6266SJeff Kirsher GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */ 1753527a6266SJeff Kirsher GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */ 1754527a6266SJeff Kirsher GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */ 1755527a6266SJeff Kirsher GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */ 1756527a6266SJeff Kirsher GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */ 1757527a6266SJeff Kirsher GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */ 1758527a6266SJeff Kirsher GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */ 1759527a6266SJeff Kirsher GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */ 1760527a6266SJeff Kirsher GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */ 1761527a6266SJeff Kirsher GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */ 1762527a6266SJeff Kirsher GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */ 1763527a6266SJeff Kirsher GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */ 1764527a6266SJeff Kirsher }; 1765527a6266SJeff Kirsher 1766527a6266SJeff Kirsher #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1767527a6266SJeff Kirsher 1768527a6266SJeff Kirsher /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1769527a6266SJeff Kirsher enum { 1770527a6266SJeff Kirsher GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */ 1771527a6266SJeff Kirsher GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */ 1772527a6266SJeff Kirsher GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */ 1773527a6266SJeff Kirsher GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */ 1774527a6266SJeff Kirsher }; 1775527a6266SJeff Kirsher 1776527a6266SJeff Kirsher #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK) 1777527a6266SJeff Kirsher #define TX_COL_DEF 0x04 1778527a6266SJeff Kirsher 1779527a6266SJeff Kirsher /* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1780527a6266SJeff Kirsher enum { 1781527a6266SJeff Kirsher GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */ 1782527a6266SJeff Kirsher GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */ 1783527a6266SJeff Kirsher GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */ 1784527a6266SJeff Kirsher GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */ 1785527a6266SJeff Kirsher }; 1786527a6266SJeff Kirsher 1787527a6266SJeff Kirsher /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1788527a6266SJeff Kirsher enum { 1789527a6266SJeff Kirsher GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */ 1790527a6266SJeff Kirsher GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */ 1791527a6266SJeff Kirsher GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */ 1792527a6266SJeff Kirsher GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */ 1793527a6266SJeff Kirsher 1794527a6266SJeff Kirsher TX_JAM_LEN_DEF = 0x03, 1795527a6266SJeff Kirsher TX_JAM_IPG_DEF = 0x0b, 1796527a6266SJeff Kirsher TX_IPG_JAM_DEF = 0x1c, 1797527a6266SJeff Kirsher TX_BOF_LIM_DEF = 0x04, 1798527a6266SJeff Kirsher }; 1799527a6266SJeff Kirsher 1800527a6266SJeff Kirsher #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK) 1801527a6266SJeff Kirsher #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK) 1802527a6266SJeff Kirsher #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK) 1803527a6266SJeff Kirsher #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1804527a6266SJeff Kirsher 1805527a6266SJeff Kirsher 1806527a6266SJeff Kirsher /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1807527a6266SJeff Kirsher enum { 1808527a6266SJeff Kirsher GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */ 1809527a6266SJeff Kirsher GM_SMOD_LIMIT_4 = 1<<10, /* 4 consecutive Tx trials */ 1810527a6266SJeff Kirsher GM_SMOD_VLAN_ENA = 1<<9, /* Enable VLAN (Max. Frame Len) */ 1811527a6266SJeff Kirsher GM_SMOD_JUMBO_ENA = 1<<8, /* Enable Jumbo (Max. Frame Len) */ 1812527a6266SJeff Kirsher 1813527a6266SJeff Kirsher GM_NEW_FLOW_CTRL = 1<<6, /* Enable New Flow-Control */ 1814527a6266SJeff Kirsher 1815527a6266SJeff Kirsher GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */ 1816527a6266SJeff Kirsher }; 1817527a6266SJeff Kirsher 1818527a6266SJeff Kirsher #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK) 1819527a6266SJeff Kirsher #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK) 1820527a6266SJeff Kirsher 1821527a6266SJeff Kirsher #define DATA_BLIND_DEF 0x04 1822527a6266SJeff Kirsher #define IPG_DATA_DEF_1000 0x1e 1823527a6266SJeff Kirsher #define IPG_DATA_DEF_10_100 0x18 1824527a6266SJeff Kirsher 1825527a6266SJeff Kirsher /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1826527a6266SJeff Kirsher enum { 1827527a6266SJeff Kirsher GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */ 1828527a6266SJeff Kirsher GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */ 1829527a6266SJeff Kirsher GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/ 1830527a6266SJeff Kirsher GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */ 1831527a6266SJeff Kirsher GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */ 1832527a6266SJeff Kirsher }; 1833527a6266SJeff Kirsher 1834527a6266SJeff Kirsher #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK) 1835527a6266SJeff Kirsher #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK) 1836527a6266SJeff Kirsher 1837527a6266SJeff Kirsher /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1838527a6266SJeff Kirsher enum { 1839527a6266SJeff Kirsher GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */ 1840527a6266SJeff Kirsher GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */ 1841527a6266SJeff Kirsher }; 1842527a6266SJeff Kirsher 1843527a6266SJeff Kirsher /* Receive Frame Status Encoding */ 1844527a6266SJeff Kirsher enum { 1845527a6266SJeff Kirsher GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */ 1846527a6266SJeff Kirsher GMR_FS_VLAN = 1<<13, /* VLAN Packet */ 1847527a6266SJeff Kirsher GMR_FS_JABBER = 1<<12, /* Jabber Packet */ 1848527a6266SJeff Kirsher GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */ 1849527a6266SJeff Kirsher GMR_FS_MC = 1<<10, /* Multicast Packet */ 1850527a6266SJeff Kirsher GMR_FS_BC = 1<<9, /* Broadcast Packet */ 1851527a6266SJeff Kirsher GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */ 1852527a6266SJeff Kirsher GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */ 1853527a6266SJeff Kirsher GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */ 1854527a6266SJeff Kirsher GMR_FS_MII_ERR = 1<<5, /* MII Error */ 1855527a6266SJeff Kirsher GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */ 1856527a6266SJeff Kirsher GMR_FS_FRAGMENT = 1<<3, /* Fragment */ 1857527a6266SJeff Kirsher 1858527a6266SJeff Kirsher GMR_FS_CRC_ERR = 1<<1, /* CRC Error */ 1859527a6266SJeff Kirsher GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */ 1860527a6266SJeff Kirsher 1861527a6266SJeff Kirsher GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR | 1862527a6266SJeff Kirsher GMR_FS_FRAGMENT | GMR_FS_LONG_ERR | 1863527a6266SJeff Kirsher GMR_FS_MII_ERR | GMR_FS_BAD_FC | 1864527a6266SJeff Kirsher GMR_FS_UN_SIZE | GMR_FS_JABBER, 1865527a6266SJeff Kirsher }; 1866527a6266SJeff Kirsher 1867527a6266SJeff Kirsher /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1868527a6266SJeff Kirsher enum { 1869527a6266SJeff Kirsher RX_GCLKMAC_ENA = 1<<31, /* RX MAC Clock Gating Enable */ 1870527a6266SJeff Kirsher RX_GCLKMAC_OFF = 1<<30, 1871527a6266SJeff Kirsher 1872527a6266SJeff Kirsher RX_STFW_DIS = 1<<29, /* RX Store and Forward Enable */ 1873527a6266SJeff Kirsher RX_STFW_ENA = 1<<28, 1874527a6266SJeff Kirsher 1875527a6266SJeff Kirsher RX_TRUNC_ON = 1<<27, /* enable packet truncation */ 1876527a6266SJeff Kirsher RX_TRUNC_OFF = 1<<26, /* disable packet truncation */ 1877527a6266SJeff Kirsher RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */ 1878527a6266SJeff Kirsher RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */ 1879527a6266SJeff Kirsher 1880527a6266SJeff Kirsher RX_MACSEC_FLUSH_ON = 1<<23, 1881527a6266SJeff Kirsher RX_MACSEC_FLUSH_OFF = 1<<22, 1882527a6266SJeff Kirsher RX_MACSEC_ASF_FLUSH_ON = 1<<21, 1883527a6266SJeff Kirsher RX_MACSEC_ASF_FLUSH_OFF = 1<<20, 1884527a6266SJeff Kirsher 1885527a6266SJeff Kirsher GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */ 1886527a6266SJeff Kirsher GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */ 1887527a6266SJeff Kirsher GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */ 1888527a6266SJeff Kirsher GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */ 1889527a6266SJeff Kirsher 1890527a6266SJeff Kirsher GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */ 1891527a6266SJeff Kirsher GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */ 1892527a6266SJeff Kirsher GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */ 1893527a6266SJeff Kirsher 1894527a6266SJeff Kirsher GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */ 1895527a6266SJeff Kirsher GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */ 1896527a6266SJeff Kirsher GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */ 1897527a6266SJeff Kirsher GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */ 1898527a6266SJeff Kirsher GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */ 1899527a6266SJeff Kirsher GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */ 1900527a6266SJeff Kirsher GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */ 1901527a6266SJeff Kirsher 1902527a6266SJeff Kirsher GMF_OPER_ON = 1<<3, /* Operational Mode On */ 1903527a6266SJeff Kirsher GMF_OPER_OFF = 1<<2, /* Operational Mode Off */ 1904527a6266SJeff Kirsher GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */ 1905527a6266SJeff Kirsher GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */ 1906527a6266SJeff Kirsher 1907527a6266SJeff Kirsher RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */ 1908527a6266SJeff Kirsher 1909527a6266SJeff Kirsher GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON, 1910527a6266SJeff Kirsher }; 1911527a6266SJeff Kirsher 1912527a6266SJeff Kirsher /* RX_GMF_FL_CTRL 16 bit Rx GMAC FIFO Flush Control (Yukon-Supreme) */ 1913527a6266SJeff Kirsher enum { 1914527a6266SJeff Kirsher RX_IPV6_SA_MOB_ENA = 1<<9, /* IPv6 SA Mobility Support Enable */ 1915527a6266SJeff Kirsher RX_IPV6_SA_MOB_DIS = 1<<8, /* IPv6 SA Mobility Support Disable */ 1916527a6266SJeff Kirsher RX_IPV6_DA_MOB_ENA = 1<<7, /* IPv6 DA Mobility Support Enable */ 1917527a6266SJeff Kirsher RX_IPV6_DA_MOB_DIS = 1<<6, /* IPv6 DA Mobility Support Disable */ 1918527a6266SJeff Kirsher RX_PTR_SYNCDLY_ENA = 1<<5, /* Pointers Delay Synch Enable */ 1919527a6266SJeff Kirsher RX_PTR_SYNCDLY_DIS = 1<<4, /* Pointers Delay Synch Disable */ 1920527a6266SJeff Kirsher RX_ASF_NEWFLAG_ENA = 1<<3, /* RX ASF Flag New Logic Enable */ 1921527a6266SJeff Kirsher RX_ASF_NEWFLAG_DIS = 1<<2, /* RX ASF Flag New Logic Disable */ 1922527a6266SJeff Kirsher RX_FLSH_MISSPKT_ENA = 1<<1, /* RX Flush Miss-Packet Enable */ 1923527a6266SJeff Kirsher RX_FLSH_MISSPKT_DIS = 1<<0, /* RX Flush Miss-Packet Disable */ 1924527a6266SJeff Kirsher }; 1925527a6266SJeff Kirsher 1926527a6266SJeff Kirsher /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1927527a6266SJeff Kirsher enum { 1928527a6266SJeff Kirsher TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */ 1929527a6266SJeff Kirsher }; 1930527a6266SJeff Kirsher 1931527a6266SJeff Kirsher /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */ 1932527a6266SJeff Kirsher enum { 1933527a6266SJeff Kirsher TX_STFW_DIS = 1<<31,/* Disable Store & Forward */ 1934527a6266SJeff Kirsher TX_STFW_ENA = 1<<30,/* Enable Store & Forward */ 1935527a6266SJeff Kirsher 1936527a6266SJeff Kirsher TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */ 1937527a6266SJeff Kirsher TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */ 1938527a6266SJeff Kirsher 1939527a6266SJeff Kirsher TX_PCI_JUM_ENA = 1<<23,/* PCI Jumbo Mode enable */ 1940527a6266SJeff Kirsher TX_PCI_JUM_DIS = 1<<22,/* PCI Jumbo Mode enable */ 1941527a6266SJeff Kirsher 1942527a6266SJeff Kirsher GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */ 1943527a6266SJeff Kirsher GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */ 1944527a6266SJeff Kirsher GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */ 1945527a6266SJeff Kirsher 1946527a6266SJeff Kirsher GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */ 1947527a6266SJeff Kirsher GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */ 1948527a6266SJeff Kirsher GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */ 1949527a6266SJeff Kirsher }; 1950527a6266SJeff Kirsher 1951527a6266SJeff Kirsher /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1952527a6266SJeff Kirsher enum { 1953527a6266SJeff Kirsher GMT_ST_START = 1<<2, /* Start Time Stamp Timer */ 1954527a6266SJeff Kirsher GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */ 1955527a6266SJeff Kirsher GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */ 1956527a6266SJeff Kirsher }; 1957527a6266SJeff Kirsher 1958527a6266SJeff Kirsher /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1959527a6266SJeff Kirsher enum { 1960527a6266SJeff Kirsher Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */ 1961527a6266SJeff Kirsher Y2_ASF_RESET = 1<<3, /* ASF system in reset state */ 1962527a6266SJeff Kirsher Y2_ASF_RUNNING = 1<<2, /* ASF system operational */ 1963527a6266SJeff Kirsher Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */ 1964527a6266SJeff Kirsher Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */ 1965527a6266SJeff Kirsher 1966527a6266SJeff Kirsher Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */ 1967527a6266SJeff Kirsher Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */ 1968527a6266SJeff Kirsher }; 1969527a6266SJeff Kirsher 1970527a6266SJeff Kirsher /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 1971527a6266SJeff Kirsher enum { 1972527a6266SJeff Kirsher Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ 1973527a6266SJeff Kirsher Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ 1974527a6266SJeff Kirsher }; 1975527a6266SJeff Kirsher /* HCU_CCSR CPU Control and Status Register */ 1976527a6266SJeff Kirsher enum { 1977527a6266SJeff Kirsher HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */ 1978527a6266SJeff Kirsher HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */ 1979527a6266SJeff Kirsher /* Clock Stretching Timeout */ 1980527a6266SJeff Kirsher HCU_CCSR_CS_TO = 1<<25, 1981527a6266SJeff Kirsher HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */ 1982527a6266SJeff Kirsher 1983527a6266SJeff Kirsher HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */ 1984527a6266SJeff Kirsher HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */ 1985527a6266SJeff Kirsher 1986527a6266SJeff Kirsher HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */ 1987527a6266SJeff Kirsher HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */ 1988527a6266SJeff Kirsher 1989527a6266SJeff Kirsher HCU_CCSR_SET_SYNC_CPU = 1<<5, 1990527a6266SJeff Kirsher HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */ 1991527a6266SJeff Kirsher HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3, 1992527a6266SJeff Kirsher HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */ 1993527a6266SJeff Kirsher /* Microcontroller State */ 1994527a6266SJeff Kirsher HCU_CCSR_UC_STATE_MSK = 3, 1995527a6266SJeff Kirsher HCU_CCSR_UC_STATE_BASE = 1<<0, 1996527a6266SJeff Kirsher HCU_CCSR_ASF_RESET = 0, 1997527a6266SJeff Kirsher HCU_CCSR_ASF_HALTED = 1<<1, 1998527a6266SJeff Kirsher HCU_CCSR_ASF_RUNNING = 1<<0, 1999527a6266SJeff Kirsher }; 2000527a6266SJeff Kirsher 2001527a6266SJeff Kirsher /* HCU_HCSR Host Control and Status Register */ 2002527a6266SJeff Kirsher enum { 2003527a6266SJeff Kirsher HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */ 2004527a6266SJeff Kirsher 2005527a6266SJeff Kirsher HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */ 2006527a6266SJeff Kirsher HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */ 2007527a6266SJeff Kirsher }; 2008527a6266SJeff Kirsher 2009527a6266SJeff Kirsher /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2010527a6266SJeff Kirsher enum { 2011527a6266SJeff Kirsher SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */ 2012527a6266SJeff Kirsher SC_STAT_OP_ON = 1<<3, /* Operational Mode On */ 2013527a6266SJeff Kirsher SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */ 2014527a6266SJeff Kirsher SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */ 2015527a6266SJeff Kirsher SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */ 2016527a6266SJeff Kirsher }; 2017527a6266SJeff Kirsher 2018527a6266SJeff Kirsher /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2019527a6266SJeff Kirsher enum { 2020527a6266SJeff Kirsher GMC_SET_RST = 1<<15,/* MAC SEC RST */ 2021527a6266SJeff Kirsher GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */ 2022527a6266SJeff Kirsher GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */ 2023527a6266SJeff Kirsher GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */ 2024527a6266SJeff Kirsher GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */ 2025527a6266SJeff Kirsher GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/ 2026527a6266SJeff Kirsher GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */ 2027527a6266SJeff Kirsher GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */ 2028527a6266SJeff Kirsher 2029527a6266SJeff Kirsher GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */ 2030527a6266SJeff Kirsher GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */ 2031527a6266SJeff Kirsher GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */ 2032527a6266SJeff Kirsher GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */ 2033527a6266SJeff Kirsher GMC_PAUSE_ON = 1<<3, /* Pause On */ 2034527a6266SJeff Kirsher GMC_PAUSE_OFF = 1<<2, /* Pause Off */ 2035527a6266SJeff Kirsher GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */ 2036527a6266SJeff Kirsher GMC_RST_SET = 1<<0, /* Set GMAC Reset */ 2037527a6266SJeff Kirsher }; 2038527a6266SJeff Kirsher 2039527a6266SJeff Kirsher /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2040527a6266SJeff Kirsher enum { 2041527a6266SJeff Kirsher GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */ 2042527a6266SJeff Kirsher GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */ 2043527a6266SJeff Kirsher GPC_SPEED = 3<<27, /* PHY speed (ro) */ 2044527a6266SJeff Kirsher GPC_LINK = 1<<26, /* Link up (ro) */ 2045527a6266SJeff Kirsher GPC_DUPLEX = 1<<25, /* Duplex (ro) */ 2046527a6266SJeff Kirsher GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */ 2047527a6266SJeff Kirsher 2048527a6266SJeff Kirsher GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */ 2049527a6266SJeff Kirsher GPC_TSTMODE = 1<<22, /* Test mode */ 2050527a6266SJeff Kirsher GPC_REG18 = 1<<21, /* Reg18 Power down */ 2051527a6266SJeff Kirsher GPC_REG12SEL = 3<<19, /* Reg12 power setting */ 2052527a6266SJeff Kirsher GPC_REG18SEL = 3<<17, /* Reg18 power setting */ 2053527a6266SJeff Kirsher GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */ 2054527a6266SJeff Kirsher 2055527a6266SJeff Kirsher GPC_LEDMUX = 3<<14, /* LED Mux */ 2056527a6266SJeff Kirsher GPC_INTPOL = 1<<13, /* Interrupt polarity */ 2057527a6266SJeff Kirsher GPC_DETECT = 1<<12, /* Energy detect */ 2058527a6266SJeff Kirsher GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */ 2059527a6266SJeff Kirsher GPC_SLAVE = 1<<10, /* Slave mode */ 2060527a6266SJeff Kirsher GPC_PAUSE = 1<<9, /* Pause enable */ 2061527a6266SJeff Kirsher GPC_LEDCTL = 3<<6, /* GPHY Leds */ 2062527a6266SJeff Kirsher 2063527a6266SJeff Kirsher GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 2064527a6266SJeff Kirsher GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 2065527a6266SJeff Kirsher }; 2066527a6266SJeff Kirsher 2067527a6266SJeff Kirsher /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2068527a6266SJeff Kirsher /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2069527a6266SJeff Kirsher enum { 2070527a6266SJeff Kirsher GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */ 2071527a6266SJeff Kirsher GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */ 2072527a6266SJeff Kirsher GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */ 2073527a6266SJeff Kirsher GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */ 2074527a6266SJeff Kirsher GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */ 2075527a6266SJeff Kirsher GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */ 2076527a6266SJeff Kirsher 20779cfe8b15SMirko Lindner #define GMAC_DEF_MSK (GM_IS_TX_FF_UR | GM_IS_RX_FF_OR) 2078527a6266SJeff Kirsher }; 2079527a6266SJeff Kirsher 2080527a6266SJeff Kirsher /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2081527a6266SJeff Kirsher enum { /* Bits 15.. 2: reserved */ 2082527a6266SJeff Kirsher GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */ 2083527a6266SJeff Kirsher GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */ 2084527a6266SJeff Kirsher }; 2085527a6266SJeff Kirsher 2086527a6266SJeff Kirsher 2087527a6266SJeff Kirsher /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 2088527a6266SJeff Kirsher enum { 2089527a6266SJeff Kirsher WOL_CTL_LINK_CHG_OCC = 1<<15, 2090527a6266SJeff Kirsher WOL_CTL_MAGIC_PKT_OCC = 1<<14, 2091527a6266SJeff Kirsher WOL_CTL_PATTERN_OCC = 1<<13, 2092527a6266SJeff Kirsher WOL_CTL_CLEAR_RESULT = 1<<12, 2093527a6266SJeff Kirsher WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, 2094527a6266SJeff Kirsher WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, 2095527a6266SJeff Kirsher WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, 2096527a6266SJeff Kirsher WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8, 2097527a6266SJeff Kirsher WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, 2098527a6266SJeff Kirsher WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, 2099527a6266SJeff Kirsher WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, 2100527a6266SJeff Kirsher WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4, 2101527a6266SJeff Kirsher WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, 2102527a6266SJeff Kirsher WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, 2103527a6266SJeff Kirsher WOL_CTL_ENA_PATTERN_UNIT = 1<<1, 2104527a6266SJeff Kirsher WOL_CTL_DIS_PATTERN_UNIT = 1<<0, 2105527a6266SJeff Kirsher }; 2106527a6266SJeff Kirsher 2107527a6266SJeff Kirsher 2108527a6266SJeff Kirsher /* Control flags */ 2109527a6266SJeff Kirsher enum { 2110527a6266SJeff Kirsher UDPTCP = 1<<0, 2111527a6266SJeff Kirsher CALSUM = 1<<1, 2112527a6266SJeff Kirsher WR_SUM = 1<<2, 2113527a6266SJeff Kirsher INIT_SUM= 1<<3, 2114527a6266SJeff Kirsher LOCK_SUM= 1<<4, 2115527a6266SJeff Kirsher INS_VLAN= 1<<5, 2116527a6266SJeff Kirsher EOP = 1<<7, 2117527a6266SJeff Kirsher }; 2118527a6266SJeff Kirsher 2119527a6266SJeff Kirsher enum { 2120527a6266SJeff Kirsher HW_OWNER = 1<<7, 2121527a6266SJeff Kirsher OP_TCPWRITE = 0x11, 2122527a6266SJeff Kirsher OP_TCPSTART = 0x12, 2123527a6266SJeff Kirsher OP_TCPINIT = 0x14, 2124527a6266SJeff Kirsher OP_TCPLCK = 0x18, 2125527a6266SJeff Kirsher OP_TCPCHKSUM = OP_TCPSTART, 2126527a6266SJeff Kirsher OP_TCPIS = OP_TCPINIT | OP_TCPSTART, 2127527a6266SJeff Kirsher OP_TCPLW = OP_TCPLCK | OP_TCPWRITE, 2128527a6266SJeff Kirsher OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, 2129527a6266SJeff Kirsher OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, 2130527a6266SJeff Kirsher 2131527a6266SJeff Kirsher OP_ADDR64 = 0x21, 2132527a6266SJeff Kirsher OP_VLAN = 0x22, 2133527a6266SJeff Kirsher OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, 2134527a6266SJeff Kirsher OP_LRGLEN = 0x24, 2135527a6266SJeff Kirsher OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, 2136527a6266SJeff Kirsher OP_MSS = 0x28, 2137527a6266SJeff Kirsher OP_MSSVLAN = OP_MSS | OP_VLAN, 2138527a6266SJeff Kirsher 2139527a6266SJeff Kirsher OP_BUFFER = 0x40, 2140527a6266SJeff Kirsher OP_PACKET = 0x41, 2141527a6266SJeff Kirsher OP_LARGESEND = 0x43, 2142527a6266SJeff Kirsher OP_LSOV2 = 0x45, 2143527a6266SJeff Kirsher 2144527a6266SJeff Kirsher /* YUKON-2 STATUS opcodes defines */ 2145527a6266SJeff Kirsher OP_RXSTAT = 0x60, 2146527a6266SJeff Kirsher OP_RXTIMESTAMP = 0x61, 2147527a6266SJeff Kirsher OP_RXVLAN = 0x62, 2148527a6266SJeff Kirsher OP_RXCHKS = 0x64, 2149527a6266SJeff Kirsher OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, 2150527a6266SJeff Kirsher OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, 2151527a6266SJeff Kirsher OP_RSS_HASH = 0x65, 2152527a6266SJeff Kirsher OP_TXINDEXLE = 0x68, 2153527a6266SJeff Kirsher OP_MACSEC = 0x6c, 2154527a6266SJeff Kirsher OP_PUTIDX = 0x70, 2155527a6266SJeff Kirsher }; 2156527a6266SJeff Kirsher 2157527a6266SJeff Kirsher enum status_css { 2158527a6266SJeff Kirsher CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */ 2159527a6266SJeff Kirsher CSS_ISUDP = 1<<6, /* packet is a UDP packet */ 2160527a6266SJeff Kirsher CSS_ISTCP = 1<<5, /* packet is a TCP packet */ 2161527a6266SJeff Kirsher CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */ 2162527a6266SJeff Kirsher CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */ 2163527a6266SJeff Kirsher CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */ 2164527a6266SJeff Kirsher CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */ 2165527a6266SJeff Kirsher CSS_LINK_BIT = 1<<0, /* port number (legacy) */ 2166527a6266SJeff Kirsher }; 2167527a6266SJeff Kirsher 2168527a6266SJeff Kirsher /* Yukon 2 hardware interface */ 2169527a6266SJeff Kirsher struct sky2_tx_le { 2170527a6266SJeff Kirsher __le32 addr; 2171527a6266SJeff Kirsher __le16 length; /* also vlan tag or checksum start */ 2172527a6266SJeff Kirsher u8 ctrl; 2173527a6266SJeff Kirsher u8 opcode; 2174527a6266SJeff Kirsher } __packed; 2175527a6266SJeff Kirsher 2176527a6266SJeff Kirsher struct sky2_rx_le { 2177527a6266SJeff Kirsher __le32 addr; 2178527a6266SJeff Kirsher __le16 length; 2179527a6266SJeff Kirsher u8 ctrl; 2180527a6266SJeff Kirsher u8 opcode; 2181527a6266SJeff Kirsher } __packed; 2182527a6266SJeff Kirsher 2183527a6266SJeff Kirsher struct sky2_status_le { 2184527a6266SJeff Kirsher __le32 status; /* also checksum */ 2185527a6266SJeff Kirsher __le16 length; /* also vlan tag */ 2186527a6266SJeff Kirsher u8 css; 2187527a6266SJeff Kirsher u8 opcode; 2188527a6266SJeff Kirsher } __packed; 2189527a6266SJeff Kirsher 2190527a6266SJeff Kirsher struct tx_ring_info { 2191527a6266SJeff Kirsher struct sk_buff *skb; 2192527a6266SJeff Kirsher unsigned long flags; 2193527a6266SJeff Kirsher #define TX_MAP_SINGLE 0x0001 2194527a6266SJeff Kirsher #define TX_MAP_PAGE 0x0002 2195527a6266SJeff Kirsher DEFINE_DMA_UNMAP_ADDR(mapaddr); 2196527a6266SJeff Kirsher DEFINE_DMA_UNMAP_LEN(maplen); 2197527a6266SJeff Kirsher }; 2198527a6266SJeff Kirsher 2199527a6266SJeff Kirsher struct rx_ring_info { 2200527a6266SJeff Kirsher struct sk_buff *skb; 2201527a6266SJeff Kirsher dma_addr_t data_addr; 2202527a6266SJeff Kirsher DEFINE_DMA_UNMAP_LEN(data_size); 2203527a6266SJeff Kirsher dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; 2204527a6266SJeff Kirsher }; 2205527a6266SJeff Kirsher 2206527a6266SJeff Kirsher enum flow_control { 2207527a6266SJeff Kirsher FC_NONE = 0, 2208527a6266SJeff Kirsher FC_TX = 1, 2209527a6266SJeff Kirsher FC_RX = 2, 2210527a6266SJeff Kirsher FC_BOTH = 3, 2211527a6266SJeff Kirsher }; 2212527a6266SJeff Kirsher 2213527a6266SJeff Kirsher struct sky2_stats { 2214527a6266SJeff Kirsher struct u64_stats_sync syncp; 2215527a6266SJeff Kirsher u64 packets; 2216527a6266SJeff Kirsher u64 bytes; 2217527a6266SJeff Kirsher }; 2218527a6266SJeff Kirsher 2219527a6266SJeff Kirsher struct sky2_port { 2220527a6266SJeff Kirsher struct sky2_hw *hw; 2221527a6266SJeff Kirsher struct net_device *netdev; 2222527a6266SJeff Kirsher unsigned port; 2223527a6266SJeff Kirsher u32 msg_enable; 2224527a6266SJeff Kirsher spinlock_t phy_lock; 2225527a6266SJeff Kirsher 2226527a6266SJeff Kirsher struct tx_ring_info *tx_ring; 2227527a6266SJeff Kirsher struct sky2_tx_le *tx_le; 2228527a6266SJeff Kirsher struct sky2_stats tx_stats; 2229527a6266SJeff Kirsher 2230527a6266SJeff Kirsher u16 tx_ring_size; 2231527a6266SJeff Kirsher u16 tx_cons; /* next le to check */ 2232527a6266SJeff Kirsher u16 tx_prod; /* next le to use */ 2233527a6266SJeff Kirsher u16 tx_next; /* debug only */ 2234527a6266SJeff Kirsher 2235527a6266SJeff Kirsher u16 tx_pending; 2236527a6266SJeff Kirsher u16 tx_last_mss; 2237527a6266SJeff Kirsher u32 tx_last_upper; 2238527a6266SJeff Kirsher u32 tx_tcpsum; 2239527a6266SJeff Kirsher 2240527a6266SJeff Kirsher struct rx_ring_info *rx_ring ____cacheline_aligned_in_smp; 2241527a6266SJeff Kirsher struct sky2_rx_le *rx_le; 2242527a6266SJeff Kirsher struct sky2_stats rx_stats; 2243527a6266SJeff Kirsher 2244527a6266SJeff Kirsher u16 rx_next; /* next re to check */ 2245527a6266SJeff Kirsher u16 rx_put; /* next le index to use */ 2246527a6266SJeff Kirsher u16 rx_pending; 2247527a6266SJeff Kirsher u16 rx_data_size; 2248527a6266SJeff Kirsher u16 rx_nfrags; 2249527a6266SJeff Kirsher 22504a7c9726STobias Klauser unsigned long last_rx; 2251527a6266SJeff Kirsher struct { 2252527a6266SJeff Kirsher unsigned long last; 2253527a6266SJeff Kirsher u32 mac_rp; 2254527a6266SJeff Kirsher u8 mac_lev; 2255527a6266SJeff Kirsher u8 fifo_rp; 2256527a6266SJeff Kirsher u8 fifo_lev; 2257527a6266SJeff Kirsher } check; 2258527a6266SJeff Kirsher 2259527a6266SJeff Kirsher dma_addr_t rx_le_map; 2260527a6266SJeff Kirsher dma_addr_t tx_le_map; 2261527a6266SJeff Kirsher 2262527a6266SJeff Kirsher u16 advertising; /* ADVERTISED_ bits */ 2263527a6266SJeff Kirsher u16 speed; /* SPEED_1000, SPEED_100, ... */ 2264527a6266SJeff Kirsher u8 wol; /* WAKE_ bits */ 2265527a6266SJeff Kirsher u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */ 2266527a6266SJeff Kirsher u16 flags; 2267527a6266SJeff Kirsher #define SKY2_FLAG_AUTO_SPEED 0x0002 2268527a6266SJeff Kirsher #define SKY2_FLAG_AUTO_PAUSE 0x0004 2269527a6266SJeff Kirsher 2270527a6266SJeff Kirsher enum flow_control flow_mode; 2271527a6266SJeff Kirsher enum flow_control flow_status; 2272527a6266SJeff Kirsher 2273527a6266SJeff Kirsher #ifdef CONFIG_SKY2_DEBUG 2274527a6266SJeff Kirsher struct dentry *debugfs; 2275527a6266SJeff Kirsher #endif 2276527a6266SJeff Kirsher }; 2277527a6266SJeff Kirsher 2278527a6266SJeff Kirsher struct sky2_hw { 2279527a6266SJeff Kirsher void __iomem *regs; 2280527a6266SJeff Kirsher struct pci_dev *pdev; 2281527a6266SJeff Kirsher struct napi_struct napi; 2282527a6266SJeff Kirsher struct net_device *dev[2]; 2283527a6266SJeff Kirsher unsigned long flags; 2284527a6266SJeff Kirsher #define SKY2_HW_USE_MSI 0x00000001 2285527a6266SJeff Kirsher #define SKY2_HW_FIBRE_PHY 0x00000002 2286527a6266SJeff Kirsher #define SKY2_HW_GIGABIT 0x00000004 2287527a6266SJeff Kirsher #define SKY2_HW_NEWER_PHY 0x00000008 2288527a6266SJeff Kirsher #define SKY2_HW_RAM_BUFFER 0x00000010 2289527a6266SJeff Kirsher #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */ 2290527a6266SJeff Kirsher #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */ 2291527a6266SJeff Kirsher #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */ 2292527a6266SJeff Kirsher #define SKY2_HW_RSS_BROKEN 0x00000100 2293527a6266SJeff Kirsher #define SKY2_HW_VLAN_BROKEN 0x00000200 2294527a6266SJeff Kirsher #define SKY2_HW_RSS_CHKSUM 0x00000400 /* RSS requires chksum */ 2295282edcecSstephen hemminger #define SKY2_HW_IRQ_SETUP 0x00000800 2296527a6266SJeff Kirsher 2297527a6266SJeff Kirsher u8 chip_id; 2298527a6266SJeff Kirsher u8 chip_rev; 2299527a6266SJeff Kirsher u8 pmd_type; 2300527a6266SJeff Kirsher u8 ports; 2301527a6266SJeff Kirsher 2302527a6266SJeff Kirsher struct sky2_status_le *st_le; 2303527a6266SJeff Kirsher u32 st_size; 2304527a6266SJeff Kirsher u32 st_idx; 2305527a6266SJeff Kirsher dma_addr_t st_dma; 2306527a6266SJeff Kirsher 2307527a6266SJeff Kirsher struct timer_list watchdog_timer; 2308527a6266SJeff Kirsher struct work_struct restart_work; 2309527a6266SJeff Kirsher wait_queue_head_t msi_wait; 2310527a6266SJeff Kirsher 2311527a6266SJeff Kirsher char irq_name[0]; 2312527a6266SJeff Kirsher }; 2313527a6266SJeff Kirsher 2314527a6266SJeff Kirsher static inline int sky2_is_copper(const struct sky2_hw *hw) 2315527a6266SJeff Kirsher { 2316527a6266SJeff Kirsher return !(hw->flags & SKY2_HW_FIBRE_PHY); 2317527a6266SJeff Kirsher } 2318527a6266SJeff Kirsher 2319527a6266SJeff Kirsher /* Register accessor for memory mapped device */ 2320527a6266SJeff Kirsher static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg) 2321527a6266SJeff Kirsher { 2322527a6266SJeff Kirsher return readl(hw->regs + reg); 2323527a6266SJeff Kirsher } 2324527a6266SJeff Kirsher 2325527a6266SJeff Kirsher static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg) 2326527a6266SJeff Kirsher { 2327527a6266SJeff Kirsher return readw(hw->regs + reg); 2328527a6266SJeff Kirsher } 2329527a6266SJeff Kirsher 2330527a6266SJeff Kirsher static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg) 2331527a6266SJeff Kirsher { 2332527a6266SJeff Kirsher return readb(hw->regs + reg); 2333527a6266SJeff Kirsher } 2334527a6266SJeff Kirsher 2335527a6266SJeff Kirsher static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val) 2336527a6266SJeff Kirsher { 2337527a6266SJeff Kirsher writel(val, hw->regs + reg); 2338527a6266SJeff Kirsher } 2339527a6266SJeff Kirsher 2340527a6266SJeff Kirsher static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val) 2341527a6266SJeff Kirsher { 2342527a6266SJeff Kirsher writew(val, hw->regs + reg); 2343527a6266SJeff Kirsher } 2344527a6266SJeff Kirsher 2345527a6266SJeff Kirsher static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val) 2346527a6266SJeff Kirsher { 2347527a6266SJeff Kirsher writeb(val, hw->regs + reg); 2348527a6266SJeff Kirsher } 2349527a6266SJeff Kirsher 2350527a6266SJeff Kirsher /* Yukon PHY related registers */ 2351527a6266SJeff Kirsher #define SK_GMAC_REG(port,reg) \ 2352527a6266SJeff Kirsher (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg)) 2353527a6266SJeff Kirsher #define GM_PHY_RETRIES 100 2354527a6266SJeff Kirsher 2355527a6266SJeff Kirsher static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg) 2356527a6266SJeff Kirsher { 2357527a6266SJeff Kirsher return sky2_read16(hw, SK_GMAC_REG(port,reg)); 2358527a6266SJeff Kirsher } 2359527a6266SJeff Kirsher 2360527a6266SJeff Kirsher static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg) 2361527a6266SJeff Kirsher { 2362527a6266SJeff Kirsher unsigned base = SK_GMAC_REG(port, reg); 2363527a6266SJeff Kirsher return (u32) sky2_read16(hw, base) 2364527a6266SJeff Kirsher | (u32) sky2_read16(hw, base+4) << 16; 2365527a6266SJeff Kirsher } 2366527a6266SJeff Kirsher 2367527a6266SJeff Kirsher static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg) 2368527a6266SJeff Kirsher { 2369527a6266SJeff Kirsher unsigned base = SK_GMAC_REG(port, reg); 2370527a6266SJeff Kirsher 2371527a6266SJeff Kirsher return (u64) sky2_read16(hw, base) 2372527a6266SJeff Kirsher | (u64) sky2_read16(hw, base+4) << 16 2373527a6266SJeff Kirsher | (u64) sky2_read16(hw, base+8) << 32 2374527a6266SJeff Kirsher | (u64) sky2_read16(hw, base+12) << 48; 2375527a6266SJeff Kirsher } 2376527a6266SJeff Kirsher 2377527a6266SJeff Kirsher /* There is no way to atomically read32 bit values from PHY, so retry */ 2378527a6266SJeff Kirsher static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg) 2379527a6266SJeff Kirsher { 2380527a6266SJeff Kirsher u32 val; 2381527a6266SJeff Kirsher 2382527a6266SJeff Kirsher do { 2383527a6266SJeff Kirsher val = gma_read32(hw, port, reg); 2384527a6266SJeff Kirsher } while (gma_read32(hw, port, reg) != val); 2385527a6266SJeff Kirsher 2386527a6266SJeff Kirsher return val; 2387527a6266SJeff Kirsher } 2388527a6266SJeff Kirsher 2389527a6266SJeff Kirsher static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg) 2390527a6266SJeff Kirsher { 2391527a6266SJeff Kirsher u64 val; 2392527a6266SJeff Kirsher 2393527a6266SJeff Kirsher do { 2394527a6266SJeff Kirsher val = gma_read64(hw, port, reg); 2395527a6266SJeff Kirsher } while (gma_read64(hw, port, reg) != val); 2396527a6266SJeff Kirsher 2397527a6266SJeff Kirsher return val; 2398527a6266SJeff Kirsher } 2399527a6266SJeff Kirsher 2400527a6266SJeff Kirsher static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v) 2401527a6266SJeff Kirsher { 2402527a6266SJeff Kirsher sky2_write16(hw, SK_GMAC_REG(port,r), v); 2403527a6266SJeff Kirsher } 2404527a6266SJeff Kirsher 2405527a6266SJeff Kirsher static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg, 2406527a6266SJeff Kirsher const u8 *addr) 2407527a6266SJeff Kirsher { 2408527a6266SJeff Kirsher gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8)); 2409527a6266SJeff Kirsher gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8)); 2410527a6266SJeff Kirsher gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8)); 2411527a6266SJeff Kirsher } 2412527a6266SJeff Kirsher 2413527a6266SJeff Kirsher /* PCI config space access */ 2414527a6266SJeff Kirsher static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg) 2415527a6266SJeff Kirsher { 2416527a6266SJeff Kirsher return sky2_read32(hw, Y2_CFG_SPC + reg); 2417527a6266SJeff Kirsher } 2418527a6266SJeff Kirsher 2419527a6266SJeff Kirsher static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg) 2420527a6266SJeff Kirsher { 2421527a6266SJeff Kirsher return sky2_read16(hw, Y2_CFG_SPC + reg); 2422527a6266SJeff Kirsher } 2423527a6266SJeff Kirsher 2424527a6266SJeff Kirsher static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val) 2425527a6266SJeff Kirsher { 2426527a6266SJeff Kirsher sky2_write32(hw, Y2_CFG_SPC + reg, val); 2427527a6266SJeff Kirsher } 2428527a6266SJeff Kirsher 2429527a6266SJeff Kirsher static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val) 2430527a6266SJeff Kirsher { 2431527a6266SJeff Kirsher sky2_write16(hw, Y2_CFG_SPC + reg, val); 2432527a6266SJeff Kirsher } 2433527a6266SJeff Kirsher #endif 2434