1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 #include <linux/of_device.h> 48 #include <linux/of_net.h> 49 50 #include <asm/irq.h> 51 52 #include "sky2.h" 53 54 #define DRV_NAME "sky2" 55 #define DRV_VERSION "1.30" 56 57 /* 58 * The Yukon II chipset takes 64 bit command blocks (called list elements) 59 * that are organized into three (receive, transmit, status) different rings 60 * similar to Tigon3. 61 */ 62 63 #define RX_LE_SIZE 1024 64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 66 #define RX_DEF_PENDING RX_MAX_PENDING 67 68 /* This is the worst case number of transmit list elements for a single skb: 69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 70 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 71 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 72 #define TX_MAX_PENDING 1024 73 #define TX_DEF_PENDING 63 74 75 #define TX_WATCHDOG (5 * HZ) 76 #define NAPI_WEIGHT 64 77 #define PHY_RETRIES 1000 78 79 #define SKY2_EEPROM_MAGIC 0x9955aabb 80 81 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 82 83 static const u32 default_msg = 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 87 88 static int debug = -1; /* defaults above */ 89 module_param(debug, int, 0); 90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 91 92 static int copybreak __read_mostly = 128; 93 module_param(copybreak, int, 0); 94 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 95 96 static int disable_msi = 0; 97 module_param(disable_msi, int, 0); 98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 99 100 static int legacy_pme = 0; 101 module_param(legacy_pme, int, 0); 102 MODULE_PARM_DESC(legacy_pme, "Legacy power management"); 103 104 static const struct pci_device_id sky2_id_table[] = { 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ 147 { 0 } 148 }; 149 150 MODULE_DEVICE_TABLE(pci, sky2_id_table); 151 152 /* Avoid conditionals by using array */ 153 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 154 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 155 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 156 157 static void sky2_set_multicast(struct net_device *dev); 158 static irqreturn_t sky2_intr(int irq, void *dev_id); 159 160 /* Access to PHY via serial interconnect */ 161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 162 { 163 int i; 164 165 gma_write16(hw, port, GM_SMI_DATA, val); 166 gma_write16(hw, port, GM_SMI_CTRL, 167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 168 169 for (i = 0; i < PHY_RETRIES; i++) { 170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 171 if (ctrl == 0xffff) 172 goto io_error; 173 174 if (!(ctrl & GM_SMI_CT_BUSY)) 175 return 0; 176 177 udelay(10); 178 } 179 180 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 181 return -ETIMEDOUT; 182 183 io_error: 184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 185 return -EIO; 186 } 187 188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 189 { 190 int i; 191 192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 194 195 for (i = 0; i < PHY_RETRIES; i++) { 196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 197 if (ctrl == 0xffff) 198 goto io_error; 199 200 if (ctrl & GM_SMI_CT_RD_VAL) { 201 *val = gma_read16(hw, port, GM_SMI_DATA); 202 return 0; 203 } 204 205 udelay(10); 206 } 207 208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 209 return -ETIMEDOUT; 210 io_error: 211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 212 return -EIO; 213 } 214 215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 216 { 217 u16 v; 218 __gm_phy_read(hw, port, reg, &v); 219 return v; 220 } 221 222 223 static void sky2_power_on(struct sky2_hw *hw) 224 { 225 /* switch power to VCC (WA for VAUX problem) */ 226 sky2_write8(hw, B0_POWER_CTRL, 227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 228 229 /* disable Core Clock Division, */ 230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 231 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 233 /* enable bits are inverted */ 234 sky2_write8(hw, B2_Y2_CLK_GATE, 235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 238 else 239 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 240 241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 242 u32 reg; 243 244 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 245 246 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 247 /* set all bits to 0 except bits 15..12 and 8 */ 248 reg &= P_ASPM_CONTROL_MSK; 249 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 250 251 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 252 /* set all bits to 0 except bits 28 & 27 */ 253 reg &= P_CTL_TIM_VMAIN_AV_MSK; 254 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 255 256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 257 258 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 259 260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 261 reg = sky2_read32(hw, B2_GP_IO); 262 reg |= GLB_GPIO_STAT_RACE_DIS; 263 sky2_write32(hw, B2_GP_IO, reg); 264 265 sky2_read32(hw, B2_GP_IO); 266 } 267 268 /* Turn on "driver loaded" LED */ 269 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 270 } 271 272 static void sky2_power_aux(struct sky2_hw *hw) 273 { 274 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 275 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 276 else 277 /* enable bits are inverted */ 278 sky2_write8(hw, B2_Y2_CLK_GATE, 279 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 280 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 281 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 282 283 /* switch power to VAUX if supported and PME from D3cold */ 284 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 285 pci_pme_capable(hw->pdev, PCI_D3cold)) 286 sky2_write8(hw, B0_POWER_CTRL, 287 (PC_VAUX_ENA | PC_VCC_ENA | 288 PC_VAUX_ON | PC_VCC_OFF)); 289 290 /* turn off "driver loaded LED" */ 291 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 292 } 293 294 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 295 { 296 u16 reg; 297 298 /* disable all GMAC IRQ's */ 299 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 300 301 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 302 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 303 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 304 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 305 306 reg = gma_read16(hw, port, GM_RX_CTRL); 307 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 308 gma_write16(hw, port, GM_RX_CTRL, reg); 309 } 310 311 /* flow control to advertise bits */ 312 static const u16 copper_fc_adv[] = { 313 [FC_NONE] = 0, 314 [FC_TX] = PHY_M_AN_ASP, 315 [FC_RX] = PHY_M_AN_PC, 316 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 317 }; 318 319 /* flow control to advertise bits when using 1000BaseX */ 320 static const u16 fiber_fc_adv[] = { 321 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 322 [FC_TX] = PHY_M_P_ASYM_MD_X, 323 [FC_RX] = PHY_M_P_SYM_MD_X, 324 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 325 }; 326 327 /* flow control to GMA disable bits */ 328 static const u16 gm_fc_disable[] = { 329 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 330 [FC_TX] = GM_GPCR_FC_RX_DIS, 331 [FC_RX] = GM_GPCR_FC_TX_DIS, 332 [FC_BOTH] = 0, 333 }; 334 335 336 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 337 { 338 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 339 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 340 341 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 342 !(hw->flags & SKY2_HW_NEWER_PHY)) { 343 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 344 345 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 346 PHY_M_EC_MAC_S_MSK); 347 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 348 349 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 350 if (hw->chip_id == CHIP_ID_YUKON_EC) 351 /* set downshift counter to 3x and enable downshift */ 352 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 353 else 354 /* set master & slave downshift counter to 1x */ 355 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 356 357 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 358 } 359 360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 361 if (sky2_is_copper(hw)) { 362 if (!(hw->flags & SKY2_HW_GIGABIT)) { 363 /* enable automatic crossover */ 364 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 365 366 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 367 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 368 u16 spec; 369 370 /* Enable Class A driver for FE+ A0 */ 371 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 372 spec |= PHY_M_FESC_SEL_CL_A; 373 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 374 } 375 } else { 376 /* disable energy detect */ 377 ctrl &= ~PHY_M_PC_EN_DET_MSK; 378 379 /* enable automatic crossover */ 380 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 381 382 /* downshift on PHY 88E1112 and 88E1149 is changed */ 383 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 384 (hw->flags & SKY2_HW_NEWER_PHY)) { 385 /* set downshift counter to 3x and enable downshift */ 386 ctrl &= ~PHY_M_PC_DSC_MSK; 387 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 388 } 389 } 390 } else { 391 /* workaround for deviation #4.88 (CRC errors) */ 392 /* disable Automatic Crossover */ 393 394 ctrl &= ~PHY_M_PC_MDIX_MSK; 395 } 396 397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 398 399 /* special setup for PHY 88E1112 Fiber */ 400 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 401 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 402 403 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 406 ctrl &= ~PHY_M_MAC_MD_MSK; 407 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 409 410 if (hw->pmd_type == 'P') { 411 /* select page 1 to access Fiber registers */ 412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 413 414 /* for SFP-module set SIGDET polarity to low */ 415 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 416 ctrl |= PHY_M_FIB_SIGD_POL; 417 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 418 } 419 420 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 421 } 422 423 ctrl = PHY_CT_RESET; 424 ct1000 = 0; 425 adv = PHY_AN_CSMA; 426 reg = 0; 427 428 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 429 if (sky2_is_copper(hw)) { 430 if (sky2->advertising & ADVERTISED_1000baseT_Full) 431 ct1000 |= PHY_M_1000C_AFD; 432 if (sky2->advertising & ADVERTISED_1000baseT_Half) 433 ct1000 |= PHY_M_1000C_AHD; 434 if (sky2->advertising & ADVERTISED_100baseT_Full) 435 adv |= PHY_M_AN_100_FD; 436 if (sky2->advertising & ADVERTISED_100baseT_Half) 437 adv |= PHY_M_AN_100_HD; 438 if (sky2->advertising & ADVERTISED_10baseT_Full) 439 adv |= PHY_M_AN_10_FD; 440 if (sky2->advertising & ADVERTISED_10baseT_Half) 441 adv |= PHY_M_AN_10_HD; 442 443 } else { /* special defines for FIBER (88E1040S only) */ 444 if (sky2->advertising & ADVERTISED_1000baseT_Full) 445 adv |= PHY_M_AN_1000X_AFD; 446 if (sky2->advertising & ADVERTISED_1000baseT_Half) 447 adv |= PHY_M_AN_1000X_AHD; 448 } 449 450 /* Restart Auto-negotiation */ 451 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 452 } else { 453 /* forced speed/duplex settings */ 454 ct1000 = PHY_M_1000C_MSE; 455 456 /* Disable auto update for duplex flow control and duplex */ 457 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 458 459 switch (sky2->speed) { 460 case SPEED_1000: 461 ctrl |= PHY_CT_SP1000; 462 reg |= GM_GPCR_SPEED_1000; 463 break; 464 case SPEED_100: 465 ctrl |= PHY_CT_SP100; 466 reg |= GM_GPCR_SPEED_100; 467 break; 468 } 469 470 if (sky2->duplex == DUPLEX_FULL) { 471 reg |= GM_GPCR_DUP_FULL; 472 ctrl |= PHY_CT_DUP_MD; 473 } else if (sky2->speed < SPEED_1000) 474 sky2->flow_mode = FC_NONE; 475 } 476 477 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 478 if (sky2_is_copper(hw)) 479 adv |= copper_fc_adv[sky2->flow_mode]; 480 else 481 adv |= fiber_fc_adv[sky2->flow_mode]; 482 } else { 483 reg |= GM_GPCR_AU_FCT_DIS; 484 reg |= gm_fc_disable[sky2->flow_mode]; 485 486 /* Forward pause packets to GMAC? */ 487 if (sky2->flow_mode & FC_RX) 488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 489 else 490 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 491 } 492 493 gma_write16(hw, port, GM_GP_CTRL, reg); 494 495 if (hw->flags & SKY2_HW_GIGABIT) 496 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 497 498 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 499 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 500 501 /* Setup Phy LED's */ 502 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 503 ledover = 0; 504 505 switch (hw->chip_id) { 506 case CHIP_ID_YUKON_FE: 507 /* on 88E3082 these bits are at 11..9 (shifted left) */ 508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 509 510 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 511 512 /* delete ACT LED control bits */ 513 ctrl &= ~PHY_M_FELP_LED1_MSK; 514 /* change ACT LED control to blink mode */ 515 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 517 break; 518 519 case CHIP_ID_YUKON_FE_P: 520 /* Enable Link Partner Next Page */ 521 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 522 ctrl |= PHY_M_PC_ENA_LIP_NP; 523 524 /* disable Energy Detect and enable scrambler */ 525 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 527 528 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 529 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 530 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 531 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 532 533 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 534 break; 535 536 case CHIP_ID_YUKON_XL: 537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 538 539 /* select page 3 to access LED control register */ 540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 541 542 /* set LED Function Control register */ 543 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 544 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 545 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 546 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 547 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 548 549 /* set Polarity Control register */ 550 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 551 (PHY_M_POLC_LS1_P_MIX(4) | 552 PHY_M_POLC_IS0_P_MIX(4) | 553 PHY_M_POLC_LOS_CTRL(2) | 554 PHY_M_POLC_INIT_CTRL(2) | 555 PHY_M_POLC_STA1_CTRL(2) | 556 PHY_M_POLC_STA0_CTRL(2))); 557 558 /* restore page register */ 559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 560 break; 561 562 case CHIP_ID_YUKON_EC_U: 563 case CHIP_ID_YUKON_EX: 564 case CHIP_ID_YUKON_SUPR: 565 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 566 567 /* select page 3 to access LED control register */ 568 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 569 570 /* set LED Function Control register */ 571 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 572 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 573 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 574 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 575 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 576 577 /* set Blink Rate in LED Timer Control Register */ 578 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 579 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 580 /* restore page register */ 581 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 582 break; 583 584 default: 585 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 586 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 587 588 /* turn off the Rx LED (LED_RX) */ 589 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 590 } 591 592 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 593 /* apply fixes in PHY AFE */ 594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 595 596 /* increase differential signal amplitude in 10BASE-T */ 597 gm_phy_write(hw, port, 0x18, 0xaa99); 598 gm_phy_write(hw, port, 0x17, 0x2011); 599 600 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 601 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 602 gm_phy_write(hw, port, 0x18, 0xa204); 603 gm_phy_write(hw, port, 0x17, 0x2002); 604 } 605 606 /* set page register to 0 */ 607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 608 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 609 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 610 /* apply workaround for integrated resistors calibration */ 611 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 612 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 613 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 614 /* apply fixes in PHY AFE */ 615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 616 617 /* apply RDAC termination workaround */ 618 gm_phy_write(hw, port, 24, 0x2800); 619 gm_phy_write(hw, port, 23, 0x2001); 620 621 /* set page register back to 0 */ 622 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 623 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 624 hw->chip_id < CHIP_ID_YUKON_SUPR) { 625 /* no effect on Yukon-XL */ 626 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 627 628 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 629 sky2->speed == SPEED_100) { 630 /* turn on 100 Mbps LED (LED_LINK100) */ 631 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 632 } 633 634 if (ledover) 635 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 636 637 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 638 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 639 int i; 640 /* This a phy register setup workaround copied from vendor driver. */ 641 static const struct { 642 u16 reg, val; 643 } eee_afe[] = { 644 { 0x156, 0x58ce }, 645 { 0x153, 0x99eb }, 646 { 0x141, 0x8064 }, 647 /* { 0x155, 0x130b },*/ 648 { 0x000, 0x0000 }, 649 { 0x151, 0x8433 }, 650 { 0x14b, 0x8c44 }, 651 { 0x14c, 0x0f90 }, 652 { 0x14f, 0x39aa }, 653 /* { 0x154, 0x2f39 },*/ 654 { 0x14d, 0xba33 }, 655 { 0x144, 0x0048 }, 656 { 0x152, 0x2010 }, 657 /* { 0x158, 0x1223 },*/ 658 { 0x140, 0x4444 }, 659 { 0x154, 0x2f3b }, 660 { 0x158, 0xb203 }, 661 { 0x157, 0x2029 }, 662 }; 663 664 /* Start Workaround for OptimaEEE Rev.Z0 */ 665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 666 667 gm_phy_write(hw, port, 1, 0x4099); 668 gm_phy_write(hw, port, 3, 0x1120); 669 gm_phy_write(hw, port, 11, 0x113c); 670 gm_phy_write(hw, port, 14, 0x8100); 671 gm_phy_write(hw, port, 15, 0x112a); 672 gm_phy_write(hw, port, 17, 0x1008); 673 674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 675 gm_phy_write(hw, port, 1, 0x20b0); 676 677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 678 679 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 680 /* apply AFE settings */ 681 gm_phy_write(hw, port, 17, eee_afe[i].val); 682 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 683 } 684 685 /* End Workaround for OptimaEEE */ 686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 687 688 /* Enable 10Base-Te (EEE) */ 689 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 690 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 691 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 692 reg | PHY_M_10B_TE_ENABLE); 693 } 694 } 695 696 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 697 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 698 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 699 else 700 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 701 } 702 703 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 704 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 705 706 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 707 { 708 u32 reg1; 709 710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 712 reg1 &= ~phy_power[port]; 713 714 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 715 reg1 |= coma_mode[port]; 716 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 719 sky2_pci_read32(hw, PCI_DEV_REG1); 720 721 if (hw->chip_id == CHIP_ID_YUKON_FE) 722 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 723 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 725 } 726 727 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 728 { 729 u32 reg1; 730 u16 ctrl; 731 732 /* release GPHY Control reset */ 733 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 734 735 /* release GMAC reset */ 736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 737 738 if (hw->flags & SKY2_HW_NEWER_PHY) { 739 /* select page 2 to access MAC control register */ 740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 741 742 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 743 /* allow GMII Power Down */ 744 ctrl &= ~PHY_M_MAC_GMIF_PUP; 745 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 746 747 /* set page register back to 0 */ 748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 749 } 750 751 /* setup General Purpose Control Register */ 752 gma_write16(hw, port, GM_GP_CTRL, 753 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 754 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 755 GM_GPCR_AU_SPD_DIS); 756 757 if (hw->chip_id != CHIP_ID_YUKON_EC) { 758 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 759 /* select page 2 to access MAC control register */ 760 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 761 762 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 763 /* enable Power Down */ 764 ctrl |= PHY_M_PC_POW_D_ENA; 765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 766 767 /* set page register back to 0 */ 768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 769 } 770 771 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 772 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 773 } 774 775 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 776 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 777 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 778 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 779 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 780 } 781 782 /* configure IPG according to used link speed */ 783 static void sky2_set_ipg(struct sky2_port *sky2) 784 { 785 u16 reg; 786 787 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 788 reg &= ~GM_SMOD_IPG_MSK; 789 if (sky2->speed > SPEED_100) 790 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 791 else 792 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 793 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 794 } 795 796 /* Enable Rx/Tx */ 797 static void sky2_enable_rx_tx(struct sky2_port *sky2) 798 { 799 struct sky2_hw *hw = sky2->hw; 800 unsigned port = sky2->port; 801 u16 reg; 802 803 reg = gma_read16(hw, port, GM_GP_CTRL); 804 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 805 gma_write16(hw, port, GM_GP_CTRL, reg); 806 } 807 808 /* Force a renegotiation */ 809 static void sky2_phy_reinit(struct sky2_port *sky2) 810 { 811 spin_lock_bh(&sky2->phy_lock); 812 sky2_phy_init(sky2->hw, sky2->port); 813 sky2_enable_rx_tx(sky2); 814 spin_unlock_bh(&sky2->phy_lock); 815 } 816 817 /* Put device in state to listen for Wake On Lan */ 818 static void sky2_wol_init(struct sky2_port *sky2) 819 { 820 struct sky2_hw *hw = sky2->hw; 821 unsigned port = sky2->port; 822 enum flow_control save_mode; 823 u16 ctrl; 824 825 /* Bring hardware out of reset */ 826 sky2_write16(hw, B0_CTST, CS_RST_CLR); 827 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 828 829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 830 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 831 832 /* Force to 10/100 833 * sky2_reset will re-enable on resume 834 */ 835 save_mode = sky2->flow_mode; 836 ctrl = sky2->advertising; 837 838 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 839 sky2->flow_mode = FC_NONE; 840 841 spin_lock_bh(&sky2->phy_lock); 842 sky2_phy_power_up(hw, port); 843 sky2_phy_init(hw, port); 844 spin_unlock_bh(&sky2->phy_lock); 845 846 sky2->flow_mode = save_mode; 847 sky2->advertising = ctrl; 848 849 /* Set GMAC to no flow control and auto update for speed/duplex */ 850 gma_write16(hw, port, GM_GP_CTRL, 851 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 852 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 853 854 /* Set WOL address */ 855 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 856 sky2->netdev->dev_addr, ETH_ALEN); 857 858 /* Turn on appropriate WOL control bits */ 859 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 860 ctrl = 0; 861 if (sky2->wol & WAKE_PHY) 862 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 863 else 864 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 865 866 if (sky2->wol & WAKE_MAGIC) 867 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 868 else 869 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 870 871 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 872 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 873 874 /* Disable PiG firmware */ 875 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 876 877 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ 878 if (legacy_pme) { 879 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 880 reg1 |= PCI_Y2_PME_LEGACY; 881 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 882 } 883 884 /* block receiver */ 885 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 886 sky2_read32(hw, B0_CTST); 887 } 888 889 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 890 { 891 struct net_device *dev = hw->dev[port]; 892 893 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 894 hw->chip_rev != CHIP_REV_YU_EX_A0) || 895 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 896 /* Yukon-Extreme B0 and further Extreme devices */ 897 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 898 } else if (dev->mtu > ETH_DATA_LEN) { 899 /* set Tx GMAC FIFO Almost Empty Threshold */ 900 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 901 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 902 903 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 904 } else 905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 906 } 907 908 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 909 { 910 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 911 u16 reg; 912 u32 rx_reg; 913 int i; 914 const u8 *addr = hw->dev[port]->dev_addr; 915 916 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 918 919 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 920 921 if (hw->chip_id == CHIP_ID_YUKON_XL && 922 hw->chip_rev == CHIP_REV_YU_XL_A0 && 923 port == 1) { 924 /* WA DEV_472 -- looks like crossed wires on port 2 */ 925 /* clear GMAC 1 Control reset */ 926 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 927 do { 928 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 930 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 931 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 932 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 933 } 934 935 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 936 937 /* Enable Transmit FIFO Underrun */ 938 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 939 940 spin_lock_bh(&sky2->phy_lock); 941 sky2_phy_power_up(hw, port); 942 sky2_phy_init(hw, port); 943 spin_unlock_bh(&sky2->phy_lock); 944 945 /* MIB clear */ 946 reg = gma_read16(hw, port, GM_PHY_ADDR); 947 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 948 949 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 950 gma_read16(hw, port, i); 951 gma_write16(hw, port, GM_PHY_ADDR, reg); 952 953 /* transmit control */ 954 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 955 956 /* receive control reg: unicast + multicast + no FCS */ 957 gma_write16(hw, port, GM_RX_CTRL, 958 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 959 960 /* transmit flow control */ 961 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 962 963 /* transmit parameter */ 964 gma_write16(hw, port, GM_TX_PARAM, 965 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 966 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 967 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 968 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 969 970 /* serial mode register */ 971 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 972 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 973 974 if (hw->dev[port]->mtu > ETH_DATA_LEN) 975 reg |= GM_SMOD_JUMBO_ENA; 976 977 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 978 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 979 reg |= GM_NEW_FLOW_CTRL; 980 981 gma_write16(hw, port, GM_SERIAL_MODE, reg); 982 983 /* virtual address for data */ 984 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 985 986 /* physical address: used for pause frames */ 987 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 988 989 /* ignore counter overflows */ 990 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 991 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 992 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 993 994 /* Configure Rx MAC FIFO */ 995 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 996 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 997 if (hw->chip_id == CHIP_ID_YUKON_EX || 998 hw->chip_id == CHIP_ID_YUKON_FE_P) 999 rx_reg |= GMF_RX_OVER_ON; 1000 1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 1002 1003 if (hw->chip_id == CHIP_ID_YUKON_XL) { 1004 /* Hardware errata - clear flush mask */ 1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 1006 } else { 1007 /* Flush Rx MAC FIFO on any flow control or error */ 1008 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 1009 } 1010 1011 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 1012 reg = RX_GMF_FL_THR_DEF + 1; 1013 /* Another magic mystery workaround from sk98lin */ 1014 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1015 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1016 reg = 0x178; 1017 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1018 1019 /* Configure Tx MAC FIFO */ 1020 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1021 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1022 1023 /* On chips without ram buffer, pause is controlled by MAC level */ 1024 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1025 /* Pause threshold is scaled by 8 in bytes */ 1026 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1027 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1028 reg = 1568 / 8; 1029 else 1030 reg = 1024 / 8; 1031 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1032 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1033 1034 sky2_set_tx_stfwd(hw, port); 1035 } 1036 1037 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1038 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1039 /* disable dynamic watermark */ 1040 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1041 reg &= ~TX_DYN_WM_ENA; 1042 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1043 } 1044 } 1045 1046 /* Assign Ram Buffer allocation to queue */ 1047 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1048 { 1049 u32 end; 1050 1051 /* convert from K bytes to qwords used for hw register */ 1052 start *= 1024/8; 1053 space *= 1024/8; 1054 end = start + space - 1; 1055 1056 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1057 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1058 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1059 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1060 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1061 1062 if (q == Q_R1 || q == Q_R2) { 1063 u32 tp = space - space/4; 1064 1065 /* On receive queue's set the thresholds 1066 * give receiver priority when > 3/4 full 1067 * send pause when down to 2K 1068 */ 1069 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1070 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1071 1072 tp = space - 8192/8; 1073 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1074 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1075 } else { 1076 /* Enable store & forward on Tx queue's because 1077 * Tx FIFO is only 1K on Yukon 1078 */ 1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1080 } 1081 1082 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1083 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1084 } 1085 1086 /* Setup Bus Memory Interface */ 1087 static void sky2_qset(struct sky2_hw *hw, u16 q) 1088 { 1089 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1092 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1093 } 1094 1095 /* Setup prefetch unit registers. This is the interface between 1096 * hardware and driver list elements 1097 */ 1098 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1099 dma_addr_t addr, u32 last) 1100 { 1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1105 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1106 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1107 1108 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1109 } 1110 1111 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1112 { 1113 struct sky2_tx_le *le = sky2->tx_le + *slot; 1114 1115 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1116 le->ctrl = 0; 1117 return le; 1118 } 1119 1120 static void tx_init(struct sky2_port *sky2) 1121 { 1122 struct sky2_tx_le *le; 1123 1124 sky2->tx_prod = sky2->tx_cons = 0; 1125 sky2->tx_tcpsum = 0; 1126 sky2->tx_last_mss = 0; 1127 netdev_reset_queue(sky2->netdev); 1128 1129 le = get_tx_le(sky2, &sky2->tx_prod); 1130 le->addr = 0; 1131 le->opcode = OP_ADDR64 | HW_OWNER; 1132 sky2->tx_last_upper = 0; 1133 } 1134 1135 /* Update chip's next pointer */ 1136 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1137 { 1138 /* Make sure write' to descriptors are complete before we tell hardware */ 1139 wmb(); 1140 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1141 1142 /* Synchronize I/O on since next processor may write to tail */ 1143 mmiowb(); 1144 } 1145 1146 1147 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1148 { 1149 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1150 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1151 le->ctrl = 0; 1152 return le; 1153 } 1154 1155 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1156 { 1157 unsigned size; 1158 1159 /* Space needed for frame data + headers rounded up */ 1160 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1161 1162 /* Stopping point for hardware truncation */ 1163 return (size - 8) / sizeof(u32); 1164 } 1165 1166 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1167 { 1168 struct rx_ring_info *re; 1169 unsigned size; 1170 1171 /* Space needed for frame data + headers rounded up */ 1172 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1173 1174 sky2->rx_nfrags = size >> PAGE_SHIFT; 1175 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1176 1177 /* Compute residue after pages */ 1178 size -= sky2->rx_nfrags << PAGE_SHIFT; 1179 1180 /* Optimize to handle small packets and headers */ 1181 if (size < copybreak) 1182 size = copybreak; 1183 if (size < ETH_HLEN) 1184 size = ETH_HLEN; 1185 1186 return size; 1187 } 1188 1189 /* Build description to hardware for one receive segment */ 1190 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1191 dma_addr_t map, unsigned len) 1192 { 1193 struct sky2_rx_le *le; 1194 1195 if (sizeof(dma_addr_t) > sizeof(u32)) { 1196 le = sky2_next_rx(sky2); 1197 le->addr = cpu_to_le32(upper_32_bits(map)); 1198 le->opcode = OP_ADDR64 | HW_OWNER; 1199 } 1200 1201 le = sky2_next_rx(sky2); 1202 le->addr = cpu_to_le32(lower_32_bits(map)); 1203 le->length = cpu_to_le16(len); 1204 le->opcode = op | HW_OWNER; 1205 } 1206 1207 /* Build description to hardware for one possibly fragmented skb */ 1208 static void sky2_rx_submit(struct sky2_port *sky2, 1209 const struct rx_ring_info *re) 1210 { 1211 int i; 1212 1213 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1214 1215 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1216 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1217 } 1218 1219 1220 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1221 unsigned size) 1222 { 1223 struct sk_buff *skb = re->skb; 1224 int i; 1225 1226 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1227 if (pci_dma_mapping_error(pdev, re->data_addr)) 1228 goto mapping_error; 1229 1230 dma_unmap_len_set(re, data_size, size); 1231 1232 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1233 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1234 1235 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1236 skb_frag_size(frag), 1237 DMA_FROM_DEVICE); 1238 1239 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1240 goto map_page_error; 1241 } 1242 return 0; 1243 1244 map_page_error: 1245 while (--i >= 0) { 1246 pci_unmap_page(pdev, re->frag_addr[i], 1247 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1248 PCI_DMA_FROMDEVICE); 1249 } 1250 1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1252 PCI_DMA_FROMDEVICE); 1253 1254 mapping_error: 1255 if (net_ratelimit()) 1256 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1257 skb->dev->name); 1258 return -EIO; 1259 } 1260 1261 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1262 { 1263 struct sk_buff *skb = re->skb; 1264 int i; 1265 1266 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1267 PCI_DMA_FROMDEVICE); 1268 1269 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1270 pci_unmap_page(pdev, re->frag_addr[i], 1271 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1272 PCI_DMA_FROMDEVICE); 1273 } 1274 1275 /* Tell chip where to start receive checksum. 1276 * Actually has two checksums, but set both same to avoid possible byte 1277 * order problems. 1278 */ 1279 static void rx_set_checksum(struct sky2_port *sky2) 1280 { 1281 struct sky2_rx_le *le = sky2_next_rx(sky2); 1282 1283 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1284 le->ctrl = 0; 1285 le->opcode = OP_TCPSTART | HW_OWNER; 1286 1287 sky2_write32(sky2->hw, 1288 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1289 (sky2->netdev->features & NETIF_F_RXCSUM) 1290 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1291 } 1292 1293 /* Enable/disable receive hash calculation (RSS) */ 1294 static void rx_set_rss(struct net_device *dev, netdev_features_t features) 1295 { 1296 struct sky2_port *sky2 = netdev_priv(dev); 1297 struct sky2_hw *hw = sky2->hw; 1298 int i, nkeys = 4; 1299 1300 /* Supports IPv6 and other modes */ 1301 if (hw->flags & SKY2_HW_NEW_LE) { 1302 nkeys = 10; 1303 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1304 } 1305 1306 /* Program RSS initial values */ 1307 if (features & NETIF_F_RXHASH) { 1308 u32 rss_key[10]; 1309 1310 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 1311 for (i = 0; i < nkeys; i++) 1312 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1313 rss_key[i]); 1314 1315 /* Need to turn on (undocumented) flag to make hashing work */ 1316 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1317 RX_STFW_ENA); 1318 1319 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1320 BMU_ENA_RX_RSS_HASH); 1321 } else 1322 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1323 BMU_DIS_RX_RSS_HASH); 1324 } 1325 1326 /* 1327 * The RX Stop command will not work for Yukon-2 if the BMU does not 1328 * reach the end of packet and since we can't make sure that we have 1329 * incoming data, we must reset the BMU while it is not doing a DMA 1330 * transfer. Since it is possible that the RX path is still active, 1331 * the RX RAM buffer will be stopped first, so any possible incoming 1332 * data will not trigger a DMA. After the RAM buffer is stopped, the 1333 * BMU is polled until any DMA in progress is ended and only then it 1334 * will be reset. 1335 */ 1336 static void sky2_rx_stop(struct sky2_port *sky2) 1337 { 1338 struct sky2_hw *hw = sky2->hw; 1339 unsigned rxq = rxqaddr[sky2->port]; 1340 int i; 1341 1342 /* disable the RAM Buffer receive queue */ 1343 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1344 1345 for (i = 0; i < 0xffff; i++) 1346 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1347 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1348 goto stopped; 1349 1350 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1351 stopped: 1352 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1353 1354 /* reset the Rx prefetch unit */ 1355 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1356 mmiowb(); 1357 } 1358 1359 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1360 static void sky2_rx_clean(struct sky2_port *sky2) 1361 { 1362 unsigned i; 1363 1364 if (sky2->rx_le) 1365 memset(sky2->rx_le, 0, RX_LE_BYTES); 1366 1367 for (i = 0; i < sky2->rx_pending; i++) { 1368 struct rx_ring_info *re = sky2->rx_ring + i; 1369 1370 if (re->skb) { 1371 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1372 kfree_skb(re->skb); 1373 re->skb = NULL; 1374 } 1375 } 1376 } 1377 1378 /* Basic MII support */ 1379 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1380 { 1381 struct mii_ioctl_data *data = if_mii(ifr); 1382 struct sky2_port *sky2 = netdev_priv(dev); 1383 struct sky2_hw *hw = sky2->hw; 1384 int err = -EOPNOTSUPP; 1385 1386 if (!netif_running(dev)) 1387 return -ENODEV; /* Phy still in reset */ 1388 1389 switch (cmd) { 1390 case SIOCGMIIPHY: 1391 data->phy_id = PHY_ADDR_MARV; 1392 1393 /* fallthru */ 1394 case SIOCGMIIREG: { 1395 u16 val = 0; 1396 1397 spin_lock_bh(&sky2->phy_lock); 1398 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1399 spin_unlock_bh(&sky2->phy_lock); 1400 1401 data->val_out = val; 1402 break; 1403 } 1404 1405 case SIOCSMIIREG: 1406 spin_lock_bh(&sky2->phy_lock); 1407 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1408 data->val_in); 1409 spin_unlock_bh(&sky2->phy_lock); 1410 break; 1411 } 1412 return err; 1413 } 1414 1415 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1416 1417 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) 1418 { 1419 struct sky2_port *sky2 = netdev_priv(dev); 1420 struct sky2_hw *hw = sky2->hw; 1421 u16 port = sky2->port; 1422 1423 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1425 RX_VLAN_STRIP_ON); 1426 else 1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1428 RX_VLAN_STRIP_OFF); 1429 1430 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 1431 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1432 TX_VLAN_TAG_ON); 1433 1434 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1435 } else { 1436 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1437 TX_VLAN_TAG_OFF); 1438 1439 /* Can't do transmit offload of vlan without hw vlan */ 1440 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1441 } 1442 } 1443 1444 /* Amount of required worst case padding in rx buffer */ 1445 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1446 { 1447 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1448 } 1449 1450 /* 1451 * Allocate an skb for receiving. If the MTU is large enough 1452 * make the skb non-linear with a fragment list of pages. 1453 */ 1454 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1455 { 1456 struct sk_buff *skb; 1457 int i; 1458 1459 skb = __netdev_alloc_skb(sky2->netdev, 1460 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1461 gfp); 1462 if (!skb) 1463 goto nomem; 1464 1465 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1466 unsigned char *start; 1467 /* 1468 * Workaround for a bug in FIFO that cause hang 1469 * if the FIFO if the receive buffer is not 64 byte aligned. 1470 * The buffer returned from netdev_alloc_skb is 1471 * aligned except if slab debugging is enabled. 1472 */ 1473 start = PTR_ALIGN(skb->data, 8); 1474 skb_reserve(skb, start - skb->data); 1475 } else 1476 skb_reserve(skb, NET_IP_ALIGN); 1477 1478 for (i = 0; i < sky2->rx_nfrags; i++) { 1479 struct page *page = alloc_page(gfp); 1480 1481 if (!page) 1482 goto free_partial; 1483 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1484 } 1485 1486 return skb; 1487 free_partial: 1488 kfree_skb(skb); 1489 nomem: 1490 return NULL; 1491 } 1492 1493 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1494 { 1495 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1496 } 1497 1498 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1499 { 1500 struct sky2_hw *hw = sky2->hw; 1501 unsigned i; 1502 1503 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1504 1505 /* Fill Rx ring */ 1506 for (i = 0; i < sky2->rx_pending; i++) { 1507 struct rx_ring_info *re = sky2->rx_ring + i; 1508 1509 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1510 if (!re->skb) 1511 return -ENOMEM; 1512 1513 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1514 dev_kfree_skb(re->skb); 1515 re->skb = NULL; 1516 return -ENOMEM; 1517 } 1518 } 1519 return 0; 1520 } 1521 1522 /* 1523 * Setup receiver buffer pool. 1524 * Normal case this ends up creating one list element for skb 1525 * in the receive ring. Worst case if using large MTU and each 1526 * allocation falls on a different 64 bit region, that results 1527 * in 6 list elements per ring entry. 1528 * One element is used for checksum enable/disable, and one 1529 * extra to avoid wrap. 1530 */ 1531 static void sky2_rx_start(struct sky2_port *sky2) 1532 { 1533 struct sky2_hw *hw = sky2->hw; 1534 struct rx_ring_info *re; 1535 unsigned rxq = rxqaddr[sky2->port]; 1536 unsigned i, thresh; 1537 1538 sky2->rx_put = sky2->rx_next = 0; 1539 sky2_qset(hw, rxq); 1540 1541 /* On PCI express lowering the watermark gives better performance */ 1542 if (pci_is_pcie(hw->pdev)) 1543 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1544 1545 /* These chips have no ram buffer? 1546 * MAC Rx RAM Read is controlled by hardware */ 1547 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1548 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1549 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1550 1551 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1552 1553 if (!(hw->flags & SKY2_HW_NEW_LE)) 1554 rx_set_checksum(sky2); 1555 1556 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1557 rx_set_rss(sky2->netdev, sky2->netdev->features); 1558 1559 /* submit Rx ring */ 1560 for (i = 0; i < sky2->rx_pending; i++) { 1561 re = sky2->rx_ring + i; 1562 sky2_rx_submit(sky2, re); 1563 } 1564 1565 /* 1566 * The receiver hangs if it receives frames larger than the 1567 * packet buffer. As a workaround, truncate oversize frames, but 1568 * the register is limited to 9 bits, so if you do frames > 2052 1569 * you better get the MTU right! 1570 */ 1571 thresh = sky2_get_rx_threshold(sky2); 1572 if (thresh > 0x1ff) 1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1574 else { 1575 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1577 } 1578 1579 /* Tell chip about available buffers */ 1580 sky2_rx_update(sky2, rxq); 1581 1582 if (hw->chip_id == CHIP_ID_YUKON_EX || 1583 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1584 /* 1585 * Disable flushing of non ASF packets; 1586 * must be done after initializing the BMUs; 1587 * drivers without ASF support should do this too, otherwise 1588 * it may happen that they cannot run on ASF devices; 1589 * remember that the MAC FIFO isn't reset during initialization. 1590 */ 1591 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1592 } 1593 1594 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1595 /* Enable RX Home Address & Routing Header checksum fix */ 1596 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1597 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1598 1599 /* Enable TX Home Address & Routing Header checksum fix */ 1600 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1601 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1602 } 1603 } 1604 1605 static int sky2_alloc_buffers(struct sky2_port *sky2) 1606 { 1607 struct sky2_hw *hw = sky2->hw; 1608 1609 /* must be power of 2 */ 1610 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1611 sky2->tx_ring_size * 1612 sizeof(struct sky2_tx_le), 1613 &sky2->tx_le_map); 1614 if (!sky2->tx_le) 1615 goto nomem; 1616 1617 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1618 GFP_KERNEL); 1619 if (!sky2->tx_ring) 1620 goto nomem; 1621 1622 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES, 1623 &sky2->rx_le_map); 1624 if (!sky2->rx_le) 1625 goto nomem; 1626 1627 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1628 GFP_KERNEL); 1629 if (!sky2->rx_ring) 1630 goto nomem; 1631 1632 return sky2_alloc_rx_skbs(sky2); 1633 nomem: 1634 return -ENOMEM; 1635 } 1636 1637 static void sky2_free_buffers(struct sky2_port *sky2) 1638 { 1639 struct sky2_hw *hw = sky2->hw; 1640 1641 sky2_rx_clean(sky2); 1642 1643 if (sky2->rx_le) { 1644 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1645 sky2->rx_le, sky2->rx_le_map); 1646 sky2->rx_le = NULL; 1647 } 1648 if (sky2->tx_le) { 1649 pci_free_consistent(hw->pdev, 1650 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1651 sky2->tx_le, sky2->tx_le_map); 1652 sky2->tx_le = NULL; 1653 } 1654 kfree(sky2->tx_ring); 1655 kfree(sky2->rx_ring); 1656 1657 sky2->tx_ring = NULL; 1658 sky2->rx_ring = NULL; 1659 } 1660 1661 static void sky2_hw_up(struct sky2_port *sky2) 1662 { 1663 struct sky2_hw *hw = sky2->hw; 1664 unsigned port = sky2->port; 1665 u32 ramsize; 1666 int cap; 1667 struct net_device *otherdev = hw->dev[sky2->port^1]; 1668 1669 tx_init(sky2); 1670 1671 /* 1672 * On dual port PCI-X card, there is an problem where status 1673 * can be received out of order due to split transactions 1674 */ 1675 if (otherdev && netif_running(otherdev) && 1676 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1677 u16 cmd; 1678 1679 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1680 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1681 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1682 } 1683 1684 sky2_mac_init(hw, port); 1685 1686 /* Register is number of 4K blocks on internal RAM buffer. */ 1687 ramsize = sky2_read8(hw, B2_E_0) * 4; 1688 if (ramsize > 0) { 1689 u32 rxspace; 1690 1691 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1692 if (ramsize < 16) 1693 rxspace = ramsize / 2; 1694 else 1695 rxspace = 8 + (2*(ramsize - 16))/3; 1696 1697 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1698 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1699 1700 /* Make sure SyncQ is disabled */ 1701 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1702 RB_RST_SET); 1703 } 1704 1705 sky2_qset(hw, txqaddr[port]); 1706 1707 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1708 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1709 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1710 1711 /* Set almost empty threshold */ 1712 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1713 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1714 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1715 1716 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1717 sky2->tx_ring_size - 1); 1718 1719 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1720 netdev_update_features(sky2->netdev); 1721 1722 sky2_rx_start(sky2); 1723 } 1724 1725 /* Setup device IRQ and enable napi to process */ 1726 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1727 { 1728 struct pci_dev *pdev = hw->pdev; 1729 int err; 1730 1731 err = request_irq(pdev->irq, sky2_intr, 1732 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1733 name, hw); 1734 if (err) 1735 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1736 else { 1737 hw->flags |= SKY2_HW_IRQ_SETUP; 1738 1739 napi_enable(&hw->napi); 1740 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1741 sky2_read32(hw, B0_IMSK); 1742 } 1743 1744 return err; 1745 } 1746 1747 1748 /* Bring up network interface. */ 1749 static int sky2_open(struct net_device *dev) 1750 { 1751 struct sky2_port *sky2 = netdev_priv(dev); 1752 struct sky2_hw *hw = sky2->hw; 1753 unsigned port = sky2->port; 1754 u32 imask; 1755 int err; 1756 1757 netif_carrier_off(dev); 1758 1759 err = sky2_alloc_buffers(sky2); 1760 if (err) 1761 goto err_out; 1762 1763 /* With single port, IRQ is setup when device is brought up */ 1764 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1765 goto err_out; 1766 1767 sky2_hw_up(sky2); 1768 1769 /* Enable interrupts from phy/mac for port */ 1770 imask = sky2_read32(hw, B0_IMSK); 1771 1772 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1773 hw->chip_id == CHIP_ID_YUKON_PRM || 1774 hw->chip_id == CHIP_ID_YUKON_OP_2) 1775 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1776 1777 imask |= portirq_msk[port]; 1778 sky2_write32(hw, B0_IMSK, imask); 1779 sky2_read32(hw, B0_IMSK); 1780 1781 netif_info(sky2, ifup, dev, "enabling interface\n"); 1782 1783 return 0; 1784 1785 err_out: 1786 sky2_free_buffers(sky2); 1787 return err; 1788 } 1789 1790 /* Modular subtraction in ring */ 1791 static inline int tx_inuse(const struct sky2_port *sky2) 1792 { 1793 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1794 } 1795 1796 /* Number of list elements available for next tx */ 1797 static inline int tx_avail(const struct sky2_port *sky2) 1798 { 1799 return sky2->tx_pending - tx_inuse(sky2); 1800 } 1801 1802 /* Estimate of number of transmit list elements required */ 1803 static unsigned tx_le_req(const struct sk_buff *skb) 1804 { 1805 unsigned count; 1806 1807 count = (skb_shinfo(skb)->nr_frags + 1) 1808 * (sizeof(dma_addr_t) / sizeof(u32)); 1809 1810 if (skb_is_gso(skb)) 1811 ++count; 1812 else if (sizeof(dma_addr_t) == sizeof(u32)) 1813 ++count; /* possible vlan */ 1814 1815 if (skb->ip_summed == CHECKSUM_PARTIAL) 1816 ++count; 1817 1818 return count; 1819 } 1820 1821 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1822 { 1823 if (re->flags & TX_MAP_SINGLE) 1824 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1825 dma_unmap_len(re, maplen), 1826 PCI_DMA_TODEVICE); 1827 else if (re->flags & TX_MAP_PAGE) 1828 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1829 dma_unmap_len(re, maplen), 1830 PCI_DMA_TODEVICE); 1831 re->flags = 0; 1832 } 1833 1834 /* 1835 * Put one packet in ring for transmit. 1836 * A single packet can generate multiple list elements, and 1837 * the number of ring elements will probably be less than the number 1838 * of list elements used. 1839 */ 1840 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1841 struct net_device *dev) 1842 { 1843 struct sky2_port *sky2 = netdev_priv(dev); 1844 struct sky2_hw *hw = sky2->hw; 1845 struct sky2_tx_le *le = NULL; 1846 struct tx_ring_info *re; 1847 unsigned i, len; 1848 dma_addr_t mapping; 1849 u32 upper; 1850 u16 slot; 1851 u16 mss; 1852 u8 ctrl; 1853 1854 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1855 return NETDEV_TX_BUSY; 1856 1857 len = skb_headlen(skb); 1858 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1859 1860 if (pci_dma_mapping_error(hw->pdev, mapping)) 1861 goto mapping_error; 1862 1863 slot = sky2->tx_prod; 1864 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1865 "tx queued, slot %u, len %d\n", slot, skb->len); 1866 1867 /* Send high bits if needed */ 1868 upper = upper_32_bits(mapping); 1869 if (upper != sky2->tx_last_upper) { 1870 le = get_tx_le(sky2, &slot); 1871 le->addr = cpu_to_le32(upper); 1872 sky2->tx_last_upper = upper; 1873 le->opcode = OP_ADDR64 | HW_OWNER; 1874 } 1875 1876 /* Check for TCP Segmentation Offload */ 1877 mss = skb_shinfo(skb)->gso_size; 1878 if (mss != 0) { 1879 1880 if (!(hw->flags & SKY2_HW_NEW_LE)) 1881 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1882 1883 if (mss != sky2->tx_last_mss) { 1884 le = get_tx_le(sky2, &slot); 1885 le->addr = cpu_to_le32(mss); 1886 1887 if (hw->flags & SKY2_HW_NEW_LE) 1888 le->opcode = OP_MSS | HW_OWNER; 1889 else 1890 le->opcode = OP_LRGLEN | HW_OWNER; 1891 sky2->tx_last_mss = mss; 1892 } 1893 } 1894 1895 ctrl = 0; 1896 1897 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1898 if (skb_vlan_tag_present(skb)) { 1899 if (!le) { 1900 le = get_tx_le(sky2, &slot); 1901 le->addr = 0; 1902 le->opcode = OP_VLAN|HW_OWNER; 1903 } else 1904 le->opcode |= OP_VLAN; 1905 le->length = cpu_to_be16(skb_vlan_tag_get(skb)); 1906 ctrl |= INS_VLAN; 1907 } 1908 1909 /* Handle TCP checksum offload */ 1910 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1911 /* On Yukon EX (some versions) encoding change. */ 1912 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1913 ctrl |= CALSUM; /* auto checksum */ 1914 else { 1915 const unsigned offset = skb_transport_offset(skb); 1916 u32 tcpsum; 1917 1918 tcpsum = offset << 16; /* sum start */ 1919 tcpsum |= offset + skb->csum_offset; /* sum write */ 1920 1921 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1922 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1923 ctrl |= UDPTCP; 1924 1925 if (tcpsum != sky2->tx_tcpsum) { 1926 sky2->tx_tcpsum = tcpsum; 1927 1928 le = get_tx_le(sky2, &slot); 1929 le->addr = cpu_to_le32(tcpsum); 1930 le->length = 0; /* initial checksum value */ 1931 le->ctrl = 1; /* one packet */ 1932 le->opcode = OP_TCPLISW | HW_OWNER; 1933 } 1934 } 1935 } 1936 1937 re = sky2->tx_ring + slot; 1938 re->flags = TX_MAP_SINGLE; 1939 dma_unmap_addr_set(re, mapaddr, mapping); 1940 dma_unmap_len_set(re, maplen, len); 1941 1942 le = get_tx_le(sky2, &slot); 1943 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1944 le->length = cpu_to_le16(len); 1945 le->ctrl = ctrl; 1946 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1947 1948 1949 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1950 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1951 1952 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1953 skb_frag_size(frag), DMA_TO_DEVICE); 1954 1955 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1956 goto mapping_unwind; 1957 1958 upper = upper_32_bits(mapping); 1959 if (upper != sky2->tx_last_upper) { 1960 le = get_tx_le(sky2, &slot); 1961 le->addr = cpu_to_le32(upper); 1962 sky2->tx_last_upper = upper; 1963 le->opcode = OP_ADDR64 | HW_OWNER; 1964 } 1965 1966 re = sky2->tx_ring + slot; 1967 re->flags = TX_MAP_PAGE; 1968 dma_unmap_addr_set(re, mapaddr, mapping); 1969 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1970 1971 le = get_tx_le(sky2, &slot); 1972 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1973 le->length = cpu_to_le16(skb_frag_size(frag)); 1974 le->ctrl = ctrl; 1975 le->opcode = OP_BUFFER | HW_OWNER; 1976 } 1977 1978 re->skb = skb; 1979 le->ctrl |= EOP; 1980 1981 sky2->tx_prod = slot; 1982 1983 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1984 netif_stop_queue(dev); 1985 1986 netdev_sent_queue(dev, skb->len); 1987 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1988 1989 return NETDEV_TX_OK; 1990 1991 mapping_unwind: 1992 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1993 re = sky2->tx_ring + i; 1994 1995 sky2_tx_unmap(hw->pdev, re); 1996 } 1997 1998 mapping_error: 1999 if (net_ratelimit()) 2000 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2001 dev_kfree_skb_any(skb); 2002 return NETDEV_TX_OK; 2003 } 2004 2005 /* 2006 * Free ring elements from starting at tx_cons until "done" 2007 * 2008 * NB: 2009 * 1. The hardware will tell us about partial completion of multi-part 2010 * buffers so make sure not to free skb to early. 2011 * 2. This may run in parallel start_xmit because the it only 2012 * looks at the tail of the queue of FIFO (tx_cons), not 2013 * the head (tx_prod) 2014 */ 2015 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2016 { 2017 struct net_device *dev = sky2->netdev; 2018 u16 idx; 2019 unsigned int bytes_compl = 0, pkts_compl = 0; 2020 2021 BUG_ON(done >= sky2->tx_ring_size); 2022 2023 for (idx = sky2->tx_cons; idx != done; 2024 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2025 struct tx_ring_info *re = sky2->tx_ring + idx; 2026 struct sk_buff *skb = re->skb; 2027 2028 sky2_tx_unmap(sky2->hw->pdev, re); 2029 2030 if (skb) { 2031 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2032 "tx done %u\n", idx); 2033 2034 pkts_compl++; 2035 bytes_compl += skb->len; 2036 2037 re->skb = NULL; 2038 dev_kfree_skb_any(skb); 2039 2040 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2041 } 2042 } 2043 2044 sky2->tx_cons = idx; 2045 smp_mb(); 2046 2047 netdev_completed_queue(dev, pkts_compl, bytes_compl); 2048 2049 u64_stats_update_begin(&sky2->tx_stats.syncp); 2050 sky2->tx_stats.packets += pkts_compl; 2051 sky2->tx_stats.bytes += bytes_compl; 2052 u64_stats_update_end(&sky2->tx_stats.syncp); 2053 } 2054 2055 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2056 { 2057 /* Disable Force Sync bit and Enable Alloc bit */ 2058 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2059 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2060 2061 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2062 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2063 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2064 2065 /* Reset the PCI FIFO of the async Tx queue */ 2066 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2067 BMU_RST_SET | BMU_FIFO_RST); 2068 2069 /* Reset the Tx prefetch units */ 2070 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2071 PREF_UNIT_RST_SET); 2072 2073 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2074 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2075 2076 sky2_read32(hw, B0_CTST); 2077 } 2078 2079 static void sky2_hw_down(struct sky2_port *sky2) 2080 { 2081 struct sky2_hw *hw = sky2->hw; 2082 unsigned port = sky2->port; 2083 u16 ctrl; 2084 2085 /* Force flow control off */ 2086 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2087 2088 /* Stop transmitter */ 2089 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2090 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2091 2092 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2093 RB_RST_SET | RB_DIS_OP_MD); 2094 2095 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2096 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2097 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2098 2099 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2100 2101 /* Workaround shared GMAC reset */ 2102 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2103 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2104 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2105 2106 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2107 2108 /* Force any delayed status interrupt and NAPI */ 2109 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2110 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2111 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2112 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2113 2114 sky2_rx_stop(sky2); 2115 2116 spin_lock_bh(&sky2->phy_lock); 2117 sky2_phy_power_down(hw, port); 2118 spin_unlock_bh(&sky2->phy_lock); 2119 2120 sky2_tx_reset(hw, port); 2121 2122 /* Free any pending frames stuck in HW queue */ 2123 sky2_tx_complete(sky2, sky2->tx_prod); 2124 } 2125 2126 /* Network shutdown */ 2127 static int sky2_close(struct net_device *dev) 2128 { 2129 struct sky2_port *sky2 = netdev_priv(dev); 2130 struct sky2_hw *hw = sky2->hw; 2131 2132 /* Never really got started! */ 2133 if (!sky2->tx_le) 2134 return 0; 2135 2136 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2137 2138 if (hw->ports == 1) { 2139 sky2_write32(hw, B0_IMSK, 0); 2140 sky2_read32(hw, B0_IMSK); 2141 2142 napi_disable(&hw->napi); 2143 free_irq(hw->pdev->irq, hw); 2144 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2145 } else { 2146 u32 imask; 2147 2148 /* Disable port IRQ */ 2149 imask = sky2_read32(hw, B0_IMSK); 2150 imask &= ~portirq_msk[sky2->port]; 2151 sky2_write32(hw, B0_IMSK, imask); 2152 sky2_read32(hw, B0_IMSK); 2153 2154 synchronize_irq(hw->pdev->irq); 2155 napi_synchronize(&hw->napi); 2156 } 2157 2158 sky2_hw_down(sky2); 2159 2160 sky2_free_buffers(sky2); 2161 2162 return 0; 2163 } 2164 2165 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2166 { 2167 if (hw->flags & SKY2_HW_FIBRE_PHY) 2168 return SPEED_1000; 2169 2170 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2171 if (aux & PHY_M_PS_SPEED_100) 2172 return SPEED_100; 2173 else 2174 return SPEED_10; 2175 } 2176 2177 switch (aux & PHY_M_PS_SPEED_MSK) { 2178 case PHY_M_PS_SPEED_1000: 2179 return SPEED_1000; 2180 case PHY_M_PS_SPEED_100: 2181 return SPEED_100; 2182 default: 2183 return SPEED_10; 2184 } 2185 } 2186 2187 static void sky2_link_up(struct sky2_port *sky2) 2188 { 2189 struct sky2_hw *hw = sky2->hw; 2190 unsigned port = sky2->port; 2191 static const char *fc_name[] = { 2192 [FC_NONE] = "none", 2193 [FC_TX] = "tx", 2194 [FC_RX] = "rx", 2195 [FC_BOTH] = "both", 2196 }; 2197 2198 sky2_set_ipg(sky2); 2199 2200 sky2_enable_rx_tx(sky2); 2201 2202 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2203 2204 netif_carrier_on(sky2->netdev); 2205 2206 mod_timer(&hw->watchdog_timer, jiffies + 1); 2207 2208 /* Turn on link LED */ 2209 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2210 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2211 2212 netif_info(sky2, link, sky2->netdev, 2213 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2214 sky2->speed, 2215 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2216 fc_name[sky2->flow_status]); 2217 } 2218 2219 static void sky2_link_down(struct sky2_port *sky2) 2220 { 2221 struct sky2_hw *hw = sky2->hw; 2222 unsigned port = sky2->port; 2223 u16 reg; 2224 2225 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2226 2227 reg = gma_read16(hw, port, GM_GP_CTRL); 2228 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2229 gma_write16(hw, port, GM_GP_CTRL, reg); 2230 2231 netif_carrier_off(sky2->netdev); 2232 2233 /* Turn off link LED */ 2234 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2235 2236 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2237 2238 sky2_phy_init(hw, port); 2239 } 2240 2241 static enum flow_control sky2_flow(int rx, int tx) 2242 { 2243 if (rx) 2244 return tx ? FC_BOTH : FC_RX; 2245 else 2246 return tx ? FC_TX : FC_NONE; 2247 } 2248 2249 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2250 { 2251 struct sky2_hw *hw = sky2->hw; 2252 unsigned port = sky2->port; 2253 u16 advert, lpa; 2254 2255 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2256 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2257 if (lpa & PHY_M_AN_RF) { 2258 netdev_err(sky2->netdev, "remote fault\n"); 2259 return -1; 2260 } 2261 2262 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2263 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2264 return -1; 2265 } 2266 2267 sky2->speed = sky2_phy_speed(hw, aux); 2268 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2269 2270 /* Since the pause result bits seem to in different positions on 2271 * different chips. look at registers. 2272 */ 2273 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2274 /* Shift for bits in fiber PHY */ 2275 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2276 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2277 2278 if (advert & ADVERTISE_1000XPAUSE) 2279 advert |= ADVERTISE_PAUSE_CAP; 2280 if (advert & ADVERTISE_1000XPSE_ASYM) 2281 advert |= ADVERTISE_PAUSE_ASYM; 2282 if (lpa & LPA_1000XPAUSE) 2283 lpa |= LPA_PAUSE_CAP; 2284 if (lpa & LPA_1000XPAUSE_ASYM) 2285 lpa |= LPA_PAUSE_ASYM; 2286 } 2287 2288 sky2->flow_status = FC_NONE; 2289 if (advert & ADVERTISE_PAUSE_CAP) { 2290 if (lpa & LPA_PAUSE_CAP) 2291 sky2->flow_status = FC_BOTH; 2292 else if (advert & ADVERTISE_PAUSE_ASYM) 2293 sky2->flow_status = FC_RX; 2294 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2295 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2296 sky2->flow_status = FC_TX; 2297 } 2298 2299 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2300 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2301 sky2->flow_status = FC_NONE; 2302 2303 if (sky2->flow_status & FC_TX) 2304 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2305 else 2306 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2307 2308 return 0; 2309 } 2310 2311 /* Interrupt from PHY */ 2312 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2313 { 2314 struct net_device *dev = hw->dev[port]; 2315 struct sky2_port *sky2 = netdev_priv(dev); 2316 u16 istatus, phystat; 2317 2318 if (!netif_running(dev)) 2319 return; 2320 2321 spin_lock(&sky2->phy_lock); 2322 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2323 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2324 2325 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2326 istatus, phystat); 2327 2328 if (istatus & PHY_M_IS_AN_COMPL) { 2329 if (sky2_autoneg_done(sky2, phystat) == 0 && 2330 !netif_carrier_ok(dev)) 2331 sky2_link_up(sky2); 2332 goto out; 2333 } 2334 2335 if (istatus & PHY_M_IS_LSP_CHANGE) 2336 sky2->speed = sky2_phy_speed(hw, phystat); 2337 2338 if (istatus & PHY_M_IS_DUP_CHANGE) 2339 sky2->duplex = 2340 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2341 2342 if (istatus & PHY_M_IS_LST_CHANGE) { 2343 if (phystat & PHY_M_PS_LINK_UP) 2344 sky2_link_up(sky2); 2345 else 2346 sky2_link_down(sky2); 2347 } 2348 out: 2349 spin_unlock(&sky2->phy_lock); 2350 } 2351 2352 /* Special quick link interrupt (Yukon-2 Optima only) */ 2353 static void sky2_qlink_intr(struct sky2_hw *hw) 2354 { 2355 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2356 u32 imask; 2357 u16 phy; 2358 2359 /* disable irq */ 2360 imask = sky2_read32(hw, B0_IMSK); 2361 imask &= ~Y2_IS_PHY_QLNK; 2362 sky2_write32(hw, B0_IMSK, imask); 2363 2364 /* reset PHY Link Detect */ 2365 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2366 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2367 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2368 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2369 2370 sky2_link_up(sky2); 2371 } 2372 2373 /* Transmit timeout is only called if we are running, carrier is up 2374 * and tx queue is full (stopped). 2375 */ 2376 static void sky2_tx_timeout(struct net_device *dev) 2377 { 2378 struct sky2_port *sky2 = netdev_priv(dev); 2379 struct sky2_hw *hw = sky2->hw; 2380 2381 netif_err(sky2, timer, dev, "tx timeout\n"); 2382 2383 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2384 sky2->tx_cons, sky2->tx_prod, 2385 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2386 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2387 2388 /* can't restart safely under softirq */ 2389 schedule_work(&hw->restart_work); 2390 } 2391 2392 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2393 { 2394 struct sky2_port *sky2 = netdev_priv(dev); 2395 struct sky2_hw *hw = sky2->hw; 2396 unsigned port = sky2->port; 2397 int err; 2398 u16 ctl, mode; 2399 u32 imask; 2400 2401 if (!netif_running(dev)) { 2402 dev->mtu = new_mtu; 2403 netdev_update_features(dev); 2404 return 0; 2405 } 2406 2407 imask = sky2_read32(hw, B0_IMSK); 2408 sky2_write32(hw, B0_IMSK, 0); 2409 sky2_read32(hw, B0_IMSK); 2410 2411 netif_trans_update(dev); /* prevent tx timeout */ 2412 napi_disable(&hw->napi); 2413 netif_tx_disable(dev); 2414 2415 synchronize_irq(hw->pdev->irq); 2416 2417 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2418 sky2_set_tx_stfwd(hw, port); 2419 2420 ctl = gma_read16(hw, port, GM_GP_CTRL); 2421 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2422 sky2_rx_stop(sky2); 2423 sky2_rx_clean(sky2); 2424 2425 dev->mtu = new_mtu; 2426 netdev_update_features(dev); 2427 2428 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2429 if (sky2->speed > SPEED_100) 2430 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2431 else 2432 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2433 2434 if (dev->mtu > ETH_DATA_LEN) 2435 mode |= GM_SMOD_JUMBO_ENA; 2436 2437 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2438 2439 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2440 2441 err = sky2_alloc_rx_skbs(sky2); 2442 if (!err) 2443 sky2_rx_start(sky2); 2444 else 2445 sky2_rx_clean(sky2); 2446 sky2_write32(hw, B0_IMSK, imask); 2447 2448 sky2_read32(hw, B0_Y2_SP_LISR); 2449 napi_enable(&hw->napi); 2450 2451 if (err) 2452 dev_close(dev); 2453 else { 2454 gma_write16(hw, port, GM_GP_CTRL, ctl); 2455 2456 netif_wake_queue(dev); 2457 } 2458 2459 return err; 2460 } 2461 2462 static inline bool needs_copy(const struct rx_ring_info *re, 2463 unsigned length) 2464 { 2465 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2466 /* Some architectures need the IP header to be aligned */ 2467 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) 2468 return true; 2469 #endif 2470 return length < copybreak; 2471 } 2472 2473 /* For small just reuse existing skb for next receive */ 2474 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2475 const struct rx_ring_info *re, 2476 unsigned length) 2477 { 2478 struct sk_buff *skb; 2479 2480 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2481 if (likely(skb)) { 2482 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2483 length, PCI_DMA_FROMDEVICE); 2484 skb_copy_from_linear_data(re->skb, skb->data, length); 2485 skb->ip_summed = re->skb->ip_summed; 2486 skb->csum = re->skb->csum; 2487 skb_copy_hash(skb, re->skb); 2488 skb->vlan_proto = re->skb->vlan_proto; 2489 skb->vlan_tci = re->skb->vlan_tci; 2490 2491 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2492 length, PCI_DMA_FROMDEVICE); 2493 re->skb->vlan_proto = 0; 2494 re->skb->vlan_tci = 0; 2495 skb_clear_hash(re->skb); 2496 re->skb->ip_summed = CHECKSUM_NONE; 2497 skb_put(skb, length); 2498 } 2499 return skb; 2500 } 2501 2502 /* Adjust length of skb with fragments to match received data */ 2503 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2504 unsigned int length) 2505 { 2506 int i, num_frags; 2507 unsigned int size; 2508 2509 /* put header into skb */ 2510 size = min(length, hdr_space); 2511 skb->tail += size; 2512 skb->len += size; 2513 length -= size; 2514 2515 num_frags = skb_shinfo(skb)->nr_frags; 2516 for (i = 0; i < num_frags; i++) { 2517 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2518 2519 if (length == 0) { 2520 /* don't need this page */ 2521 __skb_frag_unref(frag); 2522 --skb_shinfo(skb)->nr_frags; 2523 } else { 2524 size = min(length, (unsigned) PAGE_SIZE); 2525 2526 skb_frag_size_set(frag, size); 2527 skb->data_len += size; 2528 skb->truesize += PAGE_SIZE; 2529 skb->len += size; 2530 length -= size; 2531 } 2532 } 2533 } 2534 2535 /* Normal packet - take skb from ring element and put in a new one */ 2536 static struct sk_buff *receive_new(struct sky2_port *sky2, 2537 struct rx_ring_info *re, 2538 unsigned int length) 2539 { 2540 struct sk_buff *skb; 2541 struct rx_ring_info nre; 2542 unsigned hdr_space = sky2->rx_data_size; 2543 2544 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2545 if (unlikely(!nre.skb)) 2546 goto nobuf; 2547 2548 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2549 goto nomap; 2550 2551 skb = re->skb; 2552 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2553 prefetch(skb->data); 2554 *re = nre; 2555 2556 if (skb_shinfo(skb)->nr_frags) 2557 skb_put_frags(skb, hdr_space, length); 2558 else 2559 skb_put(skb, length); 2560 return skb; 2561 2562 nomap: 2563 dev_kfree_skb(nre.skb); 2564 nobuf: 2565 return NULL; 2566 } 2567 2568 /* 2569 * Receive one packet. 2570 * For larger packets, get new buffer. 2571 */ 2572 static struct sk_buff *sky2_receive(struct net_device *dev, 2573 u16 length, u32 status) 2574 { 2575 struct sky2_port *sky2 = netdev_priv(dev); 2576 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2577 struct sk_buff *skb = NULL; 2578 u16 count = (status & GMR_FS_LEN) >> 16; 2579 2580 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2581 "rx slot %u status 0x%x len %d\n", 2582 sky2->rx_next, status, length); 2583 2584 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2585 prefetch(sky2->rx_ring + sky2->rx_next); 2586 2587 if (skb_vlan_tag_present(re->skb)) 2588 count -= VLAN_HLEN; /* Account for vlan tag */ 2589 2590 /* This chip has hardware problems that generates bogus status. 2591 * So do only marginal checking and expect higher level protocols 2592 * to handle crap frames. 2593 */ 2594 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2595 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2596 length != count) 2597 goto okay; 2598 2599 if (status & GMR_FS_ANY_ERR) 2600 goto error; 2601 2602 if (!(status & GMR_FS_RX_OK)) 2603 goto resubmit; 2604 2605 /* if length reported by DMA does not match PHY, packet was truncated */ 2606 if (length != count) 2607 goto error; 2608 2609 okay: 2610 if (needs_copy(re, length)) 2611 skb = receive_copy(sky2, re, length); 2612 else 2613 skb = receive_new(sky2, re, length); 2614 2615 dev->stats.rx_dropped += (skb == NULL); 2616 2617 resubmit: 2618 sky2_rx_submit(sky2, re); 2619 2620 return skb; 2621 2622 error: 2623 ++dev->stats.rx_errors; 2624 2625 if (net_ratelimit()) 2626 netif_info(sky2, rx_err, dev, 2627 "rx error, status 0x%x length %d\n", status, length); 2628 2629 goto resubmit; 2630 } 2631 2632 /* Transmit complete */ 2633 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2634 { 2635 struct sky2_port *sky2 = netdev_priv(dev); 2636 2637 if (netif_running(dev)) { 2638 sky2_tx_complete(sky2, last); 2639 2640 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2641 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2642 netif_wake_queue(dev); 2643 } 2644 } 2645 2646 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2647 struct sk_buff *skb) 2648 { 2649 if (skb->ip_summed == CHECKSUM_NONE) 2650 netif_receive_skb(skb); 2651 else 2652 napi_gro_receive(&sky2->hw->napi, skb); 2653 } 2654 2655 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2656 unsigned packets, unsigned bytes) 2657 { 2658 struct net_device *dev = hw->dev[port]; 2659 struct sky2_port *sky2 = netdev_priv(dev); 2660 2661 if (packets == 0) 2662 return; 2663 2664 u64_stats_update_begin(&sky2->rx_stats.syncp); 2665 sky2->rx_stats.packets += packets; 2666 sky2->rx_stats.bytes += bytes; 2667 u64_stats_update_end(&sky2->rx_stats.syncp); 2668 2669 sky2->last_rx = jiffies; 2670 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2671 } 2672 2673 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2674 { 2675 /* If this happens then driver assuming wrong format for chip type */ 2676 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2677 2678 /* Both checksum counters are programmed to start at 2679 * the same offset, so unless there is a problem they 2680 * should match. This failure is an early indication that 2681 * hardware receive checksumming won't work. 2682 */ 2683 if (likely((u16)(status >> 16) == (u16)status)) { 2684 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2685 skb->ip_summed = CHECKSUM_COMPLETE; 2686 skb->csum = le16_to_cpu(status); 2687 } else { 2688 dev_notice(&sky2->hw->pdev->dev, 2689 "%s: receive checksum problem (status = %#x)\n", 2690 sky2->netdev->name, status); 2691 2692 /* Disable checksum offload 2693 * It will be reenabled on next ndo_set_features, but if it's 2694 * really broken, will get disabled again 2695 */ 2696 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2697 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2698 BMU_DIS_RX_CHKSUM); 2699 } 2700 } 2701 2702 static void sky2_rx_tag(struct sky2_port *sky2, u16 length) 2703 { 2704 struct sk_buff *skb; 2705 2706 skb = sky2->rx_ring[sky2->rx_next].skb; 2707 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length)); 2708 } 2709 2710 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2711 { 2712 struct sk_buff *skb; 2713 2714 skb = sky2->rx_ring[sky2->rx_next].skb; 2715 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3); 2716 } 2717 2718 /* Process status response ring */ 2719 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2720 { 2721 int work_done = 0; 2722 unsigned int total_bytes[2] = { 0 }; 2723 unsigned int total_packets[2] = { 0 }; 2724 2725 if (to_do <= 0) 2726 return work_done; 2727 2728 rmb(); 2729 do { 2730 struct sky2_port *sky2; 2731 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2732 unsigned port; 2733 struct net_device *dev; 2734 struct sk_buff *skb; 2735 u32 status; 2736 u16 length; 2737 u8 opcode = le->opcode; 2738 2739 if (!(opcode & HW_OWNER)) 2740 break; 2741 2742 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2743 2744 port = le->css & CSS_LINK_BIT; 2745 dev = hw->dev[port]; 2746 sky2 = netdev_priv(dev); 2747 length = le16_to_cpu(le->length); 2748 status = le32_to_cpu(le->status); 2749 2750 le->opcode = 0; 2751 switch (opcode & ~HW_OWNER) { 2752 case OP_RXSTAT: 2753 total_packets[port]++; 2754 total_bytes[port] += length; 2755 2756 skb = sky2_receive(dev, length, status); 2757 if (!skb) 2758 break; 2759 2760 /* This chip reports checksum status differently */ 2761 if (hw->flags & SKY2_HW_NEW_LE) { 2762 if ((dev->features & NETIF_F_RXCSUM) && 2763 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2764 (le->css & CSS_TCPUDPCSOK)) 2765 skb->ip_summed = CHECKSUM_UNNECESSARY; 2766 else 2767 skb->ip_summed = CHECKSUM_NONE; 2768 } 2769 2770 skb->protocol = eth_type_trans(skb, dev); 2771 sky2_skb_rx(sky2, skb); 2772 2773 /* Stop after net poll weight */ 2774 if (++work_done >= to_do) 2775 goto exit_loop; 2776 break; 2777 2778 case OP_RXVLAN: 2779 sky2_rx_tag(sky2, length); 2780 break; 2781 2782 case OP_RXCHKSVLAN: 2783 sky2_rx_tag(sky2, length); 2784 /* fall through */ 2785 case OP_RXCHKS: 2786 if (likely(dev->features & NETIF_F_RXCSUM)) 2787 sky2_rx_checksum(sky2, status); 2788 break; 2789 2790 case OP_RSS_HASH: 2791 sky2_rx_hash(sky2, status); 2792 break; 2793 2794 case OP_TXINDEXLE: 2795 /* TX index reports status for both ports */ 2796 sky2_tx_done(hw->dev[0], status & 0xfff); 2797 if (hw->dev[1]) 2798 sky2_tx_done(hw->dev[1], 2799 ((status >> 24) & 0xff) 2800 | (u16)(length & 0xf) << 8); 2801 break; 2802 2803 default: 2804 if (net_ratelimit()) 2805 pr_warn("unknown status opcode 0x%x\n", opcode); 2806 } 2807 } while (hw->st_idx != idx); 2808 2809 /* Fully processed status ring so clear irq */ 2810 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2811 2812 exit_loop: 2813 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2814 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2815 2816 return work_done; 2817 } 2818 2819 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2820 { 2821 struct net_device *dev = hw->dev[port]; 2822 2823 if (net_ratelimit()) 2824 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2825 2826 if (status & Y2_IS_PAR_RD1) { 2827 if (net_ratelimit()) 2828 netdev_err(dev, "ram data read parity error\n"); 2829 /* Clear IRQ */ 2830 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2831 } 2832 2833 if (status & Y2_IS_PAR_WR1) { 2834 if (net_ratelimit()) 2835 netdev_err(dev, "ram data write parity error\n"); 2836 2837 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2838 } 2839 2840 if (status & Y2_IS_PAR_MAC1) { 2841 if (net_ratelimit()) 2842 netdev_err(dev, "MAC parity error\n"); 2843 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2844 } 2845 2846 if (status & Y2_IS_PAR_RX1) { 2847 if (net_ratelimit()) 2848 netdev_err(dev, "RX parity error\n"); 2849 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2850 } 2851 2852 if (status & Y2_IS_TCP_TXA1) { 2853 if (net_ratelimit()) 2854 netdev_err(dev, "TCP segmentation error\n"); 2855 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2856 } 2857 } 2858 2859 static void sky2_hw_intr(struct sky2_hw *hw) 2860 { 2861 struct pci_dev *pdev = hw->pdev; 2862 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2863 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2864 2865 status &= hwmsk; 2866 2867 if (status & Y2_IS_TIST_OV) 2868 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2869 2870 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2871 u16 pci_err; 2872 2873 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2874 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2875 if (net_ratelimit()) 2876 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2877 pci_err); 2878 2879 sky2_pci_write16(hw, PCI_STATUS, 2880 pci_err | PCI_STATUS_ERROR_BITS); 2881 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2882 } 2883 2884 if (status & Y2_IS_PCI_EXP) { 2885 /* PCI-Express uncorrectable Error occurred */ 2886 u32 err; 2887 2888 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2889 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2890 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2891 0xfffffffful); 2892 if (net_ratelimit()) 2893 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2894 2895 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2896 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2897 } 2898 2899 if (status & Y2_HWE_L1_MASK) 2900 sky2_hw_error(hw, 0, status); 2901 status >>= 8; 2902 if (status & Y2_HWE_L1_MASK) 2903 sky2_hw_error(hw, 1, status); 2904 } 2905 2906 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2907 { 2908 struct net_device *dev = hw->dev[port]; 2909 struct sky2_port *sky2 = netdev_priv(dev); 2910 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2911 2912 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2913 2914 if (status & GM_IS_RX_CO_OV) 2915 gma_read16(hw, port, GM_RX_IRQ_SRC); 2916 2917 if (status & GM_IS_TX_CO_OV) 2918 gma_read16(hw, port, GM_TX_IRQ_SRC); 2919 2920 if (status & GM_IS_RX_FF_OR) { 2921 ++dev->stats.rx_fifo_errors; 2922 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2923 } 2924 2925 if (status & GM_IS_TX_FF_UR) { 2926 ++dev->stats.tx_fifo_errors; 2927 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2928 } 2929 } 2930 2931 /* This should never happen it is a bug. */ 2932 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2933 { 2934 struct net_device *dev = hw->dev[port]; 2935 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2936 2937 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2938 dev->name, (unsigned) q, (unsigned) idx, 2939 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2940 2941 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2942 } 2943 2944 static int sky2_rx_hung(struct net_device *dev) 2945 { 2946 struct sky2_port *sky2 = netdev_priv(dev); 2947 struct sky2_hw *hw = sky2->hw; 2948 unsigned port = sky2->port; 2949 unsigned rxq = rxqaddr[port]; 2950 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2951 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2952 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2953 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2954 2955 /* If idle and MAC or PCI is stuck */ 2956 if (sky2->check.last == sky2->last_rx && 2957 ((mac_rp == sky2->check.mac_rp && 2958 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2959 /* Check if the PCI RX hang */ 2960 (fifo_rp == sky2->check.fifo_rp && 2961 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2962 netdev_printk(KERN_DEBUG, dev, 2963 "hung mac %d:%d fifo %d (%d:%d)\n", 2964 mac_lev, mac_rp, fifo_lev, 2965 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2966 return 1; 2967 } else { 2968 sky2->check.last = sky2->last_rx; 2969 sky2->check.mac_rp = mac_rp; 2970 sky2->check.mac_lev = mac_lev; 2971 sky2->check.fifo_rp = fifo_rp; 2972 sky2->check.fifo_lev = fifo_lev; 2973 return 0; 2974 } 2975 } 2976 2977 static void sky2_watchdog(struct timer_list *t) 2978 { 2979 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer); 2980 2981 /* Check for lost IRQ once a second */ 2982 if (sky2_read32(hw, B0_ISRC)) { 2983 napi_schedule(&hw->napi); 2984 } else { 2985 int i, active = 0; 2986 2987 for (i = 0; i < hw->ports; i++) { 2988 struct net_device *dev = hw->dev[i]; 2989 if (!netif_running(dev)) 2990 continue; 2991 ++active; 2992 2993 /* For chips with Rx FIFO, check if stuck */ 2994 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2995 sky2_rx_hung(dev)) { 2996 netdev_info(dev, "receiver hang detected\n"); 2997 schedule_work(&hw->restart_work); 2998 return; 2999 } 3000 } 3001 3002 if (active == 0) 3003 return; 3004 } 3005 3006 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 3007 } 3008 3009 /* Hardware/software error handling */ 3010 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 3011 { 3012 if (net_ratelimit()) 3013 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 3014 3015 if (status & Y2_IS_HW_ERR) 3016 sky2_hw_intr(hw); 3017 3018 if (status & Y2_IS_IRQ_MAC1) 3019 sky2_mac_intr(hw, 0); 3020 3021 if (status & Y2_IS_IRQ_MAC2) 3022 sky2_mac_intr(hw, 1); 3023 3024 if (status & Y2_IS_CHK_RX1) 3025 sky2_le_error(hw, 0, Q_R1); 3026 3027 if (status & Y2_IS_CHK_RX2) 3028 sky2_le_error(hw, 1, Q_R2); 3029 3030 if (status & Y2_IS_CHK_TXA1) 3031 sky2_le_error(hw, 0, Q_XA1); 3032 3033 if (status & Y2_IS_CHK_TXA2) 3034 sky2_le_error(hw, 1, Q_XA2); 3035 } 3036 3037 static int sky2_poll(struct napi_struct *napi, int work_limit) 3038 { 3039 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3040 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3041 int work_done = 0; 3042 u16 idx; 3043 3044 if (unlikely(status & Y2_IS_ERROR)) 3045 sky2_err_intr(hw, status); 3046 3047 if (status & Y2_IS_IRQ_PHY1) 3048 sky2_phy_intr(hw, 0); 3049 3050 if (status & Y2_IS_IRQ_PHY2) 3051 sky2_phy_intr(hw, 1); 3052 3053 if (status & Y2_IS_PHY_QLNK) 3054 sky2_qlink_intr(hw); 3055 3056 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3057 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3058 3059 if (work_done >= work_limit) 3060 goto done; 3061 } 3062 3063 napi_complete_done(napi, work_done); 3064 sky2_read32(hw, B0_Y2_SP_LISR); 3065 done: 3066 3067 return work_done; 3068 } 3069 3070 static irqreturn_t sky2_intr(int irq, void *dev_id) 3071 { 3072 struct sky2_hw *hw = dev_id; 3073 u32 status; 3074 3075 /* Reading this mask interrupts as side effect */ 3076 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3077 if (status == 0 || status == ~0) { 3078 sky2_write32(hw, B0_Y2_SP_ICR, 2); 3079 return IRQ_NONE; 3080 } 3081 3082 prefetch(&hw->st_le[hw->st_idx]); 3083 3084 napi_schedule(&hw->napi); 3085 3086 return IRQ_HANDLED; 3087 } 3088 3089 #ifdef CONFIG_NET_POLL_CONTROLLER 3090 static void sky2_netpoll(struct net_device *dev) 3091 { 3092 struct sky2_port *sky2 = netdev_priv(dev); 3093 3094 napi_schedule(&sky2->hw->napi); 3095 } 3096 #endif 3097 3098 /* Chip internal frequency for clock calculations */ 3099 static u32 sky2_mhz(const struct sky2_hw *hw) 3100 { 3101 switch (hw->chip_id) { 3102 case CHIP_ID_YUKON_EC: 3103 case CHIP_ID_YUKON_EC_U: 3104 case CHIP_ID_YUKON_EX: 3105 case CHIP_ID_YUKON_SUPR: 3106 case CHIP_ID_YUKON_UL_2: 3107 case CHIP_ID_YUKON_OPT: 3108 case CHIP_ID_YUKON_PRM: 3109 case CHIP_ID_YUKON_OP_2: 3110 return 125; 3111 3112 case CHIP_ID_YUKON_FE: 3113 return 100; 3114 3115 case CHIP_ID_YUKON_FE_P: 3116 return 50; 3117 3118 case CHIP_ID_YUKON_XL: 3119 return 156; 3120 3121 default: 3122 BUG(); 3123 } 3124 } 3125 3126 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3127 { 3128 return sky2_mhz(hw) * us; 3129 } 3130 3131 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3132 { 3133 return clk / sky2_mhz(hw); 3134 } 3135 3136 3137 static int sky2_init(struct sky2_hw *hw) 3138 { 3139 u8 t8; 3140 3141 /* Enable all clocks and check for bad PCI access */ 3142 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3143 3144 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3145 3146 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3147 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3148 3149 switch (hw->chip_id) { 3150 case CHIP_ID_YUKON_XL: 3151 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3152 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3153 hw->flags |= SKY2_HW_RSS_BROKEN; 3154 break; 3155 3156 case CHIP_ID_YUKON_EC_U: 3157 hw->flags = SKY2_HW_GIGABIT 3158 | SKY2_HW_NEWER_PHY 3159 | SKY2_HW_ADV_POWER_CTL; 3160 break; 3161 3162 case CHIP_ID_YUKON_EX: 3163 hw->flags = SKY2_HW_GIGABIT 3164 | SKY2_HW_NEWER_PHY 3165 | SKY2_HW_NEW_LE 3166 | SKY2_HW_ADV_POWER_CTL 3167 | SKY2_HW_RSS_CHKSUM; 3168 3169 /* New transmit checksum */ 3170 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3171 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3172 break; 3173 3174 case CHIP_ID_YUKON_EC: 3175 /* This rev is really old, and requires untested workarounds */ 3176 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3177 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3178 return -EOPNOTSUPP; 3179 } 3180 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3181 break; 3182 3183 case CHIP_ID_YUKON_FE: 3184 hw->flags = SKY2_HW_RSS_BROKEN; 3185 break; 3186 3187 case CHIP_ID_YUKON_FE_P: 3188 hw->flags = SKY2_HW_NEWER_PHY 3189 | SKY2_HW_NEW_LE 3190 | SKY2_HW_AUTO_TX_SUM 3191 | SKY2_HW_ADV_POWER_CTL; 3192 3193 /* The workaround for status conflicts VLAN tag detection. */ 3194 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3195 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3196 break; 3197 3198 case CHIP_ID_YUKON_SUPR: 3199 hw->flags = SKY2_HW_GIGABIT 3200 | SKY2_HW_NEWER_PHY 3201 | SKY2_HW_NEW_LE 3202 | SKY2_HW_AUTO_TX_SUM 3203 | SKY2_HW_ADV_POWER_CTL; 3204 3205 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3206 hw->flags |= SKY2_HW_RSS_CHKSUM; 3207 break; 3208 3209 case CHIP_ID_YUKON_UL_2: 3210 hw->flags = SKY2_HW_GIGABIT 3211 | SKY2_HW_ADV_POWER_CTL; 3212 break; 3213 3214 case CHIP_ID_YUKON_OPT: 3215 case CHIP_ID_YUKON_PRM: 3216 case CHIP_ID_YUKON_OP_2: 3217 hw->flags = SKY2_HW_GIGABIT 3218 | SKY2_HW_NEW_LE 3219 | SKY2_HW_ADV_POWER_CTL; 3220 break; 3221 3222 default: 3223 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3224 hw->chip_id); 3225 return -EOPNOTSUPP; 3226 } 3227 3228 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3229 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3230 hw->flags |= SKY2_HW_FIBRE_PHY; 3231 3232 hw->ports = 1; 3233 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3234 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3235 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3236 ++hw->ports; 3237 } 3238 3239 if (sky2_read8(hw, B2_E_0)) 3240 hw->flags |= SKY2_HW_RAM_BUFFER; 3241 3242 return 0; 3243 } 3244 3245 static void sky2_reset(struct sky2_hw *hw) 3246 { 3247 struct pci_dev *pdev = hw->pdev; 3248 u16 status; 3249 int i; 3250 u32 hwe_mask = Y2_HWE_ALL_MASK; 3251 3252 /* disable ASF */ 3253 if (hw->chip_id == CHIP_ID_YUKON_EX 3254 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3255 sky2_write32(hw, CPU_WDOG, 0); 3256 status = sky2_read16(hw, HCU_CCSR); 3257 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3258 HCU_CCSR_UC_STATE_MSK); 3259 /* 3260 * CPU clock divider shouldn't be used because 3261 * - ASF firmware may malfunction 3262 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3263 */ 3264 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3265 sky2_write16(hw, HCU_CCSR, status); 3266 sky2_write32(hw, CPU_WDOG, 0); 3267 } else 3268 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3269 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3270 3271 /* do a SW reset */ 3272 sky2_write8(hw, B0_CTST, CS_RST_SET); 3273 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3274 3275 /* allow writes to PCI config */ 3276 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3277 3278 /* clear PCI errors, if any */ 3279 status = sky2_pci_read16(hw, PCI_STATUS); 3280 status |= PCI_STATUS_ERROR_BITS; 3281 sky2_pci_write16(hw, PCI_STATUS, status); 3282 3283 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3284 3285 if (pci_is_pcie(pdev)) { 3286 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3287 0xfffffffful); 3288 3289 /* If error bit is stuck on ignore it */ 3290 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3291 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3292 else 3293 hwe_mask |= Y2_IS_PCI_EXP; 3294 } 3295 3296 sky2_power_on(hw); 3297 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3298 3299 for (i = 0; i < hw->ports; i++) { 3300 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3301 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3302 3303 if (hw->chip_id == CHIP_ID_YUKON_EX || 3304 hw->chip_id == CHIP_ID_YUKON_SUPR) 3305 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3306 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3307 | GMC_BYP_RETR_ON); 3308 3309 } 3310 3311 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3312 /* enable MACSec clock gating */ 3313 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3314 } 3315 3316 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3317 hw->chip_id == CHIP_ID_YUKON_PRM || 3318 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3319 u16 reg; 3320 3321 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3322 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3323 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3324 3325 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3326 reg = 10; 3327 3328 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3329 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3330 } else { 3331 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3332 reg = 3; 3333 } 3334 3335 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3336 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3337 3338 /* reset PHY Link Detect */ 3339 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3340 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3341 3342 /* check if PSMv2 was running before */ 3343 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3344 if (reg & PCI_EXP_LNKCTL_ASPMC) 3345 /* restore the PCIe Link Control register */ 3346 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3347 reg); 3348 3349 if (hw->chip_id == CHIP_ID_YUKON_PRM && 3350 hw->chip_rev == CHIP_REV_YU_PRM_A0) { 3351 /* change PHY Interrupt polarity to low active */ 3352 reg = sky2_read16(hw, GPHY_CTRL); 3353 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); 3354 3355 /* adapt HW for low active PHY Interrupt */ 3356 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); 3357 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); 3358 } 3359 3360 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3361 3362 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3363 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3364 } 3365 3366 /* Clear I2C IRQ noise */ 3367 sky2_write32(hw, B2_I2C_IRQ, 1); 3368 3369 /* turn off hardware timer (unused) */ 3370 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3371 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3372 3373 /* Turn off descriptor polling */ 3374 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3375 3376 /* Turn off receive timestamp */ 3377 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3378 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3379 3380 /* enable the Tx Arbiters */ 3381 for (i = 0; i < hw->ports; i++) 3382 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3383 3384 /* Initialize ram interface */ 3385 for (i = 0; i < hw->ports; i++) { 3386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3387 3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3400 } 3401 3402 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3403 3404 for (i = 0; i < hw->ports; i++) 3405 sky2_gmac_reset(hw, i); 3406 3407 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3408 hw->st_idx = 0; 3409 3410 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3411 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3412 3413 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3414 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3415 3416 /* Set the list last index */ 3417 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3418 3419 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3420 sky2_write8(hw, STAT_FIFO_WM, 16); 3421 3422 /* set Status-FIFO ISR watermark */ 3423 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3424 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3425 else 3426 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3427 3428 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3429 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3430 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3431 3432 /* enable status unit */ 3433 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3434 3435 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3436 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3437 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3438 } 3439 3440 /* Take device down (offline). 3441 * Equivalent to doing dev_stop() but this does not 3442 * inform upper layers of the transition. 3443 */ 3444 static void sky2_detach(struct net_device *dev) 3445 { 3446 if (netif_running(dev)) { 3447 netif_tx_lock(dev); 3448 netif_device_detach(dev); /* stop txq */ 3449 netif_tx_unlock(dev); 3450 sky2_close(dev); 3451 } 3452 } 3453 3454 /* Bring device back after doing sky2_detach */ 3455 static int sky2_reattach(struct net_device *dev) 3456 { 3457 int err = 0; 3458 3459 if (netif_running(dev)) { 3460 err = sky2_open(dev); 3461 if (err) { 3462 netdev_info(dev, "could not restart %d\n", err); 3463 dev_close(dev); 3464 } else { 3465 netif_device_attach(dev); 3466 sky2_set_multicast(dev); 3467 } 3468 } 3469 3470 return err; 3471 } 3472 3473 static void sky2_all_down(struct sky2_hw *hw) 3474 { 3475 int i; 3476 3477 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3478 sky2_write32(hw, B0_IMSK, 0); 3479 sky2_read32(hw, B0_IMSK); 3480 3481 synchronize_irq(hw->pdev->irq); 3482 napi_disable(&hw->napi); 3483 } 3484 3485 for (i = 0; i < hw->ports; i++) { 3486 struct net_device *dev = hw->dev[i]; 3487 struct sky2_port *sky2 = netdev_priv(dev); 3488 3489 if (!netif_running(dev)) 3490 continue; 3491 3492 netif_carrier_off(dev); 3493 netif_tx_disable(dev); 3494 sky2_hw_down(sky2); 3495 } 3496 } 3497 3498 static void sky2_all_up(struct sky2_hw *hw) 3499 { 3500 u32 imask = Y2_IS_BASE; 3501 int i; 3502 3503 for (i = 0; i < hw->ports; i++) { 3504 struct net_device *dev = hw->dev[i]; 3505 struct sky2_port *sky2 = netdev_priv(dev); 3506 3507 if (!netif_running(dev)) 3508 continue; 3509 3510 sky2_hw_up(sky2); 3511 sky2_set_multicast(dev); 3512 imask |= portirq_msk[i]; 3513 netif_wake_queue(dev); 3514 } 3515 3516 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3517 sky2_write32(hw, B0_IMSK, imask); 3518 sky2_read32(hw, B0_IMSK); 3519 sky2_read32(hw, B0_Y2_SP_LISR); 3520 napi_enable(&hw->napi); 3521 } 3522 } 3523 3524 static void sky2_restart(struct work_struct *work) 3525 { 3526 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3527 3528 rtnl_lock(); 3529 3530 sky2_all_down(hw); 3531 sky2_reset(hw); 3532 sky2_all_up(hw); 3533 3534 rtnl_unlock(); 3535 } 3536 3537 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3538 { 3539 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3540 } 3541 3542 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3543 { 3544 const struct sky2_port *sky2 = netdev_priv(dev); 3545 3546 wol->supported = sky2_wol_supported(sky2->hw); 3547 wol->wolopts = sky2->wol; 3548 } 3549 3550 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3551 { 3552 struct sky2_port *sky2 = netdev_priv(dev); 3553 struct sky2_hw *hw = sky2->hw; 3554 bool enable_wakeup = false; 3555 int i; 3556 3557 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3558 !device_can_wakeup(&hw->pdev->dev)) 3559 return -EOPNOTSUPP; 3560 3561 sky2->wol = wol->wolopts; 3562 3563 for (i = 0; i < hw->ports; i++) { 3564 struct net_device *dev = hw->dev[i]; 3565 struct sky2_port *sky2 = netdev_priv(dev); 3566 3567 if (sky2->wol) 3568 enable_wakeup = true; 3569 } 3570 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3571 3572 return 0; 3573 } 3574 3575 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3576 { 3577 if (sky2_is_copper(hw)) { 3578 u32 modes = SUPPORTED_10baseT_Half 3579 | SUPPORTED_10baseT_Full 3580 | SUPPORTED_100baseT_Half 3581 | SUPPORTED_100baseT_Full; 3582 3583 if (hw->flags & SKY2_HW_GIGABIT) 3584 modes |= SUPPORTED_1000baseT_Half 3585 | SUPPORTED_1000baseT_Full; 3586 return modes; 3587 } else 3588 return SUPPORTED_1000baseT_Half 3589 | SUPPORTED_1000baseT_Full; 3590 } 3591 3592 static int sky2_get_link_ksettings(struct net_device *dev, 3593 struct ethtool_link_ksettings *cmd) 3594 { 3595 struct sky2_port *sky2 = netdev_priv(dev); 3596 struct sky2_hw *hw = sky2->hw; 3597 u32 supported, advertising; 3598 3599 supported = sky2_supported_modes(hw); 3600 cmd->base.phy_address = PHY_ADDR_MARV; 3601 if (sky2_is_copper(hw)) { 3602 cmd->base.port = PORT_TP; 3603 cmd->base.speed = sky2->speed; 3604 supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3605 } else { 3606 cmd->base.speed = SPEED_1000; 3607 cmd->base.port = PORT_FIBRE; 3608 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3609 } 3610 3611 advertising = sky2->advertising; 3612 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3613 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3614 cmd->base.duplex = sky2->duplex; 3615 3616 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3617 supported); 3618 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3619 advertising); 3620 3621 return 0; 3622 } 3623 3624 static int sky2_set_link_ksettings(struct net_device *dev, 3625 const struct ethtool_link_ksettings *cmd) 3626 { 3627 struct sky2_port *sky2 = netdev_priv(dev); 3628 const struct sky2_hw *hw = sky2->hw; 3629 u32 supported = sky2_supported_modes(hw); 3630 u32 new_advertising; 3631 3632 ethtool_convert_link_mode_to_legacy_u32(&new_advertising, 3633 cmd->link_modes.advertising); 3634 3635 if (cmd->base.autoneg == AUTONEG_ENABLE) { 3636 if (new_advertising & ~supported) 3637 return -EINVAL; 3638 3639 if (sky2_is_copper(hw)) 3640 sky2->advertising = new_advertising | 3641 ADVERTISED_TP | 3642 ADVERTISED_Autoneg; 3643 else 3644 sky2->advertising = new_advertising | 3645 ADVERTISED_FIBRE | 3646 ADVERTISED_Autoneg; 3647 3648 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3649 sky2->duplex = -1; 3650 sky2->speed = -1; 3651 } else { 3652 u32 setting; 3653 u32 speed = cmd->base.speed; 3654 3655 switch (speed) { 3656 case SPEED_1000: 3657 if (cmd->base.duplex == DUPLEX_FULL) 3658 setting = SUPPORTED_1000baseT_Full; 3659 else if (cmd->base.duplex == DUPLEX_HALF) 3660 setting = SUPPORTED_1000baseT_Half; 3661 else 3662 return -EINVAL; 3663 break; 3664 case SPEED_100: 3665 if (cmd->base.duplex == DUPLEX_FULL) 3666 setting = SUPPORTED_100baseT_Full; 3667 else if (cmd->base.duplex == DUPLEX_HALF) 3668 setting = SUPPORTED_100baseT_Half; 3669 else 3670 return -EINVAL; 3671 break; 3672 3673 case SPEED_10: 3674 if (cmd->base.duplex == DUPLEX_FULL) 3675 setting = SUPPORTED_10baseT_Full; 3676 else if (cmd->base.duplex == DUPLEX_HALF) 3677 setting = SUPPORTED_10baseT_Half; 3678 else 3679 return -EINVAL; 3680 break; 3681 default: 3682 return -EINVAL; 3683 } 3684 3685 if ((setting & supported) == 0) 3686 return -EINVAL; 3687 3688 sky2->speed = speed; 3689 sky2->duplex = cmd->base.duplex; 3690 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3691 } 3692 3693 if (netif_running(dev)) { 3694 sky2_phy_reinit(sky2); 3695 sky2_set_multicast(dev); 3696 } 3697 3698 return 0; 3699 } 3700 3701 static void sky2_get_drvinfo(struct net_device *dev, 3702 struct ethtool_drvinfo *info) 3703 { 3704 struct sky2_port *sky2 = netdev_priv(dev); 3705 3706 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 3707 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 3708 strlcpy(info->bus_info, pci_name(sky2->hw->pdev), 3709 sizeof(info->bus_info)); 3710 } 3711 3712 static const struct sky2_stat { 3713 char name[ETH_GSTRING_LEN]; 3714 u16 offset; 3715 } sky2_stats[] = { 3716 { "tx_bytes", GM_TXO_OK_HI }, 3717 { "rx_bytes", GM_RXO_OK_HI }, 3718 { "tx_broadcast", GM_TXF_BC_OK }, 3719 { "rx_broadcast", GM_RXF_BC_OK }, 3720 { "tx_multicast", GM_TXF_MC_OK }, 3721 { "rx_multicast", GM_RXF_MC_OK }, 3722 { "tx_unicast", GM_TXF_UC_OK }, 3723 { "rx_unicast", GM_RXF_UC_OK }, 3724 { "tx_mac_pause", GM_TXF_MPAUSE }, 3725 { "rx_mac_pause", GM_RXF_MPAUSE }, 3726 { "collisions", GM_TXF_COL }, 3727 { "late_collision",GM_TXF_LAT_COL }, 3728 { "aborted", GM_TXF_ABO_COL }, 3729 { "single_collisions", GM_TXF_SNG_COL }, 3730 { "multi_collisions", GM_TXF_MUL_COL }, 3731 3732 { "rx_short", GM_RXF_SHT }, 3733 { "rx_runt", GM_RXE_FRAG }, 3734 { "rx_64_byte_packets", GM_RXF_64B }, 3735 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3736 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3737 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3738 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3739 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3740 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3741 { "rx_too_long", GM_RXF_LNG_ERR }, 3742 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3743 { "rx_jabber", GM_RXF_JAB_PKT }, 3744 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3745 3746 { "tx_64_byte_packets", GM_TXF_64B }, 3747 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3748 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3749 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3750 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3751 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3752 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3753 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3754 }; 3755 3756 static u32 sky2_get_msglevel(struct net_device *netdev) 3757 { 3758 struct sky2_port *sky2 = netdev_priv(netdev); 3759 return sky2->msg_enable; 3760 } 3761 3762 static int sky2_nway_reset(struct net_device *dev) 3763 { 3764 struct sky2_port *sky2 = netdev_priv(dev); 3765 3766 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3767 return -EINVAL; 3768 3769 sky2_phy_reinit(sky2); 3770 sky2_set_multicast(dev); 3771 3772 return 0; 3773 } 3774 3775 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3776 { 3777 struct sky2_hw *hw = sky2->hw; 3778 unsigned port = sky2->port; 3779 int i; 3780 3781 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3782 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3783 3784 for (i = 2; i < count; i++) 3785 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3786 } 3787 3788 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3789 { 3790 struct sky2_port *sky2 = netdev_priv(netdev); 3791 sky2->msg_enable = value; 3792 } 3793 3794 static int sky2_get_sset_count(struct net_device *dev, int sset) 3795 { 3796 switch (sset) { 3797 case ETH_SS_STATS: 3798 return ARRAY_SIZE(sky2_stats); 3799 default: 3800 return -EOPNOTSUPP; 3801 } 3802 } 3803 3804 static void sky2_get_ethtool_stats(struct net_device *dev, 3805 struct ethtool_stats *stats, u64 * data) 3806 { 3807 struct sky2_port *sky2 = netdev_priv(dev); 3808 3809 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3810 } 3811 3812 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3813 { 3814 int i; 3815 3816 switch (stringset) { 3817 case ETH_SS_STATS: 3818 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3819 memcpy(data + i * ETH_GSTRING_LEN, 3820 sky2_stats[i].name, ETH_GSTRING_LEN); 3821 break; 3822 } 3823 } 3824 3825 static int sky2_set_mac_address(struct net_device *dev, void *p) 3826 { 3827 struct sky2_port *sky2 = netdev_priv(dev); 3828 struct sky2_hw *hw = sky2->hw; 3829 unsigned port = sky2->port; 3830 const struct sockaddr *addr = p; 3831 3832 if (!is_valid_ether_addr(addr->sa_data)) 3833 return -EADDRNOTAVAIL; 3834 3835 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3836 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3837 dev->dev_addr, ETH_ALEN); 3838 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3839 dev->dev_addr, ETH_ALEN); 3840 3841 /* virtual address for data */ 3842 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3843 3844 /* physical address: used for pause frames */ 3845 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3846 3847 return 0; 3848 } 3849 3850 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3851 { 3852 u32 bit; 3853 3854 bit = ether_crc(ETH_ALEN, addr) & 63; 3855 filter[bit >> 3] |= 1 << (bit & 7); 3856 } 3857 3858 static void sky2_set_multicast(struct net_device *dev) 3859 { 3860 struct sky2_port *sky2 = netdev_priv(dev); 3861 struct sky2_hw *hw = sky2->hw; 3862 unsigned port = sky2->port; 3863 struct netdev_hw_addr *ha; 3864 u16 reg; 3865 u8 filter[8]; 3866 int rx_pause; 3867 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3868 3869 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3870 memset(filter, 0, sizeof(filter)); 3871 3872 reg = gma_read16(hw, port, GM_RX_CTRL); 3873 reg |= GM_RXCR_UCF_ENA; 3874 3875 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3876 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3877 else if (dev->flags & IFF_ALLMULTI) 3878 memset(filter, 0xff, sizeof(filter)); 3879 else if (netdev_mc_empty(dev) && !rx_pause) 3880 reg &= ~GM_RXCR_MCF_ENA; 3881 else { 3882 reg |= GM_RXCR_MCF_ENA; 3883 3884 if (rx_pause) 3885 sky2_add_filter(filter, pause_mc_addr); 3886 3887 netdev_for_each_mc_addr(ha, dev) 3888 sky2_add_filter(filter, ha->addr); 3889 } 3890 3891 gma_write16(hw, port, GM_MC_ADDR_H1, 3892 (u16) filter[0] | ((u16) filter[1] << 8)); 3893 gma_write16(hw, port, GM_MC_ADDR_H2, 3894 (u16) filter[2] | ((u16) filter[3] << 8)); 3895 gma_write16(hw, port, GM_MC_ADDR_H3, 3896 (u16) filter[4] | ((u16) filter[5] << 8)); 3897 gma_write16(hw, port, GM_MC_ADDR_H4, 3898 (u16) filter[6] | ((u16) filter[7] << 8)); 3899 3900 gma_write16(hw, port, GM_RX_CTRL, reg); 3901 } 3902 3903 static void sky2_get_stats(struct net_device *dev, 3904 struct rtnl_link_stats64 *stats) 3905 { 3906 struct sky2_port *sky2 = netdev_priv(dev); 3907 struct sky2_hw *hw = sky2->hw; 3908 unsigned port = sky2->port; 3909 unsigned int start; 3910 u64 _bytes, _packets; 3911 3912 do { 3913 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp); 3914 _bytes = sky2->rx_stats.bytes; 3915 _packets = sky2->rx_stats.packets; 3916 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start)); 3917 3918 stats->rx_packets = _packets; 3919 stats->rx_bytes = _bytes; 3920 3921 do { 3922 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp); 3923 _bytes = sky2->tx_stats.bytes; 3924 _packets = sky2->tx_stats.packets; 3925 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start)); 3926 3927 stats->tx_packets = _packets; 3928 stats->tx_bytes = _bytes; 3929 3930 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3931 + get_stats32(hw, port, GM_RXF_BC_OK); 3932 3933 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3934 3935 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3936 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3937 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3938 + get_stats32(hw, port, GM_RXE_FRAG); 3939 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3940 3941 stats->rx_dropped = dev->stats.rx_dropped; 3942 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3943 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3944 } 3945 3946 /* Can have one global because blinking is controlled by 3947 * ethtool and that is always under RTNL mutex 3948 */ 3949 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3950 { 3951 struct sky2_hw *hw = sky2->hw; 3952 unsigned port = sky2->port; 3953 3954 spin_lock_bh(&sky2->phy_lock); 3955 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3956 hw->chip_id == CHIP_ID_YUKON_EX || 3957 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3958 u16 pg; 3959 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3960 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3961 3962 switch (mode) { 3963 case MO_LED_OFF: 3964 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3965 PHY_M_LEDC_LOS_CTRL(8) | 3966 PHY_M_LEDC_INIT_CTRL(8) | 3967 PHY_M_LEDC_STA1_CTRL(8) | 3968 PHY_M_LEDC_STA0_CTRL(8)); 3969 break; 3970 case MO_LED_ON: 3971 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3972 PHY_M_LEDC_LOS_CTRL(9) | 3973 PHY_M_LEDC_INIT_CTRL(9) | 3974 PHY_M_LEDC_STA1_CTRL(9) | 3975 PHY_M_LEDC_STA0_CTRL(9)); 3976 break; 3977 case MO_LED_BLINK: 3978 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3979 PHY_M_LEDC_LOS_CTRL(0xa) | 3980 PHY_M_LEDC_INIT_CTRL(0xa) | 3981 PHY_M_LEDC_STA1_CTRL(0xa) | 3982 PHY_M_LEDC_STA0_CTRL(0xa)); 3983 break; 3984 case MO_LED_NORM: 3985 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3986 PHY_M_LEDC_LOS_CTRL(1) | 3987 PHY_M_LEDC_INIT_CTRL(8) | 3988 PHY_M_LEDC_STA1_CTRL(7) | 3989 PHY_M_LEDC_STA0_CTRL(7)); 3990 } 3991 3992 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3993 } else 3994 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3995 PHY_M_LED_MO_DUP(mode) | 3996 PHY_M_LED_MO_10(mode) | 3997 PHY_M_LED_MO_100(mode) | 3998 PHY_M_LED_MO_1000(mode) | 3999 PHY_M_LED_MO_RX(mode) | 4000 PHY_M_LED_MO_TX(mode)); 4001 4002 spin_unlock_bh(&sky2->phy_lock); 4003 } 4004 4005 /* blink LED's for finding board */ 4006 static int sky2_set_phys_id(struct net_device *dev, 4007 enum ethtool_phys_id_state state) 4008 { 4009 struct sky2_port *sky2 = netdev_priv(dev); 4010 4011 switch (state) { 4012 case ETHTOOL_ID_ACTIVE: 4013 return 1; /* cycle on/off once per second */ 4014 case ETHTOOL_ID_INACTIVE: 4015 sky2_led(sky2, MO_LED_NORM); 4016 break; 4017 case ETHTOOL_ID_ON: 4018 sky2_led(sky2, MO_LED_ON); 4019 break; 4020 case ETHTOOL_ID_OFF: 4021 sky2_led(sky2, MO_LED_OFF); 4022 break; 4023 } 4024 4025 return 0; 4026 } 4027 4028 static void sky2_get_pauseparam(struct net_device *dev, 4029 struct ethtool_pauseparam *ecmd) 4030 { 4031 struct sky2_port *sky2 = netdev_priv(dev); 4032 4033 switch (sky2->flow_mode) { 4034 case FC_NONE: 4035 ecmd->tx_pause = ecmd->rx_pause = 0; 4036 break; 4037 case FC_TX: 4038 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 4039 break; 4040 case FC_RX: 4041 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 4042 break; 4043 case FC_BOTH: 4044 ecmd->tx_pause = ecmd->rx_pause = 1; 4045 } 4046 4047 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 4048 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 4049 } 4050 4051 static int sky2_set_pauseparam(struct net_device *dev, 4052 struct ethtool_pauseparam *ecmd) 4053 { 4054 struct sky2_port *sky2 = netdev_priv(dev); 4055 4056 if (ecmd->autoneg == AUTONEG_ENABLE) 4057 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4058 else 4059 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4060 4061 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4062 4063 if (netif_running(dev)) 4064 sky2_phy_reinit(sky2); 4065 4066 return 0; 4067 } 4068 4069 static int sky2_get_coalesce(struct net_device *dev, 4070 struct ethtool_coalesce *ecmd) 4071 { 4072 struct sky2_port *sky2 = netdev_priv(dev); 4073 struct sky2_hw *hw = sky2->hw; 4074 4075 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4076 ecmd->tx_coalesce_usecs = 0; 4077 else { 4078 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4079 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4080 } 4081 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4082 4083 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4084 ecmd->rx_coalesce_usecs = 0; 4085 else { 4086 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4087 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4088 } 4089 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4090 4091 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4092 ecmd->rx_coalesce_usecs_irq = 0; 4093 else { 4094 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4095 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4096 } 4097 4098 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4099 4100 return 0; 4101 } 4102 4103 /* Note: this affect both ports */ 4104 static int sky2_set_coalesce(struct net_device *dev, 4105 struct ethtool_coalesce *ecmd) 4106 { 4107 struct sky2_port *sky2 = netdev_priv(dev); 4108 struct sky2_hw *hw = sky2->hw; 4109 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4110 4111 if (ecmd->tx_coalesce_usecs > tmax || 4112 ecmd->rx_coalesce_usecs > tmax || 4113 ecmd->rx_coalesce_usecs_irq > tmax) 4114 return -EINVAL; 4115 4116 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4117 return -EINVAL; 4118 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4119 return -EINVAL; 4120 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4121 return -EINVAL; 4122 4123 if (ecmd->tx_coalesce_usecs == 0) 4124 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4125 else { 4126 sky2_write32(hw, STAT_TX_TIMER_INI, 4127 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4128 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4129 } 4130 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4131 4132 if (ecmd->rx_coalesce_usecs == 0) 4133 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4134 else { 4135 sky2_write32(hw, STAT_LEV_TIMER_INI, 4136 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4137 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4138 } 4139 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4140 4141 if (ecmd->rx_coalesce_usecs_irq == 0) 4142 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4143 else { 4144 sky2_write32(hw, STAT_ISR_TIMER_INI, 4145 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4146 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4147 } 4148 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4149 return 0; 4150 } 4151 4152 /* 4153 * Hardware is limited to min of 128 and max of 2048 for ring size 4154 * and rounded up to next power of two 4155 * to avoid division in modulus calclation 4156 */ 4157 static unsigned long roundup_ring_size(unsigned long pending) 4158 { 4159 return max(128ul, roundup_pow_of_two(pending+1)); 4160 } 4161 4162 static void sky2_get_ringparam(struct net_device *dev, 4163 struct ethtool_ringparam *ering) 4164 { 4165 struct sky2_port *sky2 = netdev_priv(dev); 4166 4167 ering->rx_max_pending = RX_MAX_PENDING; 4168 ering->tx_max_pending = TX_MAX_PENDING; 4169 4170 ering->rx_pending = sky2->rx_pending; 4171 ering->tx_pending = sky2->tx_pending; 4172 } 4173 4174 static int sky2_set_ringparam(struct net_device *dev, 4175 struct ethtool_ringparam *ering) 4176 { 4177 struct sky2_port *sky2 = netdev_priv(dev); 4178 4179 if (ering->rx_pending > RX_MAX_PENDING || 4180 ering->rx_pending < 8 || 4181 ering->tx_pending < TX_MIN_PENDING || 4182 ering->tx_pending > TX_MAX_PENDING) 4183 return -EINVAL; 4184 4185 sky2_detach(dev); 4186 4187 sky2->rx_pending = ering->rx_pending; 4188 sky2->tx_pending = ering->tx_pending; 4189 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4190 4191 return sky2_reattach(dev); 4192 } 4193 4194 static int sky2_get_regs_len(struct net_device *dev) 4195 { 4196 return 0x4000; 4197 } 4198 4199 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4200 { 4201 /* This complicated switch statement is to make sure and 4202 * only access regions that are unreserved. 4203 * Some blocks are only valid on dual port cards. 4204 */ 4205 switch (b) { 4206 /* second port */ 4207 case 5: /* Tx Arbiter 2 */ 4208 case 9: /* RX2 */ 4209 case 14 ... 15: /* TX2 */ 4210 case 17: case 19: /* Ram Buffer 2 */ 4211 case 22 ... 23: /* Tx Ram Buffer 2 */ 4212 case 25: /* Rx MAC Fifo 1 */ 4213 case 27: /* Tx MAC Fifo 2 */ 4214 case 31: /* GPHY 2 */ 4215 case 40 ... 47: /* Pattern Ram 2 */ 4216 case 52: case 54: /* TCP Segmentation 2 */ 4217 case 112 ... 116: /* GMAC 2 */ 4218 return hw->ports > 1; 4219 4220 case 0: /* Control */ 4221 case 2: /* Mac address */ 4222 case 4: /* Tx Arbiter 1 */ 4223 case 7: /* PCI express reg */ 4224 case 8: /* RX1 */ 4225 case 12 ... 13: /* TX1 */ 4226 case 16: case 18:/* Rx Ram Buffer 1 */ 4227 case 20 ... 21: /* Tx Ram Buffer 1 */ 4228 case 24: /* Rx MAC Fifo 1 */ 4229 case 26: /* Tx MAC Fifo 1 */ 4230 case 28 ... 29: /* Descriptor and status unit */ 4231 case 30: /* GPHY 1*/ 4232 case 32 ... 39: /* Pattern Ram 1 */ 4233 case 48: case 50: /* TCP Segmentation 1 */ 4234 case 56 ... 60: /* PCI space */ 4235 case 80 ... 84: /* GMAC 1 */ 4236 return 1; 4237 4238 default: 4239 return 0; 4240 } 4241 } 4242 4243 /* 4244 * Returns copy of control register region 4245 * Note: ethtool_get_regs always provides full size (16k) buffer 4246 */ 4247 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4248 void *p) 4249 { 4250 const struct sky2_port *sky2 = netdev_priv(dev); 4251 const void __iomem *io = sky2->hw->regs; 4252 unsigned int b; 4253 4254 regs->version = 1; 4255 4256 for (b = 0; b < 128; b++) { 4257 /* skip poisonous diagnostic ram region in block 3 */ 4258 if (b == 3) 4259 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4260 else if (sky2_reg_access_ok(sky2->hw, b)) 4261 memcpy_fromio(p, io, 128); 4262 else 4263 memset(p, 0, 128); 4264 4265 p += 128; 4266 io += 128; 4267 } 4268 } 4269 4270 static int sky2_get_eeprom_len(struct net_device *dev) 4271 { 4272 struct sky2_port *sky2 = netdev_priv(dev); 4273 struct sky2_hw *hw = sky2->hw; 4274 u16 reg2; 4275 4276 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4277 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4278 } 4279 4280 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4281 { 4282 unsigned long start = jiffies; 4283 4284 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4285 /* Can take up to 10.6 ms for write */ 4286 if (time_after(jiffies, start + HZ/4)) { 4287 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4288 return -ETIMEDOUT; 4289 } 4290 mdelay(1); 4291 } 4292 4293 return 0; 4294 } 4295 4296 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4297 u16 offset, size_t length) 4298 { 4299 int rc = 0; 4300 4301 while (length > 0) { 4302 u32 val; 4303 4304 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4305 rc = sky2_vpd_wait(hw, cap, 0); 4306 if (rc) 4307 break; 4308 4309 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4310 4311 memcpy(data, &val, min(sizeof(val), length)); 4312 offset += sizeof(u32); 4313 data += sizeof(u32); 4314 length -= sizeof(u32); 4315 } 4316 4317 return rc; 4318 } 4319 4320 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4321 u16 offset, unsigned int length) 4322 { 4323 unsigned int i; 4324 int rc = 0; 4325 4326 for (i = 0; i < length; i += sizeof(u32)) { 4327 u32 val = *(u32 *)(data + i); 4328 4329 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4330 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4331 4332 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4333 if (rc) 4334 break; 4335 } 4336 return rc; 4337 } 4338 4339 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4340 u8 *data) 4341 { 4342 struct sky2_port *sky2 = netdev_priv(dev); 4343 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4344 4345 if (!cap) 4346 return -EINVAL; 4347 4348 eeprom->magic = SKY2_EEPROM_MAGIC; 4349 4350 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4351 } 4352 4353 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4354 u8 *data) 4355 { 4356 struct sky2_port *sky2 = netdev_priv(dev); 4357 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4358 4359 if (!cap) 4360 return -EINVAL; 4361 4362 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4363 return -EINVAL; 4364 4365 /* Partial writes not supported */ 4366 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4367 return -EINVAL; 4368 4369 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4370 } 4371 4372 static netdev_features_t sky2_fix_features(struct net_device *dev, 4373 netdev_features_t features) 4374 { 4375 const struct sky2_port *sky2 = netdev_priv(dev); 4376 const struct sky2_hw *hw = sky2->hw; 4377 4378 /* In order to do Jumbo packets on these chips, need to turn off the 4379 * transmit store/forward. Therefore checksum offload won't work. 4380 */ 4381 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4382 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4383 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK); 4384 } 4385 4386 /* Some hardware requires receive checksum for RSS to work. */ 4387 if ( (features & NETIF_F_RXHASH) && 4388 !(features & NETIF_F_RXCSUM) && 4389 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4390 netdev_info(dev, "receive hashing forces receive checksum\n"); 4391 features |= NETIF_F_RXCSUM; 4392 } 4393 4394 return features; 4395 } 4396 4397 static int sky2_set_features(struct net_device *dev, netdev_features_t features) 4398 { 4399 struct sky2_port *sky2 = netdev_priv(dev); 4400 netdev_features_t changed = dev->features ^ features; 4401 4402 if ((changed & NETIF_F_RXCSUM) && 4403 !(sky2->hw->flags & SKY2_HW_NEW_LE)) { 4404 sky2_write32(sky2->hw, 4405 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4406 (features & NETIF_F_RXCSUM) 4407 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4408 } 4409 4410 if (changed & NETIF_F_RXHASH) 4411 rx_set_rss(dev, features); 4412 4413 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) 4414 sky2_vlan_mode(dev, features); 4415 4416 return 0; 4417 } 4418 4419 static const struct ethtool_ops sky2_ethtool_ops = { 4420 .get_drvinfo = sky2_get_drvinfo, 4421 .get_wol = sky2_get_wol, 4422 .set_wol = sky2_set_wol, 4423 .get_msglevel = sky2_get_msglevel, 4424 .set_msglevel = sky2_set_msglevel, 4425 .nway_reset = sky2_nway_reset, 4426 .get_regs_len = sky2_get_regs_len, 4427 .get_regs = sky2_get_regs, 4428 .get_link = ethtool_op_get_link, 4429 .get_eeprom_len = sky2_get_eeprom_len, 4430 .get_eeprom = sky2_get_eeprom, 4431 .set_eeprom = sky2_set_eeprom, 4432 .get_strings = sky2_get_strings, 4433 .get_coalesce = sky2_get_coalesce, 4434 .set_coalesce = sky2_set_coalesce, 4435 .get_ringparam = sky2_get_ringparam, 4436 .set_ringparam = sky2_set_ringparam, 4437 .get_pauseparam = sky2_get_pauseparam, 4438 .set_pauseparam = sky2_set_pauseparam, 4439 .set_phys_id = sky2_set_phys_id, 4440 .get_sset_count = sky2_get_sset_count, 4441 .get_ethtool_stats = sky2_get_ethtool_stats, 4442 .get_link_ksettings = sky2_get_link_ksettings, 4443 .set_link_ksettings = sky2_set_link_ksettings, 4444 }; 4445 4446 #ifdef CONFIG_SKY2_DEBUG 4447 4448 static struct dentry *sky2_debug; 4449 4450 4451 /* 4452 * Read and parse the first part of Vital Product Data 4453 */ 4454 #define VPD_SIZE 128 4455 #define VPD_MAGIC 0x82 4456 4457 static const struct vpd_tag { 4458 char tag[2]; 4459 char *label; 4460 } vpd_tags[] = { 4461 { "PN", "Part Number" }, 4462 { "EC", "Engineering Level" }, 4463 { "MN", "Manufacturer" }, 4464 { "SN", "Serial Number" }, 4465 { "YA", "Asset Tag" }, 4466 { "VL", "First Error Log Message" }, 4467 { "VF", "Second Error Log Message" }, 4468 { "VB", "Boot Agent ROM Configuration" }, 4469 { "VE", "EFI UNDI Configuration" }, 4470 }; 4471 4472 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4473 { 4474 size_t vpd_size; 4475 loff_t offs; 4476 u8 len; 4477 unsigned char *buf; 4478 u16 reg2; 4479 4480 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4481 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4482 4483 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4484 buf = kmalloc(vpd_size, GFP_KERNEL); 4485 if (!buf) { 4486 seq_puts(seq, "no memory!\n"); 4487 return; 4488 } 4489 4490 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4491 seq_puts(seq, "VPD read failed\n"); 4492 goto out; 4493 } 4494 4495 if (buf[0] != VPD_MAGIC) { 4496 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4497 goto out; 4498 } 4499 len = buf[1]; 4500 if (len == 0 || len > vpd_size - 4) { 4501 seq_printf(seq, "Invalid id length: %d\n", len); 4502 goto out; 4503 } 4504 4505 seq_printf(seq, "%.*s\n", len, buf + 3); 4506 offs = len + 3; 4507 4508 while (offs < vpd_size - 4) { 4509 int i; 4510 4511 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4512 break; 4513 len = buf[offs + 2]; 4514 if (offs + len + 3 >= vpd_size) 4515 break; 4516 4517 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4518 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4519 seq_printf(seq, " %s: %.*s\n", 4520 vpd_tags[i].label, len, buf + offs + 3); 4521 break; 4522 } 4523 } 4524 offs += len + 3; 4525 } 4526 out: 4527 kfree(buf); 4528 } 4529 4530 static int sky2_debug_show(struct seq_file *seq, void *v) 4531 { 4532 struct net_device *dev = seq->private; 4533 const struct sky2_port *sky2 = netdev_priv(dev); 4534 struct sky2_hw *hw = sky2->hw; 4535 unsigned port = sky2->port; 4536 unsigned idx, last; 4537 int sop; 4538 4539 sky2_show_vpd(seq, hw); 4540 4541 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4542 sky2_read32(hw, B0_ISRC), 4543 sky2_read32(hw, B0_IMSK), 4544 sky2_read32(hw, B0_Y2_SP_ICR)); 4545 4546 if (!netif_running(dev)) { 4547 seq_puts(seq, "network not running\n"); 4548 return 0; 4549 } 4550 4551 napi_disable(&hw->napi); 4552 last = sky2_read16(hw, STAT_PUT_IDX); 4553 4554 seq_printf(seq, "Status ring %u\n", hw->st_size); 4555 if (hw->st_idx == last) 4556 seq_puts(seq, "Status ring (empty)\n"); 4557 else { 4558 seq_puts(seq, "Status ring\n"); 4559 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4560 idx = RING_NEXT(idx, hw->st_size)) { 4561 const struct sky2_status_le *le = hw->st_le + idx; 4562 seq_printf(seq, "[%d] %#x %d %#x\n", 4563 idx, le->opcode, le->length, le->status); 4564 } 4565 seq_puts(seq, "\n"); 4566 } 4567 4568 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4569 sky2->tx_cons, sky2->tx_prod, 4570 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4571 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4572 4573 /* Dump contents of tx ring */ 4574 sop = 1; 4575 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4576 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4577 const struct sky2_tx_le *le = sky2->tx_le + idx; 4578 u32 a = le32_to_cpu(le->addr); 4579 4580 if (sop) 4581 seq_printf(seq, "%u:", idx); 4582 sop = 0; 4583 4584 switch (le->opcode & ~HW_OWNER) { 4585 case OP_ADDR64: 4586 seq_printf(seq, " %#x:", a); 4587 break; 4588 case OP_LRGLEN: 4589 seq_printf(seq, " mtu=%d", a); 4590 break; 4591 case OP_VLAN: 4592 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4593 break; 4594 case OP_TCPLISW: 4595 seq_printf(seq, " csum=%#x", a); 4596 break; 4597 case OP_LARGESEND: 4598 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4599 break; 4600 case OP_PACKET: 4601 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4602 break; 4603 case OP_BUFFER: 4604 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4605 break; 4606 default: 4607 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4608 a, le16_to_cpu(le->length)); 4609 } 4610 4611 if (le->ctrl & EOP) { 4612 seq_putc(seq, '\n'); 4613 sop = 1; 4614 } 4615 } 4616 4617 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4618 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4619 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4620 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4621 4622 sky2_read32(hw, B0_Y2_SP_LISR); 4623 napi_enable(&hw->napi); 4624 return 0; 4625 } 4626 4627 static int sky2_debug_open(struct inode *inode, struct file *file) 4628 { 4629 return single_open(file, sky2_debug_show, inode->i_private); 4630 } 4631 4632 static const struct file_operations sky2_debug_fops = { 4633 .owner = THIS_MODULE, 4634 .open = sky2_debug_open, 4635 .read = seq_read, 4636 .llseek = seq_lseek, 4637 .release = single_release, 4638 }; 4639 4640 /* 4641 * Use network device events to create/remove/rename 4642 * debugfs file entries 4643 */ 4644 static int sky2_device_event(struct notifier_block *unused, 4645 unsigned long event, void *ptr) 4646 { 4647 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4648 struct sky2_port *sky2 = netdev_priv(dev); 4649 4650 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4651 return NOTIFY_DONE; 4652 4653 switch (event) { 4654 case NETDEV_CHANGENAME: 4655 if (sky2->debugfs) { 4656 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4657 sky2_debug, dev->name); 4658 } 4659 break; 4660 4661 case NETDEV_GOING_DOWN: 4662 if (sky2->debugfs) { 4663 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4664 debugfs_remove(sky2->debugfs); 4665 sky2->debugfs = NULL; 4666 } 4667 break; 4668 4669 case NETDEV_UP: 4670 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4671 sky2_debug, dev, 4672 &sky2_debug_fops); 4673 if (IS_ERR(sky2->debugfs)) 4674 sky2->debugfs = NULL; 4675 } 4676 4677 return NOTIFY_DONE; 4678 } 4679 4680 static struct notifier_block sky2_notifier = { 4681 .notifier_call = sky2_device_event, 4682 }; 4683 4684 4685 static __init void sky2_debug_init(void) 4686 { 4687 struct dentry *ent; 4688 4689 ent = debugfs_create_dir("sky2", NULL); 4690 if (!ent || IS_ERR(ent)) 4691 return; 4692 4693 sky2_debug = ent; 4694 register_netdevice_notifier(&sky2_notifier); 4695 } 4696 4697 static __exit void sky2_debug_cleanup(void) 4698 { 4699 if (sky2_debug) { 4700 unregister_netdevice_notifier(&sky2_notifier); 4701 debugfs_remove(sky2_debug); 4702 sky2_debug = NULL; 4703 } 4704 } 4705 4706 #else 4707 #define sky2_debug_init() 4708 #define sky2_debug_cleanup() 4709 #endif 4710 4711 /* Two copies of network device operations to handle special case of 4712 not allowing netpoll on second port */ 4713 static const struct net_device_ops sky2_netdev_ops[2] = { 4714 { 4715 .ndo_open = sky2_open, 4716 .ndo_stop = sky2_close, 4717 .ndo_start_xmit = sky2_xmit_frame, 4718 .ndo_do_ioctl = sky2_ioctl, 4719 .ndo_validate_addr = eth_validate_addr, 4720 .ndo_set_mac_address = sky2_set_mac_address, 4721 .ndo_set_rx_mode = sky2_set_multicast, 4722 .ndo_change_mtu = sky2_change_mtu, 4723 .ndo_fix_features = sky2_fix_features, 4724 .ndo_set_features = sky2_set_features, 4725 .ndo_tx_timeout = sky2_tx_timeout, 4726 .ndo_get_stats64 = sky2_get_stats, 4727 #ifdef CONFIG_NET_POLL_CONTROLLER 4728 .ndo_poll_controller = sky2_netpoll, 4729 #endif 4730 }, 4731 { 4732 .ndo_open = sky2_open, 4733 .ndo_stop = sky2_close, 4734 .ndo_start_xmit = sky2_xmit_frame, 4735 .ndo_do_ioctl = sky2_ioctl, 4736 .ndo_validate_addr = eth_validate_addr, 4737 .ndo_set_mac_address = sky2_set_mac_address, 4738 .ndo_set_rx_mode = sky2_set_multicast, 4739 .ndo_change_mtu = sky2_change_mtu, 4740 .ndo_fix_features = sky2_fix_features, 4741 .ndo_set_features = sky2_set_features, 4742 .ndo_tx_timeout = sky2_tx_timeout, 4743 .ndo_get_stats64 = sky2_get_stats, 4744 }, 4745 }; 4746 4747 /* Initialize network device */ 4748 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, 4749 int highmem, int wol) 4750 { 4751 struct sky2_port *sky2; 4752 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4753 const void *iap; 4754 4755 if (!dev) 4756 return NULL; 4757 4758 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4759 dev->irq = hw->pdev->irq; 4760 dev->ethtool_ops = &sky2_ethtool_ops; 4761 dev->watchdog_timeo = TX_WATCHDOG; 4762 dev->netdev_ops = &sky2_netdev_ops[port]; 4763 4764 sky2 = netdev_priv(dev); 4765 sky2->netdev = dev; 4766 sky2->hw = hw; 4767 sky2->msg_enable = netif_msg_init(debug, default_msg); 4768 4769 u64_stats_init(&sky2->tx_stats.syncp); 4770 u64_stats_init(&sky2->rx_stats.syncp); 4771 4772 /* Auto speed and flow control */ 4773 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4774 if (hw->chip_id != CHIP_ID_YUKON_XL) 4775 dev->hw_features |= NETIF_F_RXCSUM; 4776 4777 sky2->flow_mode = FC_BOTH; 4778 4779 sky2->duplex = -1; 4780 sky2->speed = -1; 4781 sky2->advertising = sky2_supported_modes(hw); 4782 sky2->wol = wol; 4783 4784 spin_lock_init(&sky2->phy_lock); 4785 4786 sky2->tx_pending = TX_DEF_PENDING; 4787 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4788 sky2->rx_pending = RX_DEF_PENDING; 4789 4790 hw->dev[port] = dev; 4791 4792 sky2->port = port; 4793 4794 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4795 4796 if (highmem) 4797 dev->features |= NETIF_F_HIGHDMA; 4798 4799 /* Enable receive hashing unless hardware is known broken */ 4800 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4801 dev->hw_features |= NETIF_F_RXHASH; 4802 4803 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4804 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 4805 NETIF_F_HW_VLAN_CTAG_RX; 4806 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4807 } 4808 4809 dev->features |= dev->hw_features; 4810 4811 /* MTU range: 60 - 1500 or 9000 */ 4812 dev->min_mtu = ETH_ZLEN; 4813 if (hw->chip_id == CHIP_ID_YUKON_FE || 4814 hw->chip_id == CHIP_ID_YUKON_FE_P) 4815 dev->max_mtu = ETH_DATA_LEN; 4816 else 4817 dev->max_mtu = ETH_JUMBO_MTU; 4818 4819 /* try to get mac address in the following order: 4820 * 1) from device tree data 4821 * 2) from internal registers set by bootloader 4822 */ 4823 iap = of_get_mac_address(hw->pdev->dev.of_node); 4824 if (iap) 4825 memcpy(dev->dev_addr, iap, ETH_ALEN); 4826 else 4827 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, 4828 ETH_ALEN); 4829 4830 /* if the address is invalid, use a random value */ 4831 if (!is_valid_ether_addr(dev->dev_addr)) { 4832 struct sockaddr sa = { AF_UNSPEC }; 4833 4834 netdev_warn(dev, 4835 "Invalid MAC address, defaulting to random\n"); 4836 eth_hw_addr_random(dev); 4837 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); 4838 if (sky2_set_mac_address(dev, &sa)) 4839 netdev_warn(dev, "Failed to set MAC address.\n"); 4840 } 4841 4842 return dev; 4843 } 4844 4845 static void sky2_show_addr(struct net_device *dev) 4846 { 4847 const struct sky2_port *sky2 = netdev_priv(dev); 4848 4849 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4850 } 4851 4852 /* Handle software interrupt used during MSI test */ 4853 static irqreturn_t sky2_test_intr(int irq, void *dev_id) 4854 { 4855 struct sky2_hw *hw = dev_id; 4856 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4857 4858 if (status == 0) 4859 return IRQ_NONE; 4860 4861 if (status & Y2_IS_IRQ_SW) { 4862 hw->flags |= SKY2_HW_USE_MSI; 4863 wake_up(&hw->msi_wait); 4864 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4865 } 4866 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4867 4868 return IRQ_HANDLED; 4869 } 4870 4871 /* Test interrupt path by forcing a a software IRQ */ 4872 static int sky2_test_msi(struct sky2_hw *hw) 4873 { 4874 struct pci_dev *pdev = hw->pdev; 4875 int err; 4876 4877 init_waitqueue_head(&hw->msi_wait); 4878 4879 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4880 if (err) { 4881 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4882 return err; 4883 } 4884 4885 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4886 4887 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4888 sky2_read8(hw, B0_CTST); 4889 4890 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4891 4892 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4893 /* MSI test failed, go back to INTx mode */ 4894 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4895 "switching to INTx mode.\n"); 4896 4897 err = -EOPNOTSUPP; 4898 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4899 } 4900 4901 sky2_write32(hw, B0_IMSK, 0); 4902 sky2_read32(hw, B0_IMSK); 4903 4904 free_irq(pdev->irq, hw); 4905 4906 return err; 4907 } 4908 4909 /* This driver supports yukon2 chipset only */ 4910 static const char *sky2_name(u8 chipid, char *buf, int sz) 4911 { 4912 const char *name[] = { 4913 "XL", /* 0xb3 */ 4914 "EC Ultra", /* 0xb4 */ 4915 "Extreme", /* 0xb5 */ 4916 "EC", /* 0xb6 */ 4917 "FE", /* 0xb7 */ 4918 "FE+", /* 0xb8 */ 4919 "Supreme", /* 0xb9 */ 4920 "UL 2", /* 0xba */ 4921 "Unknown", /* 0xbb */ 4922 "Optima", /* 0xbc */ 4923 "OptimaEEE", /* 0xbd */ 4924 "Optima 2", /* 0xbe */ 4925 }; 4926 4927 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4928 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4929 else 4930 snprintf(buf, sz, "(chip %#x)", chipid); 4931 return buf; 4932 } 4933 4934 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 4935 { 4936 struct net_device *dev, *dev1; 4937 struct sky2_hw *hw; 4938 int err, using_dac = 0, wol_default; 4939 u32 reg; 4940 char buf1[16]; 4941 4942 err = pci_enable_device(pdev); 4943 if (err) { 4944 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4945 goto err_out; 4946 } 4947 4948 /* Get configuration information 4949 * Note: only regular PCI config access once to test for HW issues 4950 * other PCI access through shared memory for speed and to 4951 * avoid MMCONFIG problems. 4952 */ 4953 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4954 if (err) { 4955 dev_err(&pdev->dev, "PCI read config failed\n"); 4956 goto err_out_disable; 4957 } 4958 4959 if (~reg == 0) { 4960 dev_err(&pdev->dev, "PCI configuration read error\n"); 4961 err = -EIO; 4962 goto err_out_disable; 4963 } 4964 4965 err = pci_request_regions(pdev, DRV_NAME); 4966 if (err) { 4967 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4968 goto err_out_disable; 4969 } 4970 4971 pci_set_master(pdev); 4972 4973 if (sizeof(dma_addr_t) > sizeof(u32) && 4974 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4975 using_dac = 1; 4976 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4977 if (err < 0) { 4978 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4979 "for consistent allocations\n"); 4980 goto err_out_free_regions; 4981 } 4982 } else { 4983 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4984 if (err) { 4985 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4986 goto err_out_free_regions; 4987 } 4988 } 4989 4990 4991 #ifdef __BIG_ENDIAN 4992 /* The sk98lin vendor driver uses hardware byte swapping but 4993 * this driver uses software swapping. 4994 */ 4995 reg &= ~PCI_REV_DESC; 4996 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4997 if (err) { 4998 dev_err(&pdev->dev, "PCI write config failed\n"); 4999 goto err_out_free_regions; 5000 } 5001 #endif 5002 5003 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 5004 5005 err = -ENOMEM; 5006 5007 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 5008 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 5009 if (!hw) 5010 goto err_out_free_regions; 5011 5012 hw->pdev = pdev; 5013 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 5014 5015 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 5016 if (!hw->regs) { 5017 dev_err(&pdev->dev, "cannot map device registers\n"); 5018 goto err_out_free_hw; 5019 } 5020 5021 err = sky2_init(hw); 5022 if (err) 5023 goto err_out_iounmap; 5024 5025 /* ring for status responses */ 5026 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 5027 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5028 &hw->st_dma); 5029 if (!hw->st_le) { 5030 err = -ENOMEM; 5031 goto err_out_reset; 5032 } 5033 5034 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 5035 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 5036 5037 sky2_reset(hw); 5038 5039 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 5040 if (!dev) { 5041 err = -ENOMEM; 5042 goto err_out_free_pci; 5043 } 5044 5045 if (!disable_msi && pci_enable_msi(pdev) == 0) { 5046 err = sky2_test_msi(hw); 5047 if (err) { 5048 pci_disable_msi(pdev); 5049 if (err != -EOPNOTSUPP) 5050 goto err_out_free_netdev; 5051 } 5052 } 5053 5054 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 5055 5056 err = register_netdev(dev); 5057 if (err) { 5058 dev_err(&pdev->dev, "cannot register net device\n"); 5059 goto err_out_free_netdev; 5060 } 5061 5062 netif_carrier_off(dev); 5063 5064 sky2_show_addr(dev); 5065 5066 if (hw->ports > 1) { 5067 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 5068 if (!dev1) { 5069 err = -ENOMEM; 5070 goto err_out_unregister; 5071 } 5072 5073 err = register_netdev(dev1); 5074 if (err) { 5075 dev_err(&pdev->dev, "cannot register second net device\n"); 5076 goto err_out_free_dev1; 5077 } 5078 5079 err = sky2_setup_irq(hw, hw->irq_name); 5080 if (err) 5081 goto err_out_unregister_dev1; 5082 5083 sky2_show_addr(dev1); 5084 } 5085 5086 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0); 5087 INIT_WORK(&hw->restart_work, sky2_restart); 5088 5089 pci_set_drvdata(pdev, hw); 5090 pdev->d3_delay = 150; 5091 5092 return 0; 5093 5094 err_out_unregister_dev1: 5095 unregister_netdev(dev1); 5096 err_out_free_dev1: 5097 free_netdev(dev1); 5098 err_out_unregister: 5099 unregister_netdev(dev); 5100 err_out_free_netdev: 5101 if (hw->flags & SKY2_HW_USE_MSI) 5102 pci_disable_msi(pdev); 5103 free_netdev(dev); 5104 err_out_free_pci: 5105 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5106 hw->st_le, hw->st_dma); 5107 err_out_reset: 5108 sky2_write8(hw, B0_CTST, CS_RST_SET); 5109 err_out_iounmap: 5110 iounmap(hw->regs); 5111 err_out_free_hw: 5112 kfree(hw); 5113 err_out_free_regions: 5114 pci_release_regions(pdev); 5115 err_out_disable: 5116 pci_disable_device(pdev); 5117 err_out: 5118 return err; 5119 } 5120 5121 static void sky2_remove(struct pci_dev *pdev) 5122 { 5123 struct sky2_hw *hw = pci_get_drvdata(pdev); 5124 int i; 5125 5126 if (!hw) 5127 return; 5128 5129 del_timer_sync(&hw->watchdog_timer); 5130 cancel_work_sync(&hw->restart_work); 5131 5132 for (i = hw->ports-1; i >= 0; --i) 5133 unregister_netdev(hw->dev[i]); 5134 5135 sky2_write32(hw, B0_IMSK, 0); 5136 sky2_read32(hw, B0_IMSK); 5137 5138 sky2_power_aux(hw); 5139 5140 sky2_write8(hw, B0_CTST, CS_RST_SET); 5141 sky2_read8(hw, B0_CTST); 5142 5143 if (hw->ports > 1) { 5144 napi_disable(&hw->napi); 5145 free_irq(pdev->irq, hw); 5146 } 5147 5148 if (hw->flags & SKY2_HW_USE_MSI) 5149 pci_disable_msi(pdev); 5150 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5151 hw->st_le, hw->st_dma); 5152 pci_release_regions(pdev); 5153 pci_disable_device(pdev); 5154 5155 for (i = hw->ports-1; i >= 0; --i) 5156 free_netdev(hw->dev[i]); 5157 5158 iounmap(hw->regs); 5159 kfree(hw); 5160 } 5161 5162 static int sky2_suspend(struct device *dev) 5163 { 5164 struct pci_dev *pdev = to_pci_dev(dev); 5165 struct sky2_hw *hw = pci_get_drvdata(pdev); 5166 int i; 5167 5168 if (!hw) 5169 return 0; 5170 5171 del_timer_sync(&hw->watchdog_timer); 5172 cancel_work_sync(&hw->restart_work); 5173 5174 rtnl_lock(); 5175 5176 sky2_all_down(hw); 5177 for (i = 0; i < hw->ports; i++) { 5178 struct net_device *dev = hw->dev[i]; 5179 struct sky2_port *sky2 = netdev_priv(dev); 5180 5181 if (sky2->wol) 5182 sky2_wol_init(sky2); 5183 } 5184 5185 sky2_power_aux(hw); 5186 rtnl_unlock(); 5187 5188 return 0; 5189 } 5190 5191 #ifdef CONFIG_PM_SLEEP 5192 static int sky2_resume(struct device *dev) 5193 { 5194 struct pci_dev *pdev = to_pci_dev(dev); 5195 struct sky2_hw *hw = pci_get_drvdata(pdev); 5196 int err; 5197 5198 if (!hw) 5199 return 0; 5200 5201 /* Re-enable all clocks */ 5202 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5203 if (err) { 5204 dev_err(&pdev->dev, "PCI write config failed\n"); 5205 goto out; 5206 } 5207 5208 rtnl_lock(); 5209 sky2_reset(hw); 5210 sky2_all_up(hw); 5211 rtnl_unlock(); 5212 5213 return 0; 5214 out: 5215 5216 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5217 pci_disable_device(pdev); 5218 return err; 5219 } 5220 5221 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5222 #define SKY2_PM_OPS (&sky2_pm_ops) 5223 5224 #else 5225 5226 #define SKY2_PM_OPS NULL 5227 #endif 5228 5229 static void sky2_shutdown(struct pci_dev *pdev) 5230 { 5231 struct sky2_hw *hw = pci_get_drvdata(pdev); 5232 int port; 5233 5234 for (port = 0; port < hw->ports; port++) { 5235 struct net_device *ndev = hw->dev[port]; 5236 5237 rtnl_lock(); 5238 if (netif_running(ndev)) { 5239 dev_close(ndev); 5240 netif_device_detach(ndev); 5241 } 5242 rtnl_unlock(); 5243 } 5244 sky2_suspend(&pdev->dev); 5245 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5246 pci_set_power_state(pdev, PCI_D3hot); 5247 } 5248 5249 static struct pci_driver sky2_driver = { 5250 .name = DRV_NAME, 5251 .id_table = sky2_id_table, 5252 .probe = sky2_probe, 5253 .remove = sky2_remove, 5254 .shutdown = sky2_shutdown, 5255 .driver.pm = SKY2_PM_OPS, 5256 }; 5257 5258 static int __init sky2_init_module(void) 5259 { 5260 pr_info("driver version " DRV_VERSION "\n"); 5261 5262 sky2_debug_init(); 5263 return pci_register_driver(&sky2_driver); 5264 } 5265 5266 static void __exit sky2_cleanup_module(void) 5267 { 5268 pci_unregister_driver(&sky2_driver); 5269 sky2_debug_cleanup(); 5270 } 5271 5272 module_init(sky2_init_module); 5273 module_exit(sky2_cleanup_module); 5274 5275 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5276 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5277 MODULE_LICENSE("GPL"); 5278 MODULE_VERSION(DRV_VERSION); 5279