1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 #include <linux/of_device.h> 48 #include <linux/of_net.h> 49 50 #include <asm/irq.h> 51 52 #include "sky2.h" 53 54 #define DRV_NAME "sky2" 55 #define DRV_VERSION "1.30" 56 57 /* 58 * The Yukon II chipset takes 64 bit command blocks (called list elements) 59 * that are organized into three (receive, transmit, status) different rings 60 * similar to Tigon3. 61 */ 62 63 #define RX_LE_SIZE 1024 64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 66 #define RX_DEF_PENDING RX_MAX_PENDING 67 68 /* This is the worst case number of transmit list elements for a single skb: 69 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 70 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 71 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 72 #define TX_MAX_PENDING 1024 73 #define TX_DEF_PENDING 63 74 75 #define TX_WATCHDOG (5 * HZ) 76 #define NAPI_WEIGHT 64 77 #define PHY_RETRIES 1000 78 79 #define SKY2_EEPROM_MAGIC 0x9955aabb 80 81 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 82 83 static const u32 default_msg = 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 87 88 static int debug = -1; /* defaults above */ 89 module_param(debug, int, 0); 90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 91 92 static int copybreak __read_mostly = 128; 93 module_param(copybreak, int, 0); 94 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 95 96 static int disable_msi = 0; 97 module_param(disable_msi, int, 0); 98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 99 100 static int legacy_pme = 0; 101 module_param(legacy_pme, int, 0); 102 MODULE_PARM_DESC(legacy_pme, "Legacy power management"); 103 104 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = { 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ 147 { 0 } 148 }; 149 150 MODULE_DEVICE_TABLE(pci, sky2_id_table); 151 152 /* Avoid conditionals by using array */ 153 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 154 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 155 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 156 157 static void sky2_set_multicast(struct net_device *dev); 158 static irqreturn_t sky2_intr(int irq, void *dev_id); 159 160 /* Access to PHY via serial interconnect */ 161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 162 { 163 int i; 164 165 gma_write16(hw, port, GM_SMI_DATA, val); 166 gma_write16(hw, port, GM_SMI_CTRL, 167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 168 169 for (i = 0; i < PHY_RETRIES; i++) { 170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 171 if (ctrl == 0xffff) 172 goto io_error; 173 174 if (!(ctrl & GM_SMI_CT_BUSY)) 175 return 0; 176 177 udelay(10); 178 } 179 180 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 181 return -ETIMEDOUT; 182 183 io_error: 184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 185 return -EIO; 186 } 187 188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 189 { 190 int i; 191 192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 194 195 for (i = 0; i < PHY_RETRIES; i++) { 196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 197 if (ctrl == 0xffff) 198 goto io_error; 199 200 if (ctrl & GM_SMI_CT_RD_VAL) { 201 *val = gma_read16(hw, port, GM_SMI_DATA); 202 return 0; 203 } 204 205 udelay(10); 206 } 207 208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 209 return -ETIMEDOUT; 210 io_error: 211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 212 return -EIO; 213 } 214 215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 216 { 217 u16 v; 218 __gm_phy_read(hw, port, reg, &v); 219 return v; 220 } 221 222 223 static void sky2_power_on(struct sky2_hw *hw) 224 { 225 /* switch power to VCC (WA for VAUX problem) */ 226 sky2_write8(hw, B0_POWER_CTRL, 227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 228 229 /* disable Core Clock Division, */ 230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 231 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 233 /* enable bits are inverted */ 234 sky2_write8(hw, B2_Y2_CLK_GATE, 235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 238 else 239 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 240 241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 242 u32 reg; 243 244 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 245 246 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 247 /* set all bits to 0 except bits 15..12 and 8 */ 248 reg &= P_ASPM_CONTROL_MSK; 249 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 250 251 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 252 /* set all bits to 0 except bits 28 & 27 */ 253 reg &= P_CTL_TIM_VMAIN_AV_MSK; 254 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 255 256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 257 258 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 259 260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 261 reg = sky2_read32(hw, B2_GP_IO); 262 reg |= GLB_GPIO_STAT_RACE_DIS; 263 sky2_write32(hw, B2_GP_IO, reg); 264 265 sky2_read32(hw, B2_GP_IO); 266 } 267 268 /* Turn on "driver loaded" LED */ 269 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 270 } 271 272 static void sky2_power_aux(struct sky2_hw *hw) 273 { 274 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 275 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 276 else 277 /* enable bits are inverted */ 278 sky2_write8(hw, B2_Y2_CLK_GATE, 279 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 280 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 281 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 282 283 /* switch power to VAUX if supported and PME from D3cold */ 284 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 285 pci_pme_capable(hw->pdev, PCI_D3cold)) 286 sky2_write8(hw, B0_POWER_CTRL, 287 (PC_VAUX_ENA | PC_VCC_ENA | 288 PC_VAUX_ON | PC_VCC_OFF)); 289 290 /* turn off "driver loaded LED" */ 291 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 292 } 293 294 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 295 { 296 u16 reg; 297 298 /* disable all GMAC IRQ's */ 299 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 300 301 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 302 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 303 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 304 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 305 306 reg = gma_read16(hw, port, GM_RX_CTRL); 307 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 308 gma_write16(hw, port, GM_RX_CTRL, reg); 309 } 310 311 /* flow control to advertise bits */ 312 static const u16 copper_fc_adv[] = { 313 [FC_NONE] = 0, 314 [FC_TX] = PHY_M_AN_ASP, 315 [FC_RX] = PHY_M_AN_PC, 316 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 317 }; 318 319 /* flow control to advertise bits when using 1000BaseX */ 320 static const u16 fiber_fc_adv[] = { 321 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 322 [FC_TX] = PHY_M_P_ASYM_MD_X, 323 [FC_RX] = PHY_M_P_SYM_MD_X, 324 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 325 }; 326 327 /* flow control to GMA disable bits */ 328 static const u16 gm_fc_disable[] = { 329 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 330 [FC_TX] = GM_GPCR_FC_RX_DIS, 331 [FC_RX] = GM_GPCR_FC_TX_DIS, 332 [FC_BOTH] = 0, 333 }; 334 335 336 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 337 { 338 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 339 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 340 341 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 342 !(hw->flags & SKY2_HW_NEWER_PHY)) { 343 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 344 345 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 346 PHY_M_EC_MAC_S_MSK); 347 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 348 349 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 350 if (hw->chip_id == CHIP_ID_YUKON_EC) 351 /* set downshift counter to 3x and enable downshift */ 352 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 353 else 354 /* set master & slave downshift counter to 1x */ 355 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 356 357 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 358 } 359 360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 361 if (sky2_is_copper(hw)) { 362 if (!(hw->flags & SKY2_HW_GIGABIT)) { 363 /* enable automatic crossover */ 364 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 365 366 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 367 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 368 u16 spec; 369 370 /* Enable Class A driver for FE+ A0 */ 371 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 372 spec |= PHY_M_FESC_SEL_CL_A; 373 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 374 } 375 } else { 376 /* disable energy detect */ 377 ctrl &= ~PHY_M_PC_EN_DET_MSK; 378 379 /* enable automatic crossover */ 380 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 381 382 /* downshift on PHY 88E1112 and 88E1149 is changed */ 383 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 384 (hw->flags & SKY2_HW_NEWER_PHY)) { 385 /* set downshift counter to 3x and enable downshift */ 386 ctrl &= ~PHY_M_PC_DSC_MSK; 387 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 388 } 389 } 390 } else { 391 /* workaround for deviation #4.88 (CRC errors) */ 392 /* disable Automatic Crossover */ 393 394 ctrl &= ~PHY_M_PC_MDIX_MSK; 395 } 396 397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 398 399 /* special setup for PHY 88E1112 Fiber */ 400 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 401 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 402 403 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 406 ctrl &= ~PHY_M_MAC_MD_MSK; 407 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 409 410 if (hw->pmd_type == 'P') { 411 /* select page 1 to access Fiber registers */ 412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 413 414 /* for SFP-module set SIGDET polarity to low */ 415 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 416 ctrl |= PHY_M_FIB_SIGD_POL; 417 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 418 } 419 420 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 421 } 422 423 ctrl = PHY_CT_RESET; 424 ct1000 = 0; 425 adv = PHY_AN_CSMA; 426 reg = 0; 427 428 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 429 if (sky2_is_copper(hw)) { 430 if (sky2->advertising & ADVERTISED_1000baseT_Full) 431 ct1000 |= PHY_M_1000C_AFD; 432 if (sky2->advertising & ADVERTISED_1000baseT_Half) 433 ct1000 |= PHY_M_1000C_AHD; 434 if (sky2->advertising & ADVERTISED_100baseT_Full) 435 adv |= PHY_M_AN_100_FD; 436 if (sky2->advertising & ADVERTISED_100baseT_Half) 437 adv |= PHY_M_AN_100_HD; 438 if (sky2->advertising & ADVERTISED_10baseT_Full) 439 adv |= PHY_M_AN_10_FD; 440 if (sky2->advertising & ADVERTISED_10baseT_Half) 441 adv |= PHY_M_AN_10_HD; 442 443 } else { /* special defines for FIBER (88E1040S only) */ 444 if (sky2->advertising & ADVERTISED_1000baseT_Full) 445 adv |= PHY_M_AN_1000X_AFD; 446 if (sky2->advertising & ADVERTISED_1000baseT_Half) 447 adv |= PHY_M_AN_1000X_AHD; 448 } 449 450 /* Restart Auto-negotiation */ 451 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 452 } else { 453 /* forced speed/duplex settings */ 454 ct1000 = PHY_M_1000C_MSE; 455 456 /* Disable auto update for duplex flow control and duplex */ 457 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 458 459 switch (sky2->speed) { 460 case SPEED_1000: 461 ctrl |= PHY_CT_SP1000; 462 reg |= GM_GPCR_SPEED_1000; 463 break; 464 case SPEED_100: 465 ctrl |= PHY_CT_SP100; 466 reg |= GM_GPCR_SPEED_100; 467 break; 468 } 469 470 if (sky2->duplex == DUPLEX_FULL) { 471 reg |= GM_GPCR_DUP_FULL; 472 ctrl |= PHY_CT_DUP_MD; 473 } else if (sky2->speed < SPEED_1000) 474 sky2->flow_mode = FC_NONE; 475 } 476 477 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 478 if (sky2_is_copper(hw)) 479 adv |= copper_fc_adv[sky2->flow_mode]; 480 else 481 adv |= fiber_fc_adv[sky2->flow_mode]; 482 } else { 483 reg |= GM_GPCR_AU_FCT_DIS; 484 reg |= gm_fc_disable[sky2->flow_mode]; 485 486 /* Forward pause packets to GMAC? */ 487 if (sky2->flow_mode & FC_RX) 488 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 489 else 490 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 491 } 492 493 gma_write16(hw, port, GM_GP_CTRL, reg); 494 495 if (hw->flags & SKY2_HW_GIGABIT) 496 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 497 498 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 499 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 500 501 /* Setup Phy LED's */ 502 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 503 ledover = 0; 504 505 switch (hw->chip_id) { 506 case CHIP_ID_YUKON_FE: 507 /* on 88E3082 these bits are at 11..9 (shifted left) */ 508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 509 510 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 511 512 /* delete ACT LED control bits */ 513 ctrl &= ~PHY_M_FELP_LED1_MSK; 514 /* change ACT LED control to blink mode */ 515 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 516 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 517 break; 518 519 case CHIP_ID_YUKON_FE_P: 520 /* Enable Link Partner Next Page */ 521 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 522 ctrl |= PHY_M_PC_ENA_LIP_NP; 523 524 /* disable Energy Detect and enable scrambler */ 525 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 526 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 527 528 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 529 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 530 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 531 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 532 533 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 534 break; 535 536 case CHIP_ID_YUKON_XL: 537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 538 539 /* select page 3 to access LED control register */ 540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 541 542 /* set LED Function Control register */ 543 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 544 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 545 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 546 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 547 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 548 549 /* set Polarity Control register */ 550 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 551 (PHY_M_POLC_LS1_P_MIX(4) | 552 PHY_M_POLC_IS0_P_MIX(4) | 553 PHY_M_POLC_LOS_CTRL(2) | 554 PHY_M_POLC_INIT_CTRL(2) | 555 PHY_M_POLC_STA1_CTRL(2) | 556 PHY_M_POLC_STA0_CTRL(2))); 557 558 /* restore page register */ 559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 560 break; 561 562 case CHIP_ID_YUKON_EC_U: 563 case CHIP_ID_YUKON_EX: 564 case CHIP_ID_YUKON_SUPR: 565 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 566 567 /* select page 3 to access LED control register */ 568 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 569 570 /* set LED Function Control register */ 571 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 572 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 573 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 574 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 575 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 576 577 /* set Blink Rate in LED Timer Control Register */ 578 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 579 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 580 /* restore page register */ 581 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 582 break; 583 584 default: 585 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 586 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 587 588 /* turn off the Rx LED (LED_RX) */ 589 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 590 } 591 592 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 593 /* apply fixes in PHY AFE */ 594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 595 596 /* increase differential signal amplitude in 10BASE-T */ 597 gm_phy_write(hw, port, 0x18, 0xaa99); 598 gm_phy_write(hw, port, 0x17, 0x2011); 599 600 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 601 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 602 gm_phy_write(hw, port, 0x18, 0xa204); 603 gm_phy_write(hw, port, 0x17, 0x2002); 604 } 605 606 /* set page register to 0 */ 607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 608 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 609 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 610 /* apply workaround for integrated resistors calibration */ 611 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 612 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 613 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 614 /* apply fixes in PHY AFE */ 615 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 616 617 /* apply RDAC termination workaround */ 618 gm_phy_write(hw, port, 24, 0x2800); 619 gm_phy_write(hw, port, 23, 0x2001); 620 621 /* set page register back to 0 */ 622 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 623 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 624 hw->chip_id < CHIP_ID_YUKON_SUPR) { 625 /* no effect on Yukon-XL */ 626 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 627 628 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 629 sky2->speed == SPEED_100) { 630 /* turn on 100 Mbps LED (LED_LINK100) */ 631 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 632 } 633 634 if (ledover) 635 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 636 637 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 638 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 639 int i; 640 /* This a phy register setup workaround copied from vendor driver. */ 641 static const struct { 642 u16 reg, val; 643 } eee_afe[] = { 644 { 0x156, 0x58ce }, 645 { 0x153, 0x99eb }, 646 { 0x141, 0x8064 }, 647 /* { 0x155, 0x130b },*/ 648 { 0x000, 0x0000 }, 649 { 0x151, 0x8433 }, 650 { 0x14b, 0x8c44 }, 651 { 0x14c, 0x0f90 }, 652 { 0x14f, 0x39aa }, 653 /* { 0x154, 0x2f39 },*/ 654 { 0x14d, 0xba33 }, 655 { 0x144, 0x0048 }, 656 { 0x152, 0x2010 }, 657 /* { 0x158, 0x1223 },*/ 658 { 0x140, 0x4444 }, 659 { 0x154, 0x2f3b }, 660 { 0x158, 0xb203 }, 661 { 0x157, 0x2029 }, 662 }; 663 664 /* Start Workaround for OptimaEEE Rev.Z0 */ 665 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 666 667 gm_phy_write(hw, port, 1, 0x4099); 668 gm_phy_write(hw, port, 3, 0x1120); 669 gm_phy_write(hw, port, 11, 0x113c); 670 gm_phy_write(hw, port, 14, 0x8100); 671 gm_phy_write(hw, port, 15, 0x112a); 672 gm_phy_write(hw, port, 17, 0x1008); 673 674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 675 gm_phy_write(hw, port, 1, 0x20b0); 676 677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 678 679 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 680 /* apply AFE settings */ 681 gm_phy_write(hw, port, 17, eee_afe[i].val); 682 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 683 } 684 685 /* End Workaround for OptimaEEE */ 686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 687 688 /* Enable 10Base-Te (EEE) */ 689 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 690 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 691 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 692 reg | PHY_M_10B_TE_ENABLE); 693 } 694 } 695 696 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 697 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 698 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 699 else 700 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 701 } 702 703 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 704 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 705 706 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 707 { 708 u32 reg1; 709 710 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 711 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 712 reg1 &= ~phy_power[port]; 713 714 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 715 reg1 |= coma_mode[port]; 716 717 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 718 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 719 sky2_pci_read32(hw, PCI_DEV_REG1); 720 721 if (hw->chip_id == CHIP_ID_YUKON_FE) 722 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 723 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 725 } 726 727 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 728 { 729 u32 reg1; 730 u16 ctrl; 731 732 /* release GPHY Control reset */ 733 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 734 735 /* release GMAC reset */ 736 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 737 738 if (hw->flags & SKY2_HW_NEWER_PHY) { 739 /* select page 2 to access MAC control register */ 740 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 741 742 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 743 /* allow GMII Power Down */ 744 ctrl &= ~PHY_M_MAC_GMIF_PUP; 745 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 746 747 /* set page register back to 0 */ 748 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 749 } 750 751 /* setup General Purpose Control Register */ 752 gma_write16(hw, port, GM_GP_CTRL, 753 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 754 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 755 GM_GPCR_AU_SPD_DIS); 756 757 if (hw->chip_id != CHIP_ID_YUKON_EC) { 758 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 759 /* select page 2 to access MAC control register */ 760 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 761 762 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 763 /* enable Power Down */ 764 ctrl |= PHY_M_PC_POW_D_ENA; 765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 766 767 /* set page register back to 0 */ 768 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 769 } 770 771 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 772 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 773 } 774 775 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 776 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 777 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 778 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 779 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 780 } 781 782 /* configure IPG according to used link speed */ 783 static void sky2_set_ipg(struct sky2_port *sky2) 784 { 785 u16 reg; 786 787 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 788 reg &= ~GM_SMOD_IPG_MSK; 789 if (sky2->speed > SPEED_100) 790 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 791 else 792 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 793 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 794 } 795 796 /* Enable Rx/Tx */ 797 static void sky2_enable_rx_tx(struct sky2_port *sky2) 798 { 799 struct sky2_hw *hw = sky2->hw; 800 unsigned port = sky2->port; 801 u16 reg; 802 803 reg = gma_read16(hw, port, GM_GP_CTRL); 804 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 805 gma_write16(hw, port, GM_GP_CTRL, reg); 806 } 807 808 /* Force a renegotiation */ 809 static void sky2_phy_reinit(struct sky2_port *sky2) 810 { 811 spin_lock_bh(&sky2->phy_lock); 812 sky2_phy_init(sky2->hw, sky2->port); 813 sky2_enable_rx_tx(sky2); 814 spin_unlock_bh(&sky2->phy_lock); 815 } 816 817 /* Put device in state to listen for Wake On Lan */ 818 static void sky2_wol_init(struct sky2_port *sky2) 819 { 820 struct sky2_hw *hw = sky2->hw; 821 unsigned port = sky2->port; 822 enum flow_control save_mode; 823 u16 ctrl; 824 825 /* Bring hardware out of reset */ 826 sky2_write16(hw, B0_CTST, CS_RST_CLR); 827 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 828 829 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 830 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 831 832 /* Force to 10/100 833 * sky2_reset will re-enable on resume 834 */ 835 save_mode = sky2->flow_mode; 836 ctrl = sky2->advertising; 837 838 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 839 sky2->flow_mode = FC_NONE; 840 841 spin_lock_bh(&sky2->phy_lock); 842 sky2_phy_power_up(hw, port); 843 sky2_phy_init(hw, port); 844 spin_unlock_bh(&sky2->phy_lock); 845 846 sky2->flow_mode = save_mode; 847 sky2->advertising = ctrl; 848 849 /* Set GMAC to no flow control and auto update for speed/duplex */ 850 gma_write16(hw, port, GM_GP_CTRL, 851 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 852 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 853 854 /* Set WOL address */ 855 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 856 sky2->netdev->dev_addr, ETH_ALEN); 857 858 /* Turn on appropriate WOL control bits */ 859 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 860 ctrl = 0; 861 if (sky2->wol & WAKE_PHY) 862 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 863 else 864 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 865 866 if (sky2->wol & WAKE_MAGIC) 867 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 868 else 869 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 870 871 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 872 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 873 874 /* Disable PiG firmware */ 875 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 876 877 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ 878 if (legacy_pme) { 879 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 880 reg1 |= PCI_Y2_PME_LEGACY; 881 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 882 } 883 884 /* block receiver */ 885 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 886 sky2_read32(hw, B0_CTST); 887 } 888 889 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 890 { 891 struct net_device *dev = hw->dev[port]; 892 893 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 894 hw->chip_rev != CHIP_REV_YU_EX_A0) || 895 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 896 /* Yukon-Extreme B0 and further Extreme devices */ 897 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 898 } else if (dev->mtu > ETH_DATA_LEN) { 899 /* set Tx GMAC FIFO Almost Empty Threshold */ 900 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 901 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 902 903 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 904 } else 905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 906 } 907 908 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 909 { 910 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 911 u16 reg; 912 u32 rx_reg; 913 int i; 914 const u8 *addr = hw->dev[port]->dev_addr; 915 916 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 918 919 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 920 921 if (hw->chip_id == CHIP_ID_YUKON_XL && 922 hw->chip_rev == CHIP_REV_YU_XL_A0 && 923 port == 1) { 924 /* WA DEV_472 -- looks like crossed wires on port 2 */ 925 /* clear GMAC 1 Control reset */ 926 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 927 do { 928 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 930 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 931 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 932 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 933 } 934 935 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 936 937 /* Enable Transmit FIFO Underrun */ 938 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 939 940 spin_lock_bh(&sky2->phy_lock); 941 sky2_phy_power_up(hw, port); 942 sky2_phy_init(hw, port); 943 spin_unlock_bh(&sky2->phy_lock); 944 945 /* MIB clear */ 946 reg = gma_read16(hw, port, GM_PHY_ADDR); 947 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 948 949 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 950 gma_read16(hw, port, i); 951 gma_write16(hw, port, GM_PHY_ADDR, reg); 952 953 /* transmit control */ 954 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 955 956 /* receive control reg: unicast + multicast + no FCS */ 957 gma_write16(hw, port, GM_RX_CTRL, 958 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 959 960 /* transmit flow control */ 961 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 962 963 /* transmit parameter */ 964 gma_write16(hw, port, GM_TX_PARAM, 965 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 966 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 967 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 968 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 969 970 /* serial mode register */ 971 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 972 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 973 974 if (hw->dev[port]->mtu > ETH_DATA_LEN) 975 reg |= GM_SMOD_JUMBO_ENA; 976 977 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 978 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 979 reg |= GM_NEW_FLOW_CTRL; 980 981 gma_write16(hw, port, GM_SERIAL_MODE, reg); 982 983 /* virtual address for data */ 984 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 985 986 /* physical address: used for pause frames */ 987 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 988 989 /* ignore counter overflows */ 990 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 991 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 992 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 993 994 /* Configure Rx MAC FIFO */ 995 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 996 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 997 if (hw->chip_id == CHIP_ID_YUKON_EX || 998 hw->chip_id == CHIP_ID_YUKON_FE_P) 999 rx_reg |= GMF_RX_OVER_ON; 1000 1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 1002 1003 if (hw->chip_id == CHIP_ID_YUKON_XL) { 1004 /* Hardware errata - clear flush mask */ 1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 1006 } else { 1007 /* Flush Rx MAC FIFO on any flow control or error */ 1008 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 1009 } 1010 1011 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 1012 reg = RX_GMF_FL_THR_DEF + 1; 1013 /* Another magic mystery workaround from sk98lin */ 1014 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1015 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1016 reg = 0x178; 1017 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1018 1019 /* Configure Tx MAC FIFO */ 1020 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1021 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1022 1023 /* On chips without ram buffer, pause is controlled by MAC level */ 1024 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1025 /* Pause threshold is scaled by 8 in bytes */ 1026 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1027 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1028 reg = 1568 / 8; 1029 else 1030 reg = 1024 / 8; 1031 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1032 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1033 1034 sky2_set_tx_stfwd(hw, port); 1035 } 1036 1037 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1038 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1039 /* disable dynamic watermark */ 1040 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1041 reg &= ~TX_DYN_WM_ENA; 1042 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1043 } 1044 } 1045 1046 /* Assign Ram Buffer allocation to queue */ 1047 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1048 { 1049 u32 end; 1050 1051 /* convert from K bytes to qwords used for hw register */ 1052 start *= 1024/8; 1053 space *= 1024/8; 1054 end = start + space - 1; 1055 1056 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1057 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1058 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1059 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1060 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1061 1062 if (q == Q_R1 || q == Q_R2) { 1063 u32 tp = space - space/4; 1064 1065 /* On receive queue's set the thresholds 1066 * give receiver priority when > 3/4 full 1067 * send pause when down to 2K 1068 */ 1069 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1070 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1071 1072 tp = space - 8192/8; 1073 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1074 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1075 } else { 1076 /* Enable store & forward on Tx queue's because 1077 * Tx FIFO is only 1K on Yukon 1078 */ 1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1080 } 1081 1082 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1083 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1084 } 1085 1086 /* Setup Bus Memory Interface */ 1087 static void sky2_qset(struct sky2_hw *hw, u16 q) 1088 { 1089 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1092 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1093 } 1094 1095 /* Setup prefetch unit registers. This is the interface between 1096 * hardware and driver list elements 1097 */ 1098 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1099 dma_addr_t addr, u32 last) 1100 { 1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1105 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1106 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1107 1108 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1109 } 1110 1111 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1112 { 1113 struct sky2_tx_le *le = sky2->tx_le + *slot; 1114 1115 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1116 le->ctrl = 0; 1117 return le; 1118 } 1119 1120 static void tx_init(struct sky2_port *sky2) 1121 { 1122 struct sky2_tx_le *le; 1123 1124 sky2->tx_prod = sky2->tx_cons = 0; 1125 sky2->tx_tcpsum = 0; 1126 sky2->tx_last_mss = 0; 1127 netdev_reset_queue(sky2->netdev); 1128 1129 le = get_tx_le(sky2, &sky2->tx_prod); 1130 le->addr = 0; 1131 le->opcode = OP_ADDR64 | HW_OWNER; 1132 sky2->tx_last_upper = 0; 1133 } 1134 1135 /* Update chip's next pointer */ 1136 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1137 { 1138 /* Make sure write' to descriptors are complete before we tell hardware */ 1139 wmb(); 1140 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1141 1142 /* Synchronize I/O on since next processor may write to tail */ 1143 mmiowb(); 1144 } 1145 1146 1147 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1148 { 1149 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1150 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1151 le->ctrl = 0; 1152 return le; 1153 } 1154 1155 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1156 { 1157 unsigned size; 1158 1159 /* Space needed for frame data + headers rounded up */ 1160 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1161 1162 /* Stopping point for hardware truncation */ 1163 return (size - 8) / sizeof(u32); 1164 } 1165 1166 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1167 { 1168 struct rx_ring_info *re; 1169 unsigned size; 1170 1171 /* Space needed for frame data + headers rounded up */ 1172 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1173 1174 sky2->rx_nfrags = size >> PAGE_SHIFT; 1175 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1176 1177 /* Compute residue after pages */ 1178 size -= sky2->rx_nfrags << PAGE_SHIFT; 1179 1180 /* Optimize to handle small packets and headers */ 1181 if (size < copybreak) 1182 size = copybreak; 1183 if (size < ETH_HLEN) 1184 size = ETH_HLEN; 1185 1186 return size; 1187 } 1188 1189 /* Build description to hardware for one receive segment */ 1190 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1191 dma_addr_t map, unsigned len) 1192 { 1193 struct sky2_rx_le *le; 1194 1195 if (sizeof(dma_addr_t) > sizeof(u32)) { 1196 le = sky2_next_rx(sky2); 1197 le->addr = cpu_to_le32(upper_32_bits(map)); 1198 le->opcode = OP_ADDR64 | HW_OWNER; 1199 } 1200 1201 le = sky2_next_rx(sky2); 1202 le->addr = cpu_to_le32(lower_32_bits(map)); 1203 le->length = cpu_to_le16(len); 1204 le->opcode = op | HW_OWNER; 1205 } 1206 1207 /* Build description to hardware for one possibly fragmented skb */ 1208 static void sky2_rx_submit(struct sky2_port *sky2, 1209 const struct rx_ring_info *re) 1210 { 1211 int i; 1212 1213 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1214 1215 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1216 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1217 } 1218 1219 1220 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1221 unsigned size) 1222 { 1223 struct sk_buff *skb = re->skb; 1224 int i; 1225 1226 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1227 if (pci_dma_mapping_error(pdev, re->data_addr)) 1228 goto mapping_error; 1229 1230 dma_unmap_len_set(re, data_size, size); 1231 1232 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1233 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1234 1235 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1236 skb_frag_size(frag), 1237 DMA_FROM_DEVICE); 1238 1239 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1240 goto map_page_error; 1241 } 1242 return 0; 1243 1244 map_page_error: 1245 while (--i >= 0) { 1246 pci_unmap_page(pdev, re->frag_addr[i], 1247 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1248 PCI_DMA_FROMDEVICE); 1249 } 1250 1251 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1252 PCI_DMA_FROMDEVICE); 1253 1254 mapping_error: 1255 if (net_ratelimit()) 1256 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1257 skb->dev->name); 1258 return -EIO; 1259 } 1260 1261 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1262 { 1263 struct sk_buff *skb = re->skb; 1264 int i; 1265 1266 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1267 PCI_DMA_FROMDEVICE); 1268 1269 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1270 pci_unmap_page(pdev, re->frag_addr[i], 1271 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1272 PCI_DMA_FROMDEVICE); 1273 } 1274 1275 /* Tell chip where to start receive checksum. 1276 * Actually has two checksums, but set both same to avoid possible byte 1277 * order problems. 1278 */ 1279 static void rx_set_checksum(struct sky2_port *sky2) 1280 { 1281 struct sky2_rx_le *le = sky2_next_rx(sky2); 1282 1283 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1284 le->ctrl = 0; 1285 le->opcode = OP_TCPSTART | HW_OWNER; 1286 1287 sky2_write32(sky2->hw, 1288 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1289 (sky2->netdev->features & NETIF_F_RXCSUM) 1290 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1291 } 1292 1293 /* 1294 * Fixed initial key as seed to RSS. 1295 */ 1296 static const uint32_t rss_init_key[10] = { 1297 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43, 1298 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30 1299 }; 1300 1301 /* Enable/disable receive hash calculation (RSS) */ 1302 static void rx_set_rss(struct net_device *dev, netdev_features_t features) 1303 { 1304 struct sky2_port *sky2 = netdev_priv(dev); 1305 struct sky2_hw *hw = sky2->hw; 1306 int i, nkeys = 4; 1307 1308 /* Supports IPv6 and other modes */ 1309 if (hw->flags & SKY2_HW_NEW_LE) { 1310 nkeys = 10; 1311 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1312 } 1313 1314 /* Program RSS initial values */ 1315 if (features & NETIF_F_RXHASH) { 1316 for (i = 0; i < nkeys; i++) 1317 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1318 rss_init_key[i]); 1319 1320 /* Need to turn on (undocumented) flag to make hashing work */ 1321 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1322 RX_STFW_ENA); 1323 1324 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1325 BMU_ENA_RX_RSS_HASH); 1326 } else 1327 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1328 BMU_DIS_RX_RSS_HASH); 1329 } 1330 1331 /* 1332 * The RX Stop command will not work for Yukon-2 if the BMU does not 1333 * reach the end of packet and since we can't make sure that we have 1334 * incoming data, we must reset the BMU while it is not doing a DMA 1335 * transfer. Since it is possible that the RX path is still active, 1336 * the RX RAM buffer will be stopped first, so any possible incoming 1337 * data will not trigger a DMA. After the RAM buffer is stopped, the 1338 * BMU is polled until any DMA in progress is ended and only then it 1339 * will be reset. 1340 */ 1341 static void sky2_rx_stop(struct sky2_port *sky2) 1342 { 1343 struct sky2_hw *hw = sky2->hw; 1344 unsigned rxq = rxqaddr[sky2->port]; 1345 int i; 1346 1347 /* disable the RAM Buffer receive queue */ 1348 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1349 1350 for (i = 0; i < 0xffff; i++) 1351 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1352 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1353 goto stopped; 1354 1355 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1356 stopped: 1357 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1358 1359 /* reset the Rx prefetch unit */ 1360 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1361 mmiowb(); 1362 } 1363 1364 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1365 static void sky2_rx_clean(struct sky2_port *sky2) 1366 { 1367 unsigned i; 1368 1369 memset(sky2->rx_le, 0, RX_LE_BYTES); 1370 for (i = 0; i < sky2->rx_pending; i++) { 1371 struct rx_ring_info *re = sky2->rx_ring + i; 1372 1373 if (re->skb) { 1374 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1375 kfree_skb(re->skb); 1376 re->skb = NULL; 1377 } 1378 } 1379 } 1380 1381 /* Basic MII support */ 1382 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1383 { 1384 struct mii_ioctl_data *data = if_mii(ifr); 1385 struct sky2_port *sky2 = netdev_priv(dev); 1386 struct sky2_hw *hw = sky2->hw; 1387 int err = -EOPNOTSUPP; 1388 1389 if (!netif_running(dev)) 1390 return -ENODEV; /* Phy still in reset */ 1391 1392 switch (cmd) { 1393 case SIOCGMIIPHY: 1394 data->phy_id = PHY_ADDR_MARV; 1395 1396 /* fallthru */ 1397 case SIOCGMIIREG: { 1398 u16 val = 0; 1399 1400 spin_lock_bh(&sky2->phy_lock); 1401 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1402 spin_unlock_bh(&sky2->phy_lock); 1403 1404 data->val_out = val; 1405 break; 1406 } 1407 1408 case SIOCSMIIREG: 1409 spin_lock_bh(&sky2->phy_lock); 1410 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1411 data->val_in); 1412 spin_unlock_bh(&sky2->phy_lock); 1413 break; 1414 } 1415 return err; 1416 } 1417 1418 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1419 1420 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) 1421 { 1422 struct sky2_port *sky2 = netdev_priv(dev); 1423 struct sky2_hw *hw = sky2->hw; 1424 u16 port = sky2->port; 1425 1426 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1428 RX_VLAN_STRIP_ON); 1429 else 1430 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1431 RX_VLAN_STRIP_OFF); 1432 1433 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 1434 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1435 TX_VLAN_TAG_ON); 1436 1437 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1438 } else { 1439 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1440 TX_VLAN_TAG_OFF); 1441 1442 /* Can't do transmit offload of vlan without hw vlan */ 1443 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1444 } 1445 } 1446 1447 /* Amount of required worst case padding in rx buffer */ 1448 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1449 { 1450 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1451 } 1452 1453 /* 1454 * Allocate an skb for receiving. If the MTU is large enough 1455 * make the skb non-linear with a fragment list of pages. 1456 */ 1457 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1458 { 1459 struct sk_buff *skb; 1460 int i; 1461 1462 skb = __netdev_alloc_skb(sky2->netdev, 1463 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1464 gfp); 1465 if (!skb) 1466 goto nomem; 1467 1468 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1469 unsigned char *start; 1470 /* 1471 * Workaround for a bug in FIFO that cause hang 1472 * if the FIFO if the receive buffer is not 64 byte aligned. 1473 * The buffer returned from netdev_alloc_skb is 1474 * aligned except if slab debugging is enabled. 1475 */ 1476 start = PTR_ALIGN(skb->data, 8); 1477 skb_reserve(skb, start - skb->data); 1478 } else 1479 skb_reserve(skb, NET_IP_ALIGN); 1480 1481 for (i = 0; i < sky2->rx_nfrags; i++) { 1482 struct page *page = alloc_page(gfp); 1483 1484 if (!page) 1485 goto free_partial; 1486 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1487 } 1488 1489 return skb; 1490 free_partial: 1491 kfree_skb(skb); 1492 nomem: 1493 return NULL; 1494 } 1495 1496 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1497 { 1498 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1499 } 1500 1501 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1502 { 1503 struct sky2_hw *hw = sky2->hw; 1504 unsigned i; 1505 1506 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1507 1508 /* Fill Rx ring */ 1509 for (i = 0; i < sky2->rx_pending; i++) { 1510 struct rx_ring_info *re = sky2->rx_ring + i; 1511 1512 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1513 if (!re->skb) 1514 return -ENOMEM; 1515 1516 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1517 dev_kfree_skb(re->skb); 1518 re->skb = NULL; 1519 return -ENOMEM; 1520 } 1521 } 1522 return 0; 1523 } 1524 1525 /* 1526 * Setup receiver buffer pool. 1527 * Normal case this ends up creating one list element for skb 1528 * in the receive ring. Worst case if using large MTU and each 1529 * allocation falls on a different 64 bit region, that results 1530 * in 6 list elements per ring entry. 1531 * One element is used for checksum enable/disable, and one 1532 * extra to avoid wrap. 1533 */ 1534 static void sky2_rx_start(struct sky2_port *sky2) 1535 { 1536 struct sky2_hw *hw = sky2->hw; 1537 struct rx_ring_info *re; 1538 unsigned rxq = rxqaddr[sky2->port]; 1539 unsigned i, thresh; 1540 1541 sky2->rx_put = sky2->rx_next = 0; 1542 sky2_qset(hw, rxq); 1543 1544 /* On PCI express lowering the watermark gives better performance */ 1545 if (pci_is_pcie(hw->pdev)) 1546 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1547 1548 /* These chips have no ram buffer? 1549 * MAC Rx RAM Read is controlled by hardware */ 1550 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1551 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1552 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1553 1554 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1555 1556 if (!(hw->flags & SKY2_HW_NEW_LE)) 1557 rx_set_checksum(sky2); 1558 1559 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1560 rx_set_rss(sky2->netdev, sky2->netdev->features); 1561 1562 /* submit Rx ring */ 1563 for (i = 0; i < sky2->rx_pending; i++) { 1564 re = sky2->rx_ring + i; 1565 sky2_rx_submit(sky2, re); 1566 } 1567 1568 /* 1569 * The receiver hangs if it receives frames larger than the 1570 * packet buffer. As a workaround, truncate oversize frames, but 1571 * the register is limited to 9 bits, so if you do frames > 2052 1572 * you better get the MTU right! 1573 */ 1574 thresh = sky2_get_rx_threshold(sky2); 1575 if (thresh > 0x1ff) 1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1577 else { 1578 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1579 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1580 } 1581 1582 /* Tell chip about available buffers */ 1583 sky2_rx_update(sky2, rxq); 1584 1585 if (hw->chip_id == CHIP_ID_YUKON_EX || 1586 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1587 /* 1588 * Disable flushing of non ASF packets; 1589 * must be done after initializing the BMUs; 1590 * drivers without ASF support should do this too, otherwise 1591 * it may happen that they cannot run on ASF devices; 1592 * remember that the MAC FIFO isn't reset during initialization. 1593 */ 1594 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1595 } 1596 1597 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1598 /* Enable RX Home Address & Routing Header checksum fix */ 1599 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1600 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1601 1602 /* Enable TX Home Address & Routing Header checksum fix */ 1603 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1604 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1605 } 1606 } 1607 1608 static int sky2_alloc_buffers(struct sky2_port *sky2) 1609 { 1610 struct sky2_hw *hw = sky2->hw; 1611 1612 /* must be power of 2 */ 1613 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1614 sky2->tx_ring_size * 1615 sizeof(struct sky2_tx_le), 1616 &sky2->tx_le_map); 1617 if (!sky2->tx_le) 1618 goto nomem; 1619 1620 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1621 GFP_KERNEL); 1622 if (!sky2->tx_ring) 1623 goto nomem; 1624 1625 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, 1626 &sky2->rx_le_map); 1627 if (!sky2->rx_le) 1628 goto nomem; 1629 memset(sky2->rx_le, 0, RX_LE_BYTES); 1630 1631 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1632 GFP_KERNEL); 1633 if (!sky2->rx_ring) 1634 goto nomem; 1635 1636 return sky2_alloc_rx_skbs(sky2); 1637 nomem: 1638 return -ENOMEM; 1639 } 1640 1641 static void sky2_free_buffers(struct sky2_port *sky2) 1642 { 1643 struct sky2_hw *hw = sky2->hw; 1644 1645 sky2_rx_clean(sky2); 1646 1647 if (sky2->rx_le) { 1648 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1649 sky2->rx_le, sky2->rx_le_map); 1650 sky2->rx_le = NULL; 1651 } 1652 if (sky2->tx_le) { 1653 pci_free_consistent(hw->pdev, 1654 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1655 sky2->tx_le, sky2->tx_le_map); 1656 sky2->tx_le = NULL; 1657 } 1658 kfree(sky2->tx_ring); 1659 kfree(sky2->rx_ring); 1660 1661 sky2->tx_ring = NULL; 1662 sky2->rx_ring = NULL; 1663 } 1664 1665 static void sky2_hw_up(struct sky2_port *sky2) 1666 { 1667 struct sky2_hw *hw = sky2->hw; 1668 unsigned port = sky2->port; 1669 u32 ramsize; 1670 int cap; 1671 struct net_device *otherdev = hw->dev[sky2->port^1]; 1672 1673 tx_init(sky2); 1674 1675 /* 1676 * On dual port PCI-X card, there is an problem where status 1677 * can be received out of order due to split transactions 1678 */ 1679 if (otherdev && netif_running(otherdev) && 1680 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1681 u16 cmd; 1682 1683 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1684 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1685 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1686 } 1687 1688 sky2_mac_init(hw, port); 1689 1690 /* Register is number of 4K blocks on internal RAM buffer. */ 1691 ramsize = sky2_read8(hw, B2_E_0) * 4; 1692 if (ramsize > 0) { 1693 u32 rxspace; 1694 1695 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1696 if (ramsize < 16) 1697 rxspace = ramsize / 2; 1698 else 1699 rxspace = 8 + (2*(ramsize - 16))/3; 1700 1701 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1702 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1703 1704 /* Make sure SyncQ is disabled */ 1705 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1706 RB_RST_SET); 1707 } 1708 1709 sky2_qset(hw, txqaddr[port]); 1710 1711 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1712 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1713 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1714 1715 /* Set almost empty threshold */ 1716 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1717 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1718 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1719 1720 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1721 sky2->tx_ring_size - 1); 1722 1723 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1724 netdev_update_features(sky2->netdev); 1725 1726 sky2_rx_start(sky2); 1727 } 1728 1729 /* Setup device IRQ and enable napi to process */ 1730 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1731 { 1732 struct pci_dev *pdev = hw->pdev; 1733 int err; 1734 1735 err = request_irq(pdev->irq, sky2_intr, 1736 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1737 name, hw); 1738 if (err) 1739 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1740 else { 1741 hw->flags |= SKY2_HW_IRQ_SETUP; 1742 1743 napi_enable(&hw->napi); 1744 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1745 sky2_read32(hw, B0_IMSK); 1746 } 1747 1748 return err; 1749 } 1750 1751 1752 /* Bring up network interface. */ 1753 static int sky2_open(struct net_device *dev) 1754 { 1755 struct sky2_port *sky2 = netdev_priv(dev); 1756 struct sky2_hw *hw = sky2->hw; 1757 unsigned port = sky2->port; 1758 u32 imask; 1759 int err; 1760 1761 netif_carrier_off(dev); 1762 1763 err = sky2_alloc_buffers(sky2); 1764 if (err) 1765 goto err_out; 1766 1767 /* With single port, IRQ is setup when device is brought up */ 1768 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1769 goto err_out; 1770 1771 sky2_hw_up(sky2); 1772 1773 /* Enable interrupts from phy/mac for port */ 1774 imask = sky2_read32(hw, B0_IMSK); 1775 1776 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1777 hw->chip_id == CHIP_ID_YUKON_PRM || 1778 hw->chip_id == CHIP_ID_YUKON_OP_2) 1779 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1780 1781 imask |= portirq_msk[port]; 1782 sky2_write32(hw, B0_IMSK, imask); 1783 sky2_read32(hw, B0_IMSK); 1784 1785 netif_info(sky2, ifup, dev, "enabling interface\n"); 1786 1787 return 0; 1788 1789 err_out: 1790 sky2_free_buffers(sky2); 1791 return err; 1792 } 1793 1794 /* Modular subtraction in ring */ 1795 static inline int tx_inuse(const struct sky2_port *sky2) 1796 { 1797 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1798 } 1799 1800 /* Number of list elements available for next tx */ 1801 static inline int tx_avail(const struct sky2_port *sky2) 1802 { 1803 return sky2->tx_pending - tx_inuse(sky2); 1804 } 1805 1806 /* Estimate of number of transmit list elements required */ 1807 static unsigned tx_le_req(const struct sk_buff *skb) 1808 { 1809 unsigned count; 1810 1811 count = (skb_shinfo(skb)->nr_frags + 1) 1812 * (sizeof(dma_addr_t) / sizeof(u32)); 1813 1814 if (skb_is_gso(skb)) 1815 ++count; 1816 else if (sizeof(dma_addr_t) == sizeof(u32)) 1817 ++count; /* possible vlan */ 1818 1819 if (skb->ip_summed == CHECKSUM_PARTIAL) 1820 ++count; 1821 1822 return count; 1823 } 1824 1825 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1826 { 1827 if (re->flags & TX_MAP_SINGLE) 1828 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1829 dma_unmap_len(re, maplen), 1830 PCI_DMA_TODEVICE); 1831 else if (re->flags & TX_MAP_PAGE) 1832 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1833 dma_unmap_len(re, maplen), 1834 PCI_DMA_TODEVICE); 1835 re->flags = 0; 1836 } 1837 1838 /* 1839 * Put one packet in ring for transmit. 1840 * A single packet can generate multiple list elements, and 1841 * the number of ring elements will probably be less than the number 1842 * of list elements used. 1843 */ 1844 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1845 struct net_device *dev) 1846 { 1847 struct sky2_port *sky2 = netdev_priv(dev); 1848 struct sky2_hw *hw = sky2->hw; 1849 struct sky2_tx_le *le = NULL; 1850 struct tx_ring_info *re; 1851 unsigned i, len; 1852 dma_addr_t mapping; 1853 u32 upper; 1854 u16 slot; 1855 u16 mss; 1856 u8 ctrl; 1857 1858 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1859 return NETDEV_TX_BUSY; 1860 1861 len = skb_headlen(skb); 1862 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1863 1864 if (pci_dma_mapping_error(hw->pdev, mapping)) 1865 goto mapping_error; 1866 1867 slot = sky2->tx_prod; 1868 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1869 "tx queued, slot %u, len %d\n", slot, skb->len); 1870 1871 /* Send high bits if needed */ 1872 upper = upper_32_bits(mapping); 1873 if (upper != sky2->tx_last_upper) { 1874 le = get_tx_le(sky2, &slot); 1875 le->addr = cpu_to_le32(upper); 1876 sky2->tx_last_upper = upper; 1877 le->opcode = OP_ADDR64 | HW_OWNER; 1878 } 1879 1880 /* Check for TCP Segmentation Offload */ 1881 mss = skb_shinfo(skb)->gso_size; 1882 if (mss != 0) { 1883 1884 if (!(hw->flags & SKY2_HW_NEW_LE)) 1885 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1886 1887 if (mss != sky2->tx_last_mss) { 1888 le = get_tx_le(sky2, &slot); 1889 le->addr = cpu_to_le32(mss); 1890 1891 if (hw->flags & SKY2_HW_NEW_LE) 1892 le->opcode = OP_MSS | HW_OWNER; 1893 else 1894 le->opcode = OP_LRGLEN | HW_OWNER; 1895 sky2->tx_last_mss = mss; 1896 } 1897 } 1898 1899 ctrl = 0; 1900 1901 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1902 if (vlan_tx_tag_present(skb)) { 1903 if (!le) { 1904 le = get_tx_le(sky2, &slot); 1905 le->addr = 0; 1906 le->opcode = OP_VLAN|HW_OWNER; 1907 } else 1908 le->opcode |= OP_VLAN; 1909 le->length = cpu_to_be16(vlan_tx_tag_get(skb)); 1910 ctrl |= INS_VLAN; 1911 } 1912 1913 /* Handle TCP checksum offload */ 1914 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1915 /* On Yukon EX (some versions) encoding change. */ 1916 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1917 ctrl |= CALSUM; /* auto checksum */ 1918 else { 1919 const unsigned offset = skb_transport_offset(skb); 1920 u32 tcpsum; 1921 1922 tcpsum = offset << 16; /* sum start */ 1923 tcpsum |= offset + skb->csum_offset; /* sum write */ 1924 1925 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1926 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1927 ctrl |= UDPTCP; 1928 1929 if (tcpsum != sky2->tx_tcpsum) { 1930 sky2->tx_tcpsum = tcpsum; 1931 1932 le = get_tx_le(sky2, &slot); 1933 le->addr = cpu_to_le32(tcpsum); 1934 le->length = 0; /* initial checksum value */ 1935 le->ctrl = 1; /* one packet */ 1936 le->opcode = OP_TCPLISW | HW_OWNER; 1937 } 1938 } 1939 } 1940 1941 re = sky2->tx_ring + slot; 1942 re->flags = TX_MAP_SINGLE; 1943 dma_unmap_addr_set(re, mapaddr, mapping); 1944 dma_unmap_len_set(re, maplen, len); 1945 1946 le = get_tx_le(sky2, &slot); 1947 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1948 le->length = cpu_to_le16(len); 1949 le->ctrl = ctrl; 1950 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1951 1952 1953 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1954 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1955 1956 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1957 skb_frag_size(frag), DMA_TO_DEVICE); 1958 1959 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1960 goto mapping_unwind; 1961 1962 upper = upper_32_bits(mapping); 1963 if (upper != sky2->tx_last_upper) { 1964 le = get_tx_le(sky2, &slot); 1965 le->addr = cpu_to_le32(upper); 1966 sky2->tx_last_upper = upper; 1967 le->opcode = OP_ADDR64 | HW_OWNER; 1968 } 1969 1970 re = sky2->tx_ring + slot; 1971 re->flags = TX_MAP_PAGE; 1972 dma_unmap_addr_set(re, mapaddr, mapping); 1973 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1974 1975 le = get_tx_le(sky2, &slot); 1976 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1977 le->length = cpu_to_le16(skb_frag_size(frag)); 1978 le->ctrl = ctrl; 1979 le->opcode = OP_BUFFER | HW_OWNER; 1980 } 1981 1982 re->skb = skb; 1983 le->ctrl |= EOP; 1984 1985 sky2->tx_prod = slot; 1986 1987 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1988 netif_stop_queue(dev); 1989 1990 netdev_sent_queue(dev, skb->len); 1991 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1992 1993 return NETDEV_TX_OK; 1994 1995 mapping_unwind: 1996 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1997 re = sky2->tx_ring + i; 1998 1999 sky2_tx_unmap(hw->pdev, re); 2000 } 2001 2002 mapping_error: 2003 if (net_ratelimit()) 2004 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2005 dev_kfree_skb_any(skb); 2006 return NETDEV_TX_OK; 2007 } 2008 2009 /* 2010 * Free ring elements from starting at tx_cons until "done" 2011 * 2012 * NB: 2013 * 1. The hardware will tell us about partial completion of multi-part 2014 * buffers so make sure not to free skb to early. 2015 * 2. This may run in parallel start_xmit because the it only 2016 * looks at the tail of the queue of FIFO (tx_cons), not 2017 * the head (tx_prod) 2018 */ 2019 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2020 { 2021 struct net_device *dev = sky2->netdev; 2022 u16 idx; 2023 unsigned int bytes_compl = 0, pkts_compl = 0; 2024 2025 BUG_ON(done >= sky2->tx_ring_size); 2026 2027 for (idx = sky2->tx_cons; idx != done; 2028 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2029 struct tx_ring_info *re = sky2->tx_ring + idx; 2030 struct sk_buff *skb = re->skb; 2031 2032 sky2_tx_unmap(sky2->hw->pdev, re); 2033 2034 if (skb) { 2035 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2036 "tx done %u\n", idx); 2037 2038 pkts_compl++; 2039 bytes_compl += skb->len; 2040 2041 re->skb = NULL; 2042 dev_kfree_skb_any(skb); 2043 2044 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2045 } 2046 } 2047 2048 sky2->tx_cons = idx; 2049 smp_mb(); 2050 2051 netdev_completed_queue(dev, pkts_compl, bytes_compl); 2052 2053 u64_stats_update_begin(&sky2->tx_stats.syncp); 2054 sky2->tx_stats.packets += pkts_compl; 2055 sky2->tx_stats.bytes += bytes_compl; 2056 u64_stats_update_end(&sky2->tx_stats.syncp); 2057 } 2058 2059 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2060 { 2061 /* Disable Force Sync bit and Enable Alloc bit */ 2062 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2063 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2064 2065 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2066 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2067 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2068 2069 /* Reset the PCI FIFO of the async Tx queue */ 2070 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2071 BMU_RST_SET | BMU_FIFO_RST); 2072 2073 /* Reset the Tx prefetch units */ 2074 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2075 PREF_UNIT_RST_SET); 2076 2077 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2078 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2079 2080 sky2_read32(hw, B0_CTST); 2081 } 2082 2083 static void sky2_hw_down(struct sky2_port *sky2) 2084 { 2085 struct sky2_hw *hw = sky2->hw; 2086 unsigned port = sky2->port; 2087 u16 ctrl; 2088 2089 /* Force flow control off */ 2090 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2091 2092 /* Stop transmitter */ 2093 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2094 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2095 2096 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2097 RB_RST_SET | RB_DIS_OP_MD); 2098 2099 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2100 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2101 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2102 2103 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2104 2105 /* Workaround shared GMAC reset */ 2106 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2107 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2108 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2109 2110 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2111 2112 /* Force any delayed status interrupt and NAPI */ 2113 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2114 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2115 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2116 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2117 2118 sky2_rx_stop(sky2); 2119 2120 spin_lock_bh(&sky2->phy_lock); 2121 sky2_phy_power_down(hw, port); 2122 spin_unlock_bh(&sky2->phy_lock); 2123 2124 sky2_tx_reset(hw, port); 2125 2126 /* Free any pending frames stuck in HW queue */ 2127 sky2_tx_complete(sky2, sky2->tx_prod); 2128 } 2129 2130 /* Network shutdown */ 2131 static int sky2_close(struct net_device *dev) 2132 { 2133 struct sky2_port *sky2 = netdev_priv(dev); 2134 struct sky2_hw *hw = sky2->hw; 2135 2136 /* Never really got started! */ 2137 if (!sky2->tx_le) 2138 return 0; 2139 2140 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2141 2142 if (hw->ports == 1) { 2143 sky2_write32(hw, B0_IMSK, 0); 2144 sky2_read32(hw, B0_IMSK); 2145 2146 napi_disable(&hw->napi); 2147 free_irq(hw->pdev->irq, hw); 2148 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2149 } else { 2150 u32 imask; 2151 2152 /* Disable port IRQ */ 2153 imask = sky2_read32(hw, B0_IMSK); 2154 imask &= ~portirq_msk[sky2->port]; 2155 sky2_write32(hw, B0_IMSK, imask); 2156 sky2_read32(hw, B0_IMSK); 2157 2158 synchronize_irq(hw->pdev->irq); 2159 napi_synchronize(&hw->napi); 2160 } 2161 2162 sky2_hw_down(sky2); 2163 2164 sky2_free_buffers(sky2); 2165 2166 return 0; 2167 } 2168 2169 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2170 { 2171 if (hw->flags & SKY2_HW_FIBRE_PHY) 2172 return SPEED_1000; 2173 2174 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2175 if (aux & PHY_M_PS_SPEED_100) 2176 return SPEED_100; 2177 else 2178 return SPEED_10; 2179 } 2180 2181 switch (aux & PHY_M_PS_SPEED_MSK) { 2182 case PHY_M_PS_SPEED_1000: 2183 return SPEED_1000; 2184 case PHY_M_PS_SPEED_100: 2185 return SPEED_100; 2186 default: 2187 return SPEED_10; 2188 } 2189 } 2190 2191 static void sky2_link_up(struct sky2_port *sky2) 2192 { 2193 struct sky2_hw *hw = sky2->hw; 2194 unsigned port = sky2->port; 2195 static const char *fc_name[] = { 2196 [FC_NONE] = "none", 2197 [FC_TX] = "tx", 2198 [FC_RX] = "rx", 2199 [FC_BOTH] = "both", 2200 }; 2201 2202 sky2_set_ipg(sky2); 2203 2204 sky2_enable_rx_tx(sky2); 2205 2206 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2207 2208 netif_carrier_on(sky2->netdev); 2209 2210 mod_timer(&hw->watchdog_timer, jiffies + 1); 2211 2212 /* Turn on link LED */ 2213 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2214 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2215 2216 netif_info(sky2, link, sky2->netdev, 2217 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2218 sky2->speed, 2219 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2220 fc_name[sky2->flow_status]); 2221 } 2222 2223 static void sky2_link_down(struct sky2_port *sky2) 2224 { 2225 struct sky2_hw *hw = sky2->hw; 2226 unsigned port = sky2->port; 2227 u16 reg; 2228 2229 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2230 2231 reg = gma_read16(hw, port, GM_GP_CTRL); 2232 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2233 gma_write16(hw, port, GM_GP_CTRL, reg); 2234 2235 netif_carrier_off(sky2->netdev); 2236 2237 /* Turn off link LED */ 2238 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2239 2240 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2241 2242 sky2_phy_init(hw, port); 2243 } 2244 2245 static enum flow_control sky2_flow(int rx, int tx) 2246 { 2247 if (rx) 2248 return tx ? FC_BOTH : FC_RX; 2249 else 2250 return tx ? FC_TX : FC_NONE; 2251 } 2252 2253 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2254 { 2255 struct sky2_hw *hw = sky2->hw; 2256 unsigned port = sky2->port; 2257 u16 advert, lpa; 2258 2259 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2260 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2261 if (lpa & PHY_M_AN_RF) { 2262 netdev_err(sky2->netdev, "remote fault\n"); 2263 return -1; 2264 } 2265 2266 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2267 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2268 return -1; 2269 } 2270 2271 sky2->speed = sky2_phy_speed(hw, aux); 2272 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2273 2274 /* Since the pause result bits seem to in different positions on 2275 * different chips. look at registers. 2276 */ 2277 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2278 /* Shift for bits in fiber PHY */ 2279 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2280 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2281 2282 if (advert & ADVERTISE_1000XPAUSE) 2283 advert |= ADVERTISE_PAUSE_CAP; 2284 if (advert & ADVERTISE_1000XPSE_ASYM) 2285 advert |= ADVERTISE_PAUSE_ASYM; 2286 if (lpa & LPA_1000XPAUSE) 2287 lpa |= LPA_PAUSE_CAP; 2288 if (lpa & LPA_1000XPAUSE_ASYM) 2289 lpa |= LPA_PAUSE_ASYM; 2290 } 2291 2292 sky2->flow_status = FC_NONE; 2293 if (advert & ADVERTISE_PAUSE_CAP) { 2294 if (lpa & LPA_PAUSE_CAP) 2295 sky2->flow_status = FC_BOTH; 2296 else if (advert & ADVERTISE_PAUSE_ASYM) 2297 sky2->flow_status = FC_RX; 2298 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2299 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2300 sky2->flow_status = FC_TX; 2301 } 2302 2303 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2304 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2305 sky2->flow_status = FC_NONE; 2306 2307 if (sky2->flow_status & FC_TX) 2308 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2309 else 2310 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2311 2312 return 0; 2313 } 2314 2315 /* Interrupt from PHY */ 2316 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2317 { 2318 struct net_device *dev = hw->dev[port]; 2319 struct sky2_port *sky2 = netdev_priv(dev); 2320 u16 istatus, phystat; 2321 2322 if (!netif_running(dev)) 2323 return; 2324 2325 spin_lock(&sky2->phy_lock); 2326 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2327 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2328 2329 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2330 istatus, phystat); 2331 2332 if (istatus & PHY_M_IS_AN_COMPL) { 2333 if (sky2_autoneg_done(sky2, phystat) == 0 && 2334 !netif_carrier_ok(dev)) 2335 sky2_link_up(sky2); 2336 goto out; 2337 } 2338 2339 if (istatus & PHY_M_IS_LSP_CHANGE) 2340 sky2->speed = sky2_phy_speed(hw, phystat); 2341 2342 if (istatus & PHY_M_IS_DUP_CHANGE) 2343 sky2->duplex = 2344 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2345 2346 if (istatus & PHY_M_IS_LST_CHANGE) { 2347 if (phystat & PHY_M_PS_LINK_UP) 2348 sky2_link_up(sky2); 2349 else 2350 sky2_link_down(sky2); 2351 } 2352 out: 2353 spin_unlock(&sky2->phy_lock); 2354 } 2355 2356 /* Special quick link interrupt (Yukon-2 Optima only) */ 2357 static void sky2_qlink_intr(struct sky2_hw *hw) 2358 { 2359 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2360 u32 imask; 2361 u16 phy; 2362 2363 /* disable irq */ 2364 imask = sky2_read32(hw, B0_IMSK); 2365 imask &= ~Y2_IS_PHY_QLNK; 2366 sky2_write32(hw, B0_IMSK, imask); 2367 2368 /* reset PHY Link Detect */ 2369 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2370 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2371 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2372 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2373 2374 sky2_link_up(sky2); 2375 } 2376 2377 /* Transmit timeout is only called if we are running, carrier is up 2378 * and tx queue is full (stopped). 2379 */ 2380 static void sky2_tx_timeout(struct net_device *dev) 2381 { 2382 struct sky2_port *sky2 = netdev_priv(dev); 2383 struct sky2_hw *hw = sky2->hw; 2384 2385 netif_err(sky2, timer, dev, "tx timeout\n"); 2386 2387 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2388 sky2->tx_cons, sky2->tx_prod, 2389 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2390 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2391 2392 /* can't restart safely under softirq */ 2393 schedule_work(&hw->restart_work); 2394 } 2395 2396 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2397 { 2398 struct sky2_port *sky2 = netdev_priv(dev); 2399 struct sky2_hw *hw = sky2->hw; 2400 unsigned port = sky2->port; 2401 int err; 2402 u16 ctl, mode; 2403 u32 imask; 2404 2405 /* MTU size outside the spec */ 2406 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) 2407 return -EINVAL; 2408 2409 /* MTU > 1500 on yukon FE and FE+ not allowed */ 2410 if (new_mtu > ETH_DATA_LEN && 2411 (hw->chip_id == CHIP_ID_YUKON_FE || 2412 hw->chip_id == CHIP_ID_YUKON_FE_P)) 2413 return -EINVAL; 2414 2415 if (!netif_running(dev)) { 2416 dev->mtu = new_mtu; 2417 netdev_update_features(dev); 2418 return 0; 2419 } 2420 2421 imask = sky2_read32(hw, B0_IMSK); 2422 sky2_write32(hw, B0_IMSK, 0); 2423 2424 dev->trans_start = jiffies; /* prevent tx timeout */ 2425 napi_disable(&hw->napi); 2426 netif_tx_disable(dev); 2427 2428 synchronize_irq(hw->pdev->irq); 2429 2430 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2431 sky2_set_tx_stfwd(hw, port); 2432 2433 ctl = gma_read16(hw, port, GM_GP_CTRL); 2434 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2435 sky2_rx_stop(sky2); 2436 sky2_rx_clean(sky2); 2437 2438 dev->mtu = new_mtu; 2439 netdev_update_features(dev); 2440 2441 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2442 if (sky2->speed > SPEED_100) 2443 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2444 else 2445 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2446 2447 if (dev->mtu > ETH_DATA_LEN) 2448 mode |= GM_SMOD_JUMBO_ENA; 2449 2450 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2451 2452 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2453 2454 err = sky2_alloc_rx_skbs(sky2); 2455 if (!err) 2456 sky2_rx_start(sky2); 2457 else 2458 sky2_rx_clean(sky2); 2459 sky2_write32(hw, B0_IMSK, imask); 2460 2461 sky2_read32(hw, B0_Y2_SP_LISR); 2462 napi_enable(&hw->napi); 2463 2464 if (err) 2465 dev_close(dev); 2466 else { 2467 gma_write16(hw, port, GM_GP_CTRL, ctl); 2468 2469 netif_wake_queue(dev); 2470 } 2471 2472 return err; 2473 } 2474 2475 static inline bool needs_copy(const struct rx_ring_info *re, 2476 unsigned length) 2477 { 2478 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2479 /* Some architectures need the IP header to be aligned */ 2480 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) 2481 return true; 2482 #endif 2483 return length < copybreak; 2484 } 2485 2486 /* For small just reuse existing skb for next receive */ 2487 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2488 const struct rx_ring_info *re, 2489 unsigned length) 2490 { 2491 struct sk_buff *skb; 2492 2493 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2494 if (likely(skb)) { 2495 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2496 length, PCI_DMA_FROMDEVICE); 2497 skb_copy_from_linear_data(re->skb, skb->data, length); 2498 skb->ip_summed = re->skb->ip_summed; 2499 skb->csum = re->skb->csum; 2500 skb_copy_hash(skb, re->skb); 2501 skb->vlan_proto = re->skb->vlan_proto; 2502 skb->vlan_tci = re->skb->vlan_tci; 2503 2504 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2505 length, PCI_DMA_FROMDEVICE); 2506 re->skb->vlan_proto = 0; 2507 re->skb->vlan_tci = 0; 2508 skb_clear_hash(re->skb); 2509 re->skb->ip_summed = CHECKSUM_NONE; 2510 skb_put(skb, length); 2511 } 2512 return skb; 2513 } 2514 2515 /* Adjust length of skb with fragments to match received data */ 2516 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2517 unsigned int length) 2518 { 2519 int i, num_frags; 2520 unsigned int size; 2521 2522 /* put header into skb */ 2523 size = min(length, hdr_space); 2524 skb->tail += size; 2525 skb->len += size; 2526 length -= size; 2527 2528 num_frags = skb_shinfo(skb)->nr_frags; 2529 for (i = 0; i < num_frags; i++) { 2530 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2531 2532 if (length == 0) { 2533 /* don't need this page */ 2534 __skb_frag_unref(frag); 2535 --skb_shinfo(skb)->nr_frags; 2536 } else { 2537 size = min(length, (unsigned) PAGE_SIZE); 2538 2539 skb_frag_size_set(frag, size); 2540 skb->data_len += size; 2541 skb->truesize += PAGE_SIZE; 2542 skb->len += size; 2543 length -= size; 2544 } 2545 } 2546 } 2547 2548 /* Normal packet - take skb from ring element and put in a new one */ 2549 static struct sk_buff *receive_new(struct sky2_port *sky2, 2550 struct rx_ring_info *re, 2551 unsigned int length) 2552 { 2553 struct sk_buff *skb; 2554 struct rx_ring_info nre; 2555 unsigned hdr_space = sky2->rx_data_size; 2556 2557 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2558 if (unlikely(!nre.skb)) 2559 goto nobuf; 2560 2561 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2562 goto nomap; 2563 2564 skb = re->skb; 2565 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2566 prefetch(skb->data); 2567 *re = nre; 2568 2569 if (skb_shinfo(skb)->nr_frags) 2570 skb_put_frags(skb, hdr_space, length); 2571 else 2572 skb_put(skb, length); 2573 return skb; 2574 2575 nomap: 2576 dev_kfree_skb(nre.skb); 2577 nobuf: 2578 return NULL; 2579 } 2580 2581 /* 2582 * Receive one packet. 2583 * For larger packets, get new buffer. 2584 */ 2585 static struct sk_buff *sky2_receive(struct net_device *dev, 2586 u16 length, u32 status) 2587 { 2588 struct sky2_port *sky2 = netdev_priv(dev); 2589 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2590 struct sk_buff *skb = NULL; 2591 u16 count = (status & GMR_FS_LEN) >> 16; 2592 2593 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2594 "rx slot %u status 0x%x len %d\n", 2595 sky2->rx_next, status, length); 2596 2597 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2598 prefetch(sky2->rx_ring + sky2->rx_next); 2599 2600 if (vlan_tx_tag_present(re->skb)) 2601 count -= VLAN_HLEN; /* Account for vlan tag */ 2602 2603 /* This chip has hardware problems that generates bogus status. 2604 * So do only marginal checking and expect higher level protocols 2605 * to handle crap frames. 2606 */ 2607 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2608 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2609 length != count) 2610 goto okay; 2611 2612 if (status & GMR_FS_ANY_ERR) 2613 goto error; 2614 2615 if (!(status & GMR_FS_RX_OK)) 2616 goto resubmit; 2617 2618 /* if length reported by DMA does not match PHY, packet was truncated */ 2619 if (length != count) 2620 goto error; 2621 2622 okay: 2623 if (needs_copy(re, length)) 2624 skb = receive_copy(sky2, re, length); 2625 else 2626 skb = receive_new(sky2, re, length); 2627 2628 dev->stats.rx_dropped += (skb == NULL); 2629 2630 resubmit: 2631 sky2_rx_submit(sky2, re); 2632 2633 return skb; 2634 2635 error: 2636 ++dev->stats.rx_errors; 2637 2638 if (net_ratelimit()) 2639 netif_info(sky2, rx_err, dev, 2640 "rx error, status 0x%x length %d\n", status, length); 2641 2642 goto resubmit; 2643 } 2644 2645 /* Transmit complete */ 2646 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2647 { 2648 struct sky2_port *sky2 = netdev_priv(dev); 2649 2650 if (netif_running(dev)) { 2651 sky2_tx_complete(sky2, last); 2652 2653 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2654 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2655 netif_wake_queue(dev); 2656 } 2657 } 2658 2659 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2660 struct sk_buff *skb) 2661 { 2662 if (skb->ip_summed == CHECKSUM_NONE) 2663 netif_receive_skb(skb); 2664 else 2665 napi_gro_receive(&sky2->hw->napi, skb); 2666 } 2667 2668 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2669 unsigned packets, unsigned bytes) 2670 { 2671 struct net_device *dev = hw->dev[port]; 2672 struct sky2_port *sky2 = netdev_priv(dev); 2673 2674 if (packets == 0) 2675 return; 2676 2677 u64_stats_update_begin(&sky2->rx_stats.syncp); 2678 sky2->rx_stats.packets += packets; 2679 sky2->rx_stats.bytes += bytes; 2680 u64_stats_update_end(&sky2->rx_stats.syncp); 2681 2682 dev->last_rx = jiffies; 2683 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2684 } 2685 2686 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2687 { 2688 /* If this happens then driver assuming wrong format for chip type */ 2689 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2690 2691 /* Both checksum counters are programmed to start at 2692 * the same offset, so unless there is a problem they 2693 * should match. This failure is an early indication that 2694 * hardware receive checksumming won't work. 2695 */ 2696 if (likely((u16)(status >> 16) == (u16)status)) { 2697 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2698 skb->ip_summed = CHECKSUM_COMPLETE; 2699 skb->csum = le16_to_cpu(status); 2700 } else { 2701 dev_notice(&sky2->hw->pdev->dev, 2702 "%s: receive checksum problem (status = %#x)\n", 2703 sky2->netdev->name, status); 2704 2705 /* Disable checksum offload 2706 * It will be reenabled on next ndo_set_features, but if it's 2707 * really broken, will get disabled again 2708 */ 2709 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2710 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2711 BMU_DIS_RX_CHKSUM); 2712 } 2713 } 2714 2715 static void sky2_rx_tag(struct sky2_port *sky2, u16 length) 2716 { 2717 struct sk_buff *skb; 2718 2719 skb = sky2->rx_ring[sky2->rx_next].skb; 2720 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length)); 2721 } 2722 2723 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2724 { 2725 struct sk_buff *skb; 2726 2727 skb = sky2->rx_ring[sky2->rx_next].skb; 2728 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3); 2729 } 2730 2731 /* Process status response ring */ 2732 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2733 { 2734 int work_done = 0; 2735 unsigned int total_bytes[2] = { 0 }; 2736 unsigned int total_packets[2] = { 0 }; 2737 2738 if (to_do <= 0) 2739 return work_done; 2740 2741 rmb(); 2742 do { 2743 struct sky2_port *sky2; 2744 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2745 unsigned port; 2746 struct net_device *dev; 2747 struct sk_buff *skb; 2748 u32 status; 2749 u16 length; 2750 u8 opcode = le->opcode; 2751 2752 if (!(opcode & HW_OWNER)) 2753 break; 2754 2755 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2756 2757 port = le->css & CSS_LINK_BIT; 2758 dev = hw->dev[port]; 2759 sky2 = netdev_priv(dev); 2760 length = le16_to_cpu(le->length); 2761 status = le32_to_cpu(le->status); 2762 2763 le->opcode = 0; 2764 switch (opcode & ~HW_OWNER) { 2765 case OP_RXSTAT: 2766 total_packets[port]++; 2767 total_bytes[port] += length; 2768 2769 skb = sky2_receive(dev, length, status); 2770 if (!skb) 2771 break; 2772 2773 /* This chip reports checksum status differently */ 2774 if (hw->flags & SKY2_HW_NEW_LE) { 2775 if ((dev->features & NETIF_F_RXCSUM) && 2776 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2777 (le->css & CSS_TCPUDPCSOK)) 2778 skb->ip_summed = CHECKSUM_UNNECESSARY; 2779 else 2780 skb->ip_summed = CHECKSUM_NONE; 2781 } 2782 2783 skb->protocol = eth_type_trans(skb, dev); 2784 sky2_skb_rx(sky2, skb); 2785 2786 /* Stop after net poll weight */ 2787 if (++work_done >= to_do) 2788 goto exit_loop; 2789 break; 2790 2791 case OP_RXVLAN: 2792 sky2_rx_tag(sky2, length); 2793 break; 2794 2795 case OP_RXCHKSVLAN: 2796 sky2_rx_tag(sky2, length); 2797 /* fall through */ 2798 case OP_RXCHKS: 2799 if (likely(dev->features & NETIF_F_RXCSUM)) 2800 sky2_rx_checksum(sky2, status); 2801 break; 2802 2803 case OP_RSS_HASH: 2804 sky2_rx_hash(sky2, status); 2805 break; 2806 2807 case OP_TXINDEXLE: 2808 /* TX index reports status for both ports */ 2809 sky2_tx_done(hw->dev[0], status & 0xfff); 2810 if (hw->dev[1]) 2811 sky2_tx_done(hw->dev[1], 2812 ((status >> 24) & 0xff) 2813 | (u16)(length & 0xf) << 8); 2814 break; 2815 2816 default: 2817 if (net_ratelimit()) 2818 pr_warning("unknown status opcode 0x%x\n", opcode); 2819 } 2820 } while (hw->st_idx != idx); 2821 2822 /* Fully processed status ring so clear irq */ 2823 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2824 2825 exit_loop: 2826 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2827 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2828 2829 return work_done; 2830 } 2831 2832 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2833 { 2834 struct net_device *dev = hw->dev[port]; 2835 2836 if (net_ratelimit()) 2837 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2838 2839 if (status & Y2_IS_PAR_RD1) { 2840 if (net_ratelimit()) 2841 netdev_err(dev, "ram data read parity error\n"); 2842 /* Clear IRQ */ 2843 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2844 } 2845 2846 if (status & Y2_IS_PAR_WR1) { 2847 if (net_ratelimit()) 2848 netdev_err(dev, "ram data write parity error\n"); 2849 2850 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2851 } 2852 2853 if (status & Y2_IS_PAR_MAC1) { 2854 if (net_ratelimit()) 2855 netdev_err(dev, "MAC parity error\n"); 2856 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2857 } 2858 2859 if (status & Y2_IS_PAR_RX1) { 2860 if (net_ratelimit()) 2861 netdev_err(dev, "RX parity error\n"); 2862 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2863 } 2864 2865 if (status & Y2_IS_TCP_TXA1) { 2866 if (net_ratelimit()) 2867 netdev_err(dev, "TCP segmentation error\n"); 2868 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2869 } 2870 } 2871 2872 static void sky2_hw_intr(struct sky2_hw *hw) 2873 { 2874 struct pci_dev *pdev = hw->pdev; 2875 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2876 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2877 2878 status &= hwmsk; 2879 2880 if (status & Y2_IS_TIST_OV) 2881 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2882 2883 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2884 u16 pci_err; 2885 2886 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2887 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2888 if (net_ratelimit()) 2889 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2890 pci_err); 2891 2892 sky2_pci_write16(hw, PCI_STATUS, 2893 pci_err | PCI_STATUS_ERROR_BITS); 2894 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2895 } 2896 2897 if (status & Y2_IS_PCI_EXP) { 2898 /* PCI-Express uncorrectable Error occurred */ 2899 u32 err; 2900 2901 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2902 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2903 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2904 0xfffffffful); 2905 if (net_ratelimit()) 2906 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2907 2908 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2909 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2910 } 2911 2912 if (status & Y2_HWE_L1_MASK) 2913 sky2_hw_error(hw, 0, status); 2914 status >>= 8; 2915 if (status & Y2_HWE_L1_MASK) 2916 sky2_hw_error(hw, 1, status); 2917 } 2918 2919 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2920 { 2921 struct net_device *dev = hw->dev[port]; 2922 struct sky2_port *sky2 = netdev_priv(dev); 2923 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2924 2925 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2926 2927 if (status & GM_IS_RX_CO_OV) 2928 gma_read16(hw, port, GM_RX_IRQ_SRC); 2929 2930 if (status & GM_IS_TX_CO_OV) 2931 gma_read16(hw, port, GM_TX_IRQ_SRC); 2932 2933 if (status & GM_IS_RX_FF_OR) { 2934 ++dev->stats.rx_fifo_errors; 2935 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2936 } 2937 2938 if (status & GM_IS_TX_FF_UR) { 2939 ++dev->stats.tx_fifo_errors; 2940 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2941 } 2942 } 2943 2944 /* This should never happen it is a bug. */ 2945 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2946 { 2947 struct net_device *dev = hw->dev[port]; 2948 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2949 2950 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2951 dev->name, (unsigned) q, (unsigned) idx, 2952 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2953 2954 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2955 } 2956 2957 static int sky2_rx_hung(struct net_device *dev) 2958 { 2959 struct sky2_port *sky2 = netdev_priv(dev); 2960 struct sky2_hw *hw = sky2->hw; 2961 unsigned port = sky2->port; 2962 unsigned rxq = rxqaddr[port]; 2963 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2964 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2965 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2966 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2967 2968 /* If idle and MAC or PCI is stuck */ 2969 if (sky2->check.last == dev->last_rx && 2970 ((mac_rp == sky2->check.mac_rp && 2971 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2972 /* Check if the PCI RX hang */ 2973 (fifo_rp == sky2->check.fifo_rp && 2974 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2975 netdev_printk(KERN_DEBUG, dev, 2976 "hung mac %d:%d fifo %d (%d:%d)\n", 2977 mac_lev, mac_rp, fifo_lev, 2978 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2979 return 1; 2980 } else { 2981 sky2->check.last = dev->last_rx; 2982 sky2->check.mac_rp = mac_rp; 2983 sky2->check.mac_lev = mac_lev; 2984 sky2->check.fifo_rp = fifo_rp; 2985 sky2->check.fifo_lev = fifo_lev; 2986 return 0; 2987 } 2988 } 2989 2990 static void sky2_watchdog(unsigned long arg) 2991 { 2992 struct sky2_hw *hw = (struct sky2_hw *) arg; 2993 2994 /* Check for lost IRQ once a second */ 2995 if (sky2_read32(hw, B0_ISRC)) { 2996 napi_schedule(&hw->napi); 2997 } else { 2998 int i, active = 0; 2999 3000 for (i = 0; i < hw->ports; i++) { 3001 struct net_device *dev = hw->dev[i]; 3002 if (!netif_running(dev)) 3003 continue; 3004 ++active; 3005 3006 /* For chips with Rx FIFO, check if stuck */ 3007 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 3008 sky2_rx_hung(dev)) { 3009 netdev_info(dev, "receiver hang detected\n"); 3010 schedule_work(&hw->restart_work); 3011 return; 3012 } 3013 } 3014 3015 if (active == 0) 3016 return; 3017 } 3018 3019 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 3020 } 3021 3022 /* Hardware/software error handling */ 3023 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 3024 { 3025 if (net_ratelimit()) 3026 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 3027 3028 if (status & Y2_IS_HW_ERR) 3029 sky2_hw_intr(hw); 3030 3031 if (status & Y2_IS_IRQ_MAC1) 3032 sky2_mac_intr(hw, 0); 3033 3034 if (status & Y2_IS_IRQ_MAC2) 3035 sky2_mac_intr(hw, 1); 3036 3037 if (status & Y2_IS_CHK_RX1) 3038 sky2_le_error(hw, 0, Q_R1); 3039 3040 if (status & Y2_IS_CHK_RX2) 3041 sky2_le_error(hw, 1, Q_R2); 3042 3043 if (status & Y2_IS_CHK_TXA1) 3044 sky2_le_error(hw, 0, Q_XA1); 3045 3046 if (status & Y2_IS_CHK_TXA2) 3047 sky2_le_error(hw, 1, Q_XA2); 3048 } 3049 3050 static int sky2_poll(struct napi_struct *napi, int work_limit) 3051 { 3052 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3053 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3054 int work_done = 0; 3055 u16 idx; 3056 3057 if (unlikely(status & Y2_IS_ERROR)) 3058 sky2_err_intr(hw, status); 3059 3060 if (status & Y2_IS_IRQ_PHY1) 3061 sky2_phy_intr(hw, 0); 3062 3063 if (status & Y2_IS_IRQ_PHY2) 3064 sky2_phy_intr(hw, 1); 3065 3066 if (status & Y2_IS_PHY_QLNK) 3067 sky2_qlink_intr(hw); 3068 3069 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3070 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3071 3072 if (work_done >= work_limit) 3073 goto done; 3074 } 3075 3076 napi_complete(napi); 3077 sky2_read32(hw, B0_Y2_SP_LISR); 3078 done: 3079 3080 return work_done; 3081 } 3082 3083 static irqreturn_t sky2_intr(int irq, void *dev_id) 3084 { 3085 struct sky2_hw *hw = dev_id; 3086 u32 status; 3087 3088 /* Reading this mask interrupts as side effect */ 3089 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3090 if (status == 0 || status == ~0) { 3091 sky2_write32(hw, B0_Y2_SP_ICR, 2); 3092 return IRQ_NONE; 3093 } 3094 3095 prefetch(&hw->st_le[hw->st_idx]); 3096 3097 napi_schedule(&hw->napi); 3098 3099 return IRQ_HANDLED; 3100 } 3101 3102 #ifdef CONFIG_NET_POLL_CONTROLLER 3103 static void sky2_netpoll(struct net_device *dev) 3104 { 3105 struct sky2_port *sky2 = netdev_priv(dev); 3106 3107 napi_schedule(&sky2->hw->napi); 3108 } 3109 #endif 3110 3111 /* Chip internal frequency for clock calculations */ 3112 static u32 sky2_mhz(const struct sky2_hw *hw) 3113 { 3114 switch (hw->chip_id) { 3115 case CHIP_ID_YUKON_EC: 3116 case CHIP_ID_YUKON_EC_U: 3117 case CHIP_ID_YUKON_EX: 3118 case CHIP_ID_YUKON_SUPR: 3119 case CHIP_ID_YUKON_UL_2: 3120 case CHIP_ID_YUKON_OPT: 3121 case CHIP_ID_YUKON_PRM: 3122 case CHIP_ID_YUKON_OP_2: 3123 return 125; 3124 3125 case CHIP_ID_YUKON_FE: 3126 return 100; 3127 3128 case CHIP_ID_YUKON_FE_P: 3129 return 50; 3130 3131 case CHIP_ID_YUKON_XL: 3132 return 156; 3133 3134 default: 3135 BUG(); 3136 } 3137 } 3138 3139 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3140 { 3141 return sky2_mhz(hw) * us; 3142 } 3143 3144 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3145 { 3146 return clk / sky2_mhz(hw); 3147 } 3148 3149 3150 static int sky2_init(struct sky2_hw *hw) 3151 { 3152 u8 t8; 3153 3154 /* Enable all clocks and check for bad PCI access */ 3155 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3156 3157 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3158 3159 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3160 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3161 3162 switch (hw->chip_id) { 3163 case CHIP_ID_YUKON_XL: 3164 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3165 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3166 hw->flags |= SKY2_HW_RSS_BROKEN; 3167 break; 3168 3169 case CHIP_ID_YUKON_EC_U: 3170 hw->flags = SKY2_HW_GIGABIT 3171 | SKY2_HW_NEWER_PHY 3172 | SKY2_HW_ADV_POWER_CTL; 3173 break; 3174 3175 case CHIP_ID_YUKON_EX: 3176 hw->flags = SKY2_HW_GIGABIT 3177 | SKY2_HW_NEWER_PHY 3178 | SKY2_HW_NEW_LE 3179 | SKY2_HW_ADV_POWER_CTL 3180 | SKY2_HW_RSS_CHKSUM; 3181 3182 /* New transmit checksum */ 3183 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3184 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3185 break; 3186 3187 case CHIP_ID_YUKON_EC: 3188 /* This rev is really old, and requires untested workarounds */ 3189 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3190 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3191 return -EOPNOTSUPP; 3192 } 3193 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3194 break; 3195 3196 case CHIP_ID_YUKON_FE: 3197 hw->flags = SKY2_HW_RSS_BROKEN; 3198 break; 3199 3200 case CHIP_ID_YUKON_FE_P: 3201 hw->flags = SKY2_HW_NEWER_PHY 3202 | SKY2_HW_NEW_LE 3203 | SKY2_HW_AUTO_TX_SUM 3204 | SKY2_HW_ADV_POWER_CTL; 3205 3206 /* The workaround for status conflicts VLAN tag detection. */ 3207 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3208 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3209 break; 3210 3211 case CHIP_ID_YUKON_SUPR: 3212 hw->flags = SKY2_HW_GIGABIT 3213 | SKY2_HW_NEWER_PHY 3214 | SKY2_HW_NEW_LE 3215 | SKY2_HW_AUTO_TX_SUM 3216 | SKY2_HW_ADV_POWER_CTL; 3217 3218 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3219 hw->flags |= SKY2_HW_RSS_CHKSUM; 3220 break; 3221 3222 case CHIP_ID_YUKON_UL_2: 3223 hw->flags = SKY2_HW_GIGABIT 3224 | SKY2_HW_ADV_POWER_CTL; 3225 break; 3226 3227 case CHIP_ID_YUKON_OPT: 3228 case CHIP_ID_YUKON_PRM: 3229 case CHIP_ID_YUKON_OP_2: 3230 hw->flags = SKY2_HW_GIGABIT 3231 | SKY2_HW_NEW_LE 3232 | SKY2_HW_ADV_POWER_CTL; 3233 break; 3234 3235 default: 3236 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3237 hw->chip_id); 3238 return -EOPNOTSUPP; 3239 } 3240 3241 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3242 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3243 hw->flags |= SKY2_HW_FIBRE_PHY; 3244 3245 hw->ports = 1; 3246 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3247 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3248 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3249 ++hw->ports; 3250 } 3251 3252 if (sky2_read8(hw, B2_E_0)) 3253 hw->flags |= SKY2_HW_RAM_BUFFER; 3254 3255 return 0; 3256 } 3257 3258 static void sky2_reset(struct sky2_hw *hw) 3259 { 3260 struct pci_dev *pdev = hw->pdev; 3261 u16 status; 3262 int i; 3263 u32 hwe_mask = Y2_HWE_ALL_MASK; 3264 3265 /* disable ASF */ 3266 if (hw->chip_id == CHIP_ID_YUKON_EX 3267 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3268 sky2_write32(hw, CPU_WDOG, 0); 3269 status = sky2_read16(hw, HCU_CCSR); 3270 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3271 HCU_CCSR_UC_STATE_MSK); 3272 /* 3273 * CPU clock divider shouldn't be used because 3274 * - ASF firmware may malfunction 3275 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3276 */ 3277 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3278 sky2_write16(hw, HCU_CCSR, status); 3279 sky2_write32(hw, CPU_WDOG, 0); 3280 } else 3281 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3282 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3283 3284 /* do a SW reset */ 3285 sky2_write8(hw, B0_CTST, CS_RST_SET); 3286 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3287 3288 /* allow writes to PCI config */ 3289 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3290 3291 /* clear PCI errors, if any */ 3292 status = sky2_pci_read16(hw, PCI_STATUS); 3293 status |= PCI_STATUS_ERROR_BITS; 3294 sky2_pci_write16(hw, PCI_STATUS, status); 3295 3296 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3297 3298 if (pci_is_pcie(pdev)) { 3299 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3300 0xfffffffful); 3301 3302 /* If error bit is stuck on ignore it */ 3303 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3304 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3305 else 3306 hwe_mask |= Y2_IS_PCI_EXP; 3307 } 3308 3309 sky2_power_on(hw); 3310 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3311 3312 for (i = 0; i < hw->ports; i++) { 3313 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3314 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3315 3316 if (hw->chip_id == CHIP_ID_YUKON_EX || 3317 hw->chip_id == CHIP_ID_YUKON_SUPR) 3318 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3319 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3320 | GMC_BYP_RETR_ON); 3321 3322 } 3323 3324 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3325 /* enable MACSec clock gating */ 3326 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3327 } 3328 3329 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3330 hw->chip_id == CHIP_ID_YUKON_PRM || 3331 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3332 u16 reg; 3333 3334 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3335 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3336 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3337 3338 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3339 reg = 10; 3340 3341 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3342 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3343 } else { 3344 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3345 reg = 3; 3346 } 3347 3348 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3349 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3350 3351 /* reset PHY Link Detect */ 3352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3353 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3354 3355 /* check if PSMv2 was running before */ 3356 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3357 if (reg & PCI_EXP_LNKCTL_ASPMC) 3358 /* restore the PCIe Link Control register */ 3359 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3360 reg); 3361 3362 if (hw->chip_id == CHIP_ID_YUKON_PRM && 3363 hw->chip_rev == CHIP_REV_YU_PRM_A0) { 3364 /* change PHY Interrupt polarity to low active */ 3365 reg = sky2_read16(hw, GPHY_CTRL); 3366 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); 3367 3368 /* adapt HW for low active PHY Interrupt */ 3369 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); 3370 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); 3371 } 3372 3373 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3374 3375 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3376 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3377 } 3378 3379 /* Clear I2C IRQ noise */ 3380 sky2_write32(hw, B2_I2C_IRQ, 1); 3381 3382 /* turn off hardware timer (unused) */ 3383 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3384 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3385 3386 /* Turn off descriptor polling */ 3387 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3388 3389 /* Turn off receive timestamp */ 3390 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3391 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3392 3393 /* enable the Tx Arbiters */ 3394 for (i = 0; i < hw->ports; i++) 3395 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3396 3397 /* Initialize ram interface */ 3398 for (i = 0; i < hw->ports; i++) { 3399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3400 3401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3402 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3410 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3411 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3412 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3413 } 3414 3415 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3416 3417 for (i = 0; i < hw->ports; i++) 3418 sky2_gmac_reset(hw, i); 3419 3420 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3421 hw->st_idx = 0; 3422 3423 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3424 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3425 3426 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3427 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3428 3429 /* Set the list last index */ 3430 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3431 3432 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3433 sky2_write8(hw, STAT_FIFO_WM, 16); 3434 3435 /* set Status-FIFO ISR watermark */ 3436 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3437 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3438 else 3439 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3440 3441 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3442 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3443 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3444 3445 /* enable status unit */ 3446 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3447 3448 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3449 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3450 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3451 } 3452 3453 /* Take device down (offline). 3454 * Equivalent to doing dev_stop() but this does not 3455 * inform upper layers of the transition. 3456 */ 3457 static void sky2_detach(struct net_device *dev) 3458 { 3459 if (netif_running(dev)) { 3460 netif_tx_lock(dev); 3461 netif_device_detach(dev); /* stop txq */ 3462 netif_tx_unlock(dev); 3463 sky2_close(dev); 3464 } 3465 } 3466 3467 /* Bring device back after doing sky2_detach */ 3468 static int sky2_reattach(struct net_device *dev) 3469 { 3470 int err = 0; 3471 3472 if (netif_running(dev)) { 3473 err = sky2_open(dev); 3474 if (err) { 3475 netdev_info(dev, "could not restart %d\n", err); 3476 dev_close(dev); 3477 } else { 3478 netif_device_attach(dev); 3479 sky2_set_multicast(dev); 3480 } 3481 } 3482 3483 return err; 3484 } 3485 3486 static void sky2_all_down(struct sky2_hw *hw) 3487 { 3488 int i; 3489 3490 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3491 sky2_read32(hw, B0_IMSK); 3492 sky2_write32(hw, B0_IMSK, 0); 3493 3494 synchronize_irq(hw->pdev->irq); 3495 napi_disable(&hw->napi); 3496 } 3497 3498 for (i = 0; i < hw->ports; i++) { 3499 struct net_device *dev = hw->dev[i]; 3500 struct sky2_port *sky2 = netdev_priv(dev); 3501 3502 if (!netif_running(dev)) 3503 continue; 3504 3505 netif_carrier_off(dev); 3506 netif_tx_disable(dev); 3507 sky2_hw_down(sky2); 3508 } 3509 } 3510 3511 static void sky2_all_up(struct sky2_hw *hw) 3512 { 3513 u32 imask = Y2_IS_BASE; 3514 int i; 3515 3516 for (i = 0; i < hw->ports; i++) { 3517 struct net_device *dev = hw->dev[i]; 3518 struct sky2_port *sky2 = netdev_priv(dev); 3519 3520 if (!netif_running(dev)) 3521 continue; 3522 3523 sky2_hw_up(sky2); 3524 sky2_set_multicast(dev); 3525 imask |= portirq_msk[i]; 3526 netif_wake_queue(dev); 3527 } 3528 3529 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3530 sky2_write32(hw, B0_IMSK, imask); 3531 sky2_read32(hw, B0_IMSK); 3532 sky2_read32(hw, B0_Y2_SP_LISR); 3533 napi_enable(&hw->napi); 3534 } 3535 } 3536 3537 static void sky2_restart(struct work_struct *work) 3538 { 3539 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3540 3541 rtnl_lock(); 3542 3543 sky2_all_down(hw); 3544 sky2_reset(hw); 3545 sky2_all_up(hw); 3546 3547 rtnl_unlock(); 3548 } 3549 3550 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3551 { 3552 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3553 } 3554 3555 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3556 { 3557 const struct sky2_port *sky2 = netdev_priv(dev); 3558 3559 wol->supported = sky2_wol_supported(sky2->hw); 3560 wol->wolopts = sky2->wol; 3561 } 3562 3563 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3564 { 3565 struct sky2_port *sky2 = netdev_priv(dev); 3566 struct sky2_hw *hw = sky2->hw; 3567 bool enable_wakeup = false; 3568 int i; 3569 3570 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3571 !device_can_wakeup(&hw->pdev->dev)) 3572 return -EOPNOTSUPP; 3573 3574 sky2->wol = wol->wolopts; 3575 3576 for (i = 0; i < hw->ports; i++) { 3577 struct net_device *dev = hw->dev[i]; 3578 struct sky2_port *sky2 = netdev_priv(dev); 3579 3580 if (sky2->wol) 3581 enable_wakeup = true; 3582 } 3583 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3584 3585 return 0; 3586 } 3587 3588 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3589 { 3590 if (sky2_is_copper(hw)) { 3591 u32 modes = SUPPORTED_10baseT_Half 3592 | SUPPORTED_10baseT_Full 3593 | SUPPORTED_100baseT_Half 3594 | SUPPORTED_100baseT_Full; 3595 3596 if (hw->flags & SKY2_HW_GIGABIT) 3597 modes |= SUPPORTED_1000baseT_Half 3598 | SUPPORTED_1000baseT_Full; 3599 return modes; 3600 } else 3601 return SUPPORTED_1000baseT_Half 3602 | SUPPORTED_1000baseT_Full; 3603 } 3604 3605 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3606 { 3607 struct sky2_port *sky2 = netdev_priv(dev); 3608 struct sky2_hw *hw = sky2->hw; 3609 3610 ecmd->transceiver = XCVR_INTERNAL; 3611 ecmd->supported = sky2_supported_modes(hw); 3612 ecmd->phy_address = PHY_ADDR_MARV; 3613 if (sky2_is_copper(hw)) { 3614 ecmd->port = PORT_TP; 3615 ethtool_cmd_speed_set(ecmd, sky2->speed); 3616 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3617 } else { 3618 ethtool_cmd_speed_set(ecmd, SPEED_1000); 3619 ecmd->port = PORT_FIBRE; 3620 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3621 } 3622 3623 ecmd->advertising = sky2->advertising; 3624 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3625 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3626 ecmd->duplex = sky2->duplex; 3627 return 0; 3628 } 3629 3630 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 3631 { 3632 struct sky2_port *sky2 = netdev_priv(dev); 3633 const struct sky2_hw *hw = sky2->hw; 3634 u32 supported = sky2_supported_modes(hw); 3635 3636 if (ecmd->autoneg == AUTONEG_ENABLE) { 3637 if (ecmd->advertising & ~supported) 3638 return -EINVAL; 3639 3640 if (sky2_is_copper(hw)) 3641 sky2->advertising = ecmd->advertising | 3642 ADVERTISED_TP | 3643 ADVERTISED_Autoneg; 3644 else 3645 sky2->advertising = ecmd->advertising | 3646 ADVERTISED_FIBRE | 3647 ADVERTISED_Autoneg; 3648 3649 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3650 sky2->duplex = -1; 3651 sky2->speed = -1; 3652 } else { 3653 u32 setting; 3654 u32 speed = ethtool_cmd_speed(ecmd); 3655 3656 switch (speed) { 3657 case SPEED_1000: 3658 if (ecmd->duplex == DUPLEX_FULL) 3659 setting = SUPPORTED_1000baseT_Full; 3660 else if (ecmd->duplex == DUPLEX_HALF) 3661 setting = SUPPORTED_1000baseT_Half; 3662 else 3663 return -EINVAL; 3664 break; 3665 case SPEED_100: 3666 if (ecmd->duplex == DUPLEX_FULL) 3667 setting = SUPPORTED_100baseT_Full; 3668 else if (ecmd->duplex == DUPLEX_HALF) 3669 setting = SUPPORTED_100baseT_Half; 3670 else 3671 return -EINVAL; 3672 break; 3673 3674 case SPEED_10: 3675 if (ecmd->duplex == DUPLEX_FULL) 3676 setting = SUPPORTED_10baseT_Full; 3677 else if (ecmd->duplex == DUPLEX_HALF) 3678 setting = SUPPORTED_10baseT_Half; 3679 else 3680 return -EINVAL; 3681 break; 3682 default: 3683 return -EINVAL; 3684 } 3685 3686 if ((setting & supported) == 0) 3687 return -EINVAL; 3688 3689 sky2->speed = speed; 3690 sky2->duplex = ecmd->duplex; 3691 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3692 } 3693 3694 if (netif_running(dev)) { 3695 sky2_phy_reinit(sky2); 3696 sky2_set_multicast(dev); 3697 } 3698 3699 return 0; 3700 } 3701 3702 static void sky2_get_drvinfo(struct net_device *dev, 3703 struct ethtool_drvinfo *info) 3704 { 3705 struct sky2_port *sky2 = netdev_priv(dev); 3706 3707 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 3708 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 3709 strlcpy(info->bus_info, pci_name(sky2->hw->pdev), 3710 sizeof(info->bus_info)); 3711 } 3712 3713 static const struct sky2_stat { 3714 char name[ETH_GSTRING_LEN]; 3715 u16 offset; 3716 } sky2_stats[] = { 3717 { "tx_bytes", GM_TXO_OK_HI }, 3718 { "rx_bytes", GM_RXO_OK_HI }, 3719 { "tx_broadcast", GM_TXF_BC_OK }, 3720 { "rx_broadcast", GM_RXF_BC_OK }, 3721 { "tx_multicast", GM_TXF_MC_OK }, 3722 { "rx_multicast", GM_RXF_MC_OK }, 3723 { "tx_unicast", GM_TXF_UC_OK }, 3724 { "rx_unicast", GM_RXF_UC_OK }, 3725 { "tx_mac_pause", GM_TXF_MPAUSE }, 3726 { "rx_mac_pause", GM_RXF_MPAUSE }, 3727 { "collisions", GM_TXF_COL }, 3728 { "late_collision",GM_TXF_LAT_COL }, 3729 { "aborted", GM_TXF_ABO_COL }, 3730 { "single_collisions", GM_TXF_SNG_COL }, 3731 { "multi_collisions", GM_TXF_MUL_COL }, 3732 3733 { "rx_short", GM_RXF_SHT }, 3734 { "rx_runt", GM_RXE_FRAG }, 3735 { "rx_64_byte_packets", GM_RXF_64B }, 3736 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3737 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3738 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3739 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3740 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3741 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3742 { "rx_too_long", GM_RXF_LNG_ERR }, 3743 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3744 { "rx_jabber", GM_RXF_JAB_PKT }, 3745 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3746 3747 { "tx_64_byte_packets", GM_TXF_64B }, 3748 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3749 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3750 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3751 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3752 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3753 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3754 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3755 }; 3756 3757 static u32 sky2_get_msglevel(struct net_device *netdev) 3758 { 3759 struct sky2_port *sky2 = netdev_priv(netdev); 3760 return sky2->msg_enable; 3761 } 3762 3763 static int sky2_nway_reset(struct net_device *dev) 3764 { 3765 struct sky2_port *sky2 = netdev_priv(dev); 3766 3767 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3768 return -EINVAL; 3769 3770 sky2_phy_reinit(sky2); 3771 sky2_set_multicast(dev); 3772 3773 return 0; 3774 } 3775 3776 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3777 { 3778 struct sky2_hw *hw = sky2->hw; 3779 unsigned port = sky2->port; 3780 int i; 3781 3782 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3783 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3784 3785 for (i = 2; i < count; i++) 3786 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3787 } 3788 3789 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3790 { 3791 struct sky2_port *sky2 = netdev_priv(netdev); 3792 sky2->msg_enable = value; 3793 } 3794 3795 static int sky2_get_sset_count(struct net_device *dev, int sset) 3796 { 3797 switch (sset) { 3798 case ETH_SS_STATS: 3799 return ARRAY_SIZE(sky2_stats); 3800 default: 3801 return -EOPNOTSUPP; 3802 } 3803 } 3804 3805 static void sky2_get_ethtool_stats(struct net_device *dev, 3806 struct ethtool_stats *stats, u64 * data) 3807 { 3808 struct sky2_port *sky2 = netdev_priv(dev); 3809 3810 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3811 } 3812 3813 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3814 { 3815 int i; 3816 3817 switch (stringset) { 3818 case ETH_SS_STATS: 3819 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3820 memcpy(data + i * ETH_GSTRING_LEN, 3821 sky2_stats[i].name, ETH_GSTRING_LEN); 3822 break; 3823 } 3824 } 3825 3826 static int sky2_set_mac_address(struct net_device *dev, void *p) 3827 { 3828 struct sky2_port *sky2 = netdev_priv(dev); 3829 struct sky2_hw *hw = sky2->hw; 3830 unsigned port = sky2->port; 3831 const struct sockaddr *addr = p; 3832 3833 if (!is_valid_ether_addr(addr->sa_data)) 3834 return -EADDRNOTAVAIL; 3835 3836 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3837 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3838 dev->dev_addr, ETH_ALEN); 3839 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3840 dev->dev_addr, ETH_ALEN); 3841 3842 /* virtual address for data */ 3843 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3844 3845 /* physical address: used for pause frames */ 3846 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3847 3848 return 0; 3849 } 3850 3851 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3852 { 3853 u32 bit; 3854 3855 bit = ether_crc(ETH_ALEN, addr) & 63; 3856 filter[bit >> 3] |= 1 << (bit & 7); 3857 } 3858 3859 static void sky2_set_multicast(struct net_device *dev) 3860 { 3861 struct sky2_port *sky2 = netdev_priv(dev); 3862 struct sky2_hw *hw = sky2->hw; 3863 unsigned port = sky2->port; 3864 struct netdev_hw_addr *ha; 3865 u16 reg; 3866 u8 filter[8]; 3867 int rx_pause; 3868 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3869 3870 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3871 memset(filter, 0, sizeof(filter)); 3872 3873 reg = gma_read16(hw, port, GM_RX_CTRL); 3874 reg |= GM_RXCR_UCF_ENA; 3875 3876 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3877 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3878 else if (dev->flags & IFF_ALLMULTI) 3879 memset(filter, 0xff, sizeof(filter)); 3880 else if (netdev_mc_empty(dev) && !rx_pause) 3881 reg &= ~GM_RXCR_MCF_ENA; 3882 else { 3883 reg |= GM_RXCR_MCF_ENA; 3884 3885 if (rx_pause) 3886 sky2_add_filter(filter, pause_mc_addr); 3887 3888 netdev_for_each_mc_addr(ha, dev) 3889 sky2_add_filter(filter, ha->addr); 3890 } 3891 3892 gma_write16(hw, port, GM_MC_ADDR_H1, 3893 (u16) filter[0] | ((u16) filter[1] << 8)); 3894 gma_write16(hw, port, GM_MC_ADDR_H2, 3895 (u16) filter[2] | ((u16) filter[3] << 8)); 3896 gma_write16(hw, port, GM_MC_ADDR_H3, 3897 (u16) filter[4] | ((u16) filter[5] << 8)); 3898 gma_write16(hw, port, GM_MC_ADDR_H4, 3899 (u16) filter[6] | ((u16) filter[7] << 8)); 3900 3901 gma_write16(hw, port, GM_RX_CTRL, reg); 3902 } 3903 3904 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev, 3905 struct rtnl_link_stats64 *stats) 3906 { 3907 struct sky2_port *sky2 = netdev_priv(dev); 3908 struct sky2_hw *hw = sky2->hw; 3909 unsigned port = sky2->port; 3910 unsigned int start; 3911 u64 _bytes, _packets; 3912 3913 do { 3914 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp); 3915 _bytes = sky2->rx_stats.bytes; 3916 _packets = sky2->rx_stats.packets; 3917 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start)); 3918 3919 stats->rx_packets = _packets; 3920 stats->rx_bytes = _bytes; 3921 3922 do { 3923 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp); 3924 _bytes = sky2->tx_stats.bytes; 3925 _packets = sky2->tx_stats.packets; 3926 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start)); 3927 3928 stats->tx_packets = _packets; 3929 stats->tx_bytes = _bytes; 3930 3931 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3932 + get_stats32(hw, port, GM_RXF_BC_OK); 3933 3934 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3935 3936 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3937 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3938 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3939 + get_stats32(hw, port, GM_RXE_FRAG); 3940 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3941 3942 stats->rx_dropped = dev->stats.rx_dropped; 3943 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3944 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3945 3946 return stats; 3947 } 3948 3949 /* Can have one global because blinking is controlled by 3950 * ethtool and that is always under RTNL mutex 3951 */ 3952 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3953 { 3954 struct sky2_hw *hw = sky2->hw; 3955 unsigned port = sky2->port; 3956 3957 spin_lock_bh(&sky2->phy_lock); 3958 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3959 hw->chip_id == CHIP_ID_YUKON_EX || 3960 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3961 u16 pg; 3962 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3963 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3964 3965 switch (mode) { 3966 case MO_LED_OFF: 3967 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3968 PHY_M_LEDC_LOS_CTRL(8) | 3969 PHY_M_LEDC_INIT_CTRL(8) | 3970 PHY_M_LEDC_STA1_CTRL(8) | 3971 PHY_M_LEDC_STA0_CTRL(8)); 3972 break; 3973 case MO_LED_ON: 3974 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3975 PHY_M_LEDC_LOS_CTRL(9) | 3976 PHY_M_LEDC_INIT_CTRL(9) | 3977 PHY_M_LEDC_STA1_CTRL(9) | 3978 PHY_M_LEDC_STA0_CTRL(9)); 3979 break; 3980 case MO_LED_BLINK: 3981 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3982 PHY_M_LEDC_LOS_CTRL(0xa) | 3983 PHY_M_LEDC_INIT_CTRL(0xa) | 3984 PHY_M_LEDC_STA1_CTRL(0xa) | 3985 PHY_M_LEDC_STA0_CTRL(0xa)); 3986 break; 3987 case MO_LED_NORM: 3988 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3989 PHY_M_LEDC_LOS_CTRL(1) | 3990 PHY_M_LEDC_INIT_CTRL(8) | 3991 PHY_M_LEDC_STA1_CTRL(7) | 3992 PHY_M_LEDC_STA0_CTRL(7)); 3993 } 3994 3995 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3996 } else 3997 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3998 PHY_M_LED_MO_DUP(mode) | 3999 PHY_M_LED_MO_10(mode) | 4000 PHY_M_LED_MO_100(mode) | 4001 PHY_M_LED_MO_1000(mode) | 4002 PHY_M_LED_MO_RX(mode) | 4003 PHY_M_LED_MO_TX(mode)); 4004 4005 spin_unlock_bh(&sky2->phy_lock); 4006 } 4007 4008 /* blink LED's for finding board */ 4009 static int sky2_set_phys_id(struct net_device *dev, 4010 enum ethtool_phys_id_state state) 4011 { 4012 struct sky2_port *sky2 = netdev_priv(dev); 4013 4014 switch (state) { 4015 case ETHTOOL_ID_ACTIVE: 4016 return 1; /* cycle on/off once per second */ 4017 case ETHTOOL_ID_INACTIVE: 4018 sky2_led(sky2, MO_LED_NORM); 4019 break; 4020 case ETHTOOL_ID_ON: 4021 sky2_led(sky2, MO_LED_ON); 4022 break; 4023 case ETHTOOL_ID_OFF: 4024 sky2_led(sky2, MO_LED_OFF); 4025 break; 4026 } 4027 4028 return 0; 4029 } 4030 4031 static void sky2_get_pauseparam(struct net_device *dev, 4032 struct ethtool_pauseparam *ecmd) 4033 { 4034 struct sky2_port *sky2 = netdev_priv(dev); 4035 4036 switch (sky2->flow_mode) { 4037 case FC_NONE: 4038 ecmd->tx_pause = ecmd->rx_pause = 0; 4039 break; 4040 case FC_TX: 4041 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 4042 break; 4043 case FC_RX: 4044 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 4045 break; 4046 case FC_BOTH: 4047 ecmd->tx_pause = ecmd->rx_pause = 1; 4048 } 4049 4050 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 4051 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 4052 } 4053 4054 static int sky2_set_pauseparam(struct net_device *dev, 4055 struct ethtool_pauseparam *ecmd) 4056 { 4057 struct sky2_port *sky2 = netdev_priv(dev); 4058 4059 if (ecmd->autoneg == AUTONEG_ENABLE) 4060 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4061 else 4062 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4063 4064 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4065 4066 if (netif_running(dev)) 4067 sky2_phy_reinit(sky2); 4068 4069 return 0; 4070 } 4071 4072 static int sky2_get_coalesce(struct net_device *dev, 4073 struct ethtool_coalesce *ecmd) 4074 { 4075 struct sky2_port *sky2 = netdev_priv(dev); 4076 struct sky2_hw *hw = sky2->hw; 4077 4078 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4079 ecmd->tx_coalesce_usecs = 0; 4080 else { 4081 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4082 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4083 } 4084 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4085 4086 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4087 ecmd->rx_coalesce_usecs = 0; 4088 else { 4089 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4090 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4091 } 4092 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4093 4094 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4095 ecmd->rx_coalesce_usecs_irq = 0; 4096 else { 4097 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4098 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4099 } 4100 4101 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4102 4103 return 0; 4104 } 4105 4106 /* Note: this affect both ports */ 4107 static int sky2_set_coalesce(struct net_device *dev, 4108 struct ethtool_coalesce *ecmd) 4109 { 4110 struct sky2_port *sky2 = netdev_priv(dev); 4111 struct sky2_hw *hw = sky2->hw; 4112 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4113 4114 if (ecmd->tx_coalesce_usecs > tmax || 4115 ecmd->rx_coalesce_usecs > tmax || 4116 ecmd->rx_coalesce_usecs_irq > tmax) 4117 return -EINVAL; 4118 4119 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4120 return -EINVAL; 4121 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4122 return -EINVAL; 4123 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4124 return -EINVAL; 4125 4126 if (ecmd->tx_coalesce_usecs == 0) 4127 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4128 else { 4129 sky2_write32(hw, STAT_TX_TIMER_INI, 4130 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4131 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4132 } 4133 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4134 4135 if (ecmd->rx_coalesce_usecs == 0) 4136 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4137 else { 4138 sky2_write32(hw, STAT_LEV_TIMER_INI, 4139 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4140 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4141 } 4142 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4143 4144 if (ecmd->rx_coalesce_usecs_irq == 0) 4145 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4146 else { 4147 sky2_write32(hw, STAT_ISR_TIMER_INI, 4148 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4149 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4150 } 4151 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4152 return 0; 4153 } 4154 4155 /* 4156 * Hardware is limited to min of 128 and max of 2048 for ring size 4157 * and rounded up to next power of two 4158 * to avoid division in modulus calclation 4159 */ 4160 static unsigned long roundup_ring_size(unsigned long pending) 4161 { 4162 return max(128ul, roundup_pow_of_two(pending+1)); 4163 } 4164 4165 static void sky2_get_ringparam(struct net_device *dev, 4166 struct ethtool_ringparam *ering) 4167 { 4168 struct sky2_port *sky2 = netdev_priv(dev); 4169 4170 ering->rx_max_pending = RX_MAX_PENDING; 4171 ering->tx_max_pending = TX_MAX_PENDING; 4172 4173 ering->rx_pending = sky2->rx_pending; 4174 ering->tx_pending = sky2->tx_pending; 4175 } 4176 4177 static int sky2_set_ringparam(struct net_device *dev, 4178 struct ethtool_ringparam *ering) 4179 { 4180 struct sky2_port *sky2 = netdev_priv(dev); 4181 4182 if (ering->rx_pending > RX_MAX_PENDING || 4183 ering->rx_pending < 8 || 4184 ering->tx_pending < TX_MIN_PENDING || 4185 ering->tx_pending > TX_MAX_PENDING) 4186 return -EINVAL; 4187 4188 sky2_detach(dev); 4189 4190 sky2->rx_pending = ering->rx_pending; 4191 sky2->tx_pending = ering->tx_pending; 4192 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4193 4194 return sky2_reattach(dev); 4195 } 4196 4197 static int sky2_get_regs_len(struct net_device *dev) 4198 { 4199 return 0x4000; 4200 } 4201 4202 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4203 { 4204 /* This complicated switch statement is to make sure and 4205 * only access regions that are unreserved. 4206 * Some blocks are only valid on dual port cards. 4207 */ 4208 switch (b) { 4209 /* second port */ 4210 case 5: /* Tx Arbiter 2 */ 4211 case 9: /* RX2 */ 4212 case 14 ... 15: /* TX2 */ 4213 case 17: case 19: /* Ram Buffer 2 */ 4214 case 22 ... 23: /* Tx Ram Buffer 2 */ 4215 case 25: /* Rx MAC Fifo 1 */ 4216 case 27: /* Tx MAC Fifo 2 */ 4217 case 31: /* GPHY 2 */ 4218 case 40 ... 47: /* Pattern Ram 2 */ 4219 case 52: case 54: /* TCP Segmentation 2 */ 4220 case 112 ... 116: /* GMAC 2 */ 4221 return hw->ports > 1; 4222 4223 case 0: /* Control */ 4224 case 2: /* Mac address */ 4225 case 4: /* Tx Arbiter 1 */ 4226 case 7: /* PCI express reg */ 4227 case 8: /* RX1 */ 4228 case 12 ... 13: /* TX1 */ 4229 case 16: case 18:/* Rx Ram Buffer 1 */ 4230 case 20 ... 21: /* Tx Ram Buffer 1 */ 4231 case 24: /* Rx MAC Fifo 1 */ 4232 case 26: /* Tx MAC Fifo 1 */ 4233 case 28 ... 29: /* Descriptor and status unit */ 4234 case 30: /* GPHY 1*/ 4235 case 32 ... 39: /* Pattern Ram 1 */ 4236 case 48: case 50: /* TCP Segmentation 1 */ 4237 case 56 ... 60: /* PCI space */ 4238 case 80 ... 84: /* GMAC 1 */ 4239 return 1; 4240 4241 default: 4242 return 0; 4243 } 4244 } 4245 4246 /* 4247 * Returns copy of control register region 4248 * Note: ethtool_get_regs always provides full size (16k) buffer 4249 */ 4250 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4251 void *p) 4252 { 4253 const struct sky2_port *sky2 = netdev_priv(dev); 4254 const void __iomem *io = sky2->hw->regs; 4255 unsigned int b; 4256 4257 regs->version = 1; 4258 4259 for (b = 0; b < 128; b++) { 4260 /* skip poisonous diagnostic ram region in block 3 */ 4261 if (b == 3) 4262 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4263 else if (sky2_reg_access_ok(sky2->hw, b)) 4264 memcpy_fromio(p, io, 128); 4265 else 4266 memset(p, 0, 128); 4267 4268 p += 128; 4269 io += 128; 4270 } 4271 } 4272 4273 static int sky2_get_eeprom_len(struct net_device *dev) 4274 { 4275 struct sky2_port *sky2 = netdev_priv(dev); 4276 struct sky2_hw *hw = sky2->hw; 4277 u16 reg2; 4278 4279 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4280 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4281 } 4282 4283 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4284 { 4285 unsigned long start = jiffies; 4286 4287 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4288 /* Can take up to 10.6 ms for write */ 4289 if (time_after(jiffies, start + HZ/4)) { 4290 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4291 return -ETIMEDOUT; 4292 } 4293 mdelay(1); 4294 } 4295 4296 return 0; 4297 } 4298 4299 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4300 u16 offset, size_t length) 4301 { 4302 int rc = 0; 4303 4304 while (length > 0) { 4305 u32 val; 4306 4307 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4308 rc = sky2_vpd_wait(hw, cap, 0); 4309 if (rc) 4310 break; 4311 4312 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4313 4314 memcpy(data, &val, min(sizeof(val), length)); 4315 offset += sizeof(u32); 4316 data += sizeof(u32); 4317 length -= sizeof(u32); 4318 } 4319 4320 return rc; 4321 } 4322 4323 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4324 u16 offset, unsigned int length) 4325 { 4326 unsigned int i; 4327 int rc = 0; 4328 4329 for (i = 0; i < length; i += sizeof(u32)) { 4330 u32 val = *(u32 *)(data + i); 4331 4332 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4333 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4334 4335 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4336 if (rc) 4337 break; 4338 } 4339 return rc; 4340 } 4341 4342 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4343 u8 *data) 4344 { 4345 struct sky2_port *sky2 = netdev_priv(dev); 4346 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4347 4348 if (!cap) 4349 return -EINVAL; 4350 4351 eeprom->magic = SKY2_EEPROM_MAGIC; 4352 4353 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4354 } 4355 4356 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4357 u8 *data) 4358 { 4359 struct sky2_port *sky2 = netdev_priv(dev); 4360 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4361 4362 if (!cap) 4363 return -EINVAL; 4364 4365 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4366 return -EINVAL; 4367 4368 /* Partial writes not supported */ 4369 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4370 return -EINVAL; 4371 4372 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4373 } 4374 4375 static netdev_features_t sky2_fix_features(struct net_device *dev, 4376 netdev_features_t features) 4377 { 4378 const struct sky2_port *sky2 = netdev_priv(dev); 4379 const struct sky2_hw *hw = sky2->hw; 4380 4381 /* In order to do Jumbo packets on these chips, need to turn off the 4382 * transmit store/forward. Therefore checksum offload won't work. 4383 */ 4384 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4385 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4386 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM); 4387 } 4388 4389 /* Some hardware requires receive checksum for RSS to work. */ 4390 if ( (features & NETIF_F_RXHASH) && 4391 !(features & NETIF_F_RXCSUM) && 4392 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4393 netdev_info(dev, "receive hashing forces receive checksum\n"); 4394 features |= NETIF_F_RXCSUM; 4395 } 4396 4397 return features; 4398 } 4399 4400 static int sky2_set_features(struct net_device *dev, netdev_features_t features) 4401 { 4402 struct sky2_port *sky2 = netdev_priv(dev); 4403 netdev_features_t changed = dev->features ^ features; 4404 4405 if ((changed & NETIF_F_RXCSUM) && 4406 !(sky2->hw->flags & SKY2_HW_NEW_LE)) { 4407 sky2_write32(sky2->hw, 4408 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4409 (features & NETIF_F_RXCSUM) 4410 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4411 } 4412 4413 if (changed & NETIF_F_RXHASH) 4414 rx_set_rss(dev, features); 4415 4416 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) 4417 sky2_vlan_mode(dev, features); 4418 4419 return 0; 4420 } 4421 4422 static const struct ethtool_ops sky2_ethtool_ops = { 4423 .get_settings = sky2_get_settings, 4424 .set_settings = sky2_set_settings, 4425 .get_drvinfo = sky2_get_drvinfo, 4426 .get_wol = sky2_get_wol, 4427 .set_wol = sky2_set_wol, 4428 .get_msglevel = sky2_get_msglevel, 4429 .set_msglevel = sky2_set_msglevel, 4430 .nway_reset = sky2_nway_reset, 4431 .get_regs_len = sky2_get_regs_len, 4432 .get_regs = sky2_get_regs, 4433 .get_link = ethtool_op_get_link, 4434 .get_eeprom_len = sky2_get_eeprom_len, 4435 .get_eeprom = sky2_get_eeprom, 4436 .set_eeprom = sky2_set_eeprom, 4437 .get_strings = sky2_get_strings, 4438 .get_coalesce = sky2_get_coalesce, 4439 .set_coalesce = sky2_set_coalesce, 4440 .get_ringparam = sky2_get_ringparam, 4441 .set_ringparam = sky2_set_ringparam, 4442 .get_pauseparam = sky2_get_pauseparam, 4443 .set_pauseparam = sky2_set_pauseparam, 4444 .set_phys_id = sky2_set_phys_id, 4445 .get_sset_count = sky2_get_sset_count, 4446 .get_ethtool_stats = sky2_get_ethtool_stats, 4447 }; 4448 4449 #ifdef CONFIG_SKY2_DEBUG 4450 4451 static struct dentry *sky2_debug; 4452 4453 4454 /* 4455 * Read and parse the first part of Vital Product Data 4456 */ 4457 #define VPD_SIZE 128 4458 #define VPD_MAGIC 0x82 4459 4460 static const struct vpd_tag { 4461 char tag[2]; 4462 char *label; 4463 } vpd_tags[] = { 4464 { "PN", "Part Number" }, 4465 { "EC", "Engineering Level" }, 4466 { "MN", "Manufacturer" }, 4467 { "SN", "Serial Number" }, 4468 { "YA", "Asset Tag" }, 4469 { "VL", "First Error Log Message" }, 4470 { "VF", "Second Error Log Message" }, 4471 { "VB", "Boot Agent ROM Configuration" }, 4472 { "VE", "EFI UNDI Configuration" }, 4473 }; 4474 4475 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4476 { 4477 size_t vpd_size; 4478 loff_t offs; 4479 u8 len; 4480 unsigned char *buf; 4481 u16 reg2; 4482 4483 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4484 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4485 4486 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4487 buf = kmalloc(vpd_size, GFP_KERNEL); 4488 if (!buf) { 4489 seq_puts(seq, "no memory!\n"); 4490 return; 4491 } 4492 4493 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4494 seq_puts(seq, "VPD read failed\n"); 4495 goto out; 4496 } 4497 4498 if (buf[0] != VPD_MAGIC) { 4499 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4500 goto out; 4501 } 4502 len = buf[1]; 4503 if (len == 0 || len > vpd_size - 4) { 4504 seq_printf(seq, "Invalid id length: %d\n", len); 4505 goto out; 4506 } 4507 4508 seq_printf(seq, "%.*s\n", len, buf + 3); 4509 offs = len + 3; 4510 4511 while (offs < vpd_size - 4) { 4512 int i; 4513 4514 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4515 break; 4516 len = buf[offs + 2]; 4517 if (offs + len + 3 >= vpd_size) 4518 break; 4519 4520 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4521 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4522 seq_printf(seq, " %s: %.*s\n", 4523 vpd_tags[i].label, len, buf + offs + 3); 4524 break; 4525 } 4526 } 4527 offs += len + 3; 4528 } 4529 out: 4530 kfree(buf); 4531 } 4532 4533 static int sky2_debug_show(struct seq_file *seq, void *v) 4534 { 4535 struct net_device *dev = seq->private; 4536 const struct sky2_port *sky2 = netdev_priv(dev); 4537 struct sky2_hw *hw = sky2->hw; 4538 unsigned port = sky2->port; 4539 unsigned idx, last; 4540 int sop; 4541 4542 sky2_show_vpd(seq, hw); 4543 4544 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4545 sky2_read32(hw, B0_ISRC), 4546 sky2_read32(hw, B0_IMSK), 4547 sky2_read32(hw, B0_Y2_SP_ICR)); 4548 4549 if (!netif_running(dev)) { 4550 seq_printf(seq, "network not running\n"); 4551 return 0; 4552 } 4553 4554 napi_disable(&hw->napi); 4555 last = sky2_read16(hw, STAT_PUT_IDX); 4556 4557 seq_printf(seq, "Status ring %u\n", hw->st_size); 4558 if (hw->st_idx == last) 4559 seq_puts(seq, "Status ring (empty)\n"); 4560 else { 4561 seq_puts(seq, "Status ring\n"); 4562 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4563 idx = RING_NEXT(idx, hw->st_size)) { 4564 const struct sky2_status_le *le = hw->st_le + idx; 4565 seq_printf(seq, "[%d] %#x %d %#x\n", 4566 idx, le->opcode, le->length, le->status); 4567 } 4568 seq_puts(seq, "\n"); 4569 } 4570 4571 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4572 sky2->tx_cons, sky2->tx_prod, 4573 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4574 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4575 4576 /* Dump contents of tx ring */ 4577 sop = 1; 4578 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4579 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4580 const struct sky2_tx_le *le = sky2->tx_le + idx; 4581 u32 a = le32_to_cpu(le->addr); 4582 4583 if (sop) 4584 seq_printf(seq, "%u:", idx); 4585 sop = 0; 4586 4587 switch (le->opcode & ~HW_OWNER) { 4588 case OP_ADDR64: 4589 seq_printf(seq, " %#x:", a); 4590 break; 4591 case OP_LRGLEN: 4592 seq_printf(seq, " mtu=%d", a); 4593 break; 4594 case OP_VLAN: 4595 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4596 break; 4597 case OP_TCPLISW: 4598 seq_printf(seq, " csum=%#x", a); 4599 break; 4600 case OP_LARGESEND: 4601 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4602 break; 4603 case OP_PACKET: 4604 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4605 break; 4606 case OP_BUFFER: 4607 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4608 break; 4609 default: 4610 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4611 a, le16_to_cpu(le->length)); 4612 } 4613 4614 if (le->ctrl & EOP) { 4615 seq_putc(seq, '\n'); 4616 sop = 1; 4617 } 4618 } 4619 4620 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4621 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4622 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4623 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4624 4625 sky2_read32(hw, B0_Y2_SP_LISR); 4626 napi_enable(&hw->napi); 4627 return 0; 4628 } 4629 4630 static int sky2_debug_open(struct inode *inode, struct file *file) 4631 { 4632 return single_open(file, sky2_debug_show, inode->i_private); 4633 } 4634 4635 static const struct file_operations sky2_debug_fops = { 4636 .owner = THIS_MODULE, 4637 .open = sky2_debug_open, 4638 .read = seq_read, 4639 .llseek = seq_lseek, 4640 .release = single_release, 4641 }; 4642 4643 /* 4644 * Use network device events to create/remove/rename 4645 * debugfs file entries 4646 */ 4647 static int sky2_device_event(struct notifier_block *unused, 4648 unsigned long event, void *ptr) 4649 { 4650 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4651 struct sky2_port *sky2 = netdev_priv(dev); 4652 4653 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4654 return NOTIFY_DONE; 4655 4656 switch (event) { 4657 case NETDEV_CHANGENAME: 4658 if (sky2->debugfs) { 4659 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4660 sky2_debug, dev->name); 4661 } 4662 break; 4663 4664 case NETDEV_GOING_DOWN: 4665 if (sky2->debugfs) { 4666 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4667 debugfs_remove(sky2->debugfs); 4668 sky2->debugfs = NULL; 4669 } 4670 break; 4671 4672 case NETDEV_UP: 4673 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO, 4674 sky2_debug, dev, 4675 &sky2_debug_fops); 4676 if (IS_ERR(sky2->debugfs)) 4677 sky2->debugfs = NULL; 4678 } 4679 4680 return NOTIFY_DONE; 4681 } 4682 4683 static struct notifier_block sky2_notifier = { 4684 .notifier_call = sky2_device_event, 4685 }; 4686 4687 4688 static __init void sky2_debug_init(void) 4689 { 4690 struct dentry *ent; 4691 4692 ent = debugfs_create_dir("sky2", NULL); 4693 if (!ent || IS_ERR(ent)) 4694 return; 4695 4696 sky2_debug = ent; 4697 register_netdevice_notifier(&sky2_notifier); 4698 } 4699 4700 static __exit void sky2_debug_cleanup(void) 4701 { 4702 if (sky2_debug) { 4703 unregister_netdevice_notifier(&sky2_notifier); 4704 debugfs_remove(sky2_debug); 4705 sky2_debug = NULL; 4706 } 4707 } 4708 4709 #else 4710 #define sky2_debug_init() 4711 #define sky2_debug_cleanup() 4712 #endif 4713 4714 /* Two copies of network device operations to handle special case of 4715 not allowing netpoll on second port */ 4716 static const struct net_device_ops sky2_netdev_ops[2] = { 4717 { 4718 .ndo_open = sky2_open, 4719 .ndo_stop = sky2_close, 4720 .ndo_start_xmit = sky2_xmit_frame, 4721 .ndo_do_ioctl = sky2_ioctl, 4722 .ndo_validate_addr = eth_validate_addr, 4723 .ndo_set_mac_address = sky2_set_mac_address, 4724 .ndo_set_rx_mode = sky2_set_multicast, 4725 .ndo_change_mtu = sky2_change_mtu, 4726 .ndo_fix_features = sky2_fix_features, 4727 .ndo_set_features = sky2_set_features, 4728 .ndo_tx_timeout = sky2_tx_timeout, 4729 .ndo_get_stats64 = sky2_get_stats, 4730 #ifdef CONFIG_NET_POLL_CONTROLLER 4731 .ndo_poll_controller = sky2_netpoll, 4732 #endif 4733 }, 4734 { 4735 .ndo_open = sky2_open, 4736 .ndo_stop = sky2_close, 4737 .ndo_start_xmit = sky2_xmit_frame, 4738 .ndo_do_ioctl = sky2_ioctl, 4739 .ndo_validate_addr = eth_validate_addr, 4740 .ndo_set_mac_address = sky2_set_mac_address, 4741 .ndo_set_rx_mode = sky2_set_multicast, 4742 .ndo_change_mtu = sky2_change_mtu, 4743 .ndo_fix_features = sky2_fix_features, 4744 .ndo_set_features = sky2_set_features, 4745 .ndo_tx_timeout = sky2_tx_timeout, 4746 .ndo_get_stats64 = sky2_get_stats, 4747 }, 4748 }; 4749 4750 /* Initialize network device */ 4751 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, 4752 int highmem, int wol) 4753 { 4754 struct sky2_port *sky2; 4755 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4756 const void *iap; 4757 4758 if (!dev) 4759 return NULL; 4760 4761 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4762 dev->irq = hw->pdev->irq; 4763 dev->ethtool_ops = &sky2_ethtool_ops; 4764 dev->watchdog_timeo = TX_WATCHDOG; 4765 dev->netdev_ops = &sky2_netdev_ops[port]; 4766 4767 sky2 = netdev_priv(dev); 4768 sky2->netdev = dev; 4769 sky2->hw = hw; 4770 sky2->msg_enable = netif_msg_init(debug, default_msg); 4771 4772 u64_stats_init(&sky2->tx_stats.syncp); 4773 u64_stats_init(&sky2->rx_stats.syncp); 4774 4775 /* Auto speed and flow control */ 4776 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4777 if (hw->chip_id != CHIP_ID_YUKON_XL) 4778 dev->hw_features |= NETIF_F_RXCSUM; 4779 4780 sky2->flow_mode = FC_BOTH; 4781 4782 sky2->duplex = -1; 4783 sky2->speed = -1; 4784 sky2->advertising = sky2_supported_modes(hw); 4785 sky2->wol = wol; 4786 4787 spin_lock_init(&sky2->phy_lock); 4788 4789 sky2->tx_pending = TX_DEF_PENDING; 4790 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4791 sky2->rx_pending = RX_DEF_PENDING; 4792 4793 hw->dev[port] = dev; 4794 4795 sky2->port = port; 4796 4797 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4798 4799 if (highmem) 4800 dev->features |= NETIF_F_HIGHDMA; 4801 4802 /* Enable receive hashing unless hardware is known broken */ 4803 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4804 dev->hw_features |= NETIF_F_RXHASH; 4805 4806 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4807 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 4808 NETIF_F_HW_VLAN_CTAG_RX; 4809 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4810 } 4811 4812 dev->features |= dev->hw_features; 4813 4814 /* try to get mac address in the following order: 4815 * 1) from device tree data 4816 * 2) from internal registers set by bootloader 4817 */ 4818 iap = of_get_mac_address(hw->pdev->dev.of_node); 4819 if (iap) 4820 memcpy(dev->dev_addr, iap, ETH_ALEN); 4821 else 4822 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, 4823 ETH_ALEN); 4824 4825 return dev; 4826 } 4827 4828 static void sky2_show_addr(struct net_device *dev) 4829 { 4830 const struct sky2_port *sky2 = netdev_priv(dev); 4831 4832 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4833 } 4834 4835 /* Handle software interrupt used during MSI test */ 4836 static irqreturn_t sky2_test_intr(int irq, void *dev_id) 4837 { 4838 struct sky2_hw *hw = dev_id; 4839 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4840 4841 if (status == 0) 4842 return IRQ_NONE; 4843 4844 if (status & Y2_IS_IRQ_SW) { 4845 hw->flags |= SKY2_HW_USE_MSI; 4846 wake_up(&hw->msi_wait); 4847 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4848 } 4849 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4850 4851 return IRQ_HANDLED; 4852 } 4853 4854 /* Test interrupt path by forcing a a software IRQ */ 4855 static int sky2_test_msi(struct sky2_hw *hw) 4856 { 4857 struct pci_dev *pdev = hw->pdev; 4858 int err; 4859 4860 init_waitqueue_head(&hw->msi_wait); 4861 4862 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4863 if (err) { 4864 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4865 return err; 4866 } 4867 4868 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4869 4870 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4871 sky2_read8(hw, B0_CTST); 4872 4873 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4874 4875 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4876 /* MSI test failed, go back to INTx mode */ 4877 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4878 "switching to INTx mode.\n"); 4879 4880 err = -EOPNOTSUPP; 4881 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4882 } 4883 4884 sky2_write32(hw, B0_IMSK, 0); 4885 sky2_read32(hw, B0_IMSK); 4886 4887 free_irq(pdev->irq, hw); 4888 4889 return err; 4890 } 4891 4892 /* This driver supports yukon2 chipset only */ 4893 static const char *sky2_name(u8 chipid, char *buf, int sz) 4894 { 4895 const char *name[] = { 4896 "XL", /* 0xb3 */ 4897 "EC Ultra", /* 0xb4 */ 4898 "Extreme", /* 0xb5 */ 4899 "EC", /* 0xb6 */ 4900 "FE", /* 0xb7 */ 4901 "FE+", /* 0xb8 */ 4902 "Supreme", /* 0xb9 */ 4903 "UL 2", /* 0xba */ 4904 "Unknown", /* 0xbb */ 4905 "Optima", /* 0xbc */ 4906 "OptimaEEE", /* 0xbd */ 4907 "Optima 2", /* 0xbe */ 4908 }; 4909 4910 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4911 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4912 else 4913 snprintf(buf, sz, "(chip %#x)", chipid); 4914 return buf; 4915 } 4916 4917 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 4918 { 4919 struct net_device *dev, *dev1; 4920 struct sky2_hw *hw; 4921 int err, using_dac = 0, wol_default; 4922 u32 reg; 4923 char buf1[16]; 4924 4925 err = pci_enable_device(pdev); 4926 if (err) { 4927 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4928 goto err_out; 4929 } 4930 4931 /* Get configuration information 4932 * Note: only regular PCI config access once to test for HW issues 4933 * other PCI access through shared memory for speed and to 4934 * avoid MMCONFIG problems. 4935 */ 4936 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4937 if (err) { 4938 dev_err(&pdev->dev, "PCI read config failed\n"); 4939 goto err_out_disable; 4940 } 4941 4942 if (~reg == 0) { 4943 dev_err(&pdev->dev, "PCI configuration read error\n"); 4944 err = -EIO; 4945 goto err_out_disable; 4946 } 4947 4948 err = pci_request_regions(pdev, DRV_NAME); 4949 if (err) { 4950 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4951 goto err_out_disable; 4952 } 4953 4954 pci_set_master(pdev); 4955 4956 if (sizeof(dma_addr_t) > sizeof(u32) && 4957 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4958 using_dac = 1; 4959 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4960 if (err < 0) { 4961 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4962 "for consistent allocations\n"); 4963 goto err_out_free_regions; 4964 } 4965 } else { 4966 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4967 if (err) { 4968 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4969 goto err_out_free_regions; 4970 } 4971 } 4972 4973 4974 #ifdef __BIG_ENDIAN 4975 /* The sk98lin vendor driver uses hardware byte swapping but 4976 * this driver uses software swapping. 4977 */ 4978 reg &= ~PCI_REV_DESC; 4979 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 4980 if (err) { 4981 dev_err(&pdev->dev, "PCI write config failed\n"); 4982 goto err_out_free_regions; 4983 } 4984 #endif 4985 4986 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 4987 4988 err = -ENOMEM; 4989 4990 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 4991 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 4992 if (!hw) 4993 goto err_out_free_regions; 4994 4995 hw->pdev = pdev; 4996 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 4997 4998 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 4999 if (!hw->regs) { 5000 dev_err(&pdev->dev, "cannot map device registers\n"); 5001 goto err_out_free_hw; 5002 } 5003 5004 err = sky2_init(hw); 5005 if (err) 5006 goto err_out_iounmap; 5007 5008 /* ring for status responses */ 5009 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 5010 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5011 &hw->st_dma); 5012 if (!hw->st_le) { 5013 err = -ENOMEM; 5014 goto err_out_reset; 5015 } 5016 5017 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 5018 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 5019 5020 sky2_reset(hw); 5021 5022 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 5023 if (!dev) { 5024 err = -ENOMEM; 5025 goto err_out_free_pci; 5026 } 5027 5028 if (!disable_msi && pci_enable_msi(pdev) == 0) { 5029 err = sky2_test_msi(hw); 5030 if (err) { 5031 pci_disable_msi(pdev); 5032 if (err != -EOPNOTSUPP) 5033 goto err_out_free_netdev; 5034 } 5035 } 5036 5037 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 5038 5039 err = register_netdev(dev); 5040 if (err) { 5041 dev_err(&pdev->dev, "cannot register net device\n"); 5042 goto err_out_free_netdev; 5043 } 5044 5045 netif_carrier_off(dev); 5046 5047 sky2_show_addr(dev); 5048 5049 if (hw->ports > 1) { 5050 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 5051 if (!dev1) { 5052 err = -ENOMEM; 5053 goto err_out_unregister; 5054 } 5055 5056 err = register_netdev(dev1); 5057 if (err) { 5058 dev_err(&pdev->dev, "cannot register second net device\n"); 5059 goto err_out_free_dev1; 5060 } 5061 5062 err = sky2_setup_irq(hw, hw->irq_name); 5063 if (err) 5064 goto err_out_unregister_dev1; 5065 5066 sky2_show_addr(dev1); 5067 } 5068 5069 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw); 5070 INIT_WORK(&hw->restart_work, sky2_restart); 5071 5072 pci_set_drvdata(pdev, hw); 5073 pdev->d3_delay = 150; 5074 5075 return 0; 5076 5077 err_out_unregister_dev1: 5078 unregister_netdev(dev1); 5079 err_out_free_dev1: 5080 free_netdev(dev1); 5081 err_out_unregister: 5082 unregister_netdev(dev); 5083 err_out_free_netdev: 5084 if (hw->flags & SKY2_HW_USE_MSI) 5085 pci_disable_msi(pdev); 5086 free_netdev(dev); 5087 err_out_free_pci: 5088 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5089 hw->st_le, hw->st_dma); 5090 err_out_reset: 5091 sky2_write8(hw, B0_CTST, CS_RST_SET); 5092 err_out_iounmap: 5093 iounmap(hw->regs); 5094 err_out_free_hw: 5095 kfree(hw); 5096 err_out_free_regions: 5097 pci_release_regions(pdev); 5098 err_out_disable: 5099 pci_disable_device(pdev); 5100 err_out: 5101 return err; 5102 } 5103 5104 static void sky2_remove(struct pci_dev *pdev) 5105 { 5106 struct sky2_hw *hw = pci_get_drvdata(pdev); 5107 int i; 5108 5109 if (!hw) 5110 return; 5111 5112 del_timer_sync(&hw->watchdog_timer); 5113 cancel_work_sync(&hw->restart_work); 5114 5115 for (i = hw->ports-1; i >= 0; --i) 5116 unregister_netdev(hw->dev[i]); 5117 5118 sky2_write32(hw, B0_IMSK, 0); 5119 sky2_read32(hw, B0_IMSK); 5120 5121 sky2_power_aux(hw); 5122 5123 sky2_write8(hw, B0_CTST, CS_RST_SET); 5124 sky2_read8(hw, B0_CTST); 5125 5126 if (hw->ports > 1) { 5127 napi_disable(&hw->napi); 5128 free_irq(pdev->irq, hw); 5129 } 5130 5131 if (hw->flags & SKY2_HW_USE_MSI) 5132 pci_disable_msi(pdev); 5133 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5134 hw->st_le, hw->st_dma); 5135 pci_release_regions(pdev); 5136 pci_disable_device(pdev); 5137 5138 for (i = hw->ports-1; i >= 0; --i) 5139 free_netdev(hw->dev[i]); 5140 5141 iounmap(hw->regs); 5142 kfree(hw); 5143 } 5144 5145 static int sky2_suspend(struct device *dev) 5146 { 5147 struct pci_dev *pdev = to_pci_dev(dev); 5148 struct sky2_hw *hw = pci_get_drvdata(pdev); 5149 int i; 5150 5151 if (!hw) 5152 return 0; 5153 5154 del_timer_sync(&hw->watchdog_timer); 5155 cancel_work_sync(&hw->restart_work); 5156 5157 rtnl_lock(); 5158 5159 sky2_all_down(hw); 5160 for (i = 0; i < hw->ports; i++) { 5161 struct net_device *dev = hw->dev[i]; 5162 struct sky2_port *sky2 = netdev_priv(dev); 5163 5164 if (sky2->wol) 5165 sky2_wol_init(sky2); 5166 } 5167 5168 sky2_power_aux(hw); 5169 rtnl_unlock(); 5170 5171 return 0; 5172 } 5173 5174 #ifdef CONFIG_PM_SLEEP 5175 static int sky2_resume(struct device *dev) 5176 { 5177 struct pci_dev *pdev = to_pci_dev(dev); 5178 struct sky2_hw *hw = pci_get_drvdata(pdev); 5179 int err; 5180 5181 if (!hw) 5182 return 0; 5183 5184 /* Re-enable all clocks */ 5185 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5186 if (err) { 5187 dev_err(&pdev->dev, "PCI write config failed\n"); 5188 goto out; 5189 } 5190 5191 rtnl_lock(); 5192 sky2_reset(hw); 5193 sky2_all_up(hw); 5194 rtnl_unlock(); 5195 5196 return 0; 5197 out: 5198 5199 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5200 pci_disable_device(pdev); 5201 return err; 5202 } 5203 5204 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5205 #define SKY2_PM_OPS (&sky2_pm_ops) 5206 5207 #else 5208 5209 #define SKY2_PM_OPS NULL 5210 #endif 5211 5212 static void sky2_shutdown(struct pci_dev *pdev) 5213 { 5214 sky2_suspend(&pdev->dev); 5215 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5216 pci_set_power_state(pdev, PCI_D3hot); 5217 } 5218 5219 static struct pci_driver sky2_driver = { 5220 .name = DRV_NAME, 5221 .id_table = sky2_id_table, 5222 .probe = sky2_probe, 5223 .remove = sky2_remove, 5224 .shutdown = sky2_shutdown, 5225 .driver.pm = SKY2_PM_OPS, 5226 }; 5227 5228 static int __init sky2_init_module(void) 5229 { 5230 pr_info("driver version " DRV_VERSION "\n"); 5231 5232 sky2_debug_init(); 5233 return pci_register_driver(&sky2_driver); 5234 } 5235 5236 static void __exit sky2_cleanup_module(void) 5237 { 5238 pci_unregister_driver(&sky2_driver); 5239 sky2_debug_cleanup(); 5240 } 5241 5242 module_init(sky2_init_module); 5243 module_exit(sky2_cleanup_module); 5244 5245 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5246 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5247 MODULE_LICENSE("GPL"); 5248 MODULE_VERSION(DRV_VERSION); 5249