1 /*
2  * New driver for Marvell Yukon 2 chipset.
3  * Based on earlier sk98lin, and skge driver.
4  *
5  * This driver intentionally does not support all the features
6  * of the original driver such as link fail-over and link management because
7  * those should be done at higher levels.
8  *
9  * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23  */
24 
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/slab.h>
38 #include <net/ip.h>
39 #include <linux/tcp.h>
40 #include <linux/in.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47 #include <linux/of_device.h>
48 #include <linux/of_net.h>
49 
50 #include <asm/irq.h>
51 
52 #include "sky2.h"
53 
54 #define DRV_NAME		"sky2"
55 #define DRV_VERSION		"1.30"
56 
57 /*
58  * The Yukon II chipset takes 64 bit command blocks (called list elements)
59  * that are organized into three (receive, transmit, status) different rings
60  * similar to Tigon3.
61  */
62 
63 #define RX_LE_SIZE	    	1024
64 #define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING		(RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING		RX_MAX_PENDING
67 
68 /* This is the worst case number of transmit list elements for a single skb:
69    VLAN:GSO + CKSUM + Data + skb_frags * DMA */
70 #define MAX_SKB_TX_LE	(2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
71 #define TX_MIN_PENDING		(MAX_SKB_TX_LE+1)
72 #define TX_MAX_PENDING		1024
73 #define TX_DEF_PENDING		63
74 
75 #define TX_WATCHDOG		(5 * HZ)
76 #define NAPI_WEIGHT		64
77 #define PHY_RETRIES		1000
78 
79 #define SKY2_EEPROM_MAGIC	0x9955aabb
80 
81 #define RING_NEXT(x, s)	(((x)+1) & ((s)-1))
82 
83 static const u32 default_msg =
84     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85     | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87 
88 static int debug = -1;		/* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91 
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95 
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99 
100 static int legacy_pme = 0;
101 module_param(legacy_pme, int, 0);
102 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
103 
104 static const struct pci_device_id sky2_id_table[] = {
105 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
107 	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
108 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },	/* DGE-560T */
109 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, 	/* DGE-550SX */
110 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) },	/* DGE-560SX */
111 	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) },	/* DGE-550T */
112 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
113 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
114 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
115 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
116 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
117 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
118 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
119 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
120 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
121 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
122 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
123 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
124 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
125 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
126 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
127 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
128 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
129 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
130 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
131 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
132 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
133 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
134 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
135 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
136 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
137 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
138 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
139 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
140 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
141 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
142 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
143 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
144 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
145 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
146 	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
147 	{ 0 }
148 };
149 
150 MODULE_DEVICE_TABLE(pci, sky2_id_table);
151 
152 /* Avoid conditionals by using array */
153 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
154 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
155 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
156 
157 static void sky2_set_multicast(struct net_device *dev);
158 static irqreturn_t sky2_intr(int irq, void *dev_id);
159 
160 /* Access to PHY via serial interconnect */
161 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
162 {
163 	int i;
164 
165 	gma_write16(hw, port, GM_SMI_DATA, val);
166 	gma_write16(hw, port, GM_SMI_CTRL,
167 		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
168 
169 	for (i = 0; i < PHY_RETRIES; i++) {
170 		u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
171 		if (ctrl == 0xffff)
172 			goto io_error;
173 
174 		if (!(ctrl & GM_SMI_CT_BUSY))
175 			return 0;
176 
177 		udelay(10);
178 	}
179 
180 	dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
181 	return -ETIMEDOUT;
182 
183 io_error:
184 	dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
185 	return -EIO;
186 }
187 
188 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
189 {
190 	int i;
191 
192 	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
193 		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
194 
195 	for (i = 0; i < PHY_RETRIES; i++) {
196 		u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
197 		if (ctrl == 0xffff)
198 			goto io_error;
199 
200 		if (ctrl & GM_SMI_CT_RD_VAL) {
201 			*val = gma_read16(hw, port, GM_SMI_DATA);
202 			return 0;
203 		}
204 
205 		udelay(10);
206 	}
207 
208 	dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
209 	return -ETIMEDOUT;
210 io_error:
211 	dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
212 	return -EIO;
213 }
214 
215 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
216 {
217 	u16 v;
218 	__gm_phy_read(hw, port, reg, &v);
219 	return v;
220 }
221 
222 
223 static void sky2_power_on(struct sky2_hw *hw)
224 {
225 	/* switch power to VCC (WA for VAUX problem) */
226 	sky2_write8(hw, B0_POWER_CTRL,
227 		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
228 
229 	/* disable Core Clock Division, */
230 	sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
231 
232 	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
233 		/* enable bits are inverted */
234 		sky2_write8(hw, B2_Y2_CLK_GATE,
235 			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
238 	else
239 		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
240 
241 	if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
242 		u32 reg;
243 
244 		sky2_pci_write32(hw, PCI_DEV_REG3, 0);
245 
246 		reg = sky2_pci_read32(hw, PCI_DEV_REG4);
247 		/* set all bits to 0 except bits 15..12 and 8 */
248 		reg &= P_ASPM_CONTROL_MSK;
249 		sky2_pci_write32(hw, PCI_DEV_REG4, reg);
250 
251 		reg = sky2_pci_read32(hw, PCI_DEV_REG5);
252 		/* set all bits to 0 except bits 28 & 27 */
253 		reg &= P_CTL_TIM_VMAIN_AV_MSK;
254 		sky2_pci_write32(hw, PCI_DEV_REG5, reg);
255 
256 		sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
257 
258 		sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
259 
260 		/* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 		reg = sky2_read32(hw, B2_GP_IO);
262 		reg |= GLB_GPIO_STAT_RACE_DIS;
263 		sky2_write32(hw, B2_GP_IO, reg);
264 
265 		sky2_read32(hw, B2_GP_IO);
266 	}
267 
268 	/* Turn on "driver loaded" LED */
269 	sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
270 }
271 
272 static void sky2_power_aux(struct sky2_hw *hw)
273 {
274 	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
275 		sky2_write8(hw, B2_Y2_CLK_GATE, 0);
276 	else
277 		/* enable bits are inverted */
278 		sky2_write8(hw, B2_Y2_CLK_GATE,
279 			    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
280 			    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
281 			    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
282 
283 	/* switch power to VAUX if supported and PME from D3cold */
284 	if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
285 	     pci_pme_capable(hw->pdev, PCI_D3cold))
286 		sky2_write8(hw, B0_POWER_CTRL,
287 			    (PC_VAUX_ENA | PC_VCC_ENA |
288 			     PC_VAUX_ON | PC_VCC_OFF));
289 
290 	/* turn off "driver loaded LED" */
291 	sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
292 }
293 
294 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
295 {
296 	u16 reg;
297 
298 	/* disable all GMAC IRQ's */
299 	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
300 
301 	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
302 	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
303 	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
304 	gma_write16(hw, port, GM_MC_ADDR_H4, 0);
305 
306 	reg = gma_read16(hw, port, GM_RX_CTRL);
307 	reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
308 	gma_write16(hw, port, GM_RX_CTRL, reg);
309 }
310 
311 /* flow control to advertise bits */
312 static const u16 copper_fc_adv[] = {
313 	[FC_NONE]	= 0,
314 	[FC_TX]		= PHY_M_AN_ASP,
315 	[FC_RX]		= PHY_M_AN_PC,
316 	[FC_BOTH]	= PHY_M_AN_PC | PHY_M_AN_ASP,
317 };
318 
319 /* flow control to advertise bits when using 1000BaseX */
320 static const u16 fiber_fc_adv[] = {
321 	[FC_NONE] = PHY_M_P_NO_PAUSE_X,
322 	[FC_TX]   = PHY_M_P_ASYM_MD_X,
323 	[FC_RX]	  = PHY_M_P_SYM_MD_X,
324 	[FC_BOTH] = PHY_M_P_BOTH_MD_X,
325 };
326 
327 /* flow control to GMA disable bits */
328 static const u16 gm_fc_disable[] = {
329 	[FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
330 	[FC_TX]	  = GM_GPCR_FC_RX_DIS,
331 	[FC_RX]	  = GM_GPCR_FC_TX_DIS,
332 	[FC_BOTH] = 0,
333 };
334 
335 
336 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
337 {
338 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
339 	u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
340 
341 	if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
342 	    !(hw->flags & SKY2_HW_NEWER_PHY)) {
343 		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
344 
345 		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
346 			   PHY_M_EC_MAC_S_MSK);
347 		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
348 
349 		/* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
350 		if (hw->chip_id == CHIP_ID_YUKON_EC)
351 			/* set downshift counter to 3x and enable downshift */
352 			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
353 		else
354 			/* set master & slave downshift counter to 1x */
355 			ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
356 
357 		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
358 	}
359 
360 	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
361 	if (sky2_is_copper(hw)) {
362 		if (!(hw->flags & SKY2_HW_GIGABIT)) {
363 			/* enable automatic crossover */
364 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
365 
366 			if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
367 			    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
368 				u16 spec;
369 
370 				/* Enable Class A driver for FE+ A0 */
371 				spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
372 				spec |= PHY_M_FESC_SEL_CL_A;
373 				gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
374 			}
375 		} else {
376 			/* disable energy detect */
377 			ctrl &= ~PHY_M_PC_EN_DET_MSK;
378 
379 			/* enable automatic crossover */
380 			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
381 
382 			/* downshift on PHY 88E1112 and 88E1149 is changed */
383 			if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
384 			     (hw->flags & SKY2_HW_NEWER_PHY)) {
385 				/* set downshift counter to 3x and enable downshift */
386 				ctrl &= ~PHY_M_PC_DSC_MSK;
387 				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
388 			}
389 		}
390 	} else {
391 		/* workaround for deviation #4.88 (CRC errors) */
392 		/* disable Automatic Crossover */
393 
394 		ctrl &= ~PHY_M_PC_MDIX_MSK;
395 	}
396 
397 	gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
398 
399 	/* special setup for PHY 88E1112 Fiber */
400 	if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
401 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
402 
403 		/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
404 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
405 		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
406 		ctrl &= ~PHY_M_MAC_MD_MSK;
407 		ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
408 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
409 
410 		if (hw->pmd_type  == 'P') {
411 			/* select page 1 to access Fiber registers */
412 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
413 
414 			/* for SFP-module set SIGDET polarity to low */
415 			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
416 			ctrl |= PHY_M_FIB_SIGD_POL;
417 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
418 		}
419 
420 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
421 	}
422 
423 	ctrl = PHY_CT_RESET;
424 	ct1000 = 0;
425 	adv = PHY_AN_CSMA;
426 	reg = 0;
427 
428 	if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
429 		if (sky2_is_copper(hw)) {
430 			if (sky2->advertising & ADVERTISED_1000baseT_Full)
431 				ct1000 |= PHY_M_1000C_AFD;
432 			if (sky2->advertising & ADVERTISED_1000baseT_Half)
433 				ct1000 |= PHY_M_1000C_AHD;
434 			if (sky2->advertising & ADVERTISED_100baseT_Full)
435 				adv |= PHY_M_AN_100_FD;
436 			if (sky2->advertising & ADVERTISED_100baseT_Half)
437 				adv |= PHY_M_AN_100_HD;
438 			if (sky2->advertising & ADVERTISED_10baseT_Full)
439 				adv |= PHY_M_AN_10_FD;
440 			if (sky2->advertising & ADVERTISED_10baseT_Half)
441 				adv |= PHY_M_AN_10_HD;
442 
443 		} else {	/* special defines for FIBER (88E1040S only) */
444 			if (sky2->advertising & ADVERTISED_1000baseT_Full)
445 				adv |= PHY_M_AN_1000X_AFD;
446 			if (sky2->advertising & ADVERTISED_1000baseT_Half)
447 				adv |= PHY_M_AN_1000X_AHD;
448 		}
449 
450 		/* Restart Auto-negotiation */
451 		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
452 	} else {
453 		/* forced speed/duplex settings */
454 		ct1000 = PHY_M_1000C_MSE;
455 
456 		/* Disable auto update for duplex flow control and duplex */
457 		reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
458 
459 		switch (sky2->speed) {
460 		case SPEED_1000:
461 			ctrl |= PHY_CT_SP1000;
462 			reg |= GM_GPCR_SPEED_1000;
463 			break;
464 		case SPEED_100:
465 			ctrl |= PHY_CT_SP100;
466 			reg |= GM_GPCR_SPEED_100;
467 			break;
468 		}
469 
470 		if (sky2->duplex == DUPLEX_FULL) {
471 			reg |= GM_GPCR_DUP_FULL;
472 			ctrl |= PHY_CT_DUP_MD;
473 		} else if (sky2->speed < SPEED_1000)
474 			sky2->flow_mode = FC_NONE;
475 	}
476 
477 	if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
478 		if (sky2_is_copper(hw))
479 			adv |= copper_fc_adv[sky2->flow_mode];
480 		else
481 			adv |= fiber_fc_adv[sky2->flow_mode];
482 	} else {
483 		reg |= GM_GPCR_AU_FCT_DIS;
484  		reg |= gm_fc_disable[sky2->flow_mode];
485 
486 		/* Forward pause packets to GMAC? */
487 		if (sky2->flow_mode & FC_RX)
488 			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
489 		else
490 			sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
491 	}
492 
493 	gma_write16(hw, port, GM_GP_CTRL, reg);
494 
495 	if (hw->flags & SKY2_HW_GIGABIT)
496 		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
497 
498 	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
499 	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
500 
501 	/* Setup Phy LED's */
502 	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
503 	ledover = 0;
504 
505 	switch (hw->chip_id) {
506 	case CHIP_ID_YUKON_FE:
507 		/* on 88E3082 these bits are at 11..9 (shifted left) */
508 		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
509 
510 		ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
511 
512 		/* delete ACT LED control bits */
513 		ctrl &= ~PHY_M_FELP_LED1_MSK;
514 		/* change ACT LED control to blink mode */
515 		ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
516 		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
517 		break;
518 
519 	case CHIP_ID_YUKON_FE_P:
520 		/* Enable Link Partner Next Page */
521 		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
522 		ctrl |= PHY_M_PC_ENA_LIP_NP;
523 
524 		/* disable Energy Detect and enable scrambler */
525 		ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
526 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
527 
528 		/* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
529 		ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
530 			PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
531 			PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
532 
533 		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
534 		break;
535 
536 	case CHIP_ID_YUKON_XL:
537 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
538 
539 		/* select page 3 to access LED control register */
540 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
541 
542 		/* set LED Function Control register */
543 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
544 			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
545 			      PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
546 			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
547 			      PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */
548 
549 		/* set Polarity Control register */
550 		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
551 			     (PHY_M_POLC_LS1_P_MIX(4) |
552 			      PHY_M_POLC_IS0_P_MIX(4) |
553 			      PHY_M_POLC_LOS_CTRL(2) |
554 			      PHY_M_POLC_INIT_CTRL(2) |
555 			      PHY_M_POLC_STA1_CTRL(2) |
556 			      PHY_M_POLC_STA0_CTRL(2)));
557 
558 		/* restore page register */
559 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
560 		break;
561 
562 	case CHIP_ID_YUKON_EC_U:
563 	case CHIP_ID_YUKON_EX:
564 	case CHIP_ID_YUKON_SUPR:
565 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
566 
567 		/* select page 3 to access LED control register */
568 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
569 
570 		/* set LED Function Control register */
571 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
572 			     (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
573 			      PHY_M_LEDC_INIT_CTRL(8) |	/* 10 Mbps */
574 			      PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
575 			      PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
576 
577 		/* set Blink Rate in LED Timer Control Register */
578 		gm_phy_write(hw, port, PHY_MARV_INT_MASK,
579 			     ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
580 		/* restore page register */
581 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
582 		break;
583 
584 	default:
585 		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
586 		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
587 
588 		/* turn off the Rx LED (LED_RX) */
589 		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
590 	}
591 
592 	if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
593 		/* apply fixes in PHY AFE */
594 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
595 
596 		/* increase differential signal amplitude in 10BASE-T */
597 		gm_phy_write(hw, port, 0x18, 0xaa99);
598 		gm_phy_write(hw, port, 0x17, 0x2011);
599 
600 		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
601 			/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
602 			gm_phy_write(hw, port, 0x18, 0xa204);
603 			gm_phy_write(hw, port, 0x17, 0x2002);
604 		}
605 
606 		/* set page register to 0 */
607 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
608 	} else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
609 		   hw->chip_rev == CHIP_REV_YU_FE2_A0) {
610 		/* apply workaround for integrated resistors calibration */
611 		gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
612 		gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
613 	} else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
614 		/* apply fixes in PHY AFE */
615 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
616 
617 		/* apply RDAC termination workaround */
618 		gm_phy_write(hw, port, 24, 0x2800);
619 		gm_phy_write(hw, port, 23, 0x2001);
620 
621 		/* set page register back to 0 */
622 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
623 	} else if (hw->chip_id != CHIP_ID_YUKON_EX &&
624 		   hw->chip_id < CHIP_ID_YUKON_SUPR) {
625 		/* no effect on Yukon-XL */
626 		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
627 
628 		if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
629 		    sky2->speed == SPEED_100) {
630 			/* turn on 100 Mbps LED (LED_LINK100) */
631 			ledover |= PHY_M_LED_MO_100(MO_LED_ON);
632 		}
633 
634 		if (ledover)
635 			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
636 
637 	} else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
638 		   (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
639 		int i;
640 		/* This a phy register setup workaround copied from vendor driver. */
641 		static const struct {
642 			u16 reg, val;
643 		} eee_afe[] = {
644 			{ 0x156, 0x58ce },
645 			{ 0x153, 0x99eb },
646 			{ 0x141, 0x8064 },
647 			/* { 0x155, 0x130b },*/
648 			{ 0x000, 0x0000 },
649 			{ 0x151, 0x8433 },
650 			{ 0x14b, 0x8c44 },
651 			{ 0x14c, 0x0f90 },
652 			{ 0x14f, 0x39aa },
653 			/* { 0x154, 0x2f39 },*/
654 			{ 0x14d, 0xba33 },
655 			{ 0x144, 0x0048 },
656 			{ 0x152, 0x2010 },
657 			/* { 0x158, 0x1223 },*/
658 			{ 0x140, 0x4444 },
659 			{ 0x154, 0x2f3b },
660 			{ 0x158, 0xb203 },
661 			{ 0x157, 0x2029 },
662 		};
663 
664 		/* Start Workaround for OptimaEEE Rev.Z0 */
665 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
666 
667 		gm_phy_write(hw, port,  1, 0x4099);
668 		gm_phy_write(hw, port,  3, 0x1120);
669 		gm_phy_write(hw, port, 11, 0x113c);
670 		gm_phy_write(hw, port, 14, 0x8100);
671 		gm_phy_write(hw, port, 15, 0x112a);
672 		gm_phy_write(hw, port, 17, 0x1008);
673 
674 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
675 		gm_phy_write(hw, port,  1, 0x20b0);
676 
677 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
678 
679 		for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
680 			/* apply AFE settings */
681 			gm_phy_write(hw, port, 17, eee_afe[i].val);
682 			gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
683 		}
684 
685 		/* End Workaround for OptimaEEE */
686 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
687 
688 		/* Enable 10Base-Te (EEE) */
689 		if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
690 			reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
691 			gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
692 				     reg | PHY_M_10B_TE_ENABLE);
693 		}
694 	}
695 
696 	/* Enable phy interrupt on auto-negotiation complete (or link up) */
697 	if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
698 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
699 	else
700 		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
701 }
702 
703 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
704 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
705 
706 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
707 {
708 	u32 reg1;
709 
710 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
711 	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
712 	reg1 &= ~phy_power[port];
713 
714 	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
715 		reg1 |= coma_mode[port];
716 
717 	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
718 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
719 	sky2_pci_read32(hw, PCI_DEV_REG1);
720 
721 	if (hw->chip_id == CHIP_ID_YUKON_FE)
722 		gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
723 	else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
724 		sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
725 }
726 
727 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
728 {
729 	u32 reg1;
730 	u16 ctrl;
731 
732 	/* release GPHY Control reset */
733 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
734 
735 	/* release GMAC reset */
736 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
737 
738 	if (hw->flags & SKY2_HW_NEWER_PHY) {
739 		/* select page 2 to access MAC control register */
740 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
741 
742 		ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
743 		/* allow GMII Power Down */
744 		ctrl &= ~PHY_M_MAC_GMIF_PUP;
745 		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
746 
747 		/* set page register back to 0 */
748 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
749 	}
750 
751 	/* setup General Purpose Control Register */
752 	gma_write16(hw, port, GM_GP_CTRL,
753 		    GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
754 		    GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
755 		    GM_GPCR_AU_SPD_DIS);
756 
757 	if (hw->chip_id != CHIP_ID_YUKON_EC) {
758 		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
759 			/* select page 2 to access MAC control register */
760 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
761 
762 			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
763 			/* enable Power Down */
764 			ctrl |= PHY_M_PC_POW_D_ENA;
765 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
766 
767 			/* set page register back to 0 */
768 			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
769 		}
770 
771 		/* set IEEE compatible Power Down Mode (dev. #4.99) */
772 		gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
773 	}
774 
775 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
776 	reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
777 	reg1 |= phy_power[port];		/* set PHY to PowerDown/COMA Mode */
778 	sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
779 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
780 }
781 
782 /* configure IPG according to used link speed */
783 static void sky2_set_ipg(struct sky2_port *sky2)
784 {
785 	u16 reg;
786 
787 	reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
788 	reg &= ~GM_SMOD_IPG_MSK;
789 	if (sky2->speed > SPEED_100)
790 		reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
791 	else
792 		reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
793 	gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
794 }
795 
796 /* Enable Rx/Tx */
797 static void sky2_enable_rx_tx(struct sky2_port *sky2)
798 {
799 	struct sky2_hw *hw = sky2->hw;
800 	unsigned port = sky2->port;
801 	u16 reg;
802 
803 	reg = gma_read16(hw, port, GM_GP_CTRL);
804 	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
805 	gma_write16(hw, port, GM_GP_CTRL, reg);
806 }
807 
808 /* Force a renegotiation */
809 static void sky2_phy_reinit(struct sky2_port *sky2)
810 {
811 	spin_lock_bh(&sky2->phy_lock);
812 	sky2_phy_init(sky2->hw, sky2->port);
813 	sky2_enable_rx_tx(sky2);
814 	spin_unlock_bh(&sky2->phy_lock);
815 }
816 
817 /* Put device in state to listen for Wake On Lan */
818 static void sky2_wol_init(struct sky2_port *sky2)
819 {
820 	struct sky2_hw *hw = sky2->hw;
821 	unsigned port = sky2->port;
822 	enum flow_control save_mode;
823 	u16 ctrl;
824 
825 	/* Bring hardware out of reset */
826 	sky2_write16(hw, B0_CTST, CS_RST_CLR);
827 	sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
828 
829 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
830 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
831 
832 	/* Force to 10/100
833 	 * sky2_reset will re-enable on resume
834 	 */
835 	save_mode = sky2->flow_mode;
836 	ctrl = sky2->advertising;
837 
838 	sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
839 	sky2->flow_mode = FC_NONE;
840 
841 	spin_lock_bh(&sky2->phy_lock);
842 	sky2_phy_power_up(hw, port);
843 	sky2_phy_init(hw, port);
844 	spin_unlock_bh(&sky2->phy_lock);
845 
846 	sky2->flow_mode = save_mode;
847 	sky2->advertising = ctrl;
848 
849 	/* Set GMAC to no flow control and auto update for speed/duplex */
850 	gma_write16(hw, port, GM_GP_CTRL,
851 		    GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
852 		    GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
853 
854 	/* Set WOL address */
855 	memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
856 		    sky2->netdev->dev_addr, ETH_ALEN);
857 
858 	/* Turn on appropriate WOL control bits */
859 	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
860 	ctrl = 0;
861 	if (sky2->wol & WAKE_PHY)
862 		ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
863 	else
864 		ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
865 
866 	if (sky2->wol & WAKE_MAGIC)
867 		ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
868 	else
869 		ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
870 
871 	ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
872 	sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
873 
874 	/* Disable PiG firmware */
875 	sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
876 
877 	/* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
878 	if (legacy_pme) {
879 		u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
880 		reg1 |= PCI_Y2_PME_LEGACY;
881 		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
882 	}
883 
884 	/* block receiver */
885 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
886 	sky2_read32(hw, B0_CTST);
887 }
888 
889 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
890 {
891 	struct net_device *dev = hw->dev[port];
892 
893 	if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
894 	      hw->chip_rev != CHIP_REV_YU_EX_A0) ||
895 	     hw->chip_id >= CHIP_ID_YUKON_FE_P) {
896 		/* Yukon-Extreme B0 and further Extreme devices */
897 		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
898 	} else if (dev->mtu > ETH_DATA_LEN) {
899 		/* set Tx GMAC FIFO Almost Empty Threshold */
900 		sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
901 			     (ECU_JUMBO_WM << 16) | ECU_AE_THR);
902 
903 		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
904 	} else
905 		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
906 }
907 
908 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
909 {
910 	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
911 	u16 reg;
912 	u32 rx_reg;
913 	int i;
914 	const u8 *addr = hw->dev[port]->dev_addr;
915 
916 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
917 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
918 
919 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
920 
921 	if (hw->chip_id == CHIP_ID_YUKON_XL &&
922 	    hw->chip_rev == CHIP_REV_YU_XL_A0 &&
923 	    port == 1) {
924 		/* WA DEV_472 -- looks like crossed wires on port 2 */
925 		/* clear GMAC 1 Control reset */
926 		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
927 		do {
928 			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
929 			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
930 		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
931 			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
932 			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
933 	}
934 
935 	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
936 
937 	/* Enable Transmit FIFO Underrun */
938 	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
939 
940 	spin_lock_bh(&sky2->phy_lock);
941 	sky2_phy_power_up(hw, port);
942 	sky2_phy_init(hw, port);
943 	spin_unlock_bh(&sky2->phy_lock);
944 
945 	/* MIB clear */
946 	reg = gma_read16(hw, port, GM_PHY_ADDR);
947 	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
948 
949 	for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
950 		gma_read16(hw, port, i);
951 	gma_write16(hw, port, GM_PHY_ADDR, reg);
952 
953 	/* transmit control */
954 	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
955 
956 	/* receive control reg: unicast + multicast + no FCS  */
957 	gma_write16(hw, port, GM_RX_CTRL,
958 		    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
959 
960 	/* transmit flow control */
961 	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
962 
963 	/* transmit parameter */
964 	gma_write16(hw, port, GM_TX_PARAM,
965 		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
966 		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
967 		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
968 		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
969 
970 	/* serial mode register */
971 	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
972 		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
973 
974 	if (hw->dev[port]->mtu > ETH_DATA_LEN)
975 		reg |= GM_SMOD_JUMBO_ENA;
976 
977 	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
978 	    hw->chip_rev == CHIP_REV_YU_EC_U_B1)
979 		reg |= GM_NEW_FLOW_CTRL;
980 
981 	gma_write16(hw, port, GM_SERIAL_MODE, reg);
982 
983 	/* virtual address for data */
984 	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
985 
986 	/* physical address: used for pause frames */
987 	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
988 
989 	/* ignore counter overflows */
990 	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
991 	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
992 	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
993 
994 	/* Configure Rx MAC FIFO */
995 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
996 	rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
997 	if (hw->chip_id == CHIP_ID_YUKON_EX ||
998 	    hw->chip_id == CHIP_ID_YUKON_FE_P)
999 		rx_reg |= GMF_RX_OVER_ON;
1000 
1001 	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1002 
1003 	if (hw->chip_id == CHIP_ID_YUKON_XL) {
1004 		/* Hardware errata - clear flush mask */
1005 		sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1006 	} else {
1007 		/* Flush Rx MAC FIFO on any flow control or error */
1008 		sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1009 	}
1010 
1011 	/* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug  */
1012 	reg = RX_GMF_FL_THR_DEF + 1;
1013 	/* Another magic mystery workaround from sk98lin */
1014 	if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1015 	    hw->chip_rev == CHIP_REV_YU_FE2_A0)
1016 		reg = 0x178;
1017 	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1018 
1019 	/* Configure Tx MAC FIFO */
1020 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1021 	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1022 
1023 	/* On chips without ram buffer, pause is controlled by MAC level */
1024 	if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1025 		/* Pause threshold is scaled by 8 in bytes */
1026 		if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1027 		    hw->chip_rev == CHIP_REV_YU_FE2_A0)
1028 			reg = 1568 / 8;
1029 		else
1030 			reg = 1024 / 8;
1031 		sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1032 		sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1033 
1034 		sky2_set_tx_stfwd(hw, port);
1035 	}
1036 
1037 	if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1038 	    hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1039 		/* disable dynamic watermark */
1040 		reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1041 		reg &= ~TX_DYN_WM_ENA;
1042 		sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1043 	}
1044 }
1045 
1046 /* Assign Ram Buffer allocation to queue */
1047 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1048 {
1049 	u32 end;
1050 
1051 	/* convert from K bytes to qwords used for hw register */
1052 	start *= 1024/8;
1053 	space *= 1024/8;
1054 	end = start + space - 1;
1055 
1056 	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1057 	sky2_write32(hw, RB_ADDR(q, RB_START), start);
1058 	sky2_write32(hw, RB_ADDR(q, RB_END), end);
1059 	sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1060 	sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1061 
1062 	if (q == Q_R1 || q == Q_R2) {
1063 		u32 tp = space - space/4;
1064 
1065 		/* On receive queue's set the thresholds
1066 		 * give receiver priority when > 3/4 full
1067 		 * send pause when down to 2K
1068 		 */
1069 		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1070 		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1071 
1072 		tp = space - 8192/8;
1073 		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1074 		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1075 	} else {
1076 		/* Enable store & forward on Tx queue's because
1077 		 * Tx FIFO is only 1K on Yukon
1078 		 */
1079 		sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1080 	}
1081 
1082 	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1083 	sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1084 }
1085 
1086 /* Setup Bus Memory Interface */
1087 static void sky2_qset(struct sky2_hw *hw, u16 q)
1088 {
1089 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1090 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1091 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1092 	sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
1093 }
1094 
1095 /* Setup prefetch unit registers. This is the interface between
1096  * hardware and driver list elements
1097  */
1098 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1099 			       dma_addr_t addr, u32 last)
1100 {
1101 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1102 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1103 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1104 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1105 	sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1106 	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1107 
1108 	sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1109 }
1110 
1111 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1112 {
1113 	struct sky2_tx_le *le = sky2->tx_le + *slot;
1114 
1115 	*slot = RING_NEXT(*slot, sky2->tx_ring_size);
1116 	le->ctrl = 0;
1117 	return le;
1118 }
1119 
1120 static void tx_init(struct sky2_port *sky2)
1121 {
1122 	struct sky2_tx_le *le;
1123 
1124 	sky2->tx_prod = sky2->tx_cons = 0;
1125 	sky2->tx_tcpsum = 0;
1126 	sky2->tx_last_mss = 0;
1127 	netdev_reset_queue(sky2->netdev);
1128 
1129 	le = get_tx_le(sky2, &sky2->tx_prod);
1130 	le->addr = 0;
1131 	le->opcode = OP_ADDR64 | HW_OWNER;
1132 	sky2->tx_last_upper = 0;
1133 }
1134 
1135 /* Update chip's next pointer */
1136 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1137 {
1138 	/* Make sure write' to descriptors are complete before we tell hardware */
1139 	wmb();
1140 	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1141 
1142 	/* Synchronize I/O on since next processor may write to tail */
1143 	mmiowb();
1144 }
1145 
1146 
1147 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1148 {
1149 	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1150 	sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1151 	le->ctrl = 0;
1152 	return le;
1153 }
1154 
1155 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1156 {
1157 	unsigned size;
1158 
1159 	/* Space needed for frame data + headers rounded up */
1160 	size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1161 
1162 	/* Stopping point for hardware truncation */
1163 	return (size - 8) / sizeof(u32);
1164 }
1165 
1166 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1167 {
1168 	struct rx_ring_info *re;
1169 	unsigned size;
1170 
1171 	/* Space needed for frame data + headers rounded up */
1172 	size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1173 
1174 	sky2->rx_nfrags = size >> PAGE_SHIFT;
1175 	BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1176 
1177 	/* Compute residue after pages */
1178 	size -= sky2->rx_nfrags << PAGE_SHIFT;
1179 
1180 	/* Optimize to handle small packets and headers */
1181 	if (size < copybreak)
1182 		size = copybreak;
1183 	if (size < ETH_HLEN)
1184 		size = ETH_HLEN;
1185 
1186 	return size;
1187 }
1188 
1189 /* Build description to hardware for one receive segment */
1190 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1191 			dma_addr_t map, unsigned len)
1192 {
1193 	struct sky2_rx_le *le;
1194 
1195 	if (sizeof(dma_addr_t) > sizeof(u32)) {
1196 		le = sky2_next_rx(sky2);
1197 		le->addr = cpu_to_le32(upper_32_bits(map));
1198 		le->opcode = OP_ADDR64 | HW_OWNER;
1199 	}
1200 
1201 	le = sky2_next_rx(sky2);
1202 	le->addr = cpu_to_le32(lower_32_bits(map));
1203 	le->length = cpu_to_le16(len);
1204 	le->opcode = op | HW_OWNER;
1205 }
1206 
1207 /* Build description to hardware for one possibly fragmented skb */
1208 static void sky2_rx_submit(struct sky2_port *sky2,
1209 			   const struct rx_ring_info *re)
1210 {
1211 	int i;
1212 
1213 	sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1214 
1215 	for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1216 		sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1217 }
1218 
1219 
1220 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1221 			    unsigned size)
1222 {
1223 	struct sk_buff *skb = re->skb;
1224 	int i;
1225 
1226 	re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1227 	if (pci_dma_mapping_error(pdev, re->data_addr))
1228 		goto mapping_error;
1229 
1230 	dma_unmap_len_set(re, data_size, size);
1231 
1232 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1233 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1234 
1235 		re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1236 						    skb_frag_size(frag),
1237 						    DMA_FROM_DEVICE);
1238 
1239 		if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1240 			goto map_page_error;
1241 	}
1242 	return 0;
1243 
1244 map_page_error:
1245 	while (--i >= 0) {
1246 		pci_unmap_page(pdev, re->frag_addr[i],
1247 			       skb_frag_size(&skb_shinfo(skb)->frags[i]),
1248 			       PCI_DMA_FROMDEVICE);
1249 	}
1250 
1251 	pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1252 			 PCI_DMA_FROMDEVICE);
1253 
1254 mapping_error:
1255 	if (net_ratelimit())
1256 		dev_warn(&pdev->dev, "%s: rx mapping error\n",
1257 			 skb->dev->name);
1258 	return -EIO;
1259 }
1260 
1261 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1262 {
1263 	struct sk_buff *skb = re->skb;
1264 	int i;
1265 
1266 	pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1267 			 PCI_DMA_FROMDEVICE);
1268 
1269 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1270 		pci_unmap_page(pdev, re->frag_addr[i],
1271 			       skb_frag_size(&skb_shinfo(skb)->frags[i]),
1272 			       PCI_DMA_FROMDEVICE);
1273 }
1274 
1275 /* Tell chip where to start receive checksum.
1276  * Actually has two checksums, but set both same to avoid possible byte
1277  * order problems.
1278  */
1279 static void rx_set_checksum(struct sky2_port *sky2)
1280 {
1281 	struct sky2_rx_le *le = sky2_next_rx(sky2);
1282 
1283 	le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1284 	le->ctrl = 0;
1285 	le->opcode = OP_TCPSTART | HW_OWNER;
1286 
1287 	sky2_write32(sky2->hw,
1288 		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1289 		     (sky2->netdev->features & NETIF_F_RXCSUM)
1290 		     ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1291 }
1292 
1293 /*
1294  * Fixed initial key as seed to RSS.
1295  */
1296 static const uint32_t rss_init_key[10] = {
1297 	0x7c3351da, 0x51c5cf4e,	0x44adbdd1, 0xe8d38d18,	0x48897c43,
1298 	0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1299 };
1300 
1301 /* Enable/disable receive hash calculation (RSS) */
1302 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1303 {
1304 	struct sky2_port *sky2 = netdev_priv(dev);
1305 	struct sky2_hw *hw = sky2->hw;
1306 	int i, nkeys = 4;
1307 
1308 	/* Supports IPv6 and other modes */
1309 	if (hw->flags & SKY2_HW_NEW_LE) {
1310 		nkeys = 10;
1311 		sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1312 	}
1313 
1314 	/* Program RSS initial values */
1315 	if (features & NETIF_F_RXHASH) {
1316 		for (i = 0; i < nkeys; i++)
1317 			sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1318 				     rss_init_key[i]);
1319 
1320 		/* Need to turn on (undocumented) flag to make hashing work  */
1321 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1322 			     RX_STFW_ENA);
1323 
1324 		sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1325 			     BMU_ENA_RX_RSS_HASH);
1326 	} else
1327 		sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1328 			     BMU_DIS_RX_RSS_HASH);
1329 }
1330 
1331 /*
1332  * The RX Stop command will not work for Yukon-2 if the BMU does not
1333  * reach the end of packet and since we can't make sure that we have
1334  * incoming data, we must reset the BMU while it is not doing a DMA
1335  * transfer. Since it is possible that the RX path is still active,
1336  * the RX RAM buffer will be stopped first, so any possible incoming
1337  * data will not trigger a DMA. After the RAM buffer is stopped, the
1338  * BMU is polled until any DMA in progress is ended and only then it
1339  * will be reset.
1340  */
1341 static void sky2_rx_stop(struct sky2_port *sky2)
1342 {
1343 	struct sky2_hw *hw = sky2->hw;
1344 	unsigned rxq = rxqaddr[sky2->port];
1345 	int i;
1346 
1347 	/* disable the RAM Buffer receive queue */
1348 	sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1349 
1350 	for (i = 0; i < 0xffff; i++)
1351 		if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1352 		    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1353 			goto stopped;
1354 
1355 	netdev_warn(sky2->netdev, "receiver stop failed\n");
1356 stopped:
1357 	sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1358 
1359 	/* reset the Rx prefetch unit */
1360 	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1361 	mmiowb();
1362 }
1363 
1364 /* Clean out receive buffer area, assumes receiver hardware stopped */
1365 static void sky2_rx_clean(struct sky2_port *sky2)
1366 {
1367 	unsigned i;
1368 
1369 	memset(sky2->rx_le, 0, RX_LE_BYTES);
1370 	for (i = 0; i < sky2->rx_pending; i++) {
1371 		struct rx_ring_info *re = sky2->rx_ring + i;
1372 
1373 		if (re->skb) {
1374 			sky2_rx_unmap_skb(sky2->hw->pdev, re);
1375 			kfree_skb(re->skb);
1376 			re->skb = NULL;
1377 		}
1378 	}
1379 }
1380 
1381 /* Basic MII support */
1382 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1383 {
1384 	struct mii_ioctl_data *data = if_mii(ifr);
1385 	struct sky2_port *sky2 = netdev_priv(dev);
1386 	struct sky2_hw *hw = sky2->hw;
1387 	int err = -EOPNOTSUPP;
1388 
1389 	if (!netif_running(dev))
1390 		return -ENODEV;	/* Phy still in reset */
1391 
1392 	switch (cmd) {
1393 	case SIOCGMIIPHY:
1394 		data->phy_id = PHY_ADDR_MARV;
1395 
1396 		/* fallthru */
1397 	case SIOCGMIIREG: {
1398 		u16 val = 0;
1399 
1400 		spin_lock_bh(&sky2->phy_lock);
1401 		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1402 		spin_unlock_bh(&sky2->phy_lock);
1403 
1404 		data->val_out = val;
1405 		break;
1406 	}
1407 
1408 	case SIOCSMIIREG:
1409 		spin_lock_bh(&sky2->phy_lock);
1410 		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1411 				   data->val_in);
1412 		spin_unlock_bh(&sky2->phy_lock);
1413 		break;
1414 	}
1415 	return err;
1416 }
1417 
1418 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1419 
1420 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1421 {
1422 	struct sky2_port *sky2 = netdev_priv(dev);
1423 	struct sky2_hw *hw = sky2->hw;
1424 	u16 port = sky2->port;
1425 
1426 	if (features & NETIF_F_HW_VLAN_CTAG_RX)
1427 		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1428 			     RX_VLAN_STRIP_ON);
1429 	else
1430 		sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1431 			     RX_VLAN_STRIP_OFF);
1432 
1433 	if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1434 		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1435 			     TX_VLAN_TAG_ON);
1436 
1437 		dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1438 	} else {
1439 		sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1440 			     TX_VLAN_TAG_OFF);
1441 
1442 		/* Can't do transmit offload of vlan without hw vlan */
1443 		dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1444 	}
1445 }
1446 
1447 /* Amount of required worst case padding in rx buffer */
1448 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1449 {
1450 	return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1451 }
1452 
1453 /*
1454  * Allocate an skb for receiving. If the MTU is large enough
1455  * make the skb non-linear with a fragment list of pages.
1456  */
1457 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1458 {
1459 	struct sk_buff *skb;
1460 	int i;
1461 
1462 	skb = __netdev_alloc_skb(sky2->netdev,
1463 				 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1464 				 gfp);
1465 	if (!skb)
1466 		goto nomem;
1467 
1468 	if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1469 		unsigned char *start;
1470 		/*
1471 		 * Workaround for a bug in FIFO that cause hang
1472 		 * if the FIFO if the receive buffer is not 64 byte aligned.
1473 		 * The buffer returned from netdev_alloc_skb is
1474 		 * aligned except if slab debugging is enabled.
1475 		 */
1476 		start = PTR_ALIGN(skb->data, 8);
1477 		skb_reserve(skb, start - skb->data);
1478 	} else
1479 		skb_reserve(skb, NET_IP_ALIGN);
1480 
1481 	for (i = 0; i < sky2->rx_nfrags; i++) {
1482 		struct page *page = alloc_page(gfp);
1483 
1484 		if (!page)
1485 			goto free_partial;
1486 		skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1487 	}
1488 
1489 	return skb;
1490 free_partial:
1491 	kfree_skb(skb);
1492 nomem:
1493 	return NULL;
1494 }
1495 
1496 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1497 {
1498 	sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1499 }
1500 
1501 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1502 {
1503 	struct sky2_hw *hw = sky2->hw;
1504 	unsigned i;
1505 
1506 	sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1507 
1508 	/* Fill Rx ring */
1509 	for (i = 0; i < sky2->rx_pending; i++) {
1510 		struct rx_ring_info *re = sky2->rx_ring + i;
1511 
1512 		re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1513 		if (!re->skb)
1514 			return -ENOMEM;
1515 
1516 		if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1517 			dev_kfree_skb(re->skb);
1518 			re->skb = NULL;
1519 			return -ENOMEM;
1520 		}
1521 	}
1522 	return 0;
1523 }
1524 
1525 /*
1526  * Setup receiver buffer pool.
1527  * Normal case this ends up creating one list element for skb
1528  * in the receive ring. Worst case if using large MTU and each
1529  * allocation falls on a different 64 bit region, that results
1530  * in 6 list elements per ring entry.
1531  * One element is used for checksum enable/disable, and one
1532  * extra to avoid wrap.
1533  */
1534 static void sky2_rx_start(struct sky2_port *sky2)
1535 {
1536 	struct sky2_hw *hw = sky2->hw;
1537 	struct rx_ring_info *re;
1538 	unsigned rxq = rxqaddr[sky2->port];
1539 	unsigned i, thresh;
1540 
1541 	sky2->rx_put = sky2->rx_next = 0;
1542 	sky2_qset(hw, rxq);
1543 
1544 	/* On PCI express lowering the watermark gives better performance */
1545 	if (pci_is_pcie(hw->pdev))
1546 		sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1547 
1548 	/* These chips have no ram buffer?
1549 	 * MAC Rx RAM Read is controlled by hardware */
1550 	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1551 	    hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1552 		sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1553 
1554 	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1555 
1556 	if (!(hw->flags & SKY2_HW_NEW_LE))
1557 		rx_set_checksum(sky2);
1558 
1559 	if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1560 		rx_set_rss(sky2->netdev, sky2->netdev->features);
1561 
1562 	/* submit Rx ring */
1563 	for (i = 0; i < sky2->rx_pending; i++) {
1564 		re = sky2->rx_ring + i;
1565 		sky2_rx_submit(sky2, re);
1566 	}
1567 
1568 	/*
1569 	 * The receiver hangs if it receives frames larger than the
1570 	 * packet buffer. As a workaround, truncate oversize frames, but
1571 	 * the register is limited to 9 bits, so if you do frames > 2052
1572 	 * you better get the MTU right!
1573 	 */
1574 	thresh = sky2_get_rx_threshold(sky2);
1575 	if (thresh > 0x1ff)
1576 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1577 	else {
1578 		sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1579 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1580 	}
1581 
1582 	/* Tell chip about available buffers */
1583 	sky2_rx_update(sky2, rxq);
1584 
1585 	if (hw->chip_id == CHIP_ID_YUKON_EX ||
1586 	    hw->chip_id == CHIP_ID_YUKON_SUPR) {
1587 		/*
1588 		 * Disable flushing of non ASF packets;
1589 		 * must be done after initializing the BMUs;
1590 		 * drivers without ASF support should do this too, otherwise
1591 		 * it may happen that they cannot run on ASF devices;
1592 		 * remember that the MAC FIFO isn't reset during initialization.
1593 		 */
1594 		sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1595 	}
1596 
1597 	if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1598 		/* Enable RX Home Address & Routing Header checksum fix */
1599 		sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1600 			     RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1601 
1602 		/* Enable TX Home Address & Routing Header checksum fix */
1603 		sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1604 			     TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1605 	}
1606 }
1607 
1608 static int sky2_alloc_buffers(struct sky2_port *sky2)
1609 {
1610 	struct sky2_hw *hw = sky2->hw;
1611 
1612 	/* must be power of 2 */
1613 	sky2->tx_le = pci_alloc_consistent(hw->pdev,
1614 					   sky2->tx_ring_size *
1615 					   sizeof(struct sky2_tx_le),
1616 					   &sky2->tx_le_map);
1617 	if (!sky2->tx_le)
1618 		goto nomem;
1619 
1620 	sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1621 				GFP_KERNEL);
1622 	if (!sky2->tx_ring)
1623 		goto nomem;
1624 
1625 	sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES,
1626 					    &sky2->rx_le_map);
1627 	if (!sky2->rx_le)
1628 		goto nomem;
1629 
1630 	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1631 				GFP_KERNEL);
1632 	if (!sky2->rx_ring)
1633 		goto nomem;
1634 
1635 	return sky2_alloc_rx_skbs(sky2);
1636 nomem:
1637 	return -ENOMEM;
1638 }
1639 
1640 static void sky2_free_buffers(struct sky2_port *sky2)
1641 {
1642 	struct sky2_hw *hw = sky2->hw;
1643 
1644 	sky2_rx_clean(sky2);
1645 
1646 	if (sky2->rx_le) {
1647 		pci_free_consistent(hw->pdev, RX_LE_BYTES,
1648 				    sky2->rx_le, sky2->rx_le_map);
1649 		sky2->rx_le = NULL;
1650 	}
1651 	if (sky2->tx_le) {
1652 		pci_free_consistent(hw->pdev,
1653 				    sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1654 				    sky2->tx_le, sky2->tx_le_map);
1655 		sky2->tx_le = NULL;
1656 	}
1657 	kfree(sky2->tx_ring);
1658 	kfree(sky2->rx_ring);
1659 
1660 	sky2->tx_ring = NULL;
1661 	sky2->rx_ring = NULL;
1662 }
1663 
1664 static void sky2_hw_up(struct sky2_port *sky2)
1665 {
1666 	struct sky2_hw *hw = sky2->hw;
1667 	unsigned port = sky2->port;
1668 	u32 ramsize;
1669 	int cap;
1670 	struct net_device *otherdev = hw->dev[sky2->port^1];
1671 
1672 	tx_init(sky2);
1673 
1674 	/*
1675  	 * On dual port PCI-X card, there is an problem where status
1676 	 * can be received out of order due to split transactions
1677 	 */
1678 	if (otherdev && netif_running(otherdev) &&
1679  	    (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1680  		u16 cmd;
1681 
1682 		cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1683  		cmd &= ~PCI_X_CMD_MAX_SPLIT;
1684  		sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1685 	}
1686 
1687 	sky2_mac_init(hw, port);
1688 
1689 	/* Register is number of 4K blocks on internal RAM buffer. */
1690 	ramsize = sky2_read8(hw, B2_E_0) * 4;
1691 	if (ramsize > 0) {
1692 		u32 rxspace;
1693 
1694 		netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1695 		if (ramsize < 16)
1696 			rxspace = ramsize / 2;
1697 		else
1698 			rxspace = 8 + (2*(ramsize - 16))/3;
1699 
1700 		sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1701 		sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1702 
1703 		/* Make sure SyncQ is disabled */
1704 		sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1705 			    RB_RST_SET);
1706 	}
1707 
1708 	sky2_qset(hw, txqaddr[port]);
1709 
1710 	/* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1711 	if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1712 		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1713 
1714 	/* Set almost empty threshold */
1715 	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1716 	    hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1717 		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1718 
1719 	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1720 			   sky2->tx_ring_size - 1);
1721 
1722 	sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1723 	netdev_update_features(sky2->netdev);
1724 
1725 	sky2_rx_start(sky2);
1726 }
1727 
1728 /* Setup device IRQ and enable napi to process */
1729 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1730 {
1731 	struct pci_dev *pdev = hw->pdev;
1732 	int err;
1733 
1734 	err = request_irq(pdev->irq, sky2_intr,
1735 			  (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1736 			  name, hw);
1737 	if (err)
1738 		dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1739 	else {
1740 		hw->flags |= SKY2_HW_IRQ_SETUP;
1741 
1742 		napi_enable(&hw->napi);
1743 		sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1744 		sky2_read32(hw, B0_IMSK);
1745 	}
1746 
1747 	return err;
1748 }
1749 
1750 
1751 /* Bring up network interface. */
1752 static int sky2_open(struct net_device *dev)
1753 {
1754 	struct sky2_port *sky2 = netdev_priv(dev);
1755 	struct sky2_hw *hw = sky2->hw;
1756 	unsigned port = sky2->port;
1757 	u32 imask;
1758 	int err;
1759 
1760 	netif_carrier_off(dev);
1761 
1762 	err = sky2_alloc_buffers(sky2);
1763 	if (err)
1764 		goto err_out;
1765 
1766 	/* With single port, IRQ is setup when device is brought up */
1767 	if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1768 		goto err_out;
1769 
1770 	sky2_hw_up(sky2);
1771 
1772 	/* Enable interrupts from phy/mac for port */
1773 	imask = sky2_read32(hw, B0_IMSK);
1774 
1775 	if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1776 	    hw->chip_id == CHIP_ID_YUKON_PRM ||
1777 	    hw->chip_id == CHIP_ID_YUKON_OP_2)
1778 		imask |= Y2_IS_PHY_QLNK;	/* enable PHY Quick Link */
1779 
1780 	imask |= portirq_msk[port];
1781 	sky2_write32(hw, B0_IMSK, imask);
1782 	sky2_read32(hw, B0_IMSK);
1783 
1784 	netif_info(sky2, ifup, dev, "enabling interface\n");
1785 
1786 	return 0;
1787 
1788 err_out:
1789 	sky2_free_buffers(sky2);
1790 	return err;
1791 }
1792 
1793 /* Modular subtraction in ring */
1794 static inline int tx_inuse(const struct sky2_port *sky2)
1795 {
1796 	return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1797 }
1798 
1799 /* Number of list elements available for next tx */
1800 static inline int tx_avail(const struct sky2_port *sky2)
1801 {
1802 	return sky2->tx_pending - tx_inuse(sky2);
1803 }
1804 
1805 /* Estimate of number of transmit list elements required */
1806 static unsigned tx_le_req(const struct sk_buff *skb)
1807 {
1808 	unsigned count;
1809 
1810 	count = (skb_shinfo(skb)->nr_frags + 1)
1811 		* (sizeof(dma_addr_t) / sizeof(u32));
1812 
1813 	if (skb_is_gso(skb))
1814 		++count;
1815 	else if (sizeof(dma_addr_t) == sizeof(u32))
1816 		++count;	/* possible vlan */
1817 
1818 	if (skb->ip_summed == CHECKSUM_PARTIAL)
1819 		++count;
1820 
1821 	return count;
1822 }
1823 
1824 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1825 {
1826 	if (re->flags & TX_MAP_SINGLE)
1827 		pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1828 				 dma_unmap_len(re, maplen),
1829 				 PCI_DMA_TODEVICE);
1830 	else if (re->flags & TX_MAP_PAGE)
1831 		pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1832 			       dma_unmap_len(re, maplen),
1833 			       PCI_DMA_TODEVICE);
1834 	re->flags = 0;
1835 }
1836 
1837 /*
1838  * Put one packet in ring for transmit.
1839  * A single packet can generate multiple list elements, and
1840  * the number of ring elements will probably be less than the number
1841  * of list elements used.
1842  */
1843 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1844 				   struct net_device *dev)
1845 {
1846 	struct sky2_port *sky2 = netdev_priv(dev);
1847 	struct sky2_hw *hw = sky2->hw;
1848 	struct sky2_tx_le *le = NULL;
1849 	struct tx_ring_info *re;
1850 	unsigned i, len;
1851 	dma_addr_t mapping;
1852 	u32 upper;
1853 	u16 slot;
1854 	u16 mss;
1855 	u8 ctrl;
1856 
1857  	if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1858   		return NETDEV_TX_BUSY;
1859 
1860 	len = skb_headlen(skb);
1861 	mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1862 
1863 	if (pci_dma_mapping_error(hw->pdev, mapping))
1864 		goto mapping_error;
1865 
1866 	slot = sky2->tx_prod;
1867 	netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1868 		     "tx queued, slot %u, len %d\n", slot, skb->len);
1869 
1870 	/* Send high bits if needed */
1871 	upper = upper_32_bits(mapping);
1872 	if (upper != sky2->tx_last_upper) {
1873 		le = get_tx_le(sky2, &slot);
1874 		le->addr = cpu_to_le32(upper);
1875 		sky2->tx_last_upper = upper;
1876 		le->opcode = OP_ADDR64 | HW_OWNER;
1877 	}
1878 
1879 	/* Check for TCP Segmentation Offload */
1880 	mss = skb_shinfo(skb)->gso_size;
1881 	if (mss != 0) {
1882 
1883 		if (!(hw->flags & SKY2_HW_NEW_LE))
1884 			mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1885 
1886   		if (mss != sky2->tx_last_mss) {
1887 			le = get_tx_le(sky2, &slot);
1888   			le->addr = cpu_to_le32(mss);
1889 
1890 			if (hw->flags & SKY2_HW_NEW_LE)
1891 				le->opcode = OP_MSS | HW_OWNER;
1892 			else
1893 				le->opcode = OP_LRGLEN | HW_OWNER;
1894 			sky2->tx_last_mss = mss;
1895 		}
1896 	}
1897 
1898 	ctrl = 0;
1899 
1900 	/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1901 	if (vlan_tx_tag_present(skb)) {
1902 		if (!le) {
1903 			le = get_tx_le(sky2, &slot);
1904 			le->addr = 0;
1905 			le->opcode = OP_VLAN|HW_OWNER;
1906 		} else
1907 			le->opcode |= OP_VLAN;
1908 		le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1909 		ctrl |= INS_VLAN;
1910 	}
1911 
1912 	/* Handle TCP checksum offload */
1913 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
1914 		/* On Yukon EX (some versions) encoding change. */
1915  		if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1916  			ctrl |= CALSUM;	/* auto checksum */
1917 		else {
1918 			const unsigned offset = skb_transport_offset(skb);
1919 			u32 tcpsum;
1920 
1921 			tcpsum = offset << 16;			/* sum start */
1922 			tcpsum |= offset + skb->csum_offset;	/* sum write */
1923 
1924 			ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1925 			if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1926 				ctrl |= UDPTCP;
1927 
1928 			if (tcpsum != sky2->tx_tcpsum) {
1929 				sky2->tx_tcpsum = tcpsum;
1930 
1931 				le = get_tx_le(sky2, &slot);
1932 				le->addr = cpu_to_le32(tcpsum);
1933 				le->length = 0;	/* initial checksum value */
1934 				le->ctrl = 1;	/* one packet */
1935 				le->opcode = OP_TCPLISW | HW_OWNER;
1936 			}
1937 		}
1938 	}
1939 
1940 	re = sky2->tx_ring + slot;
1941 	re->flags = TX_MAP_SINGLE;
1942 	dma_unmap_addr_set(re, mapaddr, mapping);
1943 	dma_unmap_len_set(re, maplen, len);
1944 
1945 	le = get_tx_le(sky2, &slot);
1946 	le->addr = cpu_to_le32(lower_32_bits(mapping));
1947 	le->length = cpu_to_le16(len);
1948 	le->ctrl = ctrl;
1949 	le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1950 
1951 
1952 	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1953 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1954 
1955 		mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1956 					   skb_frag_size(frag), DMA_TO_DEVICE);
1957 
1958 		if (dma_mapping_error(&hw->pdev->dev, mapping))
1959 			goto mapping_unwind;
1960 
1961 		upper = upper_32_bits(mapping);
1962 		if (upper != sky2->tx_last_upper) {
1963 			le = get_tx_le(sky2, &slot);
1964 			le->addr = cpu_to_le32(upper);
1965 			sky2->tx_last_upper = upper;
1966 			le->opcode = OP_ADDR64 | HW_OWNER;
1967 		}
1968 
1969 		re = sky2->tx_ring + slot;
1970 		re->flags = TX_MAP_PAGE;
1971 		dma_unmap_addr_set(re, mapaddr, mapping);
1972 		dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1973 
1974 		le = get_tx_le(sky2, &slot);
1975 		le->addr = cpu_to_le32(lower_32_bits(mapping));
1976 		le->length = cpu_to_le16(skb_frag_size(frag));
1977 		le->ctrl = ctrl;
1978 		le->opcode = OP_BUFFER | HW_OWNER;
1979 	}
1980 
1981 	re->skb = skb;
1982 	le->ctrl |= EOP;
1983 
1984 	sky2->tx_prod = slot;
1985 
1986 	if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1987 		netif_stop_queue(dev);
1988 
1989 	netdev_sent_queue(dev, skb->len);
1990 	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1991 
1992 	return NETDEV_TX_OK;
1993 
1994 mapping_unwind:
1995 	for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1996 		re = sky2->tx_ring + i;
1997 
1998 		sky2_tx_unmap(hw->pdev, re);
1999 	}
2000 
2001 mapping_error:
2002 	if (net_ratelimit())
2003 		dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2004 	dev_kfree_skb_any(skb);
2005 	return NETDEV_TX_OK;
2006 }
2007 
2008 /*
2009  * Free ring elements from starting at tx_cons until "done"
2010  *
2011  * NB:
2012  *  1. The hardware will tell us about partial completion of multi-part
2013  *     buffers so make sure not to free skb to early.
2014  *  2. This may run in parallel start_xmit because the it only
2015  *     looks at the tail of the queue of FIFO (tx_cons), not
2016  *     the head (tx_prod)
2017  */
2018 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2019 {
2020 	struct net_device *dev = sky2->netdev;
2021 	u16 idx;
2022 	unsigned int bytes_compl = 0, pkts_compl = 0;
2023 
2024 	BUG_ON(done >= sky2->tx_ring_size);
2025 
2026 	for (idx = sky2->tx_cons; idx != done;
2027 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2028 		struct tx_ring_info *re = sky2->tx_ring + idx;
2029 		struct sk_buff *skb = re->skb;
2030 
2031 		sky2_tx_unmap(sky2->hw->pdev, re);
2032 
2033 		if (skb) {
2034 			netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2035 				     "tx done %u\n", idx);
2036 
2037 			pkts_compl++;
2038 			bytes_compl += skb->len;
2039 
2040 			re->skb = NULL;
2041 			dev_kfree_skb_any(skb);
2042 
2043 			sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2044 		}
2045 	}
2046 
2047 	sky2->tx_cons = idx;
2048 	smp_mb();
2049 
2050 	netdev_completed_queue(dev, pkts_compl, bytes_compl);
2051 
2052 	u64_stats_update_begin(&sky2->tx_stats.syncp);
2053 	sky2->tx_stats.packets += pkts_compl;
2054 	sky2->tx_stats.bytes += bytes_compl;
2055 	u64_stats_update_end(&sky2->tx_stats.syncp);
2056 }
2057 
2058 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2059 {
2060 	/* Disable Force Sync bit and Enable Alloc bit */
2061 	sky2_write8(hw, SK_REG(port, TXA_CTRL),
2062 		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2063 
2064 	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
2065 	sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2066 	sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2067 
2068 	/* Reset the PCI FIFO of the async Tx queue */
2069 	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2070 		     BMU_RST_SET | BMU_FIFO_RST);
2071 
2072 	/* Reset the Tx prefetch units */
2073 	sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2074 		     PREF_UNIT_RST_SET);
2075 
2076 	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2077 	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2078 
2079 	sky2_read32(hw, B0_CTST);
2080 }
2081 
2082 static void sky2_hw_down(struct sky2_port *sky2)
2083 {
2084 	struct sky2_hw *hw = sky2->hw;
2085 	unsigned port = sky2->port;
2086 	u16 ctrl;
2087 
2088 	/* Force flow control off */
2089 	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2090 
2091 	/* Stop transmitter */
2092 	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2093 	sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2094 
2095 	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2096 		     RB_RST_SET | RB_DIS_OP_MD);
2097 
2098 	ctrl = gma_read16(hw, port, GM_GP_CTRL);
2099 	ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2100 	gma_write16(hw, port, GM_GP_CTRL, ctrl);
2101 
2102 	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2103 
2104 	/* Workaround shared GMAC reset */
2105 	if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2106 	      port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2107 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2108 
2109 	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2110 
2111 	/* Force any delayed status interrupt and NAPI */
2112 	sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2113 	sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2114 	sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2115 	sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2116 
2117 	sky2_rx_stop(sky2);
2118 
2119 	spin_lock_bh(&sky2->phy_lock);
2120 	sky2_phy_power_down(hw, port);
2121 	spin_unlock_bh(&sky2->phy_lock);
2122 
2123 	sky2_tx_reset(hw, port);
2124 
2125 	/* Free any pending frames stuck in HW queue */
2126 	sky2_tx_complete(sky2, sky2->tx_prod);
2127 }
2128 
2129 /* Network shutdown */
2130 static int sky2_close(struct net_device *dev)
2131 {
2132 	struct sky2_port *sky2 = netdev_priv(dev);
2133 	struct sky2_hw *hw = sky2->hw;
2134 
2135 	/* Never really got started! */
2136 	if (!sky2->tx_le)
2137 		return 0;
2138 
2139 	netif_info(sky2, ifdown, dev, "disabling interface\n");
2140 
2141 	if (hw->ports == 1) {
2142 		sky2_write32(hw, B0_IMSK, 0);
2143 		sky2_read32(hw, B0_IMSK);
2144 
2145 		napi_disable(&hw->napi);
2146 		free_irq(hw->pdev->irq, hw);
2147 		hw->flags &= ~SKY2_HW_IRQ_SETUP;
2148 	} else {
2149 		u32 imask;
2150 
2151 		/* Disable port IRQ */
2152 		imask  = sky2_read32(hw, B0_IMSK);
2153 		imask &= ~portirq_msk[sky2->port];
2154 		sky2_write32(hw, B0_IMSK, imask);
2155 		sky2_read32(hw, B0_IMSK);
2156 
2157 		synchronize_irq(hw->pdev->irq);
2158 		napi_synchronize(&hw->napi);
2159 	}
2160 
2161 	sky2_hw_down(sky2);
2162 
2163 	sky2_free_buffers(sky2);
2164 
2165 	return 0;
2166 }
2167 
2168 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2169 {
2170 	if (hw->flags & SKY2_HW_FIBRE_PHY)
2171 		return SPEED_1000;
2172 
2173 	if (!(hw->flags & SKY2_HW_GIGABIT)) {
2174 		if (aux & PHY_M_PS_SPEED_100)
2175 			return SPEED_100;
2176 		else
2177 			return SPEED_10;
2178 	}
2179 
2180 	switch (aux & PHY_M_PS_SPEED_MSK) {
2181 	case PHY_M_PS_SPEED_1000:
2182 		return SPEED_1000;
2183 	case PHY_M_PS_SPEED_100:
2184 		return SPEED_100;
2185 	default:
2186 		return SPEED_10;
2187 	}
2188 }
2189 
2190 static void sky2_link_up(struct sky2_port *sky2)
2191 {
2192 	struct sky2_hw *hw = sky2->hw;
2193 	unsigned port = sky2->port;
2194 	static const char *fc_name[] = {
2195 		[FC_NONE]	= "none",
2196 		[FC_TX]		= "tx",
2197 		[FC_RX]		= "rx",
2198 		[FC_BOTH]	= "both",
2199 	};
2200 
2201 	sky2_set_ipg(sky2);
2202 
2203 	sky2_enable_rx_tx(sky2);
2204 
2205 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2206 
2207 	netif_carrier_on(sky2->netdev);
2208 
2209 	mod_timer(&hw->watchdog_timer, jiffies + 1);
2210 
2211 	/* Turn on link LED */
2212 	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2213 		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2214 
2215 	netif_info(sky2, link, sky2->netdev,
2216 		   "Link is up at %d Mbps, %s duplex, flow control %s\n",
2217 		   sky2->speed,
2218 		   sky2->duplex == DUPLEX_FULL ? "full" : "half",
2219 		   fc_name[sky2->flow_status]);
2220 }
2221 
2222 static void sky2_link_down(struct sky2_port *sky2)
2223 {
2224 	struct sky2_hw *hw = sky2->hw;
2225 	unsigned port = sky2->port;
2226 	u16 reg;
2227 
2228 	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2229 
2230 	reg = gma_read16(hw, port, GM_GP_CTRL);
2231 	reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2232 	gma_write16(hw, port, GM_GP_CTRL, reg);
2233 
2234 	netif_carrier_off(sky2->netdev);
2235 
2236 	/* Turn off link LED */
2237 	sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2238 
2239 	netif_info(sky2, link, sky2->netdev, "Link is down\n");
2240 
2241 	sky2_phy_init(hw, port);
2242 }
2243 
2244 static enum flow_control sky2_flow(int rx, int tx)
2245 {
2246 	if (rx)
2247 		return tx ? FC_BOTH : FC_RX;
2248 	else
2249 		return tx ? FC_TX : FC_NONE;
2250 }
2251 
2252 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2253 {
2254 	struct sky2_hw *hw = sky2->hw;
2255 	unsigned port = sky2->port;
2256 	u16 advert, lpa;
2257 
2258 	advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2259 	lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2260 	if (lpa & PHY_M_AN_RF) {
2261 		netdev_err(sky2->netdev, "remote fault\n");
2262 		return -1;
2263 	}
2264 
2265 	if (!(aux & PHY_M_PS_SPDUP_RES)) {
2266 		netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2267 		return -1;
2268 	}
2269 
2270 	sky2->speed = sky2_phy_speed(hw, aux);
2271 	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2272 
2273 	/* Since the pause result bits seem to in different positions on
2274 	 * different chips. look at registers.
2275 	 */
2276 	if (hw->flags & SKY2_HW_FIBRE_PHY) {
2277 		/* Shift for bits in fiber PHY */
2278 		advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2279 		lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2280 
2281 		if (advert & ADVERTISE_1000XPAUSE)
2282 			advert |= ADVERTISE_PAUSE_CAP;
2283 		if (advert & ADVERTISE_1000XPSE_ASYM)
2284 			advert |= ADVERTISE_PAUSE_ASYM;
2285 		if (lpa & LPA_1000XPAUSE)
2286 			lpa |= LPA_PAUSE_CAP;
2287 		if (lpa & LPA_1000XPAUSE_ASYM)
2288 			lpa |= LPA_PAUSE_ASYM;
2289 	}
2290 
2291 	sky2->flow_status = FC_NONE;
2292 	if (advert & ADVERTISE_PAUSE_CAP) {
2293 		if (lpa & LPA_PAUSE_CAP)
2294 			sky2->flow_status = FC_BOTH;
2295 		else if (advert & ADVERTISE_PAUSE_ASYM)
2296 			sky2->flow_status = FC_RX;
2297 	} else if (advert & ADVERTISE_PAUSE_ASYM) {
2298 		if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2299 			sky2->flow_status = FC_TX;
2300 	}
2301 
2302 	if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2303 	    !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2304 		sky2->flow_status = FC_NONE;
2305 
2306 	if (sky2->flow_status & FC_TX)
2307 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2308 	else
2309 		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2310 
2311 	return 0;
2312 }
2313 
2314 /* Interrupt from PHY */
2315 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2316 {
2317 	struct net_device *dev = hw->dev[port];
2318 	struct sky2_port *sky2 = netdev_priv(dev);
2319 	u16 istatus, phystat;
2320 
2321 	if (!netif_running(dev))
2322 		return;
2323 
2324 	spin_lock(&sky2->phy_lock);
2325 	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2326 	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2327 
2328 	netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2329 		   istatus, phystat);
2330 
2331 	if (istatus & PHY_M_IS_AN_COMPL) {
2332 		if (sky2_autoneg_done(sky2, phystat) == 0 &&
2333 		    !netif_carrier_ok(dev))
2334 			sky2_link_up(sky2);
2335 		goto out;
2336 	}
2337 
2338 	if (istatus & PHY_M_IS_LSP_CHANGE)
2339 		sky2->speed = sky2_phy_speed(hw, phystat);
2340 
2341 	if (istatus & PHY_M_IS_DUP_CHANGE)
2342 		sky2->duplex =
2343 		    (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2344 
2345 	if (istatus & PHY_M_IS_LST_CHANGE) {
2346 		if (phystat & PHY_M_PS_LINK_UP)
2347 			sky2_link_up(sky2);
2348 		else
2349 			sky2_link_down(sky2);
2350 	}
2351 out:
2352 	spin_unlock(&sky2->phy_lock);
2353 }
2354 
2355 /* Special quick link interrupt (Yukon-2 Optima only) */
2356 static void sky2_qlink_intr(struct sky2_hw *hw)
2357 {
2358 	struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2359 	u32 imask;
2360 	u16 phy;
2361 
2362 	/* disable irq */
2363 	imask = sky2_read32(hw, B0_IMSK);
2364 	imask &= ~Y2_IS_PHY_QLNK;
2365 	sky2_write32(hw, B0_IMSK, imask);
2366 
2367 	/* reset PHY Link Detect */
2368 	phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2369 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2370 	sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2371 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2372 
2373 	sky2_link_up(sky2);
2374 }
2375 
2376 /* Transmit timeout is only called if we are running, carrier is up
2377  * and tx queue is full (stopped).
2378  */
2379 static void sky2_tx_timeout(struct net_device *dev)
2380 {
2381 	struct sky2_port *sky2 = netdev_priv(dev);
2382 	struct sky2_hw *hw = sky2->hw;
2383 
2384 	netif_err(sky2, timer, dev, "tx timeout\n");
2385 
2386 	netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2387 		      sky2->tx_cons, sky2->tx_prod,
2388 		      sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2389 		      sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2390 
2391 	/* can't restart safely under softirq */
2392 	schedule_work(&hw->restart_work);
2393 }
2394 
2395 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2396 {
2397 	struct sky2_port *sky2 = netdev_priv(dev);
2398 	struct sky2_hw *hw = sky2->hw;
2399 	unsigned port = sky2->port;
2400 	int err;
2401 	u16 ctl, mode;
2402 	u32 imask;
2403 
2404 	/* MTU size outside the spec */
2405 	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2406 		return -EINVAL;
2407 
2408 	/* MTU > 1500 on yukon FE and FE+ not allowed */
2409 	if (new_mtu > ETH_DATA_LEN &&
2410 	    (hw->chip_id == CHIP_ID_YUKON_FE ||
2411 	     hw->chip_id == CHIP_ID_YUKON_FE_P))
2412 		return -EINVAL;
2413 
2414 	if (!netif_running(dev)) {
2415 		dev->mtu = new_mtu;
2416 		netdev_update_features(dev);
2417 		return 0;
2418 	}
2419 
2420 	imask = sky2_read32(hw, B0_IMSK);
2421 	sky2_write32(hw, B0_IMSK, 0);
2422 
2423 	dev->trans_start = jiffies;	/* prevent tx timeout */
2424 	napi_disable(&hw->napi);
2425 	netif_tx_disable(dev);
2426 
2427 	synchronize_irq(hw->pdev->irq);
2428 
2429 	if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2430 		sky2_set_tx_stfwd(hw, port);
2431 
2432 	ctl = gma_read16(hw, port, GM_GP_CTRL);
2433 	gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2434 	sky2_rx_stop(sky2);
2435 	sky2_rx_clean(sky2);
2436 
2437 	dev->mtu = new_mtu;
2438 	netdev_update_features(dev);
2439 
2440 	mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |	GM_SMOD_VLAN_ENA;
2441 	if (sky2->speed > SPEED_100)
2442 		mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2443 	else
2444 		mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2445 
2446 	if (dev->mtu > ETH_DATA_LEN)
2447 		mode |= GM_SMOD_JUMBO_ENA;
2448 
2449 	gma_write16(hw, port, GM_SERIAL_MODE, mode);
2450 
2451 	sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2452 
2453 	err = sky2_alloc_rx_skbs(sky2);
2454 	if (!err)
2455 		sky2_rx_start(sky2);
2456 	else
2457 		sky2_rx_clean(sky2);
2458 	sky2_write32(hw, B0_IMSK, imask);
2459 
2460 	sky2_read32(hw, B0_Y2_SP_LISR);
2461 	napi_enable(&hw->napi);
2462 
2463 	if (err)
2464 		dev_close(dev);
2465 	else {
2466 		gma_write16(hw, port, GM_GP_CTRL, ctl);
2467 
2468 		netif_wake_queue(dev);
2469 	}
2470 
2471 	return err;
2472 }
2473 
2474 static inline bool needs_copy(const struct rx_ring_info *re,
2475 			      unsigned length)
2476 {
2477 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2478 	/* Some architectures need the IP header to be aligned */
2479 	if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2480 		return true;
2481 #endif
2482 	return length < copybreak;
2483 }
2484 
2485 /* For small just reuse existing skb for next receive */
2486 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2487 				    const struct rx_ring_info *re,
2488 				    unsigned length)
2489 {
2490 	struct sk_buff *skb;
2491 
2492 	skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2493 	if (likely(skb)) {
2494 		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2495 					    length, PCI_DMA_FROMDEVICE);
2496 		skb_copy_from_linear_data(re->skb, skb->data, length);
2497 		skb->ip_summed = re->skb->ip_summed;
2498 		skb->csum = re->skb->csum;
2499 		skb_copy_hash(skb, re->skb);
2500 		skb->vlan_proto = re->skb->vlan_proto;
2501 		skb->vlan_tci = re->skb->vlan_tci;
2502 
2503 		pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2504 					       length, PCI_DMA_FROMDEVICE);
2505 		re->skb->vlan_proto = 0;
2506 		re->skb->vlan_tci = 0;
2507 		skb_clear_hash(re->skb);
2508 		re->skb->ip_summed = CHECKSUM_NONE;
2509 		skb_put(skb, length);
2510 	}
2511 	return skb;
2512 }
2513 
2514 /* Adjust length of skb with fragments to match received data */
2515 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2516 			  unsigned int length)
2517 {
2518 	int i, num_frags;
2519 	unsigned int size;
2520 
2521 	/* put header into skb */
2522 	size = min(length, hdr_space);
2523 	skb->tail += size;
2524 	skb->len += size;
2525 	length -= size;
2526 
2527 	num_frags = skb_shinfo(skb)->nr_frags;
2528 	for (i = 0; i < num_frags; i++) {
2529 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2530 
2531 		if (length == 0) {
2532 			/* don't need this page */
2533 			__skb_frag_unref(frag);
2534 			--skb_shinfo(skb)->nr_frags;
2535 		} else {
2536 			size = min(length, (unsigned) PAGE_SIZE);
2537 
2538 			skb_frag_size_set(frag, size);
2539 			skb->data_len += size;
2540 			skb->truesize += PAGE_SIZE;
2541 			skb->len += size;
2542 			length -= size;
2543 		}
2544 	}
2545 }
2546 
2547 /* Normal packet - take skb from ring element and put in a new one  */
2548 static struct sk_buff *receive_new(struct sky2_port *sky2,
2549 				   struct rx_ring_info *re,
2550 				   unsigned int length)
2551 {
2552 	struct sk_buff *skb;
2553 	struct rx_ring_info nre;
2554 	unsigned hdr_space = sky2->rx_data_size;
2555 
2556 	nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2557 	if (unlikely(!nre.skb))
2558 		goto nobuf;
2559 
2560 	if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2561 		goto nomap;
2562 
2563 	skb = re->skb;
2564 	sky2_rx_unmap_skb(sky2->hw->pdev, re);
2565 	prefetch(skb->data);
2566 	*re = nre;
2567 
2568 	if (skb_shinfo(skb)->nr_frags)
2569 		skb_put_frags(skb, hdr_space, length);
2570 	else
2571 		skb_put(skb, length);
2572 	return skb;
2573 
2574 nomap:
2575 	dev_kfree_skb(nre.skb);
2576 nobuf:
2577 	return NULL;
2578 }
2579 
2580 /*
2581  * Receive one packet.
2582  * For larger packets, get new buffer.
2583  */
2584 static struct sk_buff *sky2_receive(struct net_device *dev,
2585 				    u16 length, u32 status)
2586 {
2587  	struct sky2_port *sky2 = netdev_priv(dev);
2588 	struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2589 	struct sk_buff *skb = NULL;
2590 	u16 count = (status & GMR_FS_LEN) >> 16;
2591 
2592 	netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2593 		     "rx slot %u status 0x%x len %d\n",
2594 		     sky2->rx_next, status, length);
2595 
2596 	sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2597 	prefetch(sky2->rx_ring + sky2->rx_next);
2598 
2599 	if (vlan_tx_tag_present(re->skb))
2600 		count -= VLAN_HLEN;	/* Account for vlan tag */
2601 
2602 	/* This chip has hardware problems that generates bogus status.
2603 	 * So do only marginal checking and expect higher level protocols
2604 	 * to handle crap frames.
2605 	 */
2606 	if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2607 	    sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2608 	    length != count)
2609 		goto okay;
2610 
2611 	if (status & GMR_FS_ANY_ERR)
2612 		goto error;
2613 
2614 	if (!(status & GMR_FS_RX_OK))
2615 		goto resubmit;
2616 
2617 	/* if length reported by DMA does not match PHY, packet was truncated */
2618 	if (length != count)
2619 		goto error;
2620 
2621 okay:
2622 	if (needs_copy(re, length))
2623 		skb = receive_copy(sky2, re, length);
2624 	else
2625 		skb = receive_new(sky2, re, length);
2626 
2627 	dev->stats.rx_dropped += (skb == NULL);
2628 
2629 resubmit:
2630 	sky2_rx_submit(sky2, re);
2631 
2632 	return skb;
2633 
2634 error:
2635 	++dev->stats.rx_errors;
2636 
2637 	if (net_ratelimit())
2638 		netif_info(sky2, rx_err, dev,
2639 			   "rx error, status 0x%x length %d\n", status, length);
2640 
2641 	goto resubmit;
2642 }
2643 
2644 /* Transmit complete */
2645 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2646 {
2647 	struct sky2_port *sky2 = netdev_priv(dev);
2648 
2649 	if (netif_running(dev)) {
2650 		sky2_tx_complete(sky2, last);
2651 
2652 		/* Wake unless it's detached, and called e.g. from sky2_close() */
2653 		if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2654 			netif_wake_queue(dev);
2655 	}
2656 }
2657 
2658 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2659 			       struct sk_buff *skb)
2660 {
2661 	if (skb->ip_summed == CHECKSUM_NONE)
2662 		netif_receive_skb(skb);
2663 	else
2664 		napi_gro_receive(&sky2->hw->napi, skb);
2665 }
2666 
2667 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2668 				unsigned packets, unsigned bytes)
2669 {
2670 	struct net_device *dev = hw->dev[port];
2671 	struct sky2_port *sky2 = netdev_priv(dev);
2672 
2673 	if (packets == 0)
2674 		return;
2675 
2676 	u64_stats_update_begin(&sky2->rx_stats.syncp);
2677 	sky2->rx_stats.packets += packets;
2678 	sky2->rx_stats.bytes += bytes;
2679 	u64_stats_update_end(&sky2->rx_stats.syncp);
2680 
2681 	dev->last_rx = jiffies;
2682 	sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2683 }
2684 
2685 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2686 {
2687 	/* If this happens then driver assuming wrong format for chip type */
2688 	BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2689 
2690 	/* Both checksum counters are programmed to start at
2691 	 * the same offset, so unless there is a problem they
2692 	 * should match. This failure is an early indication that
2693 	 * hardware receive checksumming won't work.
2694 	 */
2695 	if (likely((u16)(status >> 16) == (u16)status)) {
2696 		struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2697 		skb->ip_summed = CHECKSUM_COMPLETE;
2698 		skb->csum = le16_to_cpu(status);
2699 	} else {
2700 		dev_notice(&sky2->hw->pdev->dev,
2701 			   "%s: receive checksum problem (status = %#x)\n",
2702 			   sky2->netdev->name, status);
2703 
2704 		/* Disable checksum offload
2705 		 * It will be reenabled on next ndo_set_features, but if it's
2706 		 * really broken, will get disabled again
2707 		 */
2708 		sky2->netdev->features &= ~NETIF_F_RXCSUM;
2709 		sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2710 			     BMU_DIS_RX_CHKSUM);
2711 	}
2712 }
2713 
2714 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2715 {
2716 	struct sk_buff *skb;
2717 
2718 	skb = sky2->rx_ring[sky2->rx_next].skb;
2719 	__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2720 }
2721 
2722 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2723 {
2724 	struct sk_buff *skb;
2725 
2726 	skb = sky2->rx_ring[sky2->rx_next].skb;
2727 	skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2728 }
2729 
2730 /* Process status response ring */
2731 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2732 {
2733 	int work_done = 0;
2734 	unsigned int total_bytes[2] = { 0 };
2735 	unsigned int total_packets[2] = { 0 };
2736 
2737 	if (to_do <= 0)
2738 		return work_done;
2739 
2740 	rmb();
2741 	do {
2742 		struct sky2_port *sky2;
2743 		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
2744 		unsigned port;
2745 		struct net_device *dev;
2746 		struct sk_buff *skb;
2747 		u32 status;
2748 		u16 length;
2749 		u8 opcode = le->opcode;
2750 
2751 		if (!(opcode & HW_OWNER))
2752 			break;
2753 
2754 		hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2755 
2756 		port = le->css & CSS_LINK_BIT;
2757 		dev = hw->dev[port];
2758 		sky2 = netdev_priv(dev);
2759 		length = le16_to_cpu(le->length);
2760 		status = le32_to_cpu(le->status);
2761 
2762 		le->opcode = 0;
2763 		switch (opcode & ~HW_OWNER) {
2764 		case OP_RXSTAT:
2765 			total_packets[port]++;
2766 			total_bytes[port] += length;
2767 
2768 			skb = sky2_receive(dev, length, status);
2769 			if (!skb)
2770 				break;
2771 
2772 			/* This chip reports checksum status differently */
2773 			if (hw->flags & SKY2_HW_NEW_LE) {
2774 				if ((dev->features & NETIF_F_RXCSUM) &&
2775 				    (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2776 				    (le->css & CSS_TCPUDPCSOK))
2777 					skb->ip_summed = CHECKSUM_UNNECESSARY;
2778 				else
2779 					skb->ip_summed = CHECKSUM_NONE;
2780 			}
2781 
2782 			skb->protocol = eth_type_trans(skb, dev);
2783 			sky2_skb_rx(sky2, skb);
2784 
2785 			/* Stop after net poll weight */
2786 			if (++work_done >= to_do)
2787 				goto exit_loop;
2788 			break;
2789 
2790 		case OP_RXVLAN:
2791 			sky2_rx_tag(sky2, length);
2792 			break;
2793 
2794 		case OP_RXCHKSVLAN:
2795 			sky2_rx_tag(sky2, length);
2796 			/* fall through */
2797 		case OP_RXCHKS:
2798 			if (likely(dev->features & NETIF_F_RXCSUM))
2799 				sky2_rx_checksum(sky2, status);
2800 			break;
2801 
2802 		case OP_RSS_HASH:
2803 			sky2_rx_hash(sky2, status);
2804 			break;
2805 
2806 		case OP_TXINDEXLE:
2807 			/* TX index reports status for both ports */
2808 			sky2_tx_done(hw->dev[0], status & 0xfff);
2809 			if (hw->dev[1])
2810 				sky2_tx_done(hw->dev[1],
2811 				     ((status >> 24) & 0xff)
2812 					     | (u16)(length & 0xf) << 8);
2813 			break;
2814 
2815 		default:
2816 			if (net_ratelimit())
2817 				pr_warn("unknown status opcode 0x%x\n", opcode);
2818 		}
2819 	} while (hw->st_idx != idx);
2820 
2821 	/* Fully processed status ring so clear irq */
2822 	sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2823 
2824 exit_loop:
2825 	sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2826 	sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2827 
2828 	return work_done;
2829 }
2830 
2831 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2832 {
2833 	struct net_device *dev = hw->dev[port];
2834 
2835 	if (net_ratelimit())
2836 		netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2837 
2838 	if (status & Y2_IS_PAR_RD1) {
2839 		if (net_ratelimit())
2840 			netdev_err(dev, "ram data read parity error\n");
2841 		/* Clear IRQ */
2842 		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2843 	}
2844 
2845 	if (status & Y2_IS_PAR_WR1) {
2846 		if (net_ratelimit())
2847 			netdev_err(dev, "ram data write parity error\n");
2848 
2849 		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2850 	}
2851 
2852 	if (status & Y2_IS_PAR_MAC1) {
2853 		if (net_ratelimit())
2854 			netdev_err(dev, "MAC parity error\n");
2855 		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2856 	}
2857 
2858 	if (status & Y2_IS_PAR_RX1) {
2859 		if (net_ratelimit())
2860 			netdev_err(dev, "RX parity error\n");
2861 		sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2862 	}
2863 
2864 	if (status & Y2_IS_TCP_TXA1) {
2865 		if (net_ratelimit())
2866 			netdev_err(dev, "TCP segmentation error\n");
2867 		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2868 	}
2869 }
2870 
2871 static void sky2_hw_intr(struct sky2_hw *hw)
2872 {
2873 	struct pci_dev *pdev = hw->pdev;
2874 	u32 status = sky2_read32(hw, B0_HWE_ISRC);
2875 	u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2876 
2877 	status &= hwmsk;
2878 
2879 	if (status & Y2_IS_TIST_OV)
2880 		sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2881 
2882 	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2883 		u16 pci_err;
2884 
2885 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2886 		pci_err = sky2_pci_read16(hw, PCI_STATUS);
2887 		if (net_ratelimit())
2888 			dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2889 			        pci_err);
2890 
2891 		sky2_pci_write16(hw, PCI_STATUS,
2892 				      pci_err | PCI_STATUS_ERROR_BITS);
2893 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2894 	}
2895 
2896 	if (status & Y2_IS_PCI_EXP) {
2897 		/* PCI-Express uncorrectable Error occurred */
2898 		u32 err;
2899 
2900 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2901 		err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2902 		sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2903 			     0xfffffffful);
2904 		if (net_ratelimit())
2905 			dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2906 
2907 		sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2908 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2909 	}
2910 
2911 	if (status & Y2_HWE_L1_MASK)
2912 		sky2_hw_error(hw, 0, status);
2913 	status >>= 8;
2914 	if (status & Y2_HWE_L1_MASK)
2915 		sky2_hw_error(hw, 1, status);
2916 }
2917 
2918 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2919 {
2920 	struct net_device *dev = hw->dev[port];
2921 	struct sky2_port *sky2 = netdev_priv(dev);
2922 	u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2923 
2924 	netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2925 
2926 	if (status & GM_IS_RX_CO_OV)
2927 		gma_read16(hw, port, GM_RX_IRQ_SRC);
2928 
2929 	if (status & GM_IS_TX_CO_OV)
2930 		gma_read16(hw, port, GM_TX_IRQ_SRC);
2931 
2932 	if (status & GM_IS_RX_FF_OR) {
2933 		++dev->stats.rx_fifo_errors;
2934 		sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2935 	}
2936 
2937 	if (status & GM_IS_TX_FF_UR) {
2938 		++dev->stats.tx_fifo_errors;
2939 		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2940 	}
2941 }
2942 
2943 /* This should never happen it is a bug. */
2944 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2945 {
2946 	struct net_device *dev = hw->dev[port];
2947 	u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2948 
2949 	dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2950 		dev->name, (unsigned) q, (unsigned) idx,
2951 		(unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2952 
2953 	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2954 }
2955 
2956 static int sky2_rx_hung(struct net_device *dev)
2957 {
2958 	struct sky2_port *sky2 = netdev_priv(dev);
2959 	struct sky2_hw *hw = sky2->hw;
2960 	unsigned port = sky2->port;
2961 	unsigned rxq = rxqaddr[port];
2962 	u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2963 	u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2964 	u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2965 	u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2966 
2967 	/* If idle and MAC or PCI is stuck */
2968 	if (sky2->check.last == dev->last_rx &&
2969 	    ((mac_rp == sky2->check.mac_rp &&
2970 	      mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2971 	     /* Check if the PCI RX hang */
2972 	     (fifo_rp == sky2->check.fifo_rp &&
2973 	      fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2974 		netdev_printk(KERN_DEBUG, dev,
2975 			      "hung mac %d:%d fifo %d (%d:%d)\n",
2976 			      mac_lev, mac_rp, fifo_lev,
2977 			      fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2978 		return 1;
2979 	} else {
2980 		sky2->check.last = dev->last_rx;
2981 		sky2->check.mac_rp = mac_rp;
2982 		sky2->check.mac_lev = mac_lev;
2983 		sky2->check.fifo_rp = fifo_rp;
2984 		sky2->check.fifo_lev = fifo_lev;
2985 		return 0;
2986 	}
2987 }
2988 
2989 static void sky2_watchdog(unsigned long arg)
2990 {
2991 	struct sky2_hw *hw = (struct sky2_hw *) arg;
2992 
2993 	/* Check for lost IRQ once a second */
2994 	if (sky2_read32(hw, B0_ISRC)) {
2995 		napi_schedule(&hw->napi);
2996 	} else {
2997 		int i, active = 0;
2998 
2999 		for (i = 0; i < hw->ports; i++) {
3000 			struct net_device *dev = hw->dev[i];
3001 			if (!netif_running(dev))
3002 				continue;
3003 			++active;
3004 
3005 			/* For chips with Rx FIFO, check if stuck */
3006 			if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
3007 			     sky2_rx_hung(dev)) {
3008 				netdev_info(dev, "receiver hang detected\n");
3009 				schedule_work(&hw->restart_work);
3010 				return;
3011 			}
3012 		}
3013 
3014 		if (active == 0)
3015 			return;
3016 	}
3017 
3018 	mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3019 }
3020 
3021 /* Hardware/software error handling */
3022 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3023 {
3024 	if (net_ratelimit())
3025 		dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3026 
3027 	if (status & Y2_IS_HW_ERR)
3028 		sky2_hw_intr(hw);
3029 
3030 	if (status & Y2_IS_IRQ_MAC1)
3031 		sky2_mac_intr(hw, 0);
3032 
3033 	if (status & Y2_IS_IRQ_MAC2)
3034 		sky2_mac_intr(hw, 1);
3035 
3036 	if (status & Y2_IS_CHK_RX1)
3037 		sky2_le_error(hw, 0, Q_R1);
3038 
3039 	if (status & Y2_IS_CHK_RX2)
3040 		sky2_le_error(hw, 1, Q_R2);
3041 
3042 	if (status & Y2_IS_CHK_TXA1)
3043 		sky2_le_error(hw, 0, Q_XA1);
3044 
3045 	if (status & Y2_IS_CHK_TXA2)
3046 		sky2_le_error(hw, 1, Q_XA2);
3047 }
3048 
3049 static int sky2_poll(struct napi_struct *napi, int work_limit)
3050 {
3051 	struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3052 	u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3053 	int work_done = 0;
3054 	u16 idx;
3055 
3056 	if (unlikely(status & Y2_IS_ERROR))
3057 		sky2_err_intr(hw, status);
3058 
3059 	if (status & Y2_IS_IRQ_PHY1)
3060 		sky2_phy_intr(hw, 0);
3061 
3062 	if (status & Y2_IS_IRQ_PHY2)
3063 		sky2_phy_intr(hw, 1);
3064 
3065 	if (status & Y2_IS_PHY_QLNK)
3066 		sky2_qlink_intr(hw);
3067 
3068 	while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3069 		work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3070 
3071 		if (work_done >= work_limit)
3072 			goto done;
3073 	}
3074 
3075 	napi_complete(napi);
3076 	sky2_read32(hw, B0_Y2_SP_LISR);
3077 done:
3078 
3079 	return work_done;
3080 }
3081 
3082 static irqreturn_t sky2_intr(int irq, void *dev_id)
3083 {
3084 	struct sky2_hw *hw = dev_id;
3085 	u32 status;
3086 
3087 	/* Reading this mask interrupts as side effect */
3088 	status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3089 	if (status == 0 || status == ~0) {
3090 		sky2_write32(hw, B0_Y2_SP_ICR, 2);
3091 		return IRQ_NONE;
3092 	}
3093 
3094 	prefetch(&hw->st_le[hw->st_idx]);
3095 
3096 	napi_schedule(&hw->napi);
3097 
3098 	return IRQ_HANDLED;
3099 }
3100 
3101 #ifdef CONFIG_NET_POLL_CONTROLLER
3102 static void sky2_netpoll(struct net_device *dev)
3103 {
3104 	struct sky2_port *sky2 = netdev_priv(dev);
3105 
3106 	napi_schedule(&sky2->hw->napi);
3107 }
3108 #endif
3109 
3110 /* Chip internal frequency for clock calculations */
3111 static u32 sky2_mhz(const struct sky2_hw *hw)
3112 {
3113 	switch (hw->chip_id) {
3114 	case CHIP_ID_YUKON_EC:
3115 	case CHIP_ID_YUKON_EC_U:
3116 	case CHIP_ID_YUKON_EX:
3117 	case CHIP_ID_YUKON_SUPR:
3118 	case CHIP_ID_YUKON_UL_2:
3119 	case CHIP_ID_YUKON_OPT:
3120 	case CHIP_ID_YUKON_PRM:
3121 	case CHIP_ID_YUKON_OP_2:
3122 		return 125;
3123 
3124 	case CHIP_ID_YUKON_FE:
3125 		return 100;
3126 
3127 	case CHIP_ID_YUKON_FE_P:
3128 		return 50;
3129 
3130 	case CHIP_ID_YUKON_XL:
3131 		return 156;
3132 
3133 	default:
3134 		BUG();
3135 	}
3136 }
3137 
3138 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3139 {
3140 	return sky2_mhz(hw) * us;
3141 }
3142 
3143 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3144 {
3145 	return clk / sky2_mhz(hw);
3146 }
3147 
3148 
3149 static int sky2_init(struct sky2_hw *hw)
3150 {
3151 	u8 t8;
3152 
3153 	/* Enable all clocks and check for bad PCI access */
3154 	sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3155 
3156 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
3157 
3158 	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3159 	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3160 
3161 	switch (hw->chip_id) {
3162 	case CHIP_ID_YUKON_XL:
3163 		hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3164 		if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3165 			hw->flags |= SKY2_HW_RSS_BROKEN;
3166 		break;
3167 
3168 	case CHIP_ID_YUKON_EC_U:
3169 		hw->flags = SKY2_HW_GIGABIT
3170 			| SKY2_HW_NEWER_PHY
3171 			| SKY2_HW_ADV_POWER_CTL;
3172 		break;
3173 
3174 	case CHIP_ID_YUKON_EX:
3175 		hw->flags = SKY2_HW_GIGABIT
3176 			| SKY2_HW_NEWER_PHY
3177 			| SKY2_HW_NEW_LE
3178 			| SKY2_HW_ADV_POWER_CTL
3179 			| SKY2_HW_RSS_CHKSUM;
3180 
3181 		/* New transmit checksum */
3182 		if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3183 			hw->flags |= SKY2_HW_AUTO_TX_SUM;
3184 		break;
3185 
3186 	case CHIP_ID_YUKON_EC:
3187 		/* This rev is really old, and requires untested workarounds */
3188 		if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3189 			dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3190 			return -EOPNOTSUPP;
3191 		}
3192 		hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3193 		break;
3194 
3195 	case CHIP_ID_YUKON_FE:
3196 		hw->flags = SKY2_HW_RSS_BROKEN;
3197 		break;
3198 
3199 	case CHIP_ID_YUKON_FE_P:
3200 		hw->flags = SKY2_HW_NEWER_PHY
3201 			| SKY2_HW_NEW_LE
3202 			| SKY2_HW_AUTO_TX_SUM
3203 			| SKY2_HW_ADV_POWER_CTL;
3204 
3205 		/* The workaround for status conflicts VLAN tag detection. */
3206 		if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3207 			hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3208 		break;
3209 
3210 	case CHIP_ID_YUKON_SUPR:
3211 		hw->flags = SKY2_HW_GIGABIT
3212 			| SKY2_HW_NEWER_PHY
3213 			| SKY2_HW_NEW_LE
3214 			| SKY2_HW_AUTO_TX_SUM
3215 			| SKY2_HW_ADV_POWER_CTL;
3216 
3217 		if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3218 			hw->flags |= SKY2_HW_RSS_CHKSUM;
3219 		break;
3220 
3221 	case CHIP_ID_YUKON_UL_2:
3222 		hw->flags = SKY2_HW_GIGABIT
3223 			| SKY2_HW_ADV_POWER_CTL;
3224 		break;
3225 
3226 	case CHIP_ID_YUKON_OPT:
3227 	case CHIP_ID_YUKON_PRM:
3228 	case CHIP_ID_YUKON_OP_2:
3229 		hw->flags = SKY2_HW_GIGABIT
3230 			| SKY2_HW_NEW_LE
3231 			| SKY2_HW_ADV_POWER_CTL;
3232 		break;
3233 
3234 	default:
3235 		dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3236 			hw->chip_id);
3237 		return -EOPNOTSUPP;
3238 	}
3239 
3240 	hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3241 	if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3242 		hw->flags |= SKY2_HW_FIBRE_PHY;
3243 
3244 	hw->ports = 1;
3245 	t8 = sky2_read8(hw, B2_Y2_HW_RES);
3246 	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3247 		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3248 			++hw->ports;
3249 	}
3250 
3251 	if (sky2_read8(hw, B2_E_0))
3252 		hw->flags |= SKY2_HW_RAM_BUFFER;
3253 
3254 	return 0;
3255 }
3256 
3257 static void sky2_reset(struct sky2_hw *hw)
3258 {
3259 	struct pci_dev *pdev = hw->pdev;
3260 	u16 status;
3261 	int i;
3262 	u32 hwe_mask = Y2_HWE_ALL_MASK;
3263 
3264 	/* disable ASF */
3265 	if (hw->chip_id == CHIP_ID_YUKON_EX
3266 	    || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3267 		sky2_write32(hw, CPU_WDOG, 0);
3268 		status = sky2_read16(hw, HCU_CCSR);
3269 		status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3270 			    HCU_CCSR_UC_STATE_MSK);
3271 		/*
3272 		 * CPU clock divider shouldn't be used because
3273 		 * - ASF firmware may malfunction
3274 		 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3275 		 */
3276 		status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3277 		sky2_write16(hw, HCU_CCSR, status);
3278 		sky2_write32(hw, CPU_WDOG, 0);
3279 	} else
3280 		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3281 	sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3282 
3283 	/* do a SW reset */
3284 	sky2_write8(hw, B0_CTST, CS_RST_SET);
3285 	sky2_write8(hw, B0_CTST, CS_RST_CLR);
3286 
3287 	/* allow writes to PCI config */
3288 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3289 
3290 	/* clear PCI errors, if any */
3291 	status = sky2_pci_read16(hw, PCI_STATUS);
3292 	status |= PCI_STATUS_ERROR_BITS;
3293 	sky2_pci_write16(hw, PCI_STATUS, status);
3294 
3295 	sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3296 
3297 	if (pci_is_pcie(pdev)) {
3298 		sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3299 			     0xfffffffful);
3300 
3301 		/* If error bit is stuck on ignore it */
3302 		if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3303 			dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3304 		else
3305 			hwe_mask |= Y2_IS_PCI_EXP;
3306 	}
3307 
3308 	sky2_power_on(hw);
3309 	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3310 
3311 	for (i = 0; i < hw->ports; i++) {
3312 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3313 		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3314 
3315 		if (hw->chip_id == CHIP_ID_YUKON_EX ||
3316 		    hw->chip_id == CHIP_ID_YUKON_SUPR)
3317 			sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3318 				     GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3319 				     | GMC_BYP_RETR_ON);
3320 
3321 	}
3322 
3323 	if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3324 		/* enable MACSec clock gating */
3325 		sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3326 	}
3327 
3328 	if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3329 	    hw->chip_id == CHIP_ID_YUKON_PRM ||
3330 	    hw->chip_id == CHIP_ID_YUKON_OP_2) {
3331 		u16 reg;
3332 
3333 		if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3334 			/* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3335 			sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3336 
3337 			/* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3338 			reg = 10;
3339 
3340 			/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3341 			sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3342 		} else {
3343 			/* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3344 			reg = 3;
3345 		}
3346 
3347 		reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3348 		reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3349 
3350 		/* reset PHY Link Detect */
3351 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3352 		sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3353 
3354 		/* check if PSMv2 was running before */
3355 		reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3356 		if (reg & PCI_EXP_LNKCTL_ASPMC)
3357 			/* restore the PCIe Link Control register */
3358 			sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3359 					 reg);
3360 
3361 		if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3362 			hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3363 			/* change PHY Interrupt polarity to low active */
3364 			reg = sky2_read16(hw, GPHY_CTRL);
3365 			sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3366 
3367 			/* adapt HW for low active PHY Interrupt */
3368 			reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3369 			sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3370 		}
3371 
3372 		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3373 
3374 		/* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3375 		sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3376 	}
3377 
3378 	/* Clear I2C IRQ noise */
3379 	sky2_write32(hw, B2_I2C_IRQ, 1);
3380 
3381 	/* turn off hardware timer (unused) */
3382 	sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3383 	sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3384 
3385 	/* Turn off descriptor polling */
3386 	sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3387 
3388 	/* Turn off receive timestamp */
3389 	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3390 	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3391 
3392 	/* enable the Tx Arbiters */
3393 	for (i = 0; i < hw->ports; i++)
3394 		sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3395 
3396 	/* Initialize ram interface */
3397 	for (i = 0; i < hw->ports; i++) {
3398 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3399 
3400 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3401 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3402 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3403 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3404 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3405 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3406 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3407 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3408 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3409 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3410 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3411 		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3412 	}
3413 
3414 	sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3415 
3416 	for (i = 0; i < hw->ports; i++)
3417 		sky2_gmac_reset(hw, i);
3418 
3419 	memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3420 	hw->st_idx = 0;
3421 
3422 	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3423 	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3424 
3425 	sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3426 	sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3427 
3428 	/* Set the list last index */
3429 	sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3430 
3431 	sky2_write16(hw, STAT_TX_IDX_TH, 10);
3432 	sky2_write8(hw, STAT_FIFO_WM, 16);
3433 
3434 	/* set Status-FIFO ISR watermark */
3435 	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3436 		sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3437 	else
3438 		sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3439 
3440 	sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3441 	sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3442 	sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3443 
3444 	/* enable status unit */
3445 	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3446 
3447 	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3448 	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3449 	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3450 }
3451 
3452 /* Take device down (offline).
3453  * Equivalent to doing dev_stop() but this does not
3454  * inform upper layers of the transition.
3455  */
3456 static void sky2_detach(struct net_device *dev)
3457 {
3458 	if (netif_running(dev)) {
3459 		netif_tx_lock(dev);
3460 		netif_device_detach(dev);	/* stop txq */
3461 		netif_tx_unlock(dev);
3462 		sky2_close(dev);
3463 	}
3464 }
3465 
3466 /* Bring device back after doing sky2_detach */
3467 static int sky2_reattach(struct net_device *dev)
3468 {
3469 	int err = 0;
3470 
3471 	if (netif_running(dev)) {
3472 		err = sky2_open(dev);
3473 		if (err) {
3474 			netdev_info(dev, "could not restart %d\n", err);
3475 			dev_close(dev);
3476 		} else {
3477 			netif_device_attach(dev);
3478 			sky2_set_multicast(dev);
3479 		}
3480 	}
3481 
3482 	return err;
3483 }
3484 
3485 static void sky2_all_down(struct sky2_hw *hw)
3486 {
3487 	int i;
3488 
3489 	if (hw->flags & SKY2_HW_IRQ_SETUP) {
3490 		sky2_read32(hw, B0_IMSK);
3491 		sky2_write32(hw, B0_IMSK, 0);
3492 
3493 		synchronize_irq(hw->pdev->irq);
3494 		napi_disable(&hw->napi);
3495 	}
3496 
3497 	for (i = 0; i < hw->ports; i++) {
3498 		struct net_device *dev = hw->dev[i];
3499 		struct sky2_port *sky2 = netdev_priv(dev);
3500 
3501 		if (!netif_running(dev))
3502 			continue;
3503 
3504 		netif_carrier_off(dev);
3505 		netif_tx_disable(dev);
3506 		sky2_hw_down(sky2);
3507 	}
3508 }
3509 
3510 static void sky2_all_up(struct sky2_hw *hw)
3511 {
3512 	u32 imask = Y2_IS_BASE;
3513 	int i;
3514 
3515 	for (i = 0; i < hw->ports; i++) {
3516 		struct net_device *dev = hw->dev[i];
3517 		struct sky2_port *sky2 = netdev_priv(dev);
3518 
3519 		if (!netif_running(dev))
3520 			continue;
3521 
3522 		sky2_hw_up(sky2);
3523 		sky2_set_multicast(dev);
3524 		imask |= portirq_msk[i];
3525 		netif_wake_queue(dev);
3526 	}
3527 
3528 	if (hw->flags & SKY2_HW_IRQ_SETUP) {
3529 		sky2_write32(hw, B0_IMSK, imask);
3530 		sky2_read32(hw, B0_IMSK);
3531 		sky2_read32(hw, B0_Y2_SP_LISR);
3532 		napi_enable(&hw->napi);
3533 	}
3534 }
3535 
3536 static void sky2_restart(struct work_struct *work)
3537 {
3538 	struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3539 
3540 	rtnl_lock();
3541 
3542 	sky2_all_down(hw);
3543 	sky2_reset(hw);
3544 	sky2_all_up(hw);
3545 
3546 	rtnl_unlock();
3547 }
3548 
3549 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3550 {
3551 	return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3552 }
3553 
3554 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3555 {
3556 	const struct sky2_port *sky2 = netdev_priv(dev);
3557 
3558 	wol->supported = sky2_wol_supported(sky2->hw);
3559 	wol->wolopts = sky2->wol;
3560 }
3561 
3562 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3563 {
3564 	struct sky2_port *sky2 = netdev_priv(dev);
3565 	struct sky2_hw *hw = sky2->hw;
3566 	bool enable_wakeup = false;
3567 	int i;
3568 
3569 	if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3570 	    !device_can_wakeup(&hw->pdev->dev))
3571 		return -EOPNOTSUPP;
3572 
3573 	sky2->wol = wol->wolopts;
3574 
3575 	for (i = 0; i < hw->ports; i++) {
3576 		struct net_device *dev = hw->dev[i];
3577 		struct sky2_port *sky2 = netdev_priv(dev);
3578 
3579 		if (sky2->wol)
3580 			enable_wakeup = true;
3581 	}
3582 	device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3583 
3584 	return 0;
3585 }
3586 
3587 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3588 {
3589 	if (sky2_is_copper(hw)) {
3590 		u32 modes = SUPPORTED_10baseT_Half
3591 			| SUPPORTED_10baseT_Full
3592 			| SUPPORTED_100baseT_Half
3593 			| SUPPORTED_100baseT_Full;
3594 
3595 		if (hw->flags & SKY2_HW_GIGABIT)
3596 			modes |= SUPPORTED_1000baseT_Half
3597 				| SUPPORTED_1000baseT_Full;
3598 		return modes;
3599 	} else
3600 		return SUPPORTED_1000baseT_Half
3601 			| SUPPORTED_1000baseT_Full;
3602 }
3603 
3604 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3605 {
3606 	struct sky2_port *sky2 = netdev_priv(dev);
3607 	struct sky2_hw *hw = sky2->hw;
3608 
3609 	ecmd->transceiver = XCVR_INTERNAL;
3610 	ecmd->supported = sky2_supported_modes(hw);
3611 	ecmd->phy_address = PHY_ADDR_MARV;
3612 	if (sky2_is_copper(hw)) {
3613 		ecmd->port = PORT_TP;
3614 		ethtool_cmd_speed_set(ecmd, sky2->speed);
3615 		ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_TP;
3616 	} else {
3617 		ethtool_cmd_speed_set(ecmd, SPEED_1000);
3618 		ecmd->port = PORT_FIBRE;
3619 		ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3620 	}
3621 
3622 	ecmd->advertising = sky2->advertising;
3623 	ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3624 		? AUTONEG_ENABLE : AUTONEG_DISABLE;
3625 	ecmd->duplex = sky2->duplex;
3626 	return 0;
3627 }
3628 
3629 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3630 {
3631 	struct sky2_port *sky2 = netdev_priv(dev);
3632 	const struct sky2_hw *hw = sky2->hw;
3633 	u32 supported = sky2_supported_modes(hw);
3634 
3635 	if (ecmd->autoneg == AUTONEG_ENABLE) {
3636 		if (ecmd->advertising & ~supported)
3637 			return -EINVAL;
3638 
3639 		if (sky2_is_copper(hw))
3640 			sky2->advertising = ecmd->advertising |
3641 					    ADVERTISED_TP |
3642 					    ADVERTISED_Autoneg;
3643 		else
3644 			sky2->advertising = ecmd->advertising |
3645 					    ADVERTISED_FIBRE |
3646 					    ADVERTISED_Autoneg;
3647 
3648 		sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3649 		sky2->duplex = -1;
3650 		sky2->speed = -1;
3651 	} else {
3652 		u32 setting;
3653 		u32 speed = ethtool_cmd_speed(ecmd);
3654 
3655 		switch (speed) {
3656 		case SPEED_1000:
3657 			if (ecmd->duplex == DUPLEX_FULL)
3658 				setting = SUPPORTED_1000baseT_Full;
3659 			else if (ecmd->duplex == DUPLEX_HALF)
3660 				setting = SUPPORTED_1000baseT_Half;
3661 			else
3662 				return -EINVAL;
3663 			break;
3664 		case SPEED_100:
3665 			if (ecmd->duplex == DUPLEX_FULL)
3666 				setting = SUPPORTED_100baseT_Full;
3667 			else if (ecmd->duplex == DUPLEX_HALF)
3668 				setting = SUPPORTED_100baseT_Half;
3669 			else
3670 				return -EINVAL;
3671 			break;
3672 
3673 		case SPEED_10:
3674 			if (ecmd->duplex == DUPLEX_FULL)
3675 				setting = SUPPORTED_10baseT_Full;
3676 			else if (ecmd->duplex == DUPLEX_HALF)
3677 				setting = SUPPORTED_10baseT_Half;
3678 			else
3679 				return -EINVAL;
3680 			break;
3681 		default:
3682 			return -EINVAL;
3683 		}
3684 
3685 		if ((setting & supported) == 0)
3686 			return -EINVAL;
3687 
3688 		sky2->speed = speed;
3689 		sky2->duplex = ecmd->duplex;
3690 		sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3691 	}
3692 
3693 	if (netif_running(dev)) {
3694 		sky2_phy_reinit(sky2);
3695 		sky2_set_multicast(dev);
3696 	}
3697 
3698 	return 0;
3699 }
3700 
3701 static void sky2_get_drvinfo(struct net_device *dev,
3702 			     struct ethtool_drvinfo *info)
3703 {
3704 	struct sky2_port *sky2 = netdev_priv(dev);
3705 
3706 	strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3707 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3708 	strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3709 		sizeof(info->bus_info));
3710 }
3711 
3712 static const struct sky2_stat {
3713 	char name[ETH_GSTRING_LEN];
3714 	u16 offset;
3715 } sky2_stats[] = {
3716 	{ "tx_bytes",	   GM_TXO_OK_HI },
3717 	{ "rx_bytes",	   GM_RXO_OK_HI },
3718 	{ "tx_broadcast",  GM_TXF_BC_OK },
3719 	{ "rx_broadcast",  GM_RXF_BC_OK },
3720 	{ "tx_multicast",  GM_TXF_MC_OK },
3721 	{ "rx_multicast",  GM_RXF_MC_OK },
3722 	{ "tx_unicast",    GM_TXF_UC_OK },
3723 	{ "rx_unicast",    GM_RXF_UC_OK },
3724 	{ "tx_mac_pause",  GM_TXF_MPAUSE },
3725 	{ "rx_mac_pause",  GM_RXF_MPAUSE },
3726 	{ "collisions",    GM_TXF_COL },
3727 	{ "late_collision",GM_TXF_LAT_COL },
3728 	{ "aborted", 	   GM_TXF_ABO_COL },
3729 	{ "single_collisions", GM_TXF_SNG_COL },
3730 	{ "multi_collisions", GM_TXF_MUL_COL },
3731 
3732 	{ "rx_short",      GM_RXF_SHT },
3733 	{ "rx_runt", 	   GM_RXE_FRAG },
3734 	{ "rx_64_byte_packets", GM_RXF_64B },
3735 	{ "rx_65_to_127_byte_packets", GM_RXF_127B },
3736 	{ "rx_128_to_255_byte_packets", GM_RXF_255B },
3737 	{ "rx_256_to_511_byte_packets", GM_RXF_511B },
3738 	{ "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3739 	{ "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3740 	{ "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3741 	{ "rx_too_long",   GM_RXF_LNG_ERR },
3742 	{ "rx_fifo_overflow", GM_RXE_FIFO_OV },
3743 	{ "rx_jabber",     GM_RXF_JAB_PKT },
3744 	{ "rx_fcs_error",   GM_RXF_FCS_ERR },
3745 
3746 	{ "tx_64_byte_packets", GM_TXF_64B },
3747 	{ "tx_65_to_127_byte_packets", GM_TXF_127B },
3748 	{ "tx_128_to_255_byte_packets", GM_TXF_255B },
3749 	{ "tx_256_to_511_byte_packets", GM_TXF_511B },
3750 	{ "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3751 	{ "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3752 	{ "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3753 	{ "tx_fifo_underrun", GM_TXE_FIFO_UR },
3754 };
3755 
3756 static u32 sky2_get_msglevel(struct net_device *netdev)
3757 {
3758 	struct sky2_port *sky2 = netdev_priv(netdev);
3759 	return sky2->msg_enable;
3760 }
3761 
3762 static int sky2_nway_reset(struct net_device *dev)
3763 {
3764 	struct sky2_port *sky2 = netdev_priv(dev);
3765 
3766 	if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3767 		return -EINVAL;
3768 
3769 	sky2_phy_reinit(sky2);
3770 	sky2_set_multicast(dev);
3771 
3772 	return 0;
3773 }
3774 
3775 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3776 {
3777 	struct sky2_hw *hw = sky2->hw;
3778 	unsigned port = sky2->port;
3779 	int i;
3780 
3781 	data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3782 	data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3783 
3784 	for (i = 2; i < count; i++)
3785 		data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3786 }
3787 
3788 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3789 {
3790 	struct sky2_port *sky2 = netdev_priv(netdev);
3791 	sky2->msg_enable = value;
3792 }
3793 
3794 static int sky2_get_sset_count(struct net_device *dev, int sset)
3795 {
3796 	switch (sset) {
3797 	case ETH_SS_STATS:
3798 		return ARRAY_SIZE(sky2_stats);
3799 	default:
3800 		return -EOPNOTSUPP;
3801 	}
3802 }
3803 
3804 static void sky2_get_ethtool_stats(struct net_device *dev,
3805 				   struct ethtool_stats *stats, u64 * data)
3806 {
3807 	struct sky2_port *sky2 = netdev_priv(dev);
3808 
3809 	sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3810 }
3811 
3812 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3813 {
3814 	int i;
3815 
3816 	switch (stringset) {
3817 	case ETH_SS_STATS:
3818 		for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3819 			memcpy(data + i * ETH_GSTRING_LEN,
3820 			       sky2_stats[i].name, ETH_GSTRING_LEN);
3821 		break;
3822 	}
3823 }
3824 
3825 static int sky2_set_mac_address(struct net_device *dev, void *p)
3826 {
3827 	struct sky2_port *sky2 = netdev_priv(dev);
3828 	struct sky2_hw *hw = sky2->hw;
3829 	unsigned port = sky2->port;
3830 	const struct sockaddr *addr = p;
3831 
3832 	if (!is_valid_ether_addr(addr->sa_data))
3833 		return -EADDRNOTAVAIL;
3834 
3835 	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3836 	memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3837 		    dev->dev_addr, ETH_ALEN);
3838 	memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3839 		    dev->dev_addr, ETH_ALEN);
3840 
3841 	/* virtual address for data */
3842 	gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3843 
3844 	/* physical address: used for pause frames */
3845 	gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3846 
3847 	return 0;
3848 }
3849 
3850 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3851 {
3852 	u32 bit;
3853 
3854 	bit = ether_crc(ETH_ALEN, addr) & 63;
3855 	filter[bit >> 3] |= 1 << (bit & 7);
3856 }
3857 
3858 static void sky2_set_multicast(struct net_device *dev)
3859 {
3860 	struct sky2_port *sky2 = netdev_priv(dev);
3861 	struct sky2_hw *hw = sky2->hw;
3862 	unsigned port = sky2->port;
3863 	struct netdev_hw_addr *ha;
3864 	u16 reg;
3865 	u8 filter[8];
3866 	int rx_pause;
3867 	static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3868 
3869 	rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3870 	memset(filter, 0, sizeof(filter));
3871 
3872 	reg = gma_read16(hw, port, GM_RX_CTRL);
3873 	reg |= GM_RXCR_UCF_ENA;
3874 
3875 	if (dev->flags & IFF_PROMISC)	/* promiscuous */
3876 		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3877 	else if (dev->flags & IFF_ALLMULTI)
3878 		memset(filter, 0xff, sizeof(filter));
3879 	else if (netdev_mc_empty(dev) && !rx_pause)
3880 		reg &= ~GM_RXCR_MCF_ENA;
3881 	else {
3882 		reg |= GM_RXCR_MCF_ENA;
3883 
3884 		if (rx_pause)
3885 			sky2_add_filter(filter, pause_mc_addr);
3886 
3887 		netdev_for_each_mc_addr(ha, dev)
3888 			sky2_add_filter(filter, ha->addr);
3889 	}
3890 
3891 	gma_write16(hw, port, GM_MC_ADDR_H1,
3892 		    (u16) filter[0] | ((u16) filter[1] << 8));
3893 	gma_write16(hw, port, GM_MC_ADDR_H2,
3894 		    (u16) filter[2] | ((u16) filter[3] << 8));
3895 	gma_write16(hw, port, GM_MC_ADDR_H3,
3896 		    (u16) filter[4] | ((u16) filter[5] << 8));
3897 	gma_write16(hw, port, GM_MC_ADDR_H4,
3898 		    (u16) filter[6] | ((u16) filter[7] << 8));
3899 
3900 	gma_write16(hw, port, GM_RX_CTRL, reg);
3901 }
3902 
3903 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3904 						struct rtnl_link_stats64 *stats)
3905 {
3906 	struct sky2_port *sky2 = netdev_priv(dev);
3907 	struct sky2_hw *hw = sky2->hw;
3908 	unsigned port = sky2->port;
3909 	unsigned int start;
3910 	u64 _bytes, _packets;
3911 
3912 	do {
3913 		start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3914 		_bytes = sky2->rx_stats.bytes;
3915 		_packets = sky2->rx_stats.packets;
3916 	} while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3917 
3918 	stats->rx_packets = _packets;
3919 	stats->rx_bytes = _bytes;
3920 
3921 	do {
3922 		start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3923 		_bytes = sky2->tx_stats.bytes;
3924 		_packets = sky2->tx_stats.packets;
3925 	} while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3926 
3927 	stats->tx_packets = _packets;
3928 	stats->tx_bytes = _bytes;
3929 
3930 	stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3931 		+ get_stats32(hw, port, GM_RXF_BC_OK);
3932 
3933 	stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3934 
3935 	stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3936 	stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3937 	stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3938 		+ get_stats32(hw, port, GM_RXE_FRAG);
3939 	stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3940 
3941 	stats->rx_dropped = dev->stats.rx_dropped;
3942 	stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3943 	stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3944 
3945 	return stats;
3946 }
3947 
3948 /* Can have one global because blinking is controlled by
3949  * ethtool and that is always under RTNL mutex
3950  */
3951 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3952 {
3953 	struct sky2_hw *hw = sky2->hw;
3954 	unsigned port = sky2->port;
3955 
3956 	spin_lock_bh(&sky2->phy_lock);
3957 	if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3958 	    hw->chip_id == CHIP_ID_YUKON_EX ||
3959 	    hw->chip_id == CHIP_ID_YUKON_SUPR) {
3960 		u16 pg;
3961 		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3962 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3963 
3964 		switch (mode) {
3965 		case MO_LED_OFF:
3966 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3967 				     PHY_M_LEDC_LOS_CTRL(8) |
3968 				     PHY_M_LEDC_INIT_CTRL(8) |
3969 				     PHY_M_LEDC_STA1_CTRL(8) |
3970 				     PHY_M_LEDC_STA0_CTRL(8));
3971 			break;
3972 		case MO_LED_ON:
3973 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3974 				     PHY_M_LEDC_LOS_CTRL(9) |
3975 				     PHY_M_LEDC_INIT_CTRL(9) |
3976 				     PHY_M_LEDC_STA1_CTRL(9) |
3977 				     PHY_M_LEDC_STA0_CTRL(9));
3978 			break;
3979 		case MO_LED_BLINK:
3980 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3981 				     PHY_M_LEDC_LOS_CTRL(0xa) |
3982 				     PHY_M_LEDC_INIT_CTRL(0xa) |
3983 				     PHY_M_LEDC_STA1_CTRL(0xa) |
3984 				     PHY_M_LEDC_STA0_CTRL(0xa));
3985 			break;
3986 		case MO_LED_NORM:
3987 			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3988 				     PHY_M_LEDC_LOS_CTRL(1) |
3989 				     PHY_M_LEDC_INIT_CTRL(8) |
3990 				     PHY_M_LEDC_STA1_CTRL(7) |
3991 				     PHY_M_LEDC_STA0_CTRL(7));
3992 		}
3993 
3994 		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3995 	} else
3996 		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3997 				     PHY_M_LED_MO_DUP(mode) |
3998 				     PHY_M_LED_MO_10(mode) |
3999 				     PHY_M_LED_MO_100(mode) |
4000 				     PHY_M_LED_MO_1000(mode) |
4001 				     PHY_M_LED_MO_RX(mode) |
4002 				     PHY_M_LED_MO_TX(mode));
4003 
4004 	spin_unlock_bh(&sky2->phy_lock);
4005 }
4006 
4007 /* blink LED's for finding board */
4008 static int sky2_set_phys_id(struct net_device *dev,
4009 			    enum ethtool_phys_id_state state)
4010 {
4011 	struct sky2_port *sky2 = netdev_priv(dev);
4012 
4013 	switch (state) {
4014 	case ETHTOOL_ID_ACTIVE:
4015 		return 1;	/* cycle on/off once per second */
4016 	case ETHTOOL_ID_INACTIVE:
4017 		sky2_led(sky2, MO_LED_NORM);
4018 		break;
4019 	case ETHTOOL_ID_ON:
4020 		sky2_led(sky2, MO_LED_ON);
4021 		break;
4022 	case ETHTOOL_ID_OFF:
4023 		sky2_led(sky2, MO_LED_OFF);
4024 		break;
4025 	}
4026 
4027 	return 0;
4028 }
4029 
4030 static void sky2_get_pauseparam(struct net_device *dev,
4031 				struct ethtool_pauseparam *ecmd)
4032 {
4033 	struct sky2_port *sky2 = netdev_priv(dev);
4034 
4035 	switch (sky2->flow_mode) {
4036 	case FC_NONE:
4037 		ecmd->tx_pause = ecmd->rx_pause = 0;
4038 		break;
4039 	case FC_TX:
4040 		ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4041 		break;
4042 	case FC_RX:
4043 		ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4044 		break;
4045 	case FC_BOTH:
4046 		ecmd->tx_pause = ecmd->rx_pause = 1;
4047 	}
4048 
4049 	ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4050 		? AUTONEG_ENABLE : AUTONEG_DISABLE;
4051 }
4052 
4053 static int sky2_set_pauseparam(struct net_device *dev,
4054 			       struct ethtool_pauseparam *ecmd)
4055 {
4056 	struct sky2_port *sky2 = netdev_priv(dev);
4057 
4058 	if (ecmd->autoneg == AUTONEG_ENABLE)
4059 		sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4060 	else
4061 		sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4062 
4063 	sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4064 
4065 	if (netif_running(dev))
4066 		sky2_phy_reinit(sky2);
4067 
4068 	return 0;
4069 }
4070 
4071 static int sky2_get_coalesce(struct net_device *dev,
4072 			     struct ethtool_coalesce *ecmd)
4073 {
4074 	struct sky2_port *sky2 = netdev_priv(dev);
4075 	struct sky2_hw *hw = sky2->hw;
4076 
4077 	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4078 		ecmd->tx_coalesce_usecs = 0;
4079 	else {
4080 		u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4081 		ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4082 	}
4083 	ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4084 
4085 	if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4086 		ecmd->rx_coalesce_usecs = 0;
4087 	else {
4088 		u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4089 		ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4090 	}
4091 	ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4092 
4093 	if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4094 		ecmd->rx_coalesce_usecs_irq = 0;
4095 	else {
4096 		u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4097 		ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4098 	}
4099 
4100 	ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4101 
4102 	return 0;
4103 }
4104 
4105 /* Note: this affect both ports */
4106 static int sky2_set_coalesce(struct net_device *dev,
4107 			     struct ethtool_coalesce *ecmd)
4108 {
4109 	struct sky2_port *sky2 = netdev_priv(dev);
4110 	struct sky2_hw *hw = sky2->hw;
4111 	const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4112 
4113 	if (ecmd->tx_coalesce_usecs > tmax ||
4114 	    ecmd->rx_coalesce_usecs > tmax ||
4115 	    ecmd->rx_coalesce_usecs_irq > tmax)
4116 		return -EINVAL;
4117 
4118 	if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4119 		return -EINVAL;
4120 	if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4121 		return -EINVAL;
4122 	if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4123 		return -EINVAL;
4124 
4125 	if (ecmd->tx_coalesce_usecs == 0)
4126 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4127 	else {
4128 		sky2_write32(hw, STAT_TX_TIMER_INI,
4129 			     sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4130 		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4131 	}
4132 	sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4133 
4134 	if (ecmd->rx_coalesce_usecs == 0)
4135 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4136 	else {
4137 		sky2_write32(hw, STAT_LEV_TIMER_INI,
4138 			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4139 		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4140 	}
4141 	sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4142 
4143 	if (ecmd->rx_coalesce_usecs_irq == 0)
4144 		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4145 	else {
4146 		sky2_write32(hw, STAT_ISR_TIMER_INI,
4147 			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4148 		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4149 	}
4150 	sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4151 	return 0;
4152 }
4153 
4154 /*
4155  * Hardware is limited to min of 128 and max of 2048 for ring size
4156  * and  rounded up to next power of two
4157  * to avoid division in modulus calclation
4158  */
4159 static unsigned long roundup_ring_size(unsigned long pending)
4160 {
4161 	return max(128ul, roundup_pow_of_two(pending+1));
4162 }
4163 
4164 static void sky2_get_ringparam(struct net_device *dev,
4165 			       struct ethtool_ringparam *ering)
4166 {
4167 	struct sky2_port *sky2 = netdev_priv(dev);
4168 
4169 	ering->rx_max_pending = RX_MAX_PENDING;
4170 	ering->tx_max_pending = TX_MAX_PENDING;
4171 
4172 	ering->rx_pending = sky2->rx_pending;
4173 	ering->tx_pending = sky2->tx_pending;
4174 }
4175 
4176 static int sky2_set_ringparam(struct net_device *dev,
4177 			      struct ethtool_ringparam *ering)
4178 {
4179 	struct sky2_port *sky2 = netdev_priv(dev);
4180 
4181 	if (ering->rx_pending > RX_MAX_PENDING ||
4182 	    ering->rx_pending < 8 ||
4183 	    ering->tx_pending < TX_MIN_PENDING ||
4184 	    ering->tx_pending > TX_MAX_PENDING)
4185 		return -EINVAL;
4186 
4187 	sky2_detach(dev);
4188 
4189 	sky2->rx_pending = ering->rx_pending;
4190 	sky2->tx_pending = ering->tx_pending;
4191 	sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4192 
4193 	return sky2_reattach(dev);
4194 }
4195 
4196 static int sky2_get_regs_len(struct net_device *dev)
4197 {
4198 	return 0x4000;
4199 }
4200 
4201 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4202 {
4203 	/* This complicated switch statement is to make sure and
4204 	 * only access regions that are unreserved.
4205 	 * Some blocks are only valid on dual port cards.
4206 	 */
4207 	switch (b) {
4208 	/* second port */
4209 	case 5:		/* Tx Arbiter 2 */
4210 	case 9:		/* RX2 */
4211 	case 14 ... 15:	/* TX2 */
4212 	case 17: case 19: /* Ram Buffer 2 */
4213 	case 22 ... 23: /* Tx Ram Buffer 2 */
4214 	case 25:	/* Rx MAC Fifo 1 */
4215 	case 27:	/* Tx MAC Fifo 2 */
4216 	case 31:	/* GPHY 2 */
4217 	case 40 ... 47: /* Pattern Ram 2 */
4218 	case 52: case 54: /* TCP Segmentation 2 */
4219 	case 112 ... 116: /* GMAC 2 */
4220 		return hw->ports > 1;
4221 
4222 	case 0:		/* Control */
4223 	case 2:		/* Mac address */
4224 	case 4:		/* Tx Arbiter 1 */
4225 	case 7:		/* PCI express reg */
4226 	case 8:		/* RX1 */
4227 	case 12 ... 13: /* TX1 */
4228 	case 16: case 18:/* Rx Ram Buffer 1 */
4229 	case 20 ... 21: /* Tx Ram Buffer 1 */
4230 	case 24:	/* Rx MAC Fifo 1 */
4231 	case 26:	/* Tx MAC Fifo 1 */
4232 	case 28 ... 29: /* Descriptor and status unit */
4233 	case 30:	/* GPHY 1*/
4234 	case 32 ... 39: /* Pattern Ram 1 */
4235 	case 48: case 50: /* TCP Segmentation 1 */
4236 	case 56 ... 60:	/* PCI space */
4237 	case 80 ... 84:	/* GMAC 1 */
4238 		return 1;
4239 
4240 	default:
4241 		return 0;
4242 	}
4243 }
4244 
4245 /*
4246  * Returns copy of control register region
4247  * Note: ethtool_get_regs always provides full size (16k) buffer
4248  */
4249 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4250 			  void *p)
4251 {
4252 	const struct sky2_port *sky2 = netdev_priv(dev);
4253 	const void __iomem *io = sky2->hw->regs;
4254 	unsigned int b;
4255 
4256 	regs->version = 1;
4257 
4258 	for (b = 0; b < 128; b++) {
4259 		/* skip poisonous diagnostic ram region in block 3 */
4260 		if (b == 3)
4261 			memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4262 		else if (sky2_reg_access_ok(sky2->hw, b))
4263 			memcpy_fromio(p, io, 128);
4264 		else
4265 			memset(p, 0, 128);
4266 
4267 		p += 128;
4268 		io += 128;
4269 	}
4270 }
4271 
4272 static int sky2_get_eeprom_len(struct net_device *dev)
4273 {
4274 	struct sky2_port *sky2 = netdev_priv(dev);
4275 	struct sky2_hw *hw = sky2->hw;
4276 	u16 reg2;
4277 
4278 	reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4279 	return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4280 }
4281 
4282 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4283 {
4284 	unsigned long start = jiffies;
4285 
4286 	while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4287 		/* Can take up to 10.6 ms for write */
4288 		if (time_after(jiffies, start + HZ/4)) {
4289 			dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4290 			return -ETIMEDOUT;
4291 		}
4292 		mdelay(1);
4293 	}
4294 
4295 	return 0;
4296 }
4297 
4298 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4299 			 u16 offset, size_t length)
4300 {
4301 	int rc = 0;
4302 
4303 	while (length > 0) {
4304 		u32 val;
4305 
4306 		sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4307 		rc = sky2_vpd_wait(hw, cap, 0);
4308 		if (rc)
4309 			break;
4310 
4311 		val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4312 
4313 		memcpy(data, &val, min(sizeof(val), length));
4314 		offset += sizeof(u32);
4315 		data += sizeof(u32);
4316 		length -= sizeof(u32);
4317 	}
4318 
4319 	return rc;
4320 }
4321 
4322 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4323 			  u16 offset, unsigned int length)
4324 {
4325 	unsigned int i;
4326 	int rc = 0;
4327 
4328 	for (i = 0; i < length; i += sizeof(u32)) {
4329 		u32 val = *(u32 *)(data + i);
4330 
4331 		sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4332 		sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4333 
4334 		rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4335 		if (rc)
4336 			break;
4337 	}
4338 	return rc;
4339 }
4340 
4341 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4342 			   u8 *data)
4343 {
4344 	struct sky2_port *sky2 = netdev_priv(dev);
4345 	int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4346 
4347 	if (!cap)
4348 		return -EINVAL;
4349 
4350 	eeprom->magic = SKY2_EEPROM_MAGIC;
4351 
4352 	return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4353 }
4354 
4355 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4356 			   u8 *data)
4357 {
4358 	struct sky2_port *sky2 = netdev_priv(dev);
4359 	int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4360 
4361 	if (!cap)
4362 		return -EINVAL;
4363 
4364 	if (eeprom->magic != SKY2_EEPROM_MAGIC)
4365 		return -EINVAL;
4366 
4367 	/* Partial writes not supported */
4368 	if ((eeprom->offset & 3) || (eeprom->len & 3))
4369 		return -EINVAL;
4370 
4371 	return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4372 }
4373 
4374 static netdev_features_t sky2_fix_features(struct net_device *dev,
4375 	netdev_features_t features)
4376 {
4377 	const struct sky2_port *sky2 = netdev_priv(dev);
4378 	const struct sky2_hw *hw = sky2->hw;
4379 
4380 	/* In order to do Jumbo packets on these chips, need to turn off the
4381 	 * transmit store/forward. Therefore checksum offload won't work.
4382 	 */
4383 	if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4384 		netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4385 		features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
4386 	}
4387 
4388 	/* Some hardware requires receive checksum for RSS to work. */
4389 	if ( (features & NETIF_F_RXHASH) &&
4390 	     !(features & NETIF_F_RXCSUM) &&
4391 	     (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4392 		netdev_info(dev, "receive hashing forces receive checksum\n");
4393 		features |= NETIF_F_RXCSUM;
4394 	}
4395 
4396 	return features;
4397 }
4398 
4399 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4400 {
4401 	struct sky2_port *sky2 = netdev_priv(dev);
4402 	netdev_features_t changed = dev->features ^ features;
4403 
4404 	if ((changed & NETIF_F_RXCSUM) &&
4405 	    !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4406 		sky2_write32(sky2->hw,
4407 			     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4408 			     (features & NETIF_F_RXCSUM)
4409 			     ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4410 	}
4411 
4412 	if (changed & NETIF_F_RXHASH)
4413 		rx_set_rss(dev, features);
4414 
4415 	if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4416 		sky2_vlan_mode(dev, features);
4417 
4418 	return 0;
4419 }
4420 
4421 static const struct ethtool_ops sky2_ethtool_ops = {
4422 	.get_settings	= sky2_get_settings,
4423 	.set_settings	= sky2_set_settings,
4424 	.get_drvinfo	= sky2_get_drvinfo,
4425 	.get_wol	= sky2_get_wol,
4426 	.set_wol	= sky2_set_wol,
4427 	.get_msglevel	= sky2_get_msglevel,
4428 	.set_msglevel	= sky2_set_msglevel,
4429 	.nway_reset	= sky2_nway_reset,
4430 	.get_regs_len	= sky2_get_regs_len,
4431 	.get_regs	= sky2_get_regs,
4432 	.get_link	= ethtool_op_get_link,
4433 	.get_eeprom_len	= sky2_get_eeprom_len,
4434 	.get_eeprom	= sky2_get_eeprom,
4435 	.set_eeprom	= sky2_set_eeprom,
4436 	.get_strings	= sky2_get_strings,
4437 	.get_coalesce	= sky2_get_coalesce,
4438 	.set_coalesce	= sky2_set_coalesce,
4439 	.get_ringparam	= sky2_get_ringparam,
4440 	.set_ringparam	= sky2_set_ringparam,
4441 	.get_pauseparam = sky2_get_pauseparam,
4442 	.set_pauseparam = sky2_set_pauseparam,
4443 	.set_phys_id	= sky2_set_phys_id,
4444 	.get_sset_count = sky2_get_sset_count,
4445 	.get_ethtool_stats = sky2_get_ethtool_stats,
4446 };
4447 
4448 #ifdef CONFIG_SKY2_DEBUG
4449 
4450 static struct dentry *sky2_debug;
4451 
4452 
4453 /*
4454  * Read and parse the first part of Vital Product Data
4455  */
4456 #define VPD_SIZE	128
4457 #define VPD_MAGIC	0x82
4458 
4459 static const struct vpd_tag {
4460 	char tag[2];
4461 	char *label;
4462 } vpd_tags[] = {
4463 	{ "PN",	"Part Number" },
4464 	{ "EC", "Engineering Level" },
4465 	{ "MN", "Manufacturer" },
4466 	{ "SN", "Serial Number" },
4467 	{ "YA", "Asset Tag" },
4468 	{ "VL", "First Error Log Message" },
4469 	{ "VF", "Second Error Log Message" },
4470 	{ "VB", "Boot Agent ROM Configuration" },
4471 	{ "VE", "EFI UNDI Configuration" },
4472 };
4473 
4474 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4475 {
4476 	size_t vpd_size;
4477 	loff_t offs;
4478 	u8 len;
4479 	unsigned char *buf;
4480 	u16 reg2;
4481 
4482 	reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4483 	vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4484 
4485 	seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4486 	buf = kmalloc(vpd_size, GFP_KERNEL);
4487 	if (!buf) {
4488 		seq_puts(seq, "no memory!\n");
4489 		return;
4490 	}
4491 
4492 	if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4493 		seq_puts(seq, "VPD read failed\n");
4494 		goto out;
4495 	}
4496 
4497 	if (buf[0] != VPD_MAGIC) {
4498 		seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4499 		goto out;
4500 	}
4501 	len = buf[1];
4502 	if (len == 0 || len > vpd_size - 4) {
4503 		seq_printf(seq, "Invalid id length: %d\n", len);
4504 		goto out;
4505 	}
4506 
4507 	seq_printf(seq, "%.*s\n", len, buf + 3);
4508 	offs = len + 3;
4509 
4510 	while (offs < vpd_size - 4) {
4511 		int i;
4512 
4513 		if (!memcmp("RW", buf + offs, 2))	/* end marker */
4514 			break;
4515 		len = buf[offs + 2];
4516 		if (offs + len + 3 >= vpd_size)
4517 			break;
4518 
4519 		for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4520 			if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4521 				seq_printf(seq, " %s: %.*s\n",
4522 					   vpd_tags[i].label, len, buf + offs + 3);
4523 				break;
4524 			}
4525 		}
4526 		offs += len + 3;
4527 	}
4528 out:
4529 	kfree(buf);
4530 }
4531 
4532 static int sky2_debug_show(struct seq_file *seq, void *v)
4533 {
4534 	struct net_device *dev = seq->private;
4535 	const struct sky2_port *sky2 = netdev_priv(dev);
4536 	struct sky2_hw *hw = sky2->hw;
4537 	unsigned port = sky2->port;
4538 	unsigned idx, last;
4539 	int sop;
4540 
4541 	sky2_show_vpd(seq, hw);
4542 
4543 	seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4544 		   sky2_read32(hw, B0_ISRC),
4545 		   sky2_read32(hw, B0_IMSK),
4546 		   sky2_read32(hw, B0_Y2_SP_ICR));
4547 
4548 	if (!netif_running(dev)) {
4549 		seq_printf(seq, "network not running\n");
4550 		return 0;
4551 	}
4552 
4553 	napi_disable(&hw->napi);
4554 	last = sky2_read16(hw, STAT_PUT_IDX);
4555 
4556 	seq_printf(seq, "Status ring %u\n", hw->st_size);
4557 	if (hw->st_idx == last)
4558 		seq_puts(seq, "Status ring (empty)\n");
4559 	else {
4560 		seq_puts(seq, "Status ring\n");
4561 		for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4562 		     idx = RING_NEXT(idx, hw->st_size)) {
4563 			const struct sky2_status_le *le = hw->st_le + idx;
4564 			seq_printf(seq, "[%d] %#x %d %#x\n",
4565 				   idx, le->opcode, le->length, le->status);
4566 		}
4567 		seq_puts(seq, "\n");
4568 	}
4569 
4570 	seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4571 		   sky2->tx_cons, sky2->tx_prod,
4572 		   sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4573 		   sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4574 
4575 	/* Dump contents of tx ring */
4576 	sop = 1;
4577 	for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4578 	     idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4579 		const struct sky2_tx_le *le = sky2->tx_le + idx;
4580 		u32 a = le32_to_cpu(le->addr);
4581 
4582 		if (sop)
4583 			seq_printf(seq, "%u:", idx);
4584 		sop = 0;
4585 
4586 		switch (le->opcode & ~HW_OWNER) {
4587 		case OP_ADDR64:
4588 			seq_printf(seq, " %#x:", a);
4589 			break;
4590 		case OP_LRGLEN:
4591 			seq_printf(seq, " mtu=%d", a);
4592 			break;
4593 		case OP_VLAN:
4594 			seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4595 			break;
4596 		case OP_TCPLISW:
4597 			seq_printf(seq, " csum=%#x", a);
4598 			break;
4599 		case OP_LARGESEND:
4600 			seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4601 			break;
4602 		case OP_PACKET:
4603 			seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4604 			break;
4605 		case OP_BUFFER:
4606 			seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4607 			break;
4608 		default:
4609 			seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4610 				   a, le16_to_cpu(le->length));
4611 		}
4612 
4613 		if (le->ctrl & EOP) {
4614 			seq_putc(seq, '\n');
4615 			sop = 1;
4616 		}
4617 	}
4618 
4619 	seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4620 		   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4621 		   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4622 		   sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4623 
4624 	sky2_read32(hw, B0_Y2_SP_LISR);
4625 	napi_enable(&hw->napi);
4626 	return 0;
4627 }
4628 
4629 static int sky2_debug_open(struct inode *inode, struct file *file)
4630 {
4631 	return single_open(file, sky2_debug_show, inode->i_private);
4632 }
4633 
4634 static const struct file_operations sky2_debug_fops = {
4635 	.owner		= THIS_MODULE,
4636 	.open		= sky2_debug_open,
4637 	.read		= seq_read,
4638 	.llseek		= seq_lseek,
4639 	.release	= single_release,
4640 };
4641 
4642 /*
4643  * Use network device events to create/remove/rename
4644  * debugfs file entries
4645  */
4646 static int sky2_device_event(struct notifier_block *unused,
4647 			     unsigned long event, void *ptr)
4648 {
4649 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4650 	struct sky2_port *sky2 = netdev_priv(dev);
4651 
4652 	if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4653 		return NOTIFY_DONE;
4654 
4655 	switch (event) {
4656 	case NETDEV_CHANGENAME:
4657 		if (sky2->debugfs) {
4658 			sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4659 						       sky2_debug, dev->name);
4660 		}
4661 		break;
4662 
4663 	case NETDEV_GOING_DOWN:
4664 		if (sky2->debugfs) {
4665 			netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4666 			debugfs_remove(sky2->debugfs);
4667 			sky2->debugfs = NULL;
4668 		}
4669 		break;
4670 
4671 	case NETDEV_UP:
4672 		sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4673 						    sky2_debug, dev,
4674 						    &sky2_debug_fops);
4675 		if (IS_ERR(sky2->debugfs))
4676 			sky2->debugfs = NULL;
4677 	}
4678 
4679 	return NOTIFY_DONE;
4680 }
4681 
4682 static struct notifier_block sky2_notifier = {
4683 	.notifier_call = sky2_device_event,
4684 };
4685 
4686 
4687 static __init void sky2_debug_init(void)
4688 {
4689 	struct dentry *ent;
4690 
4691 	ent = debugfs_create_dir("sky2", NULL);
4692 	if (!ent || IS_ERR(ent))
4693 		return;
4694 
4695 	sky2_debug = ent;
4696 	register_netdevice_notifier(&sky2_notifier);
4697 }
4698 
4699 static __exit void sky2_debug_cleanup(void)
4700 {
4701 	if (sky2_debug) {
4702 		unregister_netdevice_notifier(&sky2_notifier);
4703 		debugfs_remove(sky2_debug);
4704 		sky2_debug = NULL;
4705 	}
4706 }
4707 
4708 #else
4709 #define sky2_debug_init()
4710 #define sky2_debug_cleanup()
4711 #endif
4712 
4713 /* Two copies of network device operations to handle special case of
4714    not allowing netpoll on second port */
4715 static const struct net_device_ops sky2_netdev_ops[2] = {
4716   {
4717 	.ndo_open		= sky2_open,
4718 	.ndo_stop		= sky2_close,
4719 	.ndo_start_xmit		= sky2_xmit_frame,
4720 	.ndo_do_ioctl		= sky2_ioctl,
4721 	.ndo_validate_addr	= eth_validate_addr,
4722 	.ndo_set_mac_address	= sky2_set_mac_address,
4723 	.ndo_set_rx_mode	= sky2_set_multicast,
4724 	.ndo_change_mtu		= sky2_change_mtu,
4725 	.ndo_fix_features	= sky2_fix_features,
4726 	.ndo_set_features	= sky2_set_features,
4727 	.ndo_tx_timeout		= sky2_tx_timeout,
4728 	.ndo_get_stats64	= sky2_get_stats,
4729 #ifdef CONFIG_NET_POLL_CONTROLLER
4730 	.ndo_poll_controller	= sky2_netpoll,
4731 #endif
4732   },
4733   {
4734 	.ndo_open		= sky2_open,
4735 	.ndo_stop		= sky2_close,
4736 	.ndo_start_xmit		= sky2_xmit_frame,
4737 	.ndo_do_ioctl		= sky2_ioctl,
4738 	.ndo_validate_addr	= eth_validate_addr,
4739 	.ndo_set_mac_address	= sky2_set_mac_address,
4740 	.ndo_set_rx_mode	= sky2_set_multicast,
4741 	.ndo_change_mtu		= sky2_change_mtu,
4742 	.ndo_fix_features	= sky2_fix_features,
4743 	.ndo_set_features	= sky2_set_features,
4744 	.ndo_tx_timeout		= sky2_tx_timeout,
4745 	.ndo_get_stats64	= sky2_get_stats,
4746   },
4747 };
4748 
4749 /* Initialize network device */
4750 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4751 					   int highmem, int wol)
4752 {
4753 	struct sky2_port *sky2;
4754 	struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4755 	const void *iap;
4756 
4757 	if (!dev)
4758 		return NULL;
4759 
4760 	SET_NETDEV_DEV(dev, &hw->pdev->dev);
4761 	dev->irq = hw->pdev->irq;
4762 	dev->ethtool_ops = &sky2_ethtool_ops;
4763 	dev->watchdog_timeo = TX_WATCHDOG;
4764 	dev->netdev_ops = &sky2_netdev_ops[port];
4765 
4766 	sky2 = netdev_priv(dev);
4767 	sky2->netdev = dev;
4768 	sky2->hw = hw;
4769 	sky2->msg_enable = netif_msg_init(debug, default_msg);
4770 
4771 	u64_stats_init(&sky2->tx_stats.syncp);
4772 	u64_stats_init(&sky2->rx_stats.syncp);
4773 
4774 	/* Auto speed and flow control */
4775 	sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4776 	if (hw->chip_id != CHIP_ID_YUKON_XL)
4777 		dev->hw_features |= NETIF_F_RXCSUM;
4778 
4779 	sky2->flow_mode = FC_BOTH;
4780 
4781 	sky2->duplex = -1;
4782 	sky2->speed = -1;
4783 	sky2->advertising = sky2_supported_modes(hw);
4784 	sky2->wol = wol;
4785 
4786 	spin_lock_init(&sky2->phy_lock);
4787 
4788 	sky2->tx_pending = TX_DEF_PENDING;
4789 	sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4790 	sky2->rx_pending = RX_DEF_PENDING;
4791 
4792 	hw->dev[port] = dev;
4793 
4794 	sky2->port = port;
4795 
4796 	dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4797 
4798 	if (highmem)
4799 		dev->features |= NETIF_F_HIGHDMA;
4800 
4801 	/* Enable receive hashing unless hardware is known broken */
4802 	if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4803 		dev->hw_features |= NETIF_F_RXHASH;
4804 
4805 	if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4806 		dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4807 				    NETIF_F_HW_VLAN_CTAG_RX;
4808 		dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4809 	}
4810 
4811 	dev->features |= dev->hw_features;
4812 
4813 	/* try to get mac address in the following order:
4814 	 * 1) from device tree data
4815 	 * 2) from internal registers set by bootloader
4816 	 */
4817 	iap = of_get_mac_address(hw->pdev->dev.of_node);
4818 	if (iap)
4819 		memcpy(dev->dev_addr, iap, ETH_ALEN);
4820 	else
4821 		memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4822 			      ETH_ALEN);
4823 
4824 	return dev;
4825 }
4826 
4827 static void sky2_show_addr(struct net_device *dev)
4828 {
4829 	const struct sky2_port *sky2 = netdev_priv(dev);
4830 
4831 	netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4832 }
4833 
4834 /* Handle software interrupt used during MSI test */
4835 static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4836 {
4837 	struct sky2_hw *hw = dev_id;
4838 	u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4839 
4840 	if (status == 0)
4841 		return IRQ_NONE;
4842 
4843 	if (status & Y2_IS_IRQ_SW) {
4844 		hw->flags |= SKY2_HW_USE_MSI;
4845 		wake_up(&hw->msi_wait);
4846 		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4847 	}
4848 	sky2_write32(hw, B0_Y2_SP_ICR, 2);
4849 
4850 	return IRQ_HANDLED;
4851 }
4852 
4853 /* Test interrupt path by forcing a a software IRQ */
4854 static int sky2_test_msi(struct sky2_hw *hw)
4855 {
4856 	struct pci_dev *pdev = hw->pdev;
4857 	int err;
4858 
4859 	init_waitqueue_head(&hw->msi_wait);
4860 
4861 	err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4862 	if (err) {
4863 		dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4864 		return err;
4865 	}
4866 
4867 	sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4868 
4869 	sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4870 	sky2_read8(hw, B0_CTST);
4871 
4872 	wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4873 
4874 	if (!(hw->flags & SKY2_HW_USE_MSI)) {
4875 		/* MSI test failed, go back to INTx mode */
4876 		dev_info(&pdev->dev, "No interrupt generated using MSI, "
4877 			 "switching to INTx mode.\n");
4878 
4879 		err = -EOPNOTSUPP;
4880 		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4881 	}
4882 
4883 	sky2_write32(hw, B0_IMSK, 0);
4884 	sky2_read32(hw, B0_IMSK);
4885 
4886 	free_irq(pdev->irq, hw);
4887 
4888 	return err;
4889 }
4890 
4891 /* This driver supports yukon2 chipset only */
4892 static const char *sky2_name(u8 chipid, char *buf, int sz)
4893 {
4894 	const char *name[] = {
4895 		"XL",		/* 0xb3 */
4896 		"EC Ultra", 	/* 0xb4 */
4897 		"Extreme",	/* 0xb5 */
4898 		"EC",		/* 0xb6 */
4899 		"FE",		/* 0xb7 */
4900 		"FE+",		/* 0xb8 */
4901 		"Supreme",	/* 0xb9 */
4902 		"UL 2",		/* 0xba */
4903 		"Unknown",	/* 0xbb */
4904 		"Optima",	/* 0xbc */
4905 		"OptimaEEE",    /* 0xbd */
4906 		"Optima 2",	/* 0xbe */
4907 	};
4908 
4909 	if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4910 		strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4911 	else
4912 		snprintf(buf, sz, "(chip %#x)", chipid);
4913 	return buf;
4914 }
4915 
4916 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4917 {
4918 	struct net_device *dev, *dev1;
4919 	struct sky2_hw *hw;
4920 	int err, using_dac = 0, wol_default;
4921 	u32 reg;
4922 	char buf1[16];
4923 
4924 	err = pci_enable_device(pdev);
4925 	if (err) {
4926 		dev_err(&pdev->dev, "cannot enable PCI device\n");
4927 		goto err_out;
4928 	}
4929 
4930 	/* Get configuration information
4931 	 * Note: only regular PCI config access once to test for HW issues
4932 	 *       other PCI access through shared memory for speed and to
4933 	 *	 avoid MMCONFIG problems.
4934 	 */
4935 	err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4936 	if (err) {
4937 		dev_err(&pdev->dev, "PCI read config failed\n");
4938 		goto err_out_disable;
4939 	}
4940 
4941 	if (~reg == 0) {
4942 		dev_err(&pdev->dev, "PCI configuration read error\n");
4943 		err = -EIO;
4944 		goto err_out_disable;
4945 	}
4946 
4947 	err = pci_request_regions(pdev, DRV_NAME);
4948 	if (err) {
4949 		dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4950 		goto err_out_disable;
4951 	}
4952 
4953 	pci_set_master(pdev);
4954 
4955 	if (sizeof(dma_addr_t) > sizeof(u32) &&
4956 	    !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4957 		using_dac = 1;
4958 		err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4959 		if (err < 0) {
4960 			dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4961 				"for consistent allocations\n");
4962 			goto err_out_free_regions;
4963 		}
4964 	} else {
4965 		err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4966 		if (err) {
4967 			dev_err(&pdev->dev, "no usable DMA configuration\n");
4968 			goto err_out_free_regions;
4969 		}
4970 	}
4971 
4972 
4973 #ifdef __BIG_ENDIAN
4974 	/* The sk98lin vendor driver uses hardware byte swapping but
4975 	 * this driver uses software swapping.
4976 	 */
4977 	reg &= ~PCI_REV_DESC;
4978 	err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4979 	if (err) {
4980 		dev_err(&pdev->dev, "PCI write config failed\n");
4981 		goto err_out_free_regions;
4982 	}
4983 #endif
4984 
4985 	wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4986 
4987 	err = -ENOMEM;
4988 
4989 	hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4990 		     + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4991 	if (!hw)
4992 		goto err_out_free_regions;
4993 
4994 	hw->pdev = pdev;
4995 	sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4996 
4997 	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4998 	if (!hw->regs) {
4999 		dev_err(&pdev->dev, "cannot map device registers\n");
5000 		goto err_out_free_hw;
5001 	}
5002 
5003 	err = sky2_init(hw);
5004 	if (err)
5005 		goto err_out_iounmap;
5006 
5007 	/* ring for status responses */
5008 	hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
5009 	hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5010 					 &hw->st_dma);
5011 	if (!hw->st_le) {
5012 		err = -ENOMEM;
5013 		goto err_out_reset;
5014 	}
5015 
5016 	dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5017 		 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5018 
5019 	sky2_reset(hw);
5020 
5021 	dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5022 	if (!dev) {
5023 		err = -ENOMEM;
5024 		goto err_out_free_pci;
5025 	}
5026 
5027 	if (!disable_msi && pci_enable_msi(pdev) == 0) {
5028 		err = sky2_test_msi(hw);
5029 		if (err) {
5030  			pci_disable_msi(pdev);
5031 			if (err != -EOPNOTSUPP)
5032 				goto err_out_free_netdev;
5033 		}
5034  	}
5035 
5036 	netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5037 
5038 	err = register_netdev(dev);
5039 	if (err) {
5040 		dev_err(&pdev->dev, "cannot register net device\n");
5041 		goto err_out_free_netdev;
5042 	}
5043 
5044 	netif_carrier_off(dev);
5045 
5046 	sky2_show_addr(dev);
5047 
5048 	if (hw->ports > 1) {
5049 		dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5050 		if (!dev1) {
5051 			err = -ENOMEM;
5052 			goto err_out_unregister;
5053 		}
5054 
5055 		err = register_netdev(dev1);
5056 		if (err) {
5057 			dev_err(&pdev->dev, "cannot register second net device\n");
5058 			goto err_out_free_dev1;
5059 		}
5060 
5061 		err = sky2_setup_irq(hw, hw->irq_name);
5062 		if (err)
5063 			goto err_out_unregister_dev1;
5064 
5065 		sky2_show_addr(dev1);
5066 	}
5067 
5068 	setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
5069 	INIT_WORK(&hw->restart_work, sky2_restart);
5070 
5071 	pci_set_drvdata(pdev, hw);
5072 	pdev->d3_delay = 150;
5073 
5074 	return 0;
5075 
5076 err_out_unregister_dev1:
5077 	unregister_netdev(dev1);
5078 err_out_free_dev1:
5079 	free_netdev(dev1);
5080 err_out_unregister:
5081 	unregister_netdev(dev);
5082 err_out_free_netdev:
5083 	if (hw->flags & SKY2_HW_USE_MSI)
5084 		pci_disable_msi(pdev);
5085 	free_netdev(dev);
5086 err_out_free_pci:
5087 	pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5088 			    hw->st_le, hw->st_dma);
5089 err_out_reset:
5090 	sky2_write8(hw, B0_CTST, CS_RST_SET);
5091 err_out_iounmap:
5092 	iounmap(hw->regs);
5093 err_out_free_hw:
5094 	kfree(hw);
5095 err_out_free_regions:
5096 	pci_release_regions(pdev);
5097 err_out_disable:
5098 	pci_disable_device(pdev);
5099 err_out:
5100 	return err;
5101 }
5102 
5103 static void sky2_remove(struct pci_dev *pdev)
5104 {
5105 	struct sky2_hw *hw = pci_get_drvdata(pdev);
5106 	int i;
5107 
5108 	if (!hw)
5109 		return;
5110 
5111 	del_timer_sync(&hw->watchdog_timer);
5112 	cancel_work_sync(&hw->restart_work);
5113 
5114 	for (i = hw->ports-1; i >= 0; --i)
5115 		unregister_netdev(hw->dev[i]);
5116 
5117 	sky2_write32(hw, B0_IMSK, 0);
5118 	sky2_read32(hw, B0_IMSK);
5119 
5120 	sky2_power_aux(hw);
5121 
5122 	sky2_write8(hw, B0_CTST, CS_RST_SET);
5123 	sky2_read8(hw, B0_CTST);
5124 
5125 	if (hw->ports > 1) {
5126 		napi_disable(&hw->napi);
5127 		free_irq(pdev->irq, hw);
5128 	}
5129 
5130 	if (hw->flags & SKY2_HW_USE_MSI)
5131 		pci_disable_msi(pdev);
5132 	pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5133 			    hw->st_le, hw->st_dma);
5134 	pci_release_regions(pdev);
5135 	pci_disable_device(pdev);
5136 
5137 	for (i = hw->ports-1; i >= 0; --i)
5138 		free_netdev(hw->dev[i]);
5139 
5140 	iounmap(hw->regs);
5141 	kfree(hw);
5142 }
5143 
5144 static int sky2_suspend(struct device *dev)
5145 {
5146 	struct pci_dev *pdev = to_pci_dev(dev);
5147 	struct sky2_hw *hw = pci_get_drvdata(pdev);
5148 	int i;
5149 
5150 	if (!hw)
5151 		return 0;
5152 
5153 	del_timer_sync(&hw->watchdog_timer);
5154 	cancel_work_sync(&hw->restart_work);
5155 
5156 	rtnl_lock();
5157 
5158 	sky2_all_down(hw);
5159 	for (i = 0; i < hw->ports; i++) {
5160 		struct net_device *dev = hw->dev[i];
5161 		struct sky2_port *sky2 = netdev_priv(dev);
5162 
5163 		if (sky2->wol)
5164 			sky2_wol_init(sky2);
5165 	}
5166 
5167 	sky2_power_aux(hw);
5168 	rtnl_unlock();
5169 
5170 	return 0;
5171 }
5172 
5173 #ifdef CONFIG_PM_SLEEP
5174 static int sky2_resume(struct device *dev)
5175 {
5176 	struct pci_dev *pdev = to_pci_dev(dev);
5177 	struct sky2_hw *hw = pci_get_drvdata(pdev);
5178 	int err;
5179 
5180 	if (!hw)
5181 		return 0;
5182 
5183 	/* Re-enable all clocks */
5184 	err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5185 	if (err) {
5186 		dev_err(&pdev->dev, "PCI write config failed\n");
5187 		goto out;
5188 	}
5189 
5190 	rtnl_lock();
5191 	sky2_reset(hw);
5192 	sky2_all_up(hw);
5193 	rtnl_unlock();
5194 
5195 	return 0;
5196 out:
5197 
5198 	dev_err(&pdev->dev, "resume failed (%d)\n", err);
5199 	pci_disable_device(pdev);
5200 	return err;
5201 }
5202 
5203 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5204 #define SKY2_PM_OPS (&sky2_pm_ops)
5205 
5206 #else
5207 
5208 #define SKY2_PM_OPS NULL
5209 #endif
5210 
5211 static void sky2_shutdown(struct pci_dev *pdev)
5212 {
5213 	sky2_suspend(&pdev->dev);
5214 	pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5215 	pci_set_power_state(pdev, PCI_D3hot);
5216 }
5217 
5218 static struct pci_driver sky2_driver = {
5219 	.name = DRV_NAME,
5220 	.id_table = sky2_id_table,
5221 	.probe = sky2_probe,
5222 	.remove = sky2_remove,
5223 	.shutdown = sky2_shutdown,
5224 	.driver.pm = SKY2_PM_OPS,
5225 };
5226 
5227 static int __init sky2_init_module(void)
5228 {
5229 	pr_info("driver version " DRV_VERSION "\n");
5230 
5231 	sky2_debug_init();
5232 	return pci_register_driver(&sky2_driver);
5233 }
5234 
5235 static void __exit sky2_cleanup_module(void)
5236 {
5237 	pci_unregister_driver(&sky2_driver);
5238 	sky2_debug_cleanup();
5239 }
5240 
5241 module_init(sky2_init_module);
5242 module_exit(sky2_cleanup_module);
5243 
5244 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5245 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5246 MODULE_LICENSE("GPL");
5247 MODULE_VERSION(DRV_VERSION);
5248