1 /* 2 * New driver for Marvell Yukon 2 chipset. 3 * Based on earlier sk98lin, and skge driver. 4 * 5 * This driver intentionally does not support all the features 6 * of the original driver such as link fail-over and link management because 7 * those should be done at higher levels. 8 * 9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 26 27 #include <linux/crc32.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/netdevice.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/etherdevice.h> 33 #include <linux/ethtool.h> 34 #include <linux/pci.h> 35 #include <linux/interrupt.h> 36 #include <linux/ip.h> 37 #include <linux/slab.h> 38 #include <net/ip.h> 39 #include <linux/tcp.h> 40 #include <linux/in.h> 41 #include <linux/delay.h> 42 #include <linux/workqueue.h> 43 #include <linux/if_vlan.h> 44 #include <linux/prefetch.h> 45 #include <linux/debugfs.h> 46 #include <linux/mii.h> 47 #include <linux/of_device.h> 48 #include <linux/of_net.h> 49 #include <linux/dmi.h> 50 51 #include <asm/irq.h> 52 53 #include "sky2.h" 54 55 #define DRV_NAME "sky2" 56 #define DRV_VERSION "1.30" 57 58 /* 59 * The Yukon II chipset takes 64 bit command blocks (called list elements) 60 * that are organized into three (receive, transmit, status) different rings 61 * similar to Tigon3. 62 */ 63 64 #define RX_LE_SIZE 1024 65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) 66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2) 67 #define RX_DEF_PENDING RX_MAX_PENDING 68 69 /* This is the worst case number of transmit list elements for a single skb: 70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */ 71 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1)) 72 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1) 73 #define TX_MAX_PENDING 1024 74 #define TX_DEF_PENDING 63 75 76 #define TX_WATCHDOG (5 * HZ) 77 #define NAPI_WEIGHT 64 78 #define PHY_RETRIES 1000 79 80 #define SKY2_EEPROM_MAGIC 0x9955aabb 81 82 #define RING_NEXT(x, s) (((x)+1) & ((s)-1)) 83 84 static const u32 default_msg = 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK 86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; 88 89 static int debug = -1; /* defaults above */ 90 module_param(debug, int, 0); 91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 92 93 static int copybreak __read_mostly = 128; 94 module_param(copybreak, int, 0); 95 MODULE_PARM_DESC(copybreak, "Receive copy threshold"); 96 97 static int disable_msi = -1; 98 module_param(disable_msi, int, 0); 99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); 100 101 static int legacy_pme = 0; 102 module_param(legacy_pme, int, 0); 103 MODULE_PARM_DESC(legacy_pme, "Legacy power management"); 104 105 static const struct pci_device_id sky2_id_table[] = { 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */ 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */ 108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */ 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */ 112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */ 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */ 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */ 115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */ 116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */ 117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */ 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */ 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */ 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */ 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */ 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */ 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */ 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */ 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */ 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */ 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */ 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */ 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */ 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */ 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */ 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */ 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */ 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */ 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */ 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */ 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */ 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */ 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */ 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */ 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */ 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */ 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */ 144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */ 145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */ 146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */ 147 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */ 148 { 0 } 149 }; 150 151 MODULE_DEVICE_TABLE(pci, sky2_id_table); 152 153 /* Avoid conditionals by using array */ 154 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; 155 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; 156 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; 157 158 static void sky2_set_multicast(struct net_device *dev); 159 static irqreturn_t sky2_intr(int irq, void *dev_id); 160 161 /* Access to PHY via serial interconnect */ 162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) 163 { 164 int i; 165 166 gma_write16(hw, port, GM_SMI_DATA, val); 167 gma_write16(hw, port, GM_SMI_CTRL, 168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 169 170 for (i = 0; i < PHY_RETRIES; i++) { 171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 172 if (ctrl == 0xffff) 173 goto io_error; 174 175 if (!(ctrl & GM_SMI_CT_BUSY)) 176 return 0; 177 178 udelay(10); 179 } 180 181 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name); 182 return -ETIMEDOUT; 183 184 io_error: 185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 186 return -EIO; 187 } 188 189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) 190 { 191 int i; 192 193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 195 196 for (i = 0; i < PHY_RETRIES; i++) { 197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 198 if (ctrl == 0xffff) 199 goto io_error; 200 201 if (ctrl & GM_SMI_CT_RD_VAL) { 202 *val = gma_read16(hw, port, GM_SMI_DATA); 203 return 0; 204 } 205 206 udelay(10); 207 } 208 209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name); 210 return -ETIMEDOUT; 211 io_error: 212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name); 213 return -EIO; 214 } 215 216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) 217 { 218 u16 v; 219 __gm_phy_read(hw, port, reg, &v); 220 return v; 221 } 222 223 224 static void sky2_power_on(struct sky2_hw *hw) 225 { 226 /* switch power to VCC (WA for VAUX problem) */ 227 sky2_write8(hw, B0_POWER_CTRL, 228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 229 230 /* disable Core Clock Division, */ 231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 232 233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 234 /* enable bits are inverted */ 235 sky2_write8(hw, B2_Y2_CLK_GATE, 236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 239 else 240 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 241 242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 243 u32 reg; 244 245 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 246 247 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 248 /* set all bits to 0 except bits 15..12 and 8 */ 249 reg &= P_ASPM_CONTROL_MSK; 250 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 251 252 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 253 /* set all bits to 0 except bits 28 & 27 */ 254 reg &= P_CTL_TIM_VMAIN_AV_MSK; 255 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 256 257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 258 259 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON); 260 261 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 262 reg = sky2_read32(hw, B2_GP_IO); 263 reg |= GLB_GPIO_STAT_RACE_DIS; 264 sky2_write32(hw, B2_GP_IO, reg); 265 266 sky2_read32(hw, B2_GP_IO); 267 } 268 269 /* Turn on "driver loaded" LED */ 270 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON); 271 } 272 273 static void sky2_power_aux(struct sky2_hw *hw) 274 { 275 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 276 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 277 else 278 /* enable bits are inverted */ 279 sky2_write8(hw, B2_Y2_CLK_GATE, 280 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 281 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 282 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 283 284 /* switch power to VAUX if supported and PME from D3cold */ 285 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) && 286 pci_pme_capable(hw->pdev, PCI_D3cold)) 287 sky2_write8(hw, B0_POWER_CTRL, 288 (PC_VAUX_ENA | PC_VCC_ENA | 289 PC_VAUX_ON | PC_VCC_OFF)); 290 291 /* turn off "driver loaded LED" */ 292 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF); 293 } 294 295 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) 296 { 297 u16 reg; 298 299 /* disable all GMAC IRQ's */ 300 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 301 302 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 303 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 304 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 305 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 306 307 reg = gma_read16(hw, port, GM_RX_CTRL); 308 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 309 gma_write16(hw, port, GM_RX_CTRL, reg); 310 } 311 312 /* flow control to advertise bits */ 313 static const u16 copper_fc_adv[] = { 314 [FC_NONE] = 0, 315 [FC_TX] = PHY_M_AN_ASP, 316 [FC_RX] = PHY_M_AN_PC, 317 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP, 318 }; 319 320 /* flow control to advertise bits when using 1000BaseX */ 321 static const u16 fiber_fc_adv[] = { 322 [FC_NONE] = PHY_M_P_NO_PAUSE_X, 323 [FC_TX] = PHY_M_P_ASYM_MD_X, 324 [FC_RX] = PHY_M_P_SYM_MD_X, 325 [FC_BOTH] = PHY_M_P_BOTH_MD_X, 326 }; 327 328 /* flow control to GMA disable bits */ 329 static const u16 gm_fc_disable[] = { 330 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS, 331 [FC_TX] = GM_GPCR_FC_RX_DIS, 332 [FC_RX] = GM_GPCR_FC_TX_DIS, 333 [FC_BOTH] = 0, 334 }; 335 336 337 static void sky2_phy_init(struct sky2_hw *hw, unsigned port) 338 { 339 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 340 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 341 342 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 343 !(hw->flags & SKY2_HW_NEWER_PHY)) { 344 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 345 346 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 347 PHY_M_EC_MAC_S_MSK); 348 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 349 350 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 351 if (hw->chip_id == CHIP_ID_YUKON_EC) 352 /* set downshift counter to 3x and enable downshift */ 353 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 354 else 355 /* set master & slave downshift counter to 1x */ 356 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 357 358 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 359 } 360 361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 362 if (sky2_is_copper(hw)) { 363 if (!(hw->flags & SKY2_HW_GIGABIT)) { 364 /* enable automatic crossover */ 365 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 366 367 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 368 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 369 u16 spec; 370 371 /* Enable Class A driver for FE+ A0 */ 372 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 373 spec |= PHY_M_FESC_SEL_CL_A; 374 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 375 } 376 } else { 377 /* disable energy detect */ 378 ctrl &= ~PHY_M_PC_EN_DET_MSK; 379 380 /* enable automatic crossover */ 381 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 382 383 /* downshift on PHY 88E1112 and 88E1149 is changed */ 384 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) && 385 (hw->flags & SKY2_HW_NEWER_PHY)) { 386 /* set downshift counter to 3x and enable downshift */ 387 ctrl &= ~PHY_M_PC_DSC_MSK; 388 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 389 } 390 } 391 } else { 392 /* workaround for deviation #4.88 (CRC errors) */ 393 /* disable Automatic Crossover */ 394 395 ctrl &= ~PHY_M_PC_MDIX_MSK; 396 } 397 398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 399 400 /* special setup for PHY 88E1112 Fiber */ 401 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 402 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 403 404 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 407 ctrl &= ~PHY_M_MAC_MD_MSK; 408 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 410 411 if (hw->pmd_type == 'P') { 412 /* select page 1 to access Fiber registers */ 413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 414 415 /* for SFP-module set SIGDET polarity to low */ 416 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 417 ctrl |= PHY_M_FIB_SIGD_POL; 418 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 419 } 420 421 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 422 } 423 424 ctrl = PHY_CT_RESET; 425 ct1000 = 0; 426 adv = PHY_AN_CSMA; 427 reg = 0; 428 429 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) { 430 if (sky2_is_copper(hw)) { 431 if (sky2->advertising & ADVERTISED_1000baseT_Full) 432 ct1000 |= PHY_M_1000C_AFD; 433 if (sky2->advertising & ADVERTISED_1000baseT_Half) 434 ct1000 |= PHY_M_1000C_AHD; 435 if (sky2->advertising & ADVERTISED_100baseT_Full) 436 adv |= PHY_M_AN_100_FD; 437 if (sky2->advertising & ADVERTISED_100baseT_Half) 438 adv |= PHY_M_AN_100_HD; 439 if (sky2->advertising & ADVERTISED_10baseT_Full) 440 adv |= PHY_M_AN_10_FD; 441 if (sky2->advertising & ADVERTISED_10baseT_Half) 442 adv |= PHY_M_AN_10_HD; 443 444 } else { /* special defines for FIBER (88E1040S only) */ 445 if (sky2->advertising & ADVERTISED_1000baseT_Full) 446 adv |= PHY_M_AN_1000X_AFD; 447 if (sky2->advertising & ADVERTISED_1000baseT_Half) 448 adv |= PHY_M_AN_1000X_AHD; 449 } 450 451 /* Restart Auto-negotiation */ 452 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 453 } else { 454 /* forced speed/duplex settings */ 455 ct1000 = PHY_M_1000C_MSE; 456 457 /* Disable auto update for duplex flow control and duplex */ 458 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS; 459 460 switch (sky2->speed) { 461 case SPEED_1000: 462 ctrl |= PHY_CT_SP1000; 463 reg |= GM_GPCR_SPEED_1000; 464 break; 465 case SPEED_100: 466 ctrl |= PHY_CT_SP100; 467 reg |= GM_GPCR_SPEED_100; 468 break; 469 } 470 471 if (sky2->duplex == DUPLEX_FULL) { 472 reg |= GM_GPCR_DUP_FULL; 473 ctrl |= PHY_CT_DUP_MD; 474 } else if (sky2->speed < SPEED_1000) 475 sky2->flow_mode = FC_NONE; 476 } 477 478 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) { 479 if (sky2_is_copper(hw)) 480 adv |= copper_fc_adv[sky2->flow_mode]; 481 else 482 adv |= fiber_fc_adv[sky2->flow_mode]; 483 } else { 484 reg |= GM_GPCR_AU_FCT_DIS; 485 reg |= gm_fc_disable[sky2->flow_mode]; 486 487 /* Forward pause packets to GMAC? */ 488 if (sky2->flow_mode & FC_RX) 489 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 490 else 491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 492 } 493 494 gma_write16(hw, port, GM_GP_CTRL, reg); 495 496 if (hw->flags & SKY2_HW_GIGABIT) 497 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 498 499 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 500 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 501 502 /* Setup Phy LED's */ 503 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 504 ledover = 0; 505 506 switch (hw->chip_id) { 507 case CHIP_ID_YUKON_FE: 508 /* on 88E3082 these bits are at 11..9 (shifted left) */ 509 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 510 511 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 512 513 /* delete ACT LED control bits */ 514 ctrl &= ~PHY_M_FELP_LED1_MSK; 515 /* change ACT LED control to blink mode */ 516 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 517 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 518 break; 519 520 case CHIP_ID_YUKON_FE_P: 521 /* Enable Link Partner Next Page */ 522 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 523 ctrl |= PHY_M_PC_ENA_LIP_NP; 524 525 /* disable Energy Detect and enable scrambler */ 526 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 528 529 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 530 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 531 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 532 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 533 534 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 535 break; 536 537 case CHIP_ID_YUKON_XL: 538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 539 540 /* select page 3 to access LED control register */ 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 542 543 /* set LED Function Control register */ 544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 546 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 548 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 549 550 /* set Polarity Control register */ 551 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 552 (PHY_M_POLC_LS1_P_MIX(4) | 553 PHY_M_POLC_IS0_P_MIX(4) | 554 PHY_M_POLC_LOS_CTRL(2) | 555 PHY_M_POLC_INIT_CTRL(2) | 556 PHY_M_POLC_STA1_CTRL(2) | 557 PHY_M_POLC_STA0_CTRL(2))); 558 559 /* restore page register */ 560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 561 break; 562 563 case CHIP_ID_YUKON_EC_U: 564 case CHIP_ID_YUKON_EX: 565 case CHIP_ID_YUKON_SUPR: 566 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 567 568 /* select page 3 to access LED control register */ 569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 570 571 /* set LED Function Control register */ 572 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 573 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 574 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 575 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 576 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 577 578 /* set Blink Rate in LED Timer Control Register */ 579 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 580 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 581 /* restore page register */ 582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 583 break; 584 585 default: 586 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 587 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 588 589 /* turn off the Rx LED (LED_RX) */ 590 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 591 } 592 593 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 594 /* apply fixes in PHY AFE */ 595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 596 597 /* increase differential signal amplitude in 10BASE-T */ 598 gm_phy_write(hw, port, 0x18, 0xaa99); 599 gm_phy_write(hw, port, 0x17, 0x2011); 600 601 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 602 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 603 gm_phy_write(hw, port, 0x18, 0xa204); 604 gm_phy_write(hw, port, 0x17, 0x2002); 605 } 606 607 /* set page register to 0 */ 608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 609 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 610 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 611 /* apply workaround for integrated resistors calibration */ 612 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 613 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 614 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 615 /* apply fixes in PHY AFE */ 616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 617 618 /* apply RDAC termination workaround */ 619 gm_phy_write(hw, port, 24, 0x2800); 620 gm_phy_write(hw, port, 23, 0x2001); 621 622 /* set page register back to 0 */ 623 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 624 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 625 hw->chip_id < CHIP_ID_YUKON_SUPR) { 626 /* no effect on Yukon-XL */ 627 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 628 629 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) || 630 sky2->speed == SPEED_100) { 631 /* turn on 100 Mbps LED (LED_LINK100) */ 632 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 633 } 634 635 if (ledover) 636 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 637 638 } else if (hw->chip_id == CHIP_ID_YUKON_PRM && 639 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) { 640 int i; 641 /* This a phy register setup workaround copied from vendor driver. */ 642 static const struct { 643 u16 reg, val; 644 } eee_afe[] = { 645 { 0x156, 0x58ce }, 646 { 0x153, 0x99eb }, 647 { 0x141, 0x8064 }, 648 /* { 0x155, 0x130b },*/ 649 { 0x000, 0x0000 }, 650 { 0x151, 0x8433 }, 651 { 0x14b, 0x8c44 }, 652 { 0x14c, 0x0f90 }, 653 { 0x14f, 0x39aa }, 654 /* { 0x154, 0x2f39 },*/ 655 { 0x14d, 0xba33 }, 656 { 0x144, 0x0048 }, 657 { 0x152, 0x2010 }, 658 /* { 0x158, 0x1223 },*/ 659 { 0x140, 0x4444 }, 660 { 0x154, 0x2f3b }, 661 { 0x158, 0xb203 }, 662 { 0x157, 0x2029 }, 663 }; 664 665 /* Start Workaround for OptimaEEE Rev.Z0 */ 666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb); 667 668 gm_phy_write(hw, port, 1, 0x4099); 669 gm_phy_write(hw, port, 3, 0x1120); 670 gm_phy_write(hw, port, 11, 0x113c); 671 gm_phy_write(hw, port, 14, 0x8100); 672 gm_phy_write(hw, port, 15, 0x112a); 673 gm_phy_write(hw, port, 17, 0x1008); 674 675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc); 676 gm_phy_write(hw, port, 1, 0x20b0); 677 678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff); 679 680 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) { 681 /* apply AFE settings */ 682 gm_phy_write(hw, port, 17, eee_afe[i].val); 683 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13); 684 } 685 686 /* End Workaround for OptimaEEE */ 687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 688 689 /* Enable 10Base-Te (EEE) */ 690 if (hw->chip_id >= CHIP_ID_YUKON_PRM) { 691 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 692 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, 693 reg | PHY_M_10B_TE_ENABLE); 694 } 695 } 696 697 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 698 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) 699 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 700 else 701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 702 } 703 704 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; 705 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; 706 707 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port) 708 { 709 u32 reg1; 710 711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 712 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 713 reg1 &= ~phy_power[port]; 714 715 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1) 716 reg1 |= coma_mode[port]; 717 718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 720 sky2_pci_read32(hw, PCI_DEV_REG1); 721 722 if (hw->chip_id == CHIP_ID_YUKON_FE) 723 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 724 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 726 } 727 728 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port) 729 { 730 u32 reg1; 731 u16 ctrl; 732 733 /* release GPHY Control reset */ 734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 735 736 /* release GMAC reset */ 737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 738 739 if (hw->flags & SKY2_HW_NEWER_PHY) { 740 /* select page 2 to access MAC control register */ 741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 742 743 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 744 /* allow GMII Power Down */ 745 ctrl &= ~PHY_M_MAC_GMIF_PUP; 746 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 747 748 /* set page register back to 0 */ 749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 750 } 751 752 /* setup General Purpose Control Register */ 753 gma_write16(hw, port, GM_GP_CTRL, 754 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | 755 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS | 756 GM_GPCR_AU_SPD_DIS); 757 758 if (hw->chip_id != CHIP_ID_YUKON_EC) { 759 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 760 /* select page 2 to access MAC control register */ 761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 762 763 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 764 /* enable Power Down */ 765 ctrl |= PHY_M_PC_POW_D_ENA; 766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 767 768 /* set page register back to 0 */ 769 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 770 } 771 772 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 773 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 774 } 775 776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 777 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 778 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 779 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 780 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 781 } 782 783 /* configure IPG according to used link speed */ 784 static void sky2_set_ipg(struct sky2_port *sky2) 785 { 786 u16 reg; 787 788 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE); 789 reg &= ~GM_SMOD_IPG_MSK; 790 if (sky2->speed > SPEED_100) 791 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 792 else 793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 794 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg); 795 } 796 797 /* Enable Rx/Tx */ 798 static void sky2_enable_rx_tx(struct sky2_port *sky2) 799 { 800 struct sky2_hw *hw = sky2->hw; 801 unsigned port = sky2->port; 802 u16 reg; 803 804 reg = gma_read16(hw, port, GM_GP_CTRL); 805 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 806 gma_write16(hw, port, GM_GP_CTRL, reg); 807 } 808 809 /* Force a renegotiation */ 810 static void sky2_phy_reinit(struct sky2_port *sky2) 811 { 812 spin_lock_bh(&sky2->phy_lock); 813 sky2_phy_init(sky2->hw, sky2->port); 814 sky2_enable_rx_tx(sky2); 815 spin_unlock_bh(&sky2->phy_lock); 816 } 817 818 /* Put device in state to listen for Wake On Lan */ 819 static void sky2_wol_init(struct sky2_port *sky2) 820 { 821 struct sky2_hw *hw = sky2->hw; 822 unsigned port = sky2->port; 823 enum flow_control save_mode; 824 u16 ctrl; 825 826 /* Bring hardware out of reset */ 827 sky2_write16(hw, B0_CTST, CS_RST_CLR); 828 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 829 830 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 831 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 832 833 /* Force to 10/100 834 * sky2_reset will re-enable on resume 835 */ 836 save_mode = sky2->flow_mode; 837 ctrl = sky2->advertising; 838 839 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full); 840 sky2->flow_mode = FC_NONE; 841 842 spin_lock_bh(&sky2->phy_lock); 843 sky2_phy_power_up(hw, port); 844 sky2_phy_init(hw, port); 845 spin_unlock_bh(&sky2->phy_lock); 846 847 sky2->flow_mode = save_mode; 848 sky2->advertising = ctrl; 849 850 /* Set GMAC to no flow control and auto update for speed/duplex */ 851 gma_write16(hw, port, GM_GP_CTRL, 852 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 853 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 854 855 /* Set WOL address */ 856 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 857 sky2->netdev->dev_addr, ETH_ALEN); 858 859 /* Turn on appropriate WOL control bits */ 860 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 861 ctrl = 0; 862 if (sky2->wol & WAKE_PHY) 863 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 864 else 865 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 866 867 if (sky2->wol & WAKE_MAGIC) 868 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 869 else 870 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 871 872 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 873 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 874 875 /* Disable PiG firmware */ 876 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF); 877 878 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */ 879 if (legacy_pme) { 880 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 881 reg1 |= PCI_Y2_PME_LEGACY; 882 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 883 } 884 885 /* block receiver */ 886 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 887 sky2_read32(hw, B0_CTST); 888 } 889 890 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port) 891 { 892 struct net_device *dev = hw->dev[port]; 893 894 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 895 hw->chip_rev != CHIP_REV_YU_EX_A0) || 896 hw->chip_id >= CHIP_ID_YUKON_FE_P) { 897 /* Yukon-Extreme B0 and further Extreme devices */ 898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 899 } else if (dev->mtu > ETH_DATA_LEN) { 900 /* set Tx GMAC FIFO Almost Empty Threshold */ 901 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 902 (ECU_JUMBO_WM << 16) | ECU_AE_THR); 903 904 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); 905 } else 906 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 907 } 908 909 static void sky2_mac_init(struct sky2_hw *hw, unsigned port) 910 { 911 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 912 u16 reg; 913 u32 rx_reg; 914 int i; 915 const u8 *addr = hw->dev[port]->dev_addr; 916 917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 918 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 919 920 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 921 922 if (hw->chip_id == CHIP_ID_YUKON_XL && 923 hw->chip_rev == CHIP_REV_YU_XL_A0 && 924 port == 1) { 925 /* WA DEV_472 -- looks like crossed wires on port 2 */ 926 /* clear GMAC 1 Control reset */ 927 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 928 do { 929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 930 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 931 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 932 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 933 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 934 } 935 936 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 937 938 /* Enable Transmit FIFO Underrun */ 939 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 940 941 spin_lock_bh(&sky2->phy_lock); 942 sky2_phy_power_up(hw, port); 943 sky2_phy_init(hw, port); 944 spin_unlock_bh(&sky2->phy_lock); 945 946 /* MIB clear */ 947 reg = gma_read16(hw, port, GM_PHY_ADDR); 948 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 949 950 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 951 gma_read16(hw, port, i); 952 gma_write16(hw, port, GM_PHY_ADDR, reg); 953 954 /* transmit control */ 955 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 956 957 /* receive control reg: unicast + multicast + no FCS */ 958 gma_write16(hw, port, GM_RX_CTRL, 959 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 960 961 /* transmit flow control */ 962 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 963 964 /* transmit parameter */ 965 gma_write16(hw, port, GM_TX_PARAM, 966 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 967 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 968 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 969 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 970 971 /* serial mode register */ 972 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 973 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000); 974 975 if (hw->dev[port]->mtu > ETH_DATA_LEN) 976 reg |= GM_SMOD_JUMBO_ENA; 977 978 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 979 hw->chip_rev == CHIP_REV_YU_EC_U_B1) 980 reg |= GM_NEW_FLOW_CTRL; 981 982 gma_write16(hw, port, GM_SERIAL_MODE, reg); 983 984 /* virtual address for data */ 985 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 986 987 /* physical address: used for pause frames */ 988 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 989 990 /* ignore counter overflows */ 991 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 992 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 993 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 994 995 /* Configure Rx MAC FIFO */ 996 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 997 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 998 if (hw->chip_id == CHIP_ID_YUKON_EX || 999 hw->chip_id == CHIP_ID_YUKON_FE_P) 1000 rx_reg |= GMF_RX_OVER_ON; 1001 1002 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 1003 1004 if (hw->chip_id == CHIP_ID_YUKON_XL) { 1005 /* Hardware errata - clear flush mask */ 1006 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 1007 } else { 1008 /* Flush Rx MAC FIFO on any flow control or error */ 1009 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 1010 } 1011 1012 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 1013 reg = RX_GMF_FL_THR_DEF + 1; 1014 /* Another magic mystery workaround from sk98lin */ 1015 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1016 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1017 reg = 0x178; 1018 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 1019 1020 /* Configure Tx MAC FIFO */ 1021 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 1022 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 1023 1024 /* On chips without ram buffer, pause is controlled by MAC level */ 1025 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 1026 /* Pause threshold is scaled by 8 in bytes */ 1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1028 hw->chip_rev == CHIP_REV_YU_FE2_A0) 1029 reg = 1568 / 8; 1030 else 1031 reg = 1024 / 8; 1032 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg); 1033 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8); 1034 1035 sky2_set_tx_stfwd(hw, port); 1036 } 1037 1038 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 1039 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 1040 /* disable dynamic watermark */ 1041 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 1042 reg &= ~TX_DYN_WM_ENA; 1043 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 1044 } 1045 } 1046 1047 /* Assign Ram Buffer allocation to queue */ 1048 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space) 1049 { 1050 u32 end; 1051 1052 /* convert from K bytes to qwords used for hw register */ 1053 start *= 1024/8; 1054 space *= 1024/8; 1055 end = start + space - 1; 1056 1057 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 1058 sky2_write32(hw, RB_ADDR(q, RB_START), start); 1059 sky2_write32(hw, RB_ADDR(q, RB_END), end); 1060 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 1061 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 1062 1063 if (q == Q_R1 || q == Q_R2) { 1064 u32 tp = space - space/4; 1065 1066 /* On receive queue's set the thresholds 1067 * give receiver priority when > 3/4 full 1068 * send pause when down to 2K 1069 */ 1070 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 1071 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 1072 1073 tp = space - 8192/8; 1074 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 1075 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 1076 } else { 1077 /* Enable store & forward on Tx queue's because 1078 * Tx FIFO is only 1K on Yukon 1079 */ 1080 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 1081 } 1082 1083 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 1084 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 1085 } 1086 1087 /* Setup Bus Memory Interface */ 1088 static void sky2_qset(struct sky2_hw *hw, u16 q) 1089 { 1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 1092 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 1093 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 1094 } 1095 1096 /* Setup prefetch unit registers. This is the interface between 1097 * hardware and driver list elements 1098 */ 1099 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, 1100 dma_addr_t addr, u32 last) 1101 { 1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr)); 1105 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr)); 1106 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 1107 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 1108 1109 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 1110 } 1111 1112 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) 1113 { 1114 struct sky2_tx_le *le = sky2->tx_le + *slot; 1115 1116 *slot = RING_NEXT(*slot, sky2->tx_ring_size); 1117 le->ctrl = 0; 1118 return le; 1119 } 1120 1121 static void tx_init(struct sky2_port *sky2) 1122 { 1123 struct sky2_tx_le *le; 1124 1125 sky2->tx_prod = sky2->tx_cons = 0; 1126 sky2->tx_tcpsum = 0; 1127 sky2->tx_last_mss = 0; 1128 netdev_reset_queue(sky2->netdev); 1129 1130 le = get_tx_le(sky2, &sky2->tx_prod); 1131 le->addr = 0; 1132 le->opcode = OP_ADDR64 | HW_OWNER; 1133 sky2->tx_last_upper = 0; 1134 } 1135 1136 /* Update chip's next pointer */ 1137 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) 1138 { 1139 /* Make sure write' to descriptors are complete before we tell hardware */ 1140 wmb(); 1141 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 1142 1143 /* Synchronize I/O on since next processor may write to tail */ 1144 mmiowb(); 1145 } 1146 1147 1148 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) 1149 { 1150 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 1151 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 1152 le->ctrl = 0; 1153 return le; 1154 } 1155 1156 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2) 1157 { 1158 unsigned size; 1159 1160 /* Space needed for frame data + headers rounded up */ 1161 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1162 1163 /* Stopping point for hardware truncation */ 1164 return (size - 8) / sizeof(u32); 1165 } 1166 1167 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2) 1168 { 1169 struct rx_ring_info *re; 1170 unsigned size; 1171 1172 /* Space needed for frame data + headers rounded up */ 1173 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8); 1174 1175 sky2->rx_nfrags = size >> PAGE_SHIFT; 1176 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr)); 1177 1178 /* Compute residue after pages */ 1179 size -= sky2->rx_nfrags << PAGE_SHIFT; 1180 1181 /* Optimize to handle small packets and headers */ 1182 if (size < copybreak) 1183 size = copybreak; 1184 if (size < ETH_HLEN) 1185 size = ETH_HLEN; 1186 1187 return size; 1188 } 1189 1190 /* Build description to hardware for one receive segment */ 1191 static void sky2_rx_add(struct sky2_port *sky2, u8 op, 1192 dma_addr_t map, unsigned len) 1193 { 1194 struct sky2_rx_le *le; 1195 1196 if (sizeof(dma_addr_t) > sizeof(u32)) { 1197 le = sky2_next_rx(sky2); 1198 le->addr = cpu_to_le32(upper_32_bits(map)); 1199 le->opcode = OP_ADDR64 | HW_OWNER; 1200 } 1201 1202 le = sky2_next_rx(sky2); 1203 le->addr = cpu_to_le32(lower_32_bits(map)); 1204 le->length = cpu_to_le16(len); 1205 le->opcode = op | HW_OWNER; 1206 } 1207 1208 /* Build description to hardware for one possibly fragmented skb */ 1209 static void sky2_rx_submit(struct sky2_port *sky2, 1210 const struct rx_ring_info *re) 1211 { 1212 int i; 1213 1214 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 1215 1216 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++) 1217 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE); 1218 } 1219 1220 1221 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re, 1222 unsigned size) 1223 { 1224 struct sk_buff *skb = re->skb; 1225 int i; 1226 1227 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE); 1228 if (pci_dma_mapping_error(pdev, re->data_addr)) 1229 goto mapping_error; 1230 1231 dma_unmap_len_set(re, data_size, size); 1232 1233 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1234 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1235 1236 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0, 1237 skb_frag_size(frag), 1238 DMA_FROM_DEVICE); 1239 1240 if (dma_mapping_error(&pdev->dev, re->frag_addr[i])) 1241 goto map_page_error; 1242 } 1243 return 0; 1244 1245 map_page_error: 1246 while (--i >= 0) { 1247 pci_unmap_page(pdev, re->frag_addr[i], 1248 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1249 PCI_DMA_FROMDEVICE); 1250 } 1251 1252 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1253 PCI_DMA_FROMDEVICE); 1254 1255 mapping_error: 1256 if (net_ratelimit()) 1257 dev_warn(&pdev->dev, "%s: rx mapping error\n", 1258 skb->dev->name); 1259 return -EIO; 1260 } 1261 1262 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re) 1263 { 1264 struct sk_buff *skb = re->skb; 1265 int i; 1266 1267 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size), 1268 PCI_DMA_FROMDEVICE); 1269 1270 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) 1271 pci_unmap_page(pdev, re->frag_addr[i], 1272 skb_frag_size(&skb_shinfo(skb)->frags[i]), 1273 PCI_DMA_FROMDEVICE); 1274 } 1275 1276 /* Tell chip where to start receive checksum. 1277 * Actually has two checksums, but set both same to avoid possible byte 1278 * order problems. 1279 */ 1280 static void rx_set_checksum(struct sky2_port *sky2) 1281 { 1282 struct sky2_rx_le *le = sky2_next_rx(sky2); 1283 1284 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 1285 le->ctrl = 0; 1286 le->opcode = OP_TCPSTART | HW_OWNER; 1287 1288 sky2_write32(sky2->hw, 1289 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1290 (sky2->netdev->features & NETIF_F_RXCSUM) 1291 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 1292 } 1293 1294 /* Enable/disable receive hash calculation (RSS) */ 1295 static void rx_set_rss(struct net_device *dev, netdev_features_t features) 1296 { 1297 struct sky2_port *sky2 = netdev_priv(dev); 1298 struct sky2_hw *hw = sky2->hw; 1299 int i, nkeys = 4; 1300 1301 /* Supports IPv6 and other modes */ 1302 if (hw->flags & SKY2_HW_NEW_LE) { 1303 nkeys = 10; 1304 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL); 1305 } 1306 1307 /* Program RSS initial values */ 1308 if (features & NETIF_F_RXHASH) { 1309 u32 rss_key[10]; 1310 1311 netdev_rss_key_fill(rss_key, sizeof(rss_key)); 1312 for (i = 0; i < nkeys; i++) 1313 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4), 1314 rss_key[i]); 1315 1316 /* Need to turn on (undocumented) flag to make hashing work */ 1317 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), 1318 RX_STFW_ENA); 1319 1320 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1321 BMU_ENA_RX_RSS_HASH); 1322 } else 1323 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 1324 BMU_DIS_RX_RSS_HASH); 1325 } 1326 1327 /* 1328 * The RX Stop command will not work for Yukon-2 if the BMU does not 1329 * reach the end of packet and since we can't make sure that we have 1330 * incoming data, we must reset the BMU while it is not doing a DMA 1331 * transfer. Since it is possible that the RX path is still active, 1332 * the RX RAM buffer will be stopped first, so any possible incoming 1333 * data will not trigger a DMA. After the RAM buffer is stopped, the 1334 * BMU is polled until any DMA in progress is ended and only then it 1335 * will be reset. 1336 */ 1337 static void sky2_rx_stop(struct sky2_port *sky2) 1338 { 1339 struct sky2_hw *hw = sky2->hw; 1340 unsigned rxq = rxqaddr[sky2->port]; 1341 int i; 1342 1343 /* disable the RAM Buffer receive queue */ 1344 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 1345 1346 for (i = 0; i < 0xffff; i++) 1347 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 1348 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 1349 goto stopped; 1350 1351 netdev_warn(sky2->netdev, "receiver stop failed\n"); 1352 stopped: 1353 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 1354 1355 /* reset the Rx prefetch unit */ 1356 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 1357 mmiowb(); 1358 } 1359 1360 /* Clean out receive buffer area, assumes receiver hardware stopped */ 1361 static void sky2_rx_clean(struct sky2_port *sky2) 1362 { 1363 unsigned i; 1364 1365 if (sky2->rx_le) 1366 memset(sky2->rx_le, 0, RX_LE_BYTES); 1367 1368 for (i = 0; i < sky2->rx_pending; i++) { 1369 struct rx_ring_info *re = sky2->rx_ring + i; 1370 1371 if (re->skb) { 1372 sky2_rx_unmap_skb(sky2->hw->pdev, re); 1373 kfree_skb(re->skb); 1374 re->skb = NULL; 1375 } 1376 } 1377 } 1378 1379 /* Basic MII support */ 1380 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1381 { 1382 struct mii_ioctl_data *data = if_mii(ifr); 1383 struct sky2_port *sky2 = netdev_priv(dev); 1384 struct sky2_hw *hw = sky2->hw; 1385 int err = -EOPNOTSUPP; 1386 1387 if (!netif_running(dev)) 1388 return -ENODEV; /* Phy still in reset */ 1389 1390 switch (cmd) { 1391 case SIOCGMIIPHY: 1392 data->phy_id = PHY_ADDR_MARV; 1393 1394 /* fallthru */ 1395 case SIOCGMIIREG: { 1396 u16 val = 0; 1397 1398 spin_lock_bh(&sky2->phy_lock); 1399 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); 1400 spin_unlock_bh(&sky2->phy_lock); 1401 1402 data->val_out = val; 1403 break; 1404 } 1405 1406 case SIOCSMIIREG: 1407 spin_lock_bh(&sky2->phy_lock); 1408 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, 1409 data->val_in); 1410 spin_unlock_bh(&sky2->phy_lock); 1411 break; 1412 } 1413 return err; 1414 } 1415 1416 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO) 1417 1418 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features) 1419 { 1420 struct sky2_port *sky2 = netdev_priv(dev); 1421 struct sky2_hw *hw = sky2->hw; 1422 u16 port = sky2->port; 1423 1424 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1425 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1426 RX_VLAN_STRIP_ON); 1427 else 1428 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), 1429 RX_VLAN_STRIP_OFF); 1430 1431 if (features & NETIF_F_HW_VLAN_CTAG_TX) { 1432 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1433 TX_VLAN_TAG_ON); 1434 1435 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 1436 } else { 1437 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 1438 TX_VLAN_TAG_OFF); 1439 1440 /* Can't do transmit offload of vlan without hw vlan */ 1441 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS; 1442 } 1443 } 1444 1445 /* Amount of required worst case padding in rx buffer */ 1446 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw) 1447 { 1448 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2; 1449 } 1450 1451 /* 1452 * Allocate an skb for receiving. If the MTU is large enough 1453 * make the skb non-linear with a fragment list of pages. 1454 */ 1455 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp) 1456 { 1457 struct sk_buff *skb; 1458 int i; 1459 1460 skb = __netdev_alloc_skb(sky2->netdev, 1461 sky2->rx_data_size + sky2_rx_pad(sky2->hw), 1462 gfp); 1463 if (!skb) 1464 goto nomem; 1465 1466 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) { 1467 unsigned char *start; 1468 /* 1469 * Workaround for a bug in FIFO that cause hang 1470 * if the FIFO if the receive buffer is not 64 byte aligned. 1471 * The buffer returned from netdev_alloc_skb is 1472 * aligned except if slab debugging is enabled. 1473 */ 1474 start = PTR_ALIGN(skb->data, 8); 1475 skb_reserve(skb, start - skb->data); 1476 } else 1477 skb_reserve(skb, NET_IP_ALIGN); 1478 1479 for (i = 0; i < sky2->rx_nfrags; i++) { 1480 struct page *page = alloc_page(gfp); 1481 1482 if (!page) 1483 goto free_partial; 1484 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE); 1485 } 1486 1487 return skb; 1488 free_partial: 1489 kfree_skb(skb); 1490 nomem: 1491 return NULL; 1492 } 1493 1494 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq) 1495 { 1496 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 1497 } 1498 1499 static int sky2_alloc_rx_skbs(struct sky2_port *sky2) 1500 { 1501 struct sky2_hw *hw = sky2->hw; 1502 unsigned i; 1503 1504 sky2->rx_data_size = sky2_get_rx_data_size(sky2); 1505 1506 /* Fill Rx ring */ 1507 for (i = 0; i < sky2->rx_pending; i++) { 1508 struct rx_ring_info *re = sky2->rx_ring + i; 1509 1510 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL); 1511 if (!re->skb) 1512 return -ENOMEM; 1513 1514 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) { 1515 dev_kfree_skb(re->skb); 1516 re->skb = NULL; 1517 return -ENOMEM; 1518 } 1519 } 1520 return 0; 1521 } 1522 1523 /* 1524 * Setup receiver buffer pool. 1525 * Normal case this ends up creating one list element for skb 1526 * in the receive ring. Worst case if using large MTU and each 1527 * allocation falls on a different 64 bit region, that results 1528 * in 6 list elements per ring entry. 1529 * One element is used for checksum enable/disable, and one 1530 * extra to avoid wrap. 1531 */ 1532 static void sky2_rx_start(struct sky2_port *sky2) 1533 { 1534 struct sky2_hw *hw = sky2->hw; 1535 struct rx_ring_info *re; 1536 unsigned rxq = rxqaddr[sky2->port]; 1537 unsigned i, thresh; 1538 1539 sky2->rx_put = sky2->rx_next = 0; 1540 sky2_qset(hw, rxq); 1541 1542 /* On PCI express lowering the watermark gives better performance */ 1543 if (pci_is_pcie(hw->pdev)) 1544 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 1545 1546 /* These chips have no ram buffer? 1547 * MAC Rx RAM Read is controlled by hardware */ 1548 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1549 hw->chip_rev > CHIP_REV_YU_EC_U_A0) 1550 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 1551 1552 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 1553 1554 if (!(hw->flags & SKY2_HW_NEW_LE)) 1555 rx_set_checksum(sky2); 1556 1557 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 1558 rx_set_rss(sky2->netdev, sky2->netdev->features); 1559 1560 /* submit Rx ring */ 1561 for (i = 0; i < sky2->rx_pending; i++) { 1562 re = sky2->rx_ring + i; 1563 sky2_rx_submit(sky2, re); 1564 } 1565 1566 /* 1567 * The receiver hangs if it receives frames larger than the 1568 * packet buffer. As a workaround, truncate oversize frames, but 1569 * the register is limited to 9 bits, so if you do frames > 2052 1570 * you better get the MTU right! 1571 */ 1572 thresh = sky2_get_rx_threshold(sky2); 1573 if (thresh > 0x1ff) 1574 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 1575 else { 1576 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 1578 } 1579 1580 /* Tell chip about available buffers */ 1581 sky2_rx_update(sky2, rxq); 1582 1583 if (hw->chip_id == CHIP_ID_YUKON_EX || 1584 hw->chip_id == CHIP_ID_YUKON_SUPR) { 1585 /* 1586 * Disable flushing of non ASF packets; 1587 * must be done after initializing the BMUs; 1588 * drivers without ASF support should do this too, otherwise 1589 * it may happen that they cannot run on ASF devices; 1590 * remember that the MAC FIFO isn't reset during initialization. 1591 */ 1592 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF); 1593 } 1594 1595 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) { 1596 /* Enable RX Home Address & Routing Header checksum fix */ 1597 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL), 1598 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA); 1599 1600 /* Enable TX Home Address & Routing Header checksum fix */ 1601 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST), 1602 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN); 1603 } 1604 } 1605 1606 static int sky2_alloc_buffers(struct sky2_port *sky2) 1607 { 1608 struct sky2_hw *hw = sky2->hw; 1609 1610 /* must be power of 2 */ 1611 sky2->tx_le = pci_alloc_consistent(hw->pdev, 1612 sky2->tx_ring_size * 1613 sizeof(struct sky2_tx_le), 1614 &sky2->tx_le_map); 1615 if (!sky2->tx_le) 1616 goto nomem; 1617 1618 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info), 1619 GFP_KERNEL); 1620 if (!sky2->tx_ring) 1621 goto nomem; 1622 1623 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES, 1624 &sky2->rx_le_map); 1625 if (!sky2->rx_le) 1626 goto nomem; 1627 1628 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info), 1629 GFP_KERNEL); 1630 if (!sky2->rx_ring) 1631 goto nomem; 1632 1633 return sky2_alloc_rx_skbs(sky2); 1634 nomem: 1635 return -ENOMEM; 1636 } 1637 1638 static void sky2_free_buffers(struct sky2_port *sky2) 1639 { 1640 struct sky2_hw *hw = sky2->hw; 1641 1642 sky2_rx_clean(sky2); 1643 1644 if (sky2->rx_le) { 1645 pci_free_consistent(hw->pdev, RX_LE_BYTES, 1646 sky2->rx_le, sky2->rx_le_map); 1647 sky2->rx_le = NULL; 1648 } 1649 if (sky2->tx_le) { 1650 pci_free_consistent(hw->pdev, 1651 sky2->tx_ring_size * sizeof(struct sky2_tx_le), 1652 sky2->tx_le, sky2->tx_le_map); 1653 sky2->tx_le = NULL; 1654 } 1655 kfree(sky2->tx_ring); 1656 kfree(sky2->rx_ring); 1657 1658 sky2->tx_ring = NULL; 1659 sky2->rx_ring = NULL; 1660 } 1661 1662 static void sky2_hw_up(struct sky2_port *sky2) 1663 { 1664 struct sky2_hw *hw = sky2->hw; 1665 unsigned port = sky2->port; 1666 u32 ramsize; 1667 int cap; 1668 struct net_device *otherdev = hw->dev[sky2->port^1]; 1669 1670 tx_init(sky2); 1671 1672 /* 1673 * On dual port PCI-X card, there is an problem where status 1674 * can be received out of order due to split transactions 1675 */ 1676 if (otherdev && netif_running(otherdev) && 1677 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { 1678 u16 cmd; 1679 1680 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); 1681 cmd &= ~PCI_X_CMD_MAX_SPLIT; 1682 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); 1683 } 1684 1685 sky2_mac_init(hw, port); 1686 1687 /* Register is number of 4K blocks on internal RAM buffer. */ 1688 ramsize = sky2_read8(hw, B2_E_0) * 4; 1689 if (ramsize > 0) { 1690 u32 rxspace; 1691 1692 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize); 1693 if (ramsize < 16) 1694 rxspace = ramsize / 2; 1695 else 1696 rxspace = 8 + (2*(ramsize - 16))/3; 1697 1698 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 1699 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 1700 1701 /* Make sure SyncQ is disabled */ 1702 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 1703 RB_RST_SET); 1704 } 1705 1706 sky2_qset(hw, txqaddr[port]); 1707 1708 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 1709 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 1710 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 1711 1712 /* Set almost empty threshold */ 1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 1714 hw->chip_rev == CHIP_REV_YU_EC_U_A0) 1715 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 1716 1717 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 1718 sky2->tx_ring_size - 1); 1719 1720 sky2_vlan_mode(sky2->netdev, sky2->netdev->features); 1721 netdev_update_features(sky2->netdev); 1722 1723 sky2_rx_start(sky2); 1724 } 1725 1726 /* Setup device IRQ and enable napi to process */ 1727 static int sky2_setup_irq(struct sky2_hw *hw, const char *name) 1728 { 1729 struct pci_dev *pdev = hw->pdev; 1730 int err; 1731 1732 err = request_irq(pdev->irq, sky2_intr, 1733 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED, 1734 name, hw); 1735 if (err) 1736 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 1737 else { 1738 hw->flags |= SKY2_HW_IRQ_SETUP; 1739 1740 napi_enable(&hw->napi); 1741 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 1742 sky2_read32(hw, B0_IMSK); 1743 } 1744 1745 return err; 1746 } 1747 1748 1749 /* Bring up network interface. */ 1750 static int sky2_open(struct net_device *dev) 1751 { 1752 struct sky2_port *sky2 = netdev_priv(dev); 1753 struct sky2_hw *hw = sky2->hw; 1754 unsigned port = sky2->port; 1755 u32 imask; 1756 int err; 1757 1758 netif_carrier_off(dev); 1759 1760 err = sky2_alloc_buffers(sky2); 1761 if (err) 1762 goto err_out; 1763 1764 /* With single port, IRQ is setup when device is brought up */ 1765 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name))) 1766 goto err_out; 1767 1768 sky2_hw_up(sky2); 1769 1770 /* Enable interrupts from phy/mac for port */ 1771 imask = sky2_read32(hw, B0_IMSK); 1772 1773 if (hw->chip_id == CHIP_ID_YUKON_OPT || 1774 hw->chip_id == CHIP_ID_YUKON_PRM || 1775 hw->chip_id == CHIP_ID_YUKON_OP_2) 1776 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */ 1777 1778 imask |= portirq_msk[port]; 1779 sky2_write32(hw, B0_IMSK, imask); 1780 sky2_read32(hw, B0_IMSK); 1781 1782 netif_info(sky2, ifup, dev, "enabling interface\n"); 1783 1784 return 0; 1785 1786 err_out: 1787 sky2_free_buffers(sky2); 1788 return err; 1789 } 1790 1791 /* Modular subtraction in ring */ 1792 static inline int tx_inuse(const struct sky2_port *sky2) 1793 { 1794 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1); 1795 } 1796 1797 /* Number of list elements available for next tx */ 1798 static inline int tx_avail(const struct sky2_port *sky2) 1799 { 1800 return sky2->tx_pending - tx_inuse(sky2); 1801 } 1802 1803 /* Estimate of number of transmit list elements required */ 1804 static unsigned tx_le_req(const struct sk_buff *skb) 1805 { 1806 unsigned count; 1807 1808 count = (skb_shinfo(skb)->nr_frags + 1) 1809 * (sizeof(dma_addr_t) / sizeof(u32)); 1810 1811 if (skb_is_gso(skb)) 1812 ++count; 1813 else if (sizeof(dma_addr_t) == sizeof(u32)) 1814 ++count; /* possible vlan */ 1815 1816 if (skb->ip_summed == CHECKSUM_PARTIAL) 1817 ++count; 1818 1819 return count; 1820 } 1821 1822 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) 1823 { 1824 if (re->flags & TX_MAP_SINGLE) 1825 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr), 1826 dma_unmap_len(re, maplen), 1827 PCI_DMA_TODEVICE); 1828 else if (re->flags & TX_MAP_PAGE) 1829 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr), 1830 dma_unmap_len(re, maplen), 1831 PCI_DMA_TODEVICE); 1832 re->flags = 0; 1833 } 1834 1835 /* 1836 * Put one packet in ring for transmit. 1837 * A single packet can generate multiple list elements, and 1838 * the number of ring elements will probably be less than the number 1839 * of list elements used. 1840 */ 1841 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, 1842 struct net_device *dev) 1843 { 1844 struct sky2_port *sky2 = netdev_priv(dev); 1845 struct sky2_hw *hw = sky2->hw; 1846 struct sky2_tx_le *le = NULL; 1847 struct tx_ring_info *re; 1848 unsigned i, len; 1849 dma_addr_t mapping; 1850 u32 upper; 1851 u16 slot; 1852 u16 mss; 1853 u8 ctrl; 1854 1855 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) 1856 return NETDEV_TX_BUSY; 1857 1858 len = skb_headlen(skb); 1859 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); 1860 1861 if (pci_dma_mapping_error(hw->pdev, mapping)) 1862 goto mapping_error; 1863 1864 slot = sky2->tx_prod; 1865 netif_printk(sky2, tx_queued, KERN_DEBUG, dev, 1866 "tx queued, slot %u, len %d\n", slot, skb->len); 1867 1868 /* Send high bits if needed */ 1869 upper = upper_32_bits(mapping); 1870 if (upper != sky2->tx_last_upper) { 1871 le = get_tx_le(sky2, &slot); 1872 le->addr = cpu_to_le32(upper); 1873 sky2->tx_last_upper = upper; 1874 le->opcode = OP_ADDR64 | HW_OWNER; 1875 } 1876 1877 /* Check for TCP Segmentation Offload */ 1878 mss = skb_shinfo(skb)->gso_size; 1879 if (mss != 0) { 1880 1881 if (!(hw->flags & SKY2_HW_NEW_LE)) 1882 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb); 1883 1884 if (mss != sky2->tx_last_mss) { 1885 le = get_tx_le(sky2, &slot); 1886 le->addr = cpu_to_le32(mss); 1887 1888 if (hw->flags & SKY2_HW_NEW_LE) 1889 le->opcode = OP_MSS | HW_OWNER; 1890 else 1891 le->opcode = OP_LRGLEN | HW_OWNER; 1892 sky2->tx_last_mss = mss; 1893 } 1894 } 1895 1896 ctrl = 0; 1897 1898 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ 1899 if (skb_vlan_tag_present(skb)) { 1900 if (!le) { 1901 le = get_tx_le(sky2, &slot); 1902 le->addr = 0; 1903 le->opcode = OP_VLAN|HW_OWNER; 1904 } else 1905 le->opcode |= OP_VLAN; 1906 le->length = cpu_to_be16(skb_vlan_tag_get(skb)); 1907 ctrl |= INS_VLAN; 1908 } 1909 1910 /* Handle TCP checksum offload */ 1911 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1912 /* On Yukon EX (some versions) encoding change. */ 1913 if (hw->flags & SKY2_HW_AUTO_TX_SUM) 1914 ctrl |= CALSUM; /* auto checksum */ 1915 else { 1916 const unsigned offset = skb_transport_offset(skb); 1917 u32 tcpsum; 1918 1919 tcpsum = offset << 16; /* sum start */ 1920 tcpsum |= offset + skb->csum_offset; /* sum write */ 1921 1922 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 1923 if (ip_hdr(skb)->protocol == IPPROTO_UDP) 1924 ctrl |= UDPTCP; 1925 1926 if (tcpsum != sky2->tx_tcpsum) { 1927 sky2->tx_tcpsum = tcpsum; 1928 1929 le = get_tx_le(sky2, &slot); 1930 le->addr = cpu_to_le32(tcpsum); 1931 le->length = 0; /* initial checksum value */ 1932 le->ctrl = 1; /* one packet */ 1933 le->opcode = OP_TCPLISW | HW_OWNER; 1934 } 1935 } 1936 } 1937 1938 re = sky2->tx_ring + slot; 1939 re->flags = TX_MAP_SINGLE; 1940 dma_unmap_addr_set(re, mapaddr, mapping); 1941 dma_unmap_len_set(re, maplen, len); 1942 1943 le = get_tx_le(sky2, &slot); 1944 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1945 le->length = cpu_to_le16(len); 1946 le->ctrl = ctrl; 1947 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); 1948 1949 1950 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1951 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1952 1953 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 1954 skb_frag_size(frag), DMA_TO_DEVICE); 1955 1956 if (dma_mapping_error(&hw->pdev->dev, mapping)) 1957 goto mapping_unwind; 1958 1959 upper = upper_32_bits(mapping); 1960 if (upper != sky2->tx_last_upper) { 1961 le = get_tx_le(sky2, &slot); 1962 le->addr = cpu_to_le32(upper); 1963 sky2->tx_last_upper = upper; 1964 le->opcode = OP_ADDR64 | HW_OWNER; 1965 } 1966 1967 re = sky2->tx_ring + slot; 1968 re->flags = TX_MAP_PAGE; 1969 dma_unmap_addr_set(re, mapaddr, mapping); 1970 dma_unmap_len_set(re, maplen, skb_frag_size(frag)); 1971 1972 le = get_tx_le(sky2, &slot); 1973 le->addr = cpu_to_le32(lower_32_bits(mapping)); 1974 le->length = cpu_to_le16(skb_frag_size(frag)); 1975 le->ctrl = ctrl; 1976 le->opcode = OP_BUFFER | HW_OWNER; 1977 } 1978 1979 re->skb = skb; 1980 le->ctrl |= EOP; 1981 1982 sky2->tx_prod = slot; 1983 1984 if (tx_avail(sky2) <= MAX_SKB_TX_LE) 1985 netif_stop_queue(dev); 1986 1987 netdev_sent_queue(dev, skb->len); 1988 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 1989 1990 return NETDEV_TX_OK; 1991 1992 mapping_unwind: 1993 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) { 1994 re = sky2->tx_ring + i; 1995 1996 sky2_tx_unmap(hw->pdev, re); 1997 } 1998 1999 mapping_error: 2000 if (net_ratelimit()) 2001 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2002 dev_kfree_skb_any(skb); 2003 return NETDEV_TX_OK; 2004 } 2005 2006 /* 2007 * Free ring elements from starting at tx_cons until "done" 2008 * 2009 * NB: 2010 * 1. The hardware will tell us about partial completion of multi-part 2011 * buffers so make sure not to free skb to early. 2012 * 2. This may run in parallel start_xmit because the it only 2013 * looks at the tail of the queue of FIFO (tx_cons), not 2014 * the head (tx_prod) 2015 */ 2016 static void sky2_tx_complete(struct sky2_port *sky2, u16 done) 2017 { 2018 struct net_device *dev = sky2->netdev; 2019 u16 idx; 2020 unsigned int bytes_compl = 0, pkts_compl = 0; 2021 2022 BUG_ON(done >= sky2->tx_ring_size); 2023 2024 for (idx = sky2->tx_cons; idx != done; 2025 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 2026 struct tx_ring_info *re = sky2->tx_ring + idx; 2027 struct sk_buff *skb = re->skb; 2028 2029 sky2_tx_unmap(sky2->hw->pdev, re); 2030 2031 if (skb) { 2032 netif_printk(sky2, tx_done, KERN_DEBUG, dev, 2033 "tx done %u\n", idx); 2034 2035 pkts_compl++; 2036 bytes_compl += skb->len; 2037 2038 re->skb = NULL; 2039 dev_kfree_skb_any(skb); 2040 2041 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); 2042 } 2043 } 2044 2045 sky2->tx_cons = idx; 2046 smp_mb(); 2047 2048 netdev_completed_queue(dev, pkts_compl, bytes_compl); 2049 2050 u64_stats_update_begin(&sky2->tx_stats.syncp); 2051 sky2->tx_stats.packets += pkts_compl; 2052 sky2->tx_stats.bytes += bytes_compl; 2053 u64_stats_update_end(&sky2->tx_stats.syncp); 2054 } 2055 2056 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port) 2057 { 2058 /* Disable Force Sync bit and Enable Alloc bit */ 2059 sky2_write8(hw, SK_REG(port, TXA_CTRL), 2060 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2061 2062 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2063 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2064 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2065 2066 /* Reset the PCI FIFO of the async Tx queue */ 2067 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 2068 BMU_RST_SET | BMU_FIFO_RST); 2069 2070 /* Reset the Tx prefetch units */ 2071 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 2072 PREF_UNIT_RST_SET); 2073 2074 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2075 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2076 2077 sky2_read32(hw, B0_CTST); 2078 } 2079 2080 static void sky2_hw_down(struct sky2_port *sky2) 2081 { 2082 struct sky2_hw *hw = sky2->hw; 2083 unsigned port = sky2->port; 2084 u16 ctrl; 2085 2086 /* Force flow control off */ 2087 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2088 2089 /* Stop transmitter */ 2090 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 2091 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 2092 2093 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2094 RB_RST_SET | RB_DIS_OP_MD); 2095 2096 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2097 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 2098 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2099 2100 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2101 2102 /* Workaround shared GMAC reset */ 2103 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && 2104 port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) 2105 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2106 2107 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2108 2109 /* Force any delayed status interrupt and NAPI */ 2110 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0); 2111 sky2_write32(hw, STAT_TX_TIMER_CNT, 0); 2112 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0); 2113 sky2_read8(hw, STAT_ISR_TIMER_CTRL); 2114 2115 sky2_rx_stop(sky2); 2116 2117 spin_lock_bh(&sky2->phy_lock); 2118 sky2_phy_power_down(hw, port); 2119 spin_unlock_bh(&sky2->phy_lock); 2120 2121 sky2_tx_reset(hw, port); 2122 2123 /* Free any pending frames stuck in HW queue */ 2124 sky2_tx_complete(sky2, sky2->tx_prod); 2125 } 2126 2127 /* Network shutdown */ 2128 static int sky2_close(struct net_device *dev) 2129 { 2130 struct sky2_port *sky2 = netdev_priv(dev); 2131 struct sky2_hw *hw = sky2->hw; 2132 2133 /* Never really got started! */ 2134 if (!sky2->tx_le) 2135 return 0; 2136 2137 netif_info(sky2, ifdown, dev, "disabling interface\n"); 2138 2139 if (hw->ports == 1) { 2140 sky2_write32(hw, B0_IMSK, 0); 2141 sky2_read32(hw, B0_IMSK); 2142 2143 napi_disable(&hw->napi); 2144 free_irq(hw->pdev->irq, hw); 2145 hw->flags &= ~SKY2_HW_IRQ_SETUP; 2146 } else { 2147 u32 imask; 2148 2149 /* Disable port IRQ */ 2150 imask = sky2_read32(hw, B0_IMSK); 2151 imask &= ~portirq_msk[sky2->port]; 2152 sky2_write32(hw, B0_IMSK, imask); 2153 sky2_read32(hw, B0_IMSK); 2154 2155 synchronize_irq(hw->pdev->irq); 2156 napi_synchronize(&hw->napi); 2157 } 2158 2159 sky2_hw_down(sky2); 2160 2161 sky2_free_buffers(sky2); 2162 2163 return 0; 2164 } 2165 2166 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) 2167 { 2168 if (hw->flags & SKY2_HW_FIBRE_PHY) 2169 return SPEED_1000; 2170 2171 if (!(hw->flags & SKY2_HW_GIGABIT)) { 2172 if (aux & PHY_M_PS_SPEED_100) 2173 return SPEED_100; 2174 else 2175 return SPEED_10; 2176 } 2177 2178 switch (aux & PHY_M_PS_SPEED_MSK) { 2179 case PHY_M_PS_SPEED_1000: 2180 return SPEED_1000; 2181 case PHY_M_PS_SPEED_100: 2182 return SPEED_100; 2183 default: 2184 return SPEED_10; 2185 } 2186 } 2187 2188 static void sky2_link_up(struct sky2_port *sky2) 2189 { 2190 struct sky2_hw *hw = sky2->hw; 2191 unsigned port = sky2->port; 2192 static const char *fc_name[] = { 2193 [FC_NONE] = "none", 2194 [FC_TX] = "tx", 2195 [FC_RX] = "rx", 2196 [FC_BOTH] = "both", 2197 }; 2198 2199 sky2_set_ipg(sky2); 2200 2201 sky2_enable_rx_tx(sky2); 2202 2203 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 2204 2205 netif_carrier_on(sky2->netdev); 2206 2207 mod_timer(&hw->watchdog_timer, jiffies + 1); 2208 2209 /* Turn on link LED */ 2210 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 2211 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 2212 2213 netif_info(sky2, link, sky2->netdev, 2214 "Link is up at %d Mbps, %s duplex, flow control %s\n", 2215 sky2->speed, 2216 sky2->duplex == DUPLEX_FULL ? "full" : "half", 2217 fc_name[sky2->flow_status]); 2218 } 2219 2220 static void sky2_link_down(struct sky2_port *sky2) 2221 { 2222 struct sky2_hw *hw = sky2->hw; 2223 unsigned port = sky2->port; 2224 u16 reg; 2225 2226 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 2227 2228 reg = gma_read16(hw, port, GM_GP_CTRL); 2229 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2230 gma_write16(hw, port, GM_GP_CTRL, reg); 2231 2232 netif_carrier_off(sky2->netdev); 2233 2234 /* Turn off link LED */ 2235 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 2236 2237 netif_info(sky2, link, sky2->netdev, "Link is down\n"); 2238 2239 sky2_phy_init(hw, port); 2240 } 2241 2242 static enum flow_control sky2_flow(int rx, int tx) 2243 { 2244 if (rx) 2245 return tx ? FC_BOTH : FC_RX; 2246 else 2247 return tx ? FC_TX : FC_NONE; 2248 } 2249 2250 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) 2251 { 2252 struct sky2_hw *hw = sky2->hw; 2253 unsigned port = sky2->port; 2254 u16 advert, lpa; 2255 2256 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2257 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 2258 if (lpa & PHY_M_AN_RF) { 2259 netdev_err(sky2->netdev, "remote fault\n"); 2260 return -1; 2261 } 2262 2263 if (!(aux & PHY_M_PS_SPDUP_RES)) { 2264 netdev_err(sky2->netdev, "speed/duplex mismatch\n"); 2265 return -1; 2266 } 2267 2268 sky2->speed = sky2_phy_speed(hw, aux); 2269 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2270 2271 /* Since the pause result bits seem to in different positions on 2272 * different chips. look at registers. 2273 */ 2274 if (hw->flags & SKY2_HW_FIBRE_PHY) { 2275 /* Shift for bits in fiber PHY */ 2276 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM); 2277 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM); 2278 2279 if (advert & ADVERTISE_1000XPAUSE) 2280 advert |= ADVERTISE_PAUSE_CAP; 2281 if (advert & ADVERTISE_1000XPSE_ASYM) 2282 advert |= ADVERTISE_PAUSE_ASYM; 2283 if (lpa & LPA_1000XPAUSE) 2284 lpa |= LPA_PAUSE_CAP; 2285 if (lpa & LPA_1000XPAUSE_ASYM) 2286 lpa |= LPA_PAUSE_ASYM; 2287 } 2288 2289 sky2->flow_status = FC_NONE; 2290 if (advert & ADVERTISE_PAUSE_CAP) { 2291 if (lpa & LPA_PAUSE_CAP) 2292 sky2->flow_status = FC_BOTH; 2293 else if (advert & ADVERTISE_PAUSE_ASYM) 2294 sky2->flow_status = FC_RX; 2295 } else if (advert & ADVERTISE_PAUSE_ASYM) { 2296 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 2297 sky2->flow_status = FC_TX; 2298 } 2299 2300 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 && 2301 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 2302 sky2->flow_status = FC_NONE; 2303 2304 if (sky2->flow_status & FC_TX) 2305 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2306 else 2307 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2308 2309 return 0; 2310 } 2311 2312 /* Interrupt from PHY */ 2313 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) 2314 { 2315 struct net_device *dev = hw->dev[port]; 2316 struct sky2_port *sky2 = netdev_priv(dev); 2317 u16 istatus, phystat; 2318 2319 if (!netif_running(dev)) 2320 return; 2321 2322 spin_lock(&sky2->phy_lock); 2323 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2324 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2325 2326 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n", 2327 istatus, phystat); 2328 2329 if (istatus & PHY_M_IS_AN_COMPL) { 2330 if (sky2_autoneg_done(sky2, phystat) == 0 && 2331 !netif_carrier_ok(dev)) 2332 sky2_link_up(sky2); 2333 goto out; 2334 } 2335 2336 if (istatus & PHY_M_IS_LSP_CHANGE) 2337 sky2->speed = sky2_phy_speed(hw, phystat); 2338 2339 if (istatus & PHY_M_IS_DUP_CHANGE) 2340 sky2->duplex = 2341 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2342 2343 if (istatus & PHY_M_IS_LST_CHANGE) { 2344 if (phystat & PHY_M_PS_LINK_UP) 2345 sky2_link_up(sky2); 2346 else 2347 sky2_link_down(sky2); 2348 } 2349 out: 2350 spin_unlock(&sky2->phy_lock); 2351 } 2352 2353 /* Special quick link interrupt (Yukon-2 Optima only) */ 2354 static void sky2_qlink_intr(struct sky2_hw *hw) 2355 { 2356 struct sky2_port *sky2 = netdev_priv(hw->dev[0]); 2357 u32 imask; 2358 u16 phy; 2359 2360 /* disable irq */ 2361 imask = sky2_read32(hw, B0_IMSK); 2362 imask &= ~Y2_IS_PHY_QLNK; 2363 sky2_write32(hw, B0_IMSK, imask); 2364 2365 /* reset PHY Link Detect */ 2366 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2367 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2368 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2369 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2370 2371 sky2_link_up(sky2); 2372 } 2373 2374 /* Transmit timeout is only called if we are running, carrier is up 2375 * and tx queue is full (stopped). 2376 */ 2377 static void sky2_tx_timeout(struct net_device *dev) 2378 { 2379 struct sky2_port *sky2 = netdev_priv(dev); 2380 struct sky2_hw *hw = sky2->hw; 2381 2382 netif_err(sky2, timer, dev, "tx timeout\n"); 2383 2384 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n", 2385 sky2->tx_cons, sky2->tx_prod, 2386 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 2387 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE))); 2388 2389 /* can't restart safely under softirq */ 2390 schedule_work(&hw->restart_work); 2391 } 2392 2393 static int sky2_change_mtu(struct net_device *dev, int new_mtu) 2394 { 2395 struct sky2_port *sky2 = netdev_priv(dev); 2396 struct sky2_hw *hw = sky2->hw; 2397 unsigned port = sky2->port; 2398 int err; 2399 u16 ctl, mode; 2400 u32 imask; 2401 2402 if (!netif_running(dev)) { 2403 dev->mtu = new_mtu; 2404 netdev_update_features(dev); 2405 return 0; 2406 } 2407 2408 imask = sky2_read32(hw, B0_IMSK); 2409 sky2_write32(hw, B0_IMSK, 0); 2410 sky2_read32(hw, B0_IMSK); 2411 2412 netif_trans_update(dev); /* prevent tx timeout */ 2413 napi_disable(&hw->napi); 2414 netif_tx_disable(dev); 2415 2416 synchronize_irq(hw->pdev->irq); 2417 2418 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) 2419 sky2_set_tx_stfwd(hw, port); 2420 2421 ctl = gma_read16(hw, port, GM_GP_CTRL); 2422 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); 2423 sky2_rx_stop(sky2); 2424 sky2_rx_clean(sky2); 2425 2426 dev->mtu = new_mtu; 2427 netdev_update_features(dev); 2428 2429 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA; 2430 if (sky2->speed > SPEED_100) 2431 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000); 2432 else 2433 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100); 2434 2435 if (dev->mtu > ETH_DATA_LEN) 2436 mode |= GM_SMOD_JUMBO_ENA; 2437 2438 gma_write16(hw, port, GM_SERIAL_MODE, mode); 2439 2440 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); 2441 2442 err = sky2_alloc_rx_skbs(sky2); 2443 if (!err) 2444 sky2_rx_start(sky2); 2445 else 2446 sky2_rx_clean(sky2); 2447 sky2_write32(hw, B0_IMSK, imask); 2448 2449 sky2_read32(hw, B0_Y2_SP_LISR); 2450 napi_enable(&hw->napi); 2451 2452 if (err) 2453 dev_close(dev); 2454 else { 2455 gma_write16(hw, port, GM_GP_CTRL, ctl); 2456 2457 netif_wake_queue(dev); 2458 } 2459 2460 return err; 2461 } 2462 2463 static inline bool needs_copy(const struct rx_ring_info *re, 2464 unsigned length) 2465 { 2466 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS 2467 /* Some architectures need the IP header to be aligned */ 2468 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32))) 2469 return true; 2470 #endif 2471 return length < copybreak; 2472 } 2473 2474 /* For small just reuse existing skb for next receive */ 2475 static struct sk_buff *receive_copy(struct sky2_port *sky2, 2476 const struct rx_ring_info *re, 2477 unsigned length) 2478 { 2479 struct sk_buff *skb; 2480 2481 skb = netdev_alloc_skb_ip_align(sky2->netdev, length); 2482 if (likely(skb)) { 2483 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr, 2484 length, PCI_DMA_FROMDEVICE); 2485 skb_copy_from_linear_data(re->skb, skb->data, length); 2486 skb->ip_summed = re->skb->ip_summed; 2487 skb->csum = re->skb->csum; 2488 skb_copy_hash(skb, re->skb); 2489 __vlan_hwaccel_copy_tag(skb, re->skb); 2490 2491 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr, 2492 length, PCI_DMA_FROMDEVICE); 2493 __vlan_hwaccel_clear_tag(re->skb); 2494 skb_clear_hash(re->skb); 2495 re->skb->ip_summed = CHECKSUM_NONE; 2496 skb_put(skb, length); 2497 } 2498 return skb; 2499 } 2500 2501 /* Adjust length of skb with fragments to match received data */ 2502 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space, 2503 unsigned int length) 2504 { 2505 int i, num_frags; 2506 unsigned int size; 2507 2508 /* put header into skb */ 2509 size = min(length, hdr_space); 2510 skb->tail += size; 2511 skb->len += size; 2512 length -= size; 2513 2514 num_frags = skb_shinfo(skb)->nr_frags; 2515 for (i = 0; i < num_frags; i++) { 2516 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2517 2518 if (length == 0) { 2519 /* don't need this page */ 2520 __skb_frag_unref(frag); 2521 --skb_shinfo(skb)->nr_frags; 2522 } else { 2523 size = min(length, (unsigned) PAGE_SIZE); 2524 2525 skb_frag_size_set(frag, size); 2526 skb->data_len += size; 2527 skb->truesize += PAGE_SIZE; 2528 skb->len += size; 2529 length -= size; 2530 } 2531 } 2532 } 2533 2534 /* Normal packet - take skb from ring element and put in a new one */ 2535 static struct sk_buff *receive_new(struct sky2_port *sky2, 2536 struct rx_ring_info *re, 2537 unsigned int length) 2538 { 2539 struct sk_buff *skb; 2540 struct rx_ring_info nre; 2541 unsigned hdr_space = sky2->rx_data_size; 2542 2543 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC); 2544 if (unlikely(!nre.skb)) 2545 goto nobuf; 2546 2547 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space)) 2548 goto nomap; 2549 2550 skb = re->skb; 2551 sky2_rx_unmap_skb(sky2->hw->pdev, re); 2552 prefetch(skb->data); 2553 *re = nre; 2554 2555 if (skb_shinfo(skb)->nr_frags) 2556 skb_put_frags(skb, hdr_space, length); 2557 else 2558 skb_put(skb, length); 2559 return skb; 2560 2561 nomap: 2562 dev_kfree_skb(nre.skb); 2563 nobuf: 2564 return NULL; 2565 } 2566 2567 /* 2568 * Receive one packet. 2569 * For larger packets, get new buffer. 2570 */ 2571 static struct sk_buff *sky2_receive(struct net_device *dev, 2572 u16 length, u32 status) 2573 { 2574 struct sky2_port *sky2 = netdev_priv(dev); 2575 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 2576 struct sk_buff *skb = NULL; 2577 u16 count = (status & GMR_FS_LEN) >> 16; 2578 2579 netif_printk(sky2, rx_status, KERN_DEBUG, dev, 2580 "rx slot %u status 0x%x len %d\n", 2581 sky2->rx_next, status, length); 2582 2583 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; 2584 prefetch(sky2->rx_ring + sky2->rx_next); 2585 2586 if (skb_vlan_tag_present(re->skb)) 2587 count -= VLAN_HLEN; /* Account for vlan tag */ 2588 2589 /* This chip has hardware problems that generates bogus status. 2590 * So do only marginal checking and expect higher level protocols 2591 * to handle crap frames. 2592 */ 2593 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 2594 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 2595 length != count) 2596 goto okay; 2597 2598 if (status & GMR_FS_ANY_ERR) 2599 goto error; 2600 2601 if (!(status & GMR_FS_RX_OK)) 2602 goto resubmit; 2603 2604 /* if length reported by DMA does not match PHY, packet was truncated */ 2605 if (length != count) 2606 goto error; 2607 2608 okay: 2609 if (needs_copy(re, length)) 2610 skb = receive_copy(sky2, re, length); 2611 else 2612 skb = receive_new(sky2, re, length); 2613 2614 dev->stats.rx_dropped += (skb == NULL); 2615 2616 resubmit: 2617 sky2_rx_submit(sky2, re); 2618 2619 return skb; 2620 2621 error: 2622 ++dev->stats.rx_errors; 2623 2624 if (net_ratelimit()) 2625 netif_info(sky2, rx_err, dev, 2626 "rx error, status 0x%x length %d\n", status, length); 2627 2628 goto resubmit; 2629 } 2630 2631 /* Transmit complete */ 2632 static inline void sky2_tx_done(struct net_device *dev, u16 last) 2633 { 2634 struct sky2_port *sky2 = netdev_priv(dev); 2635 2636 if (netif_running(dev)) { 2637 sky2_tx_complete(sky2, last); 2638 2639 /* Wake unless it's detached, and called e.g. from sky2_close() */ 2640 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4) 2641 netif_wake_queue(dev); 2642 } 2643 } 2644 2645 static inline void sky2_skb_rx(const struct sky2_port *sky2, 2646 struct sk_buff *skb) 2647 { 2648 if (skb->ip_summed == CHECKSUM_NONE) 2649 netif_receive_skb(skb); 2650 else 2651 napi_gro_receive(&sky2->hw->napi, skb); 2652 } 2653 2654 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port, 2655 unsigned packets, unsigned bytes) 2656 { 2657 struct net_device *dev = hw->dev[port]; 2658 struct sky2_port *sky2 = netdev_priv(dev); 2659 2660 if (packets == 0) 2661 return; 2662 2663 u64_stats_update_begin(&sky2->rx_stats.syncp); 2664 sky2->rx_stats.packets += packets; 2665 sky2->rx_stats.bytes += bytes; 2666 u64_stats_update_end(&sky2->rx_stats.syncp); 2667 2668 sky2->last_rx = jiffies; 2669 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); 2670 } 2671 2672 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status) 2673 { 2674 /* If this happens then driver assuming wrong format for chip type */ 2675 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE); 2676 2677 /* Both checksum counters are programmed to start at 2678 * the same offset, so unless there is a problem they 2679 * should match. This failure is an early indication that 2680 * hardware receive checksumming won't work. 2681 */ 2682 if (likely((u16)(status >> 16) == (u16)status)) { 2683 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb; 2684 skb->ip_summed = CHECKSUM_COMPLETE; 2685 skb->csum = le16_to_cpu(status); 2686 } else { 2687 dev_notice(&sky2->hw->pdev->dev, 2688 "%s: receive checksum problem (status = %#x)\n", 2689 sky2->netdev->name, status); 2690 2691 /* Disable checksum offload 2692 * It will be reenabled on next ndo_set_features, but if it's 2693 * really broken, will get disabled again 2694 */ 2695 sky2->netdev->features &= ~NETIF_F_RXCSUM; 2696 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), 2697 BMU_DIS_RX_CHKSUM); 2698 } 2699 } 2700 2701 static void sky2_rx_tag(struct sky2_port *sky2, u16 length) 2702 { 2703 struct sk_buff *skb; 2704 2705 skb = sky2->rx_ring[sky2->rx_next].skb; 2706 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length)); 2707 } 2708 2709 static void sky2_rx_hash(struct sky2_port *sky2, u32 status) 2710 { 2711 struct sk_buff *skb; 2712 2713 skb = sky2->rx_ring[sky2->rx_next].skb; 2714 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3); 2715 } 2716 2717 /* Process status response ring */ 2718 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx) 2719 { 2720 int work_done = 0; 2721 unsigned int total_bytes[2] = { 0 }; 2722 unsigned int total_packets[2] = { 0 }; 2723 2724 if (to_do <= 0) 2725 return work_done; 2726 2727 rmb(); 2728 do { 2729 struct sky2_port *sky2; 2730 struct sky2_status_le *le = hw->st_le + hw->st_idx; 2731 unsigned port; 2732 struct net_device *dev; 2733 struct sk_buff *skb; 2734 u32 status; 2735 u16 length; 2736 u8 opcode = le->opcode; 2737 2738 if (!(opcode & HW_OWNER)) 2739 break; 2740 2741 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size); 2742 2743 port = le->css & CSS_LINK_BIT; 2744 dev = hw->dev[port]; 2745 sky2 = netdev_priv(dev); 2746 length = le16_to_cpu(le->length); 2747 status = le32_to_cpu(le->status); 2748 2749 le->opcode = 0; 2750 switch (opcode & ~HW_OWNER) { 2751 case OP_RXSTAT: 2752 total_packets[port]++; 2753 total_bytes[port] += length; 2754 2755 skb = sky2_receive(dev, length, status); 2756 if (!skb) 2757 break; 2758 2759 /* This chip reports checksum status differently */ 2760 if (hw->flags & SKY2_HW_NEW_LE) { 2761 if ((dev->features & NETIF_F_RXCSUM) && 2762 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) && 2763 (le->css & CSS_TCPUDPCSOK)) 2764 skb->ip_summed = CHECKSUM_UNNECESSARY; 2765 else 2766 skb->ip_summed = CHECKSUM_NONE; 2767 } 2768 2769 skb->protocol = eth_type_trans(skb, dev); 2770 sky2_skb_rx(sky2, skb); 2771 2772 /* Stop after net poll weight */ 2773 if (++work_done >= to_do) 2774 goto exit_loop; 2775 break; 2776 2777 case OP_RXVLAN: 2778 sky2_rx_tag(sky2, length); 2779 break; 2780 2781 case OP_RXCHKSVLAN: 2782 sky2_rx_tag(sky2, length); 2783 /* fall through */ 2784 case OP_RXCHKS: 2785 if (likely(dev->features & NETIF_F_RXCSUM)) 2786 sky2_rx_checksum(sky2, status); 2787 break; 2788 2789 case OP_RSS_HASH: 2790 sky2_rx_hash(sky2, status); 2791 break; 2792 2793 case OP_TXINDEXLE: 2794 /* TX index reports status for both ports */ 2795 sky2_tx_done(hw->dev[0], status & 0xfff); 2796 if (hw->dev[1]) 2797 sky2_tx_done(hw->dev[1], 2798 ((status >> 24) & 0xff) 2799 | (u16)(length & 0xf) << 8); 2800 break; 2801 2802 default: 2803 if (net_ratelimit()) 2804 pr_warn("unknown status opcode 0x%x\n", opcode); 2805 } 2806 } while (hw->st_idx != idx); 2807 2808 /* Fully processed status ring so clear irq */ 2809 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 2810 2811 exit_loop: 2812 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]); 2813 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]); 2814 2815 return work_done; 2816 } 2817 2818 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) 2819 { 2820 struct net_device *dev = hw->dev[port]; 2821 2822 if (net_ratelimit()) 2823 netdev_info(dev, "hw error interrupt status 0x%x\n", status); 2824 2825 if (status & Y2_IS_PAR_RD1) { 2826 if (net_ratelimit()) 2827 netdev_err(dev, "ram data read parity error\n"); 2828 /* Clear IRQ */ 2829 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 2830 } 2831 2832 if (status & Y2_IS_PAR_WR1) { 2833 if (net_ratelimit()) 2834 netdev_err(dev, "ram data write parity error\n"); 2835 2836 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 2837 } 2838 2839 if (status & Y2_IS_PAR_MAC1) { 2840 if (net_ratelimit()) 2841 netdev_err(dev, "MAC parity error\n"); 2842 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 2843 } 2844 2845 if (status & Y2_IS_PAR_RX1) { 2846 if (net_ratelimit()) 2847 netdev_err(dev, "RX parity error\n"); 2848 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 2849 } 2850 2851 if (status & Y2_IS_TCP_TXA1) { 2852 if (net_ratelimit()) 2853 netdev_err(dev, "TCP segmentation error\n"); 2854 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 2855 } 2856 } 2857 2858 static void sky2_hw_intr(struct sky2_hw *hw) 2859 { 2860 struct pci_dev *pdev = hw->pdev; 2861 u32 status = sky2_read32(hw, B0_HWE_ISRC); 2862 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 2863 2864 status &= hwmsk; 2865 2866 if (status & Y2_IS_TIST_OV) 2867 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2868 2869 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 2870 u16 pci_err; 2871 2872 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2873 pci_err = sky2_pci_read16(hw, PCI_STATUS); 2874 if (net_ratelimit()) 2875 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", 2876 pci_err); 2877 2878 sky2_pci_write16(hw, PCI_STATUS, 2879 pci_err | PCI_STATUS_ERROR_BITS); 2880 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2881 } 2882 2883 if (status & Y2_IS_PCI_EXP) { 2884 /* PCI-Express uncorrectable Error occurred */ 2885 u32 err; 2886 2887 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2888 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2889 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 2890 0xfffffffful); 2891 if (net_ratelimit()) 2892 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err); 2893 2894 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 2895 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2896 } 2897 2898 if (status & Y2_HWE_L1_MASK) 2899 sky2_hw_error(hw, 0, status); 2900 status >>= 8; 2901 if (status & Y2_HWE_L1_MASK) 2902 sky2_hw_error(hw, 1, status); 2903 } 2904 2905 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) 2906 { 2907 struct net_device *dev = hw->dev[port]; 2908 struct sky2_port *sky2 = netdev_priv(dev); 2909 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2910 2911 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status); 2912 2913 if (status & GM_IS_RX_CO_OV) 2914 gma_read16(hw, port, GM_RX_IRQ_SRC); 2915 2916 if (status & GM_IS_TX_CO_OV) 2917 gma_read16(hw, port, GM_TX_IRQ_SRC); 2918 2919 if (status & GM_IS_RX_FF_OR) { 2920 ++dev->stats.rx_fifo_errors; 2921 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2922 } 2923 2924 if (status & GM_IS_TX_FF_UR) { 2925 ++dev->stats.tx_fifo_errors; 2926 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2927 } 2928 } 2929 2930 /* This should never happen it is a bug. */ 2931 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q) 2932 { 2933 struct net_device *dev = hw->dev[port]; 2934 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 2935 2936 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n", 2937 dev->name, (unsigned) q, (unsigned) idx, 2938 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX))); 2939 2940 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 2941 } 2942 2943 static int sky2_rx_hung(struct net_device *dev) 2944 { 2945 struct sky2_port *sky2 = netdev_priv(dev); 2946 struct sky2_hw *hw = sky2->hw; 2947 unsigned port = sky2->port; 2948 unsigned rxq = rxqaddr[port]; 2949 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP)); 2950 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV)); 2951 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP)); 2952 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL)); 2953 2954 /* If idle and MAC or PCI is stuck */ 2955 if (sky2->check.last == sky2->last_rx && 2956 ((mac_rp == sky2->check.mac_rp && 2957 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) || 2958 /* Check if the PCI RX hang */ 2959 (fifo_rp == sky2->check.fifo_rp && 2960 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) { 2961 netdev_printk(KERN_DEBUG, dev, 2962 "hung mac %d:%d fifo %d (%d:%d)\n", 2963 mac_lev, mac_rp, fifo_lev, 2964 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP))); 2965 return 1; 2966 } else { 2967 sky2->check.last = sky2->last_rx; 2968 sky2->check.mac_rp = mac_rp; 2969 sky2->check.mac_lev = mac_lev; 2970 sky2->check.fifo_rp = fifo_rp; 2971 sky2->check.fifo_lev = fifo_lev; 2972 return 0; 2973 } 2974 } 2975 2976 static void sky2_watchdog(struct timer_list *t) 2977 { 2978 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer); 2979 2980 /* Check for lost IRQ once a second */ 2981 if (sky2_read32(hw, B0_ISRC)) { 2982 napi_schedule(&hw->napi); 2983 } else { 2984 int i, active = 0; 2985 2986 for (i = 0; i < hw->ports; i++) { 2987 struct net_device *dev = hw->dev[i]; 2988 if (!netif_running(dev)) 2989 continue; 2990 ++active; 2991 2992 /* For chips with Rx FIFO, check if stuck */ 2993 if ((hw->flags & SKY2_HW_RAM_BUFFER) && 2994 sky2_rx_hung(dev)) { 2995 netdev_info(dev, "receiver hang detected\n"); 2996 schedule_work(&hw->restart_work); 2997 return; 2998 } 2999 } 3000 3001 if (active == 0) 3002 return; 3003 } 3004 3005 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ)); 3006 } 3007 3008 /* Hardware/software error handling */ 3009 static void sky2_err_intr(struct sky2_hw *hw, u32 status) 3010 { 3011 if (net_ratelimit()) 3012 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status); 3013 3014 if (status & Y2_IS_HW_ERR) 3015 sky2_hw_intr(hw); 3016 3017 if (status & Y2_IS_IRQ_MAC1) 3018 sky2_mac_intr(hw, 0); 3019 3020 if (status & Y2_IS_IRQ_MAC2) 3021 sky2_mac_intr(hw, 1); 3022 3023 if (status & Y2_IS_CHK_RX1) 3024 sky2_le_error(hw, 0, Q_R1); 3025 3026 if (status & Y2_IS_CHK_RX2) 3027 sky2_le_error(hw, 1, Q_R2); 3028 3029 if (status & Y2_IS_CHK_TXA1) 3030 sky2_le_error(hw, 0, Q_XA1); 3031 3032 if (status & Y2_IS_CHK_TXA2) 3033 sky2_le_error(hw, 1, Q_XA2); 3034 } 3035 3036 static int sky2_poll(struct napi_struct *napi, int work_limit) 3037 { 3038 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi); 3039 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 3040 int work_done = 0; 3041 u16 idx; 3042 3043 if (unlikely(status & Y2_IS_ERROR)) 3044 sky2_err_intr(hw, status); 3045 3046 if (status & Y2_IS_IRQ_PHY1) 3047 sky2_phy_intr(hw, 0); 3048 3049 if (status & Y2_IS_IRQ_PHY2) 3050 sky2_phy_intr(hw, 1); 3051 3052 if (status & Y2_IS_PHY_QLNK) 3053 sky2_qlink_intr(hw); 3054 3055 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 3056 work_done += sky2_status_intr(hw, work_limit - work_done, idx); 3057 3058 if (work_done >= work_limit) 3059 goto done; 3060 } 3061 3062 napi_complete_done(napi, work_done); 3063 sky2_read32(hw, B0_Y2_SP_LISR); 3064 done: 3065 3066 return work_done; 3067 } 3068 3069 static irqreturn_t sky2_intr(int irq, void *dev_id) 3070 { 3071 struct sky2_hw *hw = dev_id; 3072 u32 status; 3073 3074 /* Reading this mask interrupts as side effect */ 3075 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 3076 if (status == 0 || status == ~0) { 3077 sky2_write32(hw, B0_Y2_SP_ICR, 2); 3078 return IRQ_NONE; 3079 } 3080 3081 prefetch(&hw->st_le[hw->st_idx]); 3082 3083 napi_schedule(&hw->napi); 3084 3085 return IRQ_HANDLED; 3086 } 3087 3088 #ifdef CONFIG_NET_POLL_CONTROLLER 3089 static void sky2_netpoll(struct net_device *dev) 3090 { 3091 struct sky2_port *sky2 = netdev_priv(dev); 3092 3093 napi_schedule(&sky2->hw->napi); 3094 } 3095 #endif 3096 3097 /* Chip internal frequency for clock calculations */ 3098 static u32 sky2_mhz(const struct sky2_hw *hw) 3099 { 3100 switch (hw->chip_id) { 3101 case CHIP_ID_YUKON_EC: 3102 case CHIP_ID_YUKON_EC_U: 3103 case CHIP_ID_YUKON_EX: 3104 case CHIP_ID_YUKON_SUPR: 3105 case CHIP_ID_YUKON_UL_2: 3106 case CHIP_ID_YUKON_OPT: 3107 case CHIP_ID_YUKON_PRM: 3108 case CHIP_ID_YUKON_OP_2: 3109 return 125; 3110 3111 case CHIP_ID_YUKON_FE: 3112 return 100; 3113 3114 case CHIP_ID_YUKON_FE_P: 3115 return 50; 3116 3117 case CHIP_ID_YUKON_XL: 3118 return 156; 3119 3120 default: 3121 BUG(); 3122 } 3123 } 3124 3125 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) 3126 { 3127 return sky2_mhz(hw) * us; 3128 } 3129 3130 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) 3131 { 3132 return clk / sky2_mhz(hw); 3133 } 3134 3135 3136 static int sky2_init(struct sky2_hw *hw) 3137 { 3138 u8 t8; 3139 3140 /* Enable all clocks and check for bad PCI access */ 3141 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 3142 3143 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3144 3145 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 3146 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 3147 3148 switch (hw->chip_id) { 3149 case CHIP_ID_YUKON_XL: 3150 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 3151 if (hw->chip_rev < CHIP_REV_YU_XL_A2) 3152 hw->flags |= SKY2_HW_RSS_BROKEN; 3153 break; 3154 3155 case CHIP_ID_YUKON_EC_U: 3156 hw->flags = SKY2_HW_GIGABIT 3157 | SKY2_HW_NEWER_PHY 3158 | SKY2_HW_ADV_POWER_CTL; 3159 break; 3160 3161 case CHIP_ID_YUKON_EX: 3162 hw->flags = SKY2_HW_GIGABIT 3163 | SKY2_HW_NEWER_PHY 3164 | SKY2_HW_NEW_LE 3165 | SKY2_HW_ADV_POWER_CTL 3166 | SKY2_HW_RSS_CHKSUM; 3167 3168 /* New transmit checksum */ 3169 if (hw->chip_rev != CHIP_REV_YU_EX_B0) 3170 hw->flags |= SKY2_HW_AUTO_TX_SUM; 3171 break; 3172 3173 case CHIP_ID_YUKON_EC: 3174 /* This rev is really old, and requires untested workarounds */ 3175 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 3176 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n"); 3177 return -EOPNOTSUPP; 3178 } 3179 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN; 3180 break; 3181 3182 case CHIP_ID_YUKON_FE: 3183 hw->flags = SKY2_HW_RSS_BROKEN; 3184 break; 3185 3186 case CHIP_ID_YUKON_FE_P: 3187 hw->flags = SKY2_HW_NEWER_PHY 3188 | SKY2_HW_NEW_LE 3189 | SKY2_HW_AUTO_TX_SUM 3190 | SKY2_HW_ADV_POWER_CTL; 3191 3192 /* The workaround for status conflicts VLAN tag detection. */ 3193 if (hw->chip_rev == CHIP_REV_YU_FE2_A0) 3194 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM; 3195 break; 3196 3197 case CHIP_ID_YUKON_SUPR: 3198 hw->flags = SKY2_HW_GIGABIT 3199 | SKY2_HW_NEWER_PHY 3200 | SKY2_HW_NEW_LE 3201 | SKY2_HW_AUTO_TX_SUM 3202 | SKY2_HW_ADV_POWER_CTL; 3203 3204 if (hw->chip_rev == CHIP_REV_YU_SU_A0) 3205 hw->flags |= SKY2_HW_RSS_CHKSUM; 3206 break; 3207 3208 case CHIP_ID_YUKON_UL_2: 3209 hw->flags = SKY2_HW_GIGABIT 3210 | SKY2_HW_ADV_POWER_CTL; 3211 break; 3212 3213 case CHIP_ID_YUKON_OPT: 3214 case CHIP_ID_YUKON_PRM: 3215 case CHIP_ID_YUKON_OP_2: 3216 hw->flags = SKY2_HW_GIGABIT 3217 | SKY2_HW_NEW_LE 3218 | SKY2_HW_ADV_POWER_CTL; 3219 break; 3220 3221 default: 3222 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3223 hw->chip_id); 3224 return -EOPNOTSUPP; 3225 } 3226 3227 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 3228 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 3229 hw->flags |= SKY2_HW_FIBRE_PHY; 3230 3231 hw->ports = 1; 3232 t8 = sky2_read8(hw, B2_Y2_HW_RES); 3233 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 3234 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 3235 ++hw->ports; 3236 } 3237 3238 if (sky2_read8(hw, B2_E_0)) 3239 hw->flags |= SKY2_HW_RAM_BUFFER; 3240 3241 return 0; 3242 } 3243 3244 static void sky2_reset(struct sky2_hw *hw) 3245 { 3246 struct pci_dev *pdev = hw->pdev; 3247 u16 status; 3248 int i; 3249 u32 hwe_mask = Y2_HWE_ALL_MASK; 3250 3251 /* disable ASF */ 3252 if (hw->chip_id == CHIP_ID_YUKON_EX 3253 || hw->chip_id == CHIP_ID_YUKON_SUPR) { 3254 sky2_write32(hw, CPU_WDOG, 0); 3255 status = sky2_read16(hw, HCU_CCSR); 3256 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 3257 HCU_CCSR_UC_STATE_MSK); 3258 /* 3259 * CPU clock divider shouldn't be used because 3260 * - ASF firmware may malfunction 3261 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks 3262 */ 3263 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK; 3264 sky2_write16(hw, HCU_CCSR, status); 3265 sky2_write32(hw, CPU_WDOG, 0); 3266 } else 3267 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 3268 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 3269 3270 /* do a SW reset */ 3271 sky2_write8(hw, B0_CTST, CS_RST_SET); 3272 sky2_write8(hw, B0_CTST, CS_RST_CLR); 3273 3274 /* allow writes to PCI config */ 3275 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3276 3277 /* clear PCI errors, if any */ 3278 status = sky2_pci_read16(hw, PCI_STATUS); 3279 status |= PCI_STATUS_ERROR_BITS; 3280 sky2_pci_write16(hw, PCI_STATUS, status); 3281 3282 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 3283 3284 if (pci_is_pcie(pdev)) { 3285 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 3286 0xfffffffful); 3287 3288 /* If error bit is stuck on ignore it */ 3289 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 3290 dev_info(&pdev->dev, "ignoring stuck error report bit\n"); 3291 else 3292 hwe_mask |= Y2_IS_PCI_EXP; 3293 } 3294 3295 sky2_power_on(hw); 3296 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3297 3298 for (i = 0; i < hw->ports; i++) { 3299 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3300 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3301 3302 if (hw->chip_id == CHIP_ID_YUKON_EX || 3303 hw->chip_id == CHIP_ID_YUKON_SUPR) 3304 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 3305 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 3306 | GMC_BYP_RETR_ON); 3307 3308 } 3309 3310 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) { 3311 /* enable MACSec clock gating */ 3312 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS); 3313 } 3314 3315 if (hw->chip_id == CHIP_ID_YUKON_OPT || 3316 hw->chip_id == CHIP_ID_YUKON_PRM || 3317 hw->chip_id == CHIP_ID_YUKON_OP_2) { 3318 u16 reg; 3319 3320 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) { 3321 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */ 3322 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7)); 3323 3324 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */ 3325 reg = 10; 3326 3327 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3328 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3329 } else { 3330 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */ 3331 reg = 3; 3332 } 3333 3334 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3335 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT; 3336 3337 /* reset PHY Link Detect */ 3338 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3339 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3340 3341 /* check if PSMv2 was running before */ 3342 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3); 3343 if (reg & PCI_EXP_LNKCTL_ASPMC) 3344 /* restore the PCIe Link Control register */ 3345 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL, 3346 reg); 3347 3348 if (hw->chip_id == CHIP_ID_YUKON_PRM && 3349 hw->chip_rev == CHIP_REV_YU_PRM_A0) { 3350 /* change PHY Interrupt polarity to low active */ 3351 reg = sky2_read16(hw, GPHY_CTRL); 3352 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL); 3353 3354 /* adapt HW for low active PHY Interrupt */ 3355 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL); 3356 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1); 3357 } 3358 3359 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3360 3361 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3362 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3363 } 3364 3365 /* Clear I2C IRQ noise */ 3366 sky2_write32(hw, B2_I2C_IRQ, 1); 3367 3368 /* turn off hardware timer (unused) */ 3369 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 3370 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3371 3372 /* Turn off descriptor polling */ 3373 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 3374 3375 /* Turn off receive timestamp */ 3376 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 3377 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3378 3379 /* enable the Tx Arbiters */ 3380 for (i = 0; i < hw->ports; i++) 3381 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3382 3383 /* Initialize ram interface */ 3384 for (i = 0; i < hw->ports; i++) { 3385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 3386 3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 3395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 3396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 3397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 3398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 3399 } 3400 3401 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 3402 3403 for (i = 0; i < hw->ports; i++) 3404 sky2_gmac_reset(hw, i); 3405 3406 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le)); 3407 hw->st_idx = 0; 3408 3409 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 3410 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 3411 3412 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 3413 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 3414 3415 /* Set the list last index */ 3416 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1); 3417 3418 sky2_write16(hw, STAT_TX_IDX_TH, 10); 3419 sky2_write8(hw, STAT_FIFO_WM, 16); 3420 3421 /* set Status-FIFO ISR watermark */ 3422 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 3423 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 3424 else 3425 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 3426 3427 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 3428 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 3429 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 3430 3431 /* enable status unit */ 3432 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 3433 3434 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 3435 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 3436 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 3437 } 3438 3439 /* Take device down (offline). 3440 * Equivalent to doing dev_stop() but this does not 3441 * inform upper layers of the transition. 3442 */ 3443 static void sky2_detach(struct net_device *dev) 3444 { 3445 if (netif_running(dev)) { 3446 netif_tx_lock(dev); 3447 netif_device_detach(dev); /* stop txq */ 3448 netif_tx_unlock(dev); 3449 sky2_close(dev); 3450 } 3451 } 3452 3453 /* Bring device back after doing sky2_detach */ 3454 static int sky2_reattach(struct net_device *dev) 3455 { 3456 int err = 0; 3457 3458 if (netif_running(dev)) { 3459 err = sky2_open(dev); 3460 if (err) { 3461 netdev_info(dev, "could not restart %d\n", err); 3462 dev_close(dev); 3463 } else { 3464 netif_device_attach(dev); 3465 sky2_set_multicast(dev); 3466 } 3467 } 3468 3469 return err; 3470 } 3471 3472 static void sky2_all_down(struct sky2_hw *hw) 3473 { 3474 int i; 3475 3476 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3477 sky2_write32(hw, B0_IMSK, 0); 3478 sky2_read32(hw, B0_IMSK); 3479 3480 synchronize_irq(hw->pdev->irq); 3481 napi_disable(&hw->napi); 3482 } 3483 3484 for (i = 0; i < hw->ports; i++) { 3485 struct net_device *dev = hw->dev[i]; 3486 struct sky2_port *sky2 = netdev_priv(dev); 3487 3488 if (!netif_running(dev)) 3489 continue; 3490 3491 netif_carrier_off(dev); 3492 netif_tx_disable(dev); 3493 sky2_hw_down(sky2); 3494 } 3495 } 3496 3497 static void sky2_all_up(struct sky2_hw *hw) 3498 { 3499 u32 imask = Y2_IS_BASE; 3500 int i; 3501 3502 for (i = 0; i < hw->ports; i++) { 3503 struct net_device *dev = hw->dev[i]; 3504 struct sky2_port *sky2 = netdev_priv(dev); 3505 3506 if (!netif_running(dev)) 3507 continue; 3508 3509 sky2_hw_up(sky2); 3510 sky2_set_multicast(dev); 3511 imask |= portirq_msk[i]; 3512 netif_wake_queue(dev); 3513 } 3514 3515 if (hw->flags & SKY2_HW_IRQ_SETUP) { 3516 sky2_write32(hw, B0_IMSK, imask); 3517 sky2_read32(hw, B0_IMSK); 3518 sky2_read32(hw, B0_Y2_SP_LISR); 3519 napi_enable(&hw->napi); 3520 } 3521 } 3522 3523 static void sky2_restart(struct work_struct *work) 3524 { 3525 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work); 3526 3527 rtnl_lock(); 3528 3529 sky2_all_down(hw); 3530 sky2_reset(hw); 3531 sky2_all_up(hw); 3532 3533 rtnl_unlock(); 3534 } 3535 3536 static inline u8 sky2_wol_supported(const struct sky2_hw *hw) 3537 { 3538 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0; 3539 } 3540 3541 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3542 { 3543 const struct sky2_port *sky2 = netdev_priv(dev); 3544 3545 wol->supported = sky2_wol_supported(sky2->hw); 3546 wol->wolopts = sky2->wol; 3547 } 3548 3549 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 3550 { 3551 struct sky2_port *sky2 = netdev_priv(dev); 3552 struct sky2_hw *hw = sky2->hw; 3553 bool enable_wakeup = false; 3554 int i; 3555 3556 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) || 3557 !device_can_wakeup(&hw->pdev->dev)) 3558 return -EOPNOTSUPP; 3559 3560 sky2->wol = wol->wolopts; 3561 3562 for (i = 0; i < hw->ports; i++) { 3563 struct net_device *dev = hw->dev[i]; 3564 struct sky2_port *sky2 = netdev_priv(dev); 3565 3566 if (sky2->wol) 3567 enable_wakeup = true; 3568 } 3569 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup); 3570 3571 return 0; 3572 } 3573 3574 static u32 sky2_supported_modes(const struct sky2_hw *hw) 3575 { 3576 if (sky2_is_copper(hw)) { 3577 u32 modes = SUPPORTED_10baseT_Half 3578 | SUPPORTED_10baseT_Full 3579 | SUPPORTED_100baseT_Half 3580 | SUPPORTED_100baseT_Full; 3581 3582 if (hw->flags & SKY2_HW_GIGABIT) 3583 modes |= SUPPORTED_1000baseT_Half 3584 | SUPPORTED_1000baseT_Full; 3585 return modes; 3586 } else 3587 return SUPPORTED_1000baseT_Half 3588 | SUPPORTED_1000baseT_Full; 3589 } 3590 3591 static int sky2_get_link_ksettings(struct net_device *dev, 3592 struct ethtool_link_ksettings *cmd) 3593 { 3594 struct sky2_port *sky2 = netdev_priv(dev); 3595 struct sky2_hw *hw = sky2->hw; 3596 u32 supported, advertising; 3597 3598 supported = sky2_supported_modes(hw); 3599 cmd->base.phy_address = PHY_ADDR_MARV; 3600 if (sky2_is_copper(hw)) { 3601 cmd->base.port = PORT_TP; 3602 cmd->base.speed = sky2->speed; 3603 supported |= SUPPORTED_Autoneg | SUPPORTED_TP; 3604 } else { 3605 cmd->base.speed = SPEED_1000; 3606 cmd->base.port = PORT_FIBRE; 3607 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE; 3608 } 3609 3610 advertising = sky2->advertising; 3611 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED) 3612 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 3613 cmd->base.duplex = sky2->duplex; 3614 3615 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 3616 supported); 3617 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 3618 advertising); 3619 3620 return 0; 3621 } 3622 3623 static int sky2_set_link_ksettings(struct net_device *dev, 3624 const struct ethtool_link_ksettings *cmd) 3625 { 3626 struct sky2_port *sky2 = netdev_priv(dev); 3627 const struct sky2_hw *hw = sky2->hw; 3628 u32 supported = sky2_supported_modes(hw); 3629 u32 new_advertising; 3630 3631 ethtool_convert_link_mode_to_legacy_u32(&new_advertising, 3632 cmd->link_modes.advertising); 3633 3634 if (cmd->base.autoneg == AUTONEG_ENABLE) { 3635 if (new_advertising & ~supported) 3636 return -EINVAL; 3637 3638 if (sky2_is_copper(hw)) 3639 sky2->advertising = new_advertising | 3640 ADVERTISED_TP | 3641 ADVERTISED_Autoneg; 3642 else 3643 sky2->advertising = new_advertising | 3644 ADVERTISED_FIBRE | 3645 ADVERTISED_Autoneg; 3646 3647 sky2->flags |= SKY2_FLAG_AUTO_SPEED; 3648 sky2->duplex = -1; 3649 sky2->speed = -1; 3650 } else { 3651 u32 setting; 3652 u32 speed = cmd->base.speed; 3653 3654 switch (speed) { 3655 case SPEED_1000: 3656 if (cmd->base.duplex == DUPLEX_FULL) 3657 setting = SUPPORTED_1000baseT_Full; 3658 else if (cmd->base.duplex == DUPLEX_HALF) 3659 setting = SUPPORTED_1000baseT_Half; 3660 else 3661 return -EINVAL; 3662 break; 3663 case SPEED_100: 3664 if (cmd->base.duplex == DUPLEX_FULL) 3665 setting = SUPPORTED_100baseT_Full; 3666 else if (cmd->base.duplex == DUPLEX_HALF) 3667 setting = SUPPORTED_100baseT_Half; 3668 else 3669 return -EINVAL; 3670 break; 3671 3672 case SPEED_10: 3673 if (cmd->base.duplex == DUPLEX_FULL) 3674 setting = SUPPORTED_10baseT_Full; 3675 else if (cmd->base.duplex == DUPLEX_HALF) 3676 setting = SUPPORTED_10baseT_Half; 3677 else 3678 return -EINVAL; 3679 break; 3680 default: 3681 return -EINVAL; 3682 } 3683 3684 if ((setting & supported) == 0) 3685 return -EINVAL; 3686 3687 sky2->speed = speed; 3688 sky2->duplex = cmd->base.duplex; 3689 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED; 3690 } 3691 3692 if (netif_running(dev)) { 3693 sky2_phy_reinit(sky2); 3694 sky2_set_multicast(dev); 3695 } 3696 3697 return 0; 3698 } 3699 3700 static void sky2_get_drvinfo(struct net_device *dev, 3701 struct ethtool_drvinfo *info) 3702 { 3703 struct sky2_port *sky2 = netdev_priv(dev); 3704 3705 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 3706 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 3707 strlcpy(info->bus_info, pci_name(sky2->hw->pdev), 3708 sizeof(info->bus_info)); 3709 } 3710 3711 static const struct sky2_stat { 3712 char name[ETH_GSTRING_LEN]; 3713 u16 offset; 3714 } sky2_stats[] = { 3715 { "tx_bytes", GM_TXO_OK_HI }, 3716 { "rx_bytes", GM_RXO_OK_HI }, 3717 { "tx_broadcast", GM_TXF_BC_OK }, 3718 { "rx_broadcast", GM_RXF_BC_OK }, 3719 { "tx_multicast", GM_TXF_MC_OK }, 3720 { "rx_multicast", GM_RXF_MC_OK }, 3721 { "tx_unicast", GM_TXF_UC_OK }, 3722 { "rx_unicast", GM_RXF_UC_OK }, 3723 { "tx_mac_pause", GM_TXF_MPAUSE }, 3724 { "rx_mac_pause", GM_RXF_MPAUSE }, 3725 { "collisions", GM_TXF_COL }, 3726 { "late_collision",GM_TXF_LAT_COL }, 3727 { "aborted", GM_TXF_ABO_COL }, 3728 { "single_collisions", GM_TXF_SNG_COL }, 3729 { "multi_collisions", GM_TXF_MUL_COL }, 3730 3731 { "rx_short", GM_RXF_SHT }, 3732 { "rx_runt", GM_RXE_FRAG }, 3733 { "rx_64_byte_packets", GM_RXF_64B }, 3734 { "rx_65_to_127_byte_packets", GM_RXF_127B }, 3735 { "rx_128_to_255_byte_packets", GM_RXF_255B }, 3736 { "rx_256_to_511_byte_packets", GM_RXF_511B }, 3737 { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, 3738 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, 3739 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, 3740 { "rx_too_long", GM_RXF_LNG_ERR }, 3741 { "rx_fifo_overflow", GM_RXE_FIFO_OV }, 3742 { "rx_jabber", GM_RXF_JAB_PKT }, 3743 { "rx_fcs_error", GM_RXF_FCS_ERR }, 3744 3745 { "tx_64_byte_packets", GM_TXF_64B }, 3746 { "tx_65_to_127_byte_packets", GM_TXF_127B }, 3747 { "tx_128_to_255_byte_packets", GM_TXF_255B }, 3748 { "tx_256_to_511_byte_packets", GM_TXF_511B }, 3749 { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, 3750 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, 3751 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, 3752 { "tx_fifo_underrun", GM_TXE_FIFO_UR }, 3753 }; 3754 3755 static u32 sky2_get_msglevel(struct net_device *netdev) 3756 { 3757 struct sky2_port *sky2 = netdev_priv(netdev); 3758 return sky2->msg_enable; 3759 } 3760 3761 static int sky2_nway_reset(struct net_device *dev) 3762 { 3763 struct sky2_port *sky2 = netdev_priv(dev); 3764 3765 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED)) 3766 return -EINVAL; 3767 3768 sky2_phy_reinit(sky2); 3769 sky2_set_multicast(dev); 3770 3771 return 0; 3772 } 3773 3774 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) 3775 { 3776 struct sky2_hw *hw = sky2->hw; 3777 unsigned port = sky2->port; 3778 int i; 3779 3780 data[0] = get_stats64(hw, port, GM_TXO_OK_LO); 3781 data[1] = get_stats64(hw, port, GM_RXO_OK_LO); 3782 3783 for (i = 2; i < count; i++) 3784 data[i] = get_stats32(hw, port, sky2_stats[i].offset); 3785 } 3786 3787 static void sky2_set_msglevel(struct net_device *netdev, u32 value) 3788 { 3789 struct sky2_port *sky2 = netdev_priv(netdev); 3790 sky2->msg_enable = value; 3791 } 3792 3793 static int sky2_get_sset_count(struct net_device *dev, int sset) 3794 { 3795 switch (sset) { 3796 case ETH_SS_STATS: 3797 return ARRAY_SIZE(sky2_stats); 3798 default: 3799 return -EOPNOTSUPP; 3800 } 3801 } 3802 3803 static void sky2_get_ethtool_stats(struct net_device *dev, 3804 struct ethtool_stats *stats, u64 * data) 3805 { 3806 struct sky2_port *sky2 = netdev_priv(dev); 3807 3808 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); 3809 } 3810 3811 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) 3812 { 3813 int i; 3814 3815 switch (stringset) { 3816 case ETH_SS_STATS: 3817 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) 3818 memcpy(data + i * ETH_GSTRING_LEN, 3819 sky2_stats[i].name, ETH_GSTRING_LEN); 3820 break; 3821 } 3822 } 3823 3824 static int sky2_set_mac_address(struct net_device *dev, void *p) 3825 { 3826 struct sky2_port *sky2 = netdev_priv(dev); 3827 struct sky2_hw *hw = sky2->hw; 3828 unsigned port = sky2->port; 3829 const struct sockaddr *addr = p; 3830 3831 if (!is_valid_ether_addr(addr->sa_data)) 3832 return -EADDRNOTAVAIL; 3833 3834 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 3835 memcpy_toio(hw->regs + B2_MAC_1 + port * 8, 3836 dev->dev_addr, ETH_ALEN); 3837 memcpy_toio(hw->regs + B2_MAC_2 + port * 8, 3838 dev->dev_addr, ETH_ALEN); 3839 3840 /* virtual address for data */ 3841 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3842 3843 /* physical address: used for pause frames */ 3844 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3845 3846 return 0; 3847 } 3848 3849 static inline void sky2_add_filter(u8 filter[8], const u8 *addr) 3850 { 3851 u32 bit; 3852 3853 bit = ether_crc(ETH_ALEN, addr) & 63; 3854 filter[bit >> 3] |= 1 << (bit & 7); 3855 } 3856 3857 static void sky2_set_multicast(struct net_device *dev) 3858 { 3859 struct sky2_port *sky2 = netdev_priv(dev); 3860 struct sky2_hw *hw = sky2->hw; 3861 unsigned port = sky2->port; 3862 struct netdev_hw_addr *ha; 3863 u16 reg; 3864 u8 filter[8]; 3865 int rx_pause; 3866 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 3867 3868 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 3869 memset(filter, 0, sizeof(filter)); 3870 3871 reg = gma_read16(hw, port, GM_RX_CTRL); 3872 reg |= GM_RXCR_UCF_ENA; 3873 3874 if (dev->flags & IFF_PROMISC) /* promiscuous */ 3875 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 3876 else if (dev->flags & IFF_ALLMULTI) 3877 memset(filter, 0xff, sizeof(filter)); 3878 else if (netdev_mc_empty(dev) && !rx_pause) 3879 reg &= ~GM_RXCR_MCF_ENA; 3880 else { 3881 reg |= GM_RXCR_MCF_ENA; 3882 3883 if (rx_pause) 3884 sky2_add_filter(filter, pause_mc_addr); 3885 3886 netdev_for_each_mc_addr(ha, dev) 3887 sky2_add_filter(filter, ha->addr); 3888 } 3889 3890 gma_write16(hw, port, GM_MC_ADDR_H1, 3891 (u16) filter[0] | ((u16) filter[1] << 8)); 3892 gma_write16(hw, port, GM_MC_ADDR_H2, 3893 (u16) filter[2] | ((u16) filter[3] << 8)); 3894 gma_write16(hw, port, GM_MC_ADDR_H3, 3895 (u16) filter[4] | ((u16) filter[5] << 8)); 3896 gma_write16(hw, port, GM_MC_ADDR_H4, 3897 (u16) filter[6] | ((u16) filter[7] << 8)); 3898 3899 gma_write16(hw, port, GM_RX_CTRL, reg); 3900 } 3901 3902 static void sky2_get_stats(struct net_device *dev, 3903 struct rtnl_link_stats64 *stats) 3904 { 3905 struct sky2_port *sky2 = netdev_priv(dev); 3906 struct sky2_hw *hw = sky2->hw; 3907 unsigned port = sky2->port; 3908 unsigned int start; 3909 u64 _bytes, _packets; 3910 3911 do { 3912 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp); 3913 _bytes = sky2->rx_stats.bytes; 3914 _packets = sky2->rx_stats.packets; 3915 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start)); 3916 3917 stats->rx_packets = _packets; 3918 stats->rx_bytes = _bytes; 3919 3920 do { 3921 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp); 3922 _bytes = sky2->tx_stats.bytes; 3923 _packets = sky2->tx_stats.packets; 3924 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start)); 3925 3926 stats->tx_packets = _packets; 3927 stats->tx_bytes = _bytes; 3928 3929 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK) 3930 + get_stats32(hw, port, GM_RXF_BC_OK); 3931 3932 stats->collisions = get_stats32(hw, port, GM_TXF_COL); 3933 3934 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR); 3935 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR); 3936 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT) 3937 + get_stats32(hw, port, GM_RXE_FRAG); 3938 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV); 3939 3940 stats->rx_dropped = dev->stats.rx_dropped; 3941 stats->rx_fifo_errors = dev->stats.rx_fifo_errors; 3942 stats->tx_fifo_errors = dev->stats.tx_fifo_errors; 3943 } 3944 3945 /* Can have one global because blinking is controlled by 3946 * ethtool and that is always under RTNL mutex 3947 */ 3948 static void sky2_led(struct sky2_port *sky2, enum led_mode mode) 3949 { 3950 struct sky2_hw *hw = sky2->hw; 3951 unsigned port = sky2->port; 3952 3953 spin_lock_bh(&sky2->phy_lock); 3954 if (hw->chip_id == CHIP_ID_YUKON_EC_U || 3955 hw->chip_id == CHIP_ID_YUKON_EX || 3956 hw->chip_id == CHIP_ID_YUKON_SUPR) { 3957 u16 pg; 3958 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 3959 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 3960 3961 switch (mode) { 3962 case MO_LED_OFF: 3963 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3964 PHY_M_LEDC_LOS_CTRL(8) | 3965 PHY_M_LEDC_INIT_CTRL(8) | 3966 PHY_M_LEDC_STA1_CTRL(8) | 3967 PHY_M_LEDC_STA0_CTRL(8)); 3968 break; 3969 case MO_LED_ON: 3970 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3971 PHY_M_LEDC_LOS_CTRL(9) | 3972 PHY_M_LEDC_INIT_CTRL(9) | 3973 PHY_M_LEDC_STA1_CTRL(9) | 3974 PHY_M_LEDC_STA0_CTRL(9)); 3975 break; 3976 case MO_LED_BLINK: 3977 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3978 PHY_M_LEDC_LOS_CTRL(0xa) | 3979 PHY_M_LEDC_INIT_CTRL(0xa) | 3980 PHY_M_LEDC_STA1_CTRL(0xa) | 3981 PHY_M_LEDC_STA0_CTRL(0xa)); 3982 break; 3983 case MO_LED_NORM: 3984 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 3985 PHY_M_LEDC_LOS_CTRL(1) | 3986 PHY_M_LEDC_INIT_CTRL(8) | 3987 PHY_M_LEDC_STA1_CTRL(7) | 3988 PHY_M_LEDC_STA0_CTRL(7)); 3989 } 3990 3991 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 3992 } else 3993 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 3994 PHY_M_LED_MO_DUP(mode) | 3995 PHY_M_LED_MO_10(mode) | 3996 PHY_M_LED_MO_100(mode) | 3997 PHY_M_LED_MO_1000(mode) | 3998 PHY_M_LED_MO_RX(mode) | 3999 PHY_M_LED_MO_TX(mode)); 4000 4001 spin_unlock_bh(&sky2->phy_lock); 4002 } 4003 4004 /* blink LED's for finding board */ 4005 static int sky2_set_phys_id(struct net_device *dev, 4006 enum ethtool_phys_id_state state) 4007 { 4008 struct sky2_port *sky2 = netdev_priv(dev); 4009 4010 switch (state) { 4011 case ETHTOOL_ID_ACTIVE: 4012 return 1; /* cycle on/off once per second */ 4013 case ETHTOOL_ID_INACTIVE: 4014 sky2_led(sky2, MO_LED_NORM); 4015 break; 4016 case ETHTOOL_ID_ON: 4017 sky2_led(sky2, MO_LED_ON); 4018 break; 4019 case ETHTOOL_ID_OFF: 4020 sky2_led(sky2, MO_LED_OFF); 4021 break; 4022 } 4023 4024 return 0; 4025 } 4026 4027 static void sky2_get_pauseparam(struct net_device *dev, 4028 struct ethtool_pauseparam *ecmd) 4029 { 4030 struct sky2_port *sky2 = netdev_priv(dev); 4031 4032 switch (sky2->flow_mode) { 4033 case FC_NONE: 4034 ecmd->tx_pause = ecmd->rx_pause = 0; 4035 break; 4036 case FC_TX: 4037 ecmd->tx_pause = 1, ecmd->rx_pause = 0; 4038 break; 4039 case FC_RX: 4040 ecmd->tx_pause = 0, ecmd->rx_pause = 1; 4041 break; 4042 case FC_BOTH: 4043 ecmd->tx_pause = ecmd->rx_pause = 1; 4044 } 4045 4046 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE) 4047 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 4048 } 4049 4050 static int sky2_set_pauseparam(struct net_device *dev, 4051 struct ethtool_pauseparam *ecmd) 4052 { 4053 struct sky2_port *sky2 = netdev_priv(dev); 4054 4055 if (ecmd->autoneg == AUTONEG_ENABLE) 4056 sky2->flags |= SKY2_FLAG_AUTO_PAUSE; 4057 else 4058 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE; 4059 4060 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause); 4061 4062 if (netif_running(dev)) 4063 sky2_phy_reinit(sky2); 4064 4065 return 0; 4066 } 4067 4068 static int sky2_get_coalesce(struct net_device *dev, 4069 struct ethtool_coalesce *ecmd) 4070 { 4071 struct sky2_port *sky2 = netdev_priv(dev); 4072 struct sky2_hw *hw = sky2->hw; 4073 4074 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) 4075 ecmd->tx_coalesce_usecs = 0; 4076 else { 4077 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); 4078 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); 4079 } 4080 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); 4081 4082 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) 4083 ecmd->rx_coalesce_usecs = 0; 4084 else { 4085 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); 4086 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); 4087 } 4088 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); 4089 4090 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) 4091 ecmd->rx_coalesce_usecs_irq = 0; 4092 else { 4093 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); 4094 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); 4095 } 4096 4097 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); 4098 4099 return 0; 4100 } 4101 4102 /* Note: this affect both ports */ 4103 static int sky2_set_coalesce(struct net_device *dev, 4104 struct ethtool_coalesce *ecmd) 4105 { 4106 struct sky2_port *sky2 = netdev_priv(dev); 4107 struct sky2_hw *hw = sky2->hw; 4108 const u32 tmax = sky2_clk2us(hw, 0x0ffffff); 4109 4110 if (ecmd->tx_coalesce_usecs > tmax || 4111 ecmd->rx_coalesce_usecs > tmax || 4112 ecmd->rx_coalesce_usecs_irq > tmax) 4113 return -EINVAL; 4114 4115 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1) 4116 return -EINVAL; 4117 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) 4118 return -EINVAL; 4119 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING) 4120 return -EINVAL; 4121 4122 if (ecmd->tx_coalesce_usecs == 0) 4123 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 4124 else { 4125 sky2_write32(hw, STAT_TX_TIMER_INI, 4126 sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); 4127 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 4128 } 4129 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); 4130 4131 if (ecmd->rx_coalesce_usecs == 0) 4132 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); 4133 else { 4134 sky2_write32(hw, STAT_LEV_TIMER_INI, 4135 sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); 4136 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 4137 } 4138 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); 4139 4140 if (ecmd->rx_coalesce_usecs_irq == 0) 4141 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); 4142 else { 4143 sky2_write32(hw, STAT_ISR_TIMER_INI, 4144 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); 4145 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 4146 } 4147 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); 4148 return 0; 4149 } 4150 4151 /* 4152 * Hardware is limited to min of 128 and max of 2048 for ring size 4153 * and rounded up to next power of two 4154 * to avoid division in modulus calclation 4155 */ 4156 static unsigned long roundup_ring_size(unsigned long pending) 4157 { 4158 return max(128ul, roundup_pow_of_two(pending+1)); 4159 } 4160 4161 static void sky2_get_ringparam(struct net_device *dev, 4162 struct ethtool_ringparam *ering) 4163 { 4164 struct sky2_port *sky2 = netdev_priv(dev); 4165 4166 ering->rx_max_pending = RX_MAX_PENDING; 4167 ering->tx_max_pending = TX_MAX_PENDING; 4168 4169 ering->rx_pending = sky2->rx_pending; 4170 ering->tx_pending = sky2->tx_pending; 4171 } 4172 4173 static int sky2_set_ringparam(struct net_device *dev, 4174 struct ethtool_ringparam *ering) 4175 { 4176 struct sky2_port *sky2 = netdev_priv(dev); 4177 4178 if (ering->rx_pending > RX_MAX_PENDING || 4179 ering->rx_pending < 8 || 4180 ering->tx_pending < TX_MIN_PENDING || 4181 ering->tx_pending > TX_MAX_PENDING) 4182 return -EINVAL; 4183 4184 sky2_detach(dev); 4185 4186 sky2->rx_pending = ering->rx_pending; 4187 sky2->tx_pending = ering->tx_pending; 4188 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending); 4189 4190 return sky2_reattach(dev); 4191 } 4192 4193 static int sky2_get_regs_len(struct net_device *dev) 4194 { 4195 return 0x4000; 4196 } 4197 4198 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b) 4199 { 4200 /* This complicated switch statement is to make sure and 4201 * only access regions that are unreserved. 4202 * Some blocks are only valid on dual port cards. 4203 */ 4204 switch (b) { 4205 /* second port */ 4206 case 5: /* Tx Arbiter 2 */ 4207 case 9: /* RX2 */ 4208 case 14 ... 15: /* TX2 */ 4209 case 17: case 19: /* Ram Buffer 2 */ 4210 case 22 ... 23: /* Tx Ram Buffer 2 */ 4211 case 25: /* Rx MAC Fifo 1 */ 4212 case 27: /* Tx MAC Fifo 2 */ 4213 case 31: /* GPHY 2 */ 4214 case 40 ... 47: /* Pattern Ram 2 */ 4215 case 52: case 54: /* TCP Segmentation 2 */ 4216 case 112 ... 116: /* GMAC 2 */ 4217 return hw->ports > 1; 4218 4219 case 0: /* Control */ 4220 case 2: /* Mac address */ 4221 case 4: /* Tx Arbiter 1 */ 4222 case 7: /* PCI express reg */ 4223 case 8: /* RX1 */ 4224 case 12 ... 13: /* TX1 */ 4225 case 16: case 18:/* Rx Ram Buffer 1 */ 4226 case 20 ... 21: /* Tx Ram Buffer 1 */ 4227 case 24: /* Rx MAC Fifo 1 */ 4228 case 26: /* Tx MAC Fifo 1 */ 4229 case 28 ... 29: /* Descriptor and status unit */ 4230 case 30: /* GPHY 1*/ 4231 case 32 ... 39: /* Pattern Ram 1 */ 4232 case 48: case 50: /* TCP Segmentation 1 */ 4233 case 56 ... 60: /* PCI space */ 4234 case 80 ... 84: /* GMAC 1 */ 4235 return 1; 4236 4237 default: 4238 return 0; 4239 } 4240 } 4241 4242 /* 4243 * Returns copy of control register region 4244 * Note: ethtool_get_regs always provides full size (16k) buffer 4245 */ 4246 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4247 void *p) 4248 { 4249 const struct sky2_port *sky2 = netdev_priv(dev); 4250 const void __iomem *io = sky2->hw->regs; 4251 unsigned int b; 4252 4253 regs->version = 1; 4254 4255 for (b = 0; b < 128; b++) { 4256 /* skip poisonous diagnostic ram region in block 3 */ 4257 if (b == 3) 4258 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10); 4259 else if (sky2_reg_access_ok(sky2->hw, b)) 4260 memcpy_fromio(p, io, 128); 4261 else 4262 memset(p, 0, 128); 4263 4264 p += 128; 4265 io += 128; 4266 } 4267 } 4268 4269 static int sky2_get_eeprom_len(struct net_device *dev) 4270 { 4271 struct sky2_port *sky2 = netdev_priv(dev); 4272 struct sky2_hw *hw = sky2->hw; 4273 u16 reg2; 4274 4275 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4276 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4277 } 4278 4279 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy) 4280 { 4281 unsigned long start = jiffies; 4282 4283 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) { 4284 /* Can take up to 10.6 ms for write */ 4285 if (time_after(jiffies, start + HZ/4)) { 4286 dev_err(&hw->pdev->dev, "VPD cycle timed out\n"); 4287 return -ETIMEDOUT; 4288 } 4289 msleep(1); 4290 } 4291 4292 return 0; 4293 } 4294 4295 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data, 4296 u16 offset, size_t length) 4297 { 4298 int rc = 0; 4299 4300 while (length > 0) { 4301 u32 val; 4302 4303 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); 4304 rc = sky2_vpd_wait(hw, cap, 0); 4305 if (rc) 4306 break; 4307 4308 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); 4309 4310 memcpy(data, &val, min(sizeof(val), length)); 4311 offset += sizeof(u32); 4312 data += sizeof(u32); 4313 length -= sizeof(u32); 4314 } 4315 4316 return rc; 4317 } 4318 4319 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data, 4320 u16 offset, unsigned int length) 4321 { 4322 unsigned int i; 4323 int rc = 0; 4324 4325 for (i = 0; i < length; i += sizeof(u32)) { 4326 u32 val = *(u32 *)(data + i); 4327 4328 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val); 4329 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); 4330 4331 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F); 4332 if (rc) 4333 break; 4334 } 4335 return rc; 4336 } 4337 4338 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4339 u8 *data) 4340 { 4341 struct sky2_port *sky2 = netdev_priv(dev); 4342 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4343 4344 if (!cap) 4345 return -EINVAL; 4346 4347 eeprom->magic = SKY2_EEPROM_MAGIC; 4348 4349 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4350 } 4351 4352 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 4353 u8 *data) 4354 { 4355 struct sky2_port *sky2 = netdev_priv(dev); 4356 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD); 4357 4358 if (!cap) 4359 return -EINVAL; 4360 4361 if (eeprom->magic != SKY2_EEPROM_MAGIC) 4362 return -EINVAL; 4363 4364 /* Partial writes not supported */ 4365 if ((eeprom->offset & 3) || (eeprom->len & 3)) 4366 return -EINVAL; 4367 4368 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len); 4369 } 4370 4371 static netdev_features_t sky2_fix_features(struct net_device *dev, 4372 netdev_features_t features) 4373 { 4374 const struct sky2_port *sky2 = netdev_priv(dev); 4375 const struct sky2_hw *hw = sky2->hw; 4376 4377 /* In order to do Jumbo packets on these chips, need to turn off the 4378 * transmit store/forward. Therefore checksum offload won't work. 4379 */ 4380 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) { 4381 netdev_info(dev, "checksum offload not possible with jumbo frames\n"); 4382 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK); 4383 } 4384 4385 /* Some hardware requires receive checksum for RSS to work. */ 4386 if ( (features & NETIF_F_RXHASH) && 4387 !(features & NETIF_F_RXCSUM) && 4388 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) { 4389 netdev_info(dev, "receive hashing forces receive checksum\n"); 4390 features |= NETIF_F_RXCSUM; 4391 } 4392 4393 return features; 4394 } 4395 4396 static int sky2_set_features(struct net_device *dev, netdev_features_t features) 4397 { 4398 struct sky2_port *sky2 = netdev_priv(dev); 4399 netdev_features_t changed = dev->features ^ features; 4400 4401 if ((changed & NETIF_F_RXCSUM) && 4402 !(sky2->hw->flags & SKY2_HW_NEW_LE)) { 4403 sky2_write32(sky2->hw, 4404 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 4405 (features & NETIF_F_RXCSUM) 4406 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); 4407 } 4408 4409 if (changed & NETIF_F_RXHASH) 4410 rx_set_rss(dev, features); 4411 4412 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) 4413 sky2_vlan_mode(dev, features); 4414 4415 return 0; 4416 } 4417 4418 static const struct ethtool_ops sky2_ethtool_ops = { 4419 .get_drvinfo = sky2_get_drvinfo, 4420 .get_wol = sky2_get_wol, 4421 .set_wol = sky2_set_wol, 4422 .get_msglevel = sky2_get_msglevel, 4423 .set_msglevel = sky2_set_msglevel, 4424 .nway_reset = sky2_nway_reset, 4425 .get_regs_len = sky2_get_regs_len, 4426 .get_regs = sky2_get_regs, 4427 .get_link = ethtool_op_get_link, 4428 .get_eeprom_len = sky2_get_eeprom_len, 4429 .get_eeprom = sky2_get_eeprom, 4430 .set_eeprom = sky2_set_eeprom, 4431 .get_strings = sky2_get_strings, 4432 .get_coalesce = sky2_get_coalesce, 4433 .set_coalesce = sky2_set_coalesce, 4434 .get_ringparam = sky2_get_ringparam, 4435 .set_ringparam = sky2_set_ringparam, 4436 .get_pauseparam = sky2_get_pauseparam, 4437 .set_pauseparam = sky2_set_pauseparam, 4438 .set_phys_id = sky2_set_phys_id, 4439 .get_sset_count = sky2_get_sset_count, 4440 .get_ethtool_stats = sky2_get_ethtool_stats, 4441 .get_link_ksettings = sky2_get_link_ksettings, 4442 .set_link_ksettings = sky2_set_link_ksettings, 4443 }; 4444 4445 #ifdef CONFIG_SKY2_DEBUG 4446 4447 static struct dentry *sky2_debug; 4448 4449 4450 /* 4451 * Read and parse the first part of Vital Product Data 4452 */ 4453 #define VPD_SIZE 128 4454 #define VPD_MAGIC 0x82 4455 4456 static const struct vpd_tag { 4457 char tag[2]; 4458 char *label; 4459 } vpd_tags[] = { 4460 { "PN", "Part Number" }, 4461 { "EC", "Engineering Level" }, 4462 { "MN", "Manufacturer" }, 4463 { "SN", "Serial Number" }, 4464 { "YA", "Asset Tag" }, 4465 { "VL", "First Error Log Message" }, 4466 { "VF", "Second Error Log Message" }, 4467 { "VB", "Boot Agent ROM Configuration" }, 4468 { "VE", "EFI UNDI Configuration" }, 4469 }; 4470 4471 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw) 4472 { 4473 size_t vpd_size; 4474 loff_t offs; 4475 u8 len; 4476 unsigned char *buf; 4477 u16 reg2; 4478 4479 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); 4480 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 4481 4482 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev)); 4483 buf = kmalloc(vpd_size, GFP_KERNEL); 4484 if (!buf) { 4485 seq_puts(seq, "no memory!\n"); 4486 return; 4487 } 4488 4489 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) { 4490 seq_puts(seq, "VPD read failed\n"); 4491 goto out; 4492 } 4493 4494 if (buf[0] != VPD_MAGIC) { 4495 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]); 4496 goto out; 4497 } 4498 len = buf[1]; 4499 if (len == 0 || len > vpd_size - 4) { 4500 seq_printf(seq, "Invalid id length: %d\n", len); 4501 goto out; 4502 } 4503 4504 seq_printf(seq, "%.*s\n", len, buf + 3); 4505 offs = len + 3; 4506 4507 while (offs < vpd_size - 4) { 4508 int i; 4509 4510 if (!memcmp("RW", buf + offs, 2)) /* end marker */ 4511 break; 4512 len = buf[offs + 2]; 4513 if (offs + len + 3 >= vpd_size) 4514 break; 4515 4516 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) { 4517 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) { 4518 seq_printf(seq, " %s: %.*s\n", 4519 vpd_tags[i].label, len, buf + offs + 3); 4520 break; 4521 } 4522 } 4523 offs += len + 3; 4524 } 4525 out: 4526 kfree(buf); 4527 } 4528 4529 static int sky2_debug_show(struct seq_file *seq, void *v) 4530 { 4531 struct net_device *dev = seq->private; 4532 const struct sky2_port *sky2 = netdev_priv(dev); 4533 struct sky2_hw *hw = sky2->hw; 4534 unsigned port = sky2->port; 4535 unsigned idx, last; 4536 int sop; 4537 4538 sky2_show_vpd(seq, hw); 4539 4540 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n", 4541 sky2_read32(hw, B0_ISRC), 4542 sky2_read32(hw, B0_IMSK), 4543 sky2_read32(hw, B0_Y2_SP_ICR)); 4544 4545 if (!netif_running(dev)) { 4546 seq_puts(seq, "network not running\n"); 4547 return 0; 4548 } 4549 4550 napi_disable(&hw->napi); 4551 last = sky2_read16(hw, STAT_PUT_IDX); 4552 4553 seq_printf(seq, "Status ring %u\n", hw->st_size); 4554 if (hw->st_idx == last) 4555 seq_puts(seq, "Status ring (empty)\n"); 4556 else { 4557 seq_puts(seq, "Status ring\n"); 4558 for (idx = hw->st_idx; idx != last && idx < hw->st_size; 4559 idx = RING_NEXT(idx, hw->st_size)) { 4560 const struct sky2_status_le *le = hw->st_le + idx; 4561 seq_printf(seq, "[%d] %#x %d %#x\n", 4562 idx, le->opcode, le->length, le->status); 4563 } 4564 seq_puts(seq, "\n"); 4565 } 4566 4567 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n", 4568 sky2->tx_cons, sky2->tx_prod, 4569 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX), 4570 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE))); 4571 4572 /* Dump contents of tx ring */ 4573 sop = 1; 4574 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size; 4575 idx = RING_NEXT(idx, sky2->tx_ring_size)) { 4576 const struct sky2_tx_le *le = sky2->tx_le + idx; 4577 u32 a = le32_to_cpu(le->addr); 4578 4579 if (sop) 4580 seq_printf(seq, "%u:", idx); 4581 sop = 0; 4582 4583 switch (le->opcode & ~HW_OWNER) { 4584 case OP_ADDR64: 4585 seq_printf(seq, " %#x:", a); 4586 break; 4587 case OP_LRGLEN: 4588 seq_printf(seq, " mtu=%d", a); 4589 break; 4590 case OP_VLAN: 4591 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length)); 4592 break; 4593 case OP_TCPLISW: 4594 seq_printf(seq, " csum=%#x", a); 4595 break; 4596 case OP_LARGESEND: 4597 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length)); 4598 break; 4599 case OP_PACKET: 4600 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length)); 4601 break; 4602 case OP_BUFFER: 4603 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length)); 4604 break; 4605 default: 4606 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode, 4607 a, le16_to_cpu(le->length)); 4608 } 4609 4610 if (le->ctrl & EOP) { 4611 seq_putc(seq, '\n'); 4612 sop = 1; 4613 } 4614 } 4615 4616 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n", 4617 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)), 4618 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)), 4619 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX))); 4620 4621 sky2_read32(hw, B0_Y2_SP_LISR); 4622 napi_enable(&hw->napi); 4623 return 0; 4624 } 4625 DEFINE_SHOW_ATTRIBUTE(sky2_debug); 4626 4627 /* 4628 * Use network device events to create/remove/rename 4629 * debugfs file entries 4630 */ 4631 static int sky2_device_event(struct notifier_block *unused, 4632 unsigned long event, void *ptr) 4633 { 4634 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4635 struct sky2_port *sky2 = netdev_priv(dev); 4636 4637 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug) 4638 return NOTIFY_DONE; 4639 4640 switch (event) { 4641 case NETDEV_CHANGENAME: 4642 if (sky2->debugfs) { 4643 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs, 4644 sky2_debug, dev->name); 4645 } 4646 break; 4647 4648 case NETDEV_GOING_DOWN: 4649 if (sky2->debugfs) { 4650 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n"); 4651 debugfs_remove(sky2->debugfs); 4652 sky2->debugfs = NULL; 4653 } 4654 break; 4655 4656 case NETDEV_UP: 4657 sky2->debugfs = debugfs_create_file(dev->name, 0444, 4658 sky2_debug, dev, 4659 &sky2_debug_fops); 4660 if (IS_ERR(sky2->debugfs)) 4661 sky2->debugfs = NULL; 4662 } 4663 4664 return NOTIFY_DONE; 4665 } 4666 4667 static struct notifier_block sky2_notifier = { 4668 .notifier_call = sky2_device_event, 4669 }; 4670 4671 4672 static __init void sky2_debug_init(void) 4673 { 4674 struct dentry *ent; 4675 4676 ent = debugfs_create_dir("sky2", NULL); 4677 if (!ent || IS_ERR(ent)) 4678 return; 4679 4680 sky2_debug = ent; 4681 register_netdevice_notifier(&sky2_notifier); 4682 } 4683 4684 static __exit void sky2_debug_cleanup(void) 4685 { 4686 if (sky2_debug) { 4687 unregister_netdevice_notifier(&sky2_notifier); 4688 debugfs_remove(sky2_debug); 4689 sky2_debug = NULL; 4690 } 4691 } 4692 4693 #else 4694 #define sky2_debug_init() 4695 #define sky2_debug_cleanup() 4696 #endif 4697 4698 /* Two copies of network device operations to handle special case of 4699 not allowing netpoll on second port */ 4700 static const struct net_device_ops sky2_netdev_ops[2] = { 4701 { 4702 .ndo_open = sky2_open, 4703 .ndo_stop = sky2_close, 4704 .ndo_start_xmit = sky2_xmit_frame, 4705 .ndo_do_ioctl = sky2_ioctl, 4706 .ndo_validate_addr = eth_validate_addr, 4707 .ndo_set_mac_address = sky2_set_mac_address, 4708 .ndo_set_rx_mode = sky2_set_multicast, 4709 .ndo_change_mtu = sky2_change_mtu, 4710 .ndo_fix_features = sky2_fix_features, 4711 .ndo_set_features = sky2_set_features, 4712 .ndo_tx_timeout = sky2_tx_timeout, 4713 .ndo_get_stats64 = sky2_get_stats, 4714 #ifdef CONFIG_NET_POLL_CONTROLLER 4715 .ndo_poll_controller = sky2_netpoll, 4716 #endif 4717 }, 4718 { 4719 .ndo_open = sky2_open, 4720 .ndo_stop = sky2_close, 4721 .ndo_start_xmit = sky2_xmit_frame, 4722 .ndo_do_ioctl = sky2_ioctl, 4723 .ndo_validate_addr = eth_validate_addr, 4724 .ndo_set_mac_address = sky2_set_mac_address, 4725 .ndo_set_rx_mode = sky2_set_multicast, 4726 .ndo_change_mtu = sky2_change_mtu, 4727 .ndo_fix_features = sky2_fix_features, 4728 .ndo_set_features = sky2_set_features, 4729 .ndo_tx_timeout = sky2_tx_timeout, 4730 .ndo_get_stats64 = sky2_get_stats, 4731 }, 4732 }; 4733 4734 /* Initialize network device */ 4735 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port, 4736 int highmem, int wol) 4737 { 4738 struct sky2_port *sky2; 4739 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 4740 const void *iap; 4741 4742 if (!dev) 4743 return NULL; 4744 4745 SET_NETDEV_DEV(dev, &hw->pdev->dev); 4746 dev->irq = hw->pdev->irq; 4747 dev->ethtool_ops = &sky2_ethtool_ops; 4748 dev->watchdog_timeo = TX_WATCHDOG; 4749 dev->netdev_ops = &sky2_netdev_ops[port]; 4750 4751 sky2 = netdev_priv(dev); 4752 sky2->netdev = dev; 4753 sky2->hw = hw; 4754 sky2->msg_enable = netif_msg_init(debug, default_msg); 4755 4756 u64_stats_init(&sky2->tx_stats.syncp); 4757 u64_stats_init(&sky2->rx_stats.syncp); 4758 4759 /* Auto speed and flow control */ 4760 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE; 4761 if (hw->chip_id != CHIP_ID_YUKON_XL) 4762 dev->hw_features |= NETIF_F_RXCSUM; 4763 4764 sky2->flow_mode = FC_BOTH; 4765 4766 sky2->duplex = -1; 4767 sky2->speed = -1; 4768 sky2->advertising = sky2_supported_modes(hw); 4769 sky2->wol = wol; 4770 4771 spin_lock_init(&sky2->phy_lock); 4772 4773 sky2->tx_pending = TX_DEF_PENDING; 4774 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING); 4775 sky2->rx_pending = RX_DEF_PENDING; 4776 4777 hw->dev[port] = dev; 4778 4779 sky2->port = port; 4780 4781 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO; 4782 4783 if (highmem) 4784 dev->features |= NETIF_F_HIGHDMA; 4785 4786 /* Enable receive hashing unless hardware is known broken */ 4787 if (!(hw->flags & SKY2_HW_RSS_BROKEN)) 4788 dev->hw_features |= NETIF_F_RXHASH; 4789 4790 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) { 4791 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 4792 NETIF_F_HW_VLAN_CTAG_RX; 4793 dev->vlan_features |= SKY2_VLAN_OFFLOADS; 4794 } 4795 4796 dev->features |= dev->hw_features; 4797 4798 /* MTU range: 60 - 1500 or 9000 */ 4799 dev->min_mtu = ETH_ZLEN; 4800 if (hw->chip_id == CHIP_ID_YUKON_FE || 4801 hw->chip_id == CHIP_ID_YUKON_FE_P) 4802 dev->max_mtu = ETH_DATA_LEN; 4803 else 4804 dev->max_mtu = ETH_JUMBO_MTU; 4805 4806 /* try to get mac address in the following order: 4807 * 1) from device tree data 4808 * 2) from internal registers set by bootloader 4809 */ 4810 iap = of_get_mac_address(hw->pdev->dev.of_node); 4811 if (iap) 4812 memcpy(dev->dev_addr, iap, ETH_ALEN); 4813 else 4814 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, 4815 ETH_ALEN); 4816 4817 /* if the address is invalid, use a random value */ 4818 if (!is_valid_ether_addr(dev->dev_addr)) { 4819 struct sockaddr sa = { AF_UNSPEC }; 4820 4821 netdev_warn(dev, 4822 "Invalid MAC address, defaulting to random\n"); 4823 eth_hw_addr_random(dev); 4824 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN); 4825 if (sky2_set_mac_address(dev, &sa)) 4826 netdev_warn(dev, "Failed to set MAC address.\n"); 4827 } 4828 4829 return dev; 4830 } 4831 4832 static void sky2_show_addr(struct net_device *dev) 4833 { 4834 const struct sky2_port *sky2 = netdev_priv(dev); 4835 4836 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr); 4837 } 4838 4839 /* Handle software interrupt used during MSI test */ 4840 static irqreturn_t sky2_test_intr(int irq, void *dev_id) 4841 { 4842 struct sky2_hw *hw = dev_id; 4843 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); 4844 4845 if (status == 0) 4846 return IRQ_NONE; 4847 4848 if (status & Y2_IS_IRQ_SW) { 4849 hw->flags |= SKY2_HW_USE_MSI; 4850 wake_up(&hw->msi_wait); 4851 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4852 } 4853 sky2_write32(hw, B0_Y2_SP_ICR, 2); 4854 4855 return IRQ_HANDLED; 4856 } 4857 4858 /* Test interrupt path by forcing a a software IRQ */ 4859 static int sky2_test_msi(struct sky2_hw *hw) 4860 { 4861 struct pci_dev *pdev = hw->pdev; 4862 int err; 4863 4864 init_waitqueue_head(&hw->msi_wait); 4865 4866 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw); 4867 if (err) { 4868 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq); 4869 return err; 4870 } 4871 4872 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); 4873 4874 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); 4875 sky2_read8(hw, B0_CTST); 4876 4877 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10); 4878 4879 if (!(hw->flags & SKY2_HW_USE_MSI)) { 4880 /* MSI test failed, go back to INTx mode */ 4881 dev_info(&pdev->dev, "No interrupt generated using MSI, " 4882 "switching to INTx mode.\n"); 4883 4884 err = -EOPNOTSUPP; 4885 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); 4886 } 4887 4888 sky2_write32(hw, B0_IMSK, 0); 4889 sky2_read32(hw, B0_IMSK); 4890 4891 free_irq(pdev->irq, hw); 4892 4893 return err; 4894 } 4895 4896 /* This driver supports yukon2 chipset only */ 4897 static const char *sky2_name(u8 chipid, char *buf, int sz) 4898 { 4899 const char *name[] = { 4900 "XL", /* 0xb3 */ 4901 "EC Ultra", /* 0xb4 */ 4902 "Extreme", /* 0xb5 */ 4903 "EC", /* 0xb6 */ 4904 "FE", /* 0xb7 */ 4905 "FE+", /* 0xb8 */ 4906 "Supreme", /* 0xb9 */ 4907 "UL 2", /* 0xba */ 4908 "Unknown", /* 0xbb */ 4909 "Optima", /* 0xbc */ 4910 "OptimaEEE", /* 0xbd */ 4911 "Optima 2", /* 0xbe */ 4912 }; 4913 4914 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2) 4915 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz); 4916 else 4917 snprintf(buf, sz, "(chip %#x)", chipid); 4918 return buf; 4919 } 4920 4921 static const struct dmi_system_id msi_blacklist[] = { 4922 { 4923 .ident = "Dell Inspiron 1545", 4924 .matches = { 4925 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 4926 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"), 4927 }, 4928 }, 4929 { 4930 .ident = "Gateway P-79", 4931 .matches = { 4932 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"), 4933 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"), 4934 }, 4935 }, 4936 {} 4937 }; 4938 4939 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 4940 { 4941 struct net_device *dev, *dev1; 4942 struct sky2_hw *hw; 4943 int err, using_dac = 0, wol_default; 4944 u32 reg; 4945 char buf1[16]; 4946 4947 err = pci_enable_device(pdev); 4948 if (err) { 4949 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4950 goto err_out; 4951 } 4952 4953 /* Get configuration information 4954 * Note: only regular PCI config access once to test for HW issues 4955 * other PCI access through shared memory for speed and to 4956 * avoid MMCONFIG problems. 4957 */ 4958 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 4959 if (err) { 4960 dev_err(&pdev->dev, "PCI read config failed\n"); 4961 goto err_out_disable; 4962 } 4963 4964 if (~reg == 0) { 4965 dev_err(&pdev->dev, "PCI configuration read error\n"); 4966 err = -EIO; 4967 goto err_out_disable; 4968 } 4969 4970 err = pci_request_regions(pdev, DRV_NAME); 4971 if (err) { 4972 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 4973 goto err_out_disable; 4974 } 4975 4976 pci_set_master(pdev); 4977 4978 if (sizeof(dma_addr_t) > sizeof(u32) && 4979 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) { 4980 using_dac = 1; 4981 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4982 if (err < 0) { 4983 dev_err(&pdev->dev, "unable to obtain 64 bit DMA " 4984 "for consistent allocations\n"); 4985 goto err_out_free_regions; 4986 } 4987 } else { 4988 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4989 if (err) { 4990 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4991 goto err_out_free_regions; 4992 } 4993 } 4994 4995 4996 #ifdef __BIG_ENDIAN 4997 /* The sk98lin vendor driver uses hardware byte swapping but 4998 * this driver uses software swapping. 4999 */ 5000 reg &= ~PCI_REV_DESC; 5001 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 5002 if (err) { 5003 dev_err(&pdev->dev, "PCI write config failed\n"); 5004 goto err_out_free_regions; 5005 } 5006 #endif 5007 5008 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0; 5009 5010 err = -ENOMEM; 5011 5012 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 5013 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 5014 if (!hw) 5015 goto err_out_free_regions; 5016 5017 hw->pdev = pdev; 5018 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 5019 5020 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); 5021 if (!hw->regs) { 5022 dev_err(&pdev->dev, "cannot map device registers\n"); 5023 goto err_out_free_hw; 5024 } 5025 5026 err = sky2_init(hw); 5027 if (err) 5028 goto err_out_iounmap; 5029 5030 /* ring for status responses */ 5031 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING); 5032 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5033 &hw->st_dma); 5034 if (!hw->st_le) { 5035 err = -ENOMEM; 5036 goto err_out_reset; 5037 } 5038 5039 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n", 5040 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 5041 5042 sky2_reset(hw); 5043 5044 dev = sky2_init_netdev(hw, 0, using_dac, wol_default); 5045 if (!dev) { 5046 err = -ENOMEM; 5047 goto err_out_free_pci; 5048 } 5049 5050 if (disable_msi == -1) 5051 disable_msi = !!dmi_check_system(msi_blacklist); 5052 5053 if (!disable_msi && pci_enable_msi(pdev) == 0) { 5054 err = sky2_test_msi(hw); 5055 if (err) { 5056 pci_disable_msi(pdev); 5057 if (err != -EOPNOTSUPP) 5058 goto err_out_free_netdev; 5059 } 5060 } 5061 5062 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT); 5063 5064 err = register_netdev(dev); 5065 if (err) { 5066 dev_err(&pdev->dev, "cannot register net device\n"); 5067 goto err_out_free_netdev; 5068 } 5069 5070 netif_carrier_off(dev); 5071 5072 sky2_show_addr(dev); 5073 5074 if (hw->ports > 1) { 5075 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default); 5076 if (!dev1) { 5077 err = -ENOMEM; 5078 goto err_out_unregister; 5079 } 5080 5081 err = register_netdev(dev1); 5082 if (err) { 5083 dev_err(&pdev->dev, "cannot register second net device\n"); 5084 goto err_out_free_dev1; 5085 } 5086 5087 err = sky2_setup_irq(hw, hw->irq_name); 5088 if (err) 5089 goto err_out_unregister_dev1; 5090 5091 sky2_show_addr(dev1); 5092 } 5093 5094 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0); 5095 INIT_WORK(&hw->restart_work, sky2_restart); 5096 5097 pci_set_drvdata(pdev, hw); 5098 pdev->d3_delay = 300; 5099 5100 return 0; 5101 5102 err_out_unregister_dev1: 5103 unregister_netdev(dev1); 5104 err_out_free_dev1: 5105 free_netdev(dev1); 5106 err_out_unregister: 5107 unregister_netdev(dev); 5108 err_out_free_netdev: 5109 if (hw->flags & SKY2_HW_USE_MSI) 5110 pci_disable_msi(pdev); 5111 free_netdev(dev); 5112 err_out_free_pci: 5113 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5114 hw->st_le, hw->st_dma); 5115 err_out_reset: 5116 sky2_write8(hw, B0_CTST, CS_RST_SET); 5117 err_out_iounmap: 5118 iounmap(hw->regs); 5119 err_out_free_hw: 5120 kfree(hw); 5121 err_out_free_regions: 5122 pci_release_regions(pdev); 5123 err_out_disable: 5124 pci_disable_device(pdev); 5125 err_out: 5126 return err; 5127 } 5128 5129 static void sky2_remove(struct pci_dev *pdev) 5130 { 5131 struct sky2_hw *hw = pci_get_drvdata(pdev); 5132 int i; 5133 5134 if (!hw) 5135 return; 5136 5137 del_timer_sync(&hw->watchdog_timer); 5138 cancel_work_sync(&hw->restart_work); 5139 5140 for (i = hw->ports-1; i >= 0; --i) 5141 unregister_netdev(hw->dev[i]); 5142 5143 sky2_write32(hw, B0_IMSK, 0); 5144 sky2_read32(hw, B0_IMSK); 5145 5146 sky2_power_aux(hw); 5147 5148 sky2_write8(hw, B0_CTST, CS_RST_SET); 5149 sky2_read8(hw, B0_CTST); 5150 5151 if (hw->ports > 1) { 5152 napi_disable(&hw->napi); 5153 free_irq(pdev->irq, hw); 5154 } 5155 5156 if (hw->flags & SKY2_HW_USE_MSI) 5157 pci_disable_msi(pdev); 5158 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le), 5159 hw->st_le, hw->st_dma); 5160 pci_release_regions(pdev); 5161 pci_disable_device(pdev); 5162 5163 for (i = hw->ports-1; i >= 0; --i) 5164 free_netdev(hw->dev[i]); 5165 5166 iounmap(hw->regs); 5167 kfree(hw); 5168 } 5169 5170 static int sky2_suspend(struct device *dev) 5171 { 5172 struct pci_dev *pdev = to_pci_dev(dev); 5173 struct sky2_hw *hw = pci_get_drvdata(pdev); 5174 int i; 5175 5176 if (!hw) 5177 return 0; 5178 5179 del_timer_sync(&hw->watchdog_timer); 5180 cancel_work_sync(&hw->restart_work); 5181 5182 rtnl_lock(); 5183 5184 sky2_all_down(hw); 5185 for (i = 0; i < hw->ports; i++) { 5186 struct net_device *dev = hw->dev[i]; 5187 struct sky2_port *sky2 = netdev_priv(dev); 5188 5189 if (sky2->wol) 5190 sky2_wol_init(sky2); 5191 } 5192 5193 sky2_power_aux(hw); 5194 rtnl_unlock(); 5195 5196 return 0; 5197 } 5198 5199 #ifdef CONFIG_PM_SLEEP 5200 static int sky2_resume(struct device *dev) 5201 { 5202 struct pci_dev *pdev = to_pci_dev(dev); 5203 struct sky2_hw *hw = pci_get_drvdata(pdev); 5204 int err; 5205 5206 if (!hw) 5207 return 0; 5208 5209 /* Re-enable all clocks */ 5210 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0); 5211 if (err) { 5212 dev_err(&pdev->dev, "PCI write config failed\n"); 5213 goto out; 5214 } 5215 5216 rtnl_lock(); 5217 sky2_reset(hw); 5218 sky2_all_up(hw); 5219 rtnl_unlock(); 5220 5221 return 0; 5222 out: 5223 5224 dev_err(&pdev->dev, "resume failed (%d)\n", err); 5225 pci_disable_device(pdev); 5226 return err; 5227 } 5228 5229 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume); 5230 #define SKY2_PM_OPS (&sky2_pm_ops) 5231 5232 #else 5233 5234 #define SKY2_PM_OPS NULL 5235 #endif 5236 5237 static void sky2_shutdown(struct pci_dev *pdev) 5238 { 5239 struct sky2_hw *hw = pci_get_drvdata(pdev); 5240 int port; 5241 5242 for (port = 0; port < hw->ports; port++) { 5243 struct net_device *ndev = hw->dev[port]; 5244 5245 rtnl_lock(); 5246 if (netif_running(ndev)) { 5247 dev_close(ndev); 5248 netif_device_detach(ndev); 5249 } 5250 rtnl_unlock(); 5251 } 5252 sky2_suspend(&pdev->dev); 5253 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 5254 pci_set_power_state(pdev, PCI_D3hot); 5255 } 5256 5257 static struct pci_driver sky2_driver = { 5258 .name = DRV_NAME, 5259 .id_table = sky2_id_table, 5260 .probe = sky2_probe, 5261 .remove = sky2_remove, 5262 .shutdown = sky2_shutdown, 5263 .driver.pm = SKY2_PM_OPS, 5264 }; 5265 5266 static int __init sky2_init_module(void) 5267 { 5268 pr_info("driver version " DRV_VERSION "\n"); 5269 5270 sky2_debug_init(); 5271 return pci_register_driver(&sky2_driver); 5272 } 5273 5274 static void __exit sky2_cleanup_module(void) 5275 { 5276 pci_unregister_driver(&sky2_driver); 5277 sky2_debug_cleanup(); 5278 } 5279 5280 module_init(sky2_init_module); 5281 module_exit(sky2_cleanup_module); 5282 5283 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); 5284 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 5285 MODULE_LICENSE("GPL"); 5286 MODULE_VERSION(DRV_VERSION); 5287