1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit 4 * Ethernet adapters. Based on earlier sk98lin, e100 and 5 * FreeBSD if_sk drivers. 6 * 7 * This driver intentionally does not support all the features 8 * of the original driver such as link fail-over and link management because 9 * those should be done at higher levels. 10 * 11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> 12 */ 13 14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 15 16 #include <linux/in.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/netdevice.h> 21 #include <linux/etherdevice.h> 22 #include <linux/ethtool.h> 23 #include <linux/pci.h> 24 #include <linux/if_vlan.h> 25 #include <linux/ip.h> 26 #include <linux/delay.h> 27 #include <linux/crc32.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/debugfs.h> 30 #include <linux/sched.h> 31 #include <linux/seq_file.h> 32 #include <linux/mii.h> 33 #include <linux/slab.h> 34 #include <linux/dmi.h> 35 #include <linux/prefetch.h> 36 #include <asm/irq.h> 37 38 #include "skge.h" 39 40 #define DRV_NAME "skge" 41 #define DRV_VERSION "1.14" 42 43 #define DEFAULT_TX_RING_SIZE 128 44 #define DEFAULT_RX_RING_SIZE 512 45 #define MAX_TX_RING_SIZE 1024 46 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) 47 #define MAX_RX_RING_SIZE 4096 48 #define RX_COPY_THRESHOLD 128 49 #define RX_BUF_SIZE 1536 50 #define PHY_RETRIES 1000 51 #define ETH_JUMBO_MTU 9000 52 #define TX_WATCHDOG (5 * HZ) 53 #define NAPI_WEIGHT 64 54 #define BLINK_MS 250 55 #define LINK_HZ HZ 56 57 #define SKGE_EEPROM_MAGIC 0x9933aabb 58 59 60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); 61 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>"); 62 MODULE_LICENSE("GPL"); 63 MODULE_VERSION(DRV_VERSION); 64 65 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 66 NETIF_MSG_LINK | NETIF_MSG_IFUP | 67 NETIF_MSG_IFDOWN); 68 69 static int debug = -1; /* defaults above */ 70 module_param(debug, int, 0); 71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 72 73 static const struct pci_device_id skge_id_table[] = { 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */ 75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */ 76 #ifdef CONFIG_SKGE_GENESIS 77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */ 78 #endif 79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */ 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */ 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */ 82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */ 83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */ 84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ 85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */ 86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */ 87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */ 88 { 0 } 89 }; 90 MODULE_DEVICE_TABLE(pci, skge_id_table); 91 92 static int skge_up(struct net_device *dev); 93 static int skge_down(struct net_device *dev); 94 static void skge_phy_reset(struct skge_port *skge); 95 static void skge_tx_clean(struct net_device *dev); 96 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 97 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); 98 static void genesis_get_stats(struct skge_port *skge, u64 *data); 99 static void yukon_get_stats(struct skge_port *skge, u64 *data); 100 static void yukon_init(struct skge_hw *hw, int port); 101 static void genesis_mac_init(struct skge_hw *hw, int port); 102 static void genesis_link_up(struct skge_port *skge); 103 static void skge_set_multicast(struct net_device *dev); 104 static irqreturn_t skge_intr(int irq, void *dev_id); 105 106 /* Avoid conditionals by using array */ 107 static const int txqaddr[] = { Q_XA1, Q_XA2 }; 108 static const int rxqaddr[] = { Q_R1, Q_R2 }; 109 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; 110 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; 111 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; 112 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; 113 114 static inline bool is_genesis(const struct skge_hw *hw) 115 { 116 #ifdef CONFIG_SKGE_GENESIS 117 return hw->chip_id == CHIP_ID_GENESIS; 118 #else 119 return false; 120 #endif 121 } 122 123 static int skge_get_regs_len(struct net_device *dev) 124 { 125 return 0x4000; 126 } 127 128 /* 129 * Returns copy of whole control register region 130 * Note: skip RAM address register because accessing it will 131 * cause bus hangs! 132 */ 133 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, 134 void *p) 135 { 136 const struct skge_port *skge = netdev_priv(dev); 137 const void __iomem *io = skge->hw->regs; 138 139 regs->version = 1; 140 memset(p, 0, regs->len); 141 memcpy_fromio(p, io, B3_RAM_ADDR); 142 143 if (regs->len > B3_RI_WTO_R1) { 144 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 145 regs->len - B3_RI_WTO_R1); 146 } 147 } 148 149 /* Wake on Lan only supported on Yukon chips with rev 1 or above */ 150 static u32 wol_supported(const struct skge_hw *hw) 151 { 152 if (is_genesis(hw)) 153 return 0; 154 155 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 156 return 0; 157 158 return WAKE_MAGIC | WAKE_PHY; 159 } 160 161 static void skge_wol_init(struct skge_port *skge) 162 { 163 struct skge_hw *hw = skge->hw; 164 int port = skge->port; 165 u16 ctrl; 166 167 skge_write16(hw, B0_CTST, CS_RST_CLR); 168 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR); 169 170 /* Turn on Vaux */ 171 skge_write8(hw, B0_POWER_CTRL, 172 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 173 174 /* WA code for COMA mode -- clear PHY reset */ 175 if (hw->chip_id == CHIP_ID_YUKON_LITE && 176 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 177 u32 reg = skge_read32(hw, B2_GP_IO); 178 reg |= GP_DIR_9; 179 reg &= ~GP_IO_9; 180 skge_write32(hw, B2_GP_IO, reg); 181 } 182 183 skge_write32(hw, SK_REG(port, GPHY_CTRL), 184 GPC_DIS_SLEEP | 185 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 186 GPC_ANEG_1 | GPC_RST_SET); 187 188 skge_write32(hw, SK_REG(port, GPHY_CTRL), 189 GPC_DIS_SLEEP | 190 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 | 191 GPC_ANEG_1 | GPC_RST_CLR); 192 193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 194 195 /* Force to 10/100 skge_reset will re-enable on resume */ 196 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, 197 (PHY_AN_100FULL | PHY_AN_100HALF | 198 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA)); 199 /* no 1000 HD/FD */ 200 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0); 201 gm_phy_write(hw, port, PHY_MARV_CTRL, 202 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE | 203 PHY_CT_RE_CFG | PHY_CT_DUP_MD); 204 205 206 /* Set GMAC to no flow control and auto update for speed/duplex */ 207 gma_write16(hw, port, GM_GP_CTRL, 208 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA| 209 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS); 210 211 /* Set WOL address */ 212 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR), 213 skge->netdev->dev_addr, ETH_ALEN); 214 215 /* Turn on appropriate WOL control bits */ 216 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT); 217 ctrl = 0; 218 if (skge->wol & WAKE_PHY) 219 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT; 220 else 221 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT; 222 223 if (skge->wol & WAKE_MAGIC) 224 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT; 225 else 226 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT; 227 228 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT; 229 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); 230 231 /* block receiver */ 232 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 233 } 234 235 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 236 { 237 struct skge_port *skge = netdev_priv(dev); 238 239 wol->supported = wol_supported(skge->hw); 240 wol->wolopts = skge->wol; 241 } 242 243 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 244 { 245 struct skge_port *skge = netdev_priv(dev); 246 struct skge_hw *hw = skge->hw; 247 248 if ((wol->wolopts & ~wol_supported(hw)) || 249 !device_can_wakeup(&hw->pdev->dev)) 250 return -EOPNOTSUPP; 251 252 skge->wol = wol->wolopts; 253 254 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 255 256 return 0; 257 } 258 259 /* Determine supported/advertised modes based on hardware. 260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx 261 */ 262 static u32 skge_supported_modes(const struct skge_hw *hw) 263 { 264 u32 supported; 265 266 if (hw->copper) { 267 supported = (SUPPORTED_10baseT_Half | 268 SUPPORTED_10baseT_Full | 269 SUPPORTED_100baseT_Half | 270 SUPPORTED_100baseT_Full | 271 SUPPORTED_1000baseT_Half | 272 SUPPORTED_1000baseT_Full | 273 SUPPORTED_Autoneg | 274 SUPPORTED_TP); 275 276 if (is_genesis(hw)) 277 supported &= ~(SUPPORTED_10baseT_Half | 278 SUPPORTED_10baseT_Full | 279 SUPPORTED_100baseT_Half | 280 SUPPORTED_100baseT_Full); 281 282 else if (hw->chip_id == CHIP_ID_YUKON) 283 supported &= ~SUPPORTED_1000baseT_Half; 284 } else 285 supported = (SUPPORTED_1000baseT_Full | 286 SUPPORTED_1000baseT_Half | 287 SUPPORTED_FIBRE | 288 SUPPORTED_Autoneg); 289 290 return supported; 291 } 292 293 static int skge_get_link_ksettings(struct net_device *dev, 294 struct ethtool_link_ksettings *cmd) 295 { 296 struct skge_port *skge = netdev_priv(dev); 297 struct skge_hw *hw = skge->hw; 298 u32 supported, advertising; 299 300 supported = skge_supported_modes(hw); 301 302 if (hw->copper) { 303 cmd->base.port = PORT_TP; 304 cmd->base.phy_address = hw->phy_addr; 305 } else 306 cmd->base.port = PORT_FIBRE; 307 308 advertising = skge->advertising; 309 cmd->base.autoneg = skge->autoneg; 310 cmd->base.speed = skge->speed; 311 cmd->base.duplex = skge->duplex; 312 313 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 314 supported); 315 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 316 advertising); 317 318 return 0; 319 } 320 321 static int skge_set_link_ksettings(struct net_device *dev, 322 const struct ethtool_link_ksettings *cmd) 323 { 324 struct skge_port *skge = netdev_priv(dev); 325 const struct skge_hw *hw = skge->hw; 326 u32 supported = skge_supported_modes(hw); 327 int err = 0; 328 u32 advertising; 329 330 ethtool_convert_link_mode_to_legacy_u32(&advertising, 331 cmd->link_modes.advertising); 332 333 if (cmd->base.autoneg == AUTONEG_ENABLE) { 334 advertising = supported; 335 skge->duplex = -1; 336 skge->speed = -1; 337 } else { 338 u32 setting; 339 u32 speed = cmd->base.speed; 340 341 switch (speed) { 342 case SPEED_1000: 343 if (cmd->base.duplex == DUPLEX_FULL) 344 setting = SUPPORTED_1000baseT_Full; 345 else if (cmd->base.duplex == DUPLEX_HALF) 346 setting = SUPPORTED_1000baseT_Half; 347 else 348 return -EINVAL; 349 break; 350 case SPEED_100: 351 if (cmd->base.duplex == DUPLEX_FULL) 352 setting = SUPPORTED_100baseT_Full; 353 else if (cmd->base.duplex == DUPLEX_HALF) 354 setting = SUPPORTED_100baseT_Half; 355 else 356 return -EINVAL; 357 break; 358 359 case SPEED_10: 360 if (cmd->base.duplex == DUPLEX_FULL) 361 setting = SUPPORTED_10baseT_Full; 362 else if (cmd->base.duplex == DUPLEX_HALF) 363 setting = SUPPORTED_10baseT_Half; 364 else 365 return -EINVAL; 366 break; 367 default: 368 return -EINVAL; 369 } 370 371 if ((setting & supported) == 0) 372 return -EINVAL; 373 374 skge->speed = speed; 375 skge->duplex = cmd->base.duplex; 376 } 377 378 skge->autoneg = cmd->base.autoneg; 379 skge->advertising = advertising; 380 381 if (netif_running(dev)) { 382 skge_down(dev); 383 err = skge_up(dev); 384 if (err) { 385 dev_close(dev); 386 return err; 387 } 388 } 389 390 return 0; 391 } 392 393 static void skge_get_drvinfo(struct net_device *dev, 394 struct ethtool_drvinfo *info) 395 { 396 struct skge_port *skge = netdev_priv(dev); 397 398 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 399 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 400 strlcpy(info->bus_info, pci_name(skge->hw->pdev), 401 sizeof(info->bus_info)); 402 } 403 404 static const struct skge_stat { 405 char name[ETH_GSTRING_LEN]; 406 u16 xmac_offset; 407 u16 gma_offset; 408 } skge_stats[] = { 409 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, 410 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, 411 412 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, 413 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, 414 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, 415 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, 416 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, 417 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, 418 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, 419 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, 420 421 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, 422 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, 423 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, 424 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, 425 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, 426 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, 427 428 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 429 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, 430 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, 431 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, 432 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, 433 }; 434 435 static int skge_get_sset_count(struct net_device *dev, int sset) 436 { 437 switch (sset) { 438 case ETH_SS_STATS: 439 return ARRAY_SIZE(skge_stats); 440 default: 441 return -EOPNOTSUPP; 442 } 443 } 444 445 static void skge_get_ethtool_stats(struct net_device *dev, 446 struct ethtool_stats *stats, u64 *data) 447 { 448 struct skge_port *skge = netdev_priv(dev); 449 450 if (is_genesis(skge->hw)) 451 genesis_get_stats(skge, data); 452 else 453 yukon_get_stats(skge, data); 454 } 455 456 /* Use hardware MIB variables for critical path statistics and 457 * transmit feedback not reported at interrupt. 458 * Other errors are accounted for in interrupt handler. 459 */ 460 static struct net_device_stats *skge_get_stats(struct net_device *dev) 461 { 462 struct skge_port *skge = netdev_priv(dev); 463 u64 data[ARRAY_SIZE(skge_stats)]; 464 465 if (is_genesis(skge->hw)) 466 genesis_get_stats(skge, data); 467 else 468 yukon_get_stats(skge, data); 469 470 dev->stats.tx_bytes = data[0]; 471 dev->stats.rx_bytes = data[1]; 472 dev->stats.tx_packets = data[2] + data[4] + data[6]; 473 dev->stats.rx_packets = data[3] + data[5] + data[7]; 474 dev->stats.multicast = data[3] + data[5]; 475 dev->stats.collisions = data[10]; 476 dev->stats.tx_aborted_errors = data[12]; 477 478 return &dev->stats; 479 } 480 481 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) 482 { 483 int i; 484 485 switch (stringset) { 486 case ETH_SS_STATS: 487 for (i = 0; i < ARRAY_SIZE(skge_stats); i++) 488 memcpy(data + i * ETH_GSTRING_LEN, 489 skge_stats[i].name, ETH_GSTRING_LEN); 490 break; 491 } 492 } 493 494 static void skge_get_ring_param(struct net_device *dev, 495 struct ethtool_ringparam *p, 496 struct kernel_ethtool_ringparam *kernel_p, 497 struct netlink_ext_ack *extack) 498 { 499 struct skge_port *skge = netdev_priv(dev); 500 501 p->rx_max_pending = MAX_RX_RING_SIZE; 502 p->tx_max_pending = MAX_TX_RING_SIZE; 503 504 p->rx_pending = skge->rx_ring.count; 505 p->tx_pending = skge->tx_ring.count; 506 } 507 508 static int skge_set_ring_param(struct net_device *dev, 509 struct ethtool_ringparam *p, 510 struct kernel_ethtool_ringparam *kernel_p, 511 struct netlink_ext_ack *extack) 512 { 513 struct skge_port *skge = netdev_priv(dev); 514 int err = 0; 515 516 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || 517 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) 518 return -EINVAL; 519 520 skge->rx_ring.count = p->rx_pending; 521 skge->tx_ring.count = p->tx_pending; 522 523 if (netif_running(dev)) { 524 skge_down(dev); 525 err = skge_up(dev); 526 if (err) 527 dev_close(dev); 528 } 529 530 return err; 531 } 532 533 static u32 skge_get_msglevel(struct net_device *netdev) 534 { 535 struct skge_port *skge = netdev_priv(netdev); 536 return skge->msg_enable; 537 } 538 539 static void skge_set_msglevel(struct net_device *netdev, u32 value) 540 { 541 struct skge_port *skge = netdev_priv(netdev); 542 skge->msg_enable = value; 543 } 544 545 static int skge_nway_reset(struct net_device *dev) 546 { 547 struct skge_port *skge = netdev_priv(dev); 548 549 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) 550 return -EINVAL; 551 552 skge_phy_reset(skge); 553 return 0; 554 } 555 556 static void skge_get_pauseparam(struct net_device *dev, 557 struct ethtool_pauseparam *ecmd) 558 { 559 struct skge_port *skge = netdev_priv(dev); 560 561 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) || 562 (skge->flow_control == FLOW_MODE_SYM_OR_REM)); 563 ecmd->tx_pause = (ecmd->rx_pause || 564 (skge->flow_control == FLOW_MODE_LOC_SEND)); 565 566 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause; 567 } 568 569 static int skge_set_pauseparam(struct net_device *dev, 570 struct ethtool_pauseparam *ecmd) 571 { 572 struct skge_port *skge = netdev_priv(dev); 573 struct ethtool_pauseparam old; 574 int err = 0; 575 576 skge_get_pauseparam(dev, &old); 577 578 if (ecmd->autoneg != old.autoneg) 579 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC; 580 else { 581 if (ecmd->rx_pause && ecmd->tx_pause) 582 skge->flow_control = FLOW_MODE_SYMMETRIC; 583 else if (ecmd->rx_pause && !ecmd->tx_pause) 584 skge->flow_control = FLOW_MODE_SYM_OR_REM; 585 else if (!ecmd->rx_pause && ecmd->tx_pause) 586 skge->flow_control = FLOW_MODE_LOC_SEND; 587 else 588 skge->flow_control = FLOW_MODE_NONE; 589 } 590 591 if (netif_running(dev)) { 592 skge_down(dev); 593 err = skge_up(dev); 594 if (err) { 595 dev_close(dev); 596 return err; 597 } 598 } 599 600 return 0; 601 } 602 603 /* Chip internal frequency for clock calculations */ 604 static inline u32 hwkhz(const struct skge_hw *hw) 605 { 606 return is_genesis(hw) ? 53125 : 78125; 607 } 608 609 /* Chip HZ to microseconds */ 610 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) 611 { 612 return (ticks * 1000) / hwkhz(hw); 613 } 614 615 /* Microseconds to chip HZ */ 616 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) 617 { 618 return hwkhz(hw) * usec / 1000; 619 } 620 621 static int skge_get_coalesce(struct net_device *dev, 622 struct ethtool_coalesce *ecmd, 623 struct kernel_ethtool_coalesce *kernel_coal, 624 struct netlink_ext_ack *extack) 625 { 626 struct skge_port *skge = netdev_priv(dev); 627 struct skge_hw *hw = skge->hw; 628 int port = skge->port; 629 630 ecmd->rx_coalesce_usecs = 0; 631 ecmd->tx_coalesce_usecs = 0; 632 633 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { 634 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); 635 u32 msk = skge_read32(hw, B2_IRQM_MSK); 636 637 if (msk & rxirqmask[port]) 638 ecmd->rx_coalesce_usecs = delay; 639 if (msk & txirqmask[port]) 640 ecmd->tx_coalesce_usecs = delay; 641 } 642 643 return 0; 644 } 645 646 /* Note: interrupt timer is per board, but can turn on/off per port */ 647 static int skge_set_coalesce(struct net_device *dev, 648 struct ethtool_coalesce *ecmd, 649 struct kernel_ethtool_coalesce *kernel_coal, 650 struct netlink_ext_ack *extack) 651 { 652 struct skge_port *skge = netdev_priv(dev); 653 struct skge_hw *hw = skge->hw; 654 int port = skge->port; 655 u32 msk = skge_read32(hw, B2_IRQM_MSK); 656 u32 delay = 25; 657 658 if (ecmd->rx_coalesce_usecs == 0) 659 msk &= ~rxirqmask[port]; 660 else if (ecmd->rx_coalesce_usecs < 25 || 661 ecmd->rx_coalesce_usecs > 33333) 662 return -EINVAL; 663 else { 664 msk |= rxirqmask[port]; 665 delay = ecmd->rx_coalesce_usecs; 666 } 667 668 if (ecmd->tx_coalesce_usecs == 0) 669 msk &= ~txirqmask[port]; 670 else if (ecmd->tx_coalesce_usecs < 25 || 671 ecmd->tx_coalesce_usecs > 33333) 672 return -EINVAL; 673 else { 674 msk |= txirqmask[port]; 675 delay = min(delay, ecmd->rx_coalesce_usecs); 676 } 677 678 skge_write32(hw, B2_IRQM_MSK, msk); 679 if (msk == 0) 680 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); 681 else { 682 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); 683 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 684 } 685 return 0; 686 } 687 688 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; 689 static void skge_led(struct skge_port *skge, enum led_mode mode) 690 { 691 struct skge_hw *hw = skge->hw; 692 int port = skge->port; 693 694 spin_lock_bh(&hw->phy_lock); 695 if (is_genesis(hw)) { 696 switch (mode) { 697 case LED_MODE_OFF: 698 if (hw->phy_type == SK_PHY_BCOM) 699 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); 700 else { 701 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); 702 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); 703 } 704 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 705 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); 706 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); 707 break; 708 709 case LED_MODE_ON: 710 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); 711 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 712 713 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 714 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 715 716 break; 717 718 case LED_MODE_TST: 719 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); 720 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); 721 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 722 723 if (hw->phy_type == SK_PHY_BCOM) 724 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); 725 else { 726 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); 727 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); 728 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 729 } 730 731 } 732 } else { 733 switch (mode) { 734 case LED_MODE_OFF: 735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 736 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 737 PHY_M_LED_MO_DUP(MO_LED_OFF) | 738 PHY_M_LED_MO_10(MO_LED_OFF) | 739 PHY_M_LED_MO_100(MO_LED_OFF) | 740 PHY_M_LED_MO_1000(MO_LED_OFF) | 741 PHY_M_LED_MO_RX(MO_LED_OFF)); 742 break; 743 case LED_MODE_ON: 744 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 745 PHY_M_LED_PULS_DUR(PULS_170MS) | 746 PHY_M_LED_BLINK_RT(BLINK_84MS) | 747 PHY_M_LEDC_TX_CTRL | 748 PHY_M_LEDC_DP_CTRL); 749 750 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 751 PHY_M_LED_MO_RX(MO_LED_OFF) | 752 (skge->speed == SPEED_100 ? 753 PHY_M_LED_MO_100(MO_LED_ON) : 0)); 754 break; 755 case LED_MODE_TST: 756 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 757 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 758 PHY_M_LED_MO_DUP(MO_LED_ON) | 759 PHY_M_LED_MO_10(MO_LED_ON) | 760 PHY_M_LED_MO_100(MO_LED_ON) | 761 PHY_M_LED_MO_1000(MO_LED_ON) | 762 PHY_M_LED_MO_RX(MO_LED_ON)); 763 } 764 } 765 spin_unlock_bh(&hw->phy_lock); 766 } 767 768 /* blink LED's for finding board */ 769 static int skge_set_phys_id(struct net_device *dev, 770 enum ethtool_phys_id_state state) 771 { 772 struct skge_port *skge = netdev_priv(dev); 773 774 switch (state) { 775 case ETHTOOL_ID_ACTIVE: 776 return 2; /* cycle on/off twice per second */ 777 778 case ETHTOOL_ID_ON: 779 skge_led(skge, LED_MODE_TST); 780 break; 781 782 case ETHTOOL_ID_OFF: 783 skge_led(skge, LED_MODE_OFF); 784 break; 785 786 case ETHTOOL_ID_INACTIVE: 787 /* back to regular LED state */ 788 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); 789 } 790 791 return 0; 792 } 793 794 static int skge_get_eeprom_len(struct net_device *dev) 795 { 796 struct skge_port *skge = netdev_priv(dev); 797 u32 reg2; 798 799 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); 800 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); 801 } 802 803 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset) 804 { 805 u32 val; 806 807 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); 808 809 do { 810 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 811 } while (!(offset & PCI_VPD_ADDR_F)); 812 813 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); 814 return val; 815 } 816 817 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) 818 { 819 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val); 820 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, 821 offset | PCI_VPD_ADDR_F); 822 823 do { 824 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); 825 } while (offset & PCI_VPD_ADDR_F); 826 } 827 828 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 829 u8 *data) 830 { 831 struct skge_port *skge = netdev_priv(dev); 832 struct pci_dev *pdev = skge->hw->pdev; 833 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 834 int length = eeprom->len; 835 u16 offset = eeprom->offset; 836 837 if (!cap) 838 return -EINVAL; 839 840 eeprom->magic = SKGE_EEPROM_MAGIC; 841 842 while (length > 0) { 843 u32 val = skge_vpd_read(pdev, cap, offset); 844 int n = min_t(int, length, sizeof(val)); 845 846 memcpy(data, &val, n); 847 length -= n; 848 data += n; 849 offset += n; 850 } 851 return 0; 852 } 853 854 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, 855 u8 *data) 856 { 857 struct skge_port *skge = netdev_priv(dev); 858 struct pci_dev *pdev = skge->hw->pdev; 859 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); 860 int length = eeprom->len; 861 u16 offset = eeprom->offset; 862 863 if (!cap) 864 return -EINVAL; 865 866 if (eeprom->magic != SKGE_EEPROM_MAGIC) 867 return -EINVAL; 868 869 while (length > 0) { 870 u32 val; 871 int n = min_t(int, length, sizeof(val)); 872 873 if (n < sizeof(val)) 874 val = skge_vpd_read(pdev, cap, offset); 875 memcpy(&val, data, n); 876 877 skge_vpd_write(pdev, cap, offset, val); 878 879 length -= n; 880 data += n; 881 offset += n; 882 } 883 return 0; 884 } 885 886 static const struct ethtool_ops skge_ethtool_ops = { 887 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 888 .get_drvinfo = skge_get_drvinfo, 889 .get_regs_len = skge_get_regs_len, 890 .get_regs = skge_get_regs, 891 .get_wol = skge_get_wol, 892 .set_wol = skge_set_wol, 893 .get_msglevel = skge_get_msglevel, 894 .set_msglevel = skge_set_msglevel, 895 .nway_reset = skge_nway_reset, 896 .get_link = ethtool_op_get_link, 897 .get_eeprom_len = skge_get_eeprom_len, 898 .get_eeprom = skge_get_eeprom, 899 .set_eeprom = skge_set_eeprom, 900 .get_ringparam = skge_get_ring_param, 901 .set_ringparam = skge_set_ring_param, 902 .get_pauseparam = skge_get_pauseparam, 903 .set_pauseparam = skge_set_pauseparam, 904 .get_coalesce = skge_get_coalesce, 905 .set_coalesce = skge_set_coalesce, 906 .get_strings = skge_get_strings, 907 .set_phys_id = skge_set_phys_id, 908 .get_sset_count = skge_get_sset_count, 909 .get_ethtool_stats = skge_get_ethtool_stats, 910 .get_link_ksettings = skge_get_link_ksettings, 911 .set_link_ksettings = skge_set_link_ksettings, 912 }; 913 914 /* 915 * Allocate ring elements and chain them together 916 * One-to-one association of board descriptors with ring elements 917 */ 918 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) 919 { 920 struct skge_tx_desc *d; 921 struct skge_element *e; 922 int i; 923 924 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL); 925 if (!ring->start) 926 return -ENOMEM; 927 928 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { 929 e->desc = d; 930 if (i == ring->count - 1) { 931 e->next = ring->start; 932 d->next_offset = base; 933 } else { 934 e->next = e + 1; 935 d->next_offset = base + (i+1) * sizeof(*d); 936 } 937 } 938 ring->to_use = ring->to_clean = ring->start; 939 940 return 0; 941 } 942 943 /* Allocate and setup a new buffer for receiving */ 944 static int skge_rx_setup(struct skge_port *skge, struct skge_element *e, 945 struct sk_buff *skb, unsigned int bufsize) 946 { 947 struct skge_rx_desc *rd = e->desc; 948 dma_addr_t map; 949 950 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize, 951 DMA_FROM_DEVICE); 952 953 if (dma_mapping_error(&skge->hw->pdev->dev, map)) 954 return -1; 955 956 rd->dma_lo = lower_32_bits(map); 957 rd->dma_hi = upper_32_bits(map); 958 e->skb = skb; 959 rd->csum1_start = ETH_HLEN; 960 rd->csum2_start = ETH_HLEN; 961 rd->csum1 = 0; 962 rd->csum2 = 0; 963 964 wmb(); 965 966 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; 967 dma_unmap_addr_set(e, mapaddr, map); 968 dma_unmap_len_set(e, maplen, bufsize); 969 return 0; 970 } 971 972 /* Resume receiving using existing skb, 973 * Note: DMA address is not changed by chip. 974 * MTU not changed while receiver active. 975 */ 976 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) 977 { 978 struct skge_rx_desc *rd = e->desc; 979 980 rd->csum2 = 0; 981 rd->csum2_start = ETH_HLEN; 982 983 wmb(); 984 985 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; 986 } 987 988 989 /* Free all buffers in receive ring, assumes receiver stopped */ 990 static void skge_rx_clean(struct skge_port *skge) 991 { 992 struct skge_hw *hw = skge->hw; 993 struct skge_ring *ring = &skge->rx_ring; 994 struct skge_element *e; 995 996 e = ring->start; 997 do { 998 struct skge_rx_desc *rd = e->desc; 999 rd->control = 0; 1000 if (e->skb) { 1001 dma_unmap_single(&hw->pdev->dev, 1002 dma_unmap_addr(e, mapaddr), 1003 dma_unmap_len(e, maplen), 1004 DMA_FROM_DEVICE); 1005 dev_kfree_skb(e->skb); 1006 e->skb = NULL; 1007 } 1008 } while ((e = e->next) != ring->start); 1009 } 1010 1011 1012 /* Allocate buffers for receive ring 1013 * For receive: to_clean is next received frame. 1014 */ 1015 static int skge_rx_fill(struct net_device *dev) 1016 { 1017 struct skge_port *skge = netdev_priv(dev); 1018 struct skge_ring *ring = &skge->rx_ring; 1019 struct skge_element *e; 1020 1021 e = ring->start; 1022 do { 1023 struct sk_buff *skb; 1024 1025 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, 1026 GFP_KERNEL); 1027 if (!skb) 1028 return -ENOMEM; 1029 1030 skb_reserve(skb, NET_IP_ALIGN); 1031 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) { 1032 dev_kfree_skb(skb); 1033 return -EIO; 1034 } 1035 } while ((e = e->next) != ring->start); 1036 1037 ring->to_clean = ring->start; 1038 return 0; 1039 } 1040 1041 static const char *skge_pause(enum pause_status status) 1042 { 1043 switch (status) { 1044 case FLOW_STAT_NONE: 1045 return "none"; 1046 case FLOW_STAT_REM_SEND: 1047 return "rx only"; 1048 case FLOW_STAT_LOC_SEND: 1049 return "tx_only"; 1050 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */ 1051 return "both"; 1052 default: 1053 return "indeterminated"; 1054 } 1055 } 1056 1057 1058 static void skge_link_up(struct skge_port *skge) 1059 { 1060 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), 1061 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON); 1062 1063 netif_carrier_on(skge->netdev); 1064 netif_wake_queue(skge->netdev); 1065 1066 netif_info(skge, link, skge->netdev, 1067 "Link is up at %d Mbps, %s duplex, flow control %s\n", 1068 skge->speed, 1069 skge->duplex == DUPLEX_FULL ? "full" : "half", 1070 skge_pause(skge->flow_status)); 1071 } 1072 1073 static void skge_link_down(struct skge_port *skge) 1074 { 1075 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 1076 netif_carrier_off(skge->netdev); 1077 netif_stop_queue(skge->netdev); 1078 1079 netif_info(skge, link, skge->netdev, "Link is down\n"); 1080 } 1081 1082 static void xm_link_down(struct skge_hw *hw, int port) 1083 { 1084 struct net_device *dev = hw->dev[port]; 1085 struct skge_port *skge = netdev_priv(dev); 1086 1087 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1088 1089 if (netif_carrier_ok(dev)) 1090 skge_link_down(skge); 1091 } 1092 1093 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1094 { 1095 int i; 1096 1097 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1098 *val = xm_read16(hw, port, XM_PHY_DATA); 1099 1100 if (hw->phy_type == SK_PHY_XMAC) 1101 goto ready; 1102 1103 for (i = 0; i < PHY_RETRIES; i++) { 1104 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 1105 goto ready; 1106 udelay(1); 1107 } 1108 1109 return -ETIMEDOUT; 1110 ready: 1111 *val = xm_read16(hw, port, XM_PHY_DATA); 1112 1113 return 0; 1114 } 1115 1116 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) 1117 { 1118 u16 v = 0; 1119 if (__xm_phy_read(hw, port, reg, &v)) 1120 pr_warn("%s: phy read timed out\n", hw->dev[port]->name); 1121 return v; 1122 } 1123 1124 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1125 { 1126 int i; 1127 1128 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 1129 for (i = 0; i < PHY_RETRIES; i++) { 1130 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1131 goto ready; 1132 udelay(1); 1133 } 1134 return -EIO; 1135 1136 ready: 1137 xm_write16(hw, port, XM_PHY_DATA, val); 1138 for (i = 0; i < PHY_RETRIES; i++) { 1139 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 1140 return 0; 1141 udelay(1); 1142 } 1143 return -ETIMEDOUT; 1144 } 1145 1146 static void genesis_init(struct skge_hw *hw) 1147 { 1148 /* set blink source counter */ 1149 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); 1150 skge_write8(hw, B2_BSC_CTRL, BSC_START); 1151 1152 /* configure mac arbiter */ 1153 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1154 1155 /* configure mac arbiter timeout values */ 1156 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); 1157 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); 1158 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); 1159 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); 1160 1161 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1162 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1163 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1164 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1165 1166 /* configure packet arbiter timeout */ 1167 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); 1168 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 1169 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 1170 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 1171 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 1172 } 1173 1174 static void genesis_reset(struct skge_hw *hw, int port) 1175 { 1176 static const u8 zero[8] = { 0 }; 1177 u32 reg; 1178 1179 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 1180 1181 /* reset the statistics module */ 1182 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 1183 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 1184 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 1185 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 1186 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 1187 1188 /* disable Broadcom PHY IRQ */ 1189 if (hw->phy_type == SK_PHY_BCOM) 1190 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 1191 1192 xm_outhash(hw, port, XM_HSM, zero); 1193 1194 /* Flush TX and RX fifo */ 1195 reg = xm_read32(hw, port, XM_MODE); 1196 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); 1197 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); 1198 } 1199 1200 /* Convert mode to MII values */ 1201 static const u16 phy_pause_map[] = { 1202 [FLOW_MODE_NONE] = 0, 1203 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, 1204 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, 1205 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, 1206 }; 1207 1208 /* special defines for FIBER (88E1011S only) */ 1209 static const u16 fiber_pause_map[] = { 1210 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE, 1211 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD, 1212 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD, 1213 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD, 1214 }; 1215 1216 1217 /* Check status of Broadcom phy link */ 1218 static void bcom_check_link(struct skge_hw *hw, int port) 1219 { 1220 struct net_device *dev = hw->dev[port]; 1221 struct skge_port *skge = netdev_priv(dev); 1222 u16 status; 1223 1224 /* read twice because of latch */ 1225 xm_phy_read(hw, port, PHY_BCOM_STAT); 1226 status = xm_phy_read(hw, port, PHY_BCOM_STAT); 1227 1228 if ((status & PHY_ST_LSYNC) == 0) { 1229 xm_link_down(hw, port); 1230 return; 1231 } 1232 1233 if (skge->autoneg == AUTONEG_ENABLE) { 1234 u16 lpa, aux; 1235 1236 if (!(status & PHY_ST_AN_OVER)) 1237 return; 1238 1239 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1240 if (lpa & PHY_B_AN_RF) { 1241 netdev_notice(dev, "remote fault\n"); 1242 return; 1243 } 1244 1245 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); 1246 1247 /* Check Duplex mismatch */ 1248 switch (aux & PHY_B_AS_AN_RES_MSK) { 1249 case PHY_B_RES_1000FD: 1250 skge->duplex = DUPLEX_FULL; 1251 break; 1252 case PHY_B_RES_1000HD: 1253 skge->duplex = DUPLEX_HALF; 1254 break; 1255 default: 1256 netdev_notice(dev, "duplex mismatch\n"); 1257 return; 1258 } 1259 1260 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1261 switch (aux & PHY_B_AS_PAUSE_MSK) { 1262 case PHY_B_AS_PAUSE_MSK: 1263 skge->flow_status = FLOW_STAT_SYMMETRIC; 1264 break; 1265 case PHY_B_AS_PRR: 1266 skge->flow_status = FLOW_STAT_REM_SEND; 1267 break; 1268 case PHY_B_AS_PRT: 1269 skge->flow_status = FLOW_STAT_LOC_SEND; 1270 break; 1271 default: 1272 skge->flow_status = FLOW_STAT_NONE; 1273 } 1274 skge->speed = SPEED_1000; 1275 } 1276 1277 if (!netif_carrier_ok(dev)) 1278 genesis_link_up(skge); 1279 } 1280 1281 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional 1282 * Phy on for 100 or 10Mbit operation 1283 */ 1284 static void bcom_phy_init(struct skge_port *skge) 1285 { 1286 struct skge_hw *hw = skge->hw; 1287 int port = skge->port; 1288 int i; 1289 u16 id1, r, ext, ctl; 1290 1291 /* magic workaround patterns for Broadcom */ 1292 static const struct { 1293 u16 reg; 1294 u16 val; 1295 } A1hack[] = { 1296 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, 1297 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, 1298 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, 1299 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 1300 }, C0hack[] = { 1301 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, 1302 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, 1303 }; 1304 1305 /* read Id from external PHY (all have the same address) */ 1306 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); 1307 1308 /* Optimize MDIO transfer by suppressing preamble. */ 1309 r = xm_read16(hw, port, XM_MMU_CMD); 1310 r |= XM_MMU_NO_PRE; 1311 xm_write16(hw, port, XM_MMU_CMD, r); 1312 1313 switch (id1) { 1314 case PHY_BCOM_ID1_C0: 1315 /* 1316 * Workaround BCOM Errata for the C0 type. 1317 * Write magic patterns to reserved registers. 1318 */ 1319 for (i = 0; i < ARRAY_SIZE(C0hack); i++) 1320 xm_phy_write(hw, port, 1321 C0hack[i].reg, C0hack[i].val); 1322 1323 break; 1324 case PHY_BCOM_ID1_A1: 1325 /* 1326 * Workaround BCOM Errata for the A1 type. 1327 * Write magic patterns to reserved registers. 1328 */ 1329 for (i = 0; i < ARRAY_SIZE(A1hack); i++) 1330 xm_phy_write(hw, port, 1331 A1hack[i].reg, A1hack[i].val); 1332 break; 1333 } 1334 1335 /* 1336 * Workaround BCOM Errata (#10523) for all BCom PHYs. 1337 * Disable Power Management after reset. 1338 */ 1339 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); 1340 r |= PHY_B_AC_DIS_PM; 1341 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); 1342 1343 /* Dummy read */ 1344 xm_read16(hw, port, XM_ISRC); 1345 1346 ext = PHY_B_PEC_EN_LTR; /* enable tx led */ 1347 ctl = PHY_CT_SP1000; /* always 1000mbit */ 1348 1349 if (skge->autoneg == AUTONEG_ENABLE) { 1350 /* 1351 * Workaround BCOM Errata #1 for the C5 type. 1352 * 1000Base-T Link Acquisition Failure in Slave Mode 1353 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register 1354 */ 1355 u16 adv = PHY_B_1000C_RD; 1356 if (skge->advertising & ADVERTISED_1000baseT_Half) 1357 adv |= PHY_B_1000C_AHD; 1358 if (skge->advertising & ADVERTISED_1000baseT_Full) 1359 adv |= PHY_B_1000C_AFD; 1360 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); 1361 1362 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; 1363 } else { 1364 if (skge->duplex == DUPLEX_FULL) 1365 ctl |= PHY_CT_DUP_MD; 1366 /* Force to slave */ 1367 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); 1368 } 1369 1370 /* Set autonegotiation pause parameters */ 1371 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, 1372 phy_pause_map[skge->flow_control] | PHY_AN_CSMA); 1373 1374 /* Handle Jumbo frames */ 1375 if (hw->dev[port]->mtu > ETH_DATA_LEN) { 1376 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1377 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); 1378 1379 ext |= PHY_B_PEC_HIGH_LA; 1380 1381 } 1382 1383 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); 1384 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); 1385 1386 /* Use link status change interrupt */ 1387 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1388 } 1389 1390 static void xm_phy_init(struct skge_port *skge) 1391 { 1392 struct skge_hw *hw = skge->hw; 1393 int port = skge->port; 1394 u16 ctrl = 0; 1395 1396 if (skge->autoneg == AUTONEG_ENABLE) { 1397 if (skge->advertising & ADVERTISED_1000baseT_Half) 1398 ctrl |= PHY_X_AN_HD; 1399 if (skge->advertising & ADVERTISED_1000baseT_Full) 1400 ctrl |= PHY_X_AN_FD; 1401 1402 ctrl |= fiber_pause_map[skge->flow_control]; 1403 1404 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); 1405 1406 /* Restart Auto-negotiation */ 1407 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; 1408 } else { 1409 /* Set DuplexMode in Config register */ 1410 if (skge->duplex == DUPLEX_FULL) 1411 ctrl |= PHY_CT_DUP_MD; 1412 /* 1413 * Do NOT enable Auto-negotiation here. This would hold 1414 * the link down because no IDLEs are transmitted 1415 */ 1416 } 1417 1418 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); 1419 1420 /* Poll PHY for status changes */ 1421 mod_timer(&skge->link_timer, jiffies + LINK_HZ); 1422 } 1423 1424 static int xm_check_link(struct net_device *dev) 1425 { 1426 struct skge_port *skge = netdev_priv(dev); 1427 struct skge_hw *hw = skge->hw; 1428 int port = skge->port; 1429 u16 status; 1430 1431 /* read twice because of latch */ 1432 xm_phy_read(hw, port, PHY_XMAC_STAT); 1433 status = xm_phy_read(hw, port, PHY_XMAC_STAT); 1434 1435 if ((status & PHY_ST_LSYNC) == 0) { 1436 xm_link_down(hw, port); 1437 return 0; 1438 } 1439 1440 if (skge->autoneg == AUTONEG_ENABLE) { 1441 u16 lpa, res; 1442 1443 if (!(status & PHY_ST_AN_OVER)) 1444 return 0; 1445 1446 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 1447 if (lpa & PHY_B_AN_RF) { 1448 netdev_notice(dev, "remote fault\n"); 1449 return 0; 1450 } 1451 1452 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); 1453 1454 /* Check Duplex mismatch */ 1455 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { 1456 case PHY_X_RS_FD: 1457 skge->duplex = DUPLEX_FULL; 1458 break; 1459 case PHY_X_RS_HD: 1460 skge->duplex = DUPLEX_HALF; 1461 break; 1462 default: 1463 netdev_notice(dev, "duplex mismatch\n"); 1464 return 0; 1465 } 1466 1467 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 1468 if ((skge->flow_control == FLOW_MODE_SYMMETRIC || 1469 skge->flow_control == FLOW_MODE_SYM_OR_REM) && 1470 (lpa & PHY_X_P_SYM_MD)) 1471 skge->flow_status = FLOW_STAT_SYMMETRIC; 1472 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && 1473 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) 1474 /* Enable PAUSE receive, disable PAUSE transmit */ 1475 skge->flow_status = FLOW_STAT_REM_SEND; 1476 else if (skge->flow_control == FLOW_MODE_LOC_SEND && 1477 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) 1478 /* Disable PAUSE receive, enable PAUSE transmit */ 1479 skge->flow_status = FLOW_STAT_LOC_SEND; 1480 else 1481 skge->flow_status = FLOW_STAT_NONE; 1482 1483 skge->speed = SPEED_1000; 1484 } 1485 1486 if (!netif_carrier_ok(dev)) 1487 genesis_link_up(skge); 1488 return 1; 1489 } 1490 1491 /* Poll to check for link coming up. 1492 * 1493 * Since internal PHY is wired to a level triggered pin, can't 1494 * get an interrupt when carrier is detected, need to poll for 1495 * link coming up. 1496 */ 1497 static void xm_link_timer(struct timer_list *t) 1498 { 1499 struct skge_port *skge = from_timer(skge, t, link_timer); 1500 struct net_device *dev = skge->netdev; 1501 struct skge_hw *hw = skge->hw; 1502 int port = skge->port; 1503 int i; 1504 unsigned long flags; 1505 1506 if (!netif_running(dev)) 1507 return; 1508 1509 spin_lock_irqsave(&hw->phy_lock, flags); 1510 1511 /* 1512 * Verify that the link by checking GPIO register three times. 1513 * This pin has the signal from the link_sync pin connected to it. 1514 */ 1515 for (i = 0; i < 3; i++) { 1516 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) 1517 goto link_down; 1518 } 1519 1520 /* Re-enable interrupt to detect link down */ 1521 if (xm_check_link(dev)) { 1522 u16 msk = xm_read16(hw, port, XM_IMSK); 1523 msk &= ~XM_IS_INP_ASS; 1524 xm_write16(hw, port, XM_IMSK, msk); 1525 xm_read16(hw, port, XM_ISRC); 1526 } else { 1527 link_down: 1528 mod_timer(&skge->link_timer, 1529 round_jiffies(jiffies + LINK_HZ)); 1530 } 1531 spin_unlock_irqrestore(&hw->phy_lock, flags); 1532 } 1533 1534 static void genesis_mac_init(struct skge_hw *hw, int port) 1535 { 1536 struct net_device *dev = hw->dev[port]; 1537 struct skge_port *skge = netdev_priv(dev); 1538 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; 1539 int i; 1540 u32 r; 1541 static const u8 zero[6] = { 0 }; 1542 1543 for (i = 0; i < 10; i++) { 1544 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 1545 MFF_SET_MAC_RST); 1546 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) 1547 goto reset_ok; 1548 udelay(1); 1549 } 1550 1551 netdev_warn(dev, "genesis reset failed\n"); 1552 1553 reset_ok: 1554 /* Unreset the XMAC. */ 1555 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1556 1557 /* 1558 * Perform additional initialization for external PHYs, 1559 * namely for the 1000baseTX cards that use the XMAC's 1560 * GMII mode. 1561 */ 1562 if (hw->phy_type != SK_PHY_XMAC) { 1563 /* Take external Phy out of reset */ 1564 r = skge_read32(hw, B2_GP_IO); 1565 if (port == 0) 1566 r |= GP_DIR_0|GP_IO_0; 1567 else 1568 r |= GP_DIR_2|GP_IO_2; 1569 1570 skge_write32(hw, B2_GP_IO, r); 1571 1572 /* Enable GMII interface */ 1573 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1574 } 1575 1576 1577 switch (hw->phy_type) { 1578 case SK_PHY_XMAC: 1579 xm_phy_init(skge); 1580 break; 1581 case SK_PHY_BCOM: 1582 bcom_phy_init(skge); 1583 bcom_check_link(hw, port); 1584 } 1585 1586 /* Set Station Address */ 1587 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 1588 1589 /* We don't use match addresses so clear */ 1590 for (i = 1; i < 16; i++) 1591 xm_outaddr(hw, port, XM_EXM(i), zero); 1592 1593 /* Clear MIB counters */ 1594 xm_write16(hw, port, XM_STAT_CMD, 1595 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1596 /* Clear two times according to Errata #3 */ 1597 xm_write16(hw, port, XM_STAT_CMD, 1598 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 1599 1600 /* configure Rx High Water Mark (XM_RX_HI_WM) */ 1601 xm_write16(hw, port, XM_RX_HI_WM, 1450); 1602 1603 /* We don't need the FCS appended to the packet. */ 1604 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; 1605 if (jumbo) 1606 r |= XM_RX_BIG_PK_OK; 1607 1608 if (skge->duplex == DUPLEX_HALF) { 1609 /* 1610 * If in manual half duplex mode the other side might be in 1611 * full duplex mode, so ignore if a carrier extension is not seen 1612 * on frames received 1613 */ 1614 r |= XM_RX_DIS_CEXT; 1615 } 1616 xm_write16(hw, port, XM_RX_CMD, r); 1617 1618 /* We want short frames padded to 60 bytes. */ 1619 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); 1620 1621 /* Increase threshold for jumbo frames on dual port */ 1622 if (hw->ports > 1 && jumbo) 1623 xm_write16(hw, port, XM_TX_THR, 1020); 1624 else 1625 xm_write16(hw, port, XM_TX_THR, 512); 1626 1627 /* 1628 * Enable the reception of all error frames. This is 1629 * a necessary evil due to the design of the XMAC. The 1630 * XMAC's receive FIFO is only 8K in size, however jumbo 1631 * frames can be up to 9000 bytes in length. When bad 1632 * frame filtering is enabled, the XMAC's RX FIFO operates 1633 * in 'store and forward' mode. For this to work, the 1634 * entire frame has to fit into the FIFO, but that means 1635 * that jumbo frames larger than 8192 bytes will be 1636 * truncated. Disabling all bad frame filtering causes 1637 * the RX FIFO to operate in streaming mode, in which 1638 * case the XMAC will start transferring frames out of the 1639 * RX FIFO as soon as the FIFO threshold is reached. 1640 */ 1641 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); 1642 1643 1644 /* 1645 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) 1646 * - Enable all bits excepting 'Octets Rx OK Low CntOv' 1647 * and 'Octets Rx OK Hi Cnt Ov'. 1648 */ 1649 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); 1650 1651 /* 1652 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) 1653 * - Enable all bits excepting 'Octets Tx OK Low CntOv' 1654 * and 'Octets Tx OK Hi Cnt Ov'. 1655 */ 1656 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); 1657 1658 /* Configure MAC arbiter */ 1659 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 1660 1661 /* configure timeout values */ 1662 skge_write8(hw, B3_MA_TOINI_RX1, 72); 1663 skge_write8(hw, B3_MA_TOINI_RX2, 72); 1664 skge_write8(hw, B3_MA_TOINI_TX1, 72); 1665 skge_write8(hw, B3_MA_TOINI_TX2, 72); 1666 1667 skge_write8(hw, B3_MA_RCINI_RX1, 0); 1668 skge_write8(hw, B3_MA_RCINI_RX2, 0); 1669 skge_write8(hw, B3_MA_RCINI_TX1, 0); 1670 skge_write8(hw, B3_MA_RCINI_TX2, 0); 1671 1672 /* Configure Rx MAC FIFO */ 1673 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 1674 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 1675 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 1676 1677 /* Configure Tx MAC FIFO */ 1678 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 1679 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 1680 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 1681 1682 if (jumbo) { 1683 /* Enable frame flushing if jumbo frames used */ 1684 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH); 1685 } else { 1686 /* enable timeout timers if normal frames */ 1687 skge_write16(hw, B3_PA_CTRL, 1688 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); 1689 } 1690 } 1691 1692 static void genesis_stop(struct skge_port *skge) 1693 { 1694 struct skge_hw *hw = skge->hw; 1695 int port = skge->port; 1696 unsigned retries = 1000; 1697 u16 cmd; 1698 1699 /* Disable Tx and Rx */ 1700 cmd = xm_read16(hw, port, XM_MMU_CMD); 1701 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1702 xm_write16(hw, port, XM_MMU_CMD, cmd); 1703 1704 genesis_reset(hw, port); 1705 1706 /* Clear Tx packet arbiter timeout IRQ */ 1707 skge_write16(hw, B3_PA_CTRL, 1708 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); 1709 1710 /* Reset the MAC */ 1711 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 1712 do { 1713 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 1714 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) 1715 break; 1716 } while (--retries > 0); 1717 1718 /* For external PHYs there must be special handling */ 1719 if (hw->phy_type != SK_PHY_XMAC) { 1720 u32 reg = skge_read32(hw, B2_GP_IO); 1721 if (port == 0) { 1722 reg |= GP_DIR_0; 1723 reg &= ~GP_IO_0; 1724 } else { 1725 reg |= GP_DIR_2; 1726 reg &= ~GP_IO_2; 1727 } 1728 skge_write32(hw, B2_GP_IO, reg); 1729 skge_read32(hw, B2_GP_IO); 1730 } 1731 1732 xm_write16(hw, port, XM_MMU_CMD, 1733 xm_read16(hw, port, XM_MMU_CMD) 1734 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 1735 1736 xm_read16(hw, port, XM_MMU_CMD); 1737 } 1738 1739 1740 static void genesis_get_stats(struct skge_port *skge, u64 *data) 1741 { 1742 struct skge_hw *hw = skge->hw; 1743 int port = skge->port; 1744 int i; 1745 unsigned long timeout = jiffies + HZ; 1746 1747 xm_write16(hw, port, 1748 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); 1749 1750 /* wait for update to complete */ 1751 while (xm_read16(hw, port, XM_STAT_CMD) 1752 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { 1753 if (time_after(jiffies, timeout)) 1754 break; 1755 udelay(10); 1756 } 1757 1758 /* special case for 64 bit octet counter */ 1759 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 1760 | xm_read32(hw, port, XM_TXO_OK_LO); 1761 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 1762 | xm_read32(hw, port, XM_RXO_OK_LO); 1763 1764 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 1765 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); 1766 } 1767 1768 static void genesis_mac_intr(struct skge_hw *hw, int port) 1769 { 1770 struct net_device *dev = hw->dev[port]; 1771 struct skge_port *skge = netdev_priv(dev); 1772 u16 status = xm_read16(hw, port, XM_ISRC); 1773 1774 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1775 "mac interrupt status 0x%x\n", status); 1776 1777 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) { 1778 xm_link_down(hw, port); 1779 mod_timer(&skge->link_timer, jiffies + 1); 1780 } 1781 1782 if (status & XM_IS_TXF_UR) { 1783 xm_write32(hw, port, XM_MODE, XM_MD_FTF); 1784 ++dev->stats.tx_fifo_errors; 1785 } 1786 } 1787 1788 static void genesis_link_up(struct skge_port *skge) 1789 { 1790 struct skge_hw *hw = skge->hw; 1791 int port = skge->port; 1792 u16 cmd, msk; 1793 u32 mode; 1794 1795 cmd = xm_read16(hw, port, XM_MMU_CMD); 1796 1797 /* 1798 * enabling pause frame reception is required for 1000BT 1799 * because the XMAC is not reset if the link is going down 1800 */ 1801 if (skge->flow_status == FLOW_STAT_NONE || 1802 skge->flow_status == FLOW_STAT_LOC_SEND) 1803 /* Disable Pause Frame Reception */ 1804 cmd |= XM_MMU_IGN_PF; 1805 else 1806 /* Enable Pause Frame Reception */ 1807 cmd &= ~XM_MMU_IGN_PF; 1808 1809 xm_write16(hw, port, XM_MMU_CMD, cmd); 1810 1811 mode = xm_read32(hw, port, XM_MODE); 1812 if (skge->flow_status == FLOW_STAT_SYMMETRIC || 1813 skge->flow_status == FLOW_STAT_LOC_SEND) { 1814 /* 1815 * Configure Pause Frame Generation 1816 * Use internal and external Pause Frame Generation. 1817 * Sending pause frames is edge triggered. 1818 * Send a Pause frame with the maximum pause time if 1819 * internal oder external FIFO full condition occurs. 1820 * Send a zero pause time frame to re-start transmission. 1821 */ 1822 /* XM_PAUSE_DA = '010000C28001' (default) */ 1823 /* XM_MAC_PTIME = 0xffff (maximum) */ 1824 /* remember this value is defined in big endian (!) */ 1825 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 1826 1827 mode |= XM_PAUSE_MODE; 1828 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 1829 } else { 1830 /* 1831 * disable pause frame generation is required for 1000BT 1832 * because the XMAC is not reset if the link is going down 1833 */ 1834 /* Disable Pause Mode in Mode Register */ 1835 mode &= ~XM_PAUSE_MODE; 1836 1837 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 1838 } 1839 1840 xm_write32(hw, port, XM_MODE, mode); 1841 1842 /* Turn on detection of Tx underrun */ 1843 msk = xm_read16(hw, port, XM_IMSK); 1844 msk &= ~XM_IS_TXF_UR; 1845 xm_write16(hw, port, XM_IMSK, msk); 1846 1847 xm_read16(hw, port, XM_ISRC); 1848 1849 /* get MMU Command Reg. */ 1850 cmd = xm_read16(hw, port, XM_MMU_CMD); 1851 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 1852 cmd |= XM_MMU_GMII_FD; 1853 1854 /* 1855 * Workaround BCOM Errata (#10523) for all BCom Phys 1856 * Enable Power Management after link up 1857 */ 1858 if (hw->phy_type == SK_PHY_BCOM) { 1859 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 1860 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 1861 & ~PHY_B_AC_DIS_PM); 1862 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1863 } 1864 1865 /* enable Rx/Tx */ 1866 xm_write16(hw, port, XM_MMU_CMD, 1867 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 1868 skge_link_up(skge); 1869 } 1870 1871 1872 static inline void bcom_phy_intr(struct skge_port *skge) 1873 { 1874 struct skge_hw *hw = skge->hw; 1875 int port = skge->port; 1876 u16 isrc; 1877 1878 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 1879 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 1880 "phy interrupt status 0x%x\n", isrc); 1881 1882 if (isrc & PHY_B_IS_PSE) 1883 pr_err("%s: uncorrectable pair swap error\n", 1884 hw->dev[port]->name); 1885 1886 /* Workaround BCom Errata: 1887 * enable and disable loopback mode if "NO HCD" occurs. 1888 */ 1889 if (isrc & PHY_B_IS_NO_HDCL) { 1890 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); 1891 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1892 ctrl | PHY_CT_LOOP); 1893 xm_phy_write(hw, port, PHY_BCOM_CTRL, 1894 ctrl & ~PHY_CT_LOOP); 1895 } 1896 1897 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 1898 bcom_check_link(hw, port); 1899 1900 } 1901 1902 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) 1903 { 1904 int i; 1905 1906 gma_write16(hw, port, GM_SMI_DATA, val); 1907 gma_write16(hw, port, GM_SMI_CTRL, 1908 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 1909 for (i = 0; i < PHY_RETRIES; i++) { 1910 udelay(1); 1911 1912 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 1913 return 0; 1914 } 1915 1916 pr_warn("%s: phy write timeout\n", hw->dev[port]->name); 1917 return -EIO; 1918 } 1919 1920 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) 1921 { 1922 int i; 1923 1924 gma_write16(hw, port, GM_SMI_CTRL, 1925 GM_SMI_CT_PHY_AD(hw->phy_addr) 1926 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 1927 1928 for (i = 0; i < PHY_RETRIES; i++) { 1929 udelay(1); 1930 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 1931 goto ready; 1932 } 1933 1934 return -ETIMEDOUT; 1935 ready: 1936 *val = gma_read16(hw, port, GM_SMI_DATA); 1937 return 0; 1938 } 1939 1940 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) 1941 { 1942 u16 v = 0; 1943 if (__gm_phy_read(hw, port, reg, &v)) 1944 pr_warn("%s: phy read timeout\n", hw->dev[port]->name); 1945 return v; 1946 } 1947 1948 /* Marvell Phy Initialization */ 1949 static void yukon_init(struct skge_hw *hw, int port) 1950 { 1951 struct skge_port *skge = netdev_priv(hw->dev[port]); 1952 u16 ctrl, ct1000, adv; 1953 1954 if (skge->autoneg == AUTONEG_ENABLE) { 1955 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 1956 1957 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 1958 PHY_M_EC_MAC_S_MSK); 1959 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 1960 1961 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 1962 1963 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 1964 } 1965 1966 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 1967 if (skge->autoneg == AUTONEG_DISABLE) 1968 ctrl &= ~PHY_CT_ANE; 1969 1970 ctrl |= PHY_CT_RESET; 1971 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 1972 1973 ctrl = 0; 1974 ct1000 = 0; 1975 adv = PHY_AN_CSMA; 1976 1977 if (skge->autoneg == AUTONEG_ENABLE) { 1978 if (hw->copper) { 1979 if (skge->advertising & ADVERTISED_1000baseT_Full) 1980 ct1000 |= PHY_M_1000C_AFD; 1981 if (skge->advertising & ADVERTISED_1000baseT_Half) 1982 ct1000 |= PHY_M_1000C_AHD; 1983 if (skge->advertising & ADVERTISED_100baseT_Full) 1984 adv |= PHY_M_AN_100_FD; 1985 if (skge->advertising & ADVERTISED_100baseT_Half) 1986 adv |= PHY_M_AN_100_HD; 1987 if (skge->advertising & ADVERTISED_10baseT_Full) 1988 adv |= PHY_M_AN_10_FD; 1989 if (skge->advertising & ADVERTISED_10baseT_Half) 1990 adv |= PHY_M_AN_10_HD; 1991 1992 /* Set Flow-control capabilities */ 1993 adv |= phy_pause_map[skge->flow_control]; 1994 } else { 1995 if (skge->advertising & ADVERTISED_1000baseT_Full) 1996 adv |= PHY_M_AN_1000X_AFD; 1997 if (skge->advertising & ADVERTISED_1000baseT_Half) 1998 adv |= PHY_M_AN_1000X_AHD; 1999 2000 adv |= fiber_pause_map[skge->flow_control]; 2001 } 2002 2003 /* Restart Auto-negotiation */ 2004 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 2005 } else { 2006 /* forced speed/duplex settings */ 2007 ct1000 = PHY_M_1000C_MSE; 2008 2009 if (skge->duplex == DUPLEX_FULL) 2010 ctrl |= PHY_CT_DUP_MD; 2011 2012 switch (skge->speed) { 2013 case SPEED_1000: 2014 ctrl |= PHY_CT_SP1000; 2015 break; 2016 case SPEED_100: 2017 ctrl |= PHY_CT_SP100; 2018 break; 2019 } 2020 2021 ctrl |= PHY_CT_RESET; 2022 } 2023 2024 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 2025 2026 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 2027 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2028 2029 /* Enable phy interrupt on autonegotiation complete (or link up) */ 2030 if (skge->autoneg == AUTONEG_ENABLE) 2031 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); 2032 else 2033 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2034 } 2035 2036 static void yukon_reset(struct skge_hw *hw, int port) 2037 { 2038 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 2039 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 2040 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 2041 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 2042 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 2043 2044 gma_write16(hw, port, GM_RX_CTRL, 2045 gma_read16(hw, port, GM_RX_CTRL) 2046 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2047 } 2048 2049 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ 2050 static int is_yukon_lite_a0(struct skge_hw *hw) 2051 { 2052 u32 reg; 2053 int ret; 2054 2055 if (hw->chip_id != CHIP_ID_YUKON) 2056 return 0; 2057 2058 reg = skge_read32(hw, B2_FAR); 2059 skge_write8(hw, B2_FAR + 3, 0xff); 2060 ret = (skge_read8(hw, B2_FAR + 3) != 0); 2061 skge_write32(hw, B2_FAR, reg); 2062 return ret; 2063 } 2064 2065 static void yukon_mac_init(struct skge_hw *hw, int port) 2066 { 2067 struct skge_port *skge = netdev_priv(hw->dev[port]); 2068 int i; 2069 u32 reg; 2070 const u8 *addr = hw->dev[port]->dev_addr; 2071 2072 /* WA code for COMA mode -- set PHY reset */ 2073 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2074 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2075 reg = skge_read32(hw, B2_GP_IO); 2076 reg |= GP_DIR_9 | GP_IO_9; 2077 skge_write32(hw, B2_GP_IO, reg); 2078 } 2079 2080 /* hard reset */ 2081 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2082 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2083 2084 /* WA code for COMA mode -- clear PHY reset */ 2085 if (hw->chip_id == CHIP_ID_YUKON_LITE && 2086 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 2087 reg = skge_read32(hw, B2_GP_IO); 2088 reg |= GP_DIR_9; 2089 reg &= ~GP_IO_9; 2090 skge_write32(hw, B2_GP_IO, reg); 2091 } 2092 2093 /* Set hardware config mode */ 2094 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | 2095 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; 2096 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 2097 2098 /* Clear GMC reset */ 2099 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 2100 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 2101 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 2102 2103 if (skge->autoneg == AUTONEG_DISABLE) { 2104 reg = GM_GPCR_AU_ALL_DIS; 2105 gma_write16(hw, port, GM_GP_CTRL, 2106 gma_read16(hw, port, GM_GP_CTRL) | reg); 2107 2108 switch (skge->speed) { 2109 case SPEED_1000: 2110 reg &= ~GM_GPCR_SPEED_100; 2111 reg |= GM_GPCR_SPEED_1000; 2112 break; 2113 case SPEED_100: 2114 reg &= ~GM_GPCR_SPEED_1000; 2115 reg |= GM_GPCR_SPEED_100; 2116 break; 2117 case SPEED_10: 2118 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 2119 break; 2120 } 2121 2122 if (skge->duplex == DUPLEX_FULL) 2123 reg |= GM_GPCR_DUP_FULL; 2124 } else 2125 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 2126 2127 switch (skge->flow_control) { 2128 case FLOW_MODE_NONE: 2129 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2130 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2131 break; 2132 case FLOW_MODE_LOC_SEND: 2133 /* disable Rx flow-control */ 2134 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 2135 break; 2136 case FLOW_MODE_SYMMETRIC: 2137 case FLOW_MODE_SYM_OR_REM: 2138 /* enable Tx & Rx flow-control */ 2139 break; 2140 } 2141 2142 gma_write16(hw, port, GM_GP_CTRL, reg); 2143 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 2144 2145 yukon_init(hw, port); 2146 2147 /* MIB clear */ 2148 reg = gma_read16(hw, port, GM_PHY_ADDR); 2149 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 2150 2151 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 2152 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 2153 gma_write16(hw, port, GM_PHY_ADDR, reg); 2154 2155 /* transmit control */ 2156 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 2157 2158 /* receive control reg: unicast + multicast + no FCS */ 2159 gma_write16(hw, port, GM_RX_CTRL, 2160 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 2161 2162 /* transmit flow control */ 2163 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 2164 2165 /* transmit parameter */ 2166 gma_write16(hw, port, GM_TX_PARAM, 2167 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 2168 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 2169 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 2170 2171 /* configure the Serial Mode Register */ 2172 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) 2173 | GM_SMOD_VLAN_ENA 2174 | IPG_DATA_VAL(IPG_DATA_DEF); 2175 2176 if (hw->dev[port]->mtu > ETH_DATA_LEN) 2177 reg |= GM_SMOD_JUMBO_ENA; 2178 2179 gma_write16(hw, port, GM_SERIAL_MODE, reg); 2180 2181 /* physical address: used for pause frames */ 2182 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 2183 /* virtual address for data */ 2184 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 2185 2186 /* enable interrupt mask for counter overflows */ 2187 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 2188 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 2189 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 2190 2191 /* Initialize Mac Fifo */ 2192 2193 /* Configure Rx MAC FIFO */ 2194 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 2195 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 2196 2197 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ 2198 if (is_yukon_lite_a0(hw)) 2199 reg &= ~GMF_RX_F_FL_ON; 2200 2201 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 2202 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); 2203 /* 2204 * because Pause Packet Truncation in GMAC is not working 2205 * we have to increase the Flush Threshold to 64 bytes 2206 * in order to flush pause packets in Rx FIFO on Yukon-1 2207 */ 2208 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); 2209 2210 /* Configure Tx MAC FIFO */ 2211 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 2212 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 2213 } 2214 2215 /* Go into power down mode */ 2216 static void yukon_suspend(struct skge_hw *hw, int port) 2217 { 2218 u16 ctrl; 2219 2220 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 2221 ctrl |= PHY_M_PC_POL_R_DIS; 2222 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 2223 2224 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2225 ctrl |= PHY_CT_RESET; 2226 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2227 2228 /* switch IEEE compatible power down mode on */ 2229 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 2230 ctrl |= PHY_CT_PDOWN; 2231 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 2232 } 2233 2234 static void yukon_stop(struct skge_port *skge) 2235 { 2236 struct skge_hw *hw = skge->hw; 2237 int port = skge->port; 2238 2239 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 2240 yukon_reset(hw, port); 2241 2242 gma_write16(hw, port, GM_GP_CTRL, 2243 gma_read16(hw, port, GM_GP_CTRL) 2244 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); 2245 gma_read16(hw, port, GM_GP_CTRL); 2246 2247 yukon_suspend(hw, port); 2248 2249 /* set GPHY Control reset */ 2250 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 2251 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 2252 } 2253 2254 static void yukon_get_stats(struct skge_port *skge, u64 *data) 2255 { 2256 struct skge_hw *hw = skge->hw; 2257 int port = skge->port; 2258 int i; 2259 2260 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 2261 | gma_read32(hw, port, GM_TXO_OK_LO); 2262 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 2263 | gma_read32(hw, port, GM_RXO_OK_LO); 2264 2265 for (i = 2; i < ARRAY_SIZE(skge_stats); i++) 2266 data[i] = gma_read32(hw, port, 2267 skge_stats[i].gma_offset); 2268 } 2269 2270 static void yukon_mac_intr(struct skge_hw *hw, int port) 2271 { 2272 struct net_device *dev = hw->dev[port]; 2273 struct skge_port *skge = netdev_priv(dev); 2274 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 2275 2276 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2277 "mac interrupt status 0x%x\n", status); 2278 2279 if (status & GM_IS_RX_FF_OR) { 2280 ++dev->stats.rx_fifo_errors; 2281 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2282 } 2283 2284 if (status & GM_IS_TX_FF_UR) { 2285 ++dev->stats.tx_fifo_errors; 2286 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2287 } 2288 2289 } 2290 2291 static u16 yukon_speed(const struct skge_hw *hw, u16 aux) 2292 { 2293 switch (aux & PHY_M_PS_SPEED_MSK) { 2294 case PHY_M_PS_SPEED_1000: 2295 return SPEED_1000; 2296 case PHY_M_PS_SPEED_100: 2297 return SPEED_100; 2298 default: 2299 return SPEED_10; 2300 } 2301 } 2302 2303 static void yukon_link_up(struct skge_port *skge) 2304 { 2305 struct skge_hw *hw = skge->hw; 2306 int port = skge->port; 2307 u16 reg; 2308 2309 /* Enable Transmit FIFO Underrun */ 2310 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 2311 2312 reg = gma_read16(hw, port, GM_GP_CTRL); 2313 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 2314 reg |= GM_GPCR_DUP_FULL; 2315 2316 /* enable Rx/Tx */ 2317 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 2318 gma_write16(hw, port, GM_GP_CTRL, reg); 2319 2320 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 2321 skge_link_up(skge); 2322 } 2323 2324 static void yukon_link_down(struct skge_port *skge) 2325 { 2326 struct skge_hw *hw = skge->hw; 2327 int port = skge->port; 2328 u16 ctrl; 2329 2330 ctrl = gma_read16(hw, port, GM_GP_CTRL); 2331 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2332 gma_write16(hw, port, GM_GP_CTRL, ctrl); 2333 2334 if (skge->flow_status == FLOW_STAT_REM_SEND) { 2335 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 2336 ctrl |= PHY_M_AN_ASP; 2337 /* restore Asymmetric Pause bit */ 2338 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); 2339 } 2340 2341 skge_link_down(skge); 2342 2343 yukon_init(hw, port); 2344 } 2345 2346 static void yukon_phy_intr(struct skge_port *skge) 2347 { 2348 struct skge_hw *hw = skge->hw; 2349 int port = skge->port; 2350 const char *reason = NULL; 2351 u16 istatus, phystat; 2352 2353 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 2354 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 2355 2356 netif_printk(skge, intr, KERN_DEBUG, skge->netdev, 2357 "phy interrupt status 0x%x 0x%x\n", istatus, phystat); 2358 2359 if (istatus & PHY_M_IS_AN_COMPL) { 2360 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 2361 & PHY_M_AN_RF) { 2362 reason = "remote fault"; 2363 goto failed; 2364 } 2365 2366 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { 2367 reason = "master/slave fault"; 2368 goto failed; 2369 } 2370 2371 if (!(phystat & PHY_M_PS_SPDUP_RES)) { 2372 reason = "speed/duplex"; 2373 goto failed; 2374 } 2375 2376 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) 2377 ? DUPLEX_FULL : DUPLEX_HALF; 2378 skge->speed = yukon_speed(hw, phystat); 2379 2380 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 2381 switch (phystat & PHY_M_PS_PAUSE_MSK) { 2382 case PHY_M_PS_PAUSE_MSK: 2383 skge->flow_status = FLOW_STAT_SYMMETRIC; 2384 break; 2385 case PHY_M_PS_RX_P_EN: 2386 skge->flow_status = FLOW_STAT_REM_SEND; 2387 break; 2388 case PHY_M_PS_TX_P_EN: 2389 skge->flow_status = FLOW_STAT_LOC_SEND; 2390 break; 2391 default: 2392 skge->flow_status = FLOW_STAT_NONE; 2393 } 2394 2395 if (skge->flow_status == FLOW_STAT_NONE || 2396 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 2397 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 2398 else 2399 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 2400 yukon_link_up(skge); 2401 return; 2402 } 2403 2404 if (istatus & PHY_M_IS_LSP_CHANGE) 2405 skge->speed = yukon_speed(hw, phystat); 2406 2407 if (istatus & PHY_M_IS_DUP_CHANGE) 2408 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 2409 if (istatus & PHY_M_IS_LST_CHANGE) { 2410 if (phystat & PHY_M_PS_LINK_UP) 2411 yukon_link_up(skge); 2412 else 2413 yukon_link_down(skge); 2414 } 2415 return; 2416 failed: 2417 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason); 2418 2419 /* XXX restart autonegotiation? */ 2420 } 2421 2422 static void skge_phy_reset(struct skge_port *skge) 2423 { 2424 struct skge_hw *hw = skge->hw; 2425 int port = skge->port; 2426 struct net_device *dev = hw->dev[port]; 2427 2428 netif_stop_queue(skge->netdev); 2429 netif_carrier_off(skge->netdev); 2430 2431 spin_lock_bh(&hw->phy_lock); 2432 if (is_genesis(hw)) { 2433 genesis_reset(hw, port); 2434 genesis_mac_init(hw, port); 2435 } else { 2436 yukon_reset(hw, port); 2437 yukon_init(hw, port); 2438 } 2439 spin_unlock_bh(&hw->phy_lock); 2440 2441 skge_set_multicast(dev); 2442 } 2443 2444 /* Basic MII support */ 2445 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 2446 { 2447 struct mii_ioctl_data *data = if_mii(ifr); 2448 struct skge_port *skge = netdev_priv(dev); 2449 struct skge_hw *hw = skge->hw; 2450 int err = -EOPNOTSUPP; 2451 2452 if (!netif_running(dev)) 2453 return -ENODEV; /* Phy still in reset */ 2454 2455 switch (cmd) { 2456 case SIOCGMIIPHY: 2457 data->phy_id = hw->phy_addr; 2458 2459 fallthrough; 2460 case SIOCGMIIREG: { 2461 u16 val = 0; 2462 spin_lock_bh(&hw->phy_lock); 2463 2464 if (is_genesis(hw)) 2465 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2466 else 2467 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2468 spin_unlock_bh(&hw->phy_lock); 2469 data->val_out = val; 2470 break; 2471 } 2472 2473 case SIOCSMIIREG: 2474 spin_lock_bh(&hw->phy_lock); 2475 if (is_genesis(hw)) 2476 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2477 data->val_in); 2478 else 2479 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2480 data->val_in); 2481 spin_unlock_bh(&hw->phy_lock); 2482 break; 2483 } 2484 return err; 2485 } 2486 2487 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) 2488 { 2489 u32 end; 2490 2491 start /= 8; 2492 len /= 8; 2493 end = start + len - 1; 2494 2495 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 2496 skge_write32(hw, RB_ADDR(q, RB_START), start); 2497 skge_write32(hw, RB_ADDR(q, RB_WP), start); 2498 skge_write32(hw, RB_ADDR(q, RB_RP), start); 2499 skge_write32(hw, RB_ADDR(q, RB_END), end); 2500 2501 if (q == Q_R1 || q == Q_R2) { 2502 /* Set thresholds on receive queue's */ 2503 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), 2504 start + (2*len)/3); 2505 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), 2506 start + (len/3)); 2507 } else { 2508 /* Enable store & forward on Tx queue's because 2509 * Tx FIFO is only 4K on Genesis and 1K on Yukon 2510 */ 2511 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 2512 } 2513 2514 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 2515 } 2516 2517 /* Setup Bus Memory Interface */ 2518 static void skge_qset(struct skge_port *skge, u16 q, 2519 const struct skge_element *e) 2520 { 2521 struct skge_hw *hw = skge->hw; 2522 u32 watermark = 0x600; 2523 u64 base = skge->dma + (e->desc - skge->mem); 2524 2525 /* optimization to reduce window on 32bit/33mhz */ 2526 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) 2527 watermark /= 2; 2528 2529 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); 2530 skge_write32(hw, Q_ADDR(q, Q_F), watermark); 2531 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); 2532 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); 2533 } 2534 2535 static int skge_up(struct net_device *dev) 2536 { 2537 struct skge_port *skge = netdev_priv(dev); 2538 struct skge_hw *hw = skge->hw; 2539 int port = skge->port; 2540 u32 chunk, ram_addr; 2541 size_t rx_size, tx_size; 2542 int err; 2543 2544 if (!is_valid_ether_addr(dev->dev_addr)) 2545 return -EINVAL; 2546 2547 netif_info(skge, ifup, skge->netdev, "enabling interface\n"); 2548 2549 if (dev->mtu > RX_BUF_SIZE) 2550 skge->rx_buf_size = dev->mtu + ETH_HLEN; 2551 else 2552 skge->rx_buf_size = RX_BUF_SIZE; 2553 2554 2555 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); 2556 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); 2557 skge->mem_size = tx_size + rx_size; 2558 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size, 2559 &skge->dma, GFP_KERNEL); 2560 if (!skge->mem) 2561 return -ENOMEM; 2562 2563 BUG_ON(skge->dma & 7); 2564 2565 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) { 2566 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n"); 2567 err = -EINVAL; 2568 goto free_pci_mem; 2569 } 2570 2571 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); 2572 if (err) 2573 goto free_pci_mem; 2574 2575 err = skge_rx_fill(dev); 2576 if (err) 2577 goto free_rx_ring; 2578 2579 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, 2580 skge->dma + rx_size); 2581 if (err) 2582 goto free_rx_ring; 2583 2584 if (hw->ports == 1) { 2585 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED, 2586 dev->name, hw); 2587 if (err) { 2588 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n", 2589 hw->pdev->irq, err); 2590 goto free_tx_ring; 2591 } 2592 } 2593 2594 /* Initialize MAC */ 2595 netif_carrier_off(dev); 2596 spin_lock_bh(&hw->phy_lock); 2597 if (is_genesis(hw)) 2598 genesis_mac_init(hw, port); 2599 else 2600 yukon_mac_init(hw, port); 2601 spin_unlock_bh(&hw->phy_lock); 2602 2603 /* Configure RAMbuffers - equally between ports and tx/rx */ 2604 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); 2605 ram_addr = hw->ram_offset + 2 * chunk * port; 2606 2607 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); 2608 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); 2609 2610 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); 2611 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); 2612 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); 2613 2614 /* Start receiver BMU */ 2615 wmb(); 2616 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 2617 skge_led(skge, LED_MODE_ON); 2618 2619 spin_lock_irq(&hw->hw_lock); 2620 hw->intr_mask |= portmask[port]; 2621 skge_write32(hw, B0_IMSK, hw->intr_mask); 2622 skge_read32(hw, B0_IMSK); 2623 spin_unlock_irq(&hw->hw_lock); 2624 2625 napi_enable(&skge->napi); 2626 2627 skge_set_multicast(dev); 2628 2629 return 0; 2630 2631 free_tx_ring: 2632 kfree(skge->tx_ring.start); 2633 free_rx_ring: 2634 skge_rx_clean(skge); 2635 kfree(skge->rx_ring.start); 2636 free_pci_mem: 2637 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2638 skge->dma); 2639 skge->mem = NULL; 2640 2641 return err; 2642 } 2643 2644 /* stop receiver */ 2645 static void skge_rx_stop(struct skge_hw *hw, int port) 2646 { 2647 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); 2648 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), 2649 RB_RST_SET|RB_DIS_OP_MD); 2650 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 2651 } 2652 2653 static int skge_down(struct net_device *dev) 2654 { 2655 struct skge_port *skge = netdev_priv(dev); 2656 struct skge_hw *hw = skge->hw; 2657 int port = skge->port; 2658 2659 if (!skge->mem) 2660 return 0; 2661 2662 netif_info(skge, ifdown, skge->netdev, "disabling interface\n"); 2663 2664 netif_tx_disable(dev); 2665 2666 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC) 2667 del_timer_sync(&skge->link_timer); 2668 2669 napi_disable(&skge->napi); 2670 netif_carrier_off(dev); 2671 2672 spin_lock_irq(&hw->hw_lock); 2673 hw->intr_mask &= ~portmask[port]; 2674 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask); 2675 skge_read32(hw, B0_IMSK); 2676 spin_unlock_irq(&hw->hw_lock); 2677 2678 if (hw->ports == 1) 2679 free_irq(hw->pdev->irq, hw); 2680 2681 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF); 2682 if (is_genesis(hw)) 2683 genesis_stop(skge); 2684 else 2685 yukon_stop(skge); 2686 2687 /* Stop transmitter */ 2688 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 2689 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 2690 RB_RST_SET|RB_DIS_OP_MD); 2691 2692 2693 /* Disable Force Sync bit and Enable Alloc bit */ 2694 skge_write8(hw, SK_REG(port, TXA_CTRL), 2695 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2696 2697 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 2698 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 2699 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 2700 2701 /* Reset PCI FIFO */ 2702 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 2703 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 2704 2705 /* Reset the RAM Buffer async Tx queue */ 2706 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); 2707 2708 skge_rx_stop(hw, port); 2709 2710 if (is_genesis(hw)) { 2711 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2712 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2713 } else { 2714 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 2715 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 2716 } 2717 2718 skge_led(skge, LED_MODE_OFF); 2719 2720 netif_tx_lock_bh(dev); 2721 skge_tx_clean(dev); 2722 netif_tx_unlock_bh(dev); 2723 2724 skge_rx_clean(skge); 2725 2726 kfree(skge->rx_ring.start); 2727 kfree(skge->tx_ring.start); 2728 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem, 2729 skge->dma); 2730 skge->mem = NULL; 2731 return 0; 2732 } 2733 2734 static inline int skge_avail(const struct skge_ring *ring) 2735 { 2736 smp_mb(); 2737 return ((ring->to_clean > ring->to_use) ? 0 : ring->count) 2738 + (ring->to_clean - ring->to_use) - 1; 2739 } 2740 2741 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb, 2742 struct net_device *dev) 2743 { 2744 struct skge_port *skge = netdev_priv(dev); 2745 struct skge_hw *hw = skge->hw; 2746 struct skge_element *e; 2747 struct skge_tx_desc *td; 2748 int i; 2749 u32 control, len; 2750 dma_addr_t map; 2751 2752 if (skb_padto(skb, ETH_ZLEN)) 2753 return NETDEV_TX_OK; 2754 2755 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) 2756 return NETDEV_TX_BUSY; 2757 2758 e = skge->tx_ring.to_use; 2759 td = e->desc; 2760 BUG_ON(td->control & BMU_OWN); 2761 e->skb = skb; 2762 len = skb_headlen(skb); 2763 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE); 2764 if (dma_mapping_error(&hw->pdev->dev, map)) 2765 goto mapping_error; 2766 2767 dma_unmap_addr_set(e, mapaddr, map); 2768 dma_unmap_len_set(e, maplen, len); 2769 2770 td->dma_lo = lower_32_bits(map); 2771 td->dma_hi = upper_32_bits(map); 2772 2773 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2774 const int offset = skb_checksum_start_offset(skb); 2775 2776 /* This seems backwards, but it is what the sk98lin 2777 * does. Looks like hardware is wrong? 2778 */ 2779 if (ipip_hdr(skb)->protocol == IPPROTO_UDP && 2780 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) 2781 control = BMU_TCP_CHECK; 2782 else 2783 control = BMU_UDP_CHECK; 2784 2785 td->csum_offs = 0; 2786 td->csum_start = offset; 2787 td->csum_write = offset + skb->csum_offset; 2788 } else 2789 control = BMU_CHECK; 2790 2791 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ 2792 control |= BMU_EOF | BMU_IRQ_EOF; 2793 else { 2794 struct skge_tx_desc *tf = td; 2795 2796 control |= BMU_STFWD; 2797 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2798 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2799 2800 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0, 2801 skb_frag_size(frag), DMA_TO_DEVICE); 2802 if (dma_mapping_error(&hw->pdev->dev, map)) 2803 goto mapping_unwind; 2804 2805 e = e->next; 2806 e->skb = skb; 2807 tf = e->desc; 2808 BUG_ON(tf->control & BMU_OWN); 2809 2810 tf->dma_lo = lower_32_bits(map); 2811 tf->dma_hi = upper_32_bits(map); 2812 dma_unmap_addr_set(e, mapaddr, map); 2813 dma_unmap_len_set(e, maplen, skb_frag_size(frag)); 2814 2815 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag); 2816 } 2817 tf->control |= BMU_EOF | BMU_IRQ_EOF; 2818 } 2819 /* Make sure all the descriptors written */ 2820 wmb(); 2821 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; 2822 wmb(); 2823 2824 netdev_sent_queue(dev, skb->len); 2825 2826 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); 2827 2828 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev, 2829 "tx queued, slot %td, len %d\n", 2830 e - skge->tx_ring.start, skb->len); 2831 2832 skge->tx_ring.to_use = e->next; 2833 smp_wmb(); 2834 2835 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { 2836 netdev_dbg(dev, "transmit queue full\n"); 2837 netif_stop_queue(dev); 2838 } 2839 2840 return NETDEV_TX_OK; 2841 2842 mapping_unwind: 2843 e = skge->tx_ring.to_use; 2844 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2845 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2846 while (i-- > 0) { 2847 e = e->next; 2848 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr), 2849 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2850 } 2851 2852 mapping_error: 2853 if (net_ratelimit()) 2854 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name); 2855 dev_kfree_skb_any(skb); 2856 return NETDEV_TX_OK; 2857 } 2858 2859 2860 /* Free resources associated with this reing element */ 2861 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e, 2862 u32 control) 2863 { 2864 /* skb header vs. fragment */ 2865 if (control & BMU_STF) 2866 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr), 2867 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2868 else 2869 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr), 2870 dma_unmap_len(e, maplen), DMA_TO_DEVICE); 2871 } 2872 2873 /* Free all buffers in transmit ring */ 2874 static void skge_tx_clean(struct net_device *dev) 2875 { 2876 struct skge_port *skge = netdev_priv(dev); 2877 struct skge_element *e; 2878 2879 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 2880 struct skge_tx_desc *td = e->desc; 2881 2882 skge_tx_unmap(skge->hw->pdev, e, td->control); 2883 2884 if (td->control & BMU_EOF) 2885 dev_kfree_skb(e->skb); 2886 td->control = 0; 2887 } 2888 2889 netdev_reset_queue(dev); 2890 skge->tx_ring.to_clean = e; 2891 } 2892 2893 static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue) 2894 { 2895 struct skge_port *skge = netdev_priv(dev); 2896 2897 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n"); 2898 2899 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); 2900 skge_tx_clean(dev); 2901 netif_wake_queue(dev); 2902 } 2903 2904 static int skge_change_mtu(struct net_device *dev, int new_mtu) 2905 { 2906 int err; 2907 2908 if (!netif_running(dev)) { 2909 dev->mtu = new_mtu; 2910 return 0; 2911 } 2912 2913 skge_down(dev); 2914 2915 dev->mtu = new_mtu; 2916 2917 err = skge_up(dev); 2918 if (err) 2919 dev_close(dev); 2920 2921 return err; 2922 } 2923 2924 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 }; 2925 2926 static void genesis_add_filter(u8 filter[8], const u8 *addr) 2927 { 2928 u32 crc, bit; 2929 2930 crc = ether_crc_le(ETH_ALEN, addr); 2931 bit = ~crc & 0x3f; 2932 filter[bit/8] |= 1 << (bit%8); 2933 } 2934 2935 static void genesis_set_multicast(struct net_device *dev) 2936 { 2937 struct skge_port *skge = netdev_priv(dev); 2938 struct skge_hw *hw = skge->hw; 2939 int port = skge->port; 2940 struct netdev_hw_addr *ha; 2941 u32 mode; 2942 u8 filter[8]; 2943 2944 mode = xm_read32(hw, port, XM_MODE); 2945 mode |= XM_MD_ENA_HASH; 2946 if (dev->flags & IFF_PROMISC) 2947 mode |= XM_MD_ENA_PROM; 2948 else 2949 mode &= ~XM_MD_ENA_PROM; 2950 2951 if (dev->flags & IFF_ALLMULTI) 2952 memset(filter, 0xff, sizeof(filter)); 2953 else { 2954 memset(filter, 0, sizeof(filter)); 2955 2956 if (skge->flow_status == FLOW_STAT_REM_SEND || 2957 skge->flow_status == FLOW_STAT_SYMMETRIC) 2958 genesis_add_filter(filter, pause_mc_addr); 2959 2960 netdev_for_each_mc_addr(ha, dev) 2961 genesis_add_filter(filter, ha->addr); 2962 } 2963 2964 xm_write32(hw, port, XM_MODE, mode); 2965 xm_outhash(hw, port, XM_HSM, filter); 2966 } 2967 2968 static void yukon_add_filter(u8 filter[8], const u8 *addr) 2969 { 2970 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f; 2971 2972 filter[bit / 8] |= 1 << (bit % 8); 2973 } 2974 2975 static void yukon_set_multicast(struct net_device *dev) 2976 { 2977 struct skge_port *skge = netdev_priv(dev); 2978 struct skge_hw *hw = skge->hw; 2979 int port = skge->port; 2980 struct netdev_hw_addr *ha; 2981 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND || 2982 skge->flow_status == FLOW_STAT_SYMMETRIC); 2983 u16 reg; 2984 u8 filter[8]; 2985 2986 memset(filter, 0, sizeof(filter)); 2987 2988 reg = gma_read16(hw, port, GM_RX_CTRL); 2989 reg |= GM_RXCR_UCF_ENA; 2990 2991 if (dev->flags & IFF_PROMISC) /* promiscuous */ 2992 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2993 else if (dev->flags & IFF_ALLMULTI) /* all multicast */ 2994 memset(filter, 0xff, sizeof(filter)); 2995 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */ 2996 reg &= ~GM_RXCR_MCF_ENA; 2997 else { 2998 reg |= GM_RXCR_MCF_ENA; 2999 3000 if (rx_pause) 3001 yukon_add_filter(filter, pause_mc_addr); 3002 3003 netdev_for_each_mc_addr(ha, dev) 3004 yukon_add_filter(filter, ha->addr); 3005 } 3006 3007 3008 gma_write16(hw, port, GM_MC_ADDR_H1, 3009 (u16)filter[0] | ((u16)filter[1] << 8)); 3010 gma_write16(hw, port, GM_MC_ADDR_H2, 3011 (u16)filter[2] | ((u16)filter[3] << 8)); 3012 gma_write16(hw, port, GM_MC_ADDR_H3, 3013 (u16)filter[4] | ((u16)filter[5] << 8)); 3014 gma_write16(hw, port, GM_MC_ADDR_H4, 3015 (u16)filter[6] | ((u16)filter[7] << 8)); 3016 3017 gma_write16(hw, port, GM_RX_CTRL, reg); 3018 } 3019 3020 static inline u16 phy_length(const struct skge_hw *hw, u32 status) 3021 { 3022 if (is_genesis(hw)) 3023 return status >> XMR_FS_LEN_SHIFT; 3024 else 3025 return status >> GMR_FS_LEN_SHIFT; 3026 } 3027 3028 static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 3029 { 3030 if (is_genesis(hw)) 3031 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; 3032 else 3033 return (status & GMR_FS_ANY_ERR) || 3034 (status & GMR_FS_RX_OK) == 0; 3035 } 3036 3037 static void skge_set_multicast(struct net_device *dev) 3038 { 3039 struct skge_port *skge = netdev_priv(dev); 3040 3041 if (is_genesis(skge->hw)) 3042 genesis_set_multicast(dev); 3043 else 3044 yukon_set_multicast(dev); 3045 3046 } 3047 3048 3049 /* Get receive buffer from descriptor. 3050 * Handles copy of small buffers and reallocation failures 3051 */ 3052 static struct sk_buff *skge_rx_get(struct net_device *dev, 3053 struct skge_element *e, 3054 u32 control, u32 status, u16 csum) 3055 { 3056 struct skge_port *skge = netdev_priv(dev); 3057 struct sk_buff *skb; 3058 u16 len = control & BMU_BBC; 3059 3060 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev, 3061 "rx slot %td status 0x%x len %d\n", 3062 e - skge->rx_ring.start, status, len); 3063 3064 if (len > skge->rx_buf_size) 3065 goto error; 3066 3067 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) 3068 goto error; 3069 3070 if (bad_phy_status(skge->hw, status)) 3071 goto error; 3072 3073 if (phy_length(skge->hw, status) != len) 3074 goto error; 3075 3076 if (len < RX_COPY_THRESHOLD) { 3077 skb = netdev_alloc_skb_ip_align(dev, len); 3078 if (!skb) 3079 goto resubmit; 3080 3081 dma_sync_single_for_cpu(&skge->hw->pdev->dev, 3082 dma_unmap_addr(e, mapaddr), 3083 dma_unmap_len(e, maplen), 3084 DMA_FROM_DEVICE); 3085 skb_copy_from_linear_data(e->skb, skb->data, len); 3086 dma_sync_single_for_device(&skge->hw->pdev->dev, 3087 dma_unmap_addr(e, mapaddr), 3088 dma_unmap_len(e, maplen), 3089 DMA_FROM_DEVICE); 3090 skge_rx_reuse(e, skge->rx_buf_size); 3091 } else { 3092 struct skge_element ee; 3093 struct sk_buff *nskb; 3094 3095 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size); 3096 if (!nskb) 3097 goto resubmit; 3098 3099 ee = *e; 3100 3101 skb = ee.skb; 3102 prefetch(skb->data); 3103 3104 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) { 3105 dev_kfree_skb(nskb); 3106 goto resubmit; 3107 } 3108 3109 dma_unmap_single(&skge->hw->pdev->dev, 3110 dma_unmap_addr(&ee, mapaddr), 3111 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE); 3112 } 3113 3114 skb_put(skb, len); 3115 3116 if (dev->features & NETIF_F_RXCSUM) { 3117 skb->csum = le16_to_cpu(csum); 3118 skb->ip_summed = CHECKSUM_COMPLETE; 3119 } 3120 3121 skb->protocol = eth_type_trans(skb, dev); 3122 3123 return skb; 3124 error: 3125 3126 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev, 3127 "rx err, slot %td control 0x%x status 0x%x\n", 3128 e - skge->rx_ring.start, control, status); 3129 3130 if (is_genesis(skge->hw)) { 3131 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) 3132 dev->stats.rx_length_errors++; 3133 if (status & XMR_FS_FRA_ERR) 3134 dev->stats.rx_frame_errors++; 3135 if (status & XMR_FS_FCS_ERR) 3136 dev->stats.rx_crc_errors++; 3137 } else { 3138 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) 3139 dev->stats.rx_length_errors++; 3140 if (status & GMR_FS_FRAGMENT) 3141 dev->stats.rx_frame_errors++; 3142 if (status & GMR_FS_CRC_ERR) 3143 dev->stats.rx_crc_errors++; 3144 } 3145 3146 resubmit: 3147 skge_rx_reuse(e, skge->rx_buf_size); 3148 return NULL; 3149 } 3150 3151 /* Free all buffers in Tx ring which are no longer owned by device */ 3152 static void skge_tx_done(struct net_device *dev) 3153 { 3154 struct skge_port *skge = netdev_priv(dev); 3155 struct skge_ring *ring = &skge->tx_ring; 3156 struct skge_element *e; 3157 unsigned int bytes_compl = 0, pkts_compl = 0; 3158 3159 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3160 3161 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 3162 u32 control = ((const struct skge_tx_desc *) e->desc)->control; 3163 3164 if (control & BMU_OWN) 3165 break; 3166 3167 skge_tx_unmap(skge->hw->pdev, e, control); 3168 3169 if (control & BMU_EOF) { 3170 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev, 3171 "tx done slot %td\n", 3172 e - skge->tx_ring.start); 3173 3174 pkts_compl++; 3175 bytes_compl += e->skb->len; 3176 3177 dev_consume_skb_any(e->skb); 3178 } 3179 } 3180 netdev_completed_queue(dev, pkts_compl, bytes_compl); 3181 skge->tx_ring.to_clean = e; 3182 3183 /* Can run lockless until we need to synchronize to restart queue. */ 3184 smp_mb(); 3185 3186 if (unlikely(netif_queue_stopped(dev) && 3187 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3188 netif_tx_lock(dev); 3189 if (unlikely(netif_queue_stopped(dev) && 3190 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) { 3191 netif_wake_queue(dev); 3192 3193 } 3194 netif_tx_unlock(dev); 3195 } 3196 } 3197 3198 static int skge_poll(struct napi_struct *napi, int budget) 3199 { 3200 struct skge_port *skge = container_of(napi, struct skge_port, napi); 3201 struct net_device *dev = skge->netdev; 3202 struct skge_hw *hw = skge->hw; 3203 struct skge_ring *ring = &skge->rx_ring; 3204 struct skge_element *e; 3205 int work_done = 0; 3206 3207 skge_tx_done(dev); 3208 3209 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 3210 3211 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) { 3212 struct skge_rx_desc *rd = e->desc; 3213 struct sk_buff *skb; 3214 u32 control; 3215 3216 rmb(); 3217 control = rd->control; 3218 if (control & BMU_OWN) 3219 break; 3220 3221 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); 3222 if (likely(skb)) { 3223 napi_gro_receive(napi, skb); 3224 ++work_done; 3225 } 3226 } 3227 ring->to_clean = e; 3228 3229 /* restart receiver */ 3230 wmb(); 3231 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); 3232 3233 if (work_done < budget && napi_complete_done(napi, work_done)) { 3234 unsigned long flags; 3235 3236 spin_lock_irqsave(&hw->hw_lock, flags); 3237 hw->intr_mask |= napimask[skge->port]; 3238 skge_write32(hw, B0_IMSK, hw->intr_mask); 3239 skge_read32(hw, B0_IMSK); 3240 spin_unlock_irqrestore(&hw->hw_lock, flags); 3241 } 3242 3243 return work_done; 3244 } 3245 3246 /* Parity errors seem to happen when Genesis is connected to a switch 3247 * with no other ports present. Heartbeat error?? 3248 */ 3249 static void skge_mac_parity(struct skge_hw *hw, int port) 3250 { 3251 struct net_device *dev = hw->dev[port]; 3252 3253 ++dev->stats.tx_heartbeat_errors; 3254 3255 if (is_genesis(hw)) 3256 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 3257 MFF_CLR_PERR); 3258 else 3259 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ 3260 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), 3261 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 3262 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); 3263 } 3264 3265 static void skge_mac_intr(struct skge_hw *hw, int port) 3266 { 3267 if (is_genesis(hw)) 3268 genesis_mac_intr(hw, port); 3269 else 3270 yukon_mac_intr(hw, port); 3271 } 3272 3273 /* Handle device specific framing and timeout interrupts */ 3274 static void skge_error_irq(struct skge_hw *hw) 3275 { 3276 struct pci_dev *pdev = hw->pdev; 3277 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3278 3279 if (is_genesis(hw)) { 3280 /* clear xmac errors */ 3281 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 3282 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); 3283 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) 3284 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); 3285 } else { 3286 /* Timestamp (unused) overflow */ 3287 if (hwstatus & IS_IRQ_TIST_OV) 3288 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3289 } 3290 3291 if (hwstatus & IS_RAM_RD_PAR) { 3292 dev_err(&pdev->dev, "Ram read data parity error\n"); 3293 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); 3294 } 3295 3296 if (hwstatus & IS_RAM_WR_PAR) { 3297 dev_err(&pdev->dev, "Ram write data parity error\n"); 3298 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); 3299 } 3300 3301 if (hwstatus & IS_M1_PAR_ERR) 3302 skge_mac_parity(hw, 0); 3303 3304 if (hwstatus & IS_M2_PAR_ERR) 3305 skge_mac_parity(hw, 1); 3306 3307 if (hwstatus & IS_R1_PAR_ERR) { 3308 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3309 hw->dev[0]->name); 3310 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); 3311 } 3312 3313 if (hwstatus & IS_R2_PAR_ERR) { 3314 dev_err(&pdev->dev, "%s: receive queue parity error\n", 3315 hw->dev[1]->name); 3316 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); 3317 } 3318 3319 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { 3320 u16 pci_status, pci_cmd; 3321 3322 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 3323 pci_read_config_word(pdev, PCI_STATUS, &pci_status); 3324 3325 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n", 3326 pci_cmd, pci_status); 3327 3328 /* Write the error bits back to clear them. */ 3329 pci_status &= PCI_STATUS_ERROR_BITS; 3330 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3331 pci_write_config_word(pdev, PCI_COMMAND, 3332 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 3333 pci_write_config_word(pdev, PCI_STATUS, pci_status); 3334 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3335 3336 /* if error still set then just ignore it */ 3337 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3338 if (hwstatus & IS_IRQ_STAT) { 3339 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n"); 3340 hw->intr_mask &= ~IS_HW_ERR; 3341 } 3342 } 3343 } 3344 3345 /* 3346 * Interrupt from PHY are handled in tasklet (softirq) 3347 * because accessing phy registers requires spin wait which might 3348 * cause excess interrupt latency. 3349 */ 3350 static void skge_extirq(struct tasklet_struct *t) 3351 { 3352 struct skge_hw *hw = from_tasklet(hw, t, phy_task); 3353 int port; 3354 3355 for (port = 0; port < hw->ports; port++) { 3356 struct net_device *dev = hw->dev[port]; 3357 3358 if (netif_running(dev)) { 3359 struct skge_port *skge = netdev_priv(dev); 3360 3361 spin_lock(&hw->phy_lock); 3362 if (!is_genesis(hw)) 3363 yukon_phy_intr(skge); 3364 else if (hw->phy_type == SK_PHY_BCOM) 3365 bcom_phy_intr(skge); 3366 spin_unlock(&hw->phy_lock); 3367 } 3368 } 3369 3370 spin_lock_irq(&hw->hw_lock); 3371 hw->intr_mask |= IS_EXT_REG; 3372 skge_write32(hw, B0_IMSK, hw->intr_mask); 3373 skge_read32(hw, B0_IMSK); 3374 spin_unlock_irq(&hw->hw_lock); 3375 } 3376 3377 static irqreturn_t skge_intr(int irq, void *dev_id) 3378 { 3379 struct skge_hw *hw = dev_id; 3380 u32 status; 3381 int handled = 0; 3382 3383 spin_lock(&hw->hw_lock); 3384 /* Reading this register masks IRQ */ 3385 status = skge_read32(hw, B0_SP_ISRC); 3386 if (status == 0 || status == ~0) 3387 goto out; 3388 3389 handled = 1; 3390 status &= hw->intr_mask; 3391 if (status & IS_EXT_REG) { 3392 hw->intr_mask &= ~IS_EXT_REG; 3393 tasklet_schedule(&hw->phy_task); 3394 } 3395 3396 if (status & (IS_XA1_F|IS_R1_F)) { 3397 struct skge_port *skge = netdev_priv(hw->dev[0]); 3398 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); 3399 napi_schedule(&skge->napi); 3400 } 3401 3402 if (status & IS_PA_TO_TX1) 3403 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); 3404 3405 if (status & IS_PA_TO_RX1) { 3406 ++hw->dev[0]->stats.rx_over_errors; 3407 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); 3408 } 3409 3410 3411 if (status & IS_MAC1) 3412 skge_mac_intr(hw, 0); 3413 3414 if (hw->dev[1]) { 3415 struct skge_port *skge = netdev_priv(hw->dev[1]); 3416 3417 if (status & (IS_XA2_F|IS_R2_F)) { 3418 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); 3419 napi_schedule(&skge->napi); 3420 } 3421 3422 if (status & IS_PA_TO_RX2) { 3423 ++hw->dev[1]->stats.rx_over_errors; 3424 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); 3425 } 3426 3427 if (status & IS_PA_TO_TX2) 3428 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); 3429 3430 if (status & IS_MAC2) 3431 skge_mac_intr(hw, 1); 3432 } 3433 3434 if (status & IS_HW_ERR) 3435 skge_error_irq(hw); 3436 out: 3437 skge_write32(hw, B0_IMSK, hw->intr_mask); 3438 skge_read32(hw, B0_IMSK); 3439 spin_unlock(&hw->hw_lock); 3440 3441 return IRQ_RETVAL(handled); 3442 } 3443 3444 #ifdef CONFIG_NET_POLL_CONTROLLER 3445 static void skge_netpoll(struct net_device *dev) 3446 { 3447 struct skge_port *skge = netdev_priv(dev); 3448 3449 disable_irq(dev->irq); 3450 skge_intr(dev->irq, skge->hw); 3451 enable_irq(dev->irq); 3452 } 3453 #endif 3454 3455 static int skge_set_mac_address(struct net_device *dev, void *p) 3456 { 3457 struct skge_port *skge = netdev_priv(dev); 3458 struct skge_hw *hw = skge->hw; 3459 unsigned port = skge->port; 3460 const struct sockaddr *addr = p; 3461 u16 ctrl; 3462 3463 if (!is_valid_ether_addr(addr->sa_data)) 3464 return -EADDRNOTAVAIL; 3465 3466 eth_hw_addr_set(dev, addr->sa_data); 3467 3468 if (!netif_running(dev)) { 3469 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3470 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3471 } else { 3472 /* disable Rx */ 3473 spin_lock_bh(&hw->phy_lock); 3474 ctrl = gma_read16(hw, port, GM_GP_CTRL); 3475 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA); 3476 3477 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3478 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3479 3480 if (is_genesis(hw)) 3481 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 3482 else { 3483 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3484 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); 3485 } 3486 3487 gma_write16(hw, port, GM_GP_CTRL, ctrl); 3488 spin_unlock_bh(&hw->phy_lock); 3489 } 3490 3491 return 0; 3492 } 3493 3494 static const struct { 3495 u8 id; 3496 const char *name; 3497 } skge_chips[] = { 3498 { CHIP_ID_GENESIS, "Genesis" }, 3499 { CHIP_ID_YUKON, "Yukon" }, 3500 { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, 3501 { CHIP_ID_YUKON_LP, "Yukon-LP"}, 3502 }; 3503 3504 static const char *skge_board_name(const struct skge_hw *hw) 3505 { 3506 int i; 3507 static char buf[16]; 3508 3509 for (i = 0; i < ARRAY_SIZE(skge_chips); i++) 3510 if (skge_chips[i].id == hw->chip_id) 3511 return skge_chips[i].name; 3512 3513 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id); 3514 return buf; 3515 } 3516 3517 3518 /* 3519 * Setup the board data structure, but don't bring up 3520 * the port(s) 3521 */ 3522 static int skge_reset(struct skge_hw *hw) 3523 { 3524 u32 reg; 3525 u16 ctst, pci_status; 3526 u8 t8, mac_cfg, pmd_type; 3527 int i; 3528 3529 ctst = skge_read16(hw, B0_CTST); 3530 3531 /* do a SW reset */ 3532 skge_write8(hw, B0_CTST, CS_RST_SET); 3533 skge_write8(hw, B0_CTST, CS_RST_CLR); 3534 3535 /* clear PCI errors, if any */ 3536 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3537 skge_write8(hw, B2_TST_CTRL2, 0); 3538 3539 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); 3540 pci_write_config_word(hw->pdev, PCI_STATUS, 3541 pci_status | PCI_STATUS_ERROR_BITS); 3542 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3543 skge_write8(hw, B0_CTST, CS_MRST_CLR); 3544 3545 /* restore CLK_RUN bits (for Yukon-Lite) */ 3546 skge_write16(hw, B0_CTST, 3547 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); 3548 3549 hw->chip_id = skge_read8(hw, B2_CHIP_ID); 3550 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; 3551 pmd_type = skge_read8(hw, B2_PMD_TYP); 3552 hw->copper = (pmd_type == 'T' || pmd_type == '1'); 3553 3554 switch (hw->chip_id) { 3555 case CHIP_ID_GENESIS: 3556 #ifdef CONFIG_SKGE_GENESIS 3557 switch (hw->phy_type) { 3558 case SK_PHY_XMAC: 3559 hw->phy_addr = PHY_ADDR_XMAC; 3560 break; 3561 case SK_PHY_BCOM: 3562 hw->phy_addr = PHY_ADDR_BCOM; 3563 break; 3564 default: 3565 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n", 3566 hw->phy_type); 3567 return -EOPNOTSUPP; 3568 } 3569 break; 3570 #else 3571 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n"); 3572 return -EOPNOTSUPP; 3573 #endif 3574 3575 case CHIP_ID_YUKON: 3576 case CHIP_ID_YUKON_LITE: 3577 case CHIP_ID_YUKON_LP: 3578 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') 3579 hw->copper = 1; 3580 3581 hw->phy_addr = PHY_ADDR_MARV; 3582 break; 3583 3584 default: 3585 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n", 3586 hw->chip_id); 3587 return -EOPNOTSUPP; 3588 } 3589 3590 mac_cfg = skge_read8(hw, B2_MAC_CFG); 3591 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; 3592 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; 3593 3594 /* read the adapters RAM size */ 3595 t8 = skge_read8(hw, B2_E_0); 3596 if (is_genesis(hw)) { 3597 if (t8 == 3) { 3598 /* special case: 4 x 64k x 36, offset = 0x80000 */ 3599 hw->ram_size = 0x100000; 3600 hw->ram_offset = 0x80000; 3601 } else 3602 hw->ram_size = t8 * 512; 3603 } else if (t8 == 0) 3604 hw->ram_size = 0x20000; 3605 else 3606 hw->ram_size = t8 * 4096; 3607 3608 hw->intr_mask = IS_HW_ERR; 3609 3610 /* Use PHY IRQ for all but fiber based Genesis board */ 3611 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)) 3612 hw->intr_mask |= IS_EXT_REG; 3613 3614 if (is_genesis(hw)) 3615 genesis_init(hw); 3616 else { 3617 /* switch power to VCC (WA for VAUX problem) */ 3618 skge_write8(hw, B0_POWER_CTRL, 3619 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 3620 3621 /* avoid boards with stuck Hardware error bits */ 3622 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && 3623 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { 3624 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n"); 3625 hw->intr_mask &= ~IS_HW_ERR; 3626 } 3627 3628 /* Clear PHY COMA */ 3629 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3630 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); 3631 reg &= ~PCI_PHY_COMA; 3632 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); 3633 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3634 3635 3636 for (i = 0; i < hw->ports; i++) { 3637 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 3638 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 3639 } 3640 } 3641 3642 /* turn off hardware timer (unused) */ 3643 skge_write8(hw, B2_TI_CTRL, TIM_STOP); 3644 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 3645 skge_write8(hw, B0_LED, LED_STAT_ON); 3646 3647 /* enable the Tx Arbiters */ 3648 for (i = 0; i < hw->ports; i++) 3649 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 3650 3651 /* Initialize ram interface */ 3652 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 3653 3654 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); 3655 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); 3656 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); 3657 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); 3658 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); 3659 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); 3660 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); 3661 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); 3662 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); 3663 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); 3664 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); 3665 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); 3666 3667 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); 3668 3669 /* Set interrupt moderation for Transmit only 3670 * Receive interrupts avoided by NAPI 3671 */ 3672 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); 3673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); 3674 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 3675 3676 /* Leave irq disabled until first port is brought up. */ 3677 skge_write32(hw, B0_IMSK, 0); 3678 3679 for (i = 0; i < hw->ports; i++) { 3680 if (is_genesis(hw)) 3681 genesis_reset(hw, i); 3682 else 3683 yukon_reset(hw, i); 3684 } 3685 3686 return 0; 3687 } 3688 3689 3690 #ifdef CONFIG_SKGE_DEBUG 3691 3692 static struct dentry *skge_debug; 3693 3694 static int skge_debug_show(struct seq_file *seq, void *v) 3695 { 3696 struct net_device *dev = seq->private; 3697 const struct skge_port *skge = netdev_priv(dev); 3698 const struct skge_hw *hw = skge->hw; 3699 const struct skge_element *e; 3700 3701 if (!netif_running(dev)) 3702 return -ENETDOWN; 3703 3704 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC), 3705 skge_read32(hw, B0_IMSK)); 3706 3707 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring)); 3708 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 3709 const struct skge_tx_desc *t = e->desc; 3710 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n", 3711 t->control, t->dma_hi, t->dma_lo, t->status, 3712 t->csum_offs, t->csum_write, t->csum_start); 3713 } 3714 3715 seq_puts(seq, "\nRx Ring:\n"); 3716 for (e = skge->rx_ring.to_clean; ; e = e->next) { 3717 const struct skge_rx_desc *r = e->desc; 3718 3719 if (r->control & BMU_OWN) 3720 break; 3721 3722 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n", 3723 r->control, r->dma_hi, r->dma_lo, r->status, 3724 r->timestamp, r->csum1, r->csum1_start); 3725 } 3726 3727 return 0; 3728 } 3729 DEFINE_SHOW_ATTRIBUTE(skge_debug); 3730 3731 /* 3732 * Use network device events to create/remove/rename 3733 * debugfs file entries 3734 */ 3735 static int skge_device_event(struct notifier_block *unused, 3736 unsigned long event, void *ptr) 3737 { 3738 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 3739 struct skge_port *skge; 3740 3741 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug) 3742 goto done; 3743 3744 skge = netdev_priv(dev); 3745 switch (event) { 3746 case NETDEV_CHANGENAME: 3747 if (skge->debugfs) 3748 skge->debugfs = debugfs_rename(skge_debug, 3749 skge->debugfs, 3750 skge_debug, dev->name); 3751 break; 3752 3753 case NETDEV_GOING_DOWN: 3754 debugfs_remove(skge->debugfs); 3755 skge->debugfs = NULL; 3756 break; 3757 3758 case NETDEV_UP: 3759 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug, 3760 dev, &skge_debug_fops); 3761 break; 3762 } 3763 3764 done: 3765 return NOTIFY_DONE; 3766 } 3767 3768 static struct notifier_block skge_notifier = { 3769 .notifier_call = skge_device_event, 3770 }; 3771 3772 3773 static __init void skge_debug_init(void) 3774 { 3775 skge_debug = debugfs_create_dir("skge", NULL); 3776 3777 register_netdevice_notifier(&skge_notifier); 3778 } 3779 3780 static __exit void skge_debug_cleanup(void) 3781 { 3782 if (skge_debug) { 3783 unregister_netdevice_notifier(&skge_notifier); 3784 debugfs_remove(skge_debug); 3785 skge_debug = NULL; 3786 } 3787 } 3788 3789 #else 3790 #define skge_debug_init() 3791 #define skge_debug_cleanup() 3792 #endif 3793 3794 static const struct net_device_ops skge_netdev_ops = { 3795 .ndo_open = skge_up, 3796 .ndo_stop = skge_down, 3797 .ndo_start_xmit = skge_xmit_frame, 3798 .ndo_eth_ioctl = skge_ioctl, 3799 .ndo_get_stats = skge_get_stats, 3800 .ndo_tx_timeout = skge_tx_timeout, 3801 .ndo_change_mtu = skge_change_mtu, 3802 .ndo_validate_addr = eth_validate_addr, 3803 .ndo_set_rx_mode = skge_set_multicast, 3804 .ndo_set_mac_address = skge_set_mac_address, 3805 #ifdef CONFIG_NET_POLL_CONTROLLER 3806 .ndo_poll_controller = skge_netpoll, 3807 #endif 3808 }; 3809 3810 3811 /* Initialize network device */ 3812 static struct net_device *skge_devinit(struct skge_hw *hw, int port, 3813 int highmem) 3814 { 3815 struct skge_port *skge; 3816 struct net_device *dev = alloc_etherdev(sizeof(*skge)); 3817 u8 addr[ETH_ALEN]; 3818 3819 if (!dev) 3820 return NULL; 3821 3822 SET_NETDEV_DEV(dev, &hw->pdev->dev); 3823 dev->netdev_ops = &skge_netdev_ops; 3824 dev->ethtool_ops = &skge_ethtool_ops; 3825 dev->watchdog_timeo = TX_WATCHDOG; 3826 dev->irq = hw->pdev->irq; 3827 3828 /* MTU range: 60 - 9000 */ 3829 dev->min_mtu = ETH_ZLEN; 3830 dev->max_mtu = ETH_JUMBO_MTU; 3831 3832 if (highmem) 3833 dev->features |= NETIF_F_HIGHDMA; 3834 3835 skge = netdev_priv(dev); 3836 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT); 3837 skge->netdev = dev; 3838 skge->hw = hw; 3839 skge->msg_enable = netif_msg_init(debug, default_msg); 3840 3841 skge->tx_ring.count = DEFAULT_TX_RING_SIZE; 3842 skge->rx_ring.count = DEFAULT_RX_RING_SIZE; 3843 3844 /* Auto speed and flow control */ 3845 skge->autoneg = AUTONEG_ENABLE; 3846 skge->flow_control = FLOW_MODE_SYM_OR_REM; 3847 skge->duplex = -1; 3848 skge->speed = -1; 3849 skge->advertising = skge_supported_modes(hw); 3850 3851 if (device_can_wakeup(&hw->pdev->dev)) { 3852 skge->wol = wol_supported(hw) & WAKE_MAGIC; 3853 device_set_wakeup_enable(&hw->pdev->dev, skge->wol); 3854 } 3855 3856 hw->dev[port] = dev; 3857 3858 skge->port = port; 3859 3860 /* Only used for Genesis XMAC */ 3861 if (is_genesis(hw)) 3862 timer_setup(&skge->link_timer, xm_link_timer, 0); 3863 else { 3864 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3865 NETIF_F_RXCSUM; 3866 dev->features |= dev->hw_features; 3867 } 3868 3869 /* read the mac address */ 3870 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); 3871 eth_hw_addr_set(dev, addr); 3872 3873 return dev; 3874 } 3875 3876 static void skge_show_addr(struct net_device *dev) 3877 { 3878 const struct skge_port *skge = netdev_priv(dev); 3879 3880 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr); 3881 } 3882 3883 static int only_32bit_dma; 3884 3885 static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3886 { 3887 struct net_device *dev, *dev1; 3888 struct skge_hw *hw; 3889 int err, using_dac = 0; 3890 3891 err = pci_enable_device(pdev); 3892 if (err) { 3893 dev_err(&pdev->dev, "cannot enable PCI device\n"); 3894 goto err_out; 3895 } 3896 3897 err = pci_request_regions(pdev, DRV_NAME); 3898 if (err) { 3899 dev_err(&pdev->dev, "cannot obtain PCI resources\n"); 3900 goto err_out_disable_pdev; 3901 } 3902 3903 pci_set_master(pdev); 3904 3905 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { 3906 using_dac = 1; 3907 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 3908 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) { 3909 using_dac = 0; 3910 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3911 } 3912 3913 if (err) { 3914 dev_err(&pdev->dev, "no usable DMA configuration\n"); 3915 goto err_out_free_regions; 3916 } 3917 3918 #ifdef __BIG_ENDIAN 3919 /* byte swap descriptors in hardware */ 3920 { 3921 u32 reg; 3922 3923 pci_read_config_dword(pdev, PCI_DEV_REG2, ®); 3924 reg |= PCI_REV_DESC; 3925 pci_write_config_dword(pdev, PCI_DEV_REG2, reg); 3926 } 3927 #endif 3928 3929 err = -ENOMEM; 3930 /* space for skge@pci:0000:04:00.0 */ 3931 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:") 3932 + strlen(pci_name(pdev)) + 1, GFP_KERNEL); 3933 if (!hw) 3934 goto err_out_free_regions; 3935 3936 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev)); 3937 3938 hw->pdev = pdev; 3939 spin_lock_init(&hw->hw_lock); 3940 spin_lock_init(&hw->phy_lock); 3941 tasklet_setup(&hw->phy_task, skge_extirq); 3942 3943 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000); 3944 if (!hw->regs) { 3945 dev_err(&pdev->dev, "cannot map device registers\n"); 3946 goto err_out_free_hw; 3947 } 3948 3949 err = skge_reset(hw); 3950 if (err) 3951 goto err_out_iounmap; 3952 3953 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n", 3954 DRV_VERSION, 3955 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, 3956 skge_board_name(hw), hw->chip_rev); 3957 3958 dev = skge_devinit(hw, 0, using_dac); 3959 if (!dev) { 3960 err = -ENOMEM; 3961 goto err_out_led_off; 3962 } 3963 3964 /* Some motherboards are broken and has zero in ROM. */ 3965 if (!is_valid_ether_addr(dev->dev_addr)) 3966 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n"); 3967 3968 err = register_netdev(dev); 3969 if (err) { 3970 dev_err(&pdev->dev, "cannot register net device\n"); 3971 goto err_out_free_netdev; 3972 } 3973 3974 skge_show_addr(dev); 3975 3976 if (hw->ports > 1) { 3977 dev1 = skge_devinit(hw, 1, using_dac); 3978 if (!dev1) { 3979 err = -ENOMEM; 3980 goto err_out_unregister; 3981 } 3982 3983 err = register_netdev(dev1); 3984 if (err) { 3985 dev_err(&pdev->dev, "cannot register second net device\n"); 3986 goto err_out_free_dev1; 3987 } 3988 3989 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, 3990 hw->irq_name, hw); 3991 if (err) { 3992 dev_err(&pdev->dev, "cannot assign irq %d\n", 3993 pdev->irq); 3994 goto err_out_unregister_dev1; 3995 } 3996 3997 skge_show_addr(dev1); 3998 } 3999 pci_set_drvdata(pdev, hw); 4000 4001 return 0; 4002 4003 err_out_unregister_dev1: 4004 unregister_netdev(dev1); 4005 err_out_free_dev1: 4006 free_netdev(dev1); 4007 err_out_unregister: 4008 unregister_netdev(dev); 4009 err_out_free_netdev: 4010 free_netdev(dev); 4011 err_out_led_off: 4012 skge_write16(hw, B0_LED, LED_STAT_OFF); 4013 err_out_iounmap: 4014 iounmap(hw->regs); 4015 err_out_free_hw: 4016 kfree(hw); 4017 err_out_free_regions: 4018 pci_release_regions(pdev); 4019 err_out_disable_pdev: 4020 pci_disable_device(pdev); 4021 err_out: 4022 return err; 4023 } 4024 4025 static void skge_remove(struct pci_dev *pdev) 4026 { 4027 struct skge_hw *hw = pci_get_drvdata(pdev); 4028 struct net_device *dev0, *dev1; 4029 4030 if (!hw) 4031 return; 4032 4033 dev1 = hw->dev[1]; 4034 if (dev1) 4035 unregister_netdev(dev1); 4036 dev0 = hw->dev[0]; 4037 unregister_netdev(dev0); 4038 4039 tasklet_kill(&hw->phy_task); 4040 4041 spin_lock_irq(&hw->hw_lock); 4042 hw->intr_mask = 0; 4043 4044 if (hw->ports > 1) { 4045 skge_write32(hw, B0_IMSK, 0); 4046 skge_read32(hw, B0_IMSK); 4047 } 4048 spin_unlock_irq(&hw->hw_lock); 4049 4050 skge_write16(hw, B0_LED, LED_STAT_OFF); 4051 skge_write8(hw, B0_CTST, CS_RST_SET); 4052 4053 if (hw->ports > 1) 4054 free_irq(pdev->irq, hw); 4055 pci_release_regions(pdev); 4056 pci_disable_device(pdev); 4057 if (dev1) 4058 free_netdev(dev1); 4059 free_netdev(dev0); 4060 4061 iounmap(hw->regs); 4062 kfree(hw); 4063 } 4064 4065 #ifdef CONFIG_PM_SLEEP 4066 static int skge_suspend(struct device *dev) 4067 { 4068 struct skge_hw *hw = dev_get_drvdata(dev); 4069 int i; 4070 4071 if (!hw) 4072 return 0; 4073 4074 for (i = 0; i < hw->ports; i++) { 4075 struct net_device *dev = hw->dev[i]; 4076 struct skge_port *skge = netdev_priv(dev); 4077 4078 if (netif_running(dev)) 4079 skge_down(dev); 4080 4081 if (skge->wol) 4082 skge_wol_init(skge); 4083 } 4084 4085 skge_write32(hw, B0_IMSK, 0); 4086 4087 return 0; 4088 } 4089 4090 static int skge_resume(struct device *dev) 4091 { 4092 struct skge_hw *hw = dev_get_drvdata(dev); 4093 int i, err; 4094 4095 if (!hw) 4096 return 0; 4097 4098 err = skge_reset(hw); 4099 if (err) 4100 goto out; 4101 4102 for (i = 0; i < hw->ports; i++) { 4103 struct net_device *dev = hw->dev[i]; 4104 4105 if (netif_running(dev)) { 4106 err = skge_up(dev); 4107 4108 if (err) { 4109 netdev_err(dev, "could not up: %d\n", err); 4110 dev_close(dev); 4111 goto out; 4112 } 4113 } 4114 } 4115 out: 4116 return err; 4117 } 4118 4119 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume); 4120 #define SKGE_PM_OPS (&skge_pm_ops) 4121 4122 #else 4123 4124 #define SKGE_PM_OPS NULL 4125 #endif /* CONFIG_PM_SLEEP */ 4126 4127 static void skge_shutdown(struct pci_dev *pdev) 4128 { 4129 struct skge_hw *hw = pci_get_drvdata(pdev); 4130 int i; 4131 4132 if (!hw) 4133 return; 4134 4135 for (i = 0; i < hw->ports; i++) { 4136 struct net_device *dev = hw->dev[i]; 4137 struct skge_port *skge = netdev_priv(dev); 4138 4139 if (skge->wol) 4140 skge_wol_init(skge); 4141 } 4142 4143 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev)); 4144 pci_set_power_state(pdev, PCI_D3hot); 4145 } 4146 4147 static struct pci_driver skge_driver = { 4148 .name = DRV_NAME, 4149 .id_table = skge_id_table, 4150 .probe = skge_probe, 4151 .remove = skge_remove, 4152 .shutdown = skge_shutdown, 4153 .driver.pm = SKGE_PM_OPS, 4154 }; 4155 4156 static const struct dmi_system_id skge_32bit_dma_boards[] = { 4157 { 4158 .ident = "Gigabyte nForce boards", 4159 .matches = { 4160 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"), 4161 DMI_MATCH(DMI_BOARD_NAME, "nForce"), 4162 }, 4163 }, 4164 { 4165 .ident = "ASUS P5NSLI", 4166 .matches = { 4167 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 4168 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI") 4169 }, 4170 }, 4171 { 4172 .ident = "FUJITSU SIEMENS A8NE-FM", 4173 .matches = { 4174 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."), 4175 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM") 4176 }, 4177 }, 4178 {} 4179 }; 4180 4181 static int __init skge_init_module(void) 4182 { 4183 if (dmi_check_system(skge_32bit_dma_boards)) 4184 only_32bit_dma = 1; 4185 skge_debug_init(); 4186 return pci_register_driver(&skge_driver); 4187 } 4188 4189 static void __exit skge_cleanup_module(void) 4190 { 4191 pci_unregister_driver(&skge_driver); 4192 skge_debug_cleanup(); 4193 } 4194 4195 module_init(skge_init_module); 4196 module_exit(skge_cleanup_module); 4197