1 /* 2 * PXA168 ethernet driver. 3 * Most of the code is derived from mv643xx ethernet driver. 4 * 5 * Copyright (C) 2010 Marvell International Ltd. 6 * Sachin Sanap <ssanap@marvell.com> 7 * Zhangfei Gao <zgao6@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 * Mark Brown <markb@marvell.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/etherdevice.h> 30 #include <linux/ethtool.h> 31 #include <linux/in.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/ip.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of.h> 38 #include <linux/of_net.h> 39 #include <linux/phy.h> 40 #include <linux/platform_device.h> 41 #include <linux/pxa168_eth.h> 42 #include <linux/tcp.h> 43 #include <linux/types.h> 44 #include <linux/udp.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/pgtable.h> 48 #include <asm/cacheflush.h> 49 50 #define DRIVER_NAME "pxa168-eth" 51 #define DRIVER_VERSION "0.3" 52 53 /* 54 * Registers 55 */ 56 57 #define PHY_ADDRESS 0x0000 58 #define SMI 0x0010 59 #define PORT_CONFIG 0x0400 60 #define PORT_CONFIG_EXT 0x0408 61 #define PORT_COMMAND 0x0410 62 #define PORT_STATUS 0x0418 63 #define HTPR 0x0428 64 #define MAC_ADDR_LOW 0x0430 65 #define MAC_ADDR_HIGH 0x0438 66 #define SDMA_CONFIG 0x0440 67 #define SDMA_CMD 0x0448 68 #define INT_CAUSE 0x0450 69 #define INT_W_CLEAR 0x0454 70 #define INT_MASK 0x0458 71 #define ETH_F_RX_DESC_0 0x0480 72 #define ETH_C_RX_DESC_0 0x04A0 73 #define ETH_C_TX_DESC_1 0x04E4 74 75 /* smi register */ 76 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ 77 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ 78 #define SMI_OP_W (0 << 26) /* Write operation */ 79 #define SMI_OP_R (1 << 26) /* Read operation */ 80 81 #define PHY_WAIT_ITERATIONS 10 82 83 #define PXA168_ETH_PHY_ADDR_DEFAULT 0 84 /* RX & TX descriptor command */ 85 #define BUF_OWNED_BY_DMA (1 << 31) 86 87 /* RX descriptor status */ 88 #define RX_EN_INT (1 << 23) 89 #define RX_FIRST_DESC (1 << 17) 90 #define RX_LAST_DESC (1 << 16) 91 #define RX_ERROR (1 << 15) 92 93 /* TX descriptor command */ 94 #define TX_EN_INT (1 << 23) 95 #define TX_GEN_CRC (1 << 22) 96 #define TX_ZERO_PADDING (1 << 18) 97 #define TX_FIRST_DESC (1 << 17) 98 #define TX_LAST_DESC (1 << 16) 99 #define TX_ERROR (1 << 15) 100 101 /* SDMA_CMD */ 102 #define SDMA_CMD_AT (1 << 31) 103 #define SDMA_CMD_TXDL (1 << 24) 104 #define SDMA_CMD_TXDH (1 << 23) 105 #define SDMA_CMD_AR (1 << 15) 106 #define SDMA_CMD_ERD (1 << 7) 107 108 /* Bit definitions of the Port Config Reg */ 109 #define PCR_DUPLEX_FULL (1 << 15) 110 #define PCR_HS (1 << 12) 111 #define PCR_EN (1 << 7) 112 #define PCR_PM (1 << 0) 113 114 /* Bit definitions of the Port Config Extend Reg */ 115 #define PCXR_2BSM (1 << 28) 116 #define PCXR_DSCP_EN (1 << 21) 117 #define PCXR_RMII_EN (1 << 20) 118 #define PCXR_AN_SPEED_DIS (1 << 19) 119 #define PCXR_SPEED_100 (1 << 18) 120 #define PCXR_MFL_1518 (0 << 14) 121 #define PCXR_MFL_1536 (1 << 14) 122 #define PCXR_MFL_2048 (2 << 14) 123 #define PCXR_MFL_64K (3 << 14) 124 #define PCXR_FLOWCTL_DIS (1 << 12) 125 #define PCXR_FLP (1 << 11) 126 #define PCXR_AN_FLOWCTL_DIS (1 << 10) 127 #define PCXR_AN_DUPLEX_DIS (1 << 9) 128 #define PCXR_PRIO_TX_OFF 3 129 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) 130 131 /* Bit definitions of the SDMA Config Reg */ 132 #define SDCR_BSZ_OFF 12 133 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) 134 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) 135 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) 136 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) 137 #define SDCR_BLMR (1 << 6) 138 #define SDCR_BLMT (1 << 7) 139 #define SDCR_RIFB (1 << 9) 140 #define SDCR_RC_OFF 2 141 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 142 143 /* 144 * Bit definitions of the Interrupt Cause Reg 145 * and Interrupt MASK Reg is the same 146 */ 147 #define ICR_RXBUF (1 << 0) 148 #define ICR_TXBUF_H (1 << 2) 149 #define ICR_TXBUF_L (1 << 3) 150 #define ICR_TXEND_H (1 << 6) 151 #define ICR_TXEND_L (1 << 7) 152 #define ICR_RXERR (1 << 8) 153 #define ICR_TXERR_H (1 << 10) 154 #define ICR_TXERR_L (1 << 11) 155 #define ICR_TX_UDR (1 << 13) 156 #define ICR_MII_CH (1 << 28) 157 158 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 159 ICR_TXERR_H | ICR_TXERR_L |\ 160 ICR_TXEND_H | ICR_TXEND_L |\ 161 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 162 163 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 164 165 #define NUM_RX_DESCS 64 166 #define NUM_TX_DESCS 64 167 168 #define HASH_ADD 0 169 #define HASH_DELETE 1 170 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 171 #define HOP_NUMBER 12 172 173 /* Bit definitions for Port status */ 174 #define PORT_SPEED_100 (1 << 0) 175 #define FULL_DUPLEX (1 << 1) 176 #define FLOW_CONTROL_DISABLED (1 << 2) 177 #define LINK_UP (1 << 3) 178 179 /* Bit definitions for work to be done */ 180 #define WORK_TX_DONE (1 << 1) 181 182 /* 183 * Misc definitions. 184 */ 185 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 186 187 struct rx_desc { 188 u32 cmd_sts; /* Descriptor command status */ 189 u16 byte_cnt; /* Descriptor buffer byte count */ 190 u16 buf_size; /* Buffer size */ 191 u32 buf_ptr; /* Descriptor buffer pointer */ 192 u32 next_desc_ptr; /* Next descriptor pointer */ 193 }; 194 195 struct tx_desc { 196 u32 cmd_sts; /* Command/status field */ 197 u16 reserved; 198 u16 byte_cnt; /* buffer byte count */ 199 u32 buf_ptr; /* pointer to buffer for this descriptor */ 200 u32 next_desc_ptr; /* Pointer to next descriptor */ 201 }; 202 203 struct pxa168_eth_private { 204 int port_num; /* User Ethernet port number */ 205 int phy_addr; 206 int phy_speed; 207 int phy_duplex; 208 phy_interface_t phy_intf; 209 210 int rx_resource_err; /* Rx ring resource error flag */ 211 212 /* Next available and first returning Rx resource */ 213 int rx_curr_desc_q, rx_used_desc_q; 214 215 /* Next available and first returning Tx resource */ 216 int tx_curr_desc_q, tx_used_desc_q; 217 218 struct rx_desc *p_rx_desc_area; 219 dma_addr_t rx_desc_dma; 220 int rx_desc_area_size; 221 struct sk_buff **rx_skb; 222 223 struct tx_desc *p_tx_desc_area; 224 dma_addr_t tx_desc_dma; 225 int tx_desc_area_size; 226 struct sk_buff **tx_skb; 227 228 struct work_struct tx_timeout_task; 229 230 struct net_device *dev; 231 struct napi_struct napi; 232 u8 work_todo; 233 int skb_size; 234 235 /* Size of Tx Ring per queue */ 236 int tx_ring_size; 237 /* Number of tx descriptors in use */ 238 int tx_desc_count; 239 /* Size of Rx Ring per queue */ 240 int rx_ring_size; 241 /* Number of rx descriptors in use */ 242 int rx_desc_count; 243 244 /* 245 * Used in case RX Ring is empty, which can occur when 246 * system does not have resources (skb's) 247 */ 248 struct timer_list timeout; 249 struct mii_bus *smi_bus; 250 251 /* clock */ 252 struct clk *clk; 253 struct pxa168_eth_platform_data *pd; 254 /* 255 * Ethernet controller base address. 256 */ 257 void __iomem *base; 258 259 /* Pointer to the hardware address filter table */ 260 void *htpr; 261 dma_addr_t htpr_dma; 262 }; 263 264 struct addr_table_entry { 265 __le32 lo; 266 __le32 hi; 267 }; 268 269 /* Bit fields of a Hash Table Entry */ 270 enum hash_table_entry { 271 HASH_ENTRY_VALID = 1, 272 SKIP = 2, 273 HASH_ENTRY_RECEIVE_DISCARD = 4, 274 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 275 }; 276 277 static int pxa168_get_link_ksettings(struct net_device *dev, 278 struct ethtool_link_ksettings *cmd); 279 static int pxa168_init_hw(struct pxa168_eth_private *pep); 280 static int pxa168_init_phy(struct net_device *dev); 281 static void eth_port_reset(struct net_device *dev); 282 static void eth_port_start(struct net_device *dev); 283 static int pxa168_eth_open(struct net_device *dev); 284 static int pxa168_eth_stop(struct net_device *dev); 285 286 static inline u32 rdl(struct pxa168_eth_private *pep, int offset) 287 { 288 return readl_relaxed(pep->base + offset); 289 } 290 291 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) 292 { 293 writel_relaxed(data, pep->base + offset); 294 } 295 296 static void abort_dma(struct pxa168_eth_private *pep) 297 { 298 int delay; 299 int max_retries = 40; 300 301 do { 302 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); 303 udelay(100); 304 305 delay = 10; 306 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) 307 && delay-- > 0) { 308 udelay(10); 309 } 310 } while (max_retries-- > 0 && delay <= 0); 311 312 if (max_retries <= 0) 313 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__); 314 } 315 316 static void rxq_refill(struct net_device *dev) 317 { 318 struct pxa168_eth_private *pep = netdev_priv(dev); 319 struct sk_buff *skb; 320 struct rx_desc *p_used_rx_desc; 321 int used_rx_desc; 322 323 while (pep->rx_desc_count < pep->rx_ring_size) { 324 int size; 325 326 skb = netdev_alloc_skb(dev, pep->skb_size); 327 if (!skb) 328 break; 329 if (SKB_DMA_REALIGN) 330 skb_reserve(skb, SKB_DMA_REALIGN); 331 pep->rx_desc_count++; 332 /* Get 'used' Rx descriptor */ 333 used_rx_desc = pep->rx_used_desc_q; 334 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; 335 size = skb_end_pointer(skb) - skb->data; 336 p_used_rx_desc->buf_ptr = dma_map_single(NULL, 337 skb->data, 338 size, 339 DMA_FROM_DEVICE); 340 p_used_rx_desc->buf_size = size; 341 pep->rx_skb[used_rx_desc] = skb; 342 343 /* Return the descriptor to DMA ownership */ 344 dma_wmb(); 345 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; 346 dma_wmb(); 347 348 /* Move the used descriptor pointer to the next descriptor */ 349 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; 350 351 /* Any Rx return cancels the Rx resource error status */ 352 pep->rx_resource_err = 0; 353 354 skb_reserve(skb, ETH_HW_IP_ALIGN); 355 } 356 357 /* 358 * If RX ring is empty of SKB, set a timer to try allocating 359 * again at a later time. 360 */ 361 if (pep->rx_desc_count == 0) { 362 pep->timeout.expires = jiffies + (HZ / 10); 363 add_timer(&pep->timeout); 364 } 365 } 366 367 static inline void rxq_refill_timer_wrapper(unsigned long data) 368 { 369 struct pxa168_eth_private *pep = (void *)data; 370 napi_schedule(&pep->napi); 371 } 372 373 static inline u8 flip_8_bits(u8 x) 374 { 375 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) 376 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) 377 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) 378 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); 379 } 380 381 static void nibble_swap_every_byte(unsigned char *mac_addr) 382 { 383 int i; 384 for (i = 0; i < ETH_ALEN; i++) { 385 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | 386 ((mac_addr[i] & 0xf0) >> 4); 387 } 388 } 389 390 static void inverse_every_nibble(unsigned char *mac_addr) 391 { 392 int i; 393 for (i = 0; i < ETH_ALEN; i++) 394 mac_addr[i] = flip_8_bits(mac_addr[i]); 395 } 396 397 /* 398 * ---------------------------------------------------------------------------- 399 * This function will calculate the hash function of the address. 400 * Inputs 401 * mac_addr_orig - MAC address. 402 * Outputs 403 * return the calculated entry. 404 */ 405 static u32 hash_function(unsigned char *mac_addr_orig) 406 { 407 u32 hash_result; 408 u32 addr0; 409 u32 addr1; 410 u32 addr2; 411 u32 addr3; 412 unsigned char mac_addr[ETH_ALEN]; 413 414 /* Make a copy of MAC address since we are going to performe bit 415 * operations on it 416 */ 417 memcpy(mac_addr, mac_addr_orig, ETH_ALEN); 418 419 nibble_swap_every_byte(mac_addr); 420 inverse_every_nibble(mac_addr); 421 422 addr0 = (mac_addr[5] >> 2) & 0x3f; 423 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); 424 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; 425 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); 426 427 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); 428 hash_result = hash_result & 0x07ff; 429 return hash_result; 430 } 431 432 /* 433 * ---------------------------------------------------------------------------- 434 * This function will add/del an entry to the address table. 435 * Inputs 436 * pep - ETHERNET . 437 * mac_addr - MAC address. 438 * skip - if 1, skip this address.Used in case of deleting an entry which is a 439 * part of chain in the hash table.We can't just delete the entry since 440 * that will break the chain.We need to defragment the tables time to 441 * time. 442 * rd - 0 Discard packet upon match. 443 * - 1 Receive packet upon match. 444 * Outputs 445 * address table entry is added/deleted. 446 * 0 if success. 447 * -ENOSPC if table full 448 */ 449 static int add_del_hash_entry(struct pxa168_eth_private *pep, 450 unsigned char *mac_addr, 451 u32 rd, u32 skip, int del) 452 { 453 struct addr_table_entry *entry, *start; 454 u32 new_high; 455 u32 new_low; 456 u32 i; 457 458 new_low = (((mac_addr[1] >> 4) & 0xf) << 15) 459 | (((mac_addr[1] >> 0) & 0xf) << 11) 460 | (((mac_addr[0] >> 4) & 0xf) << 7) 461 | (((mac_addr[0] >> 0) & 0xf) << 3) 462 | (((mac_addr[3] >> 4) & 0x1) << 31) 463 | (((mac_addr[3] >> 0) & 0xf) << 27) 464 | (((mac_addr[2] >> 4) & 0xf) << 23) 465 | (((mac_addr[2] >> 0) & 0xf) << 19) 466 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) 467 | HASH_ENTRY_VALID; 468 469 new_high = (((mac_addr[5] >> 4) & 0xf) << 15) 470 | (((mac_addr[5] >> 0) & 0xf) << 11) 471 | (((mac_addr[4] >> 4) & 0xf) << 7) 472 | (((mac_addr[4] >> 0) & 0xf) << 3) 473 | (((mac_addr[3] >> 5) & 0x7) << 0); 474 475 /* 476 * Pick the appropriate table, start scanning for free/reusable 477 * entries at the index obtained by hashing the specified MAC address 478 */ 479 start = pep->htpr; 480 entry = start + hash_function(mac_addr); 481 for (i = 0; i < HOP_NUMBER; i++) { 482 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { 483 break; 484 } else { 485 /* if same address put in same position */ 486 if (((le32_to_cpu(entry->lo) & 0xfffffff8) == 487 (new_low & 0xfffffff8)) && 488 (le32_to_cpu(entry->hi) == new_high)) { 489 break; 490 } 491 } 492 if (entry == start + 0x7ff) 493 entry = start; 494 else 495 entry++; 496 } 497 498 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && 499 (le32_to_cpu(entry->hi) != new_high) && del) 500 return 0; 501 502 if (i == HOP_NUMBER) { 503 if (!del) { 504 netdev_info(pep->dev, 505 "%s: table section is full, need to " 506 "move to 16kB implementation?\n", 507 __FILE__); 508 return -ENOSPC; 509 } else 510 return 0; 511 } 512 513 /* 514 * Update the selected entry 515 */ 516 if (del) { 517 entry->hi = 0; 518 entry->lo = 0; 519 } else { 520 entry->hi = cpu_to_le32(new_high); 521 entry->lo = cpu_to_le32(new_low); 522 } 523 524 return 0; 525 } 526 527 /* 528 * ---------------------------------------------------------------------------- 529 * Create an addressTable entry from MAC address info 530 * found in the specifed net_device struct 531 * 532 * Input : pointer to ethernet interface network device structure 533 * Output : N/A 534 */ 535 static void update_hash_table_mac_address(struct pxa168_eth_private *pep, 536 unsigned char *oaddr, 537 unsigned char *addr) 538 { 539 /* Delete old entry */ 540 if (oaddr) 541 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); 542 /* Add new entry */ 543 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); 544 } 545 546 static int init_hash_table(struct pxa168_eth_private *pep) 547 { 548 /* 549 * Hardware expects CPU to build a hash table based on a predefined 550 * hash function and populate it based on hardware address. The 551 * location of the hash table is identified by 32-bit pointer stored 552 * in HTPR internal register. Two possible sizes exists for the hash 553 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB 554 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support 555 * 1/2kB. 556 */ 557 /* TODO: Add support for 8kB hash table and alternative hash 558 * function.Driver can dynamically switch to them if the 1/2kB hash 559 * table is full. 560 */ 561 if (pep->htpr == NULL) { 562 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent, 563 HASH_ADDR_TABLE_SIZE, 564 &pep->htpr_dma, GFP_KERNEL); 565 if (pep->htpr == NULL) 566 return -ENOMEM; 567 } else { 568 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 569 } 570 wrl(pep, HTPR, pep->htpr_dma); 571 return 0; 572 } 573 574 static void pxa168_eth_set_rx_mode(struct net_device *dev) 575 { 576 struct pxa168_eth_private *pep = netdev_priv(dev); 577 struct netdev_hw_addr *ha; 578 u32 val; 579 580 val = rdl(pep, PORT_CONFIG); 581 if (dev->flags & IFF_PROMISC) 582 val |= PCR_PM; 583 else 584 val &= ~PCR_PM; 585 wrl(pep, PORT_CONFIG, val); 586 587 /* 588 * Remove the old list of MAC address and add dev->addr 589 * and multicast address. 590 */ 591 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 592 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 593 594 netdev_for_each_mc_addr(ha, dev) 595 update_hash_table_mac_address(pep, NULL, ha->addr); 596 } 597 598 static void pxa168_eth_get_mac_address(struct net_device *dev, 599 unsigned char *addr) 600 { 601 struct pxa168_eth_private *pep = netdev_priv(dev); 602 unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH); 603 unsigned int mac_l = rdl(pep, MAC_ADDR_LOW); 604 605 addr[0] = (mac_h >> 24) & 0xff; 606 addr[1] = (mac_h >> 16) & 0xff; 607 addr[2] = (mac_h >> 8) & 0xff; 608 addr[3] = mac_h & 0xff; 609 addr[4] = (mac_l >> 8) & 0xff; 610 addr[5] = mac_l & 0xff; 611 } 612 613 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) 614 { 615 struct sockaddr *sa = addr; 616 struct pxa168_eth_private *pep = netdev_priv(dev); 617 unsigned char oldMac[ETH_ALEN]; 618 u32 mac_h, mac_l; 619 620 if (!is_valid_ether_addr(sa->sa_data)) 621 return -EADDRNOTAVAIL; 622 memcpy(oldMac, dev->dev_addr, ETH_ALEN); 623 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 624 625 mac_h = dev->dev_addr[0] << 24; 626 mac_h |= dev->dev_addr[1] << 16; 627 mac_h |= dev->dev_addr[2] << 8; 628 mac_h |= dev->dev_addr[3]; 629 mac_l = dev->dev_addr[4] << 8; 630 mac_l |= dev->dev_addr[5]; 631 wrl(pep, MAC_ADDR_HIGH, mac_h); 632 wrl(pep, MAC_ADDR_LOW, mac_l); 633 634 netif_addr_lock_bh(dev); 635 update_hash_table_mac_address(pep, oldMac, dev->dev_addr); 636 netif_addr_unlock_bh(dev); 637 return 0; 638 } 639 640 static void eth_port_start(struct net_device *dev) 641 { 642 unsigned int val = 0; 643 struct pxa168_eth_private *pep = netdev_priv(dev); 644 int tx_curr_desc, rx_curr_desc; 645 646 phy_start(dev->phydev); 647 648 /* Assignment of Tx CTRP of given queue */ 649 tx_curr_desc = pep->tx_curr_desc_q; 650 wrl(pep, ETH_C_TX_DESC_1, 651 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); 652 653 /* Assignment of Rx CRDP of given queue */ 654 rx_curr_desc = pep->rx_curr_desc_q; 655 wrl(pep, ETH_C_RX_DESC_0, 656 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 657 658 wrl(pep, ETH_F_RX_DESC_0, 659 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 660 661 /* Clear all interrupts */ 662 wrl(pep, INT_CAUSE, 0); 663 664 /* Enable all interrupts for receive, transmit and error. */ 665 wrl(pep, INT_MASK, ALL_INTS); 666 667 val = rdl(pep, PORT_CONFIG); 668 val |= PCR_EN; 669 wrl(pep, PORT_CONFIG, val); 670 671 /* Start RX DMA engine */ 672 val = rdl(pep, SDMA_CMD); 673 val |= SDMA_CMD_ERD; 674 wrl(pep, SDMA_CMD, val); 675 } 676 677 static void eth_port_reset(struct net_device *dev) 678 { 679 struct pxa168_eth_private *pep = netdev_priv(dev); 680 unsigned int val = 0; 681 682 /* Stop all interrupts for receive, transmit and error. */ 683 wrl(pep, INT_MASK, 0); 684 685 /* Clear all interrupts */ 686 wrl(pep, INT_CAUSE, 0); 687 688 /* Stop RX DMA */ 689 val = rdl(pep, SDMA_CMD); 690 val &= ~SDMA_CMD_ERD; /* abort dma command */ 691 692 /* Abort any transmit and receive operations and put DMA 693 * in idle state. 694 */ 695 abort_dma(pep); 696 697 /* Disable port */ 698 val = rdl(pep, PORT_CONFIG); 699 val &= ~PCR_EN; 700 wrl(pep, PORT_CONFIG, val); 701 702 phy_stop(dev->phydev); 703 } 704 705 /* 706 * txq_reclaim - Free the tx desc data for completed descriptors 707 * If force is non-zero, frees uncompleted descriptors as well 708 */ 709 static int txq_reclaim(struct net_device *dev, int force) 710 { 711 struct pxa168_eth_private *pep = netdev_priv(dev); 712 struct tx_desc *desc; 713 u32 cmd_sts; 714 struct sk_buff *skb; 715 int tx_index; 716 dma_addr_t addr; 717 int count; 718 int released = 0; 719 720 netif_tx_lock(dev); 721 722 pep->work_todo &= ~WORK_TX_DONE; 723 while (pep->tx_desc_count > 0) { 724 tx_index = pep->tx_used_desc_q; 725 desc = &pep->p_tx_desc_area[tx_index]; 726 cmd_sts = desc->cmd_sts; 727 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { 728 if (released > 0) { 729 goto txq_reclaim_end; 730 } else { 731 released = -1; 732 goto txq_reclaim_end; 733 } 734 } 735 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; 736 pep->tx_desc_count--; 737 addr = desc->buf_ptr; 738 count = desc->byte_cnt; 739 skb = pep->tx_skb[tx_index]; 740 if (skb) 741 pep->tx_skb[tx_index] = NULL; 742 743 if (cmd_sts & TX_ERROR) { 744 if (net_ratelimit()) 745 netdev_err(dev, "Error in TX\n"); 746 dev->stats.tx_errors++; 747 } 748 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 749 if (skb) 750 dev_kfree_skb_irq(skb); 751 released++; 752 } 753 txq_reclaim_end: 754 netif_tx_unlock(dev); 755 return released; 756 } 757 758 static void pxa168_eth_tx_timeout(struct net_device *dev) 759 { 760 struct pxa168_eth_private *pep = netdev_priv(dev); 761 762 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count); 763 764 schedule_work(&pep->tx_timeout_task); 765 } 766 767 static void pxa168_eth_tx_timeout_task(struct work_struct *work) 768 { 769 struct pxa168_eth_private *pep = container_of(work, 770 struct pxa168_eth_private, 771 tx_timeout_task); 772 struct net_device *dev = pep->dev; 773 pxa168_eth_stop(dev); 774 pxa168_eth_open(dev); 775 } 776 777 static int rxq_process(struct net_device *dev, int budget) 778 { 779 struct pxa168_eth_private *pep = netdev_priv(dev); 780 struct net_device_stats *stats = &dev->stats; 781 unsigned int received_packets = 0; 782 struct sk_buff *skb; 783 784 while (budget-- > 0) { 785 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 786 struct rx_desc *rx_desc; 787 unsigned int cmd_sts; 788 789 /* Do not process Rx ring in case of Rx ring resource error */ 790 if (pep->rx_resource_err) 791 break; 792 rx_curr_desc = pep->rx_curr_desc_q; 793 rx_used_desc = pep->rx_used_desc_q; 794 rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; 795 cmd_sts = rx_desc->cmd_sts; 796 dma_rmb(); 797 if (cmd_sts & (BUF_OWNED_BY_DMA)) 798 break; 799 skb = pep->rx_skb[rx_curr_desc]; 800 pep->rx_skb[rx_curr_desc] = NULL; 801 802 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; 803 pep->rx_curr_desc_q = rx_next_curr_desc; 804 805 /* Rx descriptors exhausted. */ 806 /* Set the Rx ring resource error flag */ 807 if (rx_next_curr_desc == rx_used_desc) 808 pep->rx_resource_err = 1; 809 pep->rx_desc_count--; 810 dma_unmap_single(NULL, rx_desc->buf_ptr, 811 rx_desc->buf_size, 812 DMA_FROM_DEVICE); 813 received_packets++; 814 /* 815 * Update statistics. 816 * Note byte count includes 4 byte CRC count 817 */ 818 stats->rx_packets++; 819 stats->rx_bytes += rx_desc->byte_cnt; 820 /* 821 * In case received a packet without first / last bits on OR 822 * the error summary bit is on, the packets needs to be droped. 823 */ 824 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 825 (RX_FIRST_DESC | RX_LAST_DESC)) 826 || (cmd_sts & RX_ERROR)) { 827 828 stats->rx_dropped++; 829 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 830 (RX_FIRST_DESC | RX_LAST_DESC)) { 831 if (net_ratelimit()) 832 netdev_err(dev, 833 "Rx pkt on multiple desc\n"); 834 } 835 if (cmd_sts & RX_ERROR) 836 stats->rx_errors++; 837 dev_kfree_skb_irq(skb); 838 } else { 839 /* 840 * The -4 is for the CRC in the trailer of the 841 * received packet 842 */ 843 skb_put(skb, rx_desc->byte_cnt - 4); 844 skb->protocol = eth_type_trans(skb, dev); 845 netif_receive_skb(skb); 846 } 847 } 848 /* Fill RX ring with skb's */ 849 rxq_refill(dev); 850 return received_packets; 851 } 852 853 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, 854 struct net_device *dev) 855 { 856 u32 icr; 857 int ret = 0; 858 859 icr = rdl(pep, INT_CAUSE); 860 if (icr == 0) 861 return IRQ_NONE; 862 863 wrl(pep, INT_CAUSE, ~icr); 864 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { 865 pep->work_todo |= WORK_TX_DONE; 866 ret = 1; 867 } 868 if (icr & ICR_RXBUF) 869 ret = 1; 870 return ret; 871 } 872 873 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) 874 { 875 struct net_device *dev = (struct net_device *)dev_id; 876 struct pxa168_eth_private *pep = netdev_priv(dev); 877 878 if (unlikely(!pxa168_eth_collect_events(pep, dev))) 879 return IRQ_NONE; 880 /* Disable interrupts */ 881 wrl(pep, INT_MASK, 0); 882 napi_schedule(&pep->napi); 883 return IRQ_HANDLED; 884 } 885 886 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) 887 { 888 int skb_size; 889 890 /* 891 * Reserve 2+14 bytes for an ethernet header (the hardware 892 * automatically prepends 2 bytes of dummy data to each 893 * received packet), 16 bytes for up to four VLAN tags, and 894 * 4 bytes for the trailing FCS -- 36 bytes total. 895 */ 896 skb_size = pep->dev->mtu + 36; 897 898 /* 899 * Make sure that the skb size is a multiple of 8 bytes, as 900 * the lower three bits of the receive descriptor's buffer 901 * size field are ignored by the hardware. 902 */ 903 pep->skb_size = (skb_size + 7) & ~7; 904 905 /* 906 * If NET_SKB_PAD is smaller than a cache line, 907 * netdev_alloc_skb() will cause skb->data to be misaligned 908 * to a cache line boundary. If this is the case, include 909 * some extra space to allow re-aligning the data area. 910 */ 911 pep->skb_size += SKB_DMA_REALIGN; 912 913 } 914 915 static int set_port_config_ext(struct pxa168_eth_private *pep) 916 { 917 int skb_size; 918 919 pxa168_eth_recalc_skb_size(pep); 920 if (pep->skb_size <= 1518) 921 skb_size = PCXR_MFL_1518; 922 else if (pep->skb_size <= 1536) 923 skb_size = PCXR_MFL_1536; 924 else if (pep->skb_size <= 2048) 925 skb_size = PCXR_MFL_2048; 926 else 927 skb_size = PCXR_MFL_64K; 928 929 /* Extended Port Configuration */ 930 wrl(pep, PORT_CONFIG_EXT, 931 PCXR_AN_SPEED_DIS | /* Disable HW AN */ 932 PCXR_AN_DUPLEX_DIS | 933 PCXR_AN_FLOWCTL_DIS | 934 PCXR_2BSM | /* Two byte prefix aligns IP hdr */ 935 PCXR_DSCP_EN | /* Enable DSCP in IP */ 936 skb_size | PCXR_FLP | /* do not force link pass */ 937 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ 938 939 return 0; 940 } 941 942 static void pxa168_eth_adjust_link(struct net_device *dev) 943 { 944 struct pxa168_eth_private *pep = netdev_priv(dev); 945 struct phy_device *phy = dev->phydev; 946 u32 cfg, cfg_o = rdl(pep, PORT_CONFIG); 947 u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT); 948 949 cfg = cfg_o & ~PCR_DUPLEX_FULL; 950 cfgext = cfgext_o & ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN); 951 952 if (phy->interface == PHY_INTERFACE_MODE_RMII) 953 cfgext |= PCXR_RMII_EN; 954 if (phy->speed == SPEED_100) 955 cfgext |= PCXR_SPEED_100; 956 if (phy->duplex) 957 cfg |= PCR_DUPLEX_FULL; 958 if (!phy->pause) 959 cfgext |= PCXR_FLOWCTL_DIS; 960 961 /* Bail out if there has nothing changed */ 962 if (cfg == cfg_o && cfgext == cfgext_o) 963 return; 964 965 wrl(pep, PORT_CONFIG, cfg); 966 wrl(pep, PORT_CONFIG_EXT, cfgext); 967 968 phy_print_status(phy); 969 } 970 971 static int pxa168_init_phy(struct net_device *dev) 972 { 973 struct pxa168_eth_private *pep = netdev_priv(dev); 974 struct ethtool_link_ksettings cmd; 975 struct phy_device *phy = NULL; 976 int err; 977 978 if (dev->phydev) 979 return 0; 980 981 phy = mdiobus_scan(pep->smi_bus, pep->phy_addr); 982 if (IS_ERR(phy)) 983 return PTR_ERR(phy); 984 985 err = phy_connect_direct(dev, phy, pxa168_eth_adjust_link, 986 pep->phy_intf); 987 if (err) 988 return err; 989 990 err = pxa168_get_link_ksettings(dev, &cmd); 991 if (err) 992 return err; 993 994 cmd.base.phy_address = pep->phy_addr; 995 cmd.base.speed = pep->phy_speed; 996 cmd.base.duplex = pep->phy_duplex; 997 ethtool_convert_legacy_u32_to_link_mode(cmd.link_modes.advertising, 998 PHY_BASIC_FEATURES); 999 cmd.base.autoneg = AUTONEG_ENABLE; 1000 1001 if (cmd.base.speed != 0) 1002 cmd.base.autoneg = AUTONEG_DISABLE; 1003 1004 return phy_ethtool_set_link_ksettings(dev, &cmd); 1005 } 1006 1007 static int pxa168_init_hw(struct pxa168_eth_private *pep) 1008 { 1009 int err = 0; 1010 1011 /* Disable interrupts */ 1012 wrl(pep, INT_MASK, 0); 1013 wrl(pep, INT_CAUSE, 0); 1014 /* Write to ICR to clear interrupts. */ 1015 wrl(pep, INT_W_CLEAR, 0); 1016 /* Abort any transmit and receive operations and put DMA 1017 * in idle state. 1018 */ 1019 abort_dma(pep); 1020 /* Initialize address hash table */ 1021 err = init_hash_table(pep); 1022 if (err) 1023 return err; 1024 /* SDMA configuration */ 1025 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ 1026 SDCR_RIFB | /* Rx interrupt on frame */ 1027 SDCR_BLMT | /* Little endian transmit */ 1028 SDCR_BLMR | /* Little endian receive */ 1029 SDCR_RC_MAX_RETRANS); /* Max retransmit count */ 1030 /* Port Configuration */ 1031 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ 1032 set_port_config_ext(pep); 1033 1034 return err; 1035 } 1036 1037 static int rxq_init(struct net_device *dev) 1038 { 1039 struct pxa168_eth_private *pep = netdev_priv(dev); 1040 struct rx_desc *p_rx_desc; 1041 int size = 0, i = 0; 1042 int rx_desc_num = pep->rx_ring_size; 1043 1044 /* Allocate RX skb rings */ 1045 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, 1046 GFP_KERNEL); 1047 if (!pep->rx_skb) 1048 return -ENOMEM; 1049 1050 /* Allocate RX ring */ 1051 pep->rx_desc_count = 0; 1052 size = pep->rx_ring_size * sizeof(struct rx_desc); 1053 pep->rx_desc_area_size = size; 1054 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1055 &pep->rx_desc_dma, 1056 GFP_KERNEL); 1057 if (!pep->p_rx_desc_area) 1058 goto out; 1059 1060 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 1061 p_rx_desc = pep->p_rx_desc_area; 1062 for (i = 0; i < rx_desc_num; i++) { 1063 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + 1064 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); 1065 } 1066 /* Save Rx desc pointer to driver struct. */ 1067 pep->rx_curr_desc_q = 0; 1068 pep->rx_used_desc_q = 0; 1069 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); 1070 return 0; 1071 out: 1072 kfree(pep->rx_skb); 1073 return -ENOMEM; 1074 } 1075 1076 static void rxq_deinit(struct net_device *dev) 1077 { 1078 struct pxa168_eth_private *pep = netdev_priv(dev); 1079 int curr; 1080 1081 /* Free preallocated skb's on RX rings */ 1082 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { 1083 if (pep->rx_skb[curr]) { 1084 dev_kfree_skb(pep->rx_skb[curr]); 1085 pep->rx_desc_count--; 1086 } 1087 } 1088 if (pep->rx_desc_count) 1089 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n", 1090 pep->rx_desc_count); 1091 /* Free RX ring */ 1092 if (pep->p_rx_desc_area) 1093 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, 1094 pep->p_rx_desc_area, pep->rx_desc_dma); 1095 kfree(pep->rx_skb); 1096 } 1097 1098 static int txq_init(struct net_device *dev) 1099 { 1100 struct pxa168_eth_private *pep = netdev_priv(dev); 1101 struct tx_desc *p_tx_desc; 1102 int size = 0, i = 0; 1103 int tx_desc_num = pep->tx_ring_size; 1104 1105 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, 1106 GFP_KERNEL); 1107 if (!pep->tx_skb) 1108 return -ENOMEM; 1109 1110 /* Allocate TX ring */ 1111 pep->tx_desc_count = 0; 1112 size = pep->tx_ring_size * sizeof(struct tx_desc); 1113 pep->tx_desc_area_size = size; 1114 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1115 &pep->tx_desc_dma, 1116 GFP_KERNEL); 1117 if (!pep->p_tx_desc_area) 1118 goto out; 1119 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 1120 p_tx_desc = pep->p_tx_desc_area; 1121 for (i = 0; i < tx_desc_num; i++) { 1122 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + 1123 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); 1124 } 1125 pep->tx_curr_desc_q = 0; 1126 pep->tx_used_desc_q = 0; 1127 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); 1128 return 0; 1129 out: 1130 kfree(pep->tx_skb); 1131 return -ENOMEM; 1132 } 1133 1134 static void txq_deinit(struct net_device *dev) 1135 { 1136 struct pxa168_eth_private *pep = netdev_priv(dev); 1137 1138 /* Free outstanding skb's on TX ring */ 1139 txq_reclaim(dev, 1); 1140 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); 1141 /* Free TX ring */ 1142 if (pep->p_tx_desc_area) 1143 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, 1144 pep->p_tx_desc_area, pep->tx_desc_dma); 1145 kfree(pep->tx_skb); 1146 } 1147 1148 static int pxa168_eth_open(struct net_device *dev) 1149 { 1150 struct pxa168_eth_private *pep = netdev_priv(dev); 1151 int err; 1152 1153 err = pxa168_init_phy(dev); 1154 if (err) 1155 return err; 1156 1157 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev); 1158 if (err) { 1159 dev_err(&dev->dev, "can't assign irq\n"); 1160 return -EAGAIN; 1161 } 1162 pep->rx_resource_err = 0; 1163 err = rxq_init(dev); 1164 if (err != 0) 1165 goto out_free_irq; 1166 err = txq_init(dev); 1167 if (err != 0) 1168 goto out_free_rx_skb; 1169 pep->rx_used_desc_q = 0; 1170 pep->rx_curr_desc_q = 0; 1171 1172 /* Fill RX ring with skb's */ 1173 rxq_refill(dev); 1174 pep->rx_used_desc_q = 0; 1175 pep->rx_curr_desc_q = 0; 1176 netif_carrier_off(dev); 1177 napi_enable(&pep->napi); 1178 eth_port_start(dev); 1179 return 0; 1180 out_free_rx_skb: 1181 rxq_deinit(dev); 1182 out_free_irq: 1183 free_irq(dev->irq, dev); 1184 return err; 1185 } 1186 1187 static int pxa168_eth_stop(struct net_device *dev) 1188 { 1189 struct pxa168_eth_private *pep = netdev_priv(dev); 1190 eth_port_reset(dev); 1191 1192 /* Disable interrupts */ 1193 wrl(pep, INT_MASK, 0); 1194 wrl(pep, INT_CAUSE, 0); 1195 /* Write to ICR to clear interrupts. */ 1196 wrl(pep, INT_W_CLEAR, 0); 1197 napi_disable(&pep->napi); 1198 del_timer_sync(&pep->timeout); 1199 netif_carrier_off(dev); 1200 free_irq(dev->irq, dev); 1201 rxq_deinit(dev); 1202 txq_deinit(dev); 1203 1204 return 0; 1205 } 1206 1207 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) 1208 { 1209 int retval; 1210 struct pxa168_eth_private *pep = netdev_priv(dev); 1211 1212 if ((mtu > 9500) || (mtu < 68)) 1213 return -EINVAL; 1214 1215 dev->mtu = mtu; 1216 retval = set_port_config_ext(pep); 1217 1218 if (!netif_running(dev)) 1219 return 0; 1220 1221 /* 1222 * Stop and then re-open the interface. This will allocate RX 1223 * skbs of the new MTU. 1224 * There is a possible danger that the open will not succeed, 1225 * due to memory being full. 1226 */ 1227 pxa168_eth_stop(dev); 1228 if (pxa168_eth_open(dev)) { 1229 dev_err(&dev->dev, 1230 "fatal error on re-opening device after MTU change\n"); 1231 } 1232 1233 return 0; 1234 } 1235 1236 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) 1237 { 1238 int tx_desc_curr; 1239 1240 tx_desc_curr = pep->tx_curr_desc_q; 1241 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; 1242 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); 1243 pep->tx_desc_count++; 1244 1245 return tx_desc_curr; 1246 } 1247 1248 static int pxa168_rx_poll(struct napi_struct *napi, int budget) 1249 { 1250 struct pxa168_eth_private *pep = 1251 container_of(napi, struct pxa168_eth_private, napi); 1252 struct net_device *dev = pep->dev; 1253 int work_done = 0; 1254 1255 /* 1256 * We call txq_reclaim every time since in NAPI interupts are disabled 1257 * and due to this we miss the TX_DONE interrupt,which is not updated in 1258 * interrupt status register. 1259 */ 1260 txq_reclaim(dev, 0); 1261 if (netif_queue_stopped(dev) 1262 && pep->tx_ring_size - pep->tx_desc_count > 1) { 1263 netif_wake_queue(dev); 1264 } 1265 work_done = rxq_process(dev, budget); 1266 if (work_done < budget) { 1267 napi_complete(napi); 1268 wrl(pep, INT_MASK, ALL_INTS); 1269 } 1270 1271 return work_done; 1272 } 1273 1274 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1275 { 1276 struct pxa168_eth_private *pep = netdev_priv(dev); 1277 struct net_device_stats *stats = &dev->stats; 1278 struct tx_desc *desc; 1279 int tx_index; 1280 int length; 1281 1282 tx_index = eth_alloc_tx_desc_index(pep); 1283 desc = &pep->p_tx_desc_area[tx_index]; 1284 length = skb->len; 1285 pep->tx_skb[tx_index] = skb; 1286 desc->byte_cnt = length; 1287 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1288 1289 skb_tx_timestamp(skb); 1290 1291 dma_wmb(); 1292 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | 1293 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; 1294 wmb(); 1295 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); 1296 1297 stats->tx_bytes += length; 1298 stats->tx_packets++; 1299 netif_trans_update(dev); 1300 if (pep->tx_ring_size - pep->tx_desc_count <= 1) { 1301 /* We handled the current skb, but now we are out of space.*/ 1302 netif_stop_queue(dev); 1303 } 1304 1305 return NETDEV_TX_OK; 1306 } 1307 1308 static int smi_wait_ready(struct pxa168_eth_private *pep) 1309 { 1310 int i = 0; 1311 1312 /* wait for the SMI register to become available */ 1313 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { 1314 if (i == PHY_WAIT_ITERATIONS) 1315 return -ETIMEDOUT; 1316 msleep(10); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) 1323 { 1324 struct pxa168_eth_private *pep = bus->priv; 1325 int i = 0; 1326 int val; 1327 1328 if (smi_wait_ready(pep)) { 1329 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1330 return -ETIMEDOUT; 1331 } 1332 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); 1333 /* now wait for the data to be valid */ 1334 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { 1335 if (i == PHY_WAIT_ITERATIONS) { 1336 netdev_warn(pep->dev, 1337 "pxa168_eth: SMI bus read not valid\n"); 1338 return -ENODEV; 1339 } 1340 msleep(10); 1341 } 1342 1343 return val & 0xffff; 1344 } 1345 1346 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, 1347 u16 value) 1348 { 1349 struct pxa168_eth_private *pep = bus->priv; 1350 1351 if (smi_wait_ready(pep)) { 1352 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1353 return -ETIMEDOUT; 1354 } 1355 1356 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | 1357 SMI_OP_W | (value & 0xffff)); 1358 1359 if (smi_wait_ready(pep)) { 1360 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1361 return -ETIMEDOUT; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, 1368 int cmd) 1369 { 1370 if (dev->phydev != NULL) 1371 return phy_mii_ioctl(dev->phydev, ifr, cmd); 1372 1373 return -EOPNOTSUPP; 1374 } 1375 1376 static int pxa168_get_link_ksettings(struct net_device *dev, 1377 struct ethtool_link_ksettings *cmd) 1378 { 1379 int err; 1380 1381 err = phy_read_status(dev->phydev); 1382 if (err == 0) 1383 err = phy_ethtool_ksettings_get(dev->phydev, cmd); 1384 1385 return err; 1386 } 1387 1388 static void pxa168_get_drvinfo(struct net_device *dev, 1389 struct ethtool_drvinfo *info) 1390 { 1391 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); 1392 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 1393 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); 1394 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); 1395 } 1396 1397 static const struct ethtool_ops pxa168_ethtool_ops = { 1398 .get_drvinfo = pxa168_get_drvinfo, 1399 .get_link = ethtool_op_get_link, 1400 .get_ts_info = ethtool_op_get_ts_info, 1401 .get_link_ksettings = pxa168_get_link_ksettings, 1402 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1403 }; 1404 1405 static const struct net_device_ops pxa168_eth_netdev_ops = { 1406 .ndo_open = pxa168_eth_open, 1407 .ndo_stop = pxa168_eth_stop, 1408 .ndo_start_xmit = pxa168_eth_start_xmit, 1409 .ndo_set_rx_mode = pxa168_eth_set_rx_mode, 1410 .ndo_set_mac_address = pxa168_eth_set_mac_address, 1411 .ndo_validate_addr = eth_validate_addr, 1412 .ndo_do_ioctl = pxa168_eth_do_ioctl, 1413 .ndo_change_mtu = pxa168_eth_change_mtu, 1414 .ndo_tx_timeout = pxa168_eth_tx_timeout, 1415 }; 1416 1417 static int pxa168_eth_probe(struct platform_device *pdev) 1418 { 1419 struct pxa168_eth_private *pep = NULL; 1420 struct net_device *dev = NULL; 1421 struct resource *res; 1422 struct clk *clk; 1423 struct device_node *np; 1424 const unsigned char *mac_addr = NULL; 1425 int err; 1426 1427 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); 1428 1429 clk = devm_clk_get(&pdev->dev, NULL); 1430 if (IS_ERR(clk)) { 1431 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n"); 1432 return -ENODEV; 1433 } 1434 clk_prepare_enable(clk); 1435 1436 dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); 1437 if (!dev) { 1438 err = -ENOMEM; 1439 goto err_clk; 1440 } 1441 1442 platform_set_drvdata(pdev, dev); 1443 pep = netdev_priv(dev); 1444 pep->dev = dev; 1445 pep->clk = clk; 1446 1447 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1448 pep->base = devm_ioremap_resource(&pdev->dev, res); 1449 if (IS_ERR(pep->base)) { 1450 err = -ENOMEM; 1451 goto err_netdev; 1452 } 1453 1454 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1455 BUG_ON(!res); 1456 dev->irq = res->start; 1457 dev->netdev_ops = &pxa168_eth_netdev_ops; 1458 dev->watchdog_timeo = 2 * HZ; 1459 dev->base_addr = 0; 1460 dev->ethtool_ops = &pxa168_ethtool_ops; 1461 1462 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); 1463 1464 if (pdev->dev.of_node) 1465 mac_addr = of_get_mac_address(pdev->dev.of_node); 1466 1467 if (mac_addr && is_valid_ether_addr(mac_addr)) { 1468 ether_addr_copy(dev->dev_addr, mac_addr); 1469 } else { 1470 /* try reading the mac address, if set by the bootloader */ 1471 pxa168_eth_get_mac_address(dev, dev->dev_addr); 1472 if (!is_valid_ether_addr(dev->dev_addr)) { 1473 dev_info(&pdev->dev, "Using random mac address\n"); 1474 eth_hw_addr_random(dev); 1475 } 1476 } 1477 1478 pep->rx_ring_size = NUM_RX_DESCS; 1479 pep->tx_ring_size = NUM_TX_DESCS; 1480 1481 pep->pd = dev_get_platdata(&pdev->dev); 1482 if (pep->pd) { 1483 if (pep->pd->rx_queue_size) 1484 pep->rx_ring_size = pep->pd->rx_queue_size; 1485 1486 if (pep->pd->tx_queue_size) 1487 pep->tx_ring_size = pep->pd->tx_queue_size; 1488 1489 pep->port_num = pep->pd->port_number; 1490 pep->phy_addr = pep->pd->phy_addr; 1491 pep->phy_speed = pep->pd->speed; 1492 pep->phy_duplex = pep->pd->duplex; 1493 pep->phy_intf = pep->pd->intf; 1494 1495 if (pep->pd->init) 1496 pep->pd->init(); 1497 } else if (pdev->dev.of_node) { 1498 of_property_read_u32(pdev->dev.of_node, "port-id", 1499 &pep->port_num); 1500 1501 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1502 if (!np) { 1503 dev_err(&pdev->dev, "missing phy-handle\n"); 1504 err = -EINVAL; 1505 goto err_netdev; 1506 } 1507 of_property_read_u32(np, "reg", &pep->phy_addr); 1508 pep->phy_intf = of_get_phy_mode(pdev->dev.of_node); 1509 of_node_put(np); 1510 } 1511 1512 /* Hardware supports only 3 ports */ 1513 BUG_ON(pep->port_num > 2); 1514 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); 1515 1516 memset(&pep->timeout, 0, sizeof(struct timer_list)); 1517 init_timer(&pep->timeout); 1518 pep->timeout.function = rxq_refill_timer_wrapper; 1519 pep->timeout.data = (unsigned long)pep; 1520 1521 pep->smi_bus = mdiobus_alloc(); 1522 if (pep->smi_bus == NULL) { 1523 err = -ENOMEM; 1524 goto err_netdev; 1525 } 1526 pep->smi_bus->priv = pep; 1527 pep->smi_bus->name = "pxa168_eth smi"; 1528 pep->smi_bus->read = pxa168_smi_read; 1529 pep->smi_bus->write = pxa168_smi_write; 1530 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1531 pdev->name, pdev->id); 1532 pep->smi_bus->parent = &pdev->dev; 1533 pep->smi_bus->phy_mask = 0xffffffff; 1534 err = mdiobus_register(pep->smi_bus); 1535 if (err) 1536 goto err_free_mdio; 1537 1538 SET_NETDEV_DEV(dev, &pdev->dev); 1539 pxa168_init_hw(pep); 1540 err = register_netdev(dev); 1541 if (err) 1542 goto err_mdiobus; 1543 return 0; 1544 1545 err_mdiobus: 1546 mdiobus_unregister(pep->smi_bus); 1547 err_free_mdio: 1548 mdiobus_free(pep->smi_bus); 1549 err_netdev: 1550 free_netdev(dev); 1551 err_clk: 1552 clk_disable_unprepare(clk); 1553 return err; 1554 } 1555 1556 static int pxa168_eth_remove(struct platform_device *pdev) 1557 { 1558 struct net_device *dev = platform_get_drvdata(pdev); 1559 struct pxa168_eth_private *pep = netdev_priv(dev); 1560 1561 if (pep->htpr) { 1562 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, 1563 pep->htpr, pep->htpr_dma); 1564 pep->htpr = NULL; 1565 } 1566 if (dev->phydev) 1567 phy_disconnect(dev->phydev); 1568 if (pep->clk) { 1569 clk_disable_unprepare(pep->clk); 1570 } 1571 1572 mdiobus_unregister(pep->smi_bus); 1573 mdiobus_free(pep->smi_bus); 1574 unregister_netdev(dev); 1575 cancel_work_sync(&pep->tx_timeout_task); 1576 free_netdev(dev); 1577 return 0; 1578 } 1579 1580 static void pxa168_eth_shutdown(struct platform_device *pdev) 1581 { 1582 struct net_device *dev = platform_get_drvdata(pdev); 1583 eth_port_reset(dev); 1584 } 1585 1586 #ifdef CONFIG_PM 1587 static int pxa168_eth_resume(struct platform_device *pdev) 1588 { 1589 return -ENOSYS; 1590 } 1591 1592 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) 1593 { 1594 return -ENOSYS; 1595 } 1596 1597 #else 1598 #define pxa168_eth_resume NULL 1599 #define pxa168_eth_suspend NULL 1600 #endif 1601 1602 static const struct of_device_id pxa168_eth_of_match[] = { 1603 { .compatible = "marvell,pxa168-eth" }, 1604 { }, 1605 }; 1606 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match); 1607 1608 static struct platform_driver pxa168_eth_driver = { 1609 .probe = pxa168_eth_probe, 1610 .remove = pxa168_eth_remove, 1611 .shutdown = pxa168_eth_shutdown, 1612 .resume = pxa168_eth_resume, 1613 .suspend = pxa168_eth_suspend, 1614 .driver = { 1615 .name = DRIVER_NAME, 1616 .of_match_table = of_match_ptr(pxa168_eth_of_match), 1617 }, 1618 }; 1619 1620 module_platform_driver(pxa168_eth_driver); 1621 1622 MODULE_LICENSE("GPL"); 1623 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); 1624 MODULE_ALIAS("platform:pxa168_eth"); 1625