1 /* 2 * PXA168 ethernet driver. 3 * Most of the code is derived from mv643xx ethernet driver. 4 * 5 * Copyright (C) 2010 Marvell International Ltd. 6 * Sachin Sanap <ssanap@marvell.com> 7 * Zhangfei Gao <zgao6@marvell.com> 8 * Philip Rakity <prakity@marvell.com> 9 * Mark Brown <markb@marvell.com> 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * as published by the Free Software Foundation; either version 2 14 * of the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include <linux/bitops.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/dma-mapping.h> 29 #include <linux/etherdevice.h> 30 #include <linux/ethtool.h> 31 #include <linux/in.h> 32 #include <linux/interrupt.h> 33 #include <linux/io.h> 34 #include <linux/ip.h> 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of.h> 38 #include <linux/of_net.h> 39 #include <linux/phy.h> 40 #include <linux/platform_device.h> 41 #include <linux/pxa168_eth.h> 42 #include <linux/tcp.h> 43 #include <linux/types.h> 44 #include <linux/udp.h> 45 #include <linux/workqueue.h> 46 47 #include <asm/pgtable.h> 48 #include <asm/cacheflush.h> 49 50 #define DRIVER_NAME "pxa168-eth" 51 #define DRIVER_VERSION "0.3" 52 53 /* 54 * Registers 55 */ 56 57 #define PHY_ADDRESS 0x0000 58 #define SMI 0x0010 59 #define PORT_CONFIG 0x0400 60 #define PORT_CONFIG_EXT 0x0408 61 #define PORT_COMMAND 0x0410 62 #define PORT_STATUS 0x0418 63 #define HTPR 0x0428 64 #define MAC_ADDR_LOW 0x0430 65 #define MAC_ADDR_HIGH 0x0438 66 #define SDMA_CONFIG 0x0440 67 #define SDMA_CMD 0x0448 68 #define INT_CAUSE 0x0450 69 #define INT_W_CLEAR 0x0454 70 #define INT_MASK 0x0458 71 #define ETH_F_RX_DESC_0 0x0480 72 #define ETH_C_RX_DESC_0 0x04A0 73 #define ETH_C_TX_DESC_1 0x04E4 74 75 /* smi register */ 76 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */ 77 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */ 78 #define SMI_OP_W (0 << 26) /* Write operation */ 79 #define SMI_OP_R (1 << 26) /* Read operation */ 80 81 #define PHY_WAIT_ITERATIONS 10 82 83 #define PXA168_ETH_PHY_ADDR_DEFAULT 0 84 /* RX & TX descriptor command */ 85 #define BUF_OWNED_BY_DMA (1 << 31) 86 87 /* RX descriptor status */ 88 #define RX_EN_INT (1 << 23) 89 #define RX_FIRST_DESC (1 << 17) 90 #define RX_LAST_DESC (1 << 16) 91 #define RX_ERROR (1 << 15) 92 93 /* TX descriptor command */ 94 #define TX_EN_INT (1 << 23) 95 #define TX_GEN_CRC (1 << 22) 96 #define TX_ZERO_PADDING (1 << 18) 97 #define TX_FIRST_DESC (1 << 17) 98 #define TX_LAST_DESC (1 << 16) 99 #define TX_ERROR (1 << 15) 100 101 /* SDMA_CMD */ 102 #define SDMA_CMD_AT (1 << 31) 103 #define SDMA_CMD_TXDL (1 << 24) 104 #define SDMA_CMD_TXDH (1 << 23) 105 #define SDMA_CMD_AR (1 << 15) 106 #define SDMA_CMD_ERD (1 << 7) 107 108 /* Bit definitions of the Port Config Reg */ 109 #define PCR_DUPLEX_FULL (1 << 15) 110 #define PCR_HS (1 << 12) 111 #define PCR_EN (1 << 7) 112 #define PCR_PM (1 << 0) 113 114 /* Bit definitions of the Port Config Extend Reg */ 115 #define PCXR_2BSM (1 << 28) 116 #define PCXR_DSCP_EN (1 << 21) 117 #define PCXR_RMII_EN (1 << 20) 118 #define PCXR_AN_SPEED_DIS (1 << 19) 119 #define PCXR_SPEED_100 (1 << 18) 120 #define PCXR_MFL_1518 (0 << 14) 121 #define PCXR_MFL_1536 (1 << 14) 122 #define PCXR_MFL_2048 (2 << 14) 123 #define PCXR_MFL_64K (3 << 14) 124 #define PCXR_FLOWCTL_DIS (1 << 12) 125 #define PCXR_FLP (1 << 11) 126 #define PCXR_AN_FLOWCTL_DIS (1 << 10) 127 #define PCXR_AN_DUPLEX_DIS (1 << 9) 128 #define PCXR_PRIO_TX_OFF 3 129 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF) 130 131 /* Bit definitions of the SDMA Config Reg */ 132 #define SDCR_BSZ_OFF 12 133 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF) 134 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF) 135 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF) 136 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF) 137 #define SDCR_BLMR (1 << 6) 138 #define SDCR_BLMT (1 << 7) 139 #define SDCR_RIFB (1 << 9) 140 #define SDCR_RC_OFF 2 141 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF) 142 143 /* 144 * Bit definitions of the Interrupt Cause Reg 145 * and Interrupt MASK Reg is the same 146 */ 147 #define ICR_RXBUF (1 << 0) 148 #define ICR_TXBUF_H (1 << 2) 149 #define ICR_TXBUF_L (1 << 3) 150 #define ICR_TXEND_H (1 << 6) 151 #define ICR_TXEND_L (1 << 7) 152 #define ICR_RXERR (1 << 8) 153 #define ICR_TXERR_H (1 << 10) 154 #define ICR_TXERR_L (1 << 11) 155 #define ICR_TX_UDR (1 << 13) 156 #define ICR_MII_CH (1 << 28) 157 158 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\ 159 ICR_TXERR_H | ICR_TXERR_L |\ 160 ICR_TXEND_H | ICR_TXEND_L |\ 161 ICR_RXBUF | ICR_RXERR | ICR_MII_CH) 162 163 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ 164 165 #define NUM_RX_DESCS 64 166 #define NUM_TX_DESCS 64 167 168 #define HASH_ADD 0 169 #define HASH_DELETE 1 170 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */ 171 #define HOP_NUMBER 12 172 173 /* Bit definitions for Port status */ 174 #define PORT_SPEED_100 (1 << 0) 175 #define FULL_DUPLEX (1 << 1) 176 #define FLOW_CONTROL_DISABLED (1 << 2) 177 #define LINK_UP (1 << 3) 178 179 /* Bit definitions for work to be done */ 180 #define WORK_TX_DONE (1 << 1) 181 182 /* 183 * Misc definitions. 184 */ 185 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES) 186 187 struct rx_desc { 188 u32 cmd_sts; /* Descriptor command status */ 189 u16 byte_cnt; /* Descriptor buffer byte count */ 190 u16 buf_size; /* Buffer size */ 191 u32 buf_ptr; /* Descriptor buffer pointer */ 192 u32 next_desc_ptr; /* Next descriptor pointer */ 193 }; 194 195 struct tx_desc { 196 u32 cmd_sts; /* Command/status field */ 197 u16 reserved; 198 u16 byte_cnt; /* buffer byte count */ 199 u32 buf_ptr; /* pointer to buffer for this descriptor */ 200 u32 next_desc_ptr; /* Pointer to next descriptor */ 201 }; 202 203 struct pxa168_eth_private { 204 int port_num; /* User Ethernet port number */ 205 int phy_addr; 206 int phy_speed; 207 int phy_duplex; 208 phy_interface_t phy_intf; 209 210 int rx_resource_err; /* Rx ring resource error flag */ 211 212 /* Next available and first returning Rx resource */ 213 int rx_curr_desc_q, rx_used_desc_q; 214 215 /* Next available and first returning Tx resource */ 216 int tx_curr_desc_q, tx_used_desc_q; 217 218 struct rx_desc *p_rx_desc_area; 219 dma_addr_t rx_desc_dma; 220 int rx_desc_area_size; 221 struct sk_buff **rx_skb; 222 223 struct tx_desc *p_tx_desc_area; 224 dma_addr_t tx_desc_dma; 225 int tx_desc_area_size; 226 struct sk_buff **tx_skb; 227 228 struct work_struct tx_timeout_task; 229 230 struct net_device *dev; 231 struct napi_struct napi; 232 u8 work_todo; 233 int skb_size; 234 235 /* Size of Tx Ring per queue */ 236 int tx_ring_size; 237 /* Number of tx descriptors in use */ 238 int tx_desc_count; 239 /* Size of Rx Ring per queue */ 240 int rx_ring_size; 241 /* Number of rx descriptors in use */ 242 int rx_desc_count; 243 244 /* 245 * Used in case RX Ring is empty, which can occur when 246 * system does not have resources (skb's) 247 */ 248 struct timer_list timeout; 249 struct mii_bus *smi_bus; 250 struct phy_device *phy; 251 252 /* clock */ 253 struct clk *clk; 254 struct pxa168_eth_platform_data *pd; 255 /* 256 * Ethernet controller base address. 257 */ 258 void __iomem *base; 259 260 /* Pointer to the hardware address filter table */ 261 void *htpr; 262 dma_addr_t htpr_dma; 263 }; 264 265 struct addr_table_entry { 266 __le32 lo; 267 __le32 hi; 268 }; 269 270 /* Bit fields of a Hash Table Entry */ 271 enum hash_table_entry { 272 HASH_ENTRY_VALID = 1, 273 SKIP = 2, 274 HASH_ENTRY_RECEIVE_DISCARD = 4, 275 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2 276 }; 277 278 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd); 279 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd); 280 static int pxa168_init_hw(struct pxa168_eth_private *pep); 281 static int pxa168_init_phy(struct net_device *dev); 282 static void eth_port_reset(struct net_device *dev); 283 static void eth_port_start(struct net_device *dev); 284 static int pxa168_eth_open(struct net_device *dev); 285 static int pxa168_eth_stop(struct net_device *dev); 286 287 static inline u32 rdl(struct pxa168_eth_private *pep, int offset) 288 { 289 return readl(pep->base + offset); 290 } 291 292 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) 293 { 294 writel(data, pep->base + offset); 295 } 296 297 static void abort_dma(struct pxa168_eth_private *pep) 298 { 299 int delay; 300 int max_retries = 40; 301 302 do { 303 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); 304 udelay(100); 305 306 delay = 10; 307 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT)) 308 && delay-- > 0) { 309 udelay(10); 310 } 311 } while (max_retries-- > 0 && delay <= 0); 312 313 if (max_retries <= 0) 314 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__); 315 } 316 317 static void rxq_refill(struct net_device *dev) 318 { 319 struct pxa168_eth_private *pep = netdev_priv(dev); 320 struct sk_buff *skb; 321 struct rx_desc *p_used_rx_desc; 322 int used_rx_desc; 323 324 while (pep->rx_desc_count < pep->rx_ring_size) { 325 int size; 326 327 skb = netdev_alloc_skb(dev, pep->skb_size); 328 if (!skb) 329 break; 330 if (SKB_DMA_REALIGN) 331 skb_reserve(skb, SKB_DMA_REALIGN); 332 pep->rx_desc_count++; 333 /* Get 'used' Rx descriptor */ 334 used_rx_desc = pep->rx_used_desc_q; 335 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc]; 336 size = skb_end_pointer(skb) - skb->data; 337 p_used_rx_desc->buf_ptr = dma_map_single(NULL, 338 skb->data, 339 size, 340 DMA_FROM_DEVICE); 341 p_used_rx_desc->buf_size = size; 342 pep->rx_skb[used_rx_desc] = skb; 343 344 /* Return the descriptor to DMA ownership */ 345 wmb(); 346 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT; 347 wmb(); 348 349 /* Move the used descriptor pointer to the next descriptor */ 350 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size; 351 352 /* Any Rx return cancels the Rx resource error status */ 353 pep->rx_resource_err = 0; 354 355 skb_reserve(skb, ETH_HW_IP_ALIGN); 356 } 357 358 /* 359 * If RX ring is empty of SKB, set a timer to try allocating 360 * again at a later time. 361 */ 362 if (pep->rx_desc_count == 0) { 363 pep->timeout.expires = jiffies + (HZ / 10); 364 add_timer(&pep->timeout); 365 } 366 } 367 368 static inline void rxq_refill_timer_wrapper(unsigned long data) 369 { 370 struct pxa168_eth_private *pep = (void *)data; 371 napi_schedule(&pep->napi); 372 } 373 374 static inline u8 flip_8_bits(u8 x) 375 { 376 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1) 377 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3) 378 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1) 379 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3); 380 } 381 382 static void nibble_swap_every_byte(unsigned char *mac_addr) 383 { 384 int i; 385 for (i = 0; i < ETH_ALEN; i++) { 386 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) | 387 ((mac_addr[i] & 0xf0) >> 4); 388 } 389 } 390 391 static void inverse_every_nibble(unsigned char *mac_addr) 392 { 393 int i; 394 for (i = 0; i < ETH_ALEN; i++) 395 mac_addr[i] = flip_8_bits(mac_addr[i]); 396 } 397 398 /* 399 * ---------------------------------------------------------------------------- 400 * This function will calculate the hash function of the address. 401 * Inputs 402 * mac_addr_orig - MAC address. 403 * Outputs 404 * return the calculated entry. 405 */ 406 static u32 hash_function(unsigned char *mac_addr_orig) 407 { 408 u32 hash_result; 409 u32 addr0; 410 u32 addr1; 411 u32 addr2; 412 u32 addr3; 413 unsigned char mac_addr[ETH_ALEN]; 414 415 /* Make a copy of MAC address since we are going to performe bit 416 * operations on it 417 */ 418 memcpy(mac_addr, mac_addr_orig, ETH_ALEN); 419 420 nibble_swap_every_byte(mac_addr); 421 inverse_every_nibble(mac_addr); 422 423 addr0 = (mac_addr[5] >> 2) & 0x3f; 424 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2); 425 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1; 426 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8); 427 428 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3); 429 hash_result = hash_result & 0x07ff; 430 return hash_result; 431 } 432 433 /* 434 * ---------------------------------------------------------------------------- 435 * This function will add/del an entry to the address table. 436 * Inputs 437 * pep - ETHERNET . 438 * mac_addr - MAC address. 439 * skip - if 1, skip this address.Used in case of deleting an entry which is a 440 * part of chain in the hash table.We can't just delete the entry since 441 * that will break the chain.We need to defragment the tables time to 442 * time. 443 * rd - 0 Discard packet upon match. 444 * - 1 Receive packet upon match. 445 * Outputs 446 * address table entry is added/deleted. 447 * 0 if success. 448 * -ENOSPC if table full 449 */ 450 static int add_del_hash_entry(struct pxa168_eth_private *pep, 451 unsigned char *mac_addr, 452 u32 rd, u32 skip, int del) 453 { 454 struct addr_table_entry *entry, *start; 455 u32 new_high; 456 u32 new_low; 457 u32 i; 458 459 new_low = (((mac_addr[1] >> 4) & 0xf) << 15) 460 | (((mac_addr[1] >> 0) & 0xf) << 11) 461 | (((mac_addr[0] >> 4) & 0xf) << 7) 462 | (((mac_addr[0] >> 0) & 0xf) << 3) 463 | (((mac_addr[3] >> 4) & 0x1) << 31) 464 | (((mac_addr[3] >> 0) & 0xf) << 27) 465 | (((mac_addr[2] >> 4) & 0xf) << 23) 466 | (((mac_addr[2] >> 0) & 0xf) << 19) 467 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT) 468 | HASH_ENTRY_VALID; 469 470 new_high = (((mac_addr[5] >> 4) & 0xf) << 15) 471 | (((mac_addr[5] >> 0) & 0xf) << 11) 472 | (((mac_addr[4] >> 4) & 0xf) << 7) 473 | (((mac_addr[4] >> 0) & 0xf) << 3) 474 | (((mac_addr[3] >> 5) & 0x7) << 0); 475 476 /* 477 * Pick the appropriate table, start scanning for free/reusable 478 * entries at the index obtained by hashing the specified MAC address 479 */ 480 start = pep->htpr; 481 entry = start + hash_function(mac_addr); 482 for (i = 0; i < HOP_NUMBER; i++) { 483 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) { 484 break; 485 } else { 486 /* if same address put in same position */ 487 if (((le32_to_cpu(entry->lo) & 0xfffffff8) == 488 (new_low & 0xfffffff8)) && 489 (le32_to_cpu(entry->hi) == new_high)) { 490 break; 491 } 492 } 493 if (entry == start + 0x7ff) 494 entry = start; 495 else 496 entry++; 497 } 498 499 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) && 500 (le32_to_cpu(entry->hi) != new_high) && del) 501 return 0; 502 503 if (i == HOP_NUMBER) { 504 if (!del) { 505 netdev_info(pep->dev, 506 "%s: table section is full, need to " 507 "move to 16kB implementation?\n", 508 __FILE__); 509 return -ENOSPC; 510 } else 511 return 0; 512 } 513 514 /* 515 * Update the selected entry 516 */ 517 if (del) { 518 entry->hi = 0; 519 entry->lo = 0; 520 } else { 521 entry->hi = cpu_to_le32(new_high); 522 entry->lo = cpu_to_le32(new_low); 523 } 524 525 return 0; 526 } 527 528 /* 529 * ---------------------------------------------------------------------------- 530 * Create an addressTable entry from MAC address info 531 * found in the specifed net_device struct 532 * 533 * Input : pointer to ethernet interface network device structure 534 * Output : N/A 535 */ 536 static void update_hash_table_mac_address(struct pxa168_eth_private *pep, 537 unsigned char *oaddr, 538 unsigned char *addr) 539 { 540 /* Delete old entry */ 541 if (oaddr) 542 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE); 543 /* Add new entry */ 544 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD); 545 } 546 547 static int init_hash_table(struct pxa168_eth_private *pep) 548 { 549 /* 550 * Hardware expects CPU to build a hash table based on a predefined 551 * hash function and populate it based on hardware address. The 552 * location of the hash table is identified by 32-bit pointer stored 553 * in HTPR internal register. Two possible sizes exists for the hash 554 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB 555 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support 556 * 1/2kB. 557 */ 558 /* TODO: Add support for 8kB hash table and alternative hash 559 * function.Driver can dynamically switch to them if the 1/2kB hash 560 * table is full. 561 */ 562 if (pep->htpr == NULL) { 563 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent, 564 HASH_ADDR_TABLE_SIZE, 565 &pep->htpr_dma, GFP_KERNEL); 566 if (pep->htpr == NULL) 567 return -ENOMEM; 568 } else { 569 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 570 } 571 wrl(pep, HTPR, pep->htpr_dma); 572 return 0; 573 } 574 575 static void pxa168_eth_set_rx_mode(struct net_device *dev) 576 { 577 struct pxa168_eth_private *pep = netdev_priv(dev); 578 struct netdev_hw_addr *ha; 579 u32 val; 580 581 val = rdl(pep, PORT_CONFIG); 582 if (dev->flags & IFF_PROMISC) 583 val |= PCR_PM; 584 else 585 val &= ~PCR_PM; 586 wrl(pep, PORT_CONFIG, val); 587 588 /* 589 * Remove the old list of MAC address and add dev->addr 590 * and multicast address. 591 */ 592 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE); 593 update_hash_table_mac_address(pep, NULL, dev->dev_addr); 594 595 netdev_for_each_mc_addr(ha, dev) 596 update_hash_table_mac_address(pep, NULL, ha->addr); 597 } 598 599 static void pxa168_eth_get_mac_address(struct net_device *dev, 600 unsigned char *addr) 601 { 602 struct pxa168_eth_private *pep = netdev_priv(dev); 603 unsigned int mac_h = rdl(pep, MAC_ADDR_HIGH); 604 unsigned int mac_l = rdl(pep, MAC_ADDR_LOW); 605 606 addr[0] = (mac_h >> 24) & 0xff; 607 addr[1] = (mac_h >> 16) & 0xff; 608 addr[2] = (mac_h >> 8) & 0xff; 609 addr[3] = mac_h & 0xff; 610 addr[4] = (mac_l >> 8) & 0xff; 611 addr[5] = mac_l & 0xff; 612 } 613 614 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr) 615 { 616 struct sockaddr *sa = addr; 617 struct pxa168_eth_private *pep = netdev_priv(dev); 618 unsigned char oldMac[ETH_ALEN]; 619 u32 mac_h, mac_l; 620 621 if (!is_valid_ether_addr(sa->sa_data)) 622 return -EADDRNOTAVAIL; 623 memcpy(oldMac, dev->dev_addr, ETH_ALEN); 624 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN); 625 626 mac_h = dev->dev_addr[0] << 24; 627 mac_h |= dev->dev_addr[1] << 16; 628 mac_h |= dev->dev_addr[2] << 8; 629 mac_h |= dev->dev_addr[3]; 630 mac_l = dev->dev_addr[4] << 8; 631 mac_l |= dev->dev_addr[5]; 632 wrl(pep, MAC_ADDR_HIGH, mac_h); 633 wrl(pep, MAC_ADDR_LOW, mac_l); 634 635 netif_addr_lock_bh(dev); 636 update_hash_table_mac_address(pep, oldMac, dev->dev_addr); 637 netif_addr_unlock_bh(dev); 638 return 0; 639 } 640 641 static void eth_port_start(struct net_device *dev) 642 { 643 unsigned int val = 0; 644 struct pxa168_eth_private *pep = netdev_priv(dev); 645 int tx_curr_desc, rx_curr_desc; 646 647 phy_start(pep->phy); 648 649 /* Assignment of Tx CTRP of given queue */ 650 tx_curr_desc = pep->tx_curr_desc_q; 651 wrl(pep, ETH_C_TX_DESC_1, 652 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc))); 653 654 /* Assignment of Rx CRDP of given queue */ 655 rx_curr_desc = pep->rx_curr_desc_q; 656 wrl(pep, ETH_C_RX_DESC_0, 657 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 658 659 wrl(pep, ETH_F_RX_DESC_0, 660 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc))); 661 662 /* Clear all interrupts */ 663 wrl(pep, INT_CAUSE, 0); 664 665 /* Enable all interrupts for receive, transmit and error. */ 666 wrl(pep, INT_MASK, ALL_INTS); 667 668 val = rdl(pep, PORT_CONFIG); 669 val |= PCR_EN; 670 wrl(pep, PORT_CONFIG, val); 671 672 /* Start RX DMA engine */ 673 val = rdl(pep, SDMA_CMD); 674 val |= SDMA_CMD_ERD; 675 wrl(pep, SDMA_CMD, val); 676 } 677 678 static void eth_port_reset(struct net_device *dev) 679 { 680 struct pxa168_eth_private *pep = netdev_priv(dev); 681 unsigned int val = 0; 682 683 /* Stop all interrupts for receive, transmit and error. */ 684 wrl(pep, INT_MASK, 0); 685 686 /* Clear all interrupts */ 687 wrl(pep, INT_CAUSE, 0); 688 689 /* Stop RX DMA */ 690 val = rdl(pep, SDMA_CMD); 691 val &= ~SDMA_CMD_ERD; /* abort dma command */ 692 693 /* Abort any transmit and receive operations and put DMA 694 * in idle state. 695 */ 696 abort_dma(pep); 697 698 /* Disable port */ 699 val = rdl(pep, PORT_CONFIG); 700 val &= ~PCR_EN; 701 wrl(pep, PORT_CONFIG, val); 702 703 phy_stop(pep->phy); 704 } 705 706 /* 707 * txq_reclaim - Free the tx desc data for completed descriptors 708 * If force is non-zero, frees uncompleted descriptors as well 709 */ 710 static int txq_reclaim(struct net_device *dev, int force) 711 { 712 struct pxa168_eth_private *pep = netdev_priv(dev); 713 struct tx_desc *desc; 714 u32 cmd_sts; 715 struct sk_buff *skb; 716 int tx_index; 717 dma_addr_t addr; 718 int count; 719 int released = 0; 720 721 netif_tx_lock(dev); 722 723 pep->work_todo &= ~WORK_TX_DONE; 724 while (pep->tx_desc_count > 0) { 725 tx_index = pep->tx_used_desc_q; 726 desc = &pep->p_tx_desc_area[tx_index]; 727 cmd_sts = desc->cmd_sts; 728 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) { 729 if (released > 0) { 730 goto txq_reclaim_end; 731 } else { 732 released = -1; 733 goto txq_reclaim_end; 734 } 735 } 736 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size; 737 pep->tx_desc_count--; 738 addr = desc->buf_ptr; 739 count = desc->byte_cnt; 740 skb = pep->tx_skb[tx_index]; 741 if (skb) 742 pep->tx_skb[tx_index] = NULL; 743 744 if (cmd_sts & TX_ERROR) { 745 if (net_ratelimit()) 746 netdev_err(dev, "Error in TX\n"); 747 dev->stats.tx_errors++; 748 } 749 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE); 750 if (skb) 751 dev_kfree_skb_irq(skb); 752 released++; 753 } 754 txq_reclaim_end: 755 netif_tx_unlock(dev); 756 return released; 757 } 758 759 static void pxa168_eth_tx_timeout(struct net_device *dev) 760 { 761 struct pxa168_eth_private *pep = netdev_priv(dev); 762 763 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count); 764 765 schedule_work(&pep->tx_timeout_task); 766 } 767 768 static void pxa168_eth_tx_timeout_task(struct work_struct *work) 769 { 770 struct pxa168_eth_private *pep = container_of(work, 771 struct pxa168_eth_private, 772 tx_timeout_task); 773 struct net_device *dev = pep->dev; 774 pxa168_eth_stop(dev); 775 pxa168_eth_open(dev); 776 } 777 778 static int rxq_process(struct net_device *dev, int budget) 779 { 780 struct pxa168_eth_private *pep = netdev_priv(dev); 781 struct net_device_stats *stats = &dev->stats; 782 unsigned int received_packets = 0; 783 struct sk_buff *skb; 784 785 while (budget-- > 0) { 786 int rx_next_curr_desc, rx_curr_desc, rx_used_desc; 787 struct rx_desc *rx_desc; 788 unsigned int cmd_sts; 789 790 /* Do not process Rx ring in case of Rx ring resource error */ 791 if (pep->rx_resource_err) 792 break; 793 rx_curr_desc = pep->rx_curr_desc_q; 794 rx_used_desc = pep->rx_used_desc_q; 795 rx_desc = &pep->p_rx_desc_area[rx_curr_desc]; 796 cmd_sts = rx_desc->cmd_sts; 797 rmb(); 798 if (cmd_sts & (BUF_OWNED_BY_DMA)) 799 break; 800 skb = pep->rx_skb[rx_curr_desc]; 801 pep->rx_skb[rx_curr_desc] = NULL; 802 803 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size; 804 pep->rx_curr_desc_q = rx_next_curr_desc; 805 806 /* Rx descriptors exhausted. */ 807 /* Set the Rx ring resource error flag */ 808 if (rx_next_curr_desc == rx_used_desc) 809 pep->rx_resource_err = 1; 810 pep->rx_desc_count--; 811 dma_unmap_single(NULL, rx_desc->buf_ptr, 812 rx_desc->buf_size, 813 DMA_FROM_DEVICE); 814 received_packets++; 815 /* 816 * Update statistics. 817 * Note byte count includes 4 byte CRC count 818 */ 819 stats->rx_packets++; 820 stats->rx_bytes += rx_desc->byte_cnt; 821 /* 822 * In case received a packet without first / last bits on OR 823 * the error summary bit is on, the packets needs to be droped. 824 */ 825 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 826 (RX_FIRST_DESC | RX_LAST_DESC)) 827 || (cmd_sts & RX_ERROR)) { 828 829 stats->rx_dropped++; 830 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) != 831 (RX_FIRST_DESC | RX_LAST_DESC)) { 832 if (net_ratelimit()) 833 netdev_err(dev, 834 "Rx pkt on multiple desc\n"); 835 } 836 if (cmd_sts & RX_ERROR) 837 stats->rx_errors++; 838 dev_kfree_skb_irq(skb); 839 } else { 840 /* 841 * The -4 is for the CRC in the trailer of the 842 * received packet 843 */ 844 skb_put(skb, rx_desc->byte_cnt - 4); 845 skb->protocol = eth_type_trans(skb, dev); 846 netif_receive_skb(skb); 847 } 848 } 849 /* Fill RX ring with skb's */ 850 rxq_refill(dev); 851 return received_packets; 852 } 853 854 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep, 855 struct net_device *dev) 856 { 857 u32 icr; 858 int ret = 0; 859 860 icr = rdl(pep, INT_CAUSE); 861 if (icr == 0) 862 return IRQ_NONE; 863 864 wrl(pep, INT_CAUSE, ~icr); 865 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) { 866 pep->work_todo |= WORK_TX_DONE; 867 ret = 1; 868 } 869 if (icr & ICR_RXBUF) 870 ret = 1; 871 return ret; 872 } 873 874 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id) 875 { 876 struct net_device *dev = (struct net_device *)dev_id; 877 struct pxa168_eth_private *pep = netdev_priv(dev); 878 879 if (unlikely(!pxa168_eth_collect_events(pep, dev))) 880 return IRQ_NONE; 881 /* Disable interrupts */ 882 wrl(pep, INT_MASK, 0); 883 napi_schedule(&pep->napi); 884 return IRQ_HANDLED; 885 } 886 887 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep) 888 { 889 int skb_size; 890 891 /* 892 * Reserve 2+14 bytes for an ethernet header (the hardware 893 * automatically prepends 2 bytes of dummy data to each 894 * received packet), 16 bytes for up to four VLAN tags, and 895 * 4 bytes for the trailing FCS -- 36 bytes total. 896 */ 897 skb_size = pep->dev->mtu + 36; 898 899 /* 900 * Make sure that the skb size is a multiple of 8 bytes, as 901 * the lower three bits of the receive descriptor's buffer 902 * size field are ignored by the hardware. 903 */ 904 pep->skb_size = (skb_size + 7) & ~7; 905 906 /* 907 * If NET_SKB_PAD is smaller than a cache line, 908 * netdev_alloc_skb() will cause skb->data to be misaligned 909 * to a cache line boundary. If this is the case, include 910 * some extra space to allow re-aligning the data area. 911 */ 912 pep->skb_size += SKB_DMA_REALIGN; 913 914 } 915 916 static int set_port_config_ext(struct pxa168_eth_private *pep) 917 { 918 int skb_size; 919 920 pxa168_eth_recalc_skb_size(pep); 921 if (pep->skb_size <= 1518) 922 skb_size = PCXR_MFL_1518; 923 else if (pep->skb_size <= 1536) 924 skb_size = PCXR_MFL_1536; 925 else if (pep->skb_size <= 2048) 926 skb_size = PCXR_MFL_2048; 927 else 928 skb_size = PCXR_MFL_64K; 929 930 /* Extended Port Configuration */ 931 wrl(pep, PORT_CONFIG_EXT, 932 PCXR_AN_SPEED_DIS | /* Disable HW AN */ 933 PCXR_AN_DUPLEX_DIS | 934 PCXR_AN_FLOWCTL_DIS | 935 PCXR_2BSM | /* Two byte prefix aligns IP hdr */ 936 PCXR_DSCP_EN | /* Enable DSCP in IP */ 937 skb_size | PCXR_FLP | /* do not force link pass */ 938 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */ 939 940 return 0; 941 } 942 943 static void pxa168_eth_adjust_link(struct net_device *dev) 944 { 945 struct pxa168_eth_private *pep = netdev_priv(dev); 946 struct phy_device *phy = pep->phy; 947 u32 cfg, cfg_o = rdl(pep, PORT_CONFIG); 948 u32 cfgext, cfgext_o = rdl(pep, PORT_CONFIG_EXT); 949 950 cfg = cfg_o & ~PCR_DUPLEX_FULL; 951 cfgext = cfgext_o & ~(PCXR_SPEED_100 | PCXR_FLOWCTL_DIS | PCXR_RMII_EN); 952 953 if (phy->interface == PHY_INTERFACE_MODE_RMII) 954 cfgext |= PCXR_RMII_EN; 955 if (phy->speed == SPEED_100) 956 cfgext |= PCXR_SPEED_100; 957 if (phy->duplex) 958 cfg |= PCR_DUPLEX_FULL; 959 if (!phy->pause) 960 cfgext |= PCXR_FLOWCTL_DIS; 961 962 /* Bail out if there has nothing changed */ 963 if (cfg == cfg_o && cfgext == cfgext_o) 964 return; 965 966 wrl(pep, PORT_CONFIG, cfg); 967 wrl(pep, PORT_CONFIG_EXT, cfgext); 968 969 phy_print_status(phy); 970 } 971 972 static int pxa168_init_phy(struct net_device *dev) 973 { 974 struct pxa168_eth_private *pep = netdev_priv(dev); 975 struct ethtool_cmd cmd; 976 int err; 977 978 if (pep->phy) 979 return 0; 980 981 pep->phy = mdiobus_scan(pep->smi_bus, pep->phy_addr); 982 if (!pep->phy) 983 return -ENODEV; 984 985 err = phy_connect_direct(dev, pep->phy, pxa168_eth_adjust_link, 986 pep->phy_intf); 987 if (err) 988 return err; 989 990 err = pxa168_get_settings(dev, &cmd); 991 if (err) 992 return err; 993 994 cmd.phy_address = pep->phy_addr; 995 cmd.speed = pep->phy_speed; 996 cmd.duplex = pep->phy_duplex; 997 cmd.advertising = PHY_BASIC_FEATURES; 998 cmd.autoneg = AUTONEG_ENABLE; 999 1000 if (cmd.speed != 0) 1001 cmd.autoneg = AUTONEG_DISABLE; 1002 1003 return pxa168_set_settings(dev, &cmd); 1004 } 1005 1006 static int pxa168_init_hw(struct pxa168_eth_private *pep) 1007 { 1008 int err = 0; 1009 1010 /* Disable interrupts */ 1011 wrl(pep, INT_MASK, 0); 1012 wrl(pep, INT_CAUSE, 0); 1013 /* Write to ICR to clear interrupts. */ 1014 wrl(pep, INT_W_CLEAR, 0); 1015 /* Abort any transmit and receive operations and put DMA 1016 * in idle state. 1017 */ 1018 abort_dma(pep); 1019 /* Initialize address hash table */ 1020 err = init_hash_table(pep); 1021 if (err) 1022 return err; 1023 /* SDMA configuration */ 1024 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ 1025 SDCR_RIFB | /* Rx interrupt on frame */ 1026 SDCR_BLMT | /* Little endian transmit */ 1027 SDCR_BLMR | /* Little endian receive */ 1028 SDCR_RC_MAX_RETRANS); /* Max retransmit count */ 1029 /* Port Configuration */ 1030 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ 1031 set_port_config_ext(pep); 1032 1033 return err; 1034 } 1035 1036 static int rxq_init(struct net_device *dev) 1037 { 1038 struct pxa168_eth_private *pep = netdev_priv(dev); 1039 struct rx_desc *p_rx_desc; 1040 int size = 0, i = 0; 1041 int rx_desc_num = pep->rx_ring_size; 1042 1043 /* Allocate RX skb rings */ 1044 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size, 1045 GFP_KERNEL); 1046 if (!pep->rx_skb) 1047 return -ENOMEM; 1048 1049 /* Allocate RX ring */ 1050 pep->rx_desc_count = 0; 1051 size = pep->rx_ring_size * sizeof(struct rx_desc); 1052 pep->rx_desc_area_size = size; 1053 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1054 &pep->rx_desc_dma, 1055 GFP_KERNEL); 1056 if (!pep->p_rx_desc_area) 1057 goto out; 1058 1059 /* initialize the next_desc_ptr links in the Rx descriptors ring */ 1060 p_rx_desc = pep->p_rx_desc_area; 1061 for (i = 0; i < rx_desc_num; i++) { 1062 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma + 1063 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc); 1064 } 1065 /* Save Rx desc pointer to driver struct. */ 1066 pep->rx_curr_desc_q = 0; 1067 pep->rx_used_desc_q = 0; 1068 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc); 1069 return 0; 1070 out: 1071 kfree(pep->rx_skb); 1072 return -ENOMEM; 1073 } 1074 1075 static void rxq_deinit(struct net_device *dev) 1076 { 1077 struct pxa168_eth_private *pep = netdev_priv(dev); 1078 int curr; 1079 1080 /* Free preallocated skb's on RX rings */ 1081 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) { 1082 if (pep->rx_skb[curr]) { 1083 dev_kfree_skb(pep->rx_skb[curr]); 1084 pep->rx_desc_count--; 1085 } 1086 } 1087 if (pep->rx_desc_count) 1088 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n", 1089 pep->rx_desc_count); 1090 /* Free RX ring */ 1091 if (pep->p_rx_desc_area) 1092 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size, 1093 pep->p_rx_desc_area, pep->rx_desc_dma); 1094 kfree(pep->rx_skb); 1095 } 1096 1097 static int txq_init(struct net_device *dev) 1098 { 1099 struct pxa168_eth_private *pep = netdev_priv(dev); 1100 struct tx_desc *p_tx_desc; 1101 int size = 0, i = 0; 1102 int tx_desc_num = pep->tx_ring_size; 1103 1104 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size, 1105 GFP_KERNEL); 1106 if (!pep->tx_skb) 1107 return -ENOMEM; 1108 1109 /* Allocate TX ring */ 1110 pep->tx_desc_count = 0; 1111 size = pep->tx_ring_size * sizeof(struct tx_desc); 1112 pep->tx_desc_area_size = size; 1113 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size, 1114 &pep->tx_desc_dma, 1115 GFP_KERNEL); 1116 if (!pep->p_tx_desc_area) 1117 goto out; 1118 /* Initialize the next_desc_ptr links in the Tx descriptors ring */ 1119 p_tx_desc = pep->p_tx_desc_area; 1120 for (i = 0; i < tx_desc_num; i++) { 1121 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma + 1122 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc); 1123 } 1124 pep->tx_curr_desc_q = 0; 1125 pep->tx_used_desc_q = 0; 1126 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc); 1127 return 0; 1128 out: 1129 kfree(pep->tx_skb); 1130 return -ENOMEM; 1131 } 1132 1133 static void txq_deinit(struct net_device *dev) 1134 { 1135 struct pxa168_eth_private *pep = netdev_priv(dev); 1136 1137 /* Free outstanding skb's on TX ring */ 1138 txq_reclaim(dev, 1); 1139 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q); 1140 /* Free TX ring */ 1141 if (pep->p_tx_desc_area) 1142 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size, 1143 pep->p_tx_desc_area, pep->tx_desc_dma); 1144 kfree(pep->tx_skb); 1145 } 1146 1147 static int pxa168_eth_open(struct net_device *dev) 1148 { 1149 struct pxa168_eth_private *pep = netdev_priv(dev); 1150 int err; 1151 1152 err = pxa168_init_phy(dev); 1153 if (err) 1154 return err; 1155 1156 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev); 1157 if (err) { 1158 dev_err(&dev->dev, "can't assign irq\n"); 1159 return -EAGAIN; 1160 } 1161 pep->rx_resource_err = 0; 1162 err = rxq_init(dev); 1163 if (err != 0) 1164 goto out_free_irq; 1165 err = txq_init(dev); 1166 if (err != 0) 1167 goto out_free_rx_skb; 1168 pep->rx_used_desc_q = 0; 1169 pep->rx_curr_desc_q = 0; 1170 1171 /* Fill RX ring with skb's */ 1172 rxq_refill(dev); 1173 pep->rx_used_desc_q = 0; 1174 pep->rx_curr_desc_q = 0; 1175 netif_carrier_off(dev); 1176 napi_enable(&pep->napi); 1177 eth_port_start(dev); 1178 return 0; 1179 out_free_rx_skb: 1180 rxq_deinit(dev); 1181 out_free_irq: 1182 free_irq(dev->irq, dev); 1183 return err; 1184 } 1185 1186 static int pxa168_eth_stop(struct net_device *dev) 1187 { 1188 struct pxa168_eth_private *pep = netdev_priv(dev); 1189 eth_port_reset(dev); 1190 1191 /* Disable interrupts */ 1192 wrl(pep, INT_MASK, 0); 1193 wrl(pep, INT_CAUSE, 0); 1194 /* Write to ICR to clear interrupts. */ 1195 wrl(pep, INT_W_CLEAR, 0); 1196 napi_disable(&pep->napi); 1197 del_timer_sync(&pep->timeout); 1198 netif_carrier_off(dev); 1199 free_irq(dev->irq, dev); 1200 rxq_deinit(dev); 1201 txq_deinit(dev); 1202 1203 return 0; 1204 } 1205 1206 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu) 1207 { 1208 int retval; 1209 struct pxa168_eth_private *pep = netdev_priv(dev); 1210 1211 if ((mtu > 9500) || (mtu < 68)) 1212 return -EINVAL; 1213 1214 dev->mtu = mtu; 1215 retval = set_port_config_ext(pep); 1216 1217 if (!netif_running(dev)) 1218 return 0; 1219 1220 /* 1221 * Stop and then re-open the interface. This will allocate RX 1222 * skbs of the new MTU. 1223 * There is a possible danger that the open will not succeed, 1224 * due to memory being full. 1225 */ 1226 pxa168_eth_stop(dev); 1227 if (pxa168_eth_open(dev)) { 1228 dev_err(&dev->dev, 1229 "fatal error on re-opening device after MTU change\n"); 1230 } 1231 1232 return 0; 1233 } 1234 1235 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep) 1236 { 1237 int tx_desc_curr; 1238 1239 tx_desc_curr = pep->tx_curr_desc_q; 1240 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size; 1241 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q); 1242 pep->tx_desc_count++; 1243 1244 return tx_desc_curr; 1245 } 1246 1247 static int pxa168_rx_poll(struct napi_struct *napi, int budget) 1248 { 1249 struct pxa168_eth_private *pep = 1250 container_of(napi, struct pxa168_eth_private, napi); 1251 struct net_device *dev = pep->dev; 1252 int work_done = 0; 1253 1254 /* 1255 * We call txq_reclaim every time since in NAPI interupts are disabled 1256 * and due to this we miss the TX_DONE interrupt,which is not updated in 1257 * interrupt status register. 1258 */ 1259 txq_reclaim(dev, 0); 1260 if (netif_queue_stopped(dev) 1261 && pep->tx_ring_size - pep->tx_desc_count > 1) { 1262 netif_wake_queue(dev); 1263 } 1264 work_done = rxq_process(dev, budget); 1265 if (work_done < budget) { 1266 napi_complete(napi); 1267 wrl(pep, INT_MASK, ALL_INTS); 1268 } 1269 1270 return work_done; 1271 } 1272 1273 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev) 1274 { 1275 struct pxa168_eth_private *pep = netdev_priv(dev); 1276 struct net_device_stats *stats = &dev->stats; 1277 struct tx_desc *desc; 1278 int tx_index; 1279 int length; 1280 1281 tx_index = eth_alloc_tx_desc_index(pep); 1282 desc = &pep->p_tx_desc_area[tx_index]; 1283 length = skb->len; 1284 pep->tx_skb[tx_index] = skb; 1285 desc->byte_cnt = length; 1286 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE); 1287 1288 skb_tx_timestamp(skb); 1289 1290 wmb(); 1291 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC | 1292 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT; 1293 wmb(); 1294 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); 1295 1296 stats->tx_bytes += length; 1297 stats->tx_packets++; 1298 dev->trans_start = jiffies; 1299 if (pep->tx_ring_size - pep->tx_desc_count <= 1) { 1300 /* We handled the current skb, but now we are out of space.*/ 1301 netif_stop_queue(dev); 1302 } 1303 1304 return NETDEV_TX_OK; 1305 } 1306 1307 static int smi_wait_ready(struct pxa168_eth_private *pep) 1308 { 1309 int i = 0; 1310 1311 /* wait for the SMI register to become available */ 1312 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) { 1313 if (i == PHY_WAIT_ITERATIONS) 1314 return -ETIMEDOUT; 1315 msleep(10); 1316 } 1317 1318 return 0; 1319 } 1320 1321 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum) 1322 { 1323 struct pxa168_eth_private *pep = bus->priv; 1324 int i = 0; 1325 int val; 1326 1327 if (smi_wait_ready(pep)) { 1328 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1329 return -ETIMEDOUT; 1330 } 1331 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); 1332 /* now wait for the data to be valid */ 1333 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) { 1334 if (i == PHY_WAIT_ITERATIONS) { 1335 netdev_warn(pep->dev, 1336 "pxa168_eth: SMI bus read not valid\n"); 1337 return -ENODEV; 1338 } 1339 msleep(10); 1340 } 1341 1342 return val & 0xffff; 1343 } 1344 1345 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum, 1346 u16 value) 1347 { 1348 struct pxa168_eth_private *pep = bus->priv; 1349 1350 if (smi_wait_ready(pep)) { 1351 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1352 return -ETIMEDOUT; 1353 } 1354 1355 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | 1356 SMI_OP_W | (value & 0xffff)); 1357 1358 if (smi_wait_ready(pep)) { 1359 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n"); 1360 return -ETIMEDOUT; 1361 } 1362 1363 return 0; 1364 } 1365 1366 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, 1367 int cmd) 1368 { 1369 struct pxa168_eth_private *pep = netdev_priv(dev); 1370 if (pep->phy != NULL) 1371 return phy_mii_ioctl(pep->phy, ifr, cmd); 1372 1373 return -EOPNOTSUPP; 1374 } 1375 1376 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1377 { 1378 struct pxa168_eth_private *pep = netdev_priv(dev); 1379 int err; 1380 1381 err = phy_read_status(pep->phy); 1382 if (err == 0) 1383 err = phy_ethtool_gset(pep->phy, cmd); 1384 1385 return err; 1386 } 1387 1388 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1389 { 1390 struct pxa168_eth_private *pep = netdev_priv(dev); 1391 1392 return phy_ethtool_sset(pep->phy, cmd); 1393 } 1394 1395 static void pxa168_get_drvinfo(struct net_device *dev, 1396 struct ethtool_drvinfo *info) 1397 { 1398 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver)); 1399 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); 1400 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); 1401 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); 1402 } 1403 1404 static const struct ethtool_ops pxa168_ethtool_ops = { 1405 .get_settings = pxa168_get_settings, 1406 .set_settings = pxa168_set_settings, 1407 .get_drvinfo = pxa168_get_drvinfo, 1408 .get_link = ethtool_op_get_link, 1409 .get_ts_info = ethtool_op_get_ts_info, 1410 }; 1411 1412 static const struct net_device_ops pxa168_eth_netdev_ops = { 1413 .ndo_open = pxa168_eth_open, 1414 .ndo_stop = pxa168_eth_stop, 1415 .ndo_start_xmit = pxa168_eth_start_xmit, 1416 .ndo_set_rx_mode = pxa168_eth_set_rx_mode, 1417 .ndo_set_mac_address = pxa168_eth_set_mac_address, 1418 .ndo_validate_addr = eth_validate_addr, 1419 .ndo_do_ioctl = pxa168_eth_do_ioctl, 1420 .ndo_change_mtu = pxa168_eth_change_mtu, 1421 .ndo_tx_timeout = pxa168_eth_tx_timeout, 1422 }; 1423 1424 static int pxa168_eth_probe(struct platform_device *pdev) 1425 { 1426 struct pxa168_eth_private *pep = NULL; 1427 struct net_device *dev = NULL; 1428 struct resource *res; 1429 struct clk *clk; 1430 struct device_node *np; 1431 const unsigned char *mac_addr = NULL; 1432 int err; 1433 1434 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n"); 1435 1436 clk = devm_clk_get(&pdev->dev, NULL); 1437 if (IS_ERR(clk)) { 1438 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n"); 1439 return -ENODEV; 1440 } 1441 clk_prepare_enable(clk); 1442 1443 dev = alloc_etherdev(sizeof(struct pxa168_eth_private)); 1444 if (!dev) { 1445 err = -ENOMEM; 1446 goto err_clk; 1447 } 1448 1449 platform_set_drvdata(pdev, dev); 1450 pep = netdev_priv(dev); 1451 pep->dev = dev; 1452 pep->clk = clk; 1453 1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1455 pep->base = devm_ioremap_resource(&pdev->dev, res); 1456 if (IS_ERR(pep->base)) { 1457 err = -ENOMEM; 1458 goto err_netdev; 1459 } 1460 1461 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1462 BUG_ON(!res); 1463 dev->irq = res->start; 1464 dev->netdev_ops = &pxa168_eth_netdev_ops; 1465 dev->watchdog_timeo = 2 * HZ; 1466 dev->base_addr = 0; 1467 dev->ethtool_ops = &pxa168_ethtool_ops; 1468 1469 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task); 1470 1471 if (pdev->dev.of_node) 1472 mac_addr = of_get_mac_address(pdev->dev.of_node); 1473 1474 if (mac_addr && is_valid_ether_addr(mac_addr)) { 1475 ether_addr_copy(dev->dev_addr, mac_addr); 1476 } else { 1477 /* try reading the mac address, if set by the bootloader */ 1478 pxa168_eth_get_mac_address(dev, dev->dev_addr); 1479 if (!is_valid_ether_addr(dev->dev_addr)) { 1480 dev_info(&pdev->dev, "Using random mac address\n"); 1481 eth_hw_addr_random(dev); 1482 } 1483 } 1484 1485 pep->rx_ring_size = NUM_RX_DESCS; 1486 pep->tx_ring_size = NUM_TX_DESCS; 1487 1488 pep->pd = dev_get_platdata(&pdev->dev); 1489 if (pep->pd) { 1490 if (pep->pd->rx_queue_size) 1491 pep->rx_ring_size = pep->pd->rx_queue_size; 1492 1493 if (pep->pd->tx_queue_size) 1494 pep->tx_ring_size = pep->pd->tx_queue_size; 1495 1496 pep->port_num = pep->pd->port_number; 1497 pep->phy_addr = pep->pd->phy_addr; 1498 pep->phy_speed = pep->pd->speed; 1499 pep->phy_duplex = pep->pd->duplex; 1500 pep->phy_intf = pep->pd->intf; 1501 1502 if (pep->pd->init) 1503 pep->pd->init(); 1504 } else if (pdev->dev.of_node) { 1505 of_property_read_u32(pdev->dev.of_node, "port-id", 1506 &pep->port_num); 1507 1508 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); 1509 if (!np) { 1510 dev_err(&pdev->dev, "missing phy-handle\n"); 1511 return -EINVAL; 1512 } 1513 of_property_read_u32(np, "reg", &pep->phy_addr); 1514 pep->phy_intf = of_get_phy_mode(pdev->dev.of_node); 1515 } 1516 1517 /* Hardware supports only 3 ports */ 1518 BUG_ON(pep->port_num > 2); 1519 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size); 1520 1521 memset(&pep->timeout, 0, sizeof(struct timer_list)); 1522 init_timer(&pep->timeout); 1523 pep->timeout.function = rxq_refill_timer_wrapper; 1524 pep->timeout.data = (unsigned long)pep; 1525 1526 pep->smi_bus = mdiobus_alloc(); 1527 if (pep->smi_bus == NULL) { 1528 err = -ENOMEM; 1529 goto err_base; 1530 } 1531 pep->smi_bus->priv = pep; 1532 pep->smi_bus->name = "pxa168_eth smi"; 1533 pep->smi_bus->read = pxa168_smi_read; 1534 pep->smi_bus->write = pxa168_smi_write; 1535 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d", 1536 pdev->name, pdev->id); 1537 pep->smi_bus->parent = &pdev->dev; 1538 pep->smi_bus->phy_mask = 0xffffffff; 1539 err = mdiobus_register(pep->smi_bus); 1540 if (err) 1541 goto err_free_mdio; 1542 1543 SET_NETDEV_DEV(dev, &pdev->dev); 1544 pxa168_init_hw(pep); 1545 err = register_netdev(dev); 1546 if (err) 1547 goto err_mdiobus; 1548 return 0; 1549 1550 err_mdiobus: 1551 mdiobus_unregister(pep->smi_bus); 1552 err_free_mdio: 1553 mdiobus_free(pep->smi_bus); 1554 err_base: 1555 iounmap(pep->base); 1556 err_netdev: 1557 free_netdev(dev); 1558 err_clk: 1559 clk_disable(clk); 1560 clk_put(clk); 1561 return err; 1562 } 1563 1564 static int pxa168_eth_remove(struct platform_device *pdev) 1565 { 1566 struct net_device *dev = platform_get_drvdata(pdev); 1567 struct pxa168_eth_private *pep = netdev_priv(dev); 1568 1569 if (pep->htpr) { 1570 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE, 1571 pep->htpr, pep->htpr_dma); 1572 pep->htpr = NULL; 1573 } 1574 if (pep->phy) 1575 phy_disconnect(pep->phy); 1576 if (pep->clk) { 1577 clk_disable(pep->clk); 1578 clk_put(pep->clk); 1579 pep->clk = NULL; 1580 } 1581 1582 iounmap(pep->base); 1583 pep->base = NULL; 1584 mdiobus_unregister(pep->smi_bus); 1585 mdiobus_free(pep->smi_bus); 1586 unregister_netdev(dev); 1587 cancel_work_sync(&pep->tx_timeout_task); 1588 free_netdev(dev); 1589 return 0; 1590 } 1591 1592 static void pxa168_eth_shutdown(struct platform_device *pdev) 1593 { 1594 struct net_device *dev = platform_get_drvdata(pdev); 1595 eth_port_reset(dev); 1596 } 1597 1598 #ifdef CONFIG_PM 1599 static int pxa168_eth_resume(struct platform_device *pdev) 1600 { 1601 return -ENOSYS; 1602 } 1603 1604 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state) 1605 { 1606 return -ENOSYS; 1607 } 1608 1609 #else 1610 #define pxa168_eth_resume NULL 1611 #define pxa168_eth_suspend NULL 1612 #endif 1613 1614 static const struct of_device_id pxa168_eth_of_match[] = { 1615 { .compatible = "marvell,pxa168-eth" }, 1616 { }, 1617 }; 1618 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match); 1619 1620 static struct platform_driver pxa168_eth_driver = { 1621 .probe = pxa168_eth_probe, 1622 .remove = pxa168_eth_remove, 1623 .shutdown = pxa168_eth_shutdown, 1624 .resume = pxa168_eth_resume, 1625 .suspend = pxa168_eth_suspend, 1626 .driver = { 1627 .name = DRIVER_NAME, 1628 .of_match_table = of_match_ptr(pxa168_eth_of_match), 1629 }, 1630 }; 1631 1632 module_platform_driver(pxa168_eth_driver); 1633 1634 MODULE_LICENSE("GPL"); 1635 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168"); 1636 MODULE_ALIAS("platform:pxa168_eth"); 1637