1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Virtual Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/net_tstamp.h> 12 13 #include "otx2_common.h" 14 #include "otx2_reg.h" 15 #include "otx2_ptp.h" 16 #include "cn10k.h" 17 18 #define DRV_NAME "rvu_nicvf" 19 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 20 21 static const struct pci_device_id otx2_vf_id_table[] = { 22 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 24 { } 25 }; 26 27 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 28 MODULE_DESCRIPTION(DRV_STRING); 29 MODULE_LICENSE("GPL v2"); 30 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 31 32 /* RVU VF Interrupt Vector Enumeration */ 33 enum { 34 RVU_VF_INT_VEC_MBOX = 0x0, 35 }; 36 37 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 38 struct mbox_msghdr *msg) 39 { 40 if (msg->id >= MBOX_MSG_MAX) { 41 dev_err(vf->dev, 42 "Mbox msg with unknown ID %d\n", msg->id); 43 return; 44 } 45 46 if (msg->sig != OTX2_MBOX_RSP_SIG) { 47 dev_err(vf->dev, 48 "Mbox msg with wrong signature %x, ID %d\n", 49 msg->sig, msg->id); 50 return; 51 } 52 53 if (msg->rc == MBOX_MSG_INVALID) { 54 dev_err(vf->dev, 55 "PF/AF says the sent msg(s) %d were invalid\n", 56 msg->id); 57 return; 58 } 59 60 switch (msg->id) { 61 case MBOX_MSG_READY: 62 vf->pcifunc = msg->pcifunc; 63 break; 64 case MBOX_MSG_MSIX_OFFSET: 65 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 66 break; 67 case MBOX_MSG_NPA_LF_ALLOC: 68 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 69 break; 70 case MBOX_MSG_NIX_LF_ALLOC: 71 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 72 break; 73 case MBOX_MSG_NIX_TXSCH_ALLOC: 74 mbox_handler_nix_txsch_alloc(vf, 75 (struct nix_txsch_alloc_rsp *)msg); 76 break; 77 case MBOX_MSG_NIX_BP_ENABLE: 78 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 79 break; 80 default: 81 if (msg->rc) 82 dev_err(vf->dev, 83 "Mbox msg response has err %d, ID %d\n", 84 msg->rc, msg->id); 85 } 86 } 87 88 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 89 { 90 struct otx2_mbox_dev *mdev; 91 struct mbox_hdr *rsp_hdr; 92 struct mbox_msghdr *msg; 93 struct otx2_mbox *mbox; 94 struct mbox *af_mbox; 95 int offset, id; 96 97 af_mbox = container_of(work, struct mbox, mbox_wrk); 98 mbox = &af_mbox->mbox; 99 mdev = &mbox->dev[0]; 100 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 101 if (af_mbox->num_msgs == 0) 102 return; 103 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 104 105 for (id = 0; id < af_mbox->num_msgs; id++) { 106 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 107 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 108 offset = mbox->rx_start + msg->next_msgoff; 109 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 110 __otx2_mbox_reset(mbox, 0); 111 mdev->msgs_acked++; 112 } 113 } 114 115 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 116 struct mbox_msghdr *req) 117 { 118 struct msg_rsp *rsp; 119 int err; 120 121 /* Check if valid, if not reply with a invalid msg */ 122 if (req->sig != OTX2_MBOX_REQ_SIG) { 123 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 124 return -ENODEV; 125 } 126 127 switch (req->id) { 128 case MBOX_MSG_CGX_LINK_EVENT: 129 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 130 &vf->mbox.mbox_up, 0, 131 sizeof(struct msg_rsp)); 132 if (!rsp) 133 return -ENOMEM; 134 135 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 136 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 137 rsp->hdr.pcifunc = 0; 138 rsp->hdr.rc = 0; 139 err = otx2_mbox_up_handler_cgx_link_event( 140 vf, (struct cgx_link_info_msg *)req, rsp); 141 return err; 142 default: 143 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 144 return -ENODEV; 145 } 146 return 0; 147 } 148 149 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 150 { 151 struct otx2_mbox_dev *mdev; 152 struct mbox_hdr *rsp_hdr; 153 struct mbox_msghdr *msg; 154 struct otx2_mbox *mbox; 155 struct mbox *vf_mbox; 156 struct otx2_nic *vf; 157 int offset, id; 158 159 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 160 vf = vf_mbox->pfvf; 161 mbox = &vf_mbox->mbox_up; 162 mdev = &mbox->dev[0]; 163 164 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 165 if (vf_mbox->up_num_msgs == 0) 166 return; 167 168 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 169 170 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 171 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 172 otx2vf_process_mbox_msg_up(vf, msg); 173 offset = mbox->rx_start + msg->next_msgoff; 174 } 175 176 otx2_mbox_msg_send(mbox, 0); 177 } 178 179 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 180 { 181 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 182 struct otx2_mbox_dev *mdev; 183 struct otx2_mbox *mbox; 184 struct mbox_hdr *hdr; 185 186 /* Clear the IRQ */ 187 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 188 189 /* Read latest mbox data */ 190 smp_rmb(); 191 192 /* Check for PF => VF response messages */ 193 mbox = &vf->mbox.mbox; 194 mdev = &mbox->dev[0]; 195 otx2_sync_mbox_bbuf(mbox, 0); 196 197 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0)); 198 199 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 200 if (hdr->num_msgs) { 201 vf->mbox.num_msgs = hdr->num_msgs; 202 hdr->num_msgs = 0; 203 memset(mbox->hwbase + mbox->rx_start, 0, 204 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 205 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 206 } 207 /* Check for PF => VF notification messages */ 208 mbox = &vf->mbox.mbox_up; 209 mdev = &mbox->dev[0]; 210 otx2_sync_mbox_bbuf(mbox, 0); 211 212 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 213 if (hdr->num_msgs) { 214 vf->mbox.up_num_msgs = hdr->num_msgs; 215 hdr->num_msgs = 0; 216 memset(mbox->hwbase + mbox->rx_start, 0, 217 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 218 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 219 } 220 221 return IRQ_HANDLED; 222 } 223 224 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 225 { 226 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 227 228 /* Disable VF => PF mailbox IRQ */ 229 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 230 free_irq(vector, vf); 231 } 232 233 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 234 { 235 struct otx2_hw *hw = &vf->hw; 236 struct msg_req *req; 237 char *irq_name; 238 int err; 239 240 /* Register mailbox interrupt handler */ 241 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 242 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 243 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 244 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 245 if (err) { 246 dev_err(vf->dev, 247 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 248 return err; 249 } 250 251 /* Enable mailbox interrupt for msgs coming from PF. 252 * First clear to avoid spurious interrupts, if any. 253 */ 254 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 255 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 256 257 if (!probe_pf) 258 return 0; 259 260 /* Check mailbox communication with PF */ 261 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 262 if (!req) { 263 otx2vf_disable_mbox_intr(vf); 264 return -ENOMEM; 265 } 266 267 err = otx2_sync_mbox_msg(&vf->mbox); 268 if (err) { 269 dev_warn(vf->dev, 270 "AF not responding to mailbox, deferring probe\n"); 271 otx2vf_disable_mbox_intr(vf); 272 return -EPROBE_DEFER; 273 } 274 return 0; 275 } 276 277 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 278 { 279 struct mbox *mbox = &vf->mbox; 280 281 if (vf->mbox_wq) { 282 flush_workqueue(vf->mbox_wq); 283 destroy_workqueue(vf->mbox_wq); 284 vf->mbox_wq = NULL; 285 } 286 287 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 288 iounmap((void __iomem *)mbox->mbox.hwbase); 289 290 otx2_mbox_destroy(&mbox->mbox); 291 otx2_mbox_destroy(&mbox->mbox_up); 292 } 293 294 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 295 { 296 struct mbox *mbox = &vf->mbox; 297 void __iomem *hwbase; 298 int err; 299 300 mbox->pfvf = vf; 301 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox", 302 WQ_UNBOUND | WQ_HIGHPRI | 303 WQ_MEM_RECLAIM, 1); 304 if (!vf->mbox_wq) 305 return -ENOMEM; 306 307 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 308 /* For cn10k platform, VF mailbox region is in its BAR2 309 * register space 310 */ 311 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 312 } else { 313 /* Mailbox is a reserved memory (in RAM) region shared between 314 * admin function (i.e PF0) and this VF, shouldn't be mapped as 315 * device memory to allow unaligned accesses. 316 */ 317 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 318 PCI_MBOX_BAR_NUM), 319 pci_resource_len(vf->pdev, 320 PCI_MBOX_BAR_NUM)); 321 if (!hwbase) { 322 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 323 err = -ENOMEM; 324 goto exit; 325 } 326 } 327 328 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 329 MBOX_DIR_VFPF, 1); 330 if (err) 331 goto exit; 332 333 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 334 MBOX_DIR_VFPF_UP, 1); 335 if (err) 336 goto exit; 337 338 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 339 if (err) 340 goto exit; 341 342 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 343 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 344 mutex_init(&mbox->lock); 345 346 return 0; 347 exit: 348 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 349 iounmap(hwbase); 350 destroy_workqueue(vf->mbox_wq); 351 return err; 352 } 353 354 static int otx2vf_open(struct net_device *netdev) 355 { 356 struct otx2_nic *vf; 357 int err; 358 359 err = otx2_open(netdev); 360 if (err) 361 return err; 362 363 /* LBKs do not receive link events so tell everyone we are up here */ 364 vf = netdev_priv(netdev); 365 if (is_otx2_lbkvf(vf->pdev)) { 366 pr_info("%s NIC Link is UP\n", netdev->name); 367 netif_carrier_on(netdev); 368 netif_tx_start_all_queues(netdev); 369 } 370 371 return 0; 372 } 373 374 static int otx2vf_stop(struct net_device *netdev) 375 { 376 return otx2_stop(netdev); 377 } 378 379 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 380 { 381 struct otx2_nic *vf = netdev_priv(netdev); 382 int qidx = skb_get_queue_mapping(skb); 383 struct otx2_snd_queue *sq; 384 struct netdev_queue *txq; 385 386 sq = &vf->qset.sq[qidx]; 387 txq = netdev_get_tx_queue(netdev, qidx); 388 389 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 390 netif_tx_stop_queue(txq); 391 392 /* Check again, incase SQBs got freed up */ 393 smp_mb(); 394 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 395 > sq->sqe_thresh) 396 netif_tx_wake_queue(txq); 397 398 return NETDEV_TX_BUSY; 399 } 400 401 return NETDEV_TX_OK; 402 } 403 404 static void otx2vf_set_rx_mode(struct net_device *netdev) 405 { 406 struct otx2_nic *vf = netdev_priv(netdev); 407 408 queue_work(vf->otx2_wq, &vf->rx_mode_work); 409 } 410 411 static void otx2vf_do_set_rx_mode(struct work_struct *work) 412 { 413 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 414 struct net_device *netdev = vf->netdev; 415 unsigned int flags = netdev->flags; 416 struct nix_rx_mode *req; 417 418 mutex_lock(&vf->mbox.lock); 419 420 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 421 if (!req) { 422 mutex_unlock(&vf->mbox.lock); 423 return; 424 } 425 426 req->mode = NIX_RX_MODE_UCAST; 427 428 if (flags & IFF_PROMISC) 429 req->mode |= NIX_RX_MODE_PROMISC; 430 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 431 req->mode |= NIX_RX_MODE_ALLMULTI; 432 433 req->mode |= NIX_RX_MODE_USE_MCE; 434 435 otx2_sync_mbox_msg(&vf->mbox); 436 437 mutex_unlock(&vf->mbox.lock); 438 } 439 440 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 441 { 442 bool if_up = netif_running(netdev); 443 int err = 0; 444 445 if (if_up) 446 otx2vf_stop(netdev); 447 448 netdev_info(netdev, "Changing MTU from %d to %d\n", 449 netdev->mtu, new_mtu); 450 netdev->mtu = new_mtu; 451 452 if (if_up) 453 err = otx2vf_open(netdev); 454 455 return err; 456 } 457 458 static void otx2vf_reset_task(struct work_struct *work) 459 { 460 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 461 462 rtnl_lock(); 463 464 if (netif_running(vf->netdev)) { 465 otx2vf_stop(vf->netdev); 466 vf->reset_count++; 467 otx2vf_open(vf->netdev); 468 } 469 470 rtnl_unlock(); 471 } 472 473 static int otx2vf_set_features(struct net_device *netdev, 474 netdev_features_t features) 475 { 476 netdev_features_t changed = features ^ netdev->features; 477 bool ntuple_enabled = !!(features & NETIF_F_NTUPLE); 478 struct otx2_nic *vf = netdev_priv(netdev); 479 480 if (changed & NETIF_F_NTUPLE) { 481 if (!ntuple_enabled) { 482 otx2_mcam_flow_del(vf); 483 return 0; 484 } 485 486 if (!otx2_get_maxflows(vf->flow_cfg)) { 487 netdev_err(netdev, 488 "Can't enable NTUPLE, MCAM entries not allocated\n"); 489 return -EINVAL; 490 } 491 } 492 return 0; 493 } 494 495 static const struct net_device_ops otx2vf_netdev_ops = { 496 .ndo_open = otx2vf_open, 497 .ndo_stop = otx2vf_stop, 498 .ndo_start_xmit = otx2vf_xmit, 499 .ndo_set_rx_mode = otx2vf_set_rx_mode, 500 .ndo_set_mac_address = otx2_set_mac_address, 501 .ndo_change_mtu = otx2vf_change_mtu, 502 .ndo_set_features = otx2vf_set_features, 503 .ndo_get_stats64 = otx2_get_stats64, 504 .ndo_tx_timeout = otx2_tx_timeout, 505 .ndo_do_ioctl = otx2_ioctl, 506 }; 507 508 static int otx2_wq_init(struct otx2_nic *vf) 509 { 510 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 511 if (!vf->otx2_wq) 512 return -ENOMEM; 513 514 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 515 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 516 return 0; 517 } 518 519 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 520 { 521 struct otx2_hw *hw = &vf->hw; 522 int num_vec, err; 523 524 num_vec = hw->nix_msixoff; 525 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 526 527 otx2vf_disable_mbox_intr(vf); 528 pci_free_irq_vectors(hw->pdev); 529 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 530 if (err < 0) { 531 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 532 __func__, num_vec); 533 return err; 534 } 535 536 return otx2vf_register_mbox_intr(vf, false); 537 } 538 539 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 540 { 541 int num_vec = pci_msix_vec_count(pdev); 542 struct device *dev = &pdev->dev; 543 struct net_device *netdev; 544 struct otx2_nic *vf; 545 struct otx2_hw *hw; 546 int err, qcount; 547 548 err = pcim_enable_device(pdev); 549 if (err) { 550 dev_err(dev, "Failed to enable PCI device\n"); 551 return err; 552 } 553 554 err = pci_request_regions(pdev, DRV_NAME); 555 if (err) { 556 dev_err(dev, "PCI request regions failed 0x%x\n", err); 557 return err; 558 } 559 560 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 561 if (err) { 562 dev_err(dev, "DMA mask config failed, abort\n"); 563 goto err_release_regions; 564 } 565 566 pci_set_master(pdev); 567 568 qcount = num_online_cpus(); 569 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount); 570 if (!netdev) { 571 err = -ENOMEM; 572 goto err_release_regions; 573 } 574 575 pci_set_drvdata(pdev, netdev); 576 SET_NETDEV_DEV(netdev, &pdev->dev); 577 vf = netdev_priv(netdev); 578 vf->netdev = netdev; 579 vf->pdev = pdev; 580 vf->dev = dev; 581 vf->iommu_domain = iommu_get_domain_for_dev(dev); 582 583 vf->flags |= OTX2_FLAG_INTF_DOWN; 584 hw = &vf->hw; 585 hw->pdev = vf->pdev; 586 hw->rx_queues = qcount; 587 hw->tx_queues = qcount; 588 hw->max_queues = qcount; 589 hw->tot_tx_queues = qcount; 590 591 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 592 GFP_KERNEL); 593 if (!hw->irq_name) { 594 err = -ENOMEM; 595 goto err_free_netdev; 596 } 597 598 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 599 sizeof(cpumask_var_t), GFP_KERNEL); 600 if (!hw->affinity_mask) { 601 err = -ENOMEM; 602 goto err_free_netdev; 603 } 604 605 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 606 if (err < 0) { 607 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 608 __func__, num_vec); 609 goto err_free_netdev; 610 } 611 612 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 613 if (!vf->reg_base) { 614 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 615 err = -ENOMEM; 616 goto err_free_irq_vectors; 617 } 618 619 otx2_setup_dev_hw_settings(vf); 620 /* Init VF <=> PF mailbox stuff */ 621 err = otx2vf_vfaf_mbox_init(vf); 622 if (err) 623 goto err_free_irq_vectors; 624 625 /* Register mailbox interrupt */ 626 err = otx2vf_register_mbox_intr(vf, true); 627 if (err) 628 goto err_mbox_destroy; 629 630 /* Request AF to attach NPA and LIX LFs to this AF */ 631 err = otx2_attach_npa_nix(vf); 632 if (err) 633 goto err_disable_mbox_intr; 634 635 err = otx2vf_realloc_msix_vectors(vf); 636 if (err) 637 goto err_mbox_destroy; 638 639 err = otx2_set_real_num_queues(netdev, qcount, qcount); 640 if (err) 641 goto err_detach_rsrc; 642 643 err = cn10k_lmtst_init(vf); 644 if (err) 645 goto err_detach_rsrc; 646 647 /* Don't check for error. Proceed without ptp */ 648 otx2_ptp_init(vf); 649 650 /* Assign default mac address */ 651 otx2_get_mac_from_af(netdev); 652 653 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 654 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 655 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 656 NETIF_F_GSO_UDP_L4; 657 netdev->features = netdev->hw_features; 658 /* Support TSO on tag interface */ 659 netdev->vlan_features |= netdev->features; 660 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 661 NETIF_F_HW_VLAN_STAG_TX; 662 netdev->features |= netdev->hw_features; 663 664 netdev->hw_features |= NETIF_F_NTUPLE; 665 netdev->hw_features |= NETIF_F_RXALL; 666 667 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 668 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 669 670 netdev->netdev_ops = &otx2vf_netdev_ops; 671 672 netdev->min_mtu = OTX2_MIN_MTU; 673 netdev->max_mtu = otx2_get_max_mtu(vf); 674 675 /* To distinguish, for LBK VFs set netdev name explicitly */ 676 if (is_otx2_lbkvf(vf->pdev)) { 677 int n; 678 679 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 680 /* Need to subtract 1 to get proper VF number */ 681 n -= 1; 682 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 683 } 684 685 err = register_netdev(netdev); 686 if (err) { 687 dev_err(dev, "Failed to register netdevice\n"); 688 goto err_detach_rsrc; 689 } 690 691 err = otx2_wq_init(vf); 692 if (err) 693 goto err_unreg_netdev; 694 695 otx2vf_set_ethtool_ops(netdev); 696 697 err = otx2vf_mcam_flow_init(vf); 698 if (err) 699 goto err_unreg_netdev; 700 701 err = otx2_register_dl(vf); 702 if (err) 703 goto err_unreg_netdev; 704 705 /* Enable pause frames by default */ 706 vf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 707 vf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 708 709 return 0; 710 711 err_unreg_netdev: 712 unregister_netdev(netdev); 713 err_detach_rsrc: 714 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 715 qmem_free(vf->dev, vf->dync_lmt); 716 otx2_detach_resources(&vf->mbox); 717 err_disable_mbox_intr: 718 otx2vf_disable_mbox_intr(vf); 719 err_mbox_destroy: 720 otx2vf_vfaf_mbox_destroy(vf); 721 err_free_irq_vectors: 722 pci_free_irq_vectors(hw->pdev); 723 err_free_netdev: 724 pci_set_drvdata(pdev, NULL); 725 free_netdev(netdev); 726 err_release_regions: 727 pci_release_regions(pdev); 728 return err; 729 } 730 731 static void otx2vf_remove(struct pci_dev *pdev) 732 { 733 struct net_device *netdev = pci_get_drvdata(pdev); 734 struct otx2_nic *vf; 735 736 if (!netdev) 737 return; 738 739 vf = netdev_priv(netdev); 740 741 cancel_work_sync(&vf->reset_task); 742 otx2_unregister_dl(vf); 743 unregister_netdev(netdev); 744 if (vf->otx2_wq) 745 destroy_workqueue(vf->otx2_wq); 746 otx2vf_disable_mbox_intr(vf); 747 otx2_detach_resources(&vf->mbox); 748 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 749 qmem_free(vf->dev, vf->dync_lmt); 750 otx2vf_vfaf_mbox_destroy(vf); 751 pci_free_irq_vectors(vf->pdev); 752 pci_set_drvdata(pdev, NULL); 753 free_netdev(netdev); 754 755 pci_release_regions(pdev); 756 } 757 758 static struct pci_driver otx2vf_driver = { 759 .name = DRV_NAME, 760 .id_table = otx2_vf_id_table, 761 .probe = otx2vf_probe, 762 .remove = otx2vf_remove, 763 .shutdown = otx2vf_remove, 764 }; 765 766 static int __init otx2vf_init_module(void) 767 { 768 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 769 770 return pci_register_driver(&otx2vf_driver); 771 } 772 773 static void __exit otx2vf_cleanup_module(void) 774 { 775 pci_unregister_driver(&otx2vf_driver); 776 } 777 778 module_init(otx2vf_init_module); 779 module_exit(otx2vf_cleanup_module); 780