1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Virtual Function ethernet driver */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include "otx2_common.h" 9 #include "otx2_reg.h" 10 11 #define DRV_NAME "octeontx2-nicvf" 12 #define DRV_STRING "Marvell OcteonTX2 NIC Virtual Function Driver" 13 14 static const struct pci_device_id otx2_vf_id_table[] = { 15 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 16 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 17 { } 18 }; 19 20 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 21 MODULE_DESCRIPTION(DRV_STRING); 22 MODULE_LICENSE("GPL v2"); 23 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 24 25 /* RVU VF Interrupt Vector Enumeration */ 26 enum { 27 RVU_VF_INT_VEC_MBOX = 0x0, 28 }; 29 30 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 31 struct mbox_msghdr *msg) 32 { 33 if (msg->id >= MBOX_MSG_MAX) { 34 dev_err(vf->dev, 35 "Mbox msg with unknown ID %d\n", msg->id); 36 return; 37 } 38 39 if (msg->sig != OTX2_MBOX_RSP_SIG) { 40 dev_err(vf->dev, 41 "Mbox msg with wrong signature %x, ID %d\n", 42 msg->sig, msg->id); 43 return; 44 } 45 46 if (msg->rc == MBOX_MSG_INVALID) { 47 dev_err(vf->dev, 48 "PF/AF says the sent msg(s) %d were invalid\n", 49 msg->id); 50 return; 51 } 52 53 switch (msg->id) { 54 case MBOX_MSG_READY: 55 vf->pcifunc = msg->pcifunc; 56 break; 57 case MBOX_MSG_MSIX_OFFSET: 58 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 59 break; 60 case MBOX_MSG_NPA_LF_ALLOC: 61 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 62 break; 63 case MBOX_MSG_NIX_LF_ALLOC: 64 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 65 break; 66 case MBOX_MSG_NIX_TXSCH_ALLOC: 67 mbox_handler_nix_txsch_alloc(vf, 68 (struct nix_txsch_alloc_rsp *)msg); 69 break; 70 case MBOX_MSG_NIX_BP_ENABLE: 71 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 72 break; 73 default: 74 if (msg->rc) 75 dev_err(vf->dev, 76 "Mbox msg response has err %d, ID %d\n", 77 msg->rc, msg->id); 78 } 79 } 80 81 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 82 { 83 struct otx2_mbox_dev *mdev; 84 struct mbox_hdr *rsp_hdr; 85 struct mbox_msghdr *msg; 86 struct otx2_mbox *mbox; 87 struct mbox *af_mbox; 88 int offset, id; 89 90 af_mbox = container_of(work, struct mbox, mbox_wrk); 91 mbox = &af_mbox->mbox; 92 mdev = &mbox->dev[0]; 93 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 94 if (af_mbox->num_msgs == 0) 95 return; 96 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 97 98 for (id = 0; id < af_mbox->num_msgs; id++) { 99 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 100 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 101 offset = mbox->rx_start + msg->next_msgoff; 102 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 103 __otx2_mbox_reset(mbox, 0); 104 mdev->msgs_acked++; 105 } 106 } 107 108 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 109 struct mbox_msghdr *req) 110 { 111 struct msg_rsp *rsp; 112 int err; 113 114 /* Check if valid, if not reply with a invalid msg */ 115 if (req->sig != OTX2_MBOX_REQ_SIG) { 116 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 117 return -ENODEV; 118 } 119 120 switch (req->id) { 121 case MBOX_MSG_CGX_LINK_EVENT: 122 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 123 &vf->mbox.mbox_up, 0, 124 sizeof(struct msg_rsp)); 125 if (!rsp) 126 return -ENOMEM; 127 128 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 129 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 130 rsp->hdr.pcifunc = 0; 131 rsp->hdr.rc = 0; 132 err = otx2_mbox_up_handler_cgx_link_event( 133 vf, (struct cgx_link_info_msg *)req, rsp); 134 return err; 135 default: 136 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 137 return -ENODEV; 138 } 139 return 0; 140 } 141 142 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 143 { 144 struct otx2_mbox_dev *mdev; 145 struct mbox_hdr *rsp_hdr; 146 struct mbox_msghdr *msg; 147 struct otx2_mbox *mbox; 148 struct mbox *vf_mbox; 149 struct otx2_nic *vf; 150 int offset, id; 151 152 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 153 vf = vf_mbox->pfvf; 154 mbox = &vf_mbox->mbox_up; 155 mdev = &mbox->dev[0]; 156 157 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 158 if (vf_mbox->up_num_msgs == 0) 159 return; 160 161 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 162 163 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 164 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 165 otx2vf_process_mbox_msg_up(vf, msg); 166 offset = mbox->rx_start + msg->next_msgoff; 167 } 168 169 otx2_mbox_msg_send(mbox, 0); 170 } 171 172 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 173 { 174 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 175 struct otx2_mbox_dev *mdev; 176 struct otx2_mbox *mbox; 177 struct mbox_hdr *hdr; 178 179 /* Clear the IRQ */ 180 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 181 182 /* Read latest mbox data */ 183 smp_rmb(); 184 185 /* Check for PF => VF response messages */ 186 mbox = &vf->mbox.mbox; 187 mdev = &mbox->dev[0]; 188 otx2_sync_mbox_bbuf(mbox, 0); 189 190 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0)); 191 192 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 193 if (hdr->num_msgs) { 194 vf->mbox.num_msgs = hdr->num_msgs; 195 hdr->num_msgs = 0; 196 memset(mbox->hwbase + mbox->rx_start, 0, 197 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 198 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 199 } 200 /* Check for PF => VF notification messages */ 201 mbox = &vf->mbox.mbox_up; 202 mdev = &mbox->dev[0]; 203 otx2_sync_mbox_bbuf(mbox, 0); 204 205 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 206 if (hdr->num_msgs) { 207 vf->mbox.up_num_msgs = hdr->num_msgs; 208 hdr->num_msgs = 0; 209 memset(mbox->hwbase + mbox->rx_start, 0, 210 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 211 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 212 } 213 214 return IRQ_HANDLED; 215 } 216 217 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 218 { 219 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 220 221 /* Disable VF => PF mailbox IRQ */ 222 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 223 free_irq(vector, vf); 224 } 225 226 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 227 { 228 struct otx2_hw *hw = &vf->hw; 229 struct msg_req *req; 230 char *irq_name; 231 int err; 232 233 /* Register mailbox interrupt handler */ 234 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 236 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 237 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 238 if (err) { 239 dev_err(vf->dev, 240 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 241 return err; 242 } 243 244 /* Enable mailbox interrupt for msgs coming from PF. 245 * First clear to avoid spurious interrupts, if any. 246 */ 247 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 248 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 249 250 if (!probe_pf) 251 return 0; 252 253 /* Check mailbox communication with PF */ 254 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 255 if (!req) { 256 otx2vf_disable_mbox_intr(vf); 257 return -ENOMEM; 258 } 259 260 err = otx2_sync_mbox_msg(&vf->mbox); 261 if (err) { 262 dev_warn(vf->dev, 263 "AF not responding to mailbox, deferring probe\n"); 264 otx2vf_disable_mbox_intr(vf); 265 return -EPROBE_DEFER; 266 } 267 return 0; 268 } 269 270 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 271 { 272 struct mbox *mbox = &vf->mbox; 273 274 if (vf->mbox_wq) { 275 flush_workqueue(vf->mbox_wq); 276 destroy_workqueue(vf->mbox_wq); 277 vf->mbox_wq = NULL; 278 } 279 280 if (mbox->mbox.hwbase) 281 iounmap((void __iomem *)mbox->mbox.hwbase); 282 283 otx2_mbox_destroy(&mbox->mbox); 284 otx2_mbox_destroy(&mbox->mbox_up); 285 } 286 287 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 288 { 289 struct mbox *mbox = &vf->mbox; 290 void __iomem *hwbase; 291 int err; 292 293 mbox->pfvf = vf; 294 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox", 295 WQ_UNBOUND | WQ_HIGHPRI | 296 WQ_MEM_RECLAIM, 1); 297 if (!vf->mbox_wq) 298 return -ENOMEM; 299 300 /* Mailbox is a reserved memory (in RAM) region shared between 301 * admin function (i.e PF0) and this VF, shouldn't be mapped as 302 * device memory to allow unaligned accesses. 303 */ 304 hwbase = ioremap_wc(pci_resource_start(vf->pdev, PCI_MBOX_BAR_NUM), 305 pci_resource_len(vf->pdev, PCI_MBOX_BAR_NUM)); 306 if (!hwbase) { 307 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 308 err = -ENOMEM; 309 goto exit; 310 } 311 312 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 313 MBOX_DIR_VFPF, 1); 314 if (err) 315 goto exit; 316 317 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 318 MBOX_DIR_VFPF_UP, 1); 319 if (err) 320 goto exit; 321 322 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 323 if (err) 324 goto exit; 325 326 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 327 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 328 mutex_init(&mbox->lock); 329 330 return 0; 331 exit: 332 destroy_workqueue(vf->mbox_wq); 333 return err; 334 } 335 336 static int otx2vf_open(struct net_device *netdev) 337 { 338 struct otx2_nic *vf; 339 int err; 340 341 err = otx2_open(netdev); 342 if (err) 343 return err; 344 345 /* LBKs do not receive link events so tell everyone we are up here */ 346 vf = netdev_priv(netdev); 347 if (is_otx2_lbkvf(vf->pdev)) { 348 pr_info("%s NIC Link is UP\n", netdev->name); 349 netif_carrier_on(netdev); 350 netif_tx_start_all_queues(netdev); 351 } 352 353 return 0; 354 } 355 356 static int otx2vf_stop(struct net_device *netdev) 357 { 358 return otx2_stop(netdev); 359 } 360 361 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 362 { 363 struct otx2_nic *vf = netdev_priv(netdev); 364 int qidx = skb_get_queue_mapping(skb); 365 struct otx2_snd_queue *sq; 366 struct netdev_queue *txq; 367 368 sq = &vf->qset.sq[qidx]; 369 txq = netdev_get_tx_queue(netdev, qidx); 370 371 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 372 netif_tx_stop_queue(txq); 373 374 /* Check again, incase SQBs got freed up */ 375 smp_mb(); 376 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 377 > sq->sqe_thresh) 378 netif_tx_wake_queue(txq); 379 380 return NETDEV_TX_BUSY; 381 } 382 383 return NETDEV_TX_OK; 384 } 385 386 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 387 { 388 bool if_up = netif_running(netdev); 389 int err = 0; 390 391 if (if_up) 392 otx2vf_stop(netdev); 393 394 netdev_info(netdev, "Changing MTU from %d to %d\n", 395 netdev->mtu, new_mtu); 396 netdev->mtu = new_mtu; 397 398 if (if_up) 399 err = otx2vf_open(netdev); 400 401 return err; 402 } 403 404 static void otx2vf_reset_task(struct work_struct *work) 405 { 406 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 407 408 rtnl_lock(); 409 410 if (netif_running(vf->netdev)) { 411 otx2vf_stop(vf->netdev); 412 vf->reset_count++; 413 otx2vf_open(vf->netdev); 414 } 415 416 rtnl_unlock(); 417 } 418 419 static const struct net_device_ops otx2vf_netdev_ops = { 420 .ndo_open = otx2vf_open, 421 .ndo_stop = otx2vf_stop, 422 .ndo_start_xmit = otx2vf_xmit, 423 .ndo_set_mac_address = otx2_set_mac_address, 424 .ndo_change_mtu = otx2vf_change_mtu, 425 .ndo_get_stats64 = otx2_get_stats64, 426 .ndo_tx_timeout = otx2_tx_timeout, 427 }; 428 429 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 430 { 431 struct otx2_hw *hw = &vf->hw; 432 int num_vec, err; 433 434 num_vec = hw->nix_msixoff; 435 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 436 437 otx2vf_disable_mbox_intr(vf); 438 pci_free_irq_vectors(hw->pdev); 439 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 440 if (err < 0) { 441 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 442 __func__, num_vec); 443 return err; 444 } 445 446 return otx2vf_register_mbox_intr(vf, false); 447 } 448 449 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 450 { 451 int num_vec = pci_msix_vec_count(pdev); 452 struct device *dev = &pdev->dev; 453 struct net_device *netdev; 454 struct otx2_nic *vf; 455 struct otx2_hw *hw; 456 int err, qcount; 457 458 err = pcim_enable_device(pdev); 459 if (err) { 460 dev_err(dev, "Failed to enable PCI device\n"); 461 return err; 462 } 463 464 err = pci_request_regions(pdev, DRV_NAME); 465 if (err) { 466 dev_err(dev, "PCI request regions failed 0x%x\n", err); 467 return err; 468 } 469 470 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 471 if (err) { 472 dev_err(dev, "DMA mask config failed, abort\n"); 473 goto err_release_regions; 474 } 475 476 pci_set_master(pdev); 477 478 qcount = num_online_cpus(); 479 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount); 480 if (!netdev) { 481 err = -ENOMEM; 482 goto err_release_regions; 483 } 484 485 pci_set_drvdata(pdev, netdev); 486 SET_NETDEV_DEV(netdev, &pdev->dev); 487 vf = netdev_priv(netdev); 488 vf->netdev = netdev; 489 vf->pdev = pdev; 490 vf->dev = dev; 491 vf->iommu_domain = iommu_get_domain_for_dev(dev); 492 493 vf->flags |= OTX2_FLAG_INTF_DOWN; 494 hw = &vf->hw; 495 hw->pdev = vf->pdev; 496 hw->rx_queues = qcount; 497 hw->tx_queues = qcount; 498 hw->max_queues = qcount; 499 500 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 501 GFP_KERNEL); 502 if (!hw->irq_name) { 503 err = -ENOMEM; 504 goto err_free_netdev; 505 } 506 507 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 508 sizeof(cpumask_var_t), GFP_KERNEL); 509 if (!hw->affinity_mask) { 510 err = -ENOMEM; 511 goto err_free_netdev; 512 } 513 514 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 515 if (err < 0) { 516 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 517 __func__, num_vec); 518 goto err_free_netdev; 519 } 520 521 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 522 if (!vf->reg_base) { 523 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 524 err = -ENOMEM; 525 goto err_free_irq_vectors; 526 } 527 528 /* Init VF <=> PF mailbox stuff */ 529 err = otx2vf_vfaf_mbox_init(vf); 530 if (err) 531 goto err_free_irq_vectors; 532 533 /* Register mailbox interrupt */ 534 err = otx2vf_register_mbox_intr(vf, true); 535 if (err) 536 goto err_mbox_destroy; 537 538 /* Request AF to attach NPA and LIX LFs to this AF */ 539 err = otx2_attach_npa_nix(vf); 540 if (err) 541 goto err_disable_mbox_intr; 542 543 err = otx2vf_realloc_msix_vectors(vf); 544 if (err) 545 goto err_mbox_destroy; 546 547 err = otx2_set_real_num_queues(netdev, qcount, qcount); 548 if (err) 549 goto err_detach_rsrc; 550 551 otx2_setup_dev_hw_settings(vf); 552 553 /* Assign default mac address */ 554 otx2_get_mac_from_af(netdev); 555 556 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 557 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 558 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 559 NETIF_F_GSO_UDP_L4; 560 netdev->features = netdev->hw_features; 561 /* Support TSO on tag interface */ 562 netdev->vlan_features |= netdev->features; 563 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 564 NETIF_F_HW_VLAN_STAG_TX; 565 netdev->features |= netdev->hw_features; 566 567 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 568 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 569 570 netdev->netdev_ops = &otx2vf_netdev_ops; 571 572 /* MTU range: 68 - 9190 */ 573 netdev->min_mtu = OTX2_MIN_MTU; 574 netdev->max_mtu = OTX2_MAX_MTU; 575 576 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 577 578 /* To distinguish, for LBK VFs set netdev name explicitly */ 579 if (is_otx2_lbkvf(vf->pdev)) { 580 int n; 581 582 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 583 /* Need to subtract 1 to get proper VF number */ 584 n -= 1; 585 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 586 } 587 588 err = register_netdev(netdev); 589 if (err) { 590 dev_err(dev, "Failed to register netdevice\n"); 591 goto err_detach_rsrc; 592 } 593 594 otx2vf_set_ethtool_ops(netdev); 595 596 /* Enable pause frames by default */ 597 vf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 598 vf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 599 600 return 0; 601 602 err_detach_rsrc: 603 otx2_detach_resources(&vf->mbox); 604 err_disable_mbox_intr: 605 otx2vf_disable_mbox_intr(vf); 606 err_mbox_destroy: 607 otx2vf_vfaf_mbox_destroy(vf); 608 err_free_irq_vectors: 609 pci_free_irq_vectors(hw->pdev); 610 err_free_netdev: 611 pci_set_drvdata(pdev, NULL); 612 free_netdev(netdev); 613 err_release_regions: 614 pci_release_regions(pdev); 615 return err; 616 } 617 618 static void otx2vf_remove(struct pci_dev *pdev) 619 { 620 struct net_device *netdev = pci_get_drvdata(pdev); 621 struct otx2_nic *vf; 622 623 if (!netdev) 624 return; 625 626 vf = netdev_priv(netdev); 627 628 cancel_work_sync(&vf->reset_task); 629 unregister_netdev(netdev); 630 otx2vf_disable_mbox_intr(vf); 631 632 otx2_detach_resources(&vf->mbox); 633 otx2vf_vfaf_mbox_destroy(vf); 634 pci_free_irq_vectors(vf->pdev); 635 pci_set_drvdata(pdev, NULL); 636 free_netdev(netdev); 637 638 pci_release_regions(pdev); 639 } 640 641 static struct pci_driver otx2vf_driver = { 642 .name = DRV_NAME, 643 .id_table = otx2_vf_id_table, 644 .probe = otx2vf_probe, 645 .remove = otx2vf_remove, 646 .shutdown = otx2vf_remove, 647 }; 648 649 static int __init otx2vf_init_module(void) 650 { 651 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 652 653 return pci_register_driver(&otx2vf_driver); 654 } 655 656 static void __exit otx2vf_cleanup_module(void) 657 { 658 pci_unregister_driver(&otx2vf_driver); 659 } 660 661 module_init(otx2vf_init_module); 662 module_exit(otx2vf_cleanup_module); 663