1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Virtual Function ethernet driver */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 8 #include "otx2_common.h" 9 #include "otx2_reg.h" 10 #include "cn10k.h" 11 12 #define DRV_NAME "rvu_nicvf" 13 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 14 15 static const struct pci_device_id otx2_vf_id_table[] = { 16 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 17 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 18 { } 19 }; 20 21 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 22 MODULE_DESCRIPTION(DRV_STRING); 23 MODULE_LICENSE("GPL v2"); 24 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 25 26 /* RVU VF Interrupt Vector Enumeration */ 27 enum { 28 RVU_VF_INT_VEC_MBOX = 0x0, 29 }; 30 31 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 32 struct mbox_msghdr *msg) 33 { 34 if (msg->id >= MBOX_MSG_MAX) { 35 dev_err(vf->dev, 36 "Mbox msg with unknown ID %d\n", msg->id); 37 return; 38 } 39 40 if (msg->sig != OTX2_MBOX_RSP_SIG) { 41 dev_err(vf->dev, 42 "Mbox msg with wrong signature %x, ID %d\n", 43 msg->sig, msg->id); 44 return; 45 } 46 47 if (msg->rc == MBOX_MSG_INVALID) { 48 dev_err(vf->dev, 49 "PF/AF says the sent msg(s) %d were invalid\n", 50 msg->id); 51 return; 52 } 53 54 switch (msg->id) { 55 case MBOX_MSG_READY: 56 vf->pcifunc = msg->pcifunc; 57 break; 58 case MBOX_MSG_MSIX_OFFSET: 59 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 60 break; 61 case MBOX_MSG_NPA_LF_ALLOC: 62 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 63 break; 64 case MBOX_MSG_NIX_LF_ALLOC: 65 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 66 break; 67 case MBOX_MSG_NIX_TXSCH_ALLOC: 68 mbox_handler_nix_txsch_alloc(vf, 69 (struct nix_txsch_alloc_rsp *)msg); 70 break; 71 case MBOX_MSG_NIX_BP_ENABLE: 72 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 73 break; 74 default: 75 if (msg->rc) 76 dev_err(vf->dev, 77 "Mbox msg response has err %d, ID %d\n", 78 msg->rc, msg->id); 79 } 80 } 81 82 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 83 { 84 struct otx2_mbox_dev *mdev; 85 struct mbox_hdr *rsp_hdr; 86 struct mbox_msghdr *msg; 87 struct otx2_mbox *mbox; 88 struct mbox *af_mbox; 89 int offset, id; 90 91 af_mbox = container_of(work, struct mbox, mbox_wrk); 92 mbox = &af_mbox->mbox; 93 mdev = &mbox->dev[0]; 94 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 95 if (af_mbox->num_msgs == 0) 96 return; 97 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 98 99 for (id = 0; id < af_mbox->num_msgs; id++) { 100 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 101 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 102 offset = mbox->rx_start + msg->next_msgoff; 103 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 104 __otx2_mbox_reset(mbox, 0); 105 mdev->msgs_acked++; 106 } 107 } 108 109 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 110 struct mbox_msghdr *req) 111 { 112 struct msg_rsp *rsp; 113 int err; 114 115 /* Check if valid, if not reply with a invalid msg */ 116 if (req->sig != OTX2_MBOX_REQ_SIG) { 117 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 118 return -ENODEV; 119 } 120 121 switch (req->id) { 122 case MBOX_MSG_CGX_LINK_EVENT: 123 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 124 &vf->mbox.mbox_up, 0, 125 sizeof(struct msg_rsp)); 126 if (!rsp) 127 return -ENOMEM; 128 129 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 130 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 131 rsp->hdr.pcifunc = 0; 132 rsp->hdr.rc = 0; 133 err = otx2_mbox_up_handler_cgx_link_event( 134 vf, (struct cgx_link_info_msg *)req, rsp); 135 return err; 136 default: 137 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 138 return -ENODEV; 139 } 140 return 0; 141 } 142 143 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 144 { 145 struct otx2_mbox_dev *mdev; 146 struct mbox_hdr *rsp_hdr; 147 struct mbox_msghdr *msg; 148 struct otx2_mbox *mbox; 149 struct mbox *vf_mbox; 150 struct otx2_nic *vf; 151 int offset, id; 152 153 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 154 vf = vf_mbox->pfvf; 155 mbox = &vf_mbox->mbox_up; 156 mdev = &mbox->dev[0]; 157 158 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 159 if (vf_mbox->up_num_msgs == 0) 160 return; 161 162 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 163 164 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 165 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 166 otx2vf_process_mbox_msg_up(vf, msg); 167 offset = mbox->rx_start + msg->next_msgoff; 168 } 169 170 otx2_mbox_msg_send(mbox, 0); 171 } 172 173 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 174 { 175 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 176 struct otx2_mbox_dev *mdev; 177 struct otx2_mbox *mbox; 178 struct mbox_hdr *hdr; 179 180 /* Clear the IRQ */ 181 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 182 183 /* Read latest mbox data */ 184 smp_rmb(); 185 186 /* Check for PF => VF response messages */ 187 mbox = &vf->mbox.mbox; 188 mdev = &mbox->dev[0]; 189 otx2_sync_mbox_bbuf(mbox, 0); 190 191 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0)); 192 193 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 194 if (hdr->num_msgs) { 195 vf->mbox.num_msgs = hdr->num_msgs; 196 hdr->num_msgs = 0; 197 memset(mbox->hwbase + mbox->rx_start, 0, 198 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 199 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 200 } 201 /* Check for PF => VF notification messages */ 202 mbox = &vf->mbox.mbox_up; 203 mdev = &mbox->dev[0]; 204 otx2_sync_mbox_bbuf(mbox, 0); 205 206 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 207 if (hdr->num_msgs) { 208 vf->mbox.up_num_msgs = hdr->num_msgs; 209 hdr->num_msgs = 0; 210 memset(mbox->hwbase + mbox->rx_start, 0, 211 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 212 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 213 } 214 215 return IRQ_HANDLED; 216 } 217 218 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 219 { 220 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 221 222 /* Disable VF => PF mailbox IRQ */ 223 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 224 free_irq(vector, vf); 225 } 226 227 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 228 { 229 struct otx2_hw *hw = &vf->hw; 230 struct msg_req *req; 231 char *irq_name; 232 int err; 233 234 /* Register mailbox interrupt handler */ 235 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 236 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 237 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 238 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 239 if (err) { 240 dev_err(vf->dev, 241 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 242 return err; 243 } 244 245 /* Enable mailbox interrupt for msgs coming from PF. 246 * First clear to avoid spurious interrupts, if any. 247 */ 248 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 249 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 250 251 if (!probe_pf) 252 return 0; 253 254 /* Check mailbox communication with PF */ 255 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 256 if (!req) { 257 otx2vf_disable_mbox_intr(vf); 258 return -ENOMEM; 259 } 260 261 err = otx2_sync_mbox_msg(&vf->mbox); 262 if (err) { 263 dev_warn(vf->dev, 264 "AF not responding to mailbox, deferring probe\n"); 265 otx2vf_disable_mbox_intr(vf); 266 return -EPROBE_DEFER; 267 } 268 return 0; 269 } 270 271 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 272 { 273 struct mbox *mbox = &vf->mbox; 274 275 if (vf->mbox_wq) { 276 flush_workqueue(vf->mbox_wq); 277 destroy_workqueue(vf->mbox_wq); 278 vf->mbox_wq = NULL; 279 } 280 281 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 282 iounmap((void __iomem *)mbox->mbox.hwbase); 283 284 otx2_mbox_destroy(&mbox->mbox); 285 otx2_mbox_destroy(&mbox->mbox_up); 286 } 287 288 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 289 { 290 struct mbox *mbox = &vf->mbox; 291 void __iomem *hwbase; 292 int err; 293 294 mbox->pfvf = vf; 295 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox", 296 WQ_UNBOUND | WQ_HIGHPRI | 297 WQ_MEM_RECLAIM, 1); 298 if (!vf->mbox_wq) 299 return -ENOMEM; 300 301 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 302 /* For cn10k platform, VF mailbox region is in its BAR2 303 * register space 304 */ 305 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 306 } else { 307 /* Mailbox is a reserved memory (in RAM) region shared between 308 * admin function (i.e PF0) and this VF, shouldn't be mapped as 309 * device memory to allow unaligned accesses. 310 */ 311 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 312 PCI_MBOX_BAR_NUM), 313 pci_resource_len(vf->pdev, 314 PCI_MBOX_BAR_NUM)); 315 if (!hwbase) { 316 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 317 err = -ENOMEM; 318 goto exit; 319 } 320 } 321 322 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 323 MBOX_DIR_VFPF, 1); 324 if (err) 325 goto exit; 326 327 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 328 MBOX_DIR_VFPF_UP, 1); 329 if (err) 330 goto exit; 331 332 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 333 if (err) 334 goto exit; 335 336 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 337 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 338 mutex_init(&mbox->lock); 339 340 return 0; 341 exit: 342 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 343 iounmap(hwbase); 344 destroy_workqueue(vf->mbox_wq); 345 return err; 346 } 347 348 static int otx2vf_open(struct net_device *netdev) 349 { 350 struct otx2_nic *vf; 351 int err; 352 353 err = otx2_open(netdev); 354 if (err) 355 return err; 356 357 /* LBKs do not receive link events so tell everyone we are up here */ 358 vf = netdev_priv(netdev); 359 if (is_otx2_lbkvf(vf->pdev)) { 360 pr_info("%s NIC Link is UP\n", netdev->name); 361 netif_carrier_on(netdev); 362 netif_tx_start_all_queues(netdev); 363 } 364 365 return 0; 366 } 367 368 static int otx2vf_stop(struct net_device *netdev) 369 { 370 return otx2_stop(netdev); 371 } 372 373 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 374 { 375 struct otx2_nic *vf = netdev_priv(netdev); 376 int qidx = skb_get_queue_mapping(skb); 377 struct otx2_snd_queue *sq; 378 struct netdev_queue *txq; 379 380 sq = &vf->qset.sq[qidx]; 381 txq = netdev_get_tx_queue(netdev, qidx); 382 383 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 384 netif_tx_stop_queue(txq); 385 386 /* Check again, incase SQBs got freed up */ 387 smp_mb(); 388 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 389 > sq->sqe_thresh) 390 netif_tx_wake_queue(txq); 391 392 return NETDEV_TX_BUSY; 393 } 394 395 return NETDEV_TX_OK; 396 } 397 398 static void otx2vf_set_rx_mode(struct net_device *netdev) 399 { 400 struct otx2_nic *vf = netdev_priv(netdev); 401 402 queue_work(vf->otx2_wq, &vf->rx_mode_work); 403 } 404 405 static void otx2vf_do_set_rx_mode(struct work_struct *work) 406 { 407 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 408 struct net_device *netdev = vf->netdev; 409 unsigned int flags = netdev->flags; 410 struct nix_rx_mode *req; 411 412 mutex_lock(&vf->mbox.lock); 413 414 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 415 if (!req) { 416 mutex_unlock(&vf->mbox.lock); 417 return; 418 } 419 420 req->mode = NIX_RX_MODE_UCAST; 421 422 if (flags & IFF_PROMISC) 423 req->mode |= NIX_RX_MODE_PROMISC; 424 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 425 req->mode |= NIX_RX_MODE_ALLMULTI; 426 427 req->mode |= NIX_RX_MODE_USE_MCE; 428 429 otx2_sync_mbox_msg(&vf->mbox); 430 431 mutex_unlock(&vf->mbox.lock); 432 } 433 434 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 435 { 436 bool if_up = netif_running(netdev); 437 int err = 0; 438 439 if (if_up) 440 otx2vf_stop(netdev); 441 442 netdev_info(netdev, "Changing MTU from %d to %d\n", 443 netdev->mtu, new_mtu); 444 netdev->mtu = new_mtu; 445 446 if (if_up) 447 err = otx2vf_open(netdev); 448 449 return err; 450 } 451 452 static void otx2vf_reset_task(struct work_struct *work) 453 { 454 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 455 456 rtnl_lock(); 457 458 if (netif_running(vf->netdev)) { 459 otx2vf_stop(vf->netdev); 460 vf->reset_count++; 461 otx2vf_open(vf->netdev); 462 } 463 464 rtnl_unlock(); 465 } 466 467 static const struct net_device_ops otx2vf_netdev_ops = { 468 .ndo_open = otx2vf_open, 469 .ndo_stop = otx2vf_stop, 470 .ndo_start_xmit = otx2vf_xmit, 471 .ndo_set_rx_mode = otx2vf_set_rx_mode, 472 .ndo_set_mac_address = otx2_set_mac_address, 473 .ndo_change_mtu = otx2vf_change_mtu, 474 .ndo_get_stats64 = otx2_get_stats64, 475 .ndo_tx_timeout = otx2_tx_timeout, 476 }; 477 478 static int otx2_wq_init(struct otx2_nic *vf) 479 { 480 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 481 if (!vf->otx2_wq) 482 return -ENOMEM; 483 484 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 485 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 486 return 0; 487 } 488 489 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 490 { 491 struct otx2_hw *hw = &vf->hw; 492 int num_vec, err; 493 494 num_vec = hw->nix_msixoff; 495 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 496 497 otx2vf_disable_mbox_intr(vf); 498 pci_free_irq_vectors(hw->pdev); 499 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 500 if (err < 0) { 501 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 502 __func__, num_vec); 503 return err; 504 } 505 506 return otx2vf_register_mbox_intr(vf, false); 507 } 508 509 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 510 { 511 int num_vec = pci_msix_vec_count(pdev); 512 struct device *dev = &pdev->dev; 513 struct net_device *netdev; 514 struct otx2_nic *vf; 515 struct otx2_hw *hw; 516 int err, qcount; 517 518 err = pcim_enable_device(pdev); 519 if (err) { 520 dev_err(dev, "Failed to enable PCI device\n"); 521 return err; 522 } 523 524 err = pci_request_regions(pdev, DRV_NAME); 525 if (err) { 526 dev_err(dev, "PCI request regions failed 0x%x\n", err); 527 return err; 528 } 529 530 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 531 if (err) { 532 dev_err(dev, "DMA mask config failed, abort\n"); 533 goto err_release_regions; 534 } 535 536 pci_set_master(pdev); 537 538 qcount = num_online_cpus(); 539 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount, qcount); 540 if (!netdev) { 541 err = -ENOMEM; 542 goto err_release_regions; 543 } 544 545 pci_set_drvdata(pdev, netdev); 546 SET_NETDEV_DEV(netdev, &pdev->dev); 547 vf = netdev_priv(netdev); 548 vf->netdev = netdev; 549 vf->pdev = pdev; 550 vf->dev = dev; 551 vf->iommu_domain = iommu_get_domain_for_dev(dev); 552 553 vf->flags |= OTX2_FLAG_INTF_DOWN; 554 hw = &vf->hw; 555 hw->pdev = vf->pdev; 556 hw->rx_queues = qcount; 557 hw->tx_queues = qcount; 558 hw->max_queues = qcount; 559 560 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 561 GFP_KERNEL); 562 if (!hw->irq_name) { 563 err = -ENOMEM; 564 goto err_free_netdev; 565 } 566 567 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 568 sizeof(cpumask_var_t), GFP_KERNEL); 569 if (!hw->affinity_mask) { 570 err = -ENOMEM; 571 goto err_free_netdev; 572 } 573 574 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 575 if (err < 0) { 576 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 577 __func__, num_vec); 578 goto err_free_netdev; 579 } 580 581 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 582 if (!vf->reg_base) { 583 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 584 err = -ENOMEM; 585 goto err_free_irq_vectors; 586 } 587 588 otx2_setup_dev_hw_settings(vf); 589 /* Init VF <=> PF mailbox stuff */ 590 err = otx2vf_vfaf_mbox_init(vf); 591 if (err) 592 goto err_free_irq_vectors; 593 594 /* Register mailbox interrupt */ 595 err = otx2vf_register_mbox_intr(vf, true); 596 if (err) 597 goto err_mbox_destroy; 598 599 /* Request AF to attach NPA and LIX LFs to this AF */ 600 err = otx2_attach_npa_nix(vf); 601 if (err) 602 goto err_disable_mbox_intr; 603 604 err = otx2vf_realloc_msix_vectors(vf); 605 if (err) 606 goto err_mbox_destroy; 607 608 err = otx2_set_real_num_queues(netdev, qcount, qcount); 609 if (err) 610 goto err_detach_rsrc; 611 612 err = cn10k_vf_lmtst_init(vf); 613 if (err) 614 goto err_detach_rsrc; 615 616 /* Assign default mac address */ 617 otx2_get_mac_from_af(netdev); 618 619 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 620 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 621 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 622 NETIF_F_GSO_UDP_L4; 623 netdev->features = netdev->hw_features; 624 /* Support TSO on tag interface */ 625 netdev->vlan_features |= netdev->features; 626 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 627 NETIF_F_HW_VLAN_STAG_TX; 628 netdev->features |= netdev->hw_features; 629 630 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 631 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 632 633 netdev->netdev_ops = &otx2vf_netdev_ops; 634 635 /* MTU range: 68 - 9190 */ 636 netdev->min_mtu = OTX2_MIN_MTU; 637 netdev->max_mtu = otx2_get_max_mtu(vf); 638 639 /* To distinguish, for LBK VFs set netdev name explicitly */ 640 if (is_otx2_lbkvf(vf->pdev)) { 641 int n; 642 643 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 644 /* Need to subtract 1 to get proper VF number */ 645 n -= 1; 646 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 647 } 648 649 err = register_netdev(netdev); 650 if (err) { 651 dev_err(dev, "Failed to register netdevice\n"); 652 goto err_detach_rsrc; 653 } 654 655 err = otx2_wq_init(vf); 656 if (err) 657 goto err_unreg_netdev; 658 659 otx2vf_set_ethtool_ops(netdev); 660 661 /* Enable pause frames by default */ 662 vf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 663 vf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 664 665 return 0; 666 667 err_unreg_netdev: 668 unregister_netdev(netdev); 669 err_detach_rsrc: 670 if (hw->lmt_base) 671 iounmap(hw->lmt_base); 672 otx2_detach_resources(&vf->mbox); 673 err_disable_mbox_intr: 674 otx2vf_disable_mbox_intr(vf); 675 err_mbox_destroy: 676 otx2vf_vfaf_mbox_destroy(vf); 677 err_free_irq_vectors: 678 pci_free_irq_vectors(hw->pdev); 679 err_free_netdev: 680 pci_set_drvdata(pdev, NULL); 681 free_netdev(netdev); 682 err_release_regions: 683 pci_release_regions(pdev); 684 return err; 685 } 686 687 static void otx2vf_remove(struct pci_dev *pdev) 688 { 689 struct net_device *netdev = pci_get_drvdata(pdev); 690 struct otx2_nic *vf; 691 692 if (!netdev) 693 return; 694 695 vf = netdev_priv(netdev); 696 697 cancel_work_sync(&vf->reset_task); 698 unregister_netdev(netdev); 699 if (vf->otx2_wq) 700 destroy_workqueue(vf->otx2_wq); 701 otx2vf_disable_mbox_intr(vf); 702 otx2_detach_resources(&vf->mbox); 703 704 if (vf->hw.lmt_base) 705 iounmap(vf->hw.lmt_base); 706 707 otx2vf_vfaf_mbox_destroy(vf); 708 pci_free_irq_vectors(vf->pdev); 709 pci_set_drvdata(pdev, NULL); 710 free_netdev(netdev); 711 712 pci_release_regions(pdev); 713 } 714 715 static struct pci_driver otx2vf_driver = { 716 .name = DRV_NAME, 717 .id_table = otx2_vf_id_table, 718 .probe = otx2vf_probe, 719 .remove = otx2vf_remove, 720 .shutdown = otx2vf_remove, 721 }; 722 723 static int __init otx2vf_init_module(void) 724 { 725 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 726 727 return pci_register_driver(&otx2vf_driver); 728 } 729 730 static void __exit otx2vf_cleanup_module(void) 731 { 732 pci_unregister_driver(&otx2vf_driver); 733 } 734 735 module_init(otx2vf_init_module); 736 module_exit(otx2vf_cleanup_module); 737