1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Virtual Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include <linux/net_tstamp.h> 12 13 #include "otx2_common.h" 14 #include "otx2_reg.h" 15 #include "otx2_ptp.h" 16 #include "cn10k.h" 17 18 #define DRV_NAME "rvu_nicvf" 19 #define DRV_STRING "Marvell RVU NIC Virtual Function Driver" 20 21 static const struct pci_device_id otx2_vf_id_table[] = { 22 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) }, 23 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_VF) }, 24 { } 25 }; 26 27 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 28 MODULE_DESCRIPTION(DRV_STRING); 29 MODULE_LICENSE("GPL v2"); 30 MODULE_DEVICE_TABLE(pci, otx2_vf_id_table); 31 32 /* RVU VF Interrupt Vector Enumeration */ 33 enum { 34 RVU_VF_INT_VEC_MBOX = 0x0, 35 }; 36 37 static void otx2vf_process_vfaf_mbox_msg(struct otx2_nic *vf, 38 struct mbox_msghdr *msg) 39 { 40 if (msg->id >= MBOX_MSG_MAX) { 41 dev_err(vf->dev, 42 "Mbox msg with unknown ID %d\n", msg->id); 43 return; 44 } 45 46 if (msg->sig != OTX2_MBOX_RSP_SIG) { 47 dev_err(vf->dev, 48 "Mbox msg with wrong signature %x, ID %d\n", 49 msg->sig, msg->id); 50 return; 51 } 52 53 if (msg->rc == MBOX_MSG_INVALID) { 54 dev_err(vf->dev, 55 "PF/AF says the sent msg(s) %d were invalid\n", 56 msg->id); 57 return; 58 } 59 60 switch (msg->id) { 61 case MBOX_MSG_READY: 62 vf->pcifunc = msg->pcifunc; 63 break; 64 case MBOX_MSG_MSIX_OFFSET: 65 mbox_handler_msix_offset(vf, (struct msix_offset_rsp *)msg); 66 break; 67 case MBOX_MSG_NPA_LF_ALLOC: 68 mbox_handler_npa_lf_alloc(vf, (struct npa_lf_alloc_rsp *)msg); 69 break; 70 case MBOX_MSG_NIX_LF_ALLOC: 71 mbox_handler_nix_lf_alloc(vf, (struct nix_lf_alloc_rsp *)msg); 72 break; 73 case MBOX_MSG_NIX_BP_ENABLE: 74 mbox_handler_nix_bp_enable(vf, (struct nix_bp_cfg_rsp *)msg); 75 break; 76 default: 77 if (msg->rc) 78 dev_err(vf->dev, 79 "Mbox msg response has err %d, ID %d\n", 80 msg->rc, msg->id); 81 } 82 } 83 84 static void otx2vf_vfaf_mbox_handler(struct work_struct *work) 85 { 86 struct otx2_mbox_dev *mdev; 87 struct mbox_hdr *rsp_hdr; 88 struct mbox_msghdr *msg; 89 struct otx2_mbox *mbox; 90 struct mbox *af_mbox; 91 int offset, id; 92 93 af_mbox = container_of(work, struct mbox, mbox_wrk); 94 mbox = &af_mbox->mbox; 95 mdev = &mbox->dev[0]; 96 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 97 if (af_mbox->num_msgs == 0) 98 return; 99 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 100 101 for (id = 0; id < af_mbox->num_msgs; id++) { 102 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 103 otx2vf_process_vfaf_mbox_msg(af_mbox->pfvf, msg); 104 offset = mbox->rx_start + msg->next_msgoff; 105 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 106 __otx2_mbox_reset(mbox, 0); 107 mdev->msgs_acked++; 108 } 109 } 110 111 static int otx2vf_process_mbox_msg_up(struct otx2_nic *vf, 112 struct mbox_msghdr *req) 113 { 114 struct msg_rsp *rsp; 115 int err; 116 117 /* Check if valid, if not reply with a invalid msg */ 118 if (req->sig != OTX2_MBOX_REQ_SIG) { 119 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 120 return -ENODEV; 121 } 122 123 switch (req->id) { 124 case MBOX_MSG_CGX_LINK_EVENT: 125 rsp = (struct msg_rsp *)otx2_mbox_alloc_msg( 126 &vf->mbox.mbox_up, 0, 127 sizeof(struct msg_rsp)); 128 if (!rsp) 129 return -ENOMEM; 130 131 rsp->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 132 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; 133 rsp->hdr.pcifunc = 0; 134 rsp->hdr.rc = 0; 135 err = otx2_mbox_up_handler_cgx_link_event( 136 vf, (struct cgx_link_info_msg *)req, rsp); 137 return err; 138 default: 139 otx2_reply_invalid_msg(&vf->mbox.mbox_up, 0, 0, req->id); 140 return -ENODEV; 141 } 142 return 0; 143 } 144 145 static void otx2vf_vfaf_mbox_up_handler(struct work_struct *work) 146 { 147 struct otx2_mbox_dev *mdev; 148 struct mbox_hdr *rsp_hdr; 149 struct mbox_msghdr *msg; 150 struct otx2_mbox *mbox; 151 struct mbox *vf_mbox; 152 struct otx2_nic *vf; 153 int offset, id; 154 155 vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 156 vf = vf_mbox->pfvf; 157 mbox = &vf_mbox->mbox_up; 158 mdev = &mbox->dev[0]; 159 160 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 161 if (vf_mbox->up_num_msgs == 0) 162 return; 163 164 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 165 166 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 167 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 168 otx2vf_process_mbox_msg_up(vf, msg); 169 offset = mbox->rx_start + msg->next_msgoff; 170 } 171 172 otx2_mbox_msg_send(mbox, 0); 173 } 174 175 static irqreturn_t otx2vf_vfaf_mbox_intr_handler(int irq, void *vf_irq) 176 { 177 struct otx2_nic *vf = (struct otx2_nic *)vf_irq; 178 struct otx2_mbox_dev *mdev; 179 struct otx2_mbox *mbox; 180 struct mbox_hdr *hdr; 181 182 /* Clear the IRQ */ 183 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 184 185 /* Read latest mbox data */ 186 smp_rmb(); 187 188 /* Check for PF => VF response messages */ 189 mbox = &vf->mbox.mbox; 190 mdev = &mbox->dev[0]; 191 otx2_sync_mbox_bbuf(mbox, 0); 192 193 trace_otx2_msg_interrupt(mbox->pdev, "PF to VF", BIT_ULL(0)); 194 195 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 196 if (hdr->num_msgs) { 197 vf->mbox.num_msgs = hdr->num_msgs; 198 hdr->num_msgs = 0; 199 memset(mbox->hwbase + mbox->rx_start, 0, 200 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 201 queue_work(vf->mbox_wq, &vf->mbox.mbox_wrk); 202 } 203 /* Check for PF => VF notification messages */ 204 mbox = &vf->mbox.mbox_up; 205 mdev = &mbox->dev[0]; 206 otx2_sync_mbox_bbuf(mbox, 0); 207 208 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 209 if (hdr->num_msgs) { 210 vf->mbox.up_num_msgs = hdr->num_msgs; 211 hdr->num_msgs = 0; 212 memset(mbox->hwbase + mbox->rx_start, 0, 213 ALIGN(sizeof(struct mbox_hdr), sizeof(u64))); 214 queue_work(vf->mbox_wq, &vf->mbox.mbox_up_wrk); 215 } 216 217 return IRQ_HANDLED; 218 } 219 220 static void otx2vf_disable_mbox_intr(struct otx2_nic *vf) 221 { 222 int vector = pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX); 223 224 /* Disable VF => PF mailbox IRQ */ 225 otx2_write64(vf, RVU_VF_INT_ENA_W1C, BIT_ULL(0)); 226 free_irq(vector, vf); 227 } 228 229 static int otx2vf_register_mbox_intr(struct otx2_nic *vf, bool probe_pf) 230 { 231 struct otx2_hw *hw = &vf->hw; 232 struct msg_req *req; 233 char *irq_name; 234 int err; 235 236 /* Register mailbox interrupt handler */ 237 irq_name = &hw->irq_name[RVU_VF_INT_VEC_MBOX * NAME_SIZE]; 238 snprintf(irq_name, NAME_SIZE, "RVUVFAF Mbox"); 239 err = request_irq(pci_irq_vector(vf->pdev, RVU_VF_INT_VEC_MBOX), 240 otx2vf_vfaf_mbox_intr_handler, 0, irq_name, vf); 241 if (err) { 242 dev_err(vf->dev, 243 "RVUPF: IRQ registration failed for VFAF mbox irq\n"); 244 return err; 245 } 246 247 /* Enable mailbox interrupt for msgs coming from PF. 248 * First clear to avoid spurious interrupts, if any. 249 */ 250 otx2_write64(vf, RVU_VF_INT, BIT_ULL(0)); 251 otx2_write64(vf, RVU_VF_INT_ENA_W1S, BIT_ULL(0)); 252 253 if (!probe_pf) 254 return 0; 255 256 /* Check mailbox communication with PF */ 257 req = otx2_mbox_alloc_msg_ready(&vf->mbox); 258 if (!req) { 259 otx2vf_disable_mbox_intr(vf); 260 return -ENOMEM; 261 } 262 263 err = otx2_sync_mbox_msg(&vf->mbox); 264 if (err) { 265 dev_warn(vf->dev, 266 "AF not responding to mailbox, deferring probe\n"); 267 otx2vf_disable_mbox_intr(vf); 268 return -EPROBE_DEFER; 269 } 270 return 0; 271 } 272 273 static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf) 274 { 275 struct mbox *mbox = &vf->mbox; 276 277 if (vf->mbox_wq) { 278 destroy_workqueue(vf->mbox_wq); 279 vf->mbox_wq = NULL; 280 } 281 282 if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 283 iounmap((void __iomem *)mbox->mbox.hwbase); 284 285 otx2_mbox_destroy(&mbox->mbox); 286 otx2_mbox_destroy(&mbox->mbox_up); 287 } 288 289 static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf) 290 { 291 struct mbox *mbox = &vf->mbox; 292 void __iomem *hwbase; 293 int err; 294 295 mbox->pfvf = vf; 296 vf->mbox_wq = alloc_workqueue("otx2_vfaf_mailbox", 297 WQ_UNBOUND | WQ_HIGHPRI | 298 WQ_MEM_RECLAIM, 1); 299 if (!vf->mbox_wq) 300 return -ENOMEM; 301 302 if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) { 303 /* For cn10k platform, VF mailbox region is in its BAR2 304 * register space 305 */ 306 hwbase = vf->reg_base + RVU_VF_MBOX_REGION; 307 } else { 308 /* Mailbox is a reserved memory (in RAM) region shared between 309 * admin function (i.e PF0) and this VF, shouldn't be mapped as 310 * device memory to allow unaligned accesses. 311 */ 312 hwbase = ioremap_wc(pci_resource_start(vf->pdev, 313 PCI_MBOX_BAR_NUM), 314 pci_resource_len(vf->pdev, 315 PCI_MBOX_BAR_NUM)); 316 if (!hwbase) { 317 dev_err(vf->dev, "Unable to map VFAF mailbox region\n"); 318 err = -ENOMEM; 319 goto exit; 320 } 321 } 322 323 err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base, 324 MBOX_DIR_VFPF, 1); 325 if (err) 326 goto exit; 327 328 err = otx2_mbox_init(&mbox->mbox_up, hwbase, vf->pdev, vf->reg_base, 329 MBOX_DIR_VFPF_UP, 1); 330 if (err) 331 goto exit; 332 333 err = otx2_mbox_bbuf_init(mbox, vf->pdev); 334 if (err) 335 goto exit; 336 337 INIT_WORK(&mbox->mbox_wrk, otx2vf_vfaf_mbox_handler); 338 INIT_WORK(&mbox->mbox_up_wrk, otx2vf_vfaf_mbox_up_handler); 339 mutex_init(&mbox->lock); 340 341 return 0; 342 exit: 343 if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag)) 344 iounmap(hwbase); 345 destroy_workqueue(vf->mbox_wq); 346 return err; 347 } 348 349 static int otx2vf_open(struct net_device *netdev) 350 { 351 struct otx2_nic *vf; 352 int err; 353 354 err = otx2_open(netdev); 355 if (err) 356 return err; 357 358 /* LBKs do not receive link events so tell everyone we are up here */ 359 vf = netdev_priv(netdev); 360 if (is_otx2_lbkvf(vf->pdev)) { 361 pr_info("%s NIC Link is UP\n", netdev->name); 362 netif_carrier_on(netdev); 363 netif_tx_start_all_queues(netdev); 364 } 365 366 return 0; 367 } 368 369 static int otx2vf_stop(struct net_device *netdev) 370 { 371 return otx2_stop(netdev); 372 } 373 374 static netdev_tx_t otx2vf_xmit(struct sk_buff *skb, struct net_device *netdev) 375 { 376 struct otx2_nic *vf = netdev_priv(netdev); 377 int qidx = skb_get_queue_mapping(skb); 378 struct otx2_snd_queue *sq; 379 struct netdev_queue *txq; 380 381 sq = &vf->qset.sq[qidx]; 382 txq = netdev_get_tx_queue(netdev, qidx); 383 384 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 385 netif_tx_stop_queue(txq); 386 387 /* Check again, incase SQBs got freed up */ 388 smp_mb(); 389 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 390 > sq->sqe_thresh) 391 netif_tx_wake_queue(txq); 392 393 return NETDEV_TX_BUSY; 394 } 395 396 return NETDEV_TX_OK; 397 } 398 399 static void otx2vf_set_rx_mode(struct net_device *netdev) 400 { 401 struct otx2_nic *vf = netdev_priv(netdev); 402 403 queue_work(vf->otx2_wq, &vf->rx_mode_work); 404 } 405 406 static void otx2vf_do_set_rx_mode(struct work_struct *work) 407 { 408 struct otx2_nic *vf = container_of(work, struct otx2_nic, rx_mode_work); 409 struct net_device *netdev = vf->netdev; 410 unsigned int flags = netdev->flags; 411 struct nix_rx_mode *req; 412 413 mutex_lock(&vf->mbox.lock); 414 415 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&vf->mbox); 416 if (!req) { 417 mutex_unlock(&vf->mbox.lock); 418 return; 419 } 420 421 req->mode = NIX_RX_MODE_UCAST; 422 423 if (flags & IFF_PROMISC) 424 req->mode |= NIX_RX_MODE_PROMISC; 425 if (flags & (IFF_ALLMULTI | IFF_MULTICAST)) 426 req->mode |= NIX_RX_MODE_ALLMULTI; 427 428 req->mode |= NIX_RX_MODE_USE_MCE; 429 430 otx2_sync_mbox_msg(&vf->mbox); 431 432 mutex_unlock(&vf->mbox.lock); 433 } 434 435 static int otx2vf_change_mtu(struct net_device *netdev, int new_mtu) 436 { 437 bool if_up = netif_running(netdev); 438 int err = 0; 439 440 if (if_up) 441 otx2vf_stop(netdev); 442 443 netdev_info(netdev, "Changing MTU from %d to %d\n", 444 netdev->mtu, new_mtu); 445 netdev->mtu = new_mtu; 446 447 if (if_up) 448 err = otx2vf_open(netdev); 449 450 return err; 451 } 452 453 static void otx2vf_reset_task(struct work_struct *work) 454 { 455 struct otx2_nic *vf = container_of(work, struct otx2_nic, reset_task); 456 457 rtnl_lock(); 458 459 if (netif_running(vf->netdev)) { 460 otx2vf_stop(vf->netdev); 461 vf->reset_count++; 462 otx2vf_open(vf->netdev); 463 } 464 465 rtnl_unlock(); 466 } 467 468 static int otx2vf_set_features(struct net_device *netdev, 469 netdev_features_t features) 470 { 471 return otx2_handle_ntuple_tc_features(netdev, features); 472 } 473 474 static const struct net_device_ops otx2vf_netdev_ops = { 475 .ndo_open = otx2vf_open, 476 .ndo_stop = otx2vf_stop, 477 .ndo_start_xmit = otx2vf_xmit, 478 .ndo_select_queue = otx2_select_queue, 479 .ndo_set_rx_mode = otx2vf_set_rx_mode, 480 .ndo_set_mac_address = otx2_set_mac_address, 481 .ndo_change_mtu = otx2vf_change_mtu, 482 .ndo_set_features = otx2vf_set_features, 483 .ndo_get_stats64 = otx2_get_stats64, 484 .ndo_tx_timeout = otx2_tx_timeout, 485 .ndo_eth_ioctl = otx2_ioctl, 486 .ndo_setup_tc = otx2_setup_tc, 487 }; 488 489 static int otx2_wq_init(struct otx2_nic *vf) 490 { 491 vf->otx2_wq = create_singlethread_workqueue("otx2vf_wq"); 492 if (!vf->otx2_wq) 493 return -ENOMEM; 494 495 INIT_WORK(&vf->rx_mode_work, otx2vf_do_set_rx_mode); 496 INIT_WORK(&vf->reset_task, otx2vf_reset_task); 497 return 0; 498 } 499 500 static int otx2vf_realloc_msix_vectors(struct otx2_nic *vf) 501 { 502 struct otx2_hw *hw = &vf->hw; 503 int num_vec, err; 504 505 num_vec = hw->nix_msixoff; 506 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 507 508 otx2vf_disable_mbox_intr(vf); 509 pci_free_irq_vectors(hw->pdev); 510 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 511 if (err < 0) { 512 dev_err(vf->dev, "%s: Failed to realloc %d IRQ vectors\n", 513 __func__, num_vec); 514 return err; 515 } 516 517 return otx2vf_register_mbox_intr(vf, false); 518 } 519 520 static int otx2vf_probe(struct pci_dev *pdev, const struct pci_device_id *id) 521 { 522 int num_vec = pci_msix_vec_count(pdev); 523 struct device *dev = &pdev->dev; 524 int err, qcount, qos_txqs; 525 struct net_device *netdev; 526 struct otx2_nic *vf; 527 struct otx2_hw *hw; 528 529 err = pcim_enable_device(pdev); 530 if (err) { 531 dev_err(dev, "Failed to enable PCI device\n"); 532 return err; 533 } 534 535 err = pci_request_regions(pdev, DRV_NAME); 536 if (err) { 537 dev_err(dev, "PCI request regions failed 0x%x\n", err); 538 return err; 539 } 540 541 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 542 if (err) { 543 dev_err(dev, "DMA mask config failed, abort\n"); 544 goto err_release_regions; 545 } 546 547 pci_set_master(pdev); 548 549 qcount = num_online_cpus(); 550 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 551 netdev = alloc_etherdev_mqs(sizeof(*vf), qcount + qos_txqs, qcount); 552 if (!netdev) { 553 err = -ENOMEM; 554 goto err_release_regions; 555 } 556 557 pci_set_drvdata(pdev, netdev); 558 SET_NETDEV_DEV(netdev, &pdev->dev); 559 vf = netdev_priv(netdev); 560 vf->netdev = netdev; 561 vf->pdev = pdev; 562 vf->dev = dev; 563 vf->iommu_domain = iommu_get_domain_for_dev(dev); 564 565 vf->flags |= OTX2_FLAG_INTF_DOWN; 566 hw = &vf->hw; 567 hw->pdev = vf->pdev; 568 hw->rx_queues = qcount; 569 hw->tx_queues = qcount; 570 hw->max_queues = qcount; 571 hw->non_qos_queues = qcount; 572 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 573 /* Use CQE of 128 byte descriptor size by default */ 574 hw->xqe_size = 128; 575 576 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 577 GFP_KERNEL); 578 if (!hw->irq_name) { 579 err = -ENOMEM; 580 goto err_free_netdev; 581 } 582 583 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 584 sizeof(cpumask_var_t), GFP_KERNEL); 585 if (!hw->affinity_mask) { 586 err = -ENOMEM; 587 goto err_free_netdev; 588 } 589 590 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 591 if (err < 0) { 592 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 593 __func__, num_vec); 594 goto err_free_netdev; 595 } 596 597 vf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 598 if (!vf->reg_base) { 599 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 600 err = -ENOMEM; 601 goto err_free_irq_vectors; 602 } 603 604 otx2_setup_dev_hw_settings(vf); 605 /* Init VF <=> PF mailbox stuff */ 606 err = otx2vf_vfaf_mbox_init(vf); 607 if (err) 608 goto err_free_irq_vectors; 609 610 /* Register mailbox interrupt */ 611 err = otx2vf_register_mbox_intr(vf, true); 612 if (err) 613 goto err_mbox_destroy; 614 615 /* Request AF to attach NPA and LIX LFs to this AF */ 616 err = otx2_attach_npa_nix(vf); 617 if (err) 618 goto err_disable_mbox_intr; 619 620 err = otx2vf_realloc_msix_vectors(vf); 621 if (err) 622 goto err_detach_rsrc; 623 624 err = otx2_set_real_num_queues(netdev, qcount, qcount); 625 if (err) 626 goto err_detach_rsrc; 627 628 err = cn10k_lmtst_init(vf); 629 if (err) 630 goto err_detach_rsrc; 631 632 /* Don't check for error. Proceed without ptp */ 633 otx2_ptp_init(vf); 634 635 /* Assign default mac address */ 636 otx2_get_mac_from_af(netdev); 637 638 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 639 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 640 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 641 NETIF_F_GSO_UDP_L4; 642 netdev->features = netdev->hw_features; 643 /* Support TSO on tag interface */ 644 netdev->vlan_features |= netdev->features; 645 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 646 NETIF_F_HW_VLAN_STAG_TX; 647 netdev->features |= netdev->hw_features; 648 649 netdev->hw_features |= NETIF_F_NTUPLE; 650 netdev->hw_features |= NETIF_F_RXALL; 651 netdev->hw_features |= NETIF_F_HW_TC; 652 653 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 654 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 655 656 netdev->netdev_ops = &otx2vf_netdev_ops; 657 658 netdev->min_mtu = OTX2_MIN_MTU; 659 netdev->max_mtu = otx2_get_max_mtu(vf); 660 661 /* To distinguish, for LBK VFs set netdev name explicitly */ 662 if (is_otx2_lbkvf(vf->pdev)) { 663 int n; 664 665 n = (vf->pcifunc >> RVU_PFVF_FUNC_SHIFT) & RVU_PFVF_FUNC_MASK; 666 /* Need to subtract 1 to get proper VF number */ 667 n -= 1; 668 snprintf(netdev->name, sizeof(netdev->name), "lbk%d", n); 669 } 670 671 err = register_netdev(netdev); 672 if (err) { 673 dev_err(dev, "Failed to register netdevice\n"); 674 goto err_ptp_destroy; 675 } 676 677 err = otx2_wq_init(vf); 678 if (err) 679 goto err_unreg_netdev; 680 681 otx2vf_set_ethtool_ops(netdev); 682 683 err = otx2vf_mcam_flow_init(vf); 684 if (err) 685 goto err_unreg_netdev; 686 687 err = otx2_init_tc(vf); 688 if (err) 689 goto err_unreg_netdev; 690 691 err = otx2_register_dl(vf); 692 if (err) 693 goto err_shutdown_tc; 694 695 #ifdef CONFIG_DCB 696 err = otx2_dcbnl_set_ops(netdev); 697 if (err) 698 goto err_shutdown_tc; 699 #endif 700 otx2_qos_init(vf, qos_txqs); 701 702 return 0; 703 704 err_shutdown_tc: 705 otx2_shutdown_tc(vf); 706 err_unreg_netdev: 707 unregister_netdev(netdev); 708 err_ptp_destroy: 709 otx2_ptp_destroy(vf); 710 err_detach_rsrc: 711 free_percpu(vf->hw.lmt_info); 712 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 713 qmem_free(vf->dev, vf->dync_lmt); 714 otx2_detach_resources(&vf->mbox); 715 err_disable_mbox_intr: 716 otx2vf_disable_mbox_intr(vf); 717 err_mbox_destroy: 718 otx2vf_vfaf_mbox_destroy(vf); 719 err_free_irq_vectors: 720 pci_free_irq_vectors(hw->pdev); 721 err_free_netdev: 722 pci_set_drvdata(pdev, NULL); 723 free_netdev(netdev); 724 err_release_regions: 725 pci_release_regions(pdev); 726 return err; 727 } 728 729 static void otx2vf_remove(struct pci_dev *pdev) 730 { 731 struct net_device *netdev = pci_get_drvdata(pdev); 732 struct otx2_nic *vf; 733 734 if (!netdev) 735 return; 736 737 vf = netdev_priv(netdev); 738 739 /* Disable 802.3x pause frames */ 740 if (vf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 741 (vf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 742 vf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 743 vf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 744 otx2_config_pause_frm(vf); 745 } 746 747 #ifdef CONFIG_DCB 748 /* Disable PFC config */ 749 if (vf->pfc_en) { 750 vf->pfc_en = 0; 751 otx2_config_priority_flow_ctrl(vf); 752 } 753 #endif 754 755 cancel_work_sync(&vf->reset_task); 756 otx2_unregister_dl(vf); 757 unregister_netdev(netdev); 758 if (vf->otx2_wq) 759 destroy_workqueue(vf->otx2_wq); 760 otx2_ptp_destroy(vf); 761 otx2_mcam_flow_del(vf); 762 otx2_shutdown_tc(vf); 763 otx2_shutdown_qos(vf); 764 otx2vf_disable_mbox_intr(vf); 765 otx2_detach_resources(&vf->mbox); 766 free_percpu(vf->hw.lmt_info); 767 if (test_bit(CN10K_LMTST, &vf->hw.cap_flag)) 768 qmem_free(vf->dev, vf->dync_lmt); 769 otx2vf_vfaf_mbox_destroy(vf); 770 pci_free_irq_vectors(vf->pdev); 771 pci_set_drvdata(pdev, NULL); 772 free_netdev(netdev); 773 774 pci_release_regions(pdev); 775 } 776 777 static struct pci_driver otx2vf_driver = { 778 .name = DRV_NAME, 779 .id_table = otx2_vf_id_table, 780 .probe = otx2vf_probe, 781 .remove = otx2vf_remove, 782 .shutdown = otx2vf_remove, 783 }; 784 785 static int __init otx2vf_init_module(void) 786 { 787 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 788 789 return pci_register_driver(&otx2vf_driver); 790 } 791 792 static void __exit otx2vf_cleanup_module(void) 793 { 794 pci_unregister_driver(&otx2vf_driver); 795 } 796 797 module_init(otx2vf_init_module); 798 module_exit(otx2vf_cleanup_module); 799