1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_TXRX_H 9 #define OTX2_TXRX_H 10 11 #include <linux/etherdevice.h> 12 #include <linux/iommu.h> 13 #include <linux/if_vlan.h> 14 15 #define LBK_CHAN_BASE 0x000 16 #define SDP_CHAN_BASE 0x700 17 #define CGX_CHAN_BASE 0x800 18 19 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN) 20 #define OTX2_HEAD_ROOM OTX2_ALIGN 21 22 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN) 23 #define OTX2_MIN_MTU 64 24 25 #define OTX2_MAX_GSO_SEGS 255 26 #define OTX2_MAX_FRAGS_IN_SQE 9 27 28 /* Rx buffer size should be in multiples of 128bytes */ 29 #define RCV_FRAG_LEN1(x) \ 30 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \ 31 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 32 33 /* Prefer 2048 byte buffers for better last level cache 34 * utilization or data distribution across regions. 35 */ 36 #define RCV_FRAG_LEN(x) \ 37 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x)) 38 39 #define DMA_BUFFER_LEN(x) \ 40 ((x) - OTX2_HEAD_ROOM - \ 41 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 42 43 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 44 * is equal to this value. 45 */ 46 #define CQ_CQE_THRESH_DEFAULT 10 47 48 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 49 * is nonzero and this much time elapses after that. 50 */ 51 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */ 52 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */ 53 54 /* Min number of CQs (of the ones mapped to this CINT) 55 * with valid CQEs. 56 */ 57 #define CQ_QCOUNT_DEFAULT 1 58 59 struct queue_stats { 60 u64 bytes; 61 u64 pkts; 62 }; 63 64 struct otx2_rcv_queue { 65 struct queue_stats stats; 66 }; 67 68 struct sg_list { 69 u16 num_segs; 70 u64 skb; 71 u64 size[OTX2_MAX_FRAGS_IN_SQE]; 72 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; 73 }; 74 75 struct otx2_snd_queue { 76 u8 aura_id; 77 u16 head; 78 u16 sqe_size; 79 u32 sqe_cnt; 80 u16 num_sqbs; 81 u16 sqe_thresh; 82 u8 sqe_per_sqb; 83 u64 io_addr; 84 u64 *aura_fc_addr; 85 u64 *lmt_addr; 86 void *sqe_base; 87 struct qmem *sqe; 88 struct qmem *tso_hdrs; 89 struct sg_list *sg; 90 struct qmem *timestamps; 91 struct queue_stats stats; 92 u16 sqb_count; 93 u64 *sqb_ptrs; 94 } ____cacheline_aligned_in_smp; 95 96 enum cq_type { 97 CQ_RX, 98 CQ_TX, 99 CQS_PER_CINT = 2, /* RQ + SQ */ 100 }; 101 102 struct otx2_cq_poll { 103 void *dev; 104 #define CINT_INVALID_CQ 255 105 u8 cint_idx; 106 u8 cq_ids[CQS_PER_CINT]; 107 struct napi_struct napi; 108 }; 109 110 struct otx2_pool { 111 struct qmem *stack; 112 struct qmem *fc_addr; 113 u16 rbsize; 114 }; 115 116 struct otx2_cq_queue { 117 u8 cq_idx; 118 u8 cq_type; 119 u8 cint_idx; /* CQ interrupt id */ 120 u8 refill_task_sched; 121 u16 cqe_size; 122 u16 pool_ptrs; 123 u32 cqe_cnt; 124 u32 cq_head; 125 void *cqe_base; 126 struct qmem *cqe; 127 struct otx2_pool *rbpool; 128 } ____cacheline_aligned_in_smp; 129 130 struct otx2_qset { 131 u32 rqe_cnt; 132 u32 sqe_cnt; /* Keep these two at top */ 133 #define OTX2_MAX_CQ_CNT 64 134 u16 cq_cnt; 135 u16 xqe_size; 136 struct otx2_pool *pool; 137 struct otx2_cq_poll *napi; 138 struct otx2_cq_queue *cq; 139 struct otx2_snd_queue *sq; 140 struct otx2_rcv_queue *rq; 141 }; 142 143 /* Translate IOVA to physical address */ 144 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr) 145 { 146 /* Translation is installed only when IOMMU is present */ 147 if (likely(iommu_domain)) 148 return iommu_iova_to_phys(iommu_domain, dma_addr); 149 return dma_addr; 150 } 151 152 int otx2_napi_handler(struct napi_struct *napi, int budget); 153 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 154 struct sk_buff *skb, u16 qidx); 155 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, 156 int size, int qidx); 157 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 158 int size, int qidx); 159 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); 160 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); 161 #endif /* OTX2_TXRX_H */ 162