1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_TXRX_H 12 #define OTX2_TXRX_H 13 14 #include <linux/etherdevice.h> 15 #include <linux/iommu.h> 16 #include <linux/if_vlan.h> 17 18 #define LBK_CHAN_BASE 0x000 19 #define SDP_CHAN_BASE 0x700 20 #define CGX_CHAN_BASE 0x800 21 22 #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN) 23 #define OTX2_HEAD_ROOM OTX2_ALIGN 24 25 #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN) 26 #define OTX2_MIN_MTU 64 27 #define OTX2_MAX_MTU (9212 - OTX2_ETH_HLEN) 28 29 #define OTX2_MAX_GSO_SEGS 255 30 #define OTX2_MAX_FRAGS_IN_SQE 9 31 32 /* Rx buffer size should be in multiples of 128bytes */ 33 #define RCV_FRAG_LEN1(x) \ 34 ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \ 35 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 36 37 /* Prefer 2048 byte buffers for better last level cache 38 * utilization or data distribution across regions. 39 */ 40 #define RCV_FRAG_LEN(x) \ 41 ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x)) 42 43 #define DMA_BUFFER_LEN(x) \ 44 ((x) - OTX2_HEAD_ROOM - \ 45 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 46 47 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 48 * is equal to this value. 49 */ 50 #define CQ_CQE_THRESH_DEFAULT 10 51 52 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 53 * is nonzero and this much time elapses after that. 54 */ 55 #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */ 56 #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */ 57 58 /* Min number of CQs (of the ones mapped to this CINT) 59 * with valid CQEs. 60 */ 61 #define CQ_QCOUNT_DEFAULT 1 62 63 struct queue_stats { 64 u64 bytes; 65 u64 pkts; 66 }; 67 68 struct otx2_rcv_queue { 69 struct queue_stats stats; 70 }; 71 72 struct sg_list { 73 u16 num_segs; 74 u64 skb; 75 u64 size[OTX2_MAX_FRAGS_IN_SQE]; 76 u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; 77 }; 78 79 struct otx2_snd_queue { 80 u8 aura_id; 81 u16 head; 82 u16 sqe_size; 83 u32 sqe_cnt; 84 u16 num_sqbs; 85 u16 sqe_thresh; 86 u8 sqe_per_sqb; 87 u64 io_addr; 88 u64 *aura_fc_addr; 89 u64 *lmt_addr; 90 void *sqe_base; 91 struct qmem *sqe; 92 struct qmem *tso_hdrs; 93 struct sg_list *sg; 94 struct queue_stats stats; 95 u16 sqb_count; 96 u64 *sqb_ptrs; 97 } ____cacheline_aligned_in_smp; 98 99 enum cq_type { 100 CQ_RX, 101 CQ_TX, 102 CQS_PER_CINT = 2, /* RQ + SQ */ 103 }; 104 105 struct otx2_cq_poll { 106 void *dev; 107 #define CINT_INVALID_CQ 255 108 u8 cint_idx; 109 u8 cq_ids[CQS_PER_CINT]; 110 struct napi_struct napi; 111 }; 112 113 struct otx2_pool { 114 struct qmem *stack; 115 struct qmem *fc_addr; 116 u8 rbpage_order; 117 u16 rbsize; 118 u32 page_offset; 119 u16 pageref; 120 struct page *page; 121 }; 122 123 struct otx2_cq_queue { 124 u8 cq_idx; 125 u8 cq_type; 126 u8 cint_idx; /* CQ interrupt id */ 127 u8 refill_task_sched; 128 u16 cqe_size; 129 u16 pool_ptrs; 130 u32 cqe_cnt; 131 u32 cq_head; 132 void *cqe_base; 133 struct qmem *cqe; 134 struct otx2_pool *rbpool; 135 } ____cacheline_aligned_in_smp; 136 137 struct otx2_qset { 138 u32 rqe_cnt; 139 u32 sqe_cnt; /* Keep these two at top */ 140 #define OTX2_MAX_CQ_CNT 64 141 u16 cq_cnt; 142 u16 xqe_size; 143 struct otx2_pool *pool; 144 struct otx2_cq_poll *napi; 145 struct otx2_cq_queue *cq; 146 struct otx2_snd_queue *sq; 147 struct otx2_rcv_queue *rq; 148 }; 149 150 /* Translate IOVA to physical address */ 151 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr) 152 { 153 /* Translation is installed only when IOMMU is present */ 154 if (likely(iommu_domain)) 155 return iommu_iova_to_phys(iommu_domain, dma_addr); 156 return dma_addr; 157 } 158 159 int otx2_napi_handler(struct napi_struct *napi, int budget); 160 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 161 struct sk_buff *skb, u16 qidx); 162 #endif /* OTX2_TXRX_H */ 163