1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #ifndef OTX2_TXRX_H
9 #define OTX2_TXRX_H
10 
11 #include <linux/etherdevice.h>
12 #include <linux/iommu.h>
13 #include <linux/if_vlan.h>
14 #include <net/xdp.h>
15 
16 #define LBK_CHAN_BASE	0x000
17 #define SDP_CHAN_BASE	0x700
18 #define CGX_CHAN_BASE	0x800
19 
20 #define OTX2_DATA_ALIGN(X)	ALIGN(X, OTX2_ALIGN)
21 #define OTX2_HEAD_ROOM		OTX2_ALIGN
22 
23 #define	OTX2_ETH_HLEN		(VLAN_ETH_HLEN + VLAN_HLEN)
24 #define	OTX2_MIN_MTU		64
25 
26 #define OTX2_MAX_GSO_SEGS	255
27 #define OTX2_MAX_FRAGS_IN_SQE	9
28 
29 #define MAX_XDP_MTU	(1530 - OTX2_ETH_HLEN)
30 
31 /* Rx buffer size should be in multiples of 128bytes */
32 #define RCV_FRAG_LEN1(x)				\
33 		((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
34 		OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
35 
36 /* Prefer 2048 byte buffers for better last level cache
37  * utilization or data distribution across regions.
38  */
39 #define RCV_FRAG_LEN(x)	\
40 		((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
41 
42 #define DMA_BUFFER_LEN(x)	((x) - OTX2_HEAD_ROOM)
43 
44 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
45  * is equal to this value.
46  */
47 #define CQ_CQE_THRESH_DEFAULT	10
48 
49 /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
50  * is nonzero and this much time elapses after that.
51  */
52 #define CQ_TIMER_THRESH_DEFAULT	1  /* 1 usec */
53 #define CQ_TIMER_THRESH_MAX     25 /* 25 usec */
54 
55 /* Min number of CQs (of the ones mapped to this CINT)
56  * with valid CQEs.
57  */
58 #define CQ_QCOUNT_DEFAULT	1
59 
60 #define CQ_OP_STAT_OP_ERR       63
61 #define CQ_OP_STAT_CQ_ERR       46
62 
63 struct queue_stats {
64 	u64	bytes;
65 	u64	pkts;
66 };
67 
68 struct otx2_rcv_queue {
69 	struct queue_stats	stats;
70 };
71 
72 struct sg_list {
73 	u16	num_segs;
74 	u64	skb;
75 	u64	size[OTX2_MAX_FRAGS_IN_SQE];
76 	u64	dma_addr[OTX2_MAX_FRAGS_IN_SQE];
77 };
78 
79 struct otx2_snd_queue {
80 	u8			aura_id;
81 	u16			head;
82 	u16			sqe_size;
83 	u32			sqe_cnt;
84 	u16			num_sqbs;
85 	u16			sqe_thresh;
86 	u8			sqe_per_sqb;
87 	u64			 io_addr;
88 	u64			*aura_fc_addr;
89 	u64			*lmt_addr;
90 	void			*sqe_base;
91 	struct qmem		*sqe;
92 	struct qmem		*tso_hdrs;
93 	struct sg_list		*sg;
94 	struct qmem		*timestamps;
95 	struct queue_stats	stats;
96 	u16			sqb_count;
97 	u64			*sqb_ptrs;
98 } ____cacheline_aligned_in_smp;
99 
100 enum cq_type {
101 	CQ_RX,
102 	CQ_TX,
103 	CQ_XDP,
104 	CQS_PER_CINT = 3, /* RQ + SQ + XDP */
105 };
106 
107 struct otx2_cq_poll {
108 	void			*dev;
109 #define CINT_INVALID_CQ		255
110 	u8			cint_idx;
111 	u8			cq_ids[CQS_PER_CINT];
112 	struct napi_struct	napi;
113 };
114 
115 struct otx2_pool {
116 	struct qmem		*stack;
117 	struct qmem		*fc_addr;
118 	u16			rbsize;
119 };
120 
121 struct otx2_cq_queue {
122 	u8			cq_idx;
123 	u8			cq_type;
124 	u8			cint_idx; /* CQ interrupt id */
125 	u8			refill_task_sched;
126 	u16			cqe_size;
127 	u16			pool_ptrs;
128 	u32			cqe_cnt;
129 	u32			cq_head;
130 	u32			cq_tail;
131 	u32			pend_cqe;
132 	void			*cqe_base;
133 	struct qmem		*cqe;
134 	struct otx2_pool	*rbpool;
135 	struct xdp_rxq_info xdp_rxq;
136 } ____cacheline_aligned_in_smp;
137 
138 struct otx2_qset {
139 	u32			rqe_cnt;
140 	u32			sqe_cnt; /* Keep these two at top */
141 #define OTX2_MAX_CQ_CNT		64
142 	u16			cq_cnt;
143 	u16			xqe_size;
144 	struct otx2_pool	*pool;
145 	struct otx2_cq_poll	*napi;
146 	struct otx2_cq_queue	*cq;
147 	struct otx2_snd_queue	*sq;
148 	struct otx2_rcv_queue	*rq;
149 };
150 
151 /* Translate IOVA to physical address */
152 static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
153 {
154 	/* Translation is installed only when IOMMU is present */
155 	if (likely(iommu_domain))
156 		return iommu_iova_to_phys(iommu_domain, dma_addr);
157 	return dma_addr;
158 }
159 
160 int otx2_napi_handler(struct napi_struct *napi, int budget);
161 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
162 			struct sk_buff *skb, u16 qidx);
163 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
164 		     int size, int qidx);
165 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
166 		    int size, int qidx);
167 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
168 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
169 #endif /* OTX2_TXRX_H */
170