1caa2da34SSunil Goutham /* SPDX-License-Identifier: GPL-2.0 */ 2caa2da34SSunil Goutham /* Marvell OcteonTx2 RVU Ethernet driver 3caa2da34SSunil Goutham * 4caa2da34SSunil Goutham * Copyright (C) 2020 Marvell International Ltd. 5caa2da34SSunil Goutham * 6caa2da34SSunil Goutham * This program is free software; you can redistribute it and/or modify 7caa2da34SSunil Goutham * it under the terms of the GNU General Public License version 2 as 8caa2da34SSunil Goutham * published by the Free Software Foundation. 9caa2da34SSunil Goutham */ 10caa2da34SSunil Goutham 11caa2da34SSunil Goutham #ifndef OTX2_TXRX_H 12caa2da34SSunil Goutham #define OTX2_TXRX_H 13caa2da34SSunil Goutham 14caa2da34SSunil Goutham #include <linux/etherdevice.h> 15caa2da34SSunil Goutham #include <linux/iommu.h> 16caa2da34SSunil Goutham #include <linux/if_vlan.h> 17caa2da34SSunil Goutham 18caa2da34SSunil Goutham #define LBK_CHAN_BASE 0x000 19caa2da34SSunil Goutham #define SDP_CHAN_BASE 0x700 20caa2da34SSunil Goutham #define CGX_CHAN_BASE 0x800 21caa2da34SSunil Goutham 22caa2da34SSunil Goutham #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN) 23caa2da34SSunil Goutham #define OTX2_HEAD_ROOM OTX2_ALIGN 24caa2da34SSunil Goutham 2534bfe0ebSSunil Goutham #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN) 2634bfe0ebSSunil Goutham #define OTX2_MIN_MTU 64 2734bfe0ebSSunil Goutham #define OTX2_MAX_MTU (9212 - OTX2_ETH_HLEN) 2834bfe0ebSSunil Goutham 2986d74760SSunil Goutham #define OTX2_MAX_GSO_SEGS 255 303ca6c4c8SSunil Goutham #define OTX2_MAX_FRAGS_IN_SQE 9 313ca6c4c8SSunil Goutham 32caa2da34SSunil Goutham /* Rx buffer size should be in multiples of 128bytes */ 33caa2da34SSunil Goutham #define RCV_FRAG_LEN1(x) \ 34caa2da34SSunil Goutham ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \ 35caa2da34SSunil Goutham OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 36caa2da34SSunil Goutham 37caa2da34SSunil Goutham /* Prefer 2048 byte buffers for better last level cache 38caa2da34SSunil Goutham * utilization or data distribution across regions. 39caa2da34SSunil Goutham */ 40caa2da34SSunil Goutham #define RCV_FRAG_LEN(x) \ 41caa2da34SSunil Goutham ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x)) 42caa2da34SSunil Goutham 43caa2da34SSunil Goutham #define DMA_BUFFER_LEN(x) \ 44caa2da34SSunil Goutham ((x) - OTX2_HEAD_ROOM - \ 45caa2da34SSunil Goutham OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 46caa2da34SSunil Goutham 4704a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 4804a21ef3SSunil Goutham * is equal to this value. 4904a21ef3SSunil Goutham */ 5004a21ef3SSunil Goutham #define CQ_CQE_THRESH_DEFAULT 10 5104a21ef3SSunil Goutham 5204a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 5304a21ef3SSunil Goutham * is nonzero and this much time elapses after that. 5404a21ef3SSunil Goutham */ 5504a21ef3SSunil Goutham #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */ 5604a21ef3SSunil Goutham #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */ 5704a21ef3SSunil Goutham 5804a21ef3SSunil Goutham /* Min number of CQs (of the ones mapped to this CINT) 5904a21ef3SSunil Goutham * with valid CQEs. 6004a21ef3SSunil Goutham */ 6104a21ef3SSunil Goutham #define CQ_QCOUNT_DEFAULT 1 6204a21ef3SSunil Goutham 63d45d8979SChristina Jacob struct queue_stats { 64d45d8979SChristina Jacob u64 bytes; 65d45d8979SChristina Jacob u64 pkts; 66d45d8979SChristina Jacob }; 67d45d8979SChristina Jacob 68d45d8979SChristina Jacob struct otx2_rcv_queue { 69d45d8979SChristina Jacob struct queue_stats stats; 70d45d8979SChristina Jacob }; 71d45d8979SChristina Jacob 723ca6c4c8SSunil Goutham struct sg_list { 733ca6c4c8SSunil Goutham u16 num_segs; 743ca6c4c8SSunil Goutham u64 skb; 753ca6c4c8SSunil Goutham u64 size[OTX2_MAX_FRAGS_IN_SQE]; 763ca6c4c8SSunil Goutham u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; 773ca6c4c8SSunil Goutham }; 783ca6c4c8SSunil Goutham 79caa2da34SSunil Goutham struct otx2_snd_queue { 80caa2da34SSunil Goutham u8 aura_id; 813ca6c4c8SSunil Goutham u16 head; 82caa2da34SSunil Goutham u16 sqe_size; 83caa2da34SSunil Goutham u32 sqe_cnt; 84caa2da34SSunil Goutham u16 num_sqbs; 853ca6c4c8SSunil Goutham u16 sqe_thresh; 86caa2da34SSunil Goutham u8 sqe_per_sqb; 87caa2da34SSunil Goutham u64 io_addr; 88caa2da34SSunil Goutham u64 *aura_fc_addr; 89caa2da34SSunil Goutham u64 *lmt_addr; 90caa2da34SSunil Goutham void *sqe_base; 91caa2da34SSunil Goutham struct qmem *sqe; 9286d74760SSunil Goutham struct qmem *tso_hdrs; 933ca6c4c8SSunil Goutham struct sg_list *sg; 94c9c12d33SAleksey Makarov struct qmem *timestamps; 95d45d8979SChristina Jacob struct queue_stats stats; 96caa2da34SSunil Goutham u16 sqb_count; 97caa2da34SSunil Goutham u64 *sqb_ptrs; 98caa2da34SSunil Goutham } ____cacheline_aligned_in_smp; 99caa2da34SSunil Goutham 10004a21ef3SSunil Goutham enum cq_type { 10104a21ef3SSunil Goutham CQ_RX, 10204a21ef3SSunil Goutham CQ_TX, 10304a21ef3SSunil Goutham CQS_PER_CINT = 2, /* RQ + SQ */ 10404a21ef3SSunil Goutham }; 10504a21ef3SSunil Goutham 10604a21ef3SSunil Goutham struct otx2_cq_poll { 10704a21ef3SSunil Goutham void *dev; 10804a21ef3SSunil Goutham #define CINT_INVALID_CQ 255 10904a21ef3SSunil Goutham u8 cint_idx; 11004a21ef3SSunil Goutham u8 cq_ids[CQS_PER_CINT]; 11104a21ef3SSunil Goutham struct napi_struct napi; 11204a21ef3SSunil Goutham }; 11304a21ef3SSunil Goutham 114caa2da34SSunil Goutham struct otx2_pool { 115caa2da34SSunil Goutham struct qmem *stack; 116caa2da34SSunil Goutham struct qmem *fc_addr; 117caa2da34SSunil Goutham u16 rbsize; 118caa2da34SSunil Goutham }; 119caa2da34SSunil Goutham 120caa2da34SSunil Goutham struct otx2_cq_queue { 121caa2da34SSunil Goutham u8 cq_idx; 122caa2da34SSunil Goutham u8 cq_type; 123abe02543SSunil Goutham u8 cint_idx; /* CQ interrupt id */ 1244ff7d148SGeetha sowjanya u8 refill_task_sched; 125caa2da34SSunil Goutham u16 cqe_size; 126caa2da34SSunil Goutham u16 pool_ptrs; 127caa2da34SSunil Goutham u32 cqe_cnt; 128abe02543SSunil Goutham u32 cq_head; 129caa2da34SSunil Goutham void *cqe_base; 130caa2da34SSunil Goutham struct qmem *cqe; 131caa2da34SSunil Goutham struct otx2_pool *rbpool; 132caa2da34SSunil Goutham } ____cacheline_aligned_in_smp; 133caa2da34SSunil Goutham 134caa2da34SSunil Goutham struct otx2_qset { 135caa2da34SSunil Goutham u32 rqe_cnt; 136caa2da34SSunil Goutham u32 sqe_cnt; /* Keep these two at top */ 137caa2da34SSunil Goutham #define OTX2_MAX_CQ_CNT 64 138caa2da34SSunil Goutham u16 cq_cnt; 139caa2da34SSunil Goutham u16 xqe_size; 140caa2da34SSunil Goutham struct otx2_pool *pool; 14104a21ef3SSunil Goutham struct otx2_cq_poll *napi; 142caa2da34SSunil Goutham struct otx2_cq_queue *cq; 143caa2da34SSunil Goutham struct otx2_snd_queue *sq; 144d45d8979SChristina Jacob struct otx2_rcv_queue *rq; 145caa2da34SSunil Goutham }; 146caa2da34SSunil Goutham 147caa2da34SSunil Goutham /* Translate IOVA to physical address */ 148caa2da34SSunil Goutham static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr) 149caa2da34SSunil Goutham { 150caa2da34SSunil Goutham /* Translation is installed only when IOMMU is present */ 151caa2da34SSunil Goutham if (likely(iommu_domain)) 152caa2da34SSunil Goutham return iommu_iova_to_phys(iommu_domain, dma_addr); 153caa2da34SSunil Goutham return dma_addr; 154caa2da34SSunil Goutham } 155caa2da34SSunil Goutham 15604a21ef3SSunil Goutham int otx2_napi_handler(struct napi_struct *napi, int budget); 1573ca6c4c8SSunil Goutham bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 1583ca6c4c8SSunil Goutham struct sk_buff *skb, u16 qidx); 159caa2da34SSunil Goutham #endif /* OTX2_TXRX_H */ 160