1caa2da34SSunil Goutham /* SPDX-License-Identifier: GPL-2.0 */ 2cb0e3ec4SSunil Goutham /* Marvell RVU Ethernet driver 3caa2da34SSunil Goutham * 4cb0e3ec4SSunil Goutham * Copyright (C) 2020 Marvell. 5caa2da34SSunil Goutham * 6caa2da34SSunil Goutham */ 7caa2da34SSunil Goutham 8caa2da34SSunil Goutham #ifndef OTX2_TXRX_H 9caa2da34SSunil Goutham #define OTX2_TXRX_H 10caa2da34SSunil Goutham 11caa2da34SSunil Goutham #include <linux/etherdevice.h> 12caa2da34SSunil Goutham #include <linux/iommu.h> 13caa2da34SSunil Goutham #include <linux/if_vlan.h> 1406059a1aSGeetha sowjanya #include <net/xdp.h> 15caa2da34SSunil Goutham 16caa2da34SSunil Goutham #define LBK_CHAN_BASE 0x000 17caa2da34SSunil Goutham #define SDP_CHAN_BASE 0x700 18caa2da34SSunil Goutham #define CGX_CHAN_BASE 0x800 19caa2da34SSunil Goutham 20caa2da34SSunil Goutham #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN) 21caa2da34SSunil Goutham #define OTX2_HEAD_ROOM OTX2_ALIGN 22caa2da34SSunil Goutham 2334bfe0ebSSunil Goutham #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN) 2434bfe0ebSSunil Goutham #define OTX2_MIN_MTU 64 2534bfe0ebSSunil Goutham 2686d74760SSunil Goutham #define OTX2_MAX_GSO_SEGS 255 273ca6c4c8SSunil Goutham #define OTX2_MAX_FRAGS_IN_SQE 9 283ca6c4c8SSunil Goutham 2906059a1aSGeetha sowjanya #define MAX_XDP_MTU (1530 - OTX2_ETH_HLEN) 3006059a1aSGeetha sowjanya 31caa2da34SSunil Goutham /* Rx buffer size should be in multiples of 128bytes */ 32caa2da34SSunil Goutham #define RCV_FRAG_LEN1(x) \ 33caa2da34SSunil Goutham ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \ 34caa2da34SSunil Goutham OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) 35caa2da34SSunil Goutham 36caa2da34SSunil Goutham /* Prefer 2048 byte buffers for better last level cache 37caa2da34SSunil Goutham * utilization or data distribution across regions. 38caa2da34SSunil Goutham */ 39caa2da34SSunil Goutham #define RCV_FRAG_LEN(x) \ 40caa2da34SSunil Goutham ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x)) 41caa2da34SSunil Goutham 42*0182d078SSubbaraya Sundeep #define DMA_BUFFER_LEN(x) ((x) - OTX2_HEAD_ROOM) 43caa2da34SSunil Goutham 4404a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 4504a21ef3SSunil Goutham * is equal to this value. 4604a21ef3SSunil Goutham */ 4704a21ef3SSunil Goutham #define CQ_CQE_THRESH_DEFAULT 10 4804a21ef3SSunil Goutham 4904a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT] 5004a21ef3SSunil Goutham * is nonzero and this much time elapses after that. 5104a21ef3SSunil Goutham */ 5204a21ef3SSunil Goutham #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */ 5304a21ef3SSunil Goutham #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */ 5404a21ef3SSunil Goutham 5504a21ef3SSunil Goutham /* Min number of CQs (of the ones mapped to this CINT) 5604a21ef3SSunil Goutham * with valid CQEs. 5704a21ef3SSunil Goutham */ 5804a21ef3SSunil Goutham #define CQ_QCOUNT_DEFAULT 1 5904a21ef3SSunil Goutham 60af3826dbSGeetha sowjanya #define CQ_OP_STAT_OP_ERR 63 61af3826dbSGeetha sowjanya #define CQ_OP_STAT_CQ_ERR 46 62af3826dbSGeetha sowjanya 63d45d8979SChristina Jacob struct queue_stats { 64d45d8979SChristina Jacob u64 bytes; 65d45d8979SChristina Jacob u64 pkts; 66d45d8979SChristina Jacob }; 67d45d8979SChristina Jacob 68d45d8979SChristina Jacob struct otx2_rcv_queue { 69d45d8979SChristina Jacob struct queue_stats stats; 70d45d8979SChristina Jacob }; 71d45d8979SChristina Jacob 723ca6c4c8SSunil Goutham struct sg_list { 733ca6c4c8SSunil Goutham u16 num_segs; 743ca6c4c8SSunil Goutham u64 skb; 753ca6c4c8SSunil Goutham u64 size[OTX2_MAX_FRAGS_IN_SQE]; 763ca6c4c8SSunil Goutham u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; 773ca6c4c8SSunil Goutham }; 783ca6c4c8SSunil Goutham 79caa2da34SSunil Goutham struct otx2_snd_queue { 80caa2da34SSunil Goutham u8 aura_id; 813ca6c4c8SSunil Goutham u16 head; 82caa2da34SSunil Goutham u16 sqe_size; 83caa2da34SSunil Goutham u32 sqe_cnt; 84caa2da34SSunil Goutham u16 num_sqbs; 853ca6c4c8SSunil Goutham u16 sqe_thresh; 86caa2da34SSunil Goutham u8 sqe_per_sqb; 87caa2da34SSunil Goutham u64 io_addr; 88caa2da34SSunil Goutham u64 *aura_fc_addr; 89caa2da34SSunil Goutham u64 *lmt_addr; 90caa2da34SSunil Goutham void *sqe_base; 91caa2da34SSunil Goutham struct qmem *sqe; 9286d74760SSunil Goutham struct qmem *tso_hdrs; 933ca6c4c8SSunil Goutham struct sg_list *sg; 94c9c12d33SAleksey Makarov struct qmem *timestamps; 95d45d8979SChristina Jacob struct queue_stats stats; 96caa2da34SSunil Goutham u16 sqb_count; 97caa2da34SSunil Goutham u64 *sqb_ptrs; 98caa2da34SSunil Goutham } ____cacheline_aligned_in_smp; 99caa2da34SSunil Goutham 10004a21ef3SSunil Goutham enum cq_type { 10104a21ef3SSunil Goutham CQ_RX, 10204a21ef3SSunil Goutham CQ_TX, 10306059a1aSGeetha sowjanya CQ_XDP, 10406059a1aSGeetha sowjanya CQS_PER_CINT = 3, /* RQ + SQ + XDP */ 10504a21ef3SSunil Goutham }; 10604a21ef3SSunil Goutham 10704a21ef3SSunil Goutham struct otx2_cq_poll { 10804a21ef3SSunil Goutham void *dev; 10904a21ef3SSunil Goutham #define CINT_INVALID_CQ 255 11004a21ef3SSunil Goutham u8 cint_idx; 11104a21ef3SSunil Goutham u8 cq_ids[CQS_PER_CINT]; 11204a21ef3SSunil Goutham struct napi_struct napi; 11304a21ef3SSunil Goutham }; 11404a21ef3SSunil Goutham 115caa2da34SSunil Goutham struct otx2_pool { 116caa2da34SSunil Goutham struct qmem *stack; 117caa2da34SSunil Goutham struct qmem *fc_addr; 118caa2da34SSunil Goutham u16 rbsize; 119caa2da34SSunil Goutham }; 120caa2da34SSunil Goutham 121caa2da34SSunil Goutham struct otx2_cq_queue { 122caa2da34SSunil Goutham u8 cq_idx; 123caa2da34SSunil Goutham u8 cq_type; 124abe02543SSunil Goutham u8 cint_idx; /* CQ interrupt id */ 1254ff7d148SGeetha sowjanya u8 refill_task_sched; 126caa2da34SSunil Goutham u16 cqe_size; 127caa2da34SSunil Goutham u16 pool_ptrs; 128caa2da34SSunil Goutham u32 cqe_cnt; 129abe02543SSunil Goutham u32 cq_head; 130af3826dbSGeetha sowjanya u32 cq_tail; 131af3826dbSGeetha sowjanya u32 pend_cqe; 132caa2da34SSunil Goutham void *cqe_base; 133caa2da34SSunil Goutham struct qmem *cqe; 134caa2da34SSunil Goutham struct otx2_pool *rbpool; 13506059a1aSGeetha sowjanya struct xdp_rxq_info xdp_rxq; 136caa2da34SSunil Goutham } ____cacheline_aligned_in_smp; 137caa2da34SSunil Goutham 138caa2da34SSunil Goutham struct otx2_qset { 139caa2da34SSunil Goutham u32 rqe_cnt; 140caa2da34SSunil Goutham u32 sqe_cnt; /* Keep these two at top */ 141caa2da34SSunil Goutham #define OTX2_MAX_CQ_CNT 64 142caa2da34SSunil Goutham u16 cq_cnt; 143caa2da34SSunil Goutham u16 xqe_size; 144caa2da34SSunil Goutham struct otx2_pool *pool; 14504a21ef3SSunil Goutham struct otx2_cq_poll *napi; 146caa2da34SSunil Goutham struct otx2_cq_queue *cq; 147caa2da34SSunil Goutham struct otx2_snd_queue *sq; 148d45d8979SChristina Jacob struct otx2_rcv_queue *rq; 149caa2da34SSunil Goutham }; 150caa2da34SSunil Goutham 151caa2da34SSunil Goutham /* Translate IOVA to physical address */ 152caa2da34SSunil Goutham static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr) 153caa2da34SSunil Goutham { 154caa2da34SSunil Goutham /* Translation is installed only when IOMMU is present */ 155caa2da34SSunil Goutham if (likely(iommu_domain)) 156caa2da34SSunil Goutham return iommu_iova_to_phys(iommu_domain, dma_addr); 157caa2da34SSunil Goutham return dma_addr; 158caa2da34SSunil Goutham } 159caa2da34SSunil Goutham 16004a21ef3SSunil Goutham int otx2_napi_handler(struct napi_struct *napi, int budget); 1613ca6c4c8SSunil Goutham bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 1623ca6c4c8SSunil Goutham struct sk_buff *skb, u16 qidx); 1634c236d5dSGeetha sowjanya void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, 1644c236d5dSGeetha sowjanya int size, int qidx); 1654c236d5dSGeetha sowjanya void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 1664c236d5dSGeetha sowjanya int size, int qidx); 1674c236d5dSGeetha sowjanya void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); 1684c236d5dSGeetha sowjanya void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); 169caa2da34SSunil Goutham #endif /* OTX2_TXRX_H */ 170