1caa2da34SSunil Goutham /* SPDX-License-Identifier: GPL-2.0 */
2cb0e3ec4SSunil Goutham /* Marvell RVU Ethernet driver
3caa2da34SSunil Goutham *
4cb0e3ec4SSunil Goutham * Copyright (C) 2020 Marvell.
5caa2da34SSunil Goutham *
6caa2da34SSunil Goutham */
7caa2da34SSunil Goutham
8caa2da34SSunil Goutham #ifndef OTX2_TXRX_H
9caa2da34SSunil Goutham #define OTX2_TXRX_H
10caa2da34SSunil Goutham
11caa2da34SSunil Goutham #include <linux/etherdevice.h>
12caa2da34SSunil Goutham #include <linux/iommu.h>
13caa2da34SSunil Goutham #include <linux/if_vlan.h>
1406059a1aSGeetha sowjanya #include <net/xdp.h>
15caa2da34SSunil Goutham
16caa2da34SSunil Goutham #define LBK_CHAN_BASE 0x000
17caa2da34SSunil Goutham #define SDP_CHAN_BASE 0x700
18caa2da34SSunil Goutham #define CGX_CHAN_BASE 0x800
19caa2da34SSunil Goutham
20caa2da34SSunil Goutham #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
21caa2da34SSunil Goutham #define OTX2_HEAD_ROOM OTX2_ALIGN
22caa2da34SSunil Goutham
2334bfe0ebSSunil Goutham #define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
2453e99496SSubbaraya Sundeep #define OTX2_MIN_MTU 60
2534bfe0ebSSunil Goutham
2649fa4b0dSRatheesh Kannoth #define OTX2_PAGE_POOL_SZ 2048
2749fa4b0dSRatheesh Kannoth
2886d74760SSunil Goutham #define OTX2_MAX_GSO_SEGS 255
293ca6c4c8SSunil Goutham #define OTX2_MAX_FRAGS_IN_SQE 9
303ca6c4c8SSunil Goutham
3106059a1aSGeetha sowjanya #define MAX_XDP_MTU (1530 - OTX2_ETH_HLEN)
3206059a1aSGeetha sowjanya
33caa2da34SSunil Goutham /* Rx buffer size should be in multiples of 128bytes */
34caa2da34SSunil Goutham #define RCV_FRAG_LEN1(x) \
35caa2da34SSunil Goutham ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
36caa2da34SSunil Goutham OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
37caa2da34SSunil Goutham
38caa2da34SSunil Goutham /* Prefer 2048 byte buffers for better last level cache
39caa2da34SSunil Goutham * utilization or data distribution across regions.
40caa2da34SSunil Goutham */
41caa2da34SSunil Goutham #define RCV_FRAG_LEN(x) \
42caa2da34SSunil Goutham ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
43caa2da34SSunil Goutham
440182d078SSubbaraya Sundeep #define DMA_BUFFER_LEN(x) ((x) - OTX2_HEAD_ROOM)
45caa2da34SSunil Goutham
4604a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
4704a21ef3SSunil Goutham * is equal to this value.
4804a21ef3SSunil Goutham */
4904a21ef3SSunil Goutham #define CQ_CQE_THRESH_DEFAULT 10
5004a21ef3SSunil Goutham
5104a21ef3SSunil Goutham /* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
5204a21ef3SSunil Goutham * is nonzero and this much time elapses after that.
5304a21ef3SSunil Goutham */
5404a21ef3SSunil Goutham #define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
5504a21ef3SSunil Goutham #define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
5604a21ef3SSunil Goutham
5704a21ef3SSunil Goutham /* Min number of CQs (of the ones mapped to this CINT)
5804a21ef3SSunil Goutham * with valid CQEs.
5904a21ef3SSunil Goutham */
6004a21ef3SSunil Goutham #define CQ_QCOUNT_DEFAULT 1
6104a21ef3SSunil Goutham
62af3826dbSGeetha sowjanya #define CQ_OP_STAT_OP_ERR 63
63af3826dbSGeetha sowjanya #define CQ_OP_STAT_CQ_ERR 46
64af3826dbSGeetha sowjanya
65d45d8979SChristina Jacob struct queue_stats {
66d45d8979SChristina Jacob u64 bytes;
67d45d8979SChristina Jacob u64 pkts;
68d45d8979SChristina Jacob };
69d45d8979SChristina Jacob
70d45d8979SChristina Jacob struct otx2_rcv_queue {
71d45d8979SChristina Jacob struct queue_stats stats;
72d45d8979SChristina Jacob };
73d45d8979SChristina Jacob
743ca6c4c8SSunil Goutham struct sg_list {
753ca6c4c8SSunil Goutham u16 num_segs;
763ca6c4c8SSunil Goutham u64 skb;
773ca6c4c8SSunil Goutham u64 size[OTX2_MAX_FRAGS_IN_SQE];
783ca6c4c8SSunil Goutham u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
793ca6c4c8SSunil Goutham };
803ca6c4c8SSunil Goutham
81caa2da34SSunil Goutham struct otx2_snd_queue {
82caa2da34SSunil Goutham u8 aura_id;
833ca6c4c8SSunil Goutham u16 head;
84f0dfc4c8SRatheesh Kannoth u16 cons_head;
85caa2da34SSunil Goutham u16 sqe_size;
86caa2da34SSunil Goutham u32 sqe_cnt;
87caa2da34SSunil Goutham u16 num_sqbs;
883ca6c4c8SSunil Goutham u16 sqe_thresh;
89caa2da34SSunil Goutham u8 sqe_per_sqb;
90caa2da34SSunil Goutham u64 io_addr;
91caa2da34SSunil Goutham u64 *aura_fc_addr;
92caa2da34SSunil Goutham u64 *lmt_addr;
93caa2da34SSunil Goutham void *sqe_base;
94caa2da34SSunil Goutham struct qmem *sqe;
9586d74760SSunil Goutham struct qmem *tso_hdrs;
963ca6c4c8SSunil Goutham struct sg_list *sg;
97c9c12d33SAleksey Makarov struct qmem *timestamps;
98d45d8979SChristina Jacob struct queue_stats stats;
99caa2da34SSunil Goutham u16 sqb_count;
100caa2da34SSunil Goutham u64 *sqb_ptrs;
101caa2da34SSunil Goutham } ____cacheline_aligned_in_smp;
102caa2da34SSunil Goutham
10304a21ef3SSunil Goutham enum cq_type {
10404a21ef3SSunil Goutham CQ_RX,
10504a21ef3SSunil Goutham CQ_TX,
10606059a1aSGeetha sowjanya CQ_XDP,
107ab6dddd2SSubbaraya Sundeep CQ_QOS,
108ab6dddd2SSubbaraya Sundeep CQS_PER_CINT = 4, /* RQ + SQ + XDP + QOS_SQ */
10904a21ef3SSunil Goutham };
11004a21ef3SSunil Goutham
11104a21ef3SSunil Goutham struct otx2_cq_poll {
11204a21ef3SSunil Goutham void *dev;
11304a21ef3SSunil Goutham #define CINT_INVALID_CQ 255
11404a21ef3SSunil Goutham u8 cint_idx;
11504a21ef3SSunil Goutham u8 cq_ids[CQS_PER_CINT];
1166e144b47SSuman Ghosh struct dim dim;
11704a21ef3SSunil Goutham struct napi_struct napi;
11804a21ef3SSunil Goutham };
11904a21ef3SSunil Goutham
120caa2da34SSunil Goutham struct otx2_pool {
121caa2da34SSunil Goutham struct qmem *stack;
122caa2da34SSunil Goutham struct qmem *fc_addr;
123b2e3406aSRatheesh Kannoth struct page_pool *page_pool;
124caa2da34SSunil Goutham u16 rbsize;
125caa2da34SSunil Goutham };
126caa2da34SSunil Goutham
127caa2da34SSunil Goutham struct otx2_cq_queue {
128caa2da34SSunil Goutham u8 cq_idx;
129caa2da34SSunil Goutham u8 cq_type;
130abe02543SSunil Goutham u8 cint_idx; /* CQ interrupt id */
1314ff7d148SGeetha sowjanya u8 refill_task_sched;
132caa2da34SSunil Goutham u16 cqe_size;
133caa2da34SSunil Goutham u16 pool_ptrs;
134caa2da34SSunil Goutham u32 cqe_cnt;
135abe02543SSunil Goutham u32 cq_head;
136af3826dbSGeetha sowjanya u32 cq_tail;
137af3826dbSGeetha sowjanya u32 pend_cqe;
138caa2da34SSunil Goutham void *cqe_base;
139caa2da34SSunil Goutham struct qmem *cqe;
140caa2da34SSunil Goutham struct otx2_pool *rbpool;
14106059a1aSGeetha sowjanya struct xdp_rxq_info xdp_rxq;
142caa2da34SSunil Goutham } ____cacheline_aligned_in_smp;
143caa2da34SSunil Goutham
144caa2da34SSunil Goutham struct otx2_qset {
145caa2da34SSunil Goutham u32 rqe_cnt;
146caa2da34SSunil Goutham u32 sqe_cnt; /* Keep these two at top */
147caa2da34SSunil Goutham #define OTX2_MAX_CQ_CNT 64
148caa2da34SSunil Goutham u16 cq_cnt;
149caa2da34SSunil Goutham u16 xqe_size;
150caa2da34SSunil Goutham struct otx2_pool *pool;
15104a21ef3SSunil Goutham struct otx2_cq_poll *napi;
152caa2da34SSunil Goutham struct otx2_cq_queue *cq;
153caa2da34SSunil Goutham struct otx2_snd_queue *sq;
154d45d8979SChristina Jacob struct otx2_rcv_queue *rq;
155caa2da34SSunil Goutham };
156caa2da34SSunil Goutham
157caa2da34SSunil Goutham /* Translate IOVA to physical address */
otx2_iova_to_phys(void * iommu_domain,dma_addr_t dma_addr)158caa2da34SSunil Goutham static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
159caa2da34SSunil Goutham {
160caa2da34SSunil Goutham /* Translation is installed only when IOMMU is present */
161caa2da34SSunil Goutham if (likely(iommu_domain))
162caa2da34SSunil Goutham return iommu_iova_to_phys(iommu_domain, dma_addr);
163caa2da34SSunil Goutham return dma_addr;
164caa2da34SSunil Goutham }
165caa2da34SSunil Goutham
16604a21ef3SSunil Goutham int otx2_napi_handler(struct napi_struct *napi, int budget);
1673ca6c4c8SSunil Goutham bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
1683ca6c4c8SSunil Goutham struct sk_buff *skb, u16 qidx);
1694c236d5dSGeetha sowjanya void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
1704c236d5dSGeetha sowjanya int size, int qidx);
1714c236d5dSGeetha sowjanya void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
1724c236d5dSGeetha sowjanya int size, int qidx);
173*88e69af0SRatheesh Kannoth int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
174*88e69af0SRatheesh Kannoth int cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
175caa2da34SSunil Goutham #endif /* OTX2_TXRX_H */
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