1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <net/ip.h> 10 #include <net/tso.h> 11 #include <linux/bpf.h> 12 #include <linux/bpf_trace.h> 13 #include <net/ip6_checksum.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 #include "otx2_txrx.h" 19 #include "otx2_ptp.h" 20 #include "cn10k.h" 21 22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 23 #define PTP_PORT 0x13F 24 /* PTPv2 header Original Timestamp starts at byte offset 34 and 25 * contains 6 byte seconds field and 4 byte nano seconds field. 26 */ 27 #define PTP_SYNC_SEC_OFFSET 34 28 29 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 30 struct bpf_prog *prog, 31 struct nix_cqe_rx_s *cqe, 32 struct otx2_cq_queue *cq); 33 34 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf, 35 struct otx2_cq_queue *cq) 36 { 37 u64 incr = (u64)(cq->cq_idx) << 32; 38 u64 status; 39 40 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr); 41 42 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) || 43 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) { 44 dev_err(pfvf->dev, "CQ stopped due to error"); 45 return -EINVAL; 46 } 47 48 cq->cq_tail = status & 0xFFFFF; 49 cq->cq_head = (status >> 20) & 0xFFFFF; 50 if (cq->cq_tail < cq->cq_head) 51 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) + 52 cq->cq_tail; 53 else 54 cq->pend_cqe = cq->cq_tail - cq->cq_head; 55 56 return 0; 57 } 58 59 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 60 { 61 struct nix_cqe_hdr_s *cqe_hdr; 62 63 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 64 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 65 return NULL; 66 67 cq->cq_head++; 68 cq->cq_head &= (cq->cqe_cnt - 1); 69 70 return cqe_hdr; 71 } 72 73 static unsigned int frag_num(unsigned int i) 74 { 75 #ifdef __BIG_ENDIAN 76 return (i & ~3) + 3 - (i & 3); 77 #else 78 return i; 79 #endif 80 } 81 82 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 83 struct sk_buff *skb, int seg, int *len) 84 { 85 const skb_frag_t *frag; 86 struct page *page; 87 int offset; 88 89 /* First segment is always skb->data */ 90 if (!seg) { 91 page = virt_to_page(skb->data); 92 offset = offset_in_page(skb->data); 93 *len = skb_headlen(skb); 94 } else { 95 frag = &skb_shinfo(skb)->frags[seg - 1]; 96 page = skb_frag_page(frag); 97 offset = skb_frag_off(frag); 98 *len = skb_frag_size(frag); 99 } 100 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 101 } 102 103 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 104 { 105 int seg; 106 107 for (seg = 0; seg < sg->num_segs; seg++) { 108 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 109 sg->size[seg], DMA_TO_DEVICE); 110 } 111 sg->num_segs = 0; 112 } 113 114 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf, 115 struct otx2_snd_queue *sq, 116 struct nix_cqe_tx_s *cqe) 117 { 118 struct nix_send_comp_s *snd_comp = &cqe->comp; 119 struct sg_list *sg; 120 struct page *page; 121 u64 pa; 122 123 sg = &sq->sg[snd_comp->sqe_id]; 124 125 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]); 126 otx2_dma_unmap_page(pfvf, sg->dma_addr[0], 127 sg->size[0], DMA_TO_DEVICE); 128 page = virt_to_page(phys_to_virt(pa)); 129 put_page(page); 130 } 131 132 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 133 struct otx2_cq_queue *cq, 134 struct otx2_snd_queue *sq, 135 struct nix_cqe_tx_s *cqe, 136 int budget, int *tx_pkts, int *tx_bytes) 137 { 138 struct nix_send_comp_s *snd_comp = &cqe->comp; 139 struct skb_shared_hwtstamps ts; 140 struct sk_buff *skb = NULL; 141 u64 timestamp, tsns; 142 struct sg_list *sg; 143 int err; 144 145 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 146 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 147 pfvf->netdev->name, cq->cint_idx, 148 snd_comp->status); 149 150 sg = &sq->sg[snd_comp->sqe_id]; 151 skb = (struct sk_buff *)sg->skb; 152 if (unlikely(!skb)) 153 return; 154 155 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 156 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id]; 157 if (timestamp != 1) { 158 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp); 159 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 160 if (!err) { 161 memset(&ts, 0, sizeof(ts)); 162 ts.hwtstamp = ns_to_ktime(tsns); 163 skb_tstamp_tx(skb, &ts); 164 } 165 } 166 } 167 168 *tx_bytes += skb->len; 169 (*tx_pkts)++; 170 otx2_dma_unmap_skb_frags(pfvf, sg); 171 napi_consume_skb(skb, budget); 172 sg->skb = (u64)NULL; 173 } 174 175 static void otx2_set_rxtstamp(struct otx2_nic *pfvf, 176 struct sk_buff *skb, void *data) 177 { 178 u64 timestamp, tsns; 179 int err; 180 181 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)) 182 return; 183 184 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data); 185 /* The first 8 bytes is the timestamp */ 186 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 187 if (err) 188 return; 189 190 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns); 191 } 192 193 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 194 u64 iova, int len, struct nix_rx_parse_s *parse, 195 int qidx) 196 { 197 struct page *page; 198 int off = 0; 199 void *va; 200 201 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 202 203 if (likely(!skb_shinfo(skb)->nr_frags)) { 204 /* Check if data starts at some nonzero offset 205 * from the start of the buffer. For now the 206 * only possible offset is 8 bytes in the case 207 * where packet is prepended by a timestamp. 208 */ 209 if (parse->laptr) { 210 otx2_set_rxtstamp(pfvf, skb, va); 211 off = OTX2_HW_TIMESTAMP_LEN; 212 } 213 } 214 215 page = virt_to_page(va); 216 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) { 217 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 218 va - page_address(page) + off, 219 len - off, pfvf->rbsize); 220 return true; 221 } 222 223 /* If more than MAX_SKB_FRAGS fragments are received then 224 * give back those buffer pointers to hardware for reuse. 225 */ 226 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL); 227 228 return false; 229 } 230 231 static void otx2_set_rxhash(struct otx2_nic *pfvf, 232 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 233 { 234 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 235 struct otx2_rss_info *rss; 236 u32 hash = 0; 237 238 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 239 return; 240 241 rss = &pfvf->hw.rss_info; 242 if (rss->flowkey_cfg) { 243 if (rss->flowkey_cfg & 244 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 245 hash_type = PKT_HASH_TYPE_L4; 246 else 247 hash_type = PKT_HASH_TYPE_L3; 248 hash = cqe->hdr.flow_tag; 249 } 250 skb_set_hash(skb, hash, hash_type); 251 } 252 253 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe, 254 int qidx) 255 { 256 struct nix_rx_sg_s *sg = &cqe->sg; 257 void *end, *start; 258 u64 *seg_addr; 259 int seg; 260 261 start = (void *)sg; 262 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 263 while (start < end) { 264 sg = (struct nix_rx_sg_s *)start; 265 seg_addr = &sg->seg_addr; 266 for (seg = 0; seg < sg->segs; seg++, seg_addr++) 267 pfvf->hw_ops->aura_freeptr(pfvf, qidx, 268 *seg_addr & ~0x07ULL); 269 start += sizeof(*sg); 270 } 271 } 272 273 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 274 struct nix_cqe_rx_s *cqe, int qidx) 275 { 276 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 277 struct nix_rx_parse_s *parse = &cqe->parse; 278 279 if (netif_msg_rx_err(pfvf)) 280 netdev_err(pfvf->netdev, 281 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 282 qidx, parse->errlev, parse->errcode); 283 284 if (parse->errlev == NPC_ERRLVL_RE) { 285 switch (parse->errcode) { 286 case ERRCODE_FCS: 287 case ERRCODE_FCS_RCV: 288 atomic_inc(&stats->rx_fcs_errs); 289 break; 290 case ERRCODE_UNDERSIZE: 291 atomic_inc(&stats->rx_undersize_errs); 292 break; 293 case ERRCODE_OVERSIZE: 294 atomic_inc(&stats->rx_oversize_errs); 295 break; 296 case ERRCODE_OL2_LEN_MISMATCH: 297 atomic_inc(&stats->rx_len_errs); 298 break; 299 default: 300 atomic_inc(&stats->rx_other_errs); 301 break; 302 } 303 } else if (parse->errlev == NPC_ERRLVL_NIX) { 304 switch (parse->errcode) { 305 case ERRCODE_OL3_LEN: 306 case ERRCODE_OL4_LEN: 307 case ERRCODE_IL3_LEN: 308 case ERRCODE_IL4_LEN: 309 atomic_inc(&stats->rx_len_errs); 310 break; 311 case ERRCODE_OL4_CSUM: 312 case ERRCODE_IL4_CSUM: 313 atomic_inc(&stats->rx_csum_errs); 314 break; 315 default: 316 atomic_inc(&stats->rx_other_errs); 317 break; 318 } 319 } else { 320 atomic_inc(&stats->rx_other_errs); 321 /* For now ignore all the NPC parser errors and 322 * pass the packets to stack. 323 */ 324 return false; 325 } 326 327 /* If RXALL is enabled pass on packets to stack. */ 328 if (pfvf->netdev->features & NETIF_F_RXALL) 329 return false; 330 331 /* Free buffer back to pool */ 332 if (cqe->sg.segs) 333 otx2_free_rcv_seg(pfvf, cqe, qidx); 334 return true; 335 } 336 337 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 338 struct napi_struct *napi, 339 struct otx2_cq_queue *cq, 340 struct nix_cqe_rx_s *cqe) 341 { 342 struct nix_rx_parse_s *parse = &cqe->parse; 343 struct nix_rx_sg_s *sg = &cqe->sg; 344 struct sk_buff *skb = NULL; 345 void *end, *start; 346 u64 *seg_addr; 347 u16 *seg_size; 348 int seg; 349 350 if (unlikely(parse->errlev || parse->errcode)) { 351 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 352 return; 353 } 354 355 if (pfvf->xdp_prog) 356 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq)) 357 return; 358 359 skb = napi_get_frags(napi); 360 if (unlikely(!skb)) 361 return; 362 363 start = (void *)sg; 364 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 365 while (start < end) { 366 sg = (struct nix_rx_sg_s *)start; 367 seg_addr = &sg->seg_addr; 368 seg_size = (void *)sg; 369 for (seg = 0; seg < sg->segs; seg++, seg_addr++) { 370 if (otx2_skb_add_frag(pfvf, skb, *seg_addr, 371 seg_size[seg], parse, cq->cq_idx)) 372 cq->pool_ptrs++; 373 } 374 start += sizeof(*sg); 375 } 376 otx2_set_rxhash(pfvf, cqe, skb); 377 378 skb_record_rx_queue(skb, cq->cq_idx); 379 if (pfvf->netdev->features & NETIF_F_RXCSUM) 380 skb->ip_summed = CHECKSUM_UNNECESSARY; 381 382 skb_mark_for_recycle(skb); 383 384 napi_gro_frags(napi); 385 } 386 387 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 388 struct napi_struct *napi, 389 struct otx2_cq_queue *cq, int budget) 390 { 391 struct nix_cqe_rx_s *cqe; 392 int processed_cqe = 0; 393 394 if (cq->pend_cqe >= budget) 395 goto process_cqe; 396 397 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 398 return 0; 399 400 process_cqe: 401 while (likely(processed_cqe < budget) && cq->pend_cqe) { 402 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 403 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 404 !cqe->sg.seg_addr) { 405 if (!processed_cqe) 406 return 0; 407 break; 408 } 409 cq->cq_head++; 410 cq->cq_head &= (cq->cqe_cnt - 1); 411 412 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 413 414 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 415 cqe->sg.seg_addr = 0x00; 416 processed_cqe++; 417 cq->pend_cqe--; 418 } 419 420 /* Free CQEs to HW */ 421 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 422 ((u64)cq->cq_idx << 32) | processed_cqe); 423 424 return processed_cqe; 425 } 426 427 int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 428 { 429 struct otx2_nic *pfvf = dev; 430 int cnt = cq->pool_ptrs; 431 dma_addr_t bufptr; 432 433 while (cq->pool_ptrs) { 434 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) 435 break; 436 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 437 cq->pool_ptrs--; 438 } 439 440 return cnt - cq->pool_ptrs; 441 } 442 443 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 444 struct otx2_cq_queue *cq, int budget) 445 { 446 int tx_pkts = 0, tx_bytes = 0, qidx; 447 struct otx2_snd_queue *sq; 448 struct nix_cqe_tx_s *cqe; 449 int processed_cqe = 0; 450 451 if (cq->pend_cqe >= budget) 452 goto process_cqe; 453 454 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 455 return 0; 456 457 process_cqe: 458 qidx = cq->cq_idx - pfvf->hw.rx_queues; 459 sq = &pfvf->qset.sq[qidx]; 460 461 while (likely(processed_cqe < budget) && cq->pend_cqe) { 462 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 463 if (unlikely(!cqe)) { 464 if (!processed_cqe) 465 return 0; 466 break; 467 } 468 469 qidx = cq->cq_idx - pfvf->hw.rx_queues; 470 471 if (cq->cq_type == CQ_XDP) 472 otx2_xdp_snd_pkt_handler(pfvf, sq, cqe); 473 else 474 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[qidx], 475 cqe, budget, &tx_pkts, &tx_bytes); 476 477 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 478 processed_cqe++; 479 cq->pend_cqe--; 480 481 sq->cons_head++; 482 sq->cons_head &= (sq->sqe_cnt - 1); 483 } 484 485 /* Free CQEs to HW */ 486 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 487 ((u64)cq->cq_idx << 32) | processed_cqe); 488 489 if (likely(tx_pkts)) { 490 struct netdev_queue *txq; 491 492 qidx = cq->cq_idx - pfvf->hw.rx_queues; 493 494 if (qidx >= pfvf->hw.tx_queues) 495 qidx -= pfvf->hw.xdp_queues; 496 txq = netdev_get_tx_queue(pfvf->netdev, qidx); 497 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 498 /* Check if queue was stopped earlier due to ring full */ 499 smp_mb(); 500 if (netif_tx_queue_stopped(txq) && 501 netif_carrier_ok(pfvf->netdev)) 502 netif_tx_wake_queue(txq); 503 } 504 return 0; 505 } 506 507 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll) 508 { 509 struct dim_sample dim_sample; 510 u64 rx_frames, rx_bytes; 511 512 rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) + 513 OTX2_GET_RX_STATS(RX_UCAST); 514 rx_bytes = OTX2_GET_RX_STATS(RX_OCTS); 515 dim_update_sample(pfvf->napi_events, rx_frames, rx_bytes, &dim_sample); 516 net_dim(&cq_poll->dim, dim_sample); 517 } 518 519 int otx2_napi_handler(struct napi_struct *napi, int budget) 520 { 521 struct otx2_cq_queue *rx_cq = NULL; 522 struct otx2_cq_poll *cq_poll; 523 int workdone = 0, cq_idx, i; 524 struct otx2_cq_queue *cq; 525 struct otx2_qset *qset; 526 struct otx2_nic *pfvf; 527 int filled_cnt = -1; 528 529 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 530 pfvf = (struct otx2_nic *)cq_poll->dev; 531 qset = &pfvf->qset; 532 533 for (i = 0; i < CQS_PER_CINT; i++) { 534 cq_idx = cq_poll->cq_ids[i]; 535 if (unlikely(cq_idx == CINT_INVALID_CQ)) 536 continue; 537 cq = &qset->cq[cq_idx]; 538 if (cq->cq_type == CQ_RX) { 539 rx_cq = cq; 540 workdone += otx2_rx_napi_handler(pfvf, napi, 541 cq, budget); 542 } else { 543 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 544 } 545 } 546 547 if (rx_cq && rx_cq->pool_ptrs) 548 filled_cnt = pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq); 549 /* Clear the IRQ */ 550 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 551 552 if (workdone < budget && napi_complete_done(napi, workdone)) { 553 /* If interface is going down, don't re-enable IRQ */ 554 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 555 return workdone; 556 557 /* Check for adaptive interrupt coalesce */ 558 if (workdone != 0 && 559 ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) == 560 OTX2_FLAG_ADPTV_INT_COAL_ENABLED)) { 561 /* Adjust irq coalese using net_dim */ 562 otx2_adjust_adaptive_coalese(pfvf, cq_poll); 563 /* Update irq coalescing */ 564 for (i = 0; i < pfvf->hw.cint_cnt; i++) 565 otx2_config_irq_coalescing(pfvf, i); 566 } 567 568 if (unlikely(!filled_cnt)) { 569 struct refill_work *work; 570 struct delayed_work *dwork; 571 572 work = &pfvf->refill_wrk[cq->cq_idx]; 573 dwork = &work->pool_refill_work; 574 /* Schedule a task if no other task is running */ 575 if (!cq->refill_task_sched) { 576 work->napi = napi; 577 cq->refill_task_sched = true; 578 schedule_delayed_work(dwork, 579 msecs_to_jiffies(100)); 580 } 581 } else { 582 /* Re-enable interrupts */ 583 otx2_write64(pfvf, 584 NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 585 BIT_ULL(0)); 586 } 587 } 588 return workdone; 589 } 590 591 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 592 int size, int qidx) 593 { 594 u64 status; 595 596 /* Packet data stores should finish before SQE is flushed to HW */ 597 dma_wmb(); 598 599 do { 600 memcpy(sq->lmt_addr, sq->sqe_base, size); 601 status = otx2_lmt_flush(sq->io_addr); 602 } while (status == 0); 603 604 sq->head++; 605 sq->head &= (sq->sqe_cnt - 1); 606 } 607 608 #define MAX_SEGS_PER_SG 3 609 /* Add SQE scatter/gather subdescriptor structure */ 610 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 611 struct sk_buff *skb, int num_segs, int *offset) 612 { 613 struct nix_sqe_sg_s *sg = NULL; 614 u64 dma_addr, *iova = NULL; 615 u16 *sg_lens = NULL; 616 int seg, len; 617 618 sq->sg[sq->head].num_segs = 0; 619 620 for (seg = 0; seg < num_segs; seg++) { 621 if ((seg % MAX_SEGS_PER_SG) == 0) { 622 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 623 sg->ld_type = NIX_SEND_LDTYPE_LDD; 624 sg->subdc = NIX_SUBDC_SG; 625 sg->segs = 0; 626 sg_lens = (void *)sg; 627 iova = (void *)sg + sizeof(*sg); 628 /* Next subdc always starts at a 16byte boundary. 629 * So if sg->segs is whether 2 or 3, offset += 16bytes. 630 */ 631 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 632 *offset += sizeof(*sg) + (3 * sizeof(u64)); 633 else 634 *offset += sizeof(*sg) + sizeof(u64); 635 } 636 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 637 if (dma_mapping_error(pfvf->dev, dma_addr)) 638 return false; 639 640 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 641 sg->segs++; 642 *iova++ = dma_addr; 643 644 /* Save DMA mapping info for later unmapping */ 645 sq->sg[sq->head].dma_addr[seg] = dma_addr; 646 sq->sg[sq->head].size[seg] = len; 647 sq->sg[sq->head].num_segs++; 648 } 649 650 sq->sg[sq->head].skb = (u64)skb; 651 return true; 652 } 653 654 /* Add SQE extended header subdescriptor */ 655 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 656 struct sk_buff *skb, int *offset) 657 { 658 struct nix_sqe_ext_s *ext; 659 660 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 661 ext->subdc = NIX_SUBDC_EXT; 662 if (skb_shinfo(skb)->gso_size) { 663 ext->lso = 1; 664 ext->lso_sb = skb_tcp_all_headers(skb); 665 ext->lso_mps = skb_shinfo(skb)->gso_size; 666 667 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 668 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 669 ext->lso_format = pfvf->hw.lso_tsov4_idx; 670 671 /* HW adds payload size to 'ip_hdr->tot_len' while 672 * sending TSO segment, hence set payload length 673 * in IP header of the packet to just header length. 674 */ 675 ip_hdr(skb)->tot_len = 676 htons(ext->lso_sb - skb_network_offset(skb)); 677 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 678 ext->lso_format = pfvf->hw.lso_tsov6_idx; 679 ipv6_hdr(skb)->payload_len = htons(tcp_hdrlen(skb)); 680 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 681 __be16 l3_proto = vlan_get_protocol(skb); 682 struct udphdr *udph = udp_hdr(skb); 683 u16 iplen; 684 685 ext->lso_sb = skb_transport_offset(skb) + 686 sizeof(struct udphdr); 687 688 /* HW adds payload size to length fields in IP and 689 * UDP headers while segmentation, hence adjust the 690 * lengths to just header sizes. 691 */ 692 iplen = htons(ext->lso_sb - skb_network_offset(skb)); 693 if (l3_proto == htons(ETH_P_IP)) { 694 ip_hdr(skb)->tot_len = iplen; 695 ext->lso_format = pfvf->hw.lso_udpv4_idx; 696 } else { 697 ipv6_hdr(skb)->payload_len = iplen; 698 ext->lso_format = pfvf->hw.lso_udpv6_idx; 699 } 700 701 udph->len = htons(sizeof(struct udphdr)); 702 } 703 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 704 ext->tstmp = 1; 705 } 706 707 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN) 708 if (skb_vlan_tag_present(skb)) { 709 if (skb->vlan_proto == htons(ETH_P_8021Q)) { 710 ext->vlan1_ins_ena = 1; 711 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET; 712 ext->vlan1_ins_tci = skb_vlan_tag_get(skb); 713 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) { 714 ext->vlan0_ins_ena = 1; 715 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET; 716 ext->vlan0_ins_tci = skb_vlan_tag_get(skb); 717 } 718 } 719 720 *offset += sizeof(*ext); 721 } 722 723 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset, 724 int alg, u64 iova, int ptp_offset, 725 u64 base_ns, bool udp_csum_crt) 726 { 727 struct nix_sqe_mem_s *mem; 728 729 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset); 730 mem->subdc = NIX_SUBDC_MEM; 731 mem->alg = alg; 732 mem->wmem = 1; /* wait for the memory operation */ 733 mem->addr = iova; 734 735 if (ptp_offset) { 736 mem->start_offset = ptp_offset; 737 mem->udp_csum_crt = !!udp_csum_crt; 738 mem->base_ns = base_ns; 739 mem->step_type = 1; 740 } 741 742 *offset += sizeof(*mem); 743 } 744 745 /* Add SQE header subdescriptor structure */ 746 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 747 struct nix_sqe_hdr_s *sqe_hdr, 748 struct sk_buff *skb, u16 qidx) 749 { 750 int proto = 0; 751 752 /* Check if SQE was framed before, if yes then no need to 753 * set these constants again and again. 754 */ 755 if (!sqe_hdr->total) { 756 /* Don't free Tx buffers to Aura */ 757 sqe_hdr->df = 1; 758 sqe_hdr->aura = sq->aura_id; 759 /* Post a CQE Tx after pkt transmission */ 760 sqe_hdr->pnc = 1; 761 sqe_hdr->sq = (qidx >= pfvf->hw.tx_queues) ? 762 qidx + pfvf->hw.xdp_queues : qidx; 763 } 764 sqe_hdr->total = skb->len; 765 /* Set SQE identifier which will be used later for freeing SKB */ 766 sqe_hdr->sqe_id = sq->head; 767 768 /* Offload TCP/UDP checksum to HW */ 769 if (skb->ip_summed == CHECKSUM_PARTIAL) { 770 sqe_hdr->ol3ptr = skb_network_offset(skb); 771 sqe_hdr->ol4ptr = skb_transport_offset(skb); 772 /* get vlan protocol Ethertype */ 773 if (eth_type_vlan(skb->protocol)) 774 skb->protocol = vlan_get_protocol(skb); 775 776 if (skb->protocol == htons(ETH_P_IP)) { 777 proto = ip_hdr(skb)->protocol; 778 /* In case of TSO, HW needs this to be explicitly set. 779 * So set this always, instead of adding a check. 780 */ 781 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 782 } else if (skb->protocol == htons(ETH_P_IPV6)) { 783 proto = ipv6_hdr(skb)->nexthdr; 784 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6; 785 } 786 787 if (proto == IPPROTO_TCP) 788 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 789 else if (proto == IPPROTO_UDP) 790 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 791 } 792 } 793 794 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 795 struct otx2_snd_queue *sq, 796 struct sk_buff *skb, int sqe, int hdr_len) 797 { 798 int num_segs = skb_shinfo(skb)->nr_frags + 1; 799 struct sg_list *sg = &sq->sg[sqe]; 800 u64 dma_addr; 801 int seg, len; 802 803 sg->num_segs = 0; 804 805 /* Get payload length at skb->data */ 806 len = skb_headlen(skb) - hdr_len; 807 808 for (seg = 0; seg < num_segs; seg++) { 809 /* Skip skb->data, if there is no payload */ 810 if (!seg && !len) 811 continue; 812 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 813 if (dma_mapping_error(pfvf->dev, dma_addr)) 814 goto unmap; 815 816 /* Save DMA mapping info for later unmapping */ 817 sg->dma_addr[sg->num_segs] = dma_addr; 818 sg->size[sg->num_segs] = len; 819 sg->num_segs++; 820 } 821 return 0; 822 unmap: 823 otx2_dma_unmap_skb_frags(pfvf, sg); 824 return -EINVAL; 825 } 826 827 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 828 struct sk_buff *skb, int seg, 829 u64 seg_addr, int hdr_len, int sqe) 830 { 831 struct sg_list *sg = &sq->sg[sqe]; 832 const skb_frag_t *frag; 833 int offset; 834 835 if (seg < 0) 836 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 837 838 frag = &skb_shinfo(skb)->frags[seg]; 839 offset = seg_addr - (u64)skb_frag_address(frag); 840 if (skb_headlen(skb) - hdr_len) 841 seg++; 842 return sg->dma_addr[seg] + offset; 843 } 844 845 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 846 struct sg_list *list, int *offset) 847 { 848 struct nix_sqe_sg_s *sg = NULL; 849 u16 *sg_lens = NULL; 850 u64 *iova = NULL; 851 int seg; 852 853 /* Add SG descriptors with buffer addresses */ 854 for (seg = 0; seg < list->num_segs; seg++) { 855 if ((seg % MAX_SEGS_PER_SG) == 0) { 856 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 857 sg->ld_type = NIX_SEND_LDTYPE_LDD; 858 sg->subdc = NIX_SUBDC_SG; 859 sg->segs = 0; 860 sg_lens = (void *)sg; 861 iova = (void *)sg + sizeof(*sg); 862 /* Next subdc always starts at a 16byte boundary. 863 * So if sg->segs is whether 2 or 3, offset += 16bytes. 864 */ 865 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 866 *offset += sizeof(*sg) + (3 * sizeof(u64)); 867 else 868 *offset += sizeof(*sg) + sizeof(u64); 869 } 870 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 871 *iova++ = list->dma_addr[seg]; 872 sg->segs++; 873 } 874 } 875 876 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 877 struct sk_buff *skb, u16 qidx) 878 { 879 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 880 int hdr_len, tcp_data, seg_len, pkt_len, offset; 881 struct nix_sqe_hdr_s *sqe_hdr; 882 int first_sqe = sq->head; 883 struct sg_list list; 884 struct tso_t tso; 885 886 hdr_len = tso_start(skb, &tso); 887 888 /* Map SKB's fragments to DMA. 889 * It's done here to avoid mapping for every TSO segment's packet. 890 */ 891 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 892 dev_kfree_skb_any(skb); 893 return; 894 } 895 896 netdev_tx_sent_queue(txq, skb->len); 897 898 tcp_data = skb->len - hdr_len; 899 while (tcp_data > 0) { 900 char *hdr; 901 902 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 903 tcp_data -= seg_len; 904 905 /* Set SQE's SEND_HDR */ 906 memset(sq->sqe_base, 0, sq->sqe_size); 907 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 908 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 909 offset = sizeof(*sqe_hdr); 910 911 /* Add TSO segment's pkt header */ 912 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 913 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 914 list.dma_addr[0] = 915 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 916 list.size[0] = hdr_len; 917 list.num_segs = 1; 918 919 /* Add TSO segment's payload data fragments */ 920 pkt_len = hdr_len; 921 while (seg_len > 0) { 922 int size; 923 924 size = min_t(int, tso.size, seg_len); 925 926 list.size[list.num_segs] = size; 927 list.dma_addr[list.num_segs] = 928 otx2_tso_frag_dma_addr(sq, skb, 929 tso.next_frag_idx - 1, 930 (u64)tso.data, hdr_len, 931 first_sqe); 932 list.num_segs++; 933 pkt_len += size; 934 seg_len -= size; 935 tso_build_data(skb, &tso, size); 936 } 937 sqe_hdr->total = pkt_len; 938 otx2_sqe_tso_add_sg(sq, &list, &offset); 939 940 /* DMA mappings and skb needs to be freed only after last 941 * TSO segment is transmitted out. So set 'PNC' only for 942 * last segment. Also point last segment's sqe_id to first 943 * segment's SQE index where skb address and DMA mappings 944 * are saved. 945 */ 946 if (!tcp_data) { 947 sqe_hdr->pnc = 1; 948 sqe_hdr->sqe_id = first_sqe; 949 sq->sg[first_sqe].skb = (u64)skb; 950 } else { 951 sqe_hdr->pnc = 0; 952 } 953 954 sqe_hdr->sizem1 = (offset / 16) - 1; 955 956 /* Flush SQE to HW */ 957 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 958 } 959 } 960 961 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 962 struct sk_buff *skb) 963 { 964 int payload_len, last_seg_size; 965 966 if (test_bit(HW_TSO, &pfvf->hw.cap_flag)) 967 return true; 968 969 /* On 96xx A0, HW TSO not supported */ 970 if (!is_96xx_B0(pfvf->pdev)) 971 return false; 972 973 /* HW has an issue due to which when the payload of the last LSO 974 * segment is shorter than 16 bytes, some header fields may not 975 * be correctly modified, hence don't offload such TSO segments. 976 */ 977 978 payload_len = skb->len - skb_tcp_all_headers(skb); 979 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 980 if (last_seg_size && last_seg_size < 16) 981 return false; 982 983 return true; 984 } 985 986 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 987 { 988 if (!skb_shinfo(skb)->gso_size) 989 return 1; 990 991 /* HW TSO */ 992 if (is_hw_tso_supported(pfvf, skb)) 993 return 1; 994 995 /* SW TSO */ 996 return skb_shinfo(skb)->gso_segs; 997 } 998 999 static bool otx2_validate_network_transport(struct sk_buff *skb) 1000 { 1001 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) || 1002 (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) { 1003 struct udphdr *udph = udp_hdr(skb); 1004 1005 if (udph->source == htons(PTP_PORT) && 1006 udph->dest == htons(PTP_PORT)) 1007 return true; 1008 } 1009 1010 return false; 1011 } 1012 1013 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, bool *udp_csum_crt) 1014 { 1015 struct ethhdr *eth = (struct ethhdr *)(skb->data); 1016 u16 nix_offload_hlen = 0, inner_vhlen = 0; 1017 bool udp_hdr_present = false, is_sync; 1018 u8 *data = skb->data, *msgtype; 1019 __be16 proto = eth->h_proto; 1020 int network_depth = 0; 1021 1022 /* NIX is programmed to offload outer VLAN header 1023 * in case of single vlan protocol field holds Network header ETH_IP/V6 1024 * in case of stacked vlan protocol field holds Inner vlan (8100) 1025 */ 1026 if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX && 1027 skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) { 1028 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 1029 /* Get vlan protocol */ 1030 proto = __vlan_get_protocol(skb, eth->h_proto, NULL); 1031 /* SKB APIs like skb_transport_offset does not include 1032 * offloaded vlan header length. Need to explicitly add 1033 * the length 1034 */ 1035 nix_offload_hlen = VLAN_HLEN; 1036 inner_vhlen = VLAN_HLEN; 1037 } else if (skb->vlan_proto == htons(ETH_P_8021Q)) { 1038 nix_offload_hlen = VLAN_HLEN; 1039 } 1040 } else if (eth_type_vlan(eth->h_proto)) { 1041 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); 1042 } 1043 1044 switch (ntohs(proto)) { 1045 case ETH_P_1588: 1046 if (network_depth) 1047 *offset = network_depth; 1048 else 1049 *offset = ETH_HLEN + nix_offload_hlen + 1050 inner_vhlen; 1051 break; 1052 case ETH_P_IP: 1053 case ETH_P_IPV6: 1054 if (!otx2_validate_network_transport(skb)) 1055 return false; 1056 1057 *offset = nix_offload_hlen + skb_transport_offset(skb) + 1058 sizeof(struct udphdr); 1059 udp_hdr_present = true; 1060 1061 } 1062 1063 msgtype = data + *offset; 1064 /* Check PTP messageId is SYNC or not */ 1065 is_sync = !(*msgtype & 0xf); 1066 if (is_sync) 1067 *udp_csum_crt = udp_hdr_present; 1068 else 1069 *offset = 0; 1070 1071 return is_sync; 1072 } 1073 1074 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb, 1075 struct otx2_snd_queue *sq, int *offset) 1076 { 1077 struct ethhdr *eth = (struct ethhdr *)(skb->data); 1078 struct ptpv2_tstamp *origin_tstamp; 1079 bool udp_csum_crt = false; 1080 unsigned int udphoff; 1081 struct timespec64 ts; 1082 int ptp_offset = 0; 1083 __wsum skb_csum; 1084 u64 iova; 1085 1086 if (unlikely(!skb_shinfo(skb)->gso_size && 1087 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) { 1088 if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC && 1089 otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum_crt))) { 1090 origin_tstamp = (struct ptpv2_tstamp *) 1091 ((u8 *)skb->data + ptp_offset + 1092 PTP_SYNC_SEC_OFFSET); 1093 ts = ns_to_timespec64(pfvf->ptp->tstamp); 1094 origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff); 1095 origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff); 1096 origin_tstamp->nanoseconds = htonl(ts.tv_nsec); 1097 /* Point to correction field in PTP packet */ 1098 ptp_offset += 8; 1099 1100 /* When user disables hw checksum, stack calculates the csum, 1101 * but it does not cover ptp timestamp which is added later. 1102 * Recalculate the checksum manually considering the timestamp. 1103 */ 1104 if (udp_csum_crt) { 1105 struct udphdr *uh = udp_hdr(skb); 1106 1107 if (skb->ip_summed != CHECKSUM_PARTIAL && uh->check != 0) { 1108 udphoff = skb_transport_offset(skb); 1109 uh->check = 0; 1110 skb_csum = skb_checksum(skb, udphoff, skb->len - udphoff, 1111 0); 1112 if (ntohs(eth->h_proto) == ETH_P_IPV6) 1113 uh->check = csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 1114 &ipv6_hdr(skb)->daddr, 1115 skb->len - udphoff, 1116 ipv6_hdr(skb)->nexthdr, 1117 skb_csum); 1118 else 1119 uh->check = csum_tcpudp_magic(ip_hdr(skb)->saddr, 1120 ip_hdr(skb)->daddr, 1121 skb->len - udphoff, 1122 IPPROTO_UDP, 1123 skb_csum); 1124 } 1125 } 1126 } else { 1127 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1128 } 1129 iova = sq->timestamps->iova + (sq->head * sizeof(u64)); 1130 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova, 1131 ptp_offset, pfvf->ptp->base_ns, udp_csum_crt); 1132 } else { 1133 skb_tx_timestamp(skb); 1134 } 1135 } 1136 1137 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 1138 struct sk_buff *skb, u16 qidx) 1139 { 1140 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 1141 struct otx2_nic *pfvf = netdev_priv(netdev); 1142 int offset, num_segs, free_desc; 1143 struct nix_sqe_hdr_s *sqe_hdr; 1144 1145 /* Check if there is enough room between producer 1146 * and consumer index. 1147 */ 1148 free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1); 1149 if (free_desc < sq->sqe_thresh) 1150 return false; 1151 1152 if (free_desc < otx2_get_sqe_count(pfvf, skb)) 1153 return false; 1154 1155 num_segs = skb_shinfo(skb)->nr_frags + 1; 1156 1157 /* If SKB doesn't fit in a single SQE, linearize it. 1158 * TODO: Consider adding JUMP descriptor instead. 1159 */ 1160 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 1161 if (__skb_linearize(skb)) { 1162 dev_kfree_skb_any(skb); 1163 return true; 1164 } 1165 num_segs = skb_shinfo(skb)->nr_frags + 1; 1166 } 1167 1168 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 1169 /* Insert vlan tag before giving pkt to tso */ 1170 if (skb_vlan_tag_present(skb)) 1171 skb = __vlan_hwaccel_push_inside(skb); 1172 otx2_sq_append_tso(pfvf, sq, skb, qidx); 1173 return true; 1174 } 1175 1176 /* Set SQE's SEND_HDR. 1177 * Do not clear the first 64bit as it contains constant info. 1178 */ 1179 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1180 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1181 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 1182 offset = sizeof(*sqe_hdr); 1183 1184 /* Add extended header if needed */ 1185 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 1186 1187 /* Add SG subdesc with data frags */ 1188 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 1189 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 1190 return false; 1191 } 1192 1193 otx2_set_txtstamp(pfvf, skb, sq, &offset); 1194 1195 sqe_hdr->sizem1 = (offset / 16) - 1; 1196 1197 netdev_tx_sent_queue(txq, skb->len); 1198 1199 /* Flush SQE to HW */ 1200 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1201 1202 return true; 1203 } 1204 EXPORT_SYMBOL(otx2_sq_append_skb); 1205 1206 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx) 1207 { 1208 struct nix_cqe_rx_s *cqe; 1209 struct otx2_pool *pool; 1210 int processed_cqe = 0; 1211 u16 pool_id; 1212 u64 iova; 1213 1214 if (pfvf->xdp_prog) 1215 xdp_rxq_info_unreg(&cq->xdp_rxq); 1216 1217 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1218 return; 1219 1220 pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx); 1221 pool = &pfvf->qset.pool[pool_id]; 1222 1223 while (cq->pend_cqe) { 1224 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq); 1225 processed_cqe++; 1226 cq->pend_cqe--; 1227 1228 if (!cqe) 1229 continue; 1230 if (cqe->sg.segs > 1) { 1231 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx); 1232 continue; 1233 } 1234 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1235 1236 otx2_free_bufs(pfvf, pool, iova, pfvf->rbsize); 1237 } 1238 1239 /* Free CQEs to HW */ 1240 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1241 ((u64)cq->cq_idx << 32) | processed_cqe); 1242 } 1243 1244 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1245 { 1246 struct sk_buff *skb = NULL; 1247 struct otx2_snd_queue *sq; 1248 struct nix_cqe_tx_s *cqe; 1249 int processed_cqe = 0; 1250 struct sg_list *sg; 1251 int qidx; 1252 1253 qidx = cq->cq_idx - pfvf->hw.rx_queues; 1254 sq = &pfvf->qset.sq[qidx]; 1255 1256 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1257 return; 1258 1259 while (cq->pend_cqe) { 1260 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 1261 processed_cqe++; 1262 cq->pend_cqe--; 1263 1264 if (!cqe) 1265 continue; 1266 sg = &sq->sg[cqe->comp.sqe_id]; 1267 skb = (struct sk_buff *)sg->skb; 1268 if (skb) { 1269 otx2_dma_unmap_skb_frags(pfvf, sg); 1270 dev_kfree_skb_any(skb); 1271 sg->skb = (u64)NULL; 1272 } 1273 } 1274 1275 /* Free CQEs to HW */ 1276 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1277 ((u64)cq->cq_idx << 32) | processed_cqe); 1278 } 1279 1280 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 1281 { 1282 struct msg_req *msg; 1283 int err; 1284 1285 mutex_lock(&pfvf->mbox.lock); 1286 if (enable) 1287 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 1288 else 1289 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 1290 1291 if (!msg) { 1292 mutex_unlock(&pfvf->mbox.lock); 1293 return -ENOMEM; 1294 } 1295 1296 err = otx2_sync_mbox_msg(&pfvf->mbox); 1297 mutex_unlock(&pfvf->mbox.lock); 1298 return err; 1299 } 1300 1301 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr, 1302 int len, int *offset) 1303 { 1304 struct nix_sqe_sg_s *sg = NULL; 1305 u64 *iova = NULL; 1306 1307 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 1308 sg->ld_type = NIX_SEND_LDTYPE_LDD; 1309 sg->subdc = NIX_SUBDC_SG; 1310 sg->segs = 1; 1311 sg->seg1_size = len; 1312 iova = (void *)sg + sizeof(*sg); 1313 *iova = dma_addr; 1314 *offset += sizeof(*sg) + sizeof(u64); 1315 1316 sq->sg[sq->head].dma_addr[0] = dma_addr; 1317 sq->sg[sq->head].size[0] = len; 1318 sq->sg[sq->head].num_segs = 1; 1319 } 1320 1321 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx) 1322 { 1323 struct nix_sqe_hdr_s *sqe_hdr; 1324 struct otx2_snd_queue *sq; 1325 int offset, free_sqe; 1326 1327 sq = &pfvf->qset.sq[qidx]; 1328 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 1329 if (free_sqe < sq->sqe_thresh) 1330 return false; 1331 1332 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1333 1334 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1335 1336 if (!sqe_hdr->total) { 1337 sqe_hdr->aura = sq->aura_id; 1338 sqe_hdr->df = 1; 1339 sqe_hdr->sq = qidx; 1340 sqe_hdr->pnc = 1; 1341 } 1342 sqe_hdr->total = len; 1343 sqe_hdr->sqe_id = sq->head; 1344 1345 offset = sizeof(*sqe_hdr); 1346 1347 otx2_xdp_sqe_add_sg(sq, iova, len, &offset); 1348 sqe_hdr->sizem1 = (offset / 16) - 1; 1349 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1350 1351 return true; 1352 } 1353 1354 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 1355 struct bpf_prog *prog, 1356 struct nix_cqe_rx_s *cqe, 1357 struct otx2_cq_queue *cq) 1358 { 1359 unsigned char *hard_start, *data; 1360 int qidx = cq->cq_idx; 1361 struct xdp_buff xdp; 1362 struct page *page; 1363 u64 iova, pa; 1364 u32 act; 1365 int err; 1366 1367 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1368 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1369 page = virt_to_page(phys_to_virt(pa)); 1370 1371 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq); 1372 1373 data = (unsigned char *)phys_to_virt(pa); 1374 hard_start = page_address(page); 1375 xdp_prepare_buff(&xdp, hard_start, data - hard_start, 1376 cqe->sg.seg_size, false); 1377 1378 act = bpf_prog_run_xdp(prog, &xdp); 1379 1380 switch (act) { 1381 case XDP_PASS: 1382 break; 1383 case XDP_TX: 1384 qidx += pfvf->hw.tx_queues; 1385 cq->pool_ptrs++; 1386 return otx2_xdp_sq_append_pkt(pfvf, iova, 1387 cqe->sg.seg_size, qidx); 1388 case XDP_REDIRECT: 1389 cq->pool_ptrs++; 1390 err = xdp_do_redirect(pfvf->netdev, &xdp, prog); 1391 1392 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1393 DMA_FROM_DEVICE); 1394 if (!err) 1395 return true; 1396 put_page(page); 1397 break; 1398 default: 1399 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act); 1400 break; 1401 case XDP_ABORTED: 1402 trace_xdp_exception(pfvf->netdev, prog, act); 1403 break; 1404 case XDP_DROP: 1405 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1406 DMA_FROM_DEVICE); 1407 put_page(page); 1408 cq->pool_ptrs++; 1409 return true; 1410 } 1411 return false; 1412 } 1413