1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <net/ip.h> 10 #include <net/tso.h> 11 #include <linux/bpf.h> 12 #include <linux/bpf_trace.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "otx2_txrx.h" 18 #include "otx2_ptp.h" 19 #include "cn10k.h" 20 21 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 22 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 23 struct bpf_prog *prog, 24 struct nix_cqe_rx_s *cqe, 25 struct otx2_cq_queue *cq); 26 27 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf, 28 struct otx2_cq_queue *cq) 29 { 30 u64 incr = (u64)(cq->cq_idx) << 32; 31 u64 status; 32 33 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr); 34 35 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) || 36 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) { 37 dev_err(pfvf->dev, "CQ stopped due to error"); 38 return -EINVAL; 39 } 40 41 cq->cq_tail = status & 0xFFFFF; 42 cq->cq_head = (status >> 20) & 0xFFFFF; 43 if (cq->cq_tail < cq->cq_head) 44 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) + 45 cq->cq_tail; 46 else 47 cq->pend_cqe = cq->cq_tail - cq->cq_head; 48 49 return 0; 50 } 51 52 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 53 { 54 struct nix_cqe_hdr_s *cqe_hdr; 55 56 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 57 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 58 return NULL; 59 60 cq->cq_head++; 61 cq->cq_head &= (cq->cqe_cnt - 1); 62 63 return cqe_hdr; 64 } 65 66 static unsigned int frag_num(unsigned int i) 67 { 68 #ifdef __BIG_ENDIAN 69 return (i & ~3) + 3 - (i & 3); 70 #else 71 return i; 72 #endif 73 } 74 75 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 76 struct sk_buff *skb, int seg, int *len) 77 { 78 const skb_frag_t *frag; 79 struct page *page; 80 int offset; 81 82 /* First segment is always skb->data */ 83 if (!seg) { 84 page = virt_to_page(skb->data); 85 offset = offset_in_page(skb->data); 86 *len = skb_headlen(skb); 87 } else { 88 frag = &skb_shinfo(skb)->frags[seg - 1]; 89 page = skb_frag_page(frag); 90 offset = skb_frag_off(frag); 91 *len = skb_frag_size(frag); 92 } 93 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 94 } 95 96 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 97 { 98 int seg; 99 100 for (seg = 0; seg < sg->num_segs; seg++) { 101 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 102 sg->size[seg], DMA_TO_DEVICE); 103 } 104 sg->num_segs = 0; 105 } 106 107 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf, 108 struct otx2_snd_queue *sq, 109 struct nix_cqe_tx_s *cqe) 110 { 111 struct nix_send_comp_s *snd_comp = &cqe->comp; 112 struct sg_list *sg; 113 struct page *page; 114 u64 pa; 115 116 sg = &sq->sg[snd_comp->sqe_id]; 117 118 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]); 119 otx2_dma_unmap_page(pfvf, sg->dma_addr[0], 120 sg->size[0], DMA_TO_DEVICE); 121 page = virt_to_page(phys_to_virt(pa)); 122 put_page(page); 123 } 124 125 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 126 struct otx2_cq_queue *cq, 127 struct otx2_snd_queue *sq, 128 struct nix_cqe_tx_s *cqe, 129 int budget, int *tx_pkts, int *tx_bytes) 130 { 131 struct nix_send_comp_s *snd_comp = &cqe->comp; 132 struct skb_shared_hwtstamps ts; 133 struct sk_buff *skb = NULL; 134 u64 timestamp, tsns; 135 struct sg_list *sg; 136 int err; 137 138 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 139 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 140 pfvf->netdev->name, cq->cint_idx, 141 snd_comp->status); 142 143 sg = &sq->sg[snd_comp->sqe_id]; 144 skb = (struct sk_buff *)sg->skb; 145 if (unlikely(!skb)) 146 return; 147 148 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 149 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id]; 150 if (timestamp != 1) { 151 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 152 if (!err) { 153 memset(&ts, 0, sizeof(ts)); 154 ts.hwtstamp = ns_to_ktime(tsns); 155 skb_tstamp_tx(skb, &ts); 156 } 157 } 158 } 159 160 *tx_bytes += skb->len; 161 (*tx_pkts)++; 162 otx2_dma_unmap_skb_frags(pfvf, sg); 163 napi_consume_skb(skb, budget); 164 sg->skb = (u64)NULL; 165 } 166 167 static void otx2_set_rxtstamp(struct otx2_nic *pfvf, 168 struct sk_buff *skb, void *data) 169 { 170 u64 tsns; 171 int err; 172 173 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)) 174 return; 175 176 /* The first 8 bytes is the timestamp */ 177 err = otx2_ptp_tstamp2time(pfvf, be64_to_cpu(*(__be64 *)data), &tsns); 178 if (err) 179 return; 180 181 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns); 182 } 183 184 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 185 u64 iova, int len, struct nix_rx_parse_s *parse, 186 int qidx) 187 { 188 struct page *page; 189 int off = 0; 190 void *va; 191 192 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 193 194 if (likely(!skb_shinfo(skb)->nr_frags)) { 195 /* Check if data starts at some nonzero offset 196 * from the start of the buffer. For now the 197 * only possible offset is 8 bytes in the case 198 * where packet is prepended by a timestamp. 199 */ 200 if (parse->laptr) { 201 otx2_set_rxtstamp(pfvf, skb, va); 202 off = OTX2_HW_TIMESTAMP_LEN; 203 } 204 } 205 206 page = virt_to_page(va); 207 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) { 208 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 209 va - page_address(page) + off, 210 len - off, pfvf->rbsize); 211 212 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM, 213 pfvf->rbsize, DMA_FROM_DEVICE); 214 return true; 215 } 216 217 /* If more than MAX_SKB_FRAGS fragments are received then 218 * give back those buffer pointers to hardware for reuse. 219 */ 220 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL); 221 222 return false; 223 } 224 225 static void otx2_set_rxhash(struct otx2_nic *pfvf, 226 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 227 { 228 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 229 struct otx2_rss_info *rss; 230 u32 hash = 0; 231 232 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 233 return; 234 235 rss = &pfvf->hw.rss_info; 236 if (rss->flowkey_cfg) { 237 if (rss->flowkey_cfg & 238 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 239 hash_type = PKT_HASH_TYPE_L4; 240 else 241 hash_type = PKT_HASH_TYPE_L3; 242 hash = cqe->hdr.flow_tag; 243 } 244 skb_set_hash(skb, hash, hash_type); 245 } 246 247 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe, 248 int qidx) 249 { 250 struct nix_rx_sg_s *sg = &cqe->sg; 251 void *end, *start; 252 u64 *seg_addr; 253 int seg; 254 255 start = (void *)sg; 256 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 257 while (start < end) { 258 sg = (struct nix_rx_sg_s *)start; 259 seg_addr = &sg->seg_addr; 260 for (seg = 0; seg < sg->segs; seg++, seg_addr++) 261 pfvf->hw_ops->aura_freeptr(pfvf, qidx, 262 *seg_addr & ~0x07ULL); 263 start += sizeof(*sg); 264 } 265 } 266 267 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 268 struct nix_cqe_rx_s *cqe, int qidx) 269 { 270 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 271 struct nix_rx_parse_s *parse = &cqe->parse; 272 273 if (netif_msg_rx_err(pfvf)) 274 netdev_err(pfvf->netdev, 275 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 276 qidx, parse->errlev, parse->errcode); 277 278 if (parse->errlev == NPC_ERRLVL_RE) { 279 switch (parse->errcode) { 280 case ERRCODE_FCS: 281 case ERRCODE_FCS_RCV: 282 atomic_inc(&stats->rx_fcs_errs); 283 break; 284 case ERRCODE_UNDERSIZE: 285 atomic_inc(&stats->rx_undersize_errs); 286 break; 287 case ERRCODE_OVERSIZE: 288 atomic_inc(&stats->rx_oversize_errs); 289 break; 290 case ERRCODE_OL2_LEN_MISMATCH: 291 atomic_inc(&stats->rx_len_errs); 292 break; 293 default: 294 atomic_inc(&stats->rx_other_errs); 295 break; 296 } 297 } else if (parse->errlev == NPC_ERRLVL_NIX) { 298 switch (parse->errcode) { 299 case ERRCODE_OL3_LEN: 300 case ERRCODE_OL4_LEN: 301 case ERRCODE_IL3_LEN: 302 case ERRCODE_IL4_LEN: 303 atomic_inc(&stats->rx_len_errs); 304 break; 305 case ERRCODE_OL4_CSUM: 306 case ERRCODE_IL4_CSUM: 307 atomic_inc(&stats->rx_csum_errs); 308 break; 309 default: 310 atomic_inc(&stats->rx_other_errs); 311 break; 312 } 313 } else { 314 atomic_inc(&stats->rx_other_errs); 315 /* For now ignore all the NPC parser errors and 316 * pass the packets to stack. 317 */ 318 return false; 319 } 320 321 /* If RXALL is enabled pass on packets to stack. */ 322 if (pfvf->netdev->features & NETIF_F_RXALL) 323 return false; 324 325 /* Free buffer back to pool */ 326 if (cqe->sg.segs) 327 otx2_free_rcv_seg(pfvf, cqe, qidx); 328 return true; 329 } 330 331 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 332 struct napi_struct *napi, 333 struct otx2_cq_queue *cq, 334 struct nix_cqe_rx_s *cqe) 335 { 336 struct nix_rx_parse_s *parse = &cqe->parse; 337 struct nix_rx_sg_s *sg = &cqe->sg; 338 struct sk_buff *skb = NULL; 339 void *end, *start; 340 u64 *seg_addr; 341 u16 *seg_size; 342 int seg; 343 344 if (unlikely(parse->errlev || parse->errcode)) { 345 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 346 return; 347 } 348 349 if (pfvf->xdp_prog) 350 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq)) 351 return; 352 353 skb = napi_get_frags(napi); 354 if (unlikely(!skb)) 355 return; 356 357 start = (void *)sg; 358 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 359 while (start < end) { 360 sg = (struct nix_rx_sg_s *)start; 361 seg_addr = &sg->seg_addr; 362 seg_size = (void *)sg; 363 for (seg = 0; seg < sg->segs; seg++, seg_addr++) { 364 if (otx2_skb_add_frag(pfvf, skb, *seg_addr, 365 seg_size[seg], parse, cq->cq_idx)) 366 cq->pool_ptrs++; 367 } 368 start += sizeof(*sg); 369 } 370 otx2_set_rxhash(pfvf, cqe, skb); 371 372 skb_record_rx_queue(skb, cq->cq_idx); 373 if (pfvf->netdev->features & NETIF_F_RXCSUM) 374 skb->ip_summed = CHECKSUM_UNNECESSARY; 375 376 napi_gro_frags(napi); 377 } 378 379 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 380 struct napi_struct *napi, 381 struct otx2_cq_queue *cq, int budget) 382 { 383 struct nix_cqe_rx_s *cqe; 384 int processed_cqe = 0; 385 386 if (cq->pend_cqe >= budget) 387 goto process_cqe; 388 389 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 390 return 0; 391 392 process_cqe: 393 while (likely(processed_cqe < budget) && cq->pend_cqe) { 394 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 395 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 396 !cqe->sg.seg_addr) { 397 if (!processed_cqe) 398 return 0; 399 break; 400 } 401 cq->cq_head++; 402 cq->cq_head &= (cq->cqe_cnt - 1); 403 404 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 405 406 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 407 cqe->sg.seg_addr = 0x00; 408 processed_cqe++; 409 cq->pend_cqe--; 410 } 411 412 /* Free CQEs to HW */ 413 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 414 ((u64)cq->cq_idx << 32) | processed_cqe); 415 416 return processed_cqe; 417 } 418 419 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 420 { 421 struct otx2_nic *pfvf = dev; 422 dma_addr_t bufptr; 423 424 while (cq->pool_ptrs) { 425 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) 426 break; 427 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 428 cq->pool_ptrs--; 429 } 430 } 431 432 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 433 struct otx2_cq_queue *cq, int budget) 434 { 435 int tx_pkts = 0, tx_bytes = 0, qidx; 436 struct nix_cqe_tx_s *cqe; 437 int processed_cqe = 0; 438 439 if (cq->pend_cqe >= budget) 440 goto process_cqe; 441 442 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 443 return 0; 444 445 process_cqe: 446 while (likely(processed_cqe < budget) && cq->pend_cqe) { 447 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 448 if (unlikely(!cqe)) { 449 if (!processed_cqe) 450 return 0; 451 break; 452 } 453 if (cq->cq_type == CQ_XDP) { 454 qidx = cq->cq_idx - pfvf->hw.rx_queues; 455 otx2_xdp_snd_pkt_handler(pfvf, &pfvf->qset.sq[qidx], 456 cqe); 457 } else { 458 otx2_snd_pkt_handler(pfvf, cq, 459 &pfvf->qset.sq[cq->cint_idx], 460 cqe, budget, &tx_pkts, &tx_bytes); 461 } 462 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 463 processed_cqe++; 464 cq->pend_cqe--; 465 } 466 467 /* Free CQEs to HW */ 468 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 469 ((u64)cq->cq_idx << 32) | processed_cqe); 470 471 if (likely(tx_pkts)) { 472 struct netdev_queue *txq; 473 474 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx); 475 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 476 /* Check if queue was stopped earlier due to ring full */ 477 smp_mb(); 478 if (netif_tx_queue_stopped(txq) && 479 netif_carrier_ok(pfvf->netdev)) 480 netif_tx_wake_queue(txq); 481 } 482 return 0; 483 } 484 485 int otx2_napi_handler(struct napi_struct *napi, int budget) 486 { 487 struct otx2_cq_queue *rx_cq = NULL; 488 struct otx2_cq_poll *cq_poll; 489 int workdone = 0, cq_idx, i; 490 struct otx2_cq_queue *cq; 491 struct otx2_qset *qset; 492 struct otx2_nic *pfvf; 493 494 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 495 pfvf = (struct otx2_nic *)cq_poll->dev; 496 qset = &pfvf->qset; 497 498 for (i = 0; i < CQS_PER_CINT; i++) { 499 cq_idx = cq_poll->cq_ids[i]; 500 if (unlikely(cq_idx == CINT_INVALID_CQ)) 501 continue; 502 cq = &qset->cq[cq_idx]; 503 if (cq->cq_type == CQ_RX) { 504 rx_cq = cq; 505 workdone += otx2_rx_napi_handler(pfvf, napi, 506 cq, budget); 507 } else { 508 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 509 } 510 } 511 512 if (rx_cq && rx_cq->pool_ptrs) 513 pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq); 514 /* Clear the IRQ */ 515 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 516 517 if (workdone < budget && napi_complete_done(napi, workdone)) { 518 /* If interface is going down, don't re-enable IRQ */ 519 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 520 return workdone; 521 522 /* Re-enable interrupts */ 523 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 524 BIT_ULL(0)); 525 } 526 return workdone; 527 } 528 529 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 530 int size, int qidx) 531 { 532 u64 status; 533 534 /* Packet data stores should finish before SQE is flushed to HW */ 535 dma_wmb(); 536 537 do { 538 memcpy(sq->lmt_addr, sq->sqe_base, size); 539 status = otx2_lmt_flush(sq->io_addr); 540 } while (status == 0); 541 542 sq->head++; 543 sq->head &= (sq->sqe_cnt - 1); 544 } 545 546 #define MAX_SEGS_PER_SG 3 547 /* Add SQE scatter/gather subdescriptor structure */ 548 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 549 struct sk_buff *skb, int num_segs, int *offset) 550 { 551 struct nix_sqe_sg_s *sg = NULL; 552 u64 dma_addr, *iova = NULL; 553 u16 *sg_lens = NULL; 554 int seg, len; 555 556 sq->sg[sq->head].num_segs = 0; 557 558 for (seg = 0; seg < num_segs; seg++) { 559 if ((seg % MAX_SEGS_PER_SG) == 0) { 560 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 561 sg->ld_type = NIX_SEND_LDTYPE_LDD; 562 sg->subdc = NIX_SUBDC_SG; 563 sg->segs = 0; 564 sg_lens = (void *)sg; 565 iova = (void *)sg + sizeof(*sg); 566 /* Next subdc always starts at a 16byte boundary. 567 * So if sg->segs is whether 2 or 3, offset += 16bytes. 568 */ 569 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 570 *offset += sizeof(*sg) + (3 * sizeof(u64)); 571 else 572 *offset += sizeof(*sg) + sizeof(u64); 573 } 574 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 575 if (dma_mapping_error(pfvf->dev, dma_addr)) 576 return false; 577 578 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 579 sg->segs++; 580 *iova++ = dma_addr; 581 582 /* Save DMA mapping info for later unmapping */ 583 sq->sg[sq->head].dma_addr[seg] = dma_addr; 584 sq->sg[sq->head].size[seg] = len; 585 sq->sg[sq->head].num_segs++; 586 } 587 588 sq->sg[sq->head].skb = (u64)skb; 589 return true; 590 } 591 592 /* Add SQE extended header subdescriptor */ 593 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 594 struct sk_buff *skb, int *offset) 595 { 596 struct nix_sqe_ext_s *ext; 597 598 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 599 ext->subdc = NIX_SUBDC_EXT; 600 if (skb_shinfo(skb)->gso_size) { 601 ext->lso = 1; 602 ext->lso_sb = skb_transport_offset(skb) + tcp_hdrlen(skb); 603 ext->lso_mps = skb_shinfo(skb)->gso_size; 604 605 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 606 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 607 ext->lso_format = pfvf->hw.lso_tsov4_idx; 608 609 /* HW adds payload size to 'ip_hdr->tot_len' while 610 * sending TSO segment, hence set payload length 611 * in IP header of the packet to just header length. 612 */ 613 ip_hdr(skb)->tot_len = 614 htons(ext->lso_sb - skb_network_offset(skb)); 615 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 616 ext->lso_format = pfvf->hw.lso_tsov6_idx; 617 618 ipv6_hdr(skb)->payload_len = 619 htons(ext->lso_sb - skb_network_offset(skb)); 620 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 621 __be16 l3_proto = vlan_get_protocol(skb); 622 struct udphdr *udph = udp_hdr(skb); 623 u16 iplen; 624 625 ext->lso_sb = skb_transport_offset(skb) + 626 sizeof(struct udphdr); 627 628 /* HW adds payload size to length fields in IP and 629 * UDP headers while segmentation, hence adjust the 630 * lengths to just header sizes. 631 */ 632 iplen = htons(ext->lso_sb - skb_network_offset(skb)); 633 if (l3_proto == htons(ETH_P_IP)) { 634 ip_hdr(skb)->tot_len = iplen; 635 ext->lso_format = pfvf->hw.lso_udpv4_idx; 636 } else { 637 ipv6_hdr(skb)->payload_len = iplen; 638 ext->lso_format = pfvf->hw.lso_udpv6_idx; 639 } 640 641 udph->len = htons(sizeof(struct udphdr)); 642 } 643 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 644 ext->tstmp = 1; 645 } 646 647 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN) 648 if (skb_vlan_tag_present(skb)) { 649 if (skb->vlan_proto == htons(ETH_P_8021Q)) { 650 ext->vlan1_ins_ena = 1; 651 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET; 652 ext->vlan1_ins_tci = skb_vlan_tag_get(skb); 653 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) { 654 ext->vlan0_ins_ena = 1; 655 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET; 656 ext->vlan0_ins_tci = skb_vlan_tag_get(skb); 657 } 658 } 659 660 *offset += sizeof(*ext); 661 } 662 663 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset, 664 int alg, u64 iova) 665 { 666 struct nix_sqe_mem_s *mem; 667 668 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset); 669 mem->subdc = NIX_SUBDC_MEM; 670 mem->alg = alg; 671 mem->wmem = 1; /* wait for the memory operation */ 672 mem->addr = iova; 673 674 *offset += sizeof(*mem); 675 } 676 677 /* Add SQE header subdescriptor structure */ 678 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 679 struct nix_sqe_hdr_s *sqe_hdr, 680 struct sk_buff *skb, u16 qidx) 681 { 682 int proto = 0; 683 684 /* Check if SQE was framed before, if yes then no need to 685 * set these constants again and again. 686 */ 687 if (!sqe_hdr->total) { 688 /* Don't free Tx buffers to Aura */ 689 sqe_hdr->df = 1; 690 sqe_hdr->aura = sq->aura_id; 691 /* Post a CQE Tx after pkt transmission */ 692 sqe_hdr->pnc = 1; 693 sqe_hdr->sq = qidx; 694 } 695 sqe_hdr->total = skb->len; 696 /* Set SQE identifier which will be used later for freeing SKB */ 697 sqe_hdr->sqe_id = sq->head; 698 699 /* Offload TCP/UDP checksum to HW */ 700 if (skb->ip_summed == CHECKSUM_PARTIAL) { 701 sqe_hdr->ol3ptr = skb_network_offset(skb); 702 sqe_hdr->ol4ptr = skb_transport_offset(skb); 703 /* get vlan protocol Ethertype */ 704 if (eth_type_vlan(skb->protocol)) 705 skb->protocol = vlan_get_protocol(skb); 706 707 if (skb->protocol == htons(ETH_P_IP)) { 708 proto = ip_hdr(skb)->protocol; 709 /* In case of TSO, HW needs this to be explicitly set. 710 * So set this always, instead of adding a check. 711 */ 712 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 713 } else if (skb->protocol == htons(ETH_P_IPV6)) { 714 proto = ipv6_hdr(skb)->nexthdr; 715 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6; 716 } 717 718 if (proto == IPPROTO_TCP) 719 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 720 else if (proto == IPPROTO_UDP) 721 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 722 } 723 } 724 725 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 726 struct otx2_snd_queue *sq, 727 struct sk_buff *skb, int sqe, int hdr_len) 728 { 729 int num_segs = skb_shinfo(skb)->nr_frags + 1; 730 struct sg_list *sg = &sq->sg[sqe]; 731 u64 dma_addr; 732 int seg, len; 733 734 sg->num_segs = 0; 735 736 /* Get payload length at skb->data */ 737 len = skb_headlen(skb) - hdr_len; 738 739 for (seg = 0; seg < num_segs; seg++) { 740 /* Skip skb->data, if there is no payload */ 741 if (!seg && !len) 742 continue; 743 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 744 if (dma_mapping_error(pfvf->dev, dma_addr)) 745 goto unmap; 746 747 /* Save DMA mapping info for later unmapping */ 748 sg->dma_addr[sg->num_segs] = dma_addr; 749 sg->size[sg->num_segs] = len; 750 sg->num_segs++; 751 } 752 return 0; 753 unmap: 754 otx2_dma_unmap_skb_frags(pfvf, sg); 755 return -EINVAL; 756 } 757 758 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 759 struct sk_buff *skb, int seg, 760 u64 seg_addr, int hdr_len, int sqe) 761 { 762 struct sg_list *sg = &sq->sg[sqe]; 763 const skb_frag_t *frag; 764 int offset; 765 766 if (seg < 0) 767 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 768 769 frag = &skb_shinfo(skb)->frags[seg]; 770 offset = seg_addr - (u64)skb_frag_address(frag); 771 if (skb_headlen(skb) - hdr_len) 772 seg++; 773 return sg->dma_addr[seg] + offset; 774 } 775 776 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 777 struct sg_list *list, int *offset) 778 { 779 struct nix_sqe_sg_s *sg = NULL; 780 u16 *sg_lens = NULL; 781 u64 *iova = NULL; 782 int seg; 783 784 /* Add SG descriptors with buffer addresses */ 785 for (seg = 0; seg < list->num_segs; seg++) { 786 if ((seg % MAX_SEGS_PER_SG) == 0) { 787 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 788 sg->ld_type = NIX_SEND_LDTYPE_LDD; 789 sg->subdc = NIX_SUBDC_SG; 790 sg->segs = 0; 791 sg_lens = (void *)sg; 792 iova = (void *)sg + sizeof(*sg); 793 /* Next subdc always starts at a 16byte boundary. 794 * So if sg->segs is whether 2 or 3, offset += 16bytes. 795 */ 796 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 797 *offset += sizeof(*sg) + (3 * sizeof(u64)); 798 else 799 *offset += sizeof(*sg) + sizeof(u64); 800 } 801 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 802 *iova++ = list->dma_addr[seg]; 803 sg->segs++; 804 } 805 } 806 807 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 808 struct sk_buff *skb, u16 qidx) 809 { 810 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 811 int hdr_len, tcp_data, seg_len, pkt_len, offset; 812 struct nix_sqe_hdr_s *sqe_hdr; 813 int first_sqe = sq->head; 814 struct sg_list list; 815 struct tso_t tso; 816 817 hdr_len = tso_start(skb, &tso); 818 819 /* Map SKB's fragments to DMA. 820 * It's done here to avoid mapping for every TSO segment's packet. 821 */ 822 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 823 dev_kfree_skb_any(skb); 824 return; 825 } 826 827 netdev_tx_sent_queue(txq, skb->len); 828 829 tcp_data = skb->len - hdr_len; 830 while (tcp_data > 0) { 831 char *hdr; 832 833 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 834 tcp_data -= seg_len; 835 836 /* Set SQE's SEND_HDR */ 837 memset(sq->sqe_base, 0, sq->sqe_size); 838 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 839 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 840 offset = sizeof(*sqe_hdr); 841 842 /* Add TSO segment's pkt header */ 843 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 844 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 845 list.dma_addr[0] = 846 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 847 list.size[0] = hdr_len; 848 list.num_segs = 1; 849 850 /* Add TSO segment's payload data fragments */ 851 pkt_len = hdr_len; 852 while (seg_len > 0) { 853 int size; 854 855 size = min_t(int, tso.size, seg_len); 856 857 list.size[list.num_segs] = size; 858 list.dma_addr[list.num_segs] = 859 otx2_tso_frag_dma_addr(sq, skb, 860 tso.next_frag_idx - 1, 861 (u64)tso.data, hdr_len, 862 first_sqe); 863 list.num_segs++; 864 pkt_len += size; 865 seg_len -= size; 866 tso_build_data(skb, &tso, size); 867 } 868 sqe_hdr->total = pkt_len; 869 otx2_sqe_tso_add_sg(sq, &list, &offset); 870 871 /* DMA mappings and skb needs to be freed only after last 872 * TSO segment is transmitted out. So set 'PNC' only for 873 * last segment. Also point last segment's sqe_id to first 874 * segment's SQE index where skb address and DMA mappings 875 * are saved. 876 */ 877 if (!tcp_data) { 878 sqe_hdr->pnc = 1; 879 sqe_hdr->sqe_id = first_sqe; 880 sq->sg[first_sqe].skb = (u64)skb; 881 } else { 882 sqe_hdr->pnc = 0; 883 } 884 885 sqe_hdr->sizem1 = (offset / 16) - 1; 886 887 /* Flush SQE to HW */ 888 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 889 } 890 } 891 892 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 893 struct sk_buff *skb) 894 { 895 int payload_len, last_seg_size; 896 897 if (test_bit(HW_TSO, &pfvf->hw.cap_flag)) 898 return true; 899 900 /* On 96xx A0, HW TSO not supported */ 901 if (!is_96xx_B0(pfvf->pdev)) 902 return false; 903 904 /* HW has an issue due to which when the payload of the last LSO 905 * segment is shorter than 16 bytes, some header fields may not 906 * be correctly modified, hence don't offload such TSO segments. 907 */ 908 909 payload_len = skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb)); 910 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 911 if (last_seg_size && last_seg_size < 16) 912 return false; 913 914 return true; 915 } 916 917 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 918 { 919 if (!skb_shinfo(skb)->gso_size) 920 return 1; 921 922 /* HW TSO */ 923 if (is_hw_tso_supported(pfvf, skb)) 924 return 1; 925 926 /* SW TSO */ 927 return skb_shinfo(skb)->gso_segs; 928 } 929 930 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb, 931 struct otx2_snd_queue *sq, int *offset) 932 { 933 u64 iova; 934 935 if (!skb_shinfo(skb)->gso_size && 936 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 937 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 938 iova = sq->timestamps->iova + (sq->head * sizeof(u64)); 939 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova); 940 } else { 941 skb_tx_timestamp(skb); 942 } 943 } 944 945 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 946 struct sk_buff *skb, u16 qidx) 947 { 948 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 949 struct otx2_nic *pfvf = netdev_priv(netdev); 950 int offset, num_segs, free_sqe; 951 struct nix_sqe_hdr_s *sqe_hdr; 952 953 /* Check if there is room for new SQE. 954 * 'Num of SQBs freed to SQ's pool - SQ's Aura count' 955 * will give free SQE count. 956 */ 957 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 958 959 if (free_sqe < sq->sqe_thresh || 960 free_sqe < otx2_get_sqe_count(pfvf, skb)) 961 return false; 962 963 num_segs = skb_shinfo(skb)->nr_frags + 1; 964 965 /* If SKB doesn't fit in a single SQE, linearize it. 966 * TODO: Consider adding JUMP descriptor instead. 967 */ 968 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 969 if (__skb_linearize(skb)) { 970 dev_kfree_skb_any(skb); 971 return true; 972 } 973 num_segs = skb_shinfo(skb)->nr_frags + 1; 974 } 975 976 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 977 /* Insert vlan tag before giving pkt to tso */ 978 if (skb_vlan_tag_present(skb)) 979 skb = __vlan_hwaccel_push_inside(skb); 980 otx2_sq_append_tso(pfvf, sq, skb, qidx); 981 return true; 982 } 983 984 /* Set SQE's SEND_HDR. 985 * Do not clear the first 64bit as it contains constant info. 986 */ 987 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 988 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 989 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 990 offset = sizeof(*sqe_hdr); 991 992 /* Add extended header if needed */ 993 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 994 995 /* Add SG subdesc with data frags */ 996 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 997 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 998 return false; 999 } 1000 1001 otx2_set_txtstamp(pfvf, skb, sq, &offset); 1002 1003 sqe_hdr->sizem1 = (offset / 16) - 1; 1004 1005 netdev_tx_sent_queue(txq, skb->len); 1006 1007 /* Flush SQE to HW */ 1008 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1009 1010 return true; 1011 } 1012 EXPORT_SYMBOL(otx2_sq_append_skb); 1013 1014 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1015 { 1016 struct nix_cqe_rx_s *cqe; 1017 int processed_cqe = 0; 1018 u64 iova, pa; 1019 1020 if (pfvf->xdp_prog) 1021 xdp_rxq_info_unreg(&cq->xdp_rxq); 1022 1023 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1024 return; 1025 1026 while (cq->pend_cqe) { 1027 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq); 1028 processed_cqe++; 1029 cq->pend_cqe--; 1030 1031 if (!cqe) 1032 continue; 1033 if (cqe->sg.segs > 1) { 1034 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx); 1035 continue; 1036 } 1037 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1038 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1039 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); 1040 put_page(virt_to_page(phys_to_virt(pa))); 1041 } 1042 1043 /* Free CQEs to HW */ 1044 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1045 ((u64)cq->cq_idx << 32) | processed_cqe); 1046 } 1047 1048 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1049 { 1050 struct sk_buff *skb = NULL; 1051 struct otx2_snd_queue *sq; 1052 struct nix_cqe_tx_s *cqe; 1053 int processed_cqe = 0; 1054 struct sg_list *sg; 1055 1056 sq = &pfvf->qset.sq[cq->cint_idx]; 1057 1058 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1059 return; 1060 1061 while (cq->pend_cqe) { 1062 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 1063 processed_cqe++; 1064 cq->pend_cqe--; 1065 1066 if (!cqe) 1067 continue; 1068 sg = &sq->sg[cqe->comp.sqe_id]; 1069 skb = (struct sk_buff *)sg->skb; 1070 if (skb) { 1071 otx2_dma_unmap_skb_frags(pfvf, sg); 1072 dev_kfree_skb_any(skb); 1073 sg->skb = (u64)NULL; 1074 } 1075 } 1076 1077 /* Free CQEs to HW */ 1078 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1079 ((u64)cq->cq_idx << 32) | processed_cqe); 1080 } 1081 1082 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 1083 { 1084 struct msg_req *msg; 1085 int err; 1086 1087 mutex_lock(&pfvf->mbox.lock); 1088 if (enable) 1089 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 1090 else 1091 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 1092 1093 if (!msg) { 1094 mutex_unlock(&pfvf->mbox.lock); 1095 return -ENOMEM; 1096 } 1097 1098 err = otx2_sync_mbox_msg(&pfvf->mbox); 1099 mutex_unlock(&pfvf->mbox.lock); 1100 return err; 1101 } 1102 1103 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr, 1104 int len, int *offset) 1105 { 1106 struct nix_sqe_sg_s *sg = NULL; 1107 u64 *iova = NULL; 1108 1109 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 1110 sg->ld_type = NIX_SEND_LDTYPE_LDD; 1111 sg->subdc = NIX_SUBDC_SG; 1112 sg->segs = 1; 1113 sg->seg1_size = len; 1114 iova = (void *)sg + sizeof(*sg); 1115 *iova = dma_addr; 1116 *offset += sizeof(*sg) + sizeof(u64); 1117 1118 sq->sg[sq->head].dma_addr[0] = dma_addr; 1119 sq->sg[sq->head].size[0] = len; 1120 sq->sg[sq->head].num_segs = 1; 1121 } 1122 1123 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx) 1124 { 1125 struct nix_sqe_hdr_s *sqe_hdr; 1126 struct otx2_snd_queue *sq; 1127 int offset, free_sqe; 1128 1129 sq = &pfvf->qset.sq[qidx]; 1130 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 1131 if (free_sqe < sq->sqe_thresh) 1132 return false; 1133 1134 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1135 1136 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1137 1138 if (!sqe_hdr->total) { 1139 sqe_hdr->aura = sq->aura_id; 1140 sqe_hdr->df = 1; 1141 sqe_hdr->sq = qidx; 1142 sqe_hdr->pnc = 1; 1143 } 1144 sqe_hdr->total = len; 1145 sqe_hdr->sqe_id = sq->head; 1146 1147 offset = sizeof(*sqe_hdr); 1148 1149 otx2_xdp_sqe_add_sg(sq, iova, len, &offset); 1150 sqe_hdr->sizem1 = (offset / 16) - 1; 1151 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1152 1153 return true; 1154 } 1155 1156 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 1157 struct bpf_prog *prog, 1158 struct nix_cqe_rx_s *cqe, 1159 struct otx2_cq_queue *cq) 1160 { 1161 unsigned char *hard_start, *data; 1162 int qidx = cq->cq_idx; 1163 struct xdp_buff xdp; 1164 struct page *page; 1165 u64 iova, pa; 1166 u32 act; 1167 int err; 1168 1169 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1170 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1171 page = virt_to_page(phys_to_virt(pa)); 1172 1173 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq); 1174 1175 data = (unsigned char *)phys_to_virt(pa); 1176 hard_start = page_address(page); 1177 xdp_prepare_buff(&xdp, hard_start, data - hard_start, 1178 cqe->sg.seg_size, false); 1179 1180 act = bpf_prog_run_xdp(prog, &xdp); 1181 1182 switch (act) { 1183 case XDP_PASS: 1184 break; 1185 case XDP_TX: 1186 qidx += pfvf->hw.tx_queues; 1187 cq->pool_ptrs++; 1188 return otx2_xdp_sq_append_pkt(pfvf, iova, 1189 cqe->sg.seg_size, qidx); 1190 case XDP_REDIRECT: 1191 cq->pool_ptrs++; 1192 err = xdp_do_redirect(pfvf->netdev, &xdp, prog); 1193 1194 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1195 DMA_FROM_DEVICE); 1196 if (!err) 1197 return true; 1198 put_page(page); 1199 break; 1200 default: 1201 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act); 1202 break; 1203 case XDP_ABORTED: 1204 trace_xdp_exception(pfvf->netdev, prog, act); 1205 break; 1206 case XDP_DROP: 1207 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1208 DMA_FROM_DEVICE); 1209 put_page(page); 1210 cq->pool_ptrs++; 1211 return true; 1212 } 1213 return false; 1214 } 1215