1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <net/ip.h> 10 #include <net/tso.h> 11 #include <linux/bpf.h> 12 #include <linux/bpf_trace.h> 13 14 #include "otx2_reg.h" 15 #include "otx2_common.h" 16 #include "otx2_struct.h" 17 #include "otx2_txrx.h" 18 #include "otx2_ptp.h" 19 #include "cn10k.h" 20 21 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 22 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 23 struct bpf_prog *prog, 24 struct nix_cqe_rx_s *cqe, 25 struct otx2_cq_queue *cq); 26 27 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf, 28 struct otx2_cq_queue *cq) 29 { 30 u64 incr = (u64)(cq->cq_idx) << 32; 31 u64 status; 32 33 status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr); 34 35 if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) || 36 status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) { 37 dev_err(pfvf->dev, "CQ stopped due to error"); 38 return -EINVAL; 39 } 40 41 cq->cq_tail = status & 0xFFFFF; 42 cq->cq_head = (status >> 20) & 0xFFFFF; 43 if (cq->cq_tail < cq->cq_head) 44 cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) + 45 cq->cq_tail; 46 else 47 cq->pend_cqe = cq->cq_tail - cq->cq_head; 48 49 return 0; 50 } 51 52 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 53 { 54 struct nix_cqe_hdr_s *cqe_hdr; 55 56 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 57 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 58 return NULL; 59 60 cq->cq_head++; 61 cq->cq_head &= (cq->cqe_cnt - 1); 62 63 return cqe_hdr; 64 } 65 66 static unsigned int frag_num(unsigned int i) 67 { 68 #ifdef __BIG_ENDIAN 69 return (i & ~3) + 3 - (i & 3); 70 #else 71 return i; 72 #endif 73 } 74 75 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 76 struct sk_buff *skb, int seg, int *len) 77 { 78 const skb_frag_t *frag; 79 struct page *page; 80 int offset; 81 82 /* First segment is always skb->data */ 83 if (!seg) { 84 page = virt_to_page(skb->data); 85 offset = offset_in_page(skb->data); 86 *len = skb_headlen(skb); 87 } else { 88 frag = &skb_shinfo(skb)->frags[seg - 1]; 89 page = skb_frag_page(frag); 90 offset = skb_frag_off(frag); 91 *len = skb_frag_size(frag); 92 } 93 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 94 } 95 96 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 97 { 98 int seg; 99 100 for (seg = 0; seg < sg->num_segs; seg++) { 101 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 102 sg->size[seg], DMA_TO_DEVICE); 103 } 104 sg->num_segs = 0; 105 } 106 107 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf, 108 struct otx2_snd_queue *sq, 109 struct nix_cqe_tx_s *cqe) 110 { 111 struct nix_send_comp_s *snd_comp = &cqe->comp; 112 struct sg_list *sg; 113 struct page *page; 114 u64 pa; 115 116 sg = &sq->sg[snd_comp->sqe_id]; 117 118 pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]); 119 otx2_dma_unmap_page(pfvf, sg->dma_addr[0], 120 sg->size[0], DMA_TO_DEVICE); 121 page = virt_to_page(phys_to_virt(pa)); 122 put_page(page); 123 } 124 125 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 126 struct otx2_cq_queue *cq, 127 struct otx2_snd_queue *sq, 128 struct nix_cqe_tx_s *cqe, 129 int budget, int *tx_pkts, int *tx_bytes) 130 { 131 struct nix_send_comp_s *snd_comp = &cqe->comp; 132 struct skb_shared_hwtstamps ts; 133 struct sk_buff *skb = NULL; 134 u64 timestamp, tsns; 135 struct sg_list *sg; 136 int err; 137 138 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 139 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 140 pfvf->netdev->name, cq->cint_idx, 141 snd_comp->status); 142 143 sg = &sq->sg[snd_comp->sqe_id]; 144 skb = (struct sk_buff *)sg->skb; 145 if (unlikely(!skb)) 146 return; 147 148 if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) { 149 timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id]; 150 if (timestamp != 1) { 151 timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp); 152 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 153 if (!err) { 154 memset(&ts, 0, sizeof(ts)); 155 ts.hwtstamp = ns_to_ktime(tsns); 156 skb_tstamp_tx(skb, &ts); 157 } 158 } 159 } 160 161 *tx_bytes += skb->len; 162 (*tx_pkts)++; 163 otx2_dma_unmap_skb_frags(pfvf, sg); 164 napi_consume_skb(skb, budget); 165 sg->skb = (u64)NULL; 166 } 167 168 static void otx2_set_rxtstamp(struct otx2_nic *pfvf, 169 struct sk_buff *skb, void *data) 170 { 171 u64 timestamp, tsns; 172 int err; 173 174 if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED)) 175 return; 176 177 timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data); 178 /* The first 8 bytes is the timestamp */ 179 err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns); 180 if (err) 181 return; 182 183 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns); 184 } 185 186 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 187 u64 iova, int len, struct nix_rx_parse_s *parse, 188 int qidx) 189 { 190 struct page *page; 191 int off = 0; 192 void *va; 193 194 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 195 196 if (likely(!skb_shinfo(skb)->nr_frags)) { 197 /* Check if data starts at some nonzero offset 198 * from the start of the buffer. For now the 199 * only possible offset is 8 bytes in the case 200 * where packet is prepended by a timestamp. 201 */ 202 if (parse->laptr) { 203 otx2_set_rxtstamp(pfvf, skb, va); 204 off = OTX2_HW_TIMESTAMP_LEN; 205 } 206 } 207 208 page = virt_to_page(va); 209 if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) { 210 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 211 va - page_address(page) + off, 212 len - off, pfvf->rbsize); 213 214 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM, 215 pfvf->rbsize, DMA_FROM_DEVICE); 216 return true; 217 } 218 219 /* If more than MAX_SKB_FRAGS fragments are received then 220 * give back those buffer pointers to hardware for reuse. 221 */ 222 pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL); 223 224 return false; 225 } 226 227 static void otx2_set_rxhash(struct otx2_nic *pfvf, 228 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 229 { 230 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 231 struct otx2_rss_info *rss; 232 u32 hash = 0; 233 234 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 235 return; 236 237 rss = &pfvf->hw.rss_info; 238 if (rss->flowkey_cfg) { 239 if (rss->flowkey_cfg & 240 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 241 hash_type = PKT_HASH_TYPE_L4; 242 else 243 hash_type = PKT_HASH_TYPE_L3; 244 hash = cqe->hdr.flow_tag; 245 } 246 skb_set_hash(skb, hash, hash_type); 247 } 248 249 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe, 250 int qidx) 251 { 252 struct nix_rx_sg_s *sg = &cqe->sg; 253 void *end, *start; 254 u64 *seg_addr; 255 int seg; 256 257 start = (void *)sg; 258 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 259 while (start < end) { 260 sg = (struct nix_rx_sg_s *)start; 261 seg_addr = &sg->seg_addr; 262 for (seg = 0; seg < sg->segs; seg++, seg_addr++) 263 pfvf->hw_ops->aura_freeptr(pfvf, qidx, 264 *seg_addr & ~0x07ULL); 265 start += sizeof(*sg); 266 } 267 } 268 269 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 270 struct nix_cqe_rx_s *cqe, int qidx) 271 { 272 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 273 struct nix_rx_parse_s *parse = &cqe->parse; 274 275 if (netif_msg_rx_err(pfvf)) 276 netdev_err(pfvf->netdev, 277 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 278 qidx, parse->errlev, parse->errcode); 279 280 if (parse->errlev == NPC_ERRLVL_RE) { 281 switch (parse->errcode) { 282 case ERRCODE_FCS: 283 case ERRCODE_FCS_RCV: 284 atomic_inc(&stats->rx_fcs_errs); 285 break; 286 case ERRCODE_UNDERSIZE: 287 atomic_inc(&stats->rx_undersize_errs); 288 break; 289 case ERRCODE_OVERSIZE: 290 atomic_inc(&stats->rx_oversize_errs); 291 break; 292 case ERRCODE_OL2_LEN_MISMATCH: 293 atomic_inc(&stats->rx_len_errs); 294 break; 295 default: 296 atomic_inc(&stats->rx_other_errs); 297 break; 298 } 299 } else if (parse->errlev == NPC_ERRLVL_NIX) { 300 switch (parse->errcode) { 301 case ERRCODE_OL3_LEN: 302 case ERRCODE_OL4_LEN: 303 case ERRCODE_IL3_LEN: 304 case ERRCODE_IL4_LEN: 305 atomic_inc(&stats->rx_len_errs); 306 break; 307 case ERRCODE_OL4_CSUM: 308 case ERRCODE_IL4_CSUM: 309 atomic_inc(&stats->rx_csum_errs); 310 break; 311 default: 312 atomic_inc(&stats->rx_other_errs); 313 break; 314 } 315 } else { 316 atomic_inc(&stats->rx_other_errs); 317 /* For now ignore all the NPC parser errors and 318 * pass the packets to stack. 319 */ 320 return false; 321 } 322 323 /* If RXALL is enabled pass on packets to stack. */ 324 if (pfvf->netdev->features & NETIF_F_RXALL) 325 return false; 326 327 /* Free buffer back to pool */ 328 if (cqe->sg.segs) 329 otx2_free_rcv_seg(pfvf, cqe, qidx); 330 return true; 331 } 332 333 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 334 struct napi_struct *napi, 335 struct otx2_cq_queue *cq, 336 struct nix_cqe_rx_s *cqe) 337 { 338 struct nix_rx_parse_s *parse = &cqe->parse; 339 struct nix_rx_sg_s *sg = &cqe->sg; 340 struct sk_buff *skb = NULL; 341 void *end, *start; 342 u64 *seg_addr; 343 u16 *seg_size; 344 int seg; 345 346 if (unlikely(parse->errlev || parse->errcode)) { 347 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 348 return; 349 } 350 351 if (pfvf->xdp_prog) 352 if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq)) 353 return; 354 355 skb = napi_get_frags(napi); 356 if (unlikely(!skb)) 357 return; 358 359 start = (void *)sg; 360 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 361 while (start < end) { 362 sg = (struct nix_rx_sg_s *)start; 363 seg_addr = &sg->seg_addr; 364 seg_size = (void *)sg; 365 for (seg = 0; seg < sg->segs; seg++, seg_addr++) { 366 if (otx2_skb_add_frag(pfvf, skb, *seg_addr, 367 seg_size[seg], parse, cq->cq_idx)) 368 cq->pool_ptrs++; 369 } 370 start += sizeof(*sg); 371 } 372 otx2_set_rxhash(pfvf, cqe, skb); 373 374 skb_record_rx_queue(skb, cq->cq_idx); 375 if (pfvf->netdev->features & NETIF_F_RXCSUM) 376 skb->ip_summed = CHECKSUM_UNNECESSARY; 377 378 napi_gro_frags(napi); 379 } 380 381 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 382 struct napi_struct *napi, 383 struct otx2_cq_queue *cq, int budget) 384 { 385 struct nix_cqe_rx_s *cqe; 386 int processed_cqe = 0; 387 388 if (cq->pend_cqe >= budget) 389 goto process_cqe; 390 391 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 392 return 0; 393 394 process_cqe: 395 while (likely(processed_cqe < budget) && cq->pend_cqe) { 396 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 397 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 398 !cqe->sg.seg_addr) { 399 if (!processed_cqe) 400 return 0; 401 break; 402 } 403 cq->cq_head++; 404 cq->cq_head &= (cq->cqe_cnt - 1); 405 406 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 407 408 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 409 cqe->sg.seg_addr = 0x00; 410 processed_cqe++; 411 cq->pend_cqe--; 412 } 413 414 /* Free CQEs to HW */ 415 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 416 ((u64)cq->cq_idx << 32) | processed_cqe); 417 418 return processed_cqe; 419 } 420 421 void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) 422 { 423 struct otx2_nic *pfvf = dev; 424 dma_addr_t bufptr; 425 426 while (cq->pool_ptrs) { 427 if (otx2_alloc_buffer(pfvf, cq, &bufptr)) 428 break; 429 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 430 cq->pool_ptrs--; 431 } 432 } 433 434 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 435 struct otx2_cq_queue *cq, int budget) 436 { 437 int tx_pkts = 0, tx_bytes = 0, qidx; 438 struct nix_cqe_tx_s *cqe; 439 int processed_cqe = 0; 440 441 if (cq->pend_cqe >= budget) 442 goto process_cqe; 443 444 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 445 return 0; 446 447 process_cqe: 448 while (likely(processed_cqe < budget) && cq->pend_cqe) { 449 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 450 if (unlikely(!cqe)) { 451 if (!processed_cqe) 452 return 0; 453 break; 454 } 455 if (cq->cq_type == CQ_XDP) { 456 qidx = cq->cq_idx - pfvf->hw.rx_queues; 457 otx2_xdp_snd_pkt_handler(pfvf, &pfvf->qset.sq[qidx], 458 cqe); 459 } else { 460 otx2_snd_pkt_handler(pfvf, cq, 461 &pfvf->qset.sq[cq->cint_idx], 462 cqe, budget, &tx_pkts, &tx_bytes); 463 } 464 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 465 processed_cqe++; 466 cq->pend_cqe--; 467 } 468 469 /* Free CQEs to HW */ 470 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 471 ((u64)cq->cq_idx << 32) | processed_cqe); 472 473 if (likely(tx_pkts)) { 474 struct netdev_queue *txq; 475 476 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx); 477 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 478 /* Check if queue was stopped earlier due to ring full */ 479 smp_mb(); 480 if (netif_tx_queue_stopped(txq) && 481 netif_carrier_ok(pfvf->netdev)) 482 netif_tx_wake_queue(txq); 483 } 484 return 0; 485 } 486 487 int otx2_napi_handler(struct napi_struct *napi, int budget) 488 { 489 struct otx2_cq_queue *rx_cq = NULL; 490 struct otx2_cq_poll *cq_poll; 491 int workdone = 0, cq_idx, i; 492 struct otx2_cq_queue *cq; 493 struct otx2_qset *qset; 494 struct otx2_nic *pfvf; 495 496 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 497 pfvf = (struct otx2_nic *)cq_poll->dev; 498 qset = &pfvf->qset; 499 500 for (i = 0; i < CQS_PER_CINT; i++) { 501 cq_idx = cq_poll->cq_ids[i]; 502 if (unlikely(cq_idx == CINT_INVALID_CQ)) 503 continue; 504 cq = &qset->cq[cq_idx]; 505 if (cq->cq_type == CQ_RX) { 506 rx_cq = cq; 507 workdone += otx2_rx_napi_handler(pfvf, napi, 508 cq, budget); 509 } else { 510 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 511 } 512 } 513 514 if (rx_cq && rx_cq->pool_ptrs) 515 pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq); 516 /* Clear the IRQ */ 517 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 518 519 if (workdone < budget && napi_complete_done(napi, workdone)) { 520 /* If interface is going down, don't re-enable IRQ */ 521 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 522 return workdone; 523 524 /* Re-enable interrupts */ 525 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 526 BIT_ULL(0)); 527 } 528 return workdone; 529 } 530 531 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, 532 int size, int qidx) 533 { 534 u64 status; 535 536 /* Packet data stores should finish before SQE is flushed to HW */ 537 dma_wmb(); 538 539 do { 540 memcpy(sq->lmt_addr, sq->sqe_base, size); 541 status = otx2_lmt_flush(sq->io_addr); 542 } while (status == 0); 543 544 sq->head++; 545 sq->head &= (sq->sqe_cnt - 1); 546 } 547 548 #define MAX_SEGS_PER_SG 3 549 /* Add SQE scatter/gather subdescriptor structure */ 550 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 551 struct sk_buff *skb, int num_segs, int *offset) 552 { 553 struct nix_sqe_sg_s *sg = NULL; 554 u64 dma_addr, *iova = NULL; 555 u16 *sg_lens = NULL; 556 int seg, len; 557 558 sq->sg[sq->head].num_segs = 0; 559 560 for (seg = 0; seg < num_segs; seg++) { 561 if ((seg % MAX_SEGS_PER_SG) == 0) { 562 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 563 sg->ld_type = NIX_SEND_LDTYPE_LDD; 564 sg->subdc = NIX_SUBDC_SG; 565 sg->segs = 0; 566 sg_lens = (void *)sg; 567 iova = (void *)sg + sizeof(*sg); 568 /* Next subdc always starts at a 16byte boundary. 569 * So if sg->segs is whether 2 or 3, offset += 16bytes. 570 */ 571 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 572 *offset += sizeof(*sg) + (3 * sizeof(u64)); 573 else 574 *offset += sizeof(*sg) + sizeof(u64); 575 } 576 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 577 if (dma_mapping_error(pfvf->dev, dma_addr)) 578 return false; 579 580 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 581 sg->segs++; 582 *iova++ = dma_addr; 583 584 /* Save DMA mapping info for later unmapping */ 585 sq->sg[sq->head].dma_addr[seg] = dma_addr; 586 sq->sg[sq->head].size[seg] = len; 587 sq->sg[sq->head].num_segs++; 588 } 589 590 sq->sg[sq->head].skb = (u64)skb; 591 return true; 592 } 593 594 /* Add SQE extended header subdescriptor */ 595 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 596 struct sk_buff *skb, int *offset) 597 { 598 struct nix_sqe_ext_s *ext; 599 600 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 601 ext->subdc = NIX_SUBDC_EXT; 602 if (skb_shinfo(skb)->gso_size) { 603 ext->lso = 1; 604 ext->lso_sb = skb_transport_offset(skb) + tcp_hdrlen(skb); 605 ext->lso_mps = skb_shinfo(skb)->gso_size; 606 607 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 608 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 609 ext->lso_format = pfvf->hw.lso_tsov4_idx; 610 611 /* HW adds payload size to 'ip_hdr->tot_len' while 612 * sending TSO segment, hence set payload length 613 * in IP header of the packet to just header length. 614 */ 615 ip_hdr(skb)->tot_len = 616 htons(ext->lso_sb - skb_network_offset(skb)); 617 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) { 618 ext->lso_format = pfvf->hw.lso_tsov6_idx; 619 620 ipv6_hdr(skb)->payload_len = 621 htons(ext->lso_sb - skb_network_offset(skb)); 622 } else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 623 __be16 l3_proto = vlan_get_protocol(skb); 624 struct udphdr *udph = udp_hdr(skb); 625 u16 iplen; 626 627 ext->lso_sb = skb_transport_offset(skb) + 628 sizeof(struct udphdr); 629 630 /* HW adds payload size to length fields in IP and 631 * UDP headers while segmentation, hence adjust the 632 * lengths to just header sizes. 633 */ 634 iplen = htons(ext->lso_sb - skb_network_offset(skb)); 635 if (l3_proto == htons(ETH_P_IP)) { 636 ip_hdr(skb)->tot_len = iplen; 637 ext->lso_format = pfvf->hw.lso_udpv4_idx; 638 } else { 639 ipv6_hdr(skb)->payload_len = iplen; 640 ext->lso_format = pfvf->hw.lso_udpv6_idx; 641 } 642 643 udph->len = htons(sizeof(struct udphdr)); 644 } 645 } else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 646 ext->tstmp = 1; 647 } 648 649 #define OTX2_VLAN_PTR_OFFSET (ETH_HLEN - ETH_TLEN) 650 if (skb_vlan_tag_present(skb)) { 651 if (skb->vlan_proto == htons(ETH_P_8021Q)) { 652 ext->vlan1_ins_ena = 1; 653 ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET; 654 ext->vlan1_ins_tci = skb_vlan_tag_get(skb); 655 } else if (skb->vlan_proto == htons(ETH_P_8021AD)) { 656 ext->vlan0_ins_ena = 1; 657 ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET; 658 ext->vlan0_ins_tci = skb_vlan_tag_get(skb); 659 } 660 } 661 662 *offset += sizeof(*ext); 663 } 664 665 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset, 666 int alg, u64 iova) 667 { 668 struct nix_sqe_mem_s *mem; 669 670 mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset); 671 mem->subdc = NIX_SUBDC_MEM; 672 mem->alg = alg; 673 mem->wmem = 1; /* wait for the memory operation */ 674 mem->addr = iova; 675 676 *offset += sizeof(*mem); 677 } 678 679 /* Add SQE header subdescriptor structure */ 680 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 681 struct nix_sqe_hdr_s *sqe_hdr, 682 struct sk_buff *skb, u16 qidx) 683 { 684 int proto = 0; 685 686 /* Check if SQE was framed before, if yes then no need to 687 * set these constants again and again. 688 */ 689 if (!sqe_hdr->total) { 690 /* Don't free Tx buffers to Aura */ 691 sqe_hdr->df = 1; 692 sqe_hdr->aura = sq->aura_id; 693 /* Post a CQE Tx after pkt transmission */ 694 sqe_hdr->pnc = 1; 695 sqe_hdr->sq = qidx; 696 } 697 sqe_hdr->total = skb->len; 698 /* Set SQE identifier which will be used later for freeing SKB */ 699 sqe_hdr->sqe_id = sq->head; 700 701 /* Offload TCP/UDP checksum to HW */ 702 if (skb->ip_summed == CHECKSUM_PARTIAL) { 703 sqe_hdr->ol3ptr = skb_network_offset(skb); 704 sqe_hdr->ol4ptr = skb_transport_offset(skb); 705 /* get vlan protocol Ethertype */ 706 if (eth_type_vlan(skb->protocol)) 707 skb->protocol = vlan_get_protocol(skb); 708 709 if (skb->protocol == htons(ETH_P_IP)) { 710 proto = ip_hdr(skb)->protocol; 711 /* In case of TSO, HW needs this to be explicitly set. 712 * So set this always, instead of adding a check. 713 */ 714 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 715 } else if (skb->protocol == htons(ETH_P_IPV6)) { 716 proto = ipv6_hdr(skb)->nexthdr; 717 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6; 718 } 719 720 if (proto == IPPROTO_TCP) 721 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 722 else if (proto == IPPROTO_UDP) 723 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 724 } 725 } 726 727 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 728 struct otx2_snd_queue *sq, 729 struct sk_buff *skb, int sqe, int hdr_len) 730 { 731 int num_segs = skb_shinfo(skb)->nr_frags + 1; 732 struct sg_list *sg = &sq->sg[sqe]; 733 u64 dma_addr; 734 int seg, len; 735 736 sg->num_segs = 0; 737 738 /* Get payload length at skb->data */ 739 len = skb_headlen(skb) - hdr_len; 740 741 for (seg = 0; seg < num_segs; seg++) { 742 /* Skip skb->data, if there is no payload */ 743 if (!seg && !len) 744 continue; 745 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 746 if (dma_mapping_error(pfvf->dev, dma_addr)) 747 goto unmap; 748 749 /* Save DMA mapping info for later unmapping */ 750 sg->dma_addr[sg->num_segs] = dma_addr; 751 sg->size[sg->num_segs] = len; 752 sg->num_segs++; 753 } 754 return 0; 755 unmap: 756 otx2_dma_unmap_skb_frags(pfvf, sg); 757 return -EINVAL; 758 } 759 760 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 761 struct sk_buff *skb, int seg, 762 u64 seg_addr, int hdr_len, int sqe) 763 { 764 struct sg_list *sg = &sq->sg[sqe]; 765 const skb_frag_t *frag; 766 int offset; 767 768 if (seg < 0) 769 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 770 771 frag = &skb_shinfo(skb)->frags[seg]; 772 offset = seg_addr - (u64)skb_frag_address(frag); 773 if (skb_headlen(skb) - hdr_len) 774 seg++; 775 return sg->dma_addr[seg] + offset; 776 } 777 778 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 779 struct sg_list *list, int *offset) 780 { 781 struct nix_sqe_sg_s *sg = NULL; 782 u16 *sg_lens = NULL; 783 u64 *iova = NULL; 784 int seg; 785 786 /* Add SG descriptors with buffer addresses */ 787 for (seg = 0; seg < list->num_segs; seg++) { 788 if ((seg % MAX_SEGS_PER_SG) == 0) { 789 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 790 sg->ld_type = NIX_SEND_LDTYPE_LDD; 791 sg->subdc = NIX_SUBDC_SG; 792 sg->segs = 0; 793 sg_lens = (void *)sg; 794 iova = (void *)sg + sizeof(*sg); 795 /* Next subdc always starts at a 16byte boundary. 796 * So if sg->segs is whether 2 or 3, offset += 16bytes. 797 */ 798 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 799 *offset += sizeof(*sg) + (3 * sizeof(u64)); 800 else 801 *offset += sizeof(*sg) + sizeof(u64); 802 } 803 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 804 *iova++ = list->dma_addr[seg]; 805 sg->segs++; 806 } 807 } 808 809 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 810 struct sk_buff *skb, u16 qidx) 811 { 812 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 813 int hdr_len, tcp_data, seg_len, pkt_len, offset; 814 struct nix_sqe_hdr_s *sqe_hdr; 815 int first_sqe = sq->head; 816 struct sg_list list; 817 struct tso_t tso; 818 819 hdr_len = tso_start(skb, &tso); 820 821 /* Map SKB's fragments to DMA. 822 * It's done here to avoid mapping for every TSO segment's packet. 823 */ 824 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 825 dev_kfree_skb_any(skb); 826 return; 827 } 828 829 netdev_tx_sent_queue(txq, skb->len); 830 831 tcp_data = skb->len - hdr_len; 832 while (tcp_data > 0) { 833 char *hdr; 834 835 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 836 tcp_data -= seg_len; 837 838 /* Set SQE's SEND_HDR */ 839 memset(sq->sqe_base, 0, sq->sqe_size); 840 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 841 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 842 offset = sizeof(*sqe_hdr); 843 844 /* Add TSO segment's pkt header */ 845 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 846 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 847 list.dma_addr[0] = 848 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 849 list.size[0] = hdr_len; 850 list.num_segs = 1; 851 852 /* Add TSO segment's payload data fragments */ 853 pkt_len = hdr_len; 854 while (seg_len > 0) { 855 int size; 856 857 size = min_t(int, tso.size, seg_len); 858 859 list.size[list.num_segs] = size; 860 list.dma_addr[list.num_segs] = 861 otx2_tso_frag_dma_addr(sq, skb, 862 tso.next_frag_idx - 1, 863 (u64)tso.data, hdr_len, 864 first_sqe); 865 list.num_segs++; 866 pkt_len += size; 867 seg_len -= size; 868 tso_build_data(skb, &tso, size); 869 } 870 sqe_hdr->total = pkt_len; 871 otx2_sqe_tso_add_sg(sq, &list, &offset); 872 873 /* DMA mappings and skb needs to be freed only after last 874 * TSO segment is transmitted out. So set 'PNC' only for 875 * last segment. Also point last segment's sqe_id to first 876 * segment's SQE index where skb address and DMA mappings 877 * are saved. 878 */ 879 if (!tcp_data) { 880 sqe_hdr->pnc = 1; 881 sqe_hdr->sqe_id = first_sqe; 882 sq->sg[first_sqe].skb = (u64)skb; 883 } else { 884 sqe_hdr->pnc = 0; 885 } 886 887 sqe_hdr->sizem1 = (offset / 16) - 1; 888 889 /* Flush SQE to HW */ 890 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 891 } 892 } 893 894 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 895 struct sk_buff *skb) 896 { 897 int payload_len, last_seg_size; 898 899 if (test_bit(HW_TSO, &pfvf->hw.cap_flag)) 900 return true; 901 902 /* On 96xx A0, HW TSO not supported */ 903 if (!is_96xx_B0(pfvf->pdev)) 904 return false; 905 906 /* HW has an issue due to which when the payload of the last LSO 907 * segment is shorter than 16 bytes, some header fields may not 908 * be correctly modified, hence don't offload such TSO segments. 909 */ 910 911 payload_len = skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb)); 912 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 913 if (last_seg_size && last_seg_size < 16) 914 return false; 915 916 return true; 917 } 918 919 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 920 { 921 if (!skb_shinfo(skb)->gso_size) 922 return 1; 923 924 /* HW TSO */ 925 if (is_hw_tso_supported(pfvf, skb)) 926 return 1; 927 928 /* SW TSO */ 929 return skb_shinfo(skb)->gso_segs; 930 } 931 932 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb, 933 struct otx2_snd_queue *sq, int *offset) 934 { 935 u64 iova; 936 937 if (!skb_shinfo(skb)->gso_size && 938 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { 939 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 940 iova = sq->timestamps->iova + (sq->head * sizeof(u64)); 941 otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova); 942 } else { 943 skb_tx_timestamp(skb); 944 } 945 } 946 947 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 948 struct sk_buff *skb, u16 qidx) 949 { 950 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 951 struct otx2_nic *pfvf = netdev_priv(netdev); 952 int offset, num_segs, free_sqe; 953 struct nix_sqe_hdr_s *sqe_hdr; 954 955 /* Check if there is room for new SQE. 956 * 'Num of SQBs freed to SQ's pool - SQ's Aura count' 957 * will give free SQE count. 958 */ 959 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 960 961 if (free_sqe < sq->sqe_thresh || 962 free_sqe < otx2_get_sqe_count(pfvf, skb)) 963 return false; 964 965 num_segs = skb_shinfo(skb)->nr_frags + 1; 966 967 /* If SKB doesn't fit in a single SQE, linearize it. 968 * TODO: Consider adding JUMP descriptor instead. 969 */ 970 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 971 if (__skb_linearize(skb)) { 972 dev_kfree_skb_any(skb); 973 return true; 974 } 975 num_segs = skb_shinfo(skb)->nr_frags + 1; 976 } 977 978 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 979 /* Insert vlan tag before giving pkt to tso */ 980 if (skb_vlan_tag_present(skb)) 981 skb = __vlan_hwaccel_push_inside(skb); 982 otx2_sq_append_tso(pfvf, sq, skb, qidx); 983 return true; 984 } 985 986 /* Set SQE's SEND_HDR. 987 * Do not clear the first 64bit as it contains constant info. 988 */ 989 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 990 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 991 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 992 offset = sizeof(*sqe_hdr); 993 994 /* Add extended header if needed */ 995 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 996 997 /* Add SG subdesc with data frags */ 998 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 999 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 1000 return false; 1001 } 1002 1003 otx2_set_txtstamp(pfvf, skb, sq, &offset); 1004 1005 sqe_hdr->sizem1 = (offset / 16) - 1; 1006 1007 netdev_tx_sent_queue(txq, skb->len); 1008 1009 /* Flush SQE to HW */ 1010 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1011 1012 return true; 1013 } 1014 EXPORT_SYMBOL(otx2_sq_append_skb); 1015 1016 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1017 { 1018 struct nix_cqe_rx_s *cqe; 1019 int processed_cqe = 0; 1020 u64 iova, pa; 1021 1022 if (pfvf->xdp_prog) 1023 xdp_rxq_info_unreg(&cq->xdp_rxq); 1024 1025 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1026 return; 1027 1028 while (cq->pend_cqe) { 1029 cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq); 1030 processed_cqe++; 1031 cq->pend_cqe--; 1032 1033 if (!cqe) 1034 continue; 1035 if (cqe->sg.segs > 1) { 1036 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx); 1037 continue; 1038 } 1039 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1040 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1041 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); 1042 put_page(virt_to_page(phys_to_virt(pa))); 1043 } 1044 1045 /* Free CQEs to HW */ 1046 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1047 ((u64)cq->cq_idx << 32) | processed_cqe); 1048 } 1049 1050 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 1051 { 1052 struct sk_buff *skb = NULL; 1053 struct otx2_snd_queue *sq; 1054 struct nix_cqe_tx_s *cqe; 1055 int processed_cqe = 0; 1056 struct sg_list *sg; 1057 1058 sq = &pfvf->qset.sq[cq->cint_idx]; 1059 1060 if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe) 1061 return; 1062 1063 while (cq->pend_cqe) { 1064 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 1065 processed_cqe++; 1066 cq->pend_cqe--; 1067 1068 if (!cqe) 1069 continue; 1070 sg = &sq->sg[cqe->comp.sqe_id]; 1071 skb = (struct sk_buff *)sg->skb; 1072 if (skb) { 1073 otx2_dma_unmap_skb_frags(pfvf, sg); 1074 dev_kfree_skb_any(skb); 1075 sg->skb = (u64)NULL; 1076 } 1077 } 1078 1079 /* Free CQEs to HW */ 1080 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 1081 ((u64)cq->cq_idx << 32) | processed_cqe); 1082 } 1083 1084 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 1085 { 1086 struct msg_req *msg; 1087 int err; 1088 1089 mutex_lock(&pfvf->mbox.lock); 1090 if (enable) 1091 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 1092 else 1093 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 1094 1095 if (!msg) { 1096 mutex_unlock(&pfvf->mbox.lock); 1097 return -ENOMEM; 1098 } 1099 1100 err = otx2_sync_mbox_msg(&pfvf->mbox); 1101 mutex_unlock(&pfvf->mbox.lock); 1102 return err; 1103 } 1104 1105 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr, 1106 int len, int *offset) 1107 { 1108 struct nix_sqe_sg_s *sg = NULL; 1109 u64 *iova = NULL; 1110 1111 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 1112 sg->ld_type = NIX_SEND_LDTYPE_LDD; 1113 sg->subdc = NIX_SUBDC_SG; 1114 sg->segs = 1; 1115 sg->seg1_size = len; 1116 iova = (void *)sg + sizeof(*sg); 1117 *iova = dma_addr; 1118 *offset += sizeof(*sg) + sizeof(u64); 1119 1120 sq->sg[sq->head].dma_addr[0] = dma_addr; 1121 sq->sg[sq->head].size[0] = len; 1122 sq->sg[sq->head].num_segs = 1; 1123 } 1124 1125 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx) 1126 { 1127 struct nix_sqe_hdr_s *sqe_hdr; 1128 struct otx2_snd_queue *sq; 1129 int offset, free_sqe; 1130 1131 sq = &pfvf->qset.sq[qidx]; 1132 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 1133 if (free_sqe < sq->sqe_thresh) 1134 return false; 1135 1136 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 1137 1138 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 1139 1140 if (!sqe_hdr->total) { 1141 sqe_hdr->aura = sq->aura_id; 1142 sqe_hdr->df = 1; 1143 sqe_hdr->sq = qidx; 1144 sqe_hdr->pnc = 1; 1145 } 1146 sqe_hdr->total = len; 1147 sqe_hdr->sqe_id = sq->head; 1148 1149 offset = sizeof(*sqe_hdr); 1150 1151 otx2_xdp_sqe_add_sg(sq, iova, len, &offset); 1152 sqe_hdr->sizem1 = (offset / 16) - 1; 1153 pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); 1154 1155 return true; 1156 } 1157 1158 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf, 1159 struct bpf_prog *prog, 1160 struct nix_cqe_rx_s *cqe, 1161 struct otx2_cq_queue *cq) 1162 { 1163 unsigned char *hard_start, *data; 1164 int qidx = cq->cq_idx; 1165 struct xdp_buff xdp; 1166 struct page *page; 1167 u64 iova, pa; 1168 u32 act; 1169 int err; 1170 1171 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 1172 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 1173 page = virt_to_page(phys_to_virt(pa)); 1174 1175 xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq); 1176 1177 data = (unsigned char *)phys_to_virt(pa); 1178 hard_start = page_address(page); 1179 xdp_prepare_buff(&xdp, hard_start, data - hard_start, 1180 cqe->sg.seg_size, false); 1181 1182 act = bpf_prog_run_xdp(prog, &xdp); 1183 1184 switch (act) { 1185 case XDP_PASS: 1186 break; 1187 case XDP_TX: 1188 qidx += pfvf->hw.tx_queues; 1189 cq->pool_ptrs++; 1190 return otx2_xdp_sq_append_pkt(pfvf, iova, 1191 cqe->sg.seg_size, qidx); 1192 case XDP_REDIRECT: 1193 cq->pool_ptrs++; 1194 err = xdp_do_redirect(pfvf->netdev, &xdp, prog); 1195 1196 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1197 DMA_FROM_DEVICE); 1198 if (!err) 1199 return true; 1200 put_page(page); 1201 break; 1202 default: 1203 bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act); 1204 break; 1205 case XDP_ABORTED: 1206 trace_xdp_exception(pfvf->netdev, prog, act); 1207 break; 1208 case XDP_DROP: 1209 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, 1210 DMA_FROM_DEVICE); 1211 put_page(page); 1212 cq->pool_ptrs++; 1213 return true; 1214 } 1215 return false; 1216 } 1217