1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_REG_H 12 #define OTX2_REG_H 13 14 #include <rvu_struct.h> 15 16 /* RVU PF registers */ 17 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000) 18 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008) 19 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3) 20 #define RVU_PF_VF_BAR4_ADDR (0x10) 21 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) 22 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3) 23 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3) 24 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3) 25 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3) 26 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3) 27 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3) 28 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3) 29 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3) 30 #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3) 31 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3) 32 #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3) 33 #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3) 34 #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3) 35 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3) 36 #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3) 37 #define RVU_PF_PFAF_MBOX0 (0xC00) 38 #define RVU_PF_PFAF_MBOX1 (0xC08) 39 #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3) 40 #define RVU_PF_INT (0xc20) 41 #define RVU_PF_INT_W1S (0xc28) 42 #define RVU_PF_INT_ENA_W1S (0xc30) 43 #define RVU_PF_INT_ENA_W1C (0xc38) 44 #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) 45 #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) 46 #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3) 47 #define RVU_PF_VF_MBOX_ADDR (0xC40) 48 #define RVU_PF_LMTLINE_ADDR (0xC48) 49 50 /* RVU VF registers */ 51 #define RVU_VF_VFPF_MBOX0 (0x00000) 52 #define RVU_VF_VFPF_MBOX1 (0x00008) 53 #define RVU_VF_VFPF_MBOXX(a) (0x00 | (a) << 3) 54 #define RVU_VF_INT (0x20) 55 #define RVU_VF_INT_W1S (0x28) 56 #define RVU_VF_INT_ENA_W1S (0x30) 57 #define RVU_VF_INT_ENA_W1C (0x38) 58 #define RVU_VF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3) 59 #define RVU_VF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4) 60 #define RVU_VF_MSIX_VECX_CTL(a) (0x008 | (a) << 4) 61 #define RVU_VF_MSIX_PBAX(a) (0xF0000 | (a) << 3) 62 #define RVU_VF_MBOX_REGION (0xC0000) 63 64 #define RVU_FUNC_BLKADDR_SHIFT 20 65 #define RVU_FUNC_BLKADDR_MASK 0x1FULL 66 67 /* NPA LF registers */ 68 #define NPA_LFBASE (BLKTYPE_NPA << RVU_FUNC_BLKADDR_SHIFT) 69 #define NPA_LF_AURA_OP_ALLOCX(a) (NPA_LFBASE | 0x10 | (a) << 3) 70 #define NPA_LF_AURA_OP_FREE0 (NPA_LFBASE | 0x20) 71 #define NPA_LF_AURA_OP_FREE1 (NPA_LFBASE | 0x28) 72 #define NPA_LF_AURA_OP_CNT (NPA_LFBASE | 0x30) 73 #define NPA_LF_AURA_OP_LIMIT (NPA_LFBASE | 0x50) 74 #define NPA_LF_AURA_OP_INT (NPA_LFBASE | 0x60) 75 #define NPA_LF_AURA_OP_THRESH (NPA_LFBASE | 0x70) 76 #define NPA_LF_POOL_OP_PC (NPA_LFBASE | 0x100) 77 #define NPA_LF_POOL_OP_AVAILABLE (NPA_LFBASE | 0x110) 78 #define NPA_LF_POOL_OP_PTR_START0 (NPA_LFBASE | 0x120) 79 #define NPA_LF_POOL_OP_PTR_START1 (NPA_LFBASE | 0x128) 80 #define NPA_LF_POOL_OP_PTR_END0 (NPA_LFBASE | 0x130) 81 #define NPA_LF_POOL_OP_PTR_END1 (NPA_LFBASE | 0x138) 82 #define NPA_LF_POOL_OP_INT (NPA_LFBASE | 0x160) 83 #define NPA_LF_POOL_OP_THRESH (NPA_LFBASE | 0x170) 84 #define NPA_LF_ERR_INT (NPA_LFBASE | 0x200) 85 #define NPA_LF_ERR_INT_W1S (NPA_LFBASE | 0x208) 86 #define NPA_LF_ERR_INT_ENA_W1C (NPA_LFBASE | 0x210) 87 #define NPA_LF_ERR_INT_ENA_W1S (NPA_LFBASE | 0x218) 88 #define NPA_LF_RAS (NPA_LFBASE | 0x220) 89 #define NPA_LF_RAS_W1S (NPA_LFBASE | 0x228) 90 #define NPA_LF_RAS_ENA_W1C (NPA_LFBASE | 0x230) 91 #define NPA_LF_RAS_ENA_W1S (NPA_LFBASE | 0x238) 92 #define NPA_LF_QINTX_CNT(a) (NPA_LFBASE | 0x300 | (a) << 12) 93 #define NPA_LF_QINTX_INT(a) (NPA_LFBASE | 0x310 | (a) << 12) 94 #define NPA_LF_QINTX_INT_W1S(a) (NPA_LFBASE | 0x318 | (a) << 12) 95 #define NPA_LF_QINTX_ENA_W1S(a) (NPA_LFBASE | 0x320 | (a) << 12) 96 #define NPA_LF_QINTX_ENA_W1C(a) (NPA_LFBASE | 0x330 | (a) << 12) 97 #define NPA_LF_AURA_BATCH_FREE0 (NPA_LFBASE | 0x400) 98 99 /* NIX LF registers */ 100 #define NIX_LFBASE (BLKTYPE_NIX << RVU_FUNC_BLKADDR_SHIFT) 101 #define NIX_LF_RX_SECRETX(a) (NIX_LFBASE | 0x0 | (a) << 3) 102 #define NIX_LF_CFG (NIX_LFBASE | 0x100) 103 #define NIX_LF_GINT (NIX_LFBASE | 0x200) 104 #define NIX_LF_GINT_W1S (NIX_LFBASE | 0x208) 105 #define NIX_LF_GINT_ENA_W1C (NIX_LFBASE | 0x210) 106 #define NIX_LF_GINT_ENA_W1S (NIX_LFBASE | 0x218) 107 #define NIX_LF_ERR_INT (NIX_LFBASE | 0x220) 108 #define NIX_LF_ERR_INT_W1S (NIX_LFBASE | 0x228) 109 #define NIX_LF_ERR_INT_ENA_W1C (NIX_LFBASE | 0x230) 110 #define NIX_LF_ERR_INT_ENA_W1S (NIX_LFBASE | 0x238) 111 #define NIX_LF_RAS (NIX_LFBASE | 0x240) 112 #define NIX_LF_RAS_W1S (NIX_LFBASE | 0x248) 113 #define NIX_LF_RAS_ENA_W1C (NIX_LFBASE | 0x250) 114 #define NIX_LF_RAS_ENA_W1S (NIX_LFBASE | 0x258) 115 #define NIX_LF_SQ_OP_ERR_DBG (NIX_LFBASE | 0x260) 116 #define NIX_LF_MNQ_ERR_DBG (NIX_LFBASE | 0x270) 117 #define NIX_LF_SEND_ERR_DBG (NIX_LFBASE | 0x280) 118 #define NIX_LF_TX_STATX(a) (NIX_LFBASE | 0x300 | (a) << 3) 119 #define NIX_LF_RX_STATX(a) (NIX_LFBASE | 0x400 | (a) << 3) 120 #define NIX_LF_OP_SENDX(a) (NIX_LFBASE | 0x800 | (a) << 3) 121 #define NIX_LF_RQ_OP_INT (NIX_LFBASE | 0x900) 122 #define NIX_LF_RQ_OP_OCTS (NIX_LFBASE | 0x910) 123 #define NIX_LF_RQ_OP_PKTS (NIX_LFBASE | 0x920) 124 #define NIX_LF_OP_IPSEC_DYNO_CN (NIX_LFBASE | 0x980) 125 #define NIX_LF_SQ_OP_INT (NIX_LFBASE | 0xa00) 126 #define NIX_LF_SQ_OP_OCTS (NIX_LFBASE | 0xa10) 127 #define NIX_LF_SQ_OP_PKTS (NIX_LFBASE | 0xa20) 128 #define NIX_LF_SQ_OP_STATUS (NIX_LFBASE | 0xa30) 129 #define NIX_LF_CQ_OP_INT (NIX_LFBASE | 0xb00) 130 #define NIX_LF_CQ_OP_DOOR (NIX_LFBASE | 0xb30) 131 #define NIX_LF_CQ_OP_STATUS (NIX_LFBASE | 0xb40) 132 #define NIX_LF_QINTX_CNT(a) (NIX_LFBASE | 0xC00 | (a) << 12) 133 #define NIX_LF_QINTX_INT(a) (NIX_LFBASE | 0xC10 | (a) << 12) 134 #define NIX_LF_QINTX_INT_W1S(a) (NIX_LFBASE | 0xC18 | (a) << 12) 135 #define NIX_LF_QINTX_ENA_W1S(a) (NIX_LFBASE | 0xC20 | (a) << 12) 136 #define NIX_LF_QINTX_ENA_W1C(a) (NIX_LFBASE | 0xC30 | (a) << 12) 137 #define NIX_LF_CINTX_CNT(a) (NIX_LFBASE | 0xD00 | (a) << 12) 138 #define NIX_LF_CINTX_WAIT(a) (NIX_LFBASE | 0xD10 | (a) << 12) 139 #define NIX_LF_CINTX_INT(a) (NIX_LFBASE | 0xD20 | (a) << 12) 140 #define NIX_LF_CINTX_INT_W1S(a) (NIX_LFBASE | 0xD30 | (a) << 12) 141 #define NIX_LF_CINTX_ENA_W1S(a) (NIX_LFBASE | 0xD40 | (a) << 12) 142 #define NIX_LF_CINTX_ENA_W1C(a) (NIX_LFBASE | 0xD50 | (a) << 12) 143 144 /* NIX AF transmit scheduler registers */ 145 #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16) 146 #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16) 147 #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16) 148 #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16) 149 #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16) 150 #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16) 151 #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16) 152 #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16) 153 #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16) 154 #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16) 155 #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16) 156 #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16) 157 #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16) 158 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3) 159 160 /* LMT LF registers */ 161 #define LMT_LFBASE BIT_ULL(RVU_FUNC_BLKADDR_SHIFT) 162 #define LMT_LF_LMTLINEX(a) (LMT_LFBASE | 0x000 | (a) << 12) 163 #define LMT_LF_LMTCANCEL (LMT_LFBASE | 0x400) 164 165 #endif /* OTX2_REG_H */ 166