1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 19 #include "otx2_reg.h" 20 #include "otx2_common.h" 21 #include "otx2_txrx.h" 22 #include "otx2_struct.h" 23 #include "otx2_ptp.h" 24 #include "cn10k.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "rvu_nicpf" 28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 static void otx2_vf_link_event_task(struct work_struct *work); 42 43 enum { 44 TYPE_PFAF, 45 TYPE_PFVF, 46 }; 47 48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 50 51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 52 { 53 struct otx2_nic *pf = netdev_priv(netdev); 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 59 netdev->mtu); 60 return -EINVAL; 61 } 62 if (if_up) 63 otx2_stop(netdev); 64 65 netdev_info(netdev, "Changing MTU from %d to %d\n", 66 netdev->mtu, new_mtu); 67 netdev->mtu = new_mtu; 68 69 if (if_up) 70 err = otx2_open(netdev); 71 72 return err; 73 } 74 75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 76 { 77 int irq, vfs = pf->total_vfs; 78 79 /* Disable VFs ME interrupts */ 80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 82 free_irq(irq, pf); 83 84 /* Disable VFs FLR interrupts */ 85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 87 free_irq(irq, pf); 88 89 if (vfs <= 64) 90 return; 91 92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 94 free_irq(irq, pf); 95 96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 98 free_irq(irq, pf); 99 } 100 101 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 102 { 103 if (!pf->flr_wq) 104 return; 105 destroy_workqueue(pf->flr_wq); 106 pf->flr_wq = NULL; 107 devm_kfree(pf->dev, pf->flr_wrk); 108 } 109 110 static void otx2_flr_handler(struct work_struct *work) 111 { 112 struct flr_work *flrwork = container_of(work, struct flr_work, work); 113 struct otx2_nic *pf = flrwork->pf; 114 struct mbox *mbox = &pf->mbox; 115 struct msg_req *req; 116 int vf, reg = 0; 117 118 vf = flrwork - pf->flr_wrk; 119 120 mutex_lock(&mbox->lock); 121 req = otx2_mbox_alloc_msg_vf_flr(mbox); 122 if (!req) { 123 mutex_unlock(&mbox->lock); 124 return; 125 } 126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 128 129 if (!otx2_sync_mbox_msg(&pf->mbox)) { 130 if (vf >= 64) { 131 reg = 1; 132 vf = vf - 64; 133 } 134 /* clear transcation pending bit */ 135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 137 } 138 139 mutex_unlock(&mbox->lock); 140 } 141 142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 143 { 144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 145 int reg, dev, vf, start_vf, num_reg = 1; 146 u64 intr; 147 148 if (pf->total_vfs > 64) 149 num_reg = 2; 150 151 for (reg = 0; reg < num_reg; reg++) { 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 153 if (!intr) 154 continue; 155 start_vf = 64 * reg; 156 for (vf = 0; vf < 64; vf++) { 157 if (!(intr & BIT_ULL(vf))) 158 continue; 159 dev = vf + start_vf; 160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 161 /* Clear interrupt */ 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 163 /* Disable the interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 165 BIT_ULL(vf)); 166 } 167 } 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 172 { 173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 174 int vf, reg, num_reg = 1; 175 u64 intr; 176 177 if (pf->total_vfs > 64) 178 num_reg = 2; 179 180 for (reg = 0; reg < num_reg; reg++) { 181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 182 if (!intr) 183 continue; 184 for (vf = 0; vf < 64; vf++) { 185 if (!(intr & BIT_ULL(vf))) 186 continue; 187 /* clear trpend bit */ 188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 189 /* clear interrupt */ 190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 191 } 192 } 193 return IRQ_HANDLED; 194 } 195 196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 197 { 198 struct otx2_hw *hw = &pf->hw; 199 char *irq_name; 200 int ret; 201 202 /* Register ME interrupt handler*/ 203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 206 otx2_pf_me_intr_handler, 0, irq_name, pf); 207 if (ret) { 208 dev_err(pf->dev, 209 "RVUPF: IRQ registration failed for ME0\n"); 210 } 211 212 /* Register FLR interrupt handler */ 213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 216 otx2_pf_flr_intr_handler, 0, irq_name, pf); 217 if (ret) { 218 dev_err(pf->dev, 219 "RVUPF: IRQ registration failed for FLR0\n"); 220 return ret; 221 } 222 223 if (numvfs > 64) { 224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 226 rvu_get_pf(pf->pcifunc)); 227 ret = request_irq(pci_irq_vector 228 (pf->pdev, RVU_PF_INT_VEC_VFME1), 229 otx2_pf_me_intr_handler, 0, irq_name, pf); 230 if (ret) { 231 dev_err(pf->dev, 232 "RVUPF: IRQ registration failed for ME1\n"); 233 } 234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 236 rvu_get_pf(pf->pcifunc)); 237 ret = request_irq(pci_irq_vector 238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 239 otx2_pf_flr_intr_handler, 0, irq_name, pf); 240 if (ret) { 241 dev_err(pf->dev, 242 "RVUPF: IRQ registration failed for FLR1\n"); 243 return ret; 244 } 245 } 246 247 /* Enable ME interrupt for all VFs*/ 248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 250 251 /* Enable FLR interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 if (numvfs > 64) { 256 numvfs -= 64; 257 258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 260 INTR_MASK(numvfs)); 261 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 } 266 return 0; 267 } 268 269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 270 { 271 int vf; 272 273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 274 WQ_UNBOUND | WQ_HIGHPRI, 1); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 /* Error code -EIO indicate there is a communication failure 398 * to the AF. Rest of the error codes indicate that AF processed 399 * VF messages and set the error codes in response messages 400 * (if any) so simply forward responses to VF. 401 */ 402 if (err == -EIO) { 403 dev_warn(pf->dev, 404 "AF not responding to VF%d messages\n", vf); 405 /* restore PF mbase and exit */ 406 dst_mdev->mbase = pf->mbox.bbuf_base; 407 mutex_unlock(&pf->mbox.lock); 408 return err; 409 } 410 /* At this point, all the VF messages sent to AF are acked 411 * with proper responses and responses are copied to VF 412 * mailbox hence raise interrupt to VF. 413 */ 414 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 415 dst_mbox->mbox.rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 419 pf->mbox.bbuf_base, vf); 420 mutex_unlock(&pf->mbox.lock); 421 } else if (dir == MBOX_DIR_PFVF_UP) { 422 src_mdev = &src_mbox->dev[0]; 423 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 424 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 425 src_mbox->rx_start); 426 req_hdr->num_msgs = num_msgs; 427 428 dst_mbox = &pf->mbox_pfvf[0]; 429 dst_size = dst_mbox->mbox_up.tx_size - 430 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 431 /* Check if msgs fit into destination area */ 432 if (mbox_hdr->msg_size > dst_size) 433 return -EINVAL; 434 435 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 436 dst_mdev->mbase = src_mdev->mbase; 437 dst_mdev->msg_size = mbox_hdr->msg_size; 438 dst_mdev->num_msgs = mbox_hdr->num_msgs; 439 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 440 if (err) { 441 dev_warn(pf->dev, 442 "VF%d is not responding to mailbox\n", vf); 443 return err; 444 } 445 } else if (dir == MBOX_DIR_VFPF_UP) { 446 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 447 src_mbox->rx_start); 448 req_hdr->num_msgs = num_msgs; 449 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 450 &pf->mbox.mbox_up, 451 pf->mbox_pfvf[vf].bbuf_base, 452 0); 453 } 454 455 return 0; 456 } 457 458 static void otx2_pfvf_mbox_handler(struct work_struct *work) 459 { 460 struct mbox_msghdr *msg = NULL; 461 int offset, vf_idx, id, err; 462 struct otx2_mbox_dev *mdev; 463 struct mbox_hdr *req_hdr; 464 struct otx2_mbox *mbox; 465 struct mbox *vf_mbox; 466 struct otx2_nic *pf; 467 468 vf_mbox = container_of(work, struct mbox, mbox_wrk); 469 pf = vf_mbox->pfvf; 470 vf_idx = vf_mbox - pf->mbox_pfvf; 471 472 mbox = &pf->mbox_pfvf[0].mbox; 473 mdev = &mbox->dev[vf_idx]; 474 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 475 476 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 477 478 for (id = 0; id < vf_mbox->num_msgs; id++) { 479 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 480 offset); 481 482 if (msg->sig != OTX2_MBOX_REQ_SIG) 483 goto inval_msg; 484 485 /* Set VF's number in each of the msg */ 486 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 487 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 488 offset = msg->next_msgoff; 489 } 490 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 491 vf_mbox->num_msgs); 492 if (err) 493 goto inval_msg; 494 return; 495 496 inval_msg: 497 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 498 otx2_mbox_msg_send(mbox, vf_idx); 499 } 500 501 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 502 { 503 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 504 struct otx2_nic *pf = vf_mbox->pfvf; 505 struct otx2_mbox_dev *mdev; 506 int offset, id, vf_idx = 0; 507 struct mbox_hdr *rsp_hdr; 508 struct mbox_msghdr *msg; 509 struct otx2_mbox *mbox; 510 511 vf_idx = vf_mbox - pf->mbox_pfvf; 512 mbox = &pf->mbox_pfvf[0].mbox_up; 513 mdev = &mbox->dev[vf_idx]; 514 515 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 516 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 517 518 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 519 msg = mdev->mbase + offset; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(pf->dev, 523 "Mbox msg with unknown ID 0x%x\n", msg->id); 524 goto end; 525 } 526 527 if (msg->sig != OTX2_MBOX_RSP_SIG) { 528 dev_err(pf->dev, 529 "Mbox msg with wrong signature %x, ID 0x%x\n", 530 msg->sig, msg->id); 531 goto end; 532 } 533 534 switch (msg->id) { 535 case MBOX_MSG_CGX_LINK_EVENT: 536 break; 537 default: 538 if (msg->rc) 539 dev_err(pf->dev, 540 "Mbox msg response has err %d, ID 0x%x\n", 541 msg->rc, msg->id); 542 break; 543 } 544 545 end: 546 offset = mbox->rx_start + msg->next_msgoff; 547 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 548 __otx2_mbox_reset(mbox, 0); 549 mdev->msgs_acked++; 550 } 551 } 552 553 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 554 { 555 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 556 int vfs = pf->total_vfs; 557 struct mbox *mbox; 558 u64 intr; 559 560 mbox = pf->mbox_pfvf; 561 /* Handle VF interrupts */ 562 if (vfs > 64) { 563 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 564 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 566 TYPE_PFVF); 567 vfs -= 64; 568 } 569 570 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 571 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 572 573 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 574 575 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 576 577 return IRQ_HANDLED; 578 } 579 580 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 581 { 582 void __iomem *hwbase; 583 struct mbox *mbox; 584 int err, vf; 585 u64 base; 586 587 if (!numvfs) 588 return -EINVAL; 589 590 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 591 sizeof(struct mbox), GFP_KERNEL); 592 if (!pf->mbox_pfvf) 593 return -ENOMEM; 594 595 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 596 WQ_UNBOUND | WQ_HIGHPRI | 597 WQ_MEM_RECLAIM, 1); 598 if (!pf->mbox_pfvf_wq) 599 return -ENOMEM; 600 601 /* On CN10K platform, PF <-> VF mailbox region follows after 602 * PF <-> AF mailbox region. 603 */ 604 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 605 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 606 MBOX_SIZE; 607 else 608 base = readq((void __iomem *)((u64)pf->reg_base + 609 RVU_PF_VF_BAR4_ADDR)); 610 611 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 612 if (!hwbase) { 613 err = -ENOMEM; 614 goto free_wq; 615 } 616 617 mbox = &pf->mbox_pfvf[0]; 618 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF, numvfs); 620 if (err) 621 goto free_iomem; 622 623 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 624 MBOX_DIR_PFVF_UP, numvfs); 625 if (err) 626 goto free_iomem; 627 628 for (vf = 0; vf < numvfs; vf++) { 629 mbox->pfvf = pf; 630 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 631 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 632 mbox++; 633 } 634 635 return 0; 636 637 free_iomem: 638 if (hwbase) 639 iounmap(hwbase); 640 free_wq: 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 return err; 643 } 644 645 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 646 { 647 struct mbox *mbox = &pf->mbox_pfvf[0]; 648 649 if (!mbox) 650 return; 651 652 if (pf->mbox_pfvf_wq) { 653 destroy_workqueue(pf->mbox_pfvf_wq); 654 pf->mbox_pfvf_wq = NULL; 655 } 656 657 if (mbox->mbox.hwbase) 658 iounmap(mbox->mbox.hwbase); 659 660 otx2_mbox_destroy(&mbox->mbox); 661 } 662 663 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 664 { 665 /* Clear PF <=> VF mailbox IRQ */ 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 669 /* Enable PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 671 if (numvfs > 64) { 672 numvfs -= 64; 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 674 INTR_MASK(numvfs)); 675 } 676 } 677 678 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 679 { 680 int vector; 681 682 /* Disable PF <=> VF mailbox IRQ */ 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 685 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 688 free_irq(vector, pf); 689 690 if (numvfs > 64) { 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 692 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 693 free_irq(vector, pf); 694 } 695 } 696 697 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 698 { 699 struct otx2_hw *hw = &pf->hw; 700 char *irq_name; 701 int err; 702 703 /* Register MBOX0 interrupt handler */ 704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 705 if (pf->pcifunc) 706 snprintf(irq_name, NAME_SIZE, 707 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 708 else 709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 710 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 711 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 712 if (err) { 713 dev_err(pf->dev, 714 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 715 return err; 716 } 717 718 if (numvfs > 64) { 719 /* Register MBOX1 interrupt handler */ 720 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 721 if (pf->pcifunc) 722 snprintf(irq_name, NAME_SIZE, 723 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 724 else 725 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 726 err = request_irq(pci_irq_vector(pf->pdev, 727 RVU_PF_INT_VEC_VFPF_MBOX1), 728 otx2_pfvf_mbox_intr_handler, 729 0, irq_name, pf); 730 if (err) { 731 dev_err(pf->dev, 732 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 733 return err; 734 } 735 } 736 737 otx2_enable_pfvf_mbox_intr(pf, numvfs); 738 739 return 0; 740 } 741 742 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 743 struct mbox_msghdr *msg) 744 { 745 int devid; 746 747 if (msg->id >= MBOX_MSG_MAX) { 748 dev_err(pf->dev, 749 "Mbox msg with unknown ID 0x%x\n", msg->id); 750 return; 751 } 752 753 if (msg->sig != OTX2_MBOX_RSP_SIG) { 754 dev_err(pf->dev, 755 "Mbox msg with wrong signature %x, ID 0x%x\n", 756 msg->sig, msg->id); 757 return; 758 } 759 760 /* message response heading VF */ 761 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 762 if (devid) { 763 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 764 struct delayed_work *dwork; 765 766 switch (msg->id) { 767 case MBOX_MSG_NIX_LF_START_RX: 768 config->intf_down = false; 769 dwork = &config->link_event_work; 770 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 771 break; 772 case MBOX_MSG_NIX_LF_STOP_RX: 773 config->intf_down = true; 774 break; 775 } 776 777 return; 778 } 779 780 switch (msg->id) { 781 case MBOX_MSG_READY: 782 pf->pcifunc = msg->pcifunc; 783 break; 784 case MBOX_MSG_MSIX_OFFSET: 785 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 786 break; 787 case MBOX_MSG_NPA_LF_ALLOC: 788 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 789 break; 790 case MBOX_MSG_NIX_LF_ALLOC: 791 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 792 break; 793 case MBOX_MSG_NIX_TXSCH_ALLOC: 794 mbox_handler_nix_txsch_alloc(pf, 795 (struct nix_txsch_alloc_rsp *)msg); 796 break; 797 case MBOX_MSG_NIX_BP_ENABLE: 798 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_STATS: 801 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 802 break; 803 case MBOX_MSG_CGX_FEC_STATS: 804 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 805 break; 806 default: 807 if (msg->rc) 808 dev_err(pf->dev, 809 "Mbox msg response has err %d, ID 0x%x\n", 810 msg->rc, msg->id); 811 break; 812 } 813 } 814 815 static void otx2_pfaf_mbox_handler(struct work_struct *work) 816 { 817 struct otx2_mbox_dev *mdev; 818 struct mbox_hdr *rsp_hdr; 819 struct mbox_msghdr *msg; 820 struct otx2_mbox *mbox; 821 struct mbox *af_mbox; 822 struct otx2_nic *pf; 823 int offset, id; 824 825 af_mbox = container_of(work, struct mbox, mbox_wrk); 826 mbox = &af_mbox->mbox; 827 mdev = &mbox->dev[0]; 828 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 829 830 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 831 pf = af_mbox->pfvf; 832 833 for (id = 0; id < af_mbox->num_msgs; id++) { 834 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 835 otx2_process_pfaf_mbox_msg(pf, msg); 836 offset = mbox->rx_start + msg->next_msgoff; 837 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 838 __otx2_mbox_reset(mbox, 0); 839 mdev->msgs_acked++; 840 } 841 842 } 843 844 static void otx2_handle_link_event(struct otx2_nic *pf) 845 { 846 struct cgx_link_user_info *linfo = &pf->linfo; 847 struct net_device *netdev = pf->netdev; 848 849 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 850 linfo->link_up ? "UP" : "DOWN", linfo->speed, 851 linfo->full_duplex ? "Full" : "Half"); 852 if (linfo->link_up) { 853 netif_carrier_on(netdev); 854 netif_tx_start_all_queues(netdev); 855 } else { 856 netif_tx_stop_all_queues(netdev); 857 netif_carrier_off(netdev); 858 } 859 } 860 861 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 862 struct cgx_link_info_msg *msg, 863 struct msg_rsp *rsp) 864 { 865 int i; 866 867 /* Copy the link info sent by AF */ 868 pf->linfo = msg->link_info; 869 870 /* notify VFs about link event */ 871 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 872 struct otx2_vf_config *config = &pf->vf_configs[i]; 873 struct delayed_work *dwork = &config->link_event_work; 874 875 if (config->intf_down) 876 continue; 877 878 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 879 } 880 881 /* interface has not been fully configured yet */ 882 if (pf->flags & OTX2_FLAG_INTF_DOWN) 883 return 0; 884 885 otx2_handle_link_event(pf); 886 return 0; 887 } 888 889 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 890 struct mbox_msghdr *req) 891 { 892 /* Check if valid, if not reply with a invalid msg */ 893 if (req->sig != OTX2_MBOX_REQ_SIG) { 894 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 895 return -ENODEV; 896 } 897 898 switch (req->id) { 899 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 900 case _id: { \ 901 struct _rsp_type *rsp; \ 902 int err; \ 903 \ 904 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 905 &pf->mbox.mbox_up, 0, \ 906 sizeof(struct _rsp_type)); \ 907 if (!rsp) \ 908 return -ENOMEM; \ 909 \ 910 rsp->hdr.id = _id; \ 911 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 912 rsp->hdr.pcifunc = 0; \ 913 rsp->hdr.rc = 0; \ 914 \ 915 err = otx2_mbox_up_handler_ ## _fn_name( \ 916 pf, (struct _req_type *)req, rsp); \ 917 return err; \ 918 } 919 MBOX_UP_CGX_MESSAGES 920 #undef M 921 break; 922 default: 923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 924 return -ENODEV; 925 } 926 return 0; 927 } 928 929 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 930 { 931 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 932 struct otx2_mbox *mbox = &af_mbox->mbox_up; 933 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 934 struct otx2_nic *pf = af_mbox->pfvf; 935 int offset, id, devid = 0; 936 struct mbox_hdr *rsp_hdr; 937 struct mbox_msghdr *msg; 938 939 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 940 941 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 942 943 for (id = 0; id < af_mbox->up_num_msgs; id++) { 944 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 945 946 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 947 /* Skip processing VF's messages */ 948 if (!devid) 949 otx2_process_mbox_msg_up(pf, msg); 950 offset = mbox->rx_start + msg->next_msgoff; 951 } 952 if (devid) { 953 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 954 MBOX_DIR_PFVF_UP, devid - 1, 955 af_mbox->up_num_msgs); 956 return; 957 } 958 959 otx2_mbox_msg_send(mbox, 0); 960 } 961 962 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 963 { 964 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 965 struct mbox *mbox; 966 967 /* Clear the IRQ */ 968 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 969 970 mbox = &pf->mbox; 971 972 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 973 974 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 975 976 return IRQ_HANDLED; 977 } 978 979 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 980 { 981 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 982 983 /* Disable AF => PF mailbox IRQ */ 984 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 985 free_irq(vector, pf); 986 } 987 988 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 989 { 990 struct otx2_hw *hw = &pf->hw; 991 struct msg_req *req; 992 char *irq_name; 993 int err; 994 995 /* Register mailbox interrupt handler */ 996 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 997 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 998 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 999 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1000 if (err) { 1001 dev_err(pf->dev, 1002 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1003 return err; 1004 } 1005 1006 /* Enable mailbox interrupt for msgs coming from AF. 1007 * First clear to avoid spurious interrupts, if any. 1008 */ 1009 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1010 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1011 1012 if (!probe_af) 1013 return 0; 1014 1015 /* Check mailbox communication with AF */ 1016 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1017 if (!req) { 1018 otx2_disable_mbox_intr(pf); 1019 return -ENOMEM; 1020 } 1021 err = otx2_sync_mbox_msg(&pf->mbox); 1022 if (err) { 1023 dev_warn(pf->dev, 1024 "AF not responding to mailbox, deferring probe\n"); 1025 otx2_disable_mbox_intr(pf); 1026 return -EPROBE_DEFER; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1033 { 1034 struct mbox *mbox = &pf->mbox; 1035 1036 if (pf->mbox_wq) { 1037 destroy_workqueue(pf->mbox_wq); 1038 pf->mbox_wq = NULL; 1039 } 1040 1041 if (mbox->mbox.hwbase) 1042 iounmap((void __iomem *)mbox->mbox.hwbase); 1043 1044 otx2_mbox_destroy(&mbox->mbox); 1045 otx2_mbox_destroy(&mbox->mbox_up); 1046 } 1047 1048 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1049 { 1050 struct mbox *mbox = &pf->mbox; 1051 void __iomem *hwbase; 1052 int err; 1053 1054 mbox->pfvf = pf; 1055 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1056 WQ_UNBOUND | WQ_HIGHPRI | 1057 WQ_MEM_RECLAIM, 1); 1058 if (!pf->mbox_wq) 1059 return -ENOMEM; 1060 1061 /* Mailbox is a reserved memory (in RAM) region shared between 1062 * admin function (i.e AF) and this PF, shouldn't be mapped as 1063 * device memory to allow unaligned accesses. 1064 */ 1065 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1066 MBOX_SIZE); 1067 if (!hwbase) { 1068 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1069 err = -ENOMEM; 1070 goto exit; 1071 } 1072 1073 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1074 MBOX_DIR_PFAF, 1); 1075 if (err) 1076 goto exit; 1077 1078 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1079 MBOX_DIR_PFAF_UP, 1); 1080 if (err) 1081 goto exit; 1082 1083 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1084 if (err) 1085 goto exit; 1086 1087 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1088 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1089 mutex_init(&mbox->lock); 1090 1091 return 0; 1092 exit: 1093 otx2_pfaf_mbox_destroy(pf); 1094 return err; 1095 } 1096 1097 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1098 { 1099 struct msg_req *msg; 1100 int err; 1101 1102 mutex_lock(&pf->mbox.lock); 1103 if (enable) 1104 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1105 else 1106 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1107 1108 if (!msg) { 1109 mutex_unlock(&pf->mbox.lock); 1110 return -ENOMEM; 1111 } 1112 1113 err = otx2_sync_mbox_msg(&pf->mbox); 1114 mutex_unlock(&pf->mbox.lock); 1115 return err; 1116 } 1117 1118 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1119 { 1120 struct msg_req *msg; 1121 int err; 1122 1123 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap, 1124 pf->flow_cfg->dmacflt_max_flows)) 1125 netdev_warn(pf->netdev, 1126 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1127 1128 mutex_lock(&pf->mbox.lock); 1129 if (enable) 1130 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1131 else 1132 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1133 1134 if (!msg) { 1135 mutex_unlock(&pf->mbox.lock); 1136 return -ENOMEM; 1137 } 1138 1139 err = otx2_sync_mbox_msg(&pf->mbox); 1140 mutex_unlock(&pf->mbox.lock); 1141 return err; 1142 } 1143 1144 int otx2_set_real_num_queues(struct net_device *netdev, 1145 int tx_queues, int rx_queues) 1146 { 1147 int err; 1148 1149 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1150 if (err) { 1151 netdev_err(netdev, 1152 "Failed to set no of Tx queues: %d\n", tx_queues); 1153 return err; 1154 } 1155 1156 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1157 if (err) 1158 netdev_err(netdev, 1159 "Failed to set no of Rx queues: %d\n", rx_queues); 1160 return err; 1161 } 1162 EXPORT_SYMBOL(otx2_set_real_num_queues); 1163 1164 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1165 { 1166 struct otx2_nic *pf = data; 1167 u64 val, *ptr; 1168 u64 qidx = 0; 1169 1170 /* CQ */ 1171 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1172 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1173 val = otx2_atomic64_add((qidx << 44), ptr); 1174 1175 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1176 (val & NIX_CQERRINT_BITS)); 1177 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1178 continue; 1179 1180 if (val & BIT_ULL(42)) { 1181 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1182 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1183 } else { 1184 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1185 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1186 qidx); 1187 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1188 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1189 qidx); 1190 } 1191 1192 schedule_work(&pf->reset_task); 1193 } 1194 1195 /* SQ */ 1196 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1197 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1198 val = otx2_atomic64_add((qidx << 44), ptr); 1199 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1200 (val & NIX_SQINT_BITS)); 1201 1202 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1203 continue; 1204 1205 if (val & BIT_ULL(42)) { 1206 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1207 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1208 } else { 1209 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1210 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1211 qidx, 1212 otx2_read64(pf, 1213 NIX_LF_SQ_OP_ERR_DBG)); 1214 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1215 BIT_ULL(44)); 1216 } 1217 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1218 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1219 qidx, 1220 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1221 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1222 BIT_ULL(44)); 1223 } 1224 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1225 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1226 qidx, 1227 otx2_read64(pf, 1228 NIX_LF_SEND_ERR_DBG)); 1229 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1230 BIT_ULL(44)); 1231 } 1232 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1233 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1234 qidx); 1235 } 1236 1237 schedule_work(&pf->reset_task); 1238 } 1239 1240 return IRQ_HANDLED; 1241 } 1242 1243 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1244 { 1245 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1246 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1247 int qidx = cq_poll->cint_idx; 1248 1249 /* Disable interrupts. 1250 * 1251 * Completion interrupts behave in a level-triggered interrupt 1252 * fashion, and hence have to be cleared only after it is serviced. 1253 */ 1254 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1255 1256 /* Schedule NAPI */ 1257 napi_schedule_irqoff(&cq_poll->napi); 1258 1259 return IRQ_HANDLED; 1260 } 1261 1262 static void otx2_disable_napi(struct otx2_nic *pf) 1263 { 1264 struct otx2_qset *qset = &pf->qset; 1265 struct otx2_cq_poll *cq_poll; 1266 int qidx; 1267 1268 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1269 cq_poll = &qset->napi[qidx]; 1270 napi_disable(&cq_poll->napi); 1271 netif_napi_del(&cq_poll->napi); 1272 } 1273 } 1274 1275 static void otx2_free_cq_res(struct otx2_nic *pf) 1276 { 1277 struct otx2_qset *qset = &pf->qset; 1278 struct otx2_cq_queue *cq; 1279 int qidx; 1280 1281 /* Disable CQs */ 1282 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1283 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1284 cq = &qset->cq[qidx]; 1285 qmem_free(pf->dev, cq->cqe); 1286 } 1287 } 1288 1289 static void otx2_free_sq_res(struct otx2_nic *pf) 1290 { 1291 struct otx2_qset *qset = &pf->qset; 1292 struct otx2_snd_queue *sq; 1293 int qidx; 1294 1295 /* Disable SQs */ 1296 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1297 /* Free SQB pointers */ 1298 otx2_sq_free_sqbs(pf); 1299 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1300 sq = &qset->sq[qidx]; 1301 qmem_free(pf->dev, sq->sqe); 1302 qmem_free(pf->dev, sq->tso_hdrs); 1303 kfree(sq->sg); 1304 kfree(sq->sqb_ptrs); 1305 } 1306 } 1307 1308 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1309 { 1310 int frame_size; 1311 int total_size; 1312 int rbuf_size; 1313 1314 /* The data transferred by NIX to memory consists of actual packet 1315 * plus additional data which has timestamp and/or EDSA/HIGIG2 1316 * headers if interface is configured in corresponding modes. 1317 * NIX transfers entire data using 6 segments/buffers and writes 1318 * a CQE_RX descriptor with those segment addresses. First segment 1319 * has additional data prepended to packet. Also software omits a 1320 * headroom of 128 bytes in each segment. Hence the total size of 1321 * memory needed to receive a packet with 'mtu' is: 1322 * frame size = mtu + additional data; 1323 * memory = frame_size + headroom * 6; 1324 * each receive buffer size = memory / 6; 1325 */ 1326 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1327 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1328 rbuf_size = total_size / 6; 1329 1330 return ALIGN(rbuf_size, 2048); 1331 } 1332 1333 static int otx2_init_hw_resources(struct otx2_nic *pf) 1334 { 1335 struct nix_lf_free_req *free_req; 1336 struct mbox *mbox = &pf->mbox; 1337 struct otx2_hw *hw = &pf->hw; 1338 struct msg_req *req; 1339 int err = 0, lvl; 1340 1341 /* Set required NPA LF's pool counts 1342 * Auras and Pools are used in a 1:1 mapping, 1343 * so, aura count = pool count. 1344 */ 1345 hw->rqpool_cnt = hw->rx_queues; 1346 hw->sqpool_cnt = hw->tot_tx_queues; 1347 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1348 1349 /* Maximum hardware supported transmit length */ 1350 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1351 1352 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1353 1354 mutex_lock(&mbox->lock); 1355 /* NPA init */ 1356 err = otx2_config_npa(pf); 1357 if (err) 1358 goto exit; 1359 1360 /* NIX init */ 1361 err = otx2_config_nix(pf); 1362 if (err) 1363 goto err_free_npa_lf; 1364 1365 /* Enable backpressure */ 1366 otx2_nix_config_bp(pf, true); 1367 1368 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1369 err = otx2_rq_aura_pool_init(pf); 1370 if (err) { 1371 mutex_unlock(&mbox->lock); 1372 goto err_free_nix_lf; 1373 } 1374 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1375 err = otx2_sq_aura_pool_init(pf); 1376 if (err) { 1377 mutex_unlock(&mbox->lock); 1378 goto err_free_rq_ptrs; 1379 } 1380 1381 err = otx2_txsch_alloc(pf); 1382 if (err) { 1383 mutex_unlock(&mbox->lock); 1384 goto err_free_sq_ptrs; 1385 } 1386 1387 err = otx2_config_nix_queues(pf); 1388 if (err) { 1389 mutex_unlock(&mbox->lock); 1390 goto err_free_txsch; 1391 } 1392 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1393 err = otx2_txschq_config(pf, lvl); 1394 if (err) { 1395 mutex_unlock(&mbox->lock); 1396 goto err_free_nix_queues; 1397 } 1398 } 1399 mutex_unlock(&mbox->lock); 1400 return err; 1401 1402 err_free_nix_queues: 1403 otx2_free_sq_res(pf); 1404 otx2_free_cq_res(pf); 1405 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1406 err_free_txsch: 1407 if (otx2_txschq_stop(pf)) 1408 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1409 err_free_sq_ptrs: 1410 otx2_sq_free_sqbs(pf); 1411 err_free_rq_ptrs: 1412 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1413 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1414 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1415 otx2_aura_pool_free(pf); 1416 err_free_nix_lf: 1417 mutex_lock(&mbox->lock); 1418 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1419 if (free_req) { 1420 free_req->flags = NIX_LF_DISABLE_FLOWS; 1421 if (otx2_sync_mbox_msg(mbox)) 1422 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1423 } 1424 err_free_npa_lf: 1425 /* Reset NPA LF */ 1426 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1427 if (req) { 1428 if (otx2_sync_mbox_msg(mbox)) 1429 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1430 } 1431 exit: 1432 mutex_unlock(&mbox->lock); 1433 return err; 1434 } 1435 1436 static void otx2_free_hw_resources(struct otx2_nic *pf) 1437 { 1438 struct otx2_qset *qset = &pf->qset; 1439 struct nix_lf_free_req *free_req; 1440 struct mbox *mbox = &pf->mbox; 1441 struct otx2_cq_queue *cq; 1442 struct msg_req *req; 1443 int qidx, err; 1444 1445 /* Ensure all SQE are processed */ 1446 otx2_sqb_flush(pf); 1447 1448 /* Stop transmission */ 1449 err = otx2_txschq_stop(pf); 1450 if (err) 1451 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1452 1453 mutex_lock(&mbox->lock); 1454 /* Disable backpressure */ 1455 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1456 otx2_nix_config_bp(pf, false); 1457 mutex_unlock(&mbox->lock); 1458 1459 /* Disable RQs */ 1460 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1461 1462 /*Dequeue all CQEs */ 1463 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1464 cq = &qset->cq[qidx]; 1465 if (cq->cq_type == CQ_RX) 1466 otx2_cleanup_rx_cqes(pf, cq); 1467 else 1468 otx2_cleanup_tx_cqes(pf, cq); 1469 } 1470 1471 otx2_free_sq_res(pf); 1472 1473 /* Free RQ buffer pointers*/ 1474 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1475 1476 otx2_free_cq_res(pf); 1477 1478 /* Free all ingress bandwidth profiles allocated */ 1479 cn10k_free_all_ipolicers(pf); 1480 1481 mutex_lock(&mbox->lock); 1482 /* Reset NIX LF */ 1483 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1484 if (free_req) { 1485 free_req->flags = NIX_LF_DISABLE_FLOWS; 1486 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1487 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1488 if (otx2_sync_mbox_msg(mbox)) 1489 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1490 } 1491 mutex_unlock(&mbox->lock); 1492 1493 /* Disable NPA Pool and Aura hw context */ 1494 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1495 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1496 otx2_aura_pool_free(pf); 1497 1498 mutex_lock(&mbox->lock); 1499 /* Reset NPA LF */ 1500 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1501 if (req) { 1502 if (otx2_sync_mbox_msg(mbox)) 1503 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1504 } 1505 mutex_unlock(&mbox->lock); 1506 } 1507 1508 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1509 { 1510 struct net_device *netdev = pf->netdev; 1511 struct nix_rx_mode *req; 1512 bool promisc = false; 1513 1514 if (!(netdev->flags & IFF_UP)) 1515 return; 1516 1517 if ((netdev->flags & IFF_PROMISC) || 1518 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1519 promisc = true; 1520 } 1521 1522 /* Write unicast address to mcam entries or del from mcam */ 1523 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1524 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1525 1526 mutex_lock(&pf->mbox.lock); 1527 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1528 if (!req) { 1529 mutex_unlock(&pf->mbox.lock); 1530 return; 1531 } 1532 1533 req->mode = NIX_RX_MODE_UCAST; 1534 1535 if (promisc) 1536 req->mode |= NIX_RX_MODE_PROMISC; 1537 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1538 req->mode |= NIX_RX_MODE_ALLMULTI; 1539 1540 req->mode |= NIX_RX_MODE_USE_MCE; 1541 1542 otx2_sync_mbox_msg(&pf->mbox); 1543 mutex_unlock(&pf->mbox.lock); 1544 } 1545 1546 int otx2_open(struct net_device *netdev) 1547 { 1548 struct otx2_nic *pf = netdev_priv(netdev); 1549 struct otx2_cq_poll *cq_poll = NULL; 1550 struct otx2_qset *qset = &pf->qset; 1551 int err = 0, qidx, vec; 1552 char *irq_name; 1553 1554 netif_carrier_off(netdev); 1555 1556 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1557 /* RQ and SQs are mapped to different CQs, 1558 * so find out max CQ IRQs (i.e CINTs) needed. 1559 */ 1560 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1561 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1562 if (!qset->napi) 1563 return -ENOMEM; 1564 1565 /* CQ size of RQ */ 1566 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1567 /* CQ size of SQ */ 1568 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1569 1570 err = -ENOMEM; 1571 qset->cq = kcalloc(pf->qset.cq_cnt, 1572 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1573 if (!qset->cq) 1574 goto err_free_mem; 1575 1576 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1577 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1578 if (!qset->sq) 1579 goto err_free_mem; 1580 1581 qset->rq = kcalloc(pf->hw.rx_queues, 1582 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1583 if (!qset->rq) 1584 goto err_free_mem; 1585 1586 err = otx2_init_hw_resources(pf); 1587 if (err) 1588 goto err_free_mem; 1589 1590 /* Register NAPI handler */ 1591 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1592 cq_poll = &qset->napi[qidx]; 1593 cq_poll->cint_idx = qidx; 1594 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1595 * 'cq_ids[0]' points to RQ's CQ and 1596 * 'cq_ids[1]' points to SQ's CQ and 1597 * 'cq_ids[2]' points to XDP's CQ and 1598 */ 1599 cq_poll->cq_ids[CQ_RX] = 1600 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1601 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1602 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1603 if (pf->xdp_prog) 1604 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1605 (qidx + pf->hw.rx_queues + 1606 pf->hw.tx_queues) : 1607 CINT_INVALID_CQ; 1608 else 1609 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1610 1611 cq_poll->dev = (void *)pf; 1612 netif_napi_add(netdev, &cq_poll->napi, 1613 otx2_napi_handler, NAPI_POLL_WEIGHT); 1614 napi_enable(&cq_poll->napi); 1615 } 1616 1617 /* Set maximum frame size allowed in HW */ 1618 err = otx2_hw_set_mtu(pf, netdev->mtu); 1619 if (err) 1620 goto err_disable_napi; 1621 1622 /* Setup segmentation algorithms, if failed, clear offload capability */ 1623 otx2_setup_segmentation(pf); 1624 1625 /* Initialize RSS */ 1626 err = otx2_rss_init(pf); 1627 if (err) 1628 goto err_disable_napi; 1629 1630 /* Register Queue IRQ handlers */ 1631 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1632 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1633 1634 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1635 1636 err = request_irq(pci_irq_vector(pf->pdev, vec), 1637 otx2_q_intr_handler, 0, irq_name, pf); 1638 if (err) { 1639 dev_err(pf->dev, 1640 "RVUPF%d: IRQ registration failed for QERR\n", 1641 rvu_get_pf(pf->pcifunc)); 1642 goto err_disable_napi; 1643 } 1644 1645 /* Enable QINT IRQ */ 1646 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1647 1648 /* Register CQ IRQ handlers */ 1649 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1650 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1651 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1652 1653 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1654 qidx); 1655 1656 err = request_irq(pci_irq_vector(pf->pdev, vec), 1657 otx2_cq_intr_handler, 0, irq_name, 1658 &qset->napi[qidx]); 1659 if (err) { 1660 dev_err(pf->dev, 1661 "RVUPF%d: IRQ registration failed for CQ%d\n", 1662 rvu_get_pf(pf->pcifunc), qidx); 1663 goto err_free_cints; 1664 } 1665 vec++; 1666 1667 otx2_config_irq_coalescing(pf, qidx); 1668 1669 /* Enable CQ IRQ */ 1670 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1671 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1672 } 1673 1674 otx2_set_cints_affinity(pf); 1675 1676 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1677 otx2_enable_rxvlan(pf, true); 1678 1679 /* When reinitializing enable time stamping if it is enabled before */ 1680 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1681 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1682 otx2_config_hw_tx_tstamp(pf, true); 1683 } 1684 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1685 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1686 otx2_config_hw_rx_tstamp(pf, true); 1687 } 1688 1689 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1690 /* 'intf_down' may be checked on any cpu */ 1691 smp_wmb(); 1692 1693 /* we have already received link status notification */ 1694 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1695 otx2_handle_link_event(pf); 1696 1697 /* Restore pause frame settings */ 1698 otx2_config_pause_frm(pf); 1699 1700 /* Install DMAC Filters */ 1701 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1702 otx2_dmacflt_reinstall_flows(pf); 1703 1704 err = otx2_rxtx_enable(pf, true); 1705 if (err) 1706 goto err_tx_stop_queues; 1707 1708 otx2_do_set_rx_mode(pf); 1709 1710 return 0; 1711 1712 err_tx_stop_queues: 1713 netif_tx_stop_all_queues(netdev); 1714 netif_carrier_off(netdev); 1715 pf->flags |= OTX2_FLAG_INTF_DOWN; 1716 err_free_cints: 1717 otx2_free_cints(pf, qidx); 1718 vec = pci_irq_vector(pf->pdev, 1719 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1720 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1721 synchronize_irq(vec); 1722 free_irq(vec, pf); 1723 err_disable_napi: 1724 otx2_disable_napi(pf); 1725 otx2_free_hw_resources(pf); 1726 err_free_mem: 1727 kfree(qset->sq); 1728 kfree(qset->cq); 1729 kfree(qset->rq); 1730 kfree(qset->napi); 1731 return err; 1732 } 1733 EXPORT_SYMBOL(otx2_open); 1734 1735 int otx2_stop(struct net_device *netdev) 1736 { 1737 struct otx2_nic *pf = netdev_priv(netdev); 1738 struct otx2_cq_poll *cq_poll = NULL; 1739 struct otx2_qset *qset = &pf->qset; 1740 struct otx2_rss_info *rss; 1741 int qidx, vec, wrk; 1742 1743 /* If the DOWN flag is set resources are already freed */ 1744 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1745 return 0; 1746 1747 netif_carrier_off(netdev); 1748 netif_tx_stop_all_queues(netdev); 1749 1750 pf->flags |= OTX2_FLAG_INTF_DOWN; 1751 /* 'intf_down' may be checked on any cpu */ 1752 smp_wmb(); 1753 1754 /* First stop packet Rx/Tx */ 1755 otx2_rxtx_enable(pf, false); 1756 1757 /* Clear RSS enable flag */ 1758 rss = &pf->hw.rss_info; 1759 rss->enable = false; 1760 1761 /* Cleanup Queue IRQ */ 1762 vec = pci_irq_vector(pf->pdev, 1763 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1764 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1765 synchronize_irq(vec); 1766 free_irq(vec, pf); 1767 1768 /* Cleanup CQ NAPI and IRQ */ 1769 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1770 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1771 /* Disable interrupt */ 1772 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1773 1774 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1775 1776 cq_poll = &qset->napi[qidx]; 1777 napi_synchronize(&cq_poll->napi); 1778 vec++; 1779 } 1780 1781 netif_tx_disable(netdev); 1782 1783 otx2_free_hw_resources(pf); 1784 otx2_free_cints(pf, pf->hw.cint_cnt); 1785 otx2_disable_napi(pf); 1786 1787 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1788 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1789 1790 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1791 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1792 devm_kfree(pf->dev, pf->refill_wrk); 1793 1794 kfree(qset->sq); 1795 kfree(qset->cq); 1796 kfree(qset->rq); 1797 kfree(qset->napi); 1798 /* Do not clear RQ/SQ ringsize settings */ 1799 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1800 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1801 return 0; 1802 } 1803 EXPORT_SYMBOL(otx2_stop); 1804 1805 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1806 { 1807 struct otx2_nic *pf = netdev_priv(netdev); 1808 int qidx = skb_get_queue_mapping(skb); 1809 struct otx2_snd_queue *sq; 1810 struct netdev_queue *txq; 1811 1812 /* Check for minimum and maximum packet length */ 1813 if (skb->len <= ETH_HLEN || 1814 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1815 dev_kfree_skb(skb); 1816 return NETDEV_TX_OK; 1817 } 1818 1819 sq = &pf->qset.sq[qidx]; 1820 txq = netdev_get_tx_queue(netdev, qidx); 1821 1822 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1823 netif_tx_stop_queue(txq); 1824 1825 /* Check again, incase SQBs got freed up */ 1826 smp_mb(); 1827 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1828 > sq->sqe_thresh) 1829 netif_tx_wake_queue(txq); 1830 1831 return NETDEV_TX_BUSY; 1832 } 1833 1834 return NETDEV_TX_OK; 1835 } 1836 1837 static netdev_features_t otx2_fix_features(struct net_device *dev, 1838 netdev_features_t features) 1839 { 1840 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1841 features |= NETIF_F_HW_VLAN_STAG_RX; 1842 else 1843 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1844 1845 return features; 1846 } 1847 1848 static void otx2_set_rx_mode(struct net_device *netdev) 1849 { 1850 struct otx2_nic *pf = netdev_priv(netdev); 1851 1852 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1853 } 1854 1855 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 1856 { 1857 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1858 1859 otx2_do_set_rx_mode(pf); 1860 } 1861 1862 static int otx2_set_features(struct net_device *netdev, 1863 netdev_features_t features) 1864 { 1865 netdev_features_t changed = features ^ netdev->features; 1866 bool ntuple = !!(features & NETIF_F_NTUPLE); 1867 struct otx2_nic *pf = netdev_priv(netdev); 1868 bool tc = !!(features & NETIF_F_HW_TC); 1869 1870 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1871 return otx2_cgx_config_loopback(pf, 1872 features & NETIF_F_LOOPBACK); 1873 1874 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1875 return otx2_enable_rxvlan(pf, 1876 features & NETIF_F_HW_VLAN_CTAG_RX); 1877 1878 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1879 otx2_destroy_ntuple_flows(pf); 1880 1881 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1882 if (!pf->flow_cfg->max_flows) { 1883 netdev_err(netdev, 1884 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1885 return -EINVAL; 1886 } 1887 } 1888 1889 if ((changed & NETIF_F_HW_TC) && tc) { 1890 if (!pf->flow_cfg->max_flows) { 1891 netdev_err(netdev, 1892 "Can't enable TC, MCAM entries not allocated\n"); 1893 return -EINVAL; 1894 } 1895 } 1896 1897 if ((changed & NETIF_F_HW_TC) && !tc && 1898 pf->flow_cfg && pf->flow_cfg->nr_flows) { 1899 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1900 return -EBUSY; 1901 } 1902 1903 if ((changed & NETIF_F_NTUPLE) && ntuple && 1904 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1905 netdev_err(netdev, 1906 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1907 return -EINVAL; 1908 } 1909 1910 if ((changed & NETIF_F_HW_TC) && tc && 1911 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1912 netdev_err(netdev, 1913 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1914 return -EINVAL; 1915 } 1916 1917 return 0; 1918 } 1919 1920 static void otx2_reset_task(struct work_struct *work) 1921 { 1922 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1923 1924 if (!netif_running(pf->netdev)) 1925 return; 1926 1927 rtnl_lock(); 1928 otx2_stop(pf->netdev); 1929 pf->reset_count++; 1930 otx2_open(pf->netdev); 1931 netif_trans_update(pf->netdev); 1932 rtnl_unlock(); 1933 } 1934 1935 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1936 { 1937 struct msg_req *req; 1938 int err; 1939 1940 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1941 return 0; 1942 1943 mutex_lock(&pfvf->mbox.lock); 1944 if (enable) 1945 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1946 else 1947 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1948 if (!req) { 1949 mutex_unlock(&pfvf->mbox.lock); 1950 return -ENOMEM; 1951 } 1952 1953 err = otx2_sync_mbox_msg(&pfvf->mbox); 1954 if (err) { 1955 mutex_unlock(&pfvf->mbox.lock); 1956 return err; 1957 } 1958 1959 mutex_unlock(&pfvf->mbox.lock); 1960 if (enable) 1961 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1962 else 1963 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1964 return 0; 1965 } 1966 1967 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1968 { 1969 struct msg_req *req; 1970 int err; 1971 1972 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1973 return 0; 1974 1975 mutex_lock(&pfvf->mbox.lock); 1976 if (enable) 1977 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1978 else 1979 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1980 if (!req) { 1981 mutex_unlock(&pfvf->mbox.lock); 1982 return -ENOMEM; 1983 } 1984 1985 err = otx2_sync_mbox_msg(&pfvf->mbox); 1986 if (err) { 1987 mutex_unlock(&pfvf->mbox.lock); 1988 return err; 1989 } 1990 1991 mutex_unlock(&pfvf->mbox.lock); 1992 if (enable) 1993 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1994 else 1995 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1996 return 0; 1997 } 1998 1999 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2000 { 2001 struct otx2_nic *pfvf = netdev_priv(netdev); 2002 struct hwtstamp_config config; 2003 2004 if (!pfvf->ptp) 2005 return -ENODEV; 2006 2007 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2008 return -EFAULT; 2009 2010 switch (config.tx_type) { 2011 case HWTSTAMP_TX_OFF: 2012 otx2_config_hw_tx_tstamp(pfvf, false); 2013 break; 2014 case HWTSTAMP_TX_ON: 2015 otx2_config_hw_tx_tstamp(pfvf, true); 2016 break; 2017 default: 2018 return -ERANGE; 2019 } 2020 2021 switch (config.rx_filter) { 2022 case HWTSTAMP_FILTER_NONE: 2023 otx2_config_hw_rx_tstamp(pfvf, false); 2024 break; 2025 case HWTSTAMP_FILTER_ALL: 2026 case HWTSTAMP_FILTER_SOME: 2027 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2028 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2029 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2030 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2031 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2032 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2033 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2034 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2035 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2036 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2037 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2038 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2039 otx2_config_hw_rx_tstamp(pfvf, true); 2040 config.rx_filter = HWTSTAMP_FILTER_ALL; 2041 break; 2042 default: 2043 return -ERANGE; 2044 } 2045 2046 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2047 2048 return copy_to_user(ifr->ifr_data, &config, 2049 sizeof(config)) ? -EFAULT : 0; 2050 } 2051 EXPORT_SYMBOL(otx2_config_hwtstamp); 2052 2053 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2054 { 2055 struct otx2_nic *pfvf = netdev_priv(netdev); 2056 struct hwtstamp_config *cfg = &pfvf->tstamp; 2057 2058 switch (cmd) { 2059 case SIOCSHWTSTAMP: 2060 return otx2_config_hwtstamp(netdev, req); 2061 case SIOCGHWTSTAMP: 2062 return copy_to_user(req->ifr_data, cfg, 2063 sizeof(*cfg)) ? -EFAULT : 0; 2064 default: 2065 return -EOPNOTSUPP; 2066 } 2067 } 2068 EXPORT_SYMBOL(otx2_ioctl); 2069 2070 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2071 { 2072 struct npc_install_flow_req *req; 2073 int err; 2074 2075 mutex_lock(&pf->mbox.lock); 2076 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2077 if (!req) { 2078 err = -ENOMEM; 2079 goto out; 2080 } 2081 2082 ether_addr_copy(req->packet.dmac, mac); 2083 eth_broadcast_addr((u8 *)&req->mask.dmac); 2084 req->features = BIT_ULL(NPC_DMAC); 2085 req->channel = pf->hw.rx_chan_base; 2086 req->intf = NIX_INTF_RX; 2087 req->default_rule = 1; 2088 req->append = 1; 2089 req->vf = vf + 1; 2090 req->op = NIX_RX_ACTION_DEFAULT; 2091 2092 err = otx2_sync_mbox_msg(&pf->mbox); 2093 out: 2094 mutex_unlock(&pf->mbox.lock); 2095 return err; 2096 } 2097 2098 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2099 { 2100 struct otx2_nic *pf = netdev_priv(netdev); 2101 struct pci_dev *pdev = pf->pdev; 2102 struct otx2_vf_config *config; 2103 int ret; 2104 2105 if (!netif_running(netdev)) 2106 return -EAGAIN; 2107 2108 if (vf >= pf->total_vfs) 2109 return -EINVAL; 2110 2111 if (!is_valid_ether_addr(mac)) 2112 return -EINVAL; 2113 2114 config = &pf->vf_configs[vf]; 2115 ether_addr_copy(config->mac, mac); 2116 2117 ret = otx2_do_set_vf_mac(pf, vf, mac); 2118 if (ret == 0) 2119 dev_info(&pdev->dev, 2120 "Load/Reload VF driver\n"); 2121 2122 return ret; 2123 } 2124 2125 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2126 __be16 proto) 2127 { 2128 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2129 struct nix_vtag_config_rsp *vtag_rsp; 2130 struct npc_delete_flow_req *del_req; 2131 struct nix_vtag_config *vtag_req; 2132 struct npc_install_flow_req *req; 2133 struct otx2_vf_config *config; 2134 int err = 0; 2135 u32 idx; 2136 2137 config = &pf->vf_configs[vf]; 2138 2139 if (!vlan && !config->vlan) 2140 goto out; 2141 2142 mutex_lock(&pf->mbox.lock); 2143 2144 /* free old tx vtag entry */ 2145 if (config->vlan) { 2146 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2147 if (!vtag_req) { 2148 err = -ENOMEM; 2149 goto out; 2150 } 2151 vtag_req->cfg_type = 0; 2152 vtag_req->tx.free_vtag0 = 1; 2153 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2154 2155 err = otx2_sync_mbox_msg(&pf->mbox); 2156 if (err) 2157 goto out; 2158 } 2159 2160 if (!vlan && config->vlan) { 2161 /* rx */ 2162 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2163 if (!del_req) { 2164 err = -ENOMEM; 2165 goto out; 2166 } 2167 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2168 del_req->entry = 2169 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2170 err = otx2_sync_mbox_msg(&pf->mbox); 2171 if (err) 2172 goto out; 2173 2174 /* tx */ 2175 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2176 if (!del_req) { 2177 err = -ENOMEM; 2178 goto out; 2179 } 2180 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2181 del_req->entry = 2182 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2183 err = otx2_sync_mbox_msg(&pf->mbox); 2184 2185 goto out; 2186 } 2187 2188 /* rx */ 2189 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2190 if (!req) { 2191 err = -ENOMEM; 2192 goto out; 2193 } 2194 2195 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2196 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2197 req->packet.vlan_tci = htons(vlan); 2198 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2199 /* af fills the destination mac addr */ 2200 eth_broadcast_addr((u8 *)&req->mask.dmac); 2201 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2202 req->channel = pf->hw.rx_chan_base; 2203 req->intf = NIX_INTF_RX; 2204 req->vf = vf + 1; 2205 req->op = NIX_RX_ACTION_DEFAULT; 2206 req->vtag0_valid = true; 2207 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2208 req->set_cntr = 1; 2209 2210 err = otx2_sync_mbox_msg(&pf->mbox); 2211 if (err) 2212 goto out; 2213 2214 /* tx */ 2215 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2216 if (!vtag_req) { 2217 err = -ENOMEM; 2218 goto out; 2219 } 2220 2221 /* configure tx vtag params */ 2222 vtag_req->vtag_size = VTAGSIZE_T4; 2223 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2224 vtag_req->tx.cfg_vtag0 = 1; 2225 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2226 2227 err = otx2_sync_mbox_msg(&pf->mbox); 2228 if (err) 2229 goto out; 2230 2231 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2232 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2233 if (IS_ERR(vtag_rsp)) { 2234 err = PTR_ERR(vtag_rsp); 2235 goto out; 2236 } 2237 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2238 2239 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2240 if (!req) { 2241 err = -ENOMEM; 2242 goto out; 2243 } 2244 2245 eth_zero_addr((u8 *)&req->mask.dmac); 2246 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2247 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2248 req->features = BIT_ULL(NPC_DMAC); 2249 req->channel = pf->hw.tx_chan_base; 2250 req->intf = NIX_INTF_TX; 2251 req->vf = vf + 1; 2252 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2253 req->vtag0_def = vtag_rsp->vtag0_idx; 2254 req->vtag0_op = VTAG_INSERT; 2255 req->set_cntr = 1; 2256 2257 err = otx2_sync_mbox_msg(&pf->mbox); 2258 out: 2259 config->vlan = vlan; 2260 mutex_unlock(&pf->mbox.lock); 2261 return err; 2262 } 2263 2264 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2265 __be16 proto) 2266 { 2267 struct otx2_nic *pf = netdev_priv(netdev); 2268 struct pci_dev *pdev = pf->pdev; 2269 2270 if (!netif_running(netdev)) 2271 return -EAGAIN; 2272 2273 if (vf >= pci_num_vf(pdev)) 2274 return -EINVAL; 2275 2276 /* qos is currently unsupported */ 2277 if (vlan >= VLAN_N_VID || qos) 2278 return -EINVAL; 2279 2280 if (proto != htons(ETH_P_8021Q)) 2281 return -EPROTONOSUPPORT; 2282 2283 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2284 return -EOPNOTSUPP; 2285 2286 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2287 } 2288 2289 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2290 struct ifla_vf_info *ivi) 2291 { 2292 struct otx2_nic *pf = netdev_priv(netdev); 2293 struct pci_dev *pdev = pf->pdev; 2294 struct otx2_vf_config *config; 2295 2296 if (!netif_running(netdev)) 2297 return -EAGAIN; 2298 2299 if (vf >= pci_num_vf(pdev)) 2300 return -EINVAL; 2301 2302 config = &pf->vf_configs[vf]; 2303 ivi->vf = vf; 2304 ether_addr_copy(ivi->mac, config->mac); 2305 ivi->vlan = config->vlan; 2306 ivi->trusted = config->trusted; 2307 2308 return 0; 2309 } 2310 2311 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2312 int qidx) 2313 { 2314 struct page *page; 2315 u64 dma_addr; 2316 int err = 0; 2317 2318 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2319 offset_in_page(xdpf->data), xdpf->len, 2320 DMA_TO_DEVICE); 2321 if (dma_mapping_error(pf->dev, dma_addr)) 2322 return -ENOMEM; 2323 2324 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2325 if (!err) { 2326 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2327 page = virt_to_page(xdpf->data); 2328 put_page(page); 2329 return -ENOMEM; 2330 } 2331 return 0; 2332 } 2333 2334 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2335 struct xdp_frame **frames, u32 flags) 2336 { 2337 struct otx2_nic *pf = netdev_priv(netdev); 2338 int qidx = smp_processor_id(); 2339 struct otx2_snd_queue *sq; 2340 int drops = 0, i; 2341 2342 if (!netif_running(netdev)) 2343 return -ENETDOWN; 2344 2345 qidx += pf->hw.tx_queues; 2346 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2347 2348 /* Abort xmit if xdp queue is not */ 2349 if (unlikely(!sq)) 2350 return -ENXIO; 2351 2352 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2353 return -EINVAL; 2354 2355 for (i = 0; i < n; i++) { 2356 struct xdp_frame *xdpf = frames[i]; 2357 int err; 2358 2359 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2360 if (err) 2361 drops++; 2362 } 2363 return n - drops; 2364 } 2365 2366 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2367 { 2368 struct net_device *dev = pf->netdev; 2369 bool if_up = netif_running(pf->netdev); 2370 struct bpf_prog *old_prog; 2371 2372 if (prog && dev->mtu > MAX_XDP_MTU) { 2373 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2374 return -EOPNOTSUPP; 2375 } 2376 2377 if (if_up) 2378 otx2_stop(pf->netdev); 2379 2380 old_prog = xchg(&pf->xdp_prog, prog); 2381 2382 if (old_prog) 2383 bpf_prog_put(old_prog); 2384 2385 if (pf->xdp_prog) 2386 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2387 2388 /* Network stack and XDP shared same rx queues. 2389 * Use separate tx queues for XDP and network stack. 2390 */ 2391 if (pf->xdp_prog) 2392 pf->hw.xdp_queues = pf->hw.rx_queues; 2393 else 2394 pf->hw.xdp_queues = 0; 2395 2396 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2397 2398 if (if_up) 2399 otx2_open(pf->netdev); 2400 2401 return 0; 2402 } 2403 2404 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2405 { 2406 struct otx2_nic *pf = netdev_priv(netdev); 2407 2408 switch (xdp->command) { 2409 case XDP_SETUP_PROG: 2410 return otx2_xdp_setup(pf, xdp->prog); 2411 default: 2412 return -EINVAL; 2413 } 2414 } 2415 2416 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2417 int req_perm) 2418 { 2419 struct set_vf_perm *req; 2420 int rc; 2421 2422 mutex_lock(&pf->mbox.lock); 2423 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2424 if (!req) { 2425 rc = -ENOMEM; 2426 goto out; 2427 } 2428 2429 /* Let AF reset VF permissions as sriov is disabled */ 2430 if (req_perm == OTX2_RESET_VF_PERM) { 2431 req->flags |= RESET_VF_PERM; 2432 } else if (req_perm == OTX2_TRUSTED_VF) { 2433 if (pf->vf_configs[vf].trusted) 2434 req->flags |= VF_TRUSTED; 2435 } 2436 2437 req->vf = vf; 2438 rc = otx2_sync_mbox_msg(&pf->mbox); 2439 out: 2440 mutex_unlock(&pf->mbox.lock); 2441 return rc; 2442 } 2443 2444 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2445 bool enable) 2446 { 2447 struct otx2_nic *pf = netdev_priv(netdev); 2448 struct pci_dev *pdev = pf->pdev; 2449 int rc; 2450 2451 if (vf >= pci_num_vf(pdev)) 2452 return -EINVAL; 2453 2454 if (pf->vf_configs[vf].trusted == enable) 2455 return 0; 2456 2457 pf->vf_configs[vf].trusted = enable; 2458 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2459 2460 if (rc) 2461 pf->vf_configs[vf].trusted = !enable; 2462 else 2463 netdev_info(pf->netdev, "VF %d is %strusted\n", 2464 vf, enable ? "" : "not "); 2465 return rc; 2466 } 2467 2468 static const struct net_device_ops otx2_netdev_ops = { 2469 .ndo_open = otx2_open, 2470 .ndo_stop = otx2_stop, 2471 .ndo_start_xmit = otx2_xmit, 2472 .ndo_fix_features = otx2_fix_features, 2473 .ndo_set_mac_address = otx2_set_mac_address, 2474 .ndo_change_mtu = otx2_change_mtu, 2475 .ndo_set_rx_mode = otx2_set_rx_mode, 2476 .ndo_set_features = otx2_set_features, 2477 .ndo_tx_timeout = otx2_tx_timeout, 2478 .ndo_get_stats64 = otx2_get_stats64, 2479 .ndo_eth_ioctl = otx2_ioctl, 2480 .ndo_set_vf_mac = otx2_set_vf_mac, 2481 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2482 .ndo_get_vf_config = otx2_get_vf_config, 2483 .ndo_bpf = otx2_xdp, 2484 .ndo_xdp_xmit = otx2_xdp_xmit, 2485 .ndo_setup_tc = otx2_setup_tc, 2486 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2487 }; 2488 2489 static int otx2_wq_init(struct otx2_nic *pf) 2490 { 2491 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2492 if (!pf->otx2_wq) 2493 return -ENOMEM; 2494 2495 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2496 INIT_WORK(&pf->reset_task, otx2_reset_task); 2497 return 0; 2498 } 2499 2500 static int otx2_check_pf_usable(struct otx2_nic *nic) 2501 { 2502 u64 rev; 2503 2504 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2505 rev = (rev >> 12) & 0xFF; 2506 /* Check if AF has setup revision for RVUM block, 2507 * otherwise this driver probe should be deferred 2508 * until AF driver comes up. 2509 */ 2510 if (!rev) { 2511 dev_warn(nic->dev, 2512 "AF is not initialized, deferring probe\n"); 2513 return -EPROBE_DEFER; 2514 } 2515 return 0; 2516 } 2517 2518 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2519 { 2520 struct otx2_hw *hw = &pf->hw; 2521 int num_vec, err; 2522 2523 /* NPA interrupts are inot registered, so alloc only 2524 * upto NIX vector offset. 2525 */ 2526 num_vec = hw->nix_msixoff; 2527 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2528 2529 otx2_disable_mbox_intr(pf); 2530 pci_free_irq_vectors(hw->pdev); 2531 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2532 if (err < 0) { 2533 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2534 __func__, num_vec); 2535 return err; 2536 } 2537 2538 return otx2_register_mbox_intr(pf, false); 2539 } 2540 2541 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2542 { 2543 int i; 2544 2545 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2546 sizeof(struct otx2_vf_config), 2547 GFP_KERNEL); 2548 if (!pf->vf_configs) 2549 return -ENOMEM; 2550 2551 for (i = 0; i < pf->total_vfs; i++) { 2552 pf->vf_configs[i].pf = pf; 2553 pf->vf_configs[i].intf_down = true; 2554 pf->vf_configs[i].trusted = false; 2555 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2556 otx2_vf_link_event_task); 2557 } 2558 2559 return 0; 2560 } 2561 2562 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2563 { 2564 int i; 2565 2566 if (!pf->vf_configs) 2567 return; 2568 2569 for (i = 0; i < pf->total_vfs; i++) { 2570 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2571 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2572 } 2573 } 2574 2575 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2576 { 2577 struct device *dev = &pdev->dev; 2578 struct net_device *netdev; 2579 struct otx2_nic *pf; 2580 struct otx2_hw *hw; 2581 int err, qcount; 2582 int num_vec; 2583 2584 err = pcim_enable_device(pdev); 2585 if (err) { 2586 dev_err(dev, "Failed to enable PCI device\n"); 2587 return err; 2588 } 2589 2590 err = pci_request_regions(pdev, DRV_NAME); 2591 if (err) { 2592 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2593 return err; 2594 } 2595 2596 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2597 if (err) { 2598 dev_err(dev, "DMA mask config failed, abort\n"); 2599 goto err_release_regions; 2600 } 2601 2602 pci_set_master(pdev); 2603 2604 /* Set number of queues */ 2605 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2606 2607 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2608 if (!netdev) { 2609 err = -ENOMEM; 2610 goto err_release_regions; 2611 } 2612 2613 pci_set_drvdata(pdev, netdev); 2614 SET_NETDEV_DEV(netdev, &pdev->dev); 2615 pf = netdev_priv(netdev); 2616 pf->netdev = netdev; 2617 pf->pdev = pdev; 2618 pf->dev = dev; 2619 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2620 pf->flags |= OTX2_FLAG_INTF_DOWN; 2621 2622 hw = &pf->hw; 2623 hw->pdev = pdev; 2624 hw->rx_queues = qcount; 2625 hw->tx_queues = qcount; 2626 hw->tot_tx_queues = qcount; 2627 hw->max_queues = qcount; 2628 2629 num_vec = pci_msix_vec_count(pdev); 2630 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2631 GFP_KERNEL); 2632 if (!hw->irq_name) { 2633 err = -ENOMEM; 2634 goto err_free_netdev; 2635 } 2636 2637 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2638 sizeof(cpumask_var_t), GFP_KERNEL); 2639 if (!hw->affinity_mask) { 2640 err = -ENOMEM; 2641 goto err_free_netdev; 2642 } 2643 2644 /* Map CSRs */ 2645 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2646 if (!pf->reg_base) { 2647 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2648 err = -ENOMEM; 2649 goto err_free_netdev; 2650 } 2651 2652 err = otx2_check_pf_usable(pf); 2653 if (err) 2654 goto err_free_netdev; 2655 2656 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2657 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2658 if (err < 0) { 2659 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2660 __func__, num_vec); 2661 goto err_free_netdev; 2662 } 2663 2664 otx2_setup_dev_hw_settings(pf); 2665 2666 /* Init PF <=> AF mailbox stuff */ 2667 err = otx2_pfaf_mbox_init(pf); 2668 if (err) 2669 goto err_free_irq_vectors; 2670 2671 /* Register mailbox interrupt */ 2672 err = otx2_register_mbox_intr(pf, true); 2673 if (err) 2674 goto err_mbox_destroy; 2675 2676 /* Request AF to attach NPA and NIX LFs to this PF. 2677 * NIX and NPA LFs are needed for this PF to function as a NIC. 2678 */ 2679 err = otx2_attach_npa_nix(pf); 2680 if (err) 2681 goto err_disable_mbox_intr; 2682 2683 err = otx2_realloc_msix_vectors(pf); 2684 if (err) 2685 goto err_detach_rsrc; 2686 2687 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2688 if (err) 2689 goto err_detach_rsrc; 2690 2691 err = cn10k_lmtst_init(pf); 2692 if (err) 2693 goto err_detach_rsrc; 2694 2695 /* Assign default mac address */ 2696 otx2_get_mac_from_af(netdev); 2697 2698 /* Don't check for error. Proceed without ptp */ 2699 otx2_ptp_init(pf); 2700 2701 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2702 * HW allocates buffer pointer from stack and uses it for DMA'ing 2703 * ingress packet. In some scenarios HW can free back allocated buffer 2704 * pointers to pool. This makes it impossible for SW to maintain a 2705 * parallel list where physical addresses of buffer pointers (IOVAs) 2706 * given to HW can be saved for later reference. 2707 * 2708 * So the only way to convert Rx packet's buffer address is to use 2709 * IOMMU's iova_to_phys() handler which translates the address by 2710 * walking through the translation tables. 2711 */ 2712 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2713 2714 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2715 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2716 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2717 NETIF_F_GSO_UDP_L4); 2718 netdev->features |= netdev->hw_features; 2719 2720 err = otx2_mcam_flow_init(pf); 2721 if (err) 2722 goto err_ptp_destroy; 2723 2724 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2725 netdev->hw_features |= NETIF_F_NTUPLE; 2726 2727 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2728 netdev->priv_flags |= IFF_UNICAST_FLT; 2729 2730 /* Support TSO on tag interface */ 2731 netdev->vlan_features |= netdev->features; 2732 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2733 NETIF_F_HW_VLAN_STAG_TX; 2734 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2735 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2736 NETIF_F_HW_VLAN_STAG_RX; 2737 netdev->features |= netdev->hw_features; 2738 2739 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2740 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2741 netdev->hw_features |= NETIF_F_HW_TC; 2742 2743 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2744 2745 netif_set_gso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2746 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2747 2748 netdev->netdev_ops = &otx2_netdev_ops; 2749 2750 netdev->min_mtu = OTX2_MIN_MTU; 2751 netdev->max_mtu = otx2_get_max_mtu(pf); 2752 2753 err = register_netdev(netdev); 2754 if (err) { 2755 dev_err(dev, "Failed to register netdevice\n"); 2756 goto err_del_mcam_entries; 2757 } 2758 2759 err = otx2_wq_init(pf); 2760 if (err) 2761 goto err_unreg_netdev; 2762 2763 otx2_set_ethtool_ops(netdev); 2764 2765 err = otx2_init_tc(pf); 2766 if (err) 2767 goto err_mcam_flow_del; 2768 2769 err = otx2_register_dl(pf); 2770 if (err) 2771 goto err_mcam_flow_del; 2772 2773 /* Initialize SR-IOV resources */ 2774 err = otx2_sriov_vfcfg_init(pf); 2775 if (err) 2776 goto err_pf_sriov_init; 2777 2778 /* Enable link notifications */ 2779 otx2_cgx_config_linkevents(pf, true); 2780 2781 /* Enable pause frames by default */ 2782 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2783 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2784 2785 return 0; 2786 2787 err_pf_sriov_init: 2788 otx2_shutdown_tc(pf); 2789 err_mcam_flow_del: 2790 otx2_mcam_flow_del(pf); 2791 err_unreg_netdev: 2792 unregister_netdev(netdev); 2793 err_del_mcam_entries: 2794 otx2_mcam_flow_del(pf); 2795 err_ptp_destroy: 2796 otx2_ptp_destroy(pf); 2797 err_detach_rsrc: 2798 if (pf->hw.lmt_info) 2799 free_percpu(pf->hw.lmt_info); 2800 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2801 qmem_free(pf->dev, pf->dync_lmt); 2802 otx2_detach_resources(&pf->mbox); 2803 err_disable_mbox_intr: 2804 otx2_disable_mbox_intr(pf); 2805 err_mbox_destroy: 2806 otx2_pfaf_mbox_destroy(pf); 2807 err_free_irq_vectors: 2808 pci_free_irq_vectors(hw->pdev); 2809 err_free_netdev: 2810 pci_set_drvdata(pdev, NULL); 2811 free_netdev(netdev); 2812 err_release_regions: 2813 pci_release_regions(pdev); 2814 return err; 2815 } 2816 2817 static void otx2_vf_link_event_task(struct work_struct *work) 2818 { 2819 struct otx2_vf_config *config; 2820 struct cgx_link_info_msg *req; 2821 struct mbox_msghdr *msghdr; 2822 struct otx2_nic *pf; 2823 int vf_idx; 2824 2825 config = container_of(work, struct otx2_vf_config, 2826 link_event_work.work); 2827 vf_idx = config - config->pf->vf_configs; 2828 pf = config->pf; 2829 2830 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2831 sizeof(*req), sizeof(struct msg_rsp)); 2832 if (!msghdr) { 2833 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2834 return; 2835 } 2836 2837 req = (struct cgx_link_info_msg *)msghdr; 2838 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2839 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2840 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2841 2842 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2843 } 2844 2845 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2846 { 2847 struct net_device *netdev = pci_get_drvdata(pdev); 2848 struct otx2_nic *pf = netdev_priv(netdev); 2849 int ret; 2850 2851 /* Init PF <=> VF mailbox stuff */ 2852 ret = otx2_pfvf_mbox_init(pf, numvfs); 2853 if (ret) 2854 return ret; 2855 2856 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2857 if (ret) 2858 goto free_mbox; 2859 2860 ret = otx2_pf_flr_init(pf, numvfs); 2861 if (ret) 2862 goto free_intr; 2863 2864 ret = otx2_register_flr_me_intr(pf, numvfs); 2865 if (ret) 2866 goto free_flr; 2867 2868 ret = pci_enable_sriov(pdev, numvfs); 2869 if (ret) 2870 goto free_flr_intr; 2871 2872 return numvfs; 2873 free_flr_intr: 2874 otx2_disable_flr_me_intr(pf); 2875 free_flr: 2876 otx2_flr_wq_destroy(pf); 2877 free_intr: 2878 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2879 free_mbox: 2880 otx2_pfvf_mbox_destroy(pf); 2881 return ret; 2882 } 2883 2884 static int otx2_sriov_disable(struct pci_dev *pdev) 2885 { 2886 struct net_device *netdev = pci_get_drvdata(pdev); 2887 struct otx2_nic *pf = netdev_priv(netdev); 2888 int numvfs = pci_num_vf(pdev); 2889 2890 if (!numvfs) 2891 return 0; 2892 2893 pci_disable_sriov(pdev); 2894 2895 otx2_disable_flr_me_intr(pf); 2896 otx2_flr_wq_destroy(pf); 2897 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2898 otx2_pfvf_mbox_destroy(pf); 2899 2900 return 0; 2901 } 2902 2903 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2904 { 2905 if (numvfs == 0) 2906 return otx2_sriov_disable(pdev); 2907 else 2908 return otx2_sriov_enable(pdev, numvfs); 2909 } 2910 2911 static void otx2_remove(struct pci_dev *pdev) 2912 { 2913 struct net_device *netdev = pci_get_drvdata(pdev); 2914 struct otx2_nic *pf; 2915 2916 if (!netdev) 2917 return; 2918 2919 pf = netdev_priv(netdev); 2920 2921 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2922 2923 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2924 otx2_config_hw_tx_tstamp(pf, false); 2925 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2926 otx2_config_hw_rx_tstamp(pf, false); 2927 2928 cancel_work_sync(&pf->reset_task); 2929 /* Disable link notifications */ 2930 otx2_cgx_config_linkevents(pf, false); 2931 2932 otx2_unregister_dl(pf); 2933 unregister_netdev(netdev); 2934 otx2_sriov_disable(pf->pdev); 2935 otx2_sriov_vfcfg_cleanup(pf); 2936 if (pf->otx2_wq) 2937 destroy_workqueue(pf->otx2_wq); 2938 2939 otx2_ptp_destroy(pf); 2940 otx2_mcam_flow_del(pf); 2941 otx2_shutdown_tc(pf); 2942 otx2_detach_resources(&pf->mbox); 2943 if (pf->hw.lmt_info) 2944 free_percpu(pf->hw.lmt_info); 2945 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2946 qmem_free(pf->dev, pf->dync_lmt); 2947 otx2_disable_mbox_intr(pf); 2948 otx2_pfaf_mbox_destroy(pf); 2949 pci_free_irq_vectors(pf->pdev); 2950 pci_set_drvdata(pdev, NULL); 2951 free_netdev(netdev); 2952 2953 pci_release_regions(pdev); 2954 } 2955 2956 static struct pci_driver otx2_pf_driver = { 2957 .name = DRV_NAME, 2958 .id_table = otx2_pf_id_table, 2959 .probe = otx2_probe, 2960 .shutdown = otx2_remove, 2961 .remove = otx2_remove, 2962 .sriov_configure = otx2_sriov_configure 2963 }; 2964 2965 static int __init otx2_rvupf_init_module(void) 2966 { 2967 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2968 2969 return pci_register_driver(&otx2_pf_driver); 2970 } 2971 2972 static void __exit otx2_rvupf_cleanup_module(void) 2973 { 2974 pci_unregister_driver(&otx2_pf_driver); 2975 } 2976 2977 module_init(otx2_rvupf_init_module); 2978 module_exit(otx2_rvupf_cleanup_module); 2979