1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of.h> 16 #include <linux/if_vlan.h> 17 #include <linux/iommu.h> 18 #include <net/ip.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include "cn10k.h" 26 #include <rvu_trace.h> 27 28 #define DRV_NAME "rvu_nicpf" 29 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 30 31 /* Supported devices */ 32 static const struct pci_device_id otx2_pf_id_table[] = { 33 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 34 { 0, } /* end of table */ 35 }; 36 37 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 38 MODULE_DESCRIPTION(DRV_STRING); 39 MODULE_LICENSE("GPL v2"); 40 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 41 42 static void otx2_vf_link_event_task(struct work_struct *work); 43 44 enum { 45 TYPE_PFAF, 46 TYPE_PFVF, 47 }; 48 49 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 50 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 51 52 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 53 { 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (if_up) 58 otx2_stop(netdev); 59 60 netdev_info(netdev, "Changing MTU from %d to %d\n", 61 netdev->mtu, new_mtu); 62 netdev->mtu = new_mtu; 63 64 if (if_up) 65 err = otx2_open(netdev); 66 67 return err; 68 } 69 70 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 71 { 72 int irq, vfs = pf->total_vfs; 73 74 /* Disable VFs ME interrupts */ 75 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 76 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 77 free_irq(irq, pf); 78 79 /* Disable VFs FLR interrupts */ 80 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 82 free_irq(irq, pf); 83 84 if (vfs <= 64) 85 return; 86 87 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 88 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 89 free_irq(irq, pf); 90 91 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 92 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 93 free_irq(irq, pf); 94 } 95 96 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 97 { 98 if (!pf->flr_wq) 99 return; 100 destroy_workqueue(pf->flr_wq); 101 pf->flr_wq = NULL; 102 devm_kfree(pf->dev, pf->flr_wrk); 103 } 104 105 static void otx2_flr_handler(struct work_struct *work) 106 { 107 struct flr_work *flrwork = container_of(work, struct flr_work, work); 108 struct otx2_nic *pf = flrwork->pf; 109 struct mbox *mbox = &pf->mbox; 110 struct msg_req *req; 111 int vf, reg = 0; 112 113 vf = flrwork - pf->flr_wrk; 114 115 mutex_lock(&mbox->lock); 116 req = otx2_mbox_alloc_msg_vf_flr(mbox); 117 if (!req) { 118 mutex_unlock(&mbox->lock); 119 return; 120 } 121 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 122 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 123 124 if (!otx2_sync_mbox_msg(&pf->mbox)) { 125 if (vf >= 64) { 126 reg = 1; 127 vf = vf - 64; 128 } 129 /* clear transcation pending bit */ 130 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 131 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 132 } 133 134 mutex_unlock(&mbox->lock); 135 } 136 137 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 138 { 139 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 140 int reg, dev, vf, start_vf, num_reg = 1; 141 u64 intr; 142 143 if (pf->total_vfs > 64) 144 num_reg = 2; 145 146 for (reg = 0; reg < num_reg; reg++) { 147 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 148 if (!intr) 149 continue; 150 start_vf = 64 * reg; 151 for (vf = 0; vf < 64; vf++) { 152 if (!(intr & BIT_ULL(vf))) 153 continue; 154 dev = vf + start_vf; 155 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 156 /* Clear interrupt */ 157 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 158 /* Disable the interrupt */ 159 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 160 BIT_ULL(vf)); 161 } 162 } 163 return IRQ_HANDLED; 164 } 165 166 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 167 { 168 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 169 int vf, reg, num_reg = 1; 170 u64 intr; 171 172 if (pf->total_vfs > 64) 173 num_reg = 2; 174 175 for (reg = 0; reg < num_reg; reg++) { 176 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 177 if (!intr) 178 continue; 179 for (vf = 0; vf < 64; vf++) { 180 if (!(intr & BIT_ULL(vf))) 181 continue; 182 /* clear trpend bit */ 183 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 184 /* clear interrupt */ 185 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 186 } 187 } 188 return IRQ_HANDLED; 189 } 190 191 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 192 { 193 struct otx2_hw *hw = &pf->hw; 194 char *irq_name; 195 int ret; 196 197 /* Register ME interrupt handler*/ 198 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 199 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 200 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 201 otx2_pf_me_intr_handler, 0, irq_name, pf); 202 if (ret) { 203 dev_err(pf->dev, 204 "RVUPF: IRQ registration failed for ME0\n"); 205 } 206 207 /* Register FLR interrupt handler */ 208 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 209 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 210 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 211 otx2_pf_flr_intr_handler, 0, irq_name, pf); 212 if (ret) { 213 dev_err(pf->dev, 214 "RVUPF: IRQ registration failed for FLR0\n"); 215 return ret; 216 } 217 218 if (numvfs > 64) { 219 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 220 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 221 rvu_get_pf(pf->pcifunc)); 222 ret = request_irq(pci_irq_vector 223 (pf->pdev, RVU_PF_INT_VEC_VFME1), 224 otx2_pf_me_intr_handler, 0, irq_name, pf); 225 if (ret) { 226 dev_err(pf->dev, 227 "RVUPF: IRQ registration failed for ME1\n"); 228 } 229 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 230 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 231 rvu_get_pf(pf->pcifunc)); 232 ret = request_irq(pci_irq_vector 233 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 234 otx2_pf_flr_intr_handler, 0, irq_name, pf); 235 if (ret) { 236 dev_err(pf->dev, 237 "RVUPF: IRQ registration failed for FLR1\n"); 238 return ret; 239 } 240 } 241 242 /* Enable ME interrupt for all VFs*/ 243 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 244 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 245 246 /* Enable FLR interrupt for all VFs*/ 247 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 248 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 249 250 if (numvfs > 64) { 251 numvfs -= 64; 252 253 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 255 INTR_MASK(numvfs)); 256 257 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 258 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 259 INTR_MASK(numvfs)); 260 } 261 return 0; 262 } 263 264 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 265 { 266 int vf; 267 268 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 269 WQ_UNBOUND | WQ_HIGHPRI, 1); 270 if (!pf->flr_wq) 271 return -ENOMEM; 272 273 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 274 sizeof(struct flr_work), GFP_KERNEL); 275 if (!pf->flr_wrk) { 276 destroy_workqueue(pf->flr_wq); 277 return -ENOMEM; 278 } 279 280 for (vf = 0; vf < num_vfs; vf++) { 281 pf->flr_wrk[vf].pf = pf; 282 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 283 } 284 285 return 0; 286 } 287 288 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 289 int first, int mdevs, u64 intr, int type) 290 { 291 struct otx2_mbox_dev *mdev; 292 struct otx2_mbox *mbox; 293 struct mbox_hdr *hdr; 294 int i; 295 296 for (i = first; i < mdevs; i++) { 297 /* start from 0 */ 298 if (!(intr & BIT_ULL(i - first))) 299 continue; 300 301 mbox = &mw->mbox; 302 mdev = &mbox->dev[i]; 303 if (type == TYPE_PFAF) 304 otx2_sync_mbox_bbuf(mbox, i); 305 hdr = mdev->mbase + mbox->rx_start; 306 /* The hdr->num_msgs is set to zero immediately in the interrupt 307 * handler to ensure that it holds a correct value next time 308 * when the interrupt handler is called. 309 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 310 * pf>mbox.up_num_msgs holds the data for use in 311 * pfaf_mbox_up_handler. 312 */ 313 if (hdr->num_msgs) { 314 mw[i].num_msgs = hdr->num_msgs; 315 hdr->num_msgs = 0; 316 if (type == TYPE_PFAF) 317 memset(mbox->hwbase + mbox->rx_start, 0, 318 ALIGN(sizeof(struct mbox_hdr), 319 sizeof(u64))); 320 321 queue_work(mbox_wq, &mw[i].mbox_wrk); 322 } 323 324 mbox = &mw->mbox_up; 325 mdev = &mbox->dev[i]; 326 if (type == TYPE_PFAF) 327 otx2_sync_mbox_bbuf(mbox, i); 328 hdr = mdev->mbase + mbox->rx_start; 329 if (hdr->num_msgs) { 330 mw[i].up_num_msgs = hdr->num_msgs; 331 hdr->num_msgs = 0; 332 if (type == TYPE_PFAF) 333 memset(mbox->hwbase + mbox->rx_start, 0, 334 ALIGN(sizeof(struct mbox_hdr), 335 sizeof(u64))); 336 337 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 338 } 339 } 340 } 341 342 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 343 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 344 int devid) 345 { 346 struct otx2_mbox_dev *src_mdev = mdev; 347 int offset; 348 349 /* Msgs are already copied, trigger VF's mbox irq */ 350 smp_wmb(); 351 352 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 353 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 354 355 /* Restore VF's mbox bounce buffer region address */ 356 src_mdev->mbase = bbuf_base; 357 } 358 359 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 360 struct otx2_mbox *src_mbox, 361 int dir, int vf, int num_msgs) 362 { 363 struct otx2_mbox_dev *src_mdev, *dst_mdev; 364 struct mbox_hdr *mbox_hdr; 365 struct mbox_hdr *req_hdr; 366 struct mbox *dst_mbox; 367 int dst_size, err; 368 369 if (dir == MBOX_DIR_PFAF) { 370 /* Set VF's mailbox memory as PF's bounce buffer memory, so 371 * that explicit copying of VF's msgs to PF=>AF mbox region 372 * and AF=>PF responses to VF's mbox region can be avoided. 373 */ 374 src_mdev = &src_mbox->dev[vf]; 375 mbox_hdr = src_mbox->hwbase + 376 src_mbox->rx_start + (vf * MBOX_SIZE); 377 378 dst_mbox = &pf->mbox; 379 dst_size = dst_mbox->mbox.tx_size - 380 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 381 /* Check if msgs fit into destination area and has valid size */ 382 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 383 return -EINVAL; 384 385 dst_mdev = &dst_mbox->mbox.dev[0]; 386 387 mutex_lock(&pf->mbox.lock); 388 dst_mdev->mbase = src_mdev->mbase; 389 dst_mdev->msg_size = mbox_hdr->msg_size; 390 dst_mdev->num_msgs = num_msgs; 391 err = otx2_sync_mbox_msg(dst_mbox); 392 if (err) { 393 dev_warn(pf->dev, 394 "AF not responding to VF%d messages\n", vf); 395 /* restore PF mbase and exit */ 396 dst_mdev->mbase = pf->mbox.bbuf_base; 397 mutex_unlock(&pf->mbox.lock); 398 return err; 399 } 400 /* At this point, all the VF messages sent to AF are acked 401 * with proper responses and responses are copied to VF 402 * mailbox hence raise interrupt to VF. 403 */ 404 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 405 dst_mbox->mbox.rx_start); 406 req_hdr->num_msgs = num_msgs; 407 408 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 409 pf->mbox.bbuf_base, vf); 410 mutex_unlock(&pf->mbox.lock); 411 } else if (dir == MBOX_DIR_PFVF_UP) { 412 src_mdev = &src_mbox->dev[0]; 413 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 414 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 415 src_mbox->rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 dst_mbox = &pf->mbox_pfvf[0]; 419 dst_size = dst_mbox->mbox_up.tx_size - 420 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 421 /* Check if msgs fit into destination area */ 422 if (mbox_hdr->msg_size > dst_size) 423 return -EINVAL; 424 425 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 426 dst_mdev->mbase = src_mdev->mbase; 427 dst_mdev->msg_size = mbox_hdr->msg_size; 428 dst_mdev->num_msgs = mbox_hdr->num_msgs; 429 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 430 if (err) { 431 dev_warn(pf->dev, 432 "VF%d is not responding to mailbox\n", vf); 433 return err; 434 } 435 } else if (dir == MBOX_DIR_VFPF_UP) { 436 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 437 src_mbox->rx_start); 438 req_hdr->num_msgs = num_msgs; 439 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 440 &pf->mbox.mbox_up, 441 pf->mbox_pfvf[vf].bbuf_base, 442 0); 443 } 444 445 return 0; 446 } 447 448 static void otx2_pfvf_mbox_handler(struct work_struct *work) 449 { 450 struct mbox_msghdr *msg = NULL; 451 int offset, vf_idx, id, err; 452 struct otx2_mbox_dev *mdev; 453 struct mbox_hdr *req_hdr; 454 struct otx2_mbox *mbox; 455 struct mbox *vf_mbox; 456 struct otx2_nic *pf; 457 458 vf_mbox = container_of(work, struct mbox, mbox_wrk); 459 pf = vf_mbox->pfvf; 460 vf_idx = vf_mbox - pf->mbox_pfvf; 461 462 mbox = &pf->mbox_pfvf[0].mbox; 463 mdev = &mbox->dev[vf_idx]; 464 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 465 466 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 467 468 for (id = 0; id < vf_mbox->num_msgs; id++) { 469 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 470 offset); 471 472 if (msg->sig != OTX2_MBOX_REQ_SIG) 473 goto inval_msg; 474 475 /* Set VF's number in each of the msg */ 476 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 477 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 478 offset = msg->next_msgoff; 479 } 480 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 481 vf_mbox->num_msgs); 482 if (err) 483 goto inval_msg; 484 return; 485 486 inval_msg: 487 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 488 otx2_mbox_msg_send(mbox, vf_idx); 489 } 490 491 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 492 { 493 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 494 struct otx2_nic *pf = vf_mbox->pfvf; 495 struct otx2_mbox_dev *mdev; 496 int offset, id, vf_idx = 0; 497 struct mbox_hdr *rsp_hdr; 498 struct mbox_msghdr *msg; 499 struct otx2_mbox *mbox; 500 501 vf_idx = vf_mbox - pf->mbox_pfvf; 502 mbox = &pf->mbox_pfvf[0].mbox_up; 503 mdev = &mbox->dev[vf_idx]; 504 505 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 506 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 507 508 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 509 msg = mdev->mbase + offset; 510 511 if (msg->id >= MBOX_MSG_MAX) { 512 dev_err(pf->dev, 513 "Mbox msg with unknown ID 0x%x\n", msg->id); 514 goto end; 515 } 516 517 if (msg->sig != OTX2_MBOX_RSP_SIG) { 518 dev_err(pf->dev, 519 "Mbox msg with wrong signature %x, ID 0x%x\n", 520 msg->sig, msg->id); 521 goto end; 522 } 523 524 switch (msg->id) { 525 case MBOX_MSG_CGX_LINK_EVENT: 526 break; 527 default: 528 if (msg->rc) 529 dev_err(pf->dev, 530 "Mbox msg response has err %d, ID 0x%x\n", 531 msg->rc, msg->id); 532 break; 533 } 534 535 end: 536 offset = mbox->rx_start + msg->next_msgoff; 537 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 538 __otx2_mbox_reset(mbox, 0); 539 mdev->msgs_acked++; 540 } 541 } 542 543 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 544 { 545 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 546 int vfs = pf->total_vfs; 547 struct mbox *mbox; 548 u64 intr; 549 550 mbox = pf->mbox_pfvf; 551 /* Handle VF interrupts */ 552 if (vfs > 64) { 553 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 554 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 555 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 556 TYPE_PFVF); 557 vfs -= 64; 558 } 559 560 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 561 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 562 563 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 564 565 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 566 567 return IRQ_HANDLED; 568 } 569 570 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 571 { 572 void __iomem *hwbase; 573 struct mbox *mbox; 574 int err, vf; 575 u64 base; 576 577 if (!numvfs) 578 return -EINVAL; 579 580 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 581 sizeof(struct mbox), GFP_KERNEL); 582 if (!pf->mbox_pfvf) 583 return -ENOMEM; 584 585 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 586 WQ_UNBOUND | WQ_HIGHPRI | 587 WQ_MEM_RECLAIM, 1); 588 if (!pf->mbox_pfvf_wq) 589 return -ENOMEM; 590 591 /* On CN10K platform, PF <-> VF mailbox region follows after 592 * PF <-> AF mailbox region. 593 */ 594 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 595 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 596 MBOX_SIZE; 597 else 598 base = readq((void __iomem *)((u64)pf->reg_base + 599 RVU_PF_VF_BAR4_ADDR)); 600 601 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 602 if (!hwbase) { 603 err = -ENOMEM; 604 goto free_wq; 605 } 606 607 mbox = &pf->mbox_pfvf[0]; 608 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 609 MBOX_DIR_PFVF, numvfs); 610 if (err) 611 goto free_iomem; 612 613 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 614 MBOX_DIR_PFVF_UP, numvfs); 615 if (err) 616 goto free_iomem; 617 618 for (vf = 0; vf < numvfs; vf++) { 619 mbox->pfvf = pf; 620 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 621 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 622 mbox++; 623 } 624 625 return 0; 626 627 free_iomem: 628 if (hwbase) 629 iounmap(hwbase); 630 free_wq: 631 destroy_workqueue(pf->mbox_pfvf_wq); 632 return err; 633 } 634 635 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 636 { 637 struct mbox *mbox = &pf->mbox_pfvf[0]; 638 639 if (!mbox) 640 return; 641 642 if (pf->mbox_pfvf_wq) { 643 destroy_workqueue(pf->mbox_pfvf_wq); 644 pf->mbox_pfvf_wq = NULL; 645 } 646 647 if (mbox->mbox.hwbase) 648 iounmap(mbox->mbox.hwbase); 649 650 otx2_mbox_destroy(&mbox->mbox); 651 } 652 653 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 654 { 655 /* Clear PF <=> VF mailbox IRQ */ 656 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 657 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 658 659 /* Enable PF <=> VF mailbox IRQ */ 660 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 661 if (numvfs > 64) { 662 numvfs -= 64; 663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 664 INTR_MASK(numvfs)); 665 } 666 } 667 668 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 669 { 670 int vector; 671 672 /* Disable PF <=> VF mailbox IRQ */ 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 675 676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 677 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 678 free_irq(vector, pf); 679 680 if (numvfs > 64) { 681 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 682 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 683 free_irq(vector, pf); 684 } 685 } 686 687 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 688 { 689 struct otx2_hw *hw = &pf->hw; 690 char *irq_name; 691 int err; 692 693 /* Register MBOX0 interrupt handler */ 694 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 695 if (pf->pcifunc) 696 snprintf(irq_name, NAME_SIZE, 697 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 698 else 699 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 700 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 701 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 702 if (err) { 703 dev_err(pf->dev, 704 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 705 return err; 706 } 707 708 if (numvfs > 64) { 709 /* Register MBOX1 interrupt handler */ 710 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 711 if (pf->pcifunc) 712 snprintf(irq_name, NAME_SIZE, 713 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 714 else 715 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 716 err = request_irq(pci_irq_vector(pf->pdev, 717 RVU_PF_INT_VEC_VFPF_MBOX1), 718 otx2_pfvf_mbox_intr_handler, 719 0, irq_name, pf); 720 if (err) { 721 dev_err(pf->dev, 722 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 723 return err; 724 } 725 } 726 727 otx2_enable_pfvf_mbox_intr(pf, numvfs); 728 729 return 0; 730 } 731 732 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 733 struct mbox_msghdr *msg) 734 { 735 int devid; 736 737 if (msg->id >= MBOX_MSG_MAX) { 738 dev_err(pf->dev, 739 "Mbox msg with unknown ID 0x%x\n", msg->id); 740 return; 741 } 742 743 if (msg->sig != OTX2_MBOX_RSP_SIG) { 744 dev_err(pf->dev, 745 "Mbox msg with wrong signature %x, ID 0x%x\n", 746 msg->sig, msg->id); 747 return; 748 } 749 750 /* message response heading VF */ 751 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 752 if (devid) { 753 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 754 struct delayed_work *dwork; 755 756 switch (msg->id) { 757 case MBOX_MSG_NIX_LF_START_RX: 758 config->intf_down = false; 759 dwork = &config->link_event_work; 760 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 761 break; 762 case MBOX_MSG_NIX_LF_STOP_RX: 763 config->intf_down = true; 764 break; 765 } 766 767 return; 768 } 769 770 switch (msg->id) { 771 case MBOX_MSG_READY: 772 pf->pcifunc = msg->pcifunc; 773 break; 774 case MBOX_MSG_MSIX_OFFSET: 775 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 776 break; 777 case MBOX_MSG_NPA_LF_ALLOC: 778 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 779 break; 780 case MBOX_MSG_NIX_LF_ALLOC: 781 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 782 break; 783 case MBOX_MSG_NIX_TXSCH_ALLOC: 784 mbox_handler_nix_txsch_alloc(pf, 785 (struct nix_txsch_alloc_rsp *)msg); 786 break; 787 case MBOX_MSG_NIX_BP_ENABLE: 788 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 789 break; 790 case MBOX_MSG_CGX_STATS: 791 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 792 break; 793 case MBOX_MSG_CGX_FEC_STATS: 794 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 795 break; 796 default: 797 if (msg->rc) 798 dev_err(pf->dev, 799 "Mbox msg response has err %d, ID 0x%x\n", 800 msg->rc, msg->id); 801 break; 802 } 803 } 804 805 static void otx2_pfaf_mbox_handler(struct work_struct *work) 806 { 807 struct otx2_mbox_dev *mdev; 808 struct mbox_hdr *rsp_hdr; 809 struct mbox_msghdr *msg; 810 struct otx2_mbox *mbox; 811 struct mbox *af_mbox; 812 struct otx2_nic *pf; 813 int offset, id; 814 815 af_mbox = container_of(work, struct mbox, mbox_wrk); 816 mbox = &af_mbox->mbox; 817 mdev = &mbox->dev[0]; 818 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 819 820 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 821 pf = af_mbox->pfvf; 822 823 for (id = 0; id < af_mbox->num_msgs; id++) { 824 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 825 otx2_process_pfaf_mbox_msg(pf, msg); 826 offset = mbox->rx_start + msg->next_msgoff; 827 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 828 __otx2_mbox_reset(mbox, 0); 829 mdev->msgs_acked++; 830 } 831 832 } 833 834 static void otx2_handle_link_event(struct otx2_nic *pf) 835 { 836 struct cgx_link_user_info *linfo = &pf->linfo; 837 struct net_device *netdev = pf->netdev; 838 839 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 840 linfo->link_up ? "UP" : "DOWN", linfo->speed, 841 linfo->full_duplex ? "Full" : "Half"); 842 if (linfo->link_up) { 843 netif_carrier_on(netdev); 844 netif_tx_start_all_queues(netdev); 845 } else { 846 netif_tx_stop_all_queues(netdev); 847 netif_carrier_off(netdev); 848 } 849 } 850 851 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 852 struct cgx_link_info_msg *msg, 853 struct msg_rsp *rsp) 854 { 855 int i; 856 857 /* Copy the link info sent by AF */ 858 pf->linfo = msg->link_info; 859 860 /* notify VFs about link event */ 861 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 862 struct otx2_vf_config *config = &pf->vf_configs[i]; 863 struct delayed_work *dwork = &config->link_event_work; 864 865 if (config->intf_down) 866 continue; 867 868 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 869 } 870 871 /* interface has not been fully configured yet */ 872 if (pf->flags & OTX2_FLAG_INTF_DOWN) 873 return 0; 874 875 otx2_handle_link_event(pf); 876 return 0; 877 } 878 879 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 880 struct mbox_msghdr *req) 881 { 882 /* Check if valid, if not reply with a invalid msg */ 883 if (req->sig != OTX2_MBOX_REQ_SIG) { 884 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 885 return -ENODEV; 886 } 887 888 switch (req->id) { 889 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 890 case _id: { \ 891 struct _rsp_type *rsp; \ 892 int err; \ 893 \ 894 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 895 &pf->mbox.mbox_up, 0, \ 896 sizeof(struct _rsp_type)); \ 897 if (!rsp) \ 898 return -ENOMEM; \ 899 \ 900 rsp->hdr.id = _id; \ 901 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 902 rsp->hdr.pcifunc = 0; \ 903 rsp->hdr.rc = 0; \ 904 \ 905 err = otx2_mbox_up_handler_ ## _fn_name( \ 906 pf, (struct _req_type *)req, rsp); \ 907 return err; \ 908 } 909 MBOX_UP_CGX_MESSAGES 910 #undef M 911 break; 912 default: 913 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 914 return -ENODEV; 915 } 916 return 0; 917 } 918 919 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 920 { 921 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 922 struct otx2_mbox *mbox = &af_mbox->mbox_up; 923 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 924 struct otx2_nic *pf = af_mbox->pfvf; 925 int offset, id, devid = 0; 926 struct mbox_hdr *rsp_hdr; 927 struct mbox_msghdr *msg; 928 929 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 930 931 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 932 933 for (id = 0; id < af_mbox->up_num_msgs; id++) { 934 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 935 936 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 937 /* Skip processing VF's messages */ 938 if (!devid) 939 otx2_process_mbox_msg_up(pf, msg); 940 offset = mbox->rx_start + msg->next_msgoff; 941 } 942 if (devid) { 943 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 944 MBOX_DIR_PFVF_UP, devid - 1, 945 af_mbox->up_num_msgs); 946 return; 947 } 948 949 otx2_mbox_msg_send(mbox, 0); 950 } 951 952 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 953 { 954 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 955 struct mbox *mbox; 956 957 /* Clear the IRQ */ 958 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 959 960 mbox = &pf->mbox; 961 962 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 963 964 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 965 966 return IRQ_HANDLED; 967 } 968 969 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 970 { 971 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 972 973 /* Disable AF => PF mailbox IRQ */ 974 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 975 free_irq(vector, pf); 976 } 977 978 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 979 { 980 struct otx2_hw *hw = &pf->hw; 981 struct msg_req *req; 982 char *irq_name; 983 int err; 984 985 /* Register mailbox interrupt handler */ 986 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 987 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 988 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 989 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 990 if (err) { 991 dev_err(pf->dev, 992 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 993 return err; 994 } 995 996 /* Enable mailbox interrupt for msgs coming from AF. 997 * First clear to avoid spurious interrupts, if any. 998 */ 999 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1000 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1001 1002 if (!probe_af) 1003 return 0; 1004 1005 /* Check mailbox communication with AF */ 1006 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1007 if (!req) { 1008 otx2_disable_mbox_intr(pf); 1009 return -ENOMEM; 1010 } 1011 err = otx2_sync_mbox_msg(&pf->mbox); 1012 if (err) { 1013 dev_warn(pf->dev, 1014 "AF not responding to mailbox, deferring probe\n"); 1015 otx2_disable_mbox_intr(pf); 1016 return -EPROBE_DEFER; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1023 { 1024 struct mbox *mbox = &pf->mbox; 1025 1026 if (pf->mbox_wq) { 1027 destroy_workqueue(pf->mbox_wq); 1028 pf->mbox_wq = NULL; 1029 } 1030 1031 if (mbox->mbox.hwbase) 1032 iounmap((void __iomem *)mbox->mbox.hwbase); 1033 1034 otx2_mbox_destroy(&mbox->mbox); 1035 otx2_mbox_destroy(&mbox->mbox_up); 1036 } 1037 1038 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1039 { 1040 struct mbox *mbox = &pf->mbox; 1041 void __iomem *hwbase; 1042 int err; 1043 1044 mbox->pfvf = pf; 1045 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1046 WQ_UNBOUND | WQ_HIGHPRI | 1047 WQ_MEM_RECLAIM, 1); 1048 if (!pf->mbox_wq) 1049 return -ENOMEM; 1050 1051 /* Mailbox is a reserved memory (in RAM) region shared between 1052 * admin function (i.e AF) and this PF, shouldn't be mapped as 1053 * device memory to allow unaligned accesses. 1054 */ 1055 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1056 MBOX_SIZE); 1057 if (!hwbase) { 1058 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1059 err = -ENOMEM; 1060 goto exit; 1061 } 1062 1063 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1064 MBOX_DIR_PFAF, 1); 1065 if (err) 1066 goto exit; 1067 1068 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1069 MBOX_DIR_PFAF_UP, 1); 1070 if (err) 1071 goto exit; 1072 1073 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1074 if (err) 1075 goto exit; 1076 1077 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1078 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1079 mutex_init(&mbox->lock); 1080 1081 return 0; 1082 exit: 1083 otx2_pfaf_mbox_destroy(pf); 1084 return err; 1085 } 1086 1087 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1088 { 1089 struct msg_req *msg; 1090 int err; 1091 1092 mutex_lock(&pf->mbox.lock); 1093 if (enable) 1094 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1095 else 1096 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1097 1098 if (!msg) { 1099 mutex_unlock(&pf->mbox.lock); 1100 return -ENOMEM; 1101 } 1102 1103 err = otx2_sync_mbox_msg(&pf->mbox); 1104 mutex_unlock(&pf->mbox.lock); 1105 return err; 1106 } 1107 1108 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1109 { 1110 struct msg_req *msg; 1111 int err; 1112 1113 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap, 1114 pf->flow_cfg->dmacflt_max_flows)) 1115 netdev_warn(pf->netdev, 1116 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1117 1118 mutex_lock(&pf->mbox.lock); 1119 if (enable) 1120 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1121 else 1122 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1123 1124 if (!msg) { 1125 mutex_unlock(&pf->mbox.lock); 1126 return -ENOMEM; 1127 } 1128 1129 err = otx2_sync_mbox_msg(&pf->mbox); 1130 mutex_unlock(&pf->mbox.lock); 1131 return err; 1132 } 1133 1134 int otx2_set_real_num_queues(struct net_device *netdev, 1135 int tx_queues, int rx_queues) 1136 { 1137 int err; 1138 1139 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1140 if (err) { 1141 netdev_err(netdev, 1142 "Failed to set no of Tx queues: %d\n", tx_queues); 1143 return err; 1144 } 1145 1146 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1147 if (err) 1148 netdev_err(netdev, 1149 "Failed to set no of Rx queues: %d\n", rx_queues); 1150 return err; 1151 } 1152 EXPORT_SYMBOL(otx2_set_real_num_queues); 1153 1154 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1155 { 1156 struct otx2_nic *pf = data; 1157 u64 val, *ptr; 1158 u64 qidx = 0; 1159 1160 /* CQ */ 1161 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1162 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1163 val = otx2_atomic64_add((qidx << 44), ptr); 1164 1165 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1166 (val & NIX_CQERRINT_BITS)); 1167 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1168 continue; 1169 1170 if (val & BIT_ULL(42)) { 1171 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1172 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1173 } else { 1174 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1175 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1176 qidx); 1177 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1178 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1179 qidx); 1180 } 1181 1182 schedule_work(&pf->reset_task); 1183 } 1184 1185 /* SQ */ 1186 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1187 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1188 val = otx2_atomic64_add((qidx << 44), ptr); 1189 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1190 (val & NIX_SQINT_BITS)); 1191 1192 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1193 continue; 1194 1195 if (val & BIT_ULL(42)) { 1196 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1197 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1198 } else { 1199 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1200 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1201 qidx, 1202 otx2_read64(pf, 1203 NIX_LF_SQ_OP_ERR_DBG)); 1204 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1205 BIT_ULL(44)); 1206 } 1207 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1208 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1209 qidx, 1210 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1211 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1212 BIT_ULL(44)); 1213 } 1214 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1215 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1216 qidx, 1217 otx2_read64(pf, 1218 NIX_LF_SEND_ERR_DBG)); 1219 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1220 BIT_ULL(44)); 1221 } 1222 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1223 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1224 qidx); 1225 } 1226 1227 schedule_work(&pf->reset_task); 1228 } 1229 1230 return IRQ_HANDLED; 1231 } 1232 1233 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1234 { 1235 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1236 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1237 int qidx = cq_poll->cint_idx; 1238 1239 /* Disable interrupts. 1240 * 1241 * Completion interrupts behave in a level-triggered interrupt 1242 * fashion, and hence have to be cleared only after it is serviced. 1243 */ 1244 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1245 1246 /* Schedule NAPI */ 1247 napi_schedule_irqoff(&cq_poll->napi); 1248 1249 return IRQ_HANDLED; 1250 } 1251 1252 static void otx2_disable_napi(struct otx2_nic *pf) 1253 { 1254 struct otx2_qset *qset = &pf->qset; 1255 struct otx2_cq_poll *cq_poll; 1256 int qidx; 1257 1258 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1259 cq_poll = &qset->napi[qidx]; 1260 napi_disable(&cq_poll->napi); 1261 netif_napi_del(&cq_poll->napi); 1262 } 1263 } 1264 1265 static void otx2_free_cq_res(struct otx2_nic *pf) 1266 { 1267 struct otx2_qset *qset = &pf->qset; 1268 struct otx2_cq_queue *cq; 1269 int qidx; 1270 1271 /* Disable CQs */ 1272 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1273 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1274 cq = &qset->cq[qidx]; 1275 qmem_free(pf->dev, cq->cqe); 1276 } 1277 } 1278 1279 static void otx2_free_sq_res(struct otx2_nic *pf) 1280 { 1281 struct otx2_qset *qset = &pf->qset; 1282 struct otx2_snd_queue *sq; 1283 int qidx; 1284 1285 /* Disable SQs */ 1286 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1287 /* Free SQB pointers */ 1288 otx2_sq_free_sqbs(pf); 1289 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1290 sq = &qset->sq[qidx]; 1291 qmem_free(pf->dev, sq->sqe); 1292 qmem_free(pf->dev, sq->tso_hdrs); 1293 kfree(sq->sg); 1294 kfree(sq->sqb_ptrs); 1295 } 1296 } 1297 1298 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1299 { 1300 int frame_size; 1301 int total_size; 1302 int rbuf_size; 1303 1304 /* The data transferred by NIX to memory consists of actual packet 1305 * plus additional data which has timestamp and/or EDSA/HIGIG2 1306 * headers if interface is configured in corresponding modes. 1307 * NIX transfers entire data using 6 segments/buffers and writes 1308 * a CQE_RX descriptor with those segment addresses. First segment 1309 * has additional data prepended to packet. Also software omits a 1310 * headroom of 128 bytes and sizeof(struct skb_shared_info) in 1311 * each segment. Hence the total size of memory needed 1312 * to receive a packet with 'mtu' is: 1313 * frame size = mtu + additional data; 1314 * memory = frame_size + (headroom + struct skb_shared_info size) * 6; 1315 * each receive buffer size = memory / 6; 1316 */ 1317 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1318 total_size = frame_size + (OTX2_HEAD_ROOM + 1319 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) * 6; 1320 rbuf_size = total_size / 6; 1321 1322 return ALIGN(rbuf_size, 2048); 1323 } 1324 1325 static int otx2_init_hw_resources(struct otx2_nic *pf) 1326 { 1327 struct nix_lf_free_req *free_req; 1328 struct mbox *mbox = &pf->mbox; 1329 struct otx2_hw *hw = &pf->hw; 1330 struct msg_req *req; 1331 int err = 0, lvl; 1332 1333 /* Set required NPA LF's pool counts 1334 * Auras and Pools are used in a 1:1 mapping, 1335 * so, aura count = pool count. 1336 */ 1337 hw->rqpool_cnt = hw->rx_queues; 1338 hw->sqpool_cnt = hw->tx_queues; 1339 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1340 1341 pf->max_frs = pf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1342 1343 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1344 1345 mutex_lock(&mbox->lock); 1346 /* NPA init */ 1347 err = otx2_config_npa(pf); 1348 if (err) 1349 goto exit; 1350 1351 /* NIX init */ 1352 err = otx2_config_nix(pf); 1353 if (err) 1354 goto err_free_npa_lf; 1355 1356 /* Enable backpressure */ 1357 otx2_nix_config_bp(pf, true); 1358 1359 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1360 err = otx2_rq_aura_pool_init(pf); 1361 if (err) { 1362 mutex_unlock(&mbox->lock); 1363 goto err_free_nix_lf; 1364 } 1365 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1366 err = otx2_sq_aura_pool_init(pf); 1367 if (err) { 1368 mutex_unlock(&mbox->lock); 1369 goto err_free_rq_ptrs; 1370 } 1371 1372 err = otx2_txsch_alloc(pf); 1373 if (err) { 1374 mutex_unlock(&mbox->lock); 1375 goto err_free_sq_ptrs; 1376 } 1377 1378 err = otx2_config_nix_queues(pf); 1379 if (err) { 1380 mutex_unlock(&mbox->lock); 1381 goto err_free_txsch; 1382 } 1383 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1384 err = otx2_txschq_config(pf, lvl); 1385 if (err) { 1386 mutex_unlock(&mbox->lock); 1387 goto err_free_nix_queues; 1388 } 1389 } 1390 mutex_unlock(&mbox->lock); 1391 return err; 1392 1393 err_free_nix_queues: 1394 otx2_free_sq_res(pf); 1395 otx2_free_cq_res(pf); 1396 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1397 err_free_txsch: 1398 if (otx2_txschq_stop(pf)) 1399 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1400 err_free_sq_ptrs: 1401 otx2_sq_free_sqbs(pf); 1402 err_free_rq_ptrs: 1403 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1404 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1405 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1406 otx2_aura_pool_free(pf); 1407 err_free_nix_lf: 1408 mutex_lock(&mbox->lock); 1409 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1410 if (free_req) { 1411 free_req->flags = NIX_LF_DISABLE_FLOWS; 1412 if (otx2_sync_mbox_msg(mbox)) 1413 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1414 } 1415 err_free_npa_lf: 1416 /* Reset NPA LF */ 1417 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1418 if (req) { 1419 if (otx2_sync_mbox_msg(mbox)) 1420 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1421 } 1422 exit: 1423 mutex_unlock(&mbox->lock); 1424 return err; 1425 } 1426 1427 static void otx2_free_hw_resources(struct otx2_nic *pf) 1428 { 1429 struct otx2_qset *qset = &pf->qset; 1430 struct nix_lf_free_req *free_req; 1431 struct mbox *mbox = &pf->mbox; 1432 struct otx2_cq_queue *cq; 1433 struct msg_req *req; 1434 int qidx, err; 1435 1436 /* Ensure all SQE are processed */ 1437 otx2_sqb_flush(pf); 1438 1439 /* Stop transmission */ 1440 err = otx2_txschq_stop(pf); 1441 if (err) 1442 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1443 1444 mutex_lock(&mbox->lock); 1445 /* Disable backpressure */ 1446 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1447 otx2_nix_config_bp(pf, false); 1448 mutex_unlock(&mbox->lock); 1449 1450 /* Disable RQs */ 1451 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1452 1453 /*Dequeue all CQEs */ 1454 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1455 cq = &qset->cq[qidx]; 1456 if (cq->cq_type == CQ_RX) 1457 otx2_cleanup_rx_cqes(pf, cq); 1458 else 1459 otx2_cleanup_tx_cqes(pf, cq); 1460 } 1461 1462 otx2_free_sq_res(pf); 1463 1464 /* Free RQ buffer pointers*/ 1465 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1466 1467 otx2_free_cq_res(pf); 1468 1469 /* Free all ingress bandwidth profiles allocated */ 1470 cn10k_free_all_ipolicers(pf); 1471 1472 mutex_lock(&mbox->lock); 1473 /* Reset NIX LF */ 1474 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1475 if (free_req) { 1476 free_req->flags = NIX_LF_DISABLE_FLOWS; 1477 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1478 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1479 if (otx2_sync_mbox_msg(mbox)) 1480 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1481 } 1482 mutex_unlock(&mbox->lock); 1483 1484 /* Disable NPA Pool and Aura hw context */ 1485 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1486 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1487 otx2_aura_pool_free(pf); 1488 1489 mutex_lock(&mbox->lock); 1490 /* Reset NPA LF */ 1491 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1492 if (req) { 1493 if (otx2_sync_mbox_msg(mbox)) 1494 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1495 } 1496 mutex_unlock(&mbox->lock); 1497 } 1498 1499 int otx2_open(struct net_device *netdev) 1500 { 1501 struct otx2_nic *pf = netdev_priv(netdev); 1502 struct otx2_cq_poll *cq_poll = NULL; 1503 struct otx2_qset *qset = &pf->qset; 1504 int err = 0, qidx, vec; 1505 char *irq_name; 1506 1507 netif_carrier_off(netdev); 1508 1509 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues; 1510 /* RQ and SQs are mapped to different CQs, 1511 * so find out max CQ IRQs (i.e CINTs) needed. 1512 */ 1513 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1514 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1515 if (!qset->napi) 1516 return -ENOMEM; 1517 1518 /* CQ size of RQ */ 1519 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1520 /* CQ size of SQ */ 1521 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1522 1523 err = -ENOMEM; 1524 qset->cq = kcalloc(pf->qset.cq_cnt, 1525 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1526 if (!qset->cq) 1527 goto err_free_mem; 1528 1529 qset->sq = kcalloc(pf->hw.tx_queues, 1530 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1531 if (!qset->sq) 1532 goto err_free_mem; 1533 1534 qset->rq = kcalloc(pf->hw.rx_queues, 1535 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1536 if (!qset->rq) 1537 goto err_free_mem; 1538 1539 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) { 1540 /* Reserve LMT lines for NPA AURA batch free */ 1541 pf->hw.npa_lmt_base = pf->hw.lmt_base; 1542 /* Reserve LMT lines for NIX TX */ 1543 pf->hw.nix_lmt_base = (u64 *)((u64)pf->hw.npa_lmt_base + 1544 (pf->npa_lmt_lines * LMT_LINE_SIZE)); 1545 } 1546 1547 err = otx2_init_hw_resources(pf); 1548 if (err) 1549 goto err_free_mem; 1550 1551 /* Register NAPI handler */ 1552 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1553 cq_poll = &qset->napi[qidx]; 1554 cq_poll->cint_idx = qidx; 1555 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1556 * 'cq_ids[0]' points to RQ's CQ and 1557 * 'cq_ids[1]' points to SQ's CQ and 1558 */ 1559 cq_poll->cq_ids[CQ_RX] = 1560 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1561 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1562 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1563 cq_poll->dev = (void *)pf; 1564 netif_napi_add(netdev, &cq_poll->napi, 1565 otx2_napi_handler, NAPI_POLL_WEIGHT); 1566 napi_enable(&cq_poll->napi); 1567 } 1568 1569 /* Set maximum frame size allowed in HW */ 1570 err = otx2_hw_set_mtu(pf, netdev->mtu); 1571 if (err) 1572 goto err_disable_napi; 1573 1574 /* Setup segmentation algorithms, if failed, clear offload capability */ 1575 otx2_setup_segmentation(pf); 1576 1577 /* Initialize RSS */ 1578 err = otx2_rss_init(pf); 1579 if (err) 1580 goto err_disable_napi; 1581 1582 /* Register Queue IRQ handlers */ 1583 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1584 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1585 1586 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1587 1588 err = request_irq(pci_irq_vector(pf->pdev, vec), 1589 otx2_q_intr_handler, 0, irq_name, pf); 1590 if (err) { 1591 dev_err(pf->dev, 1592 "RVUPF%d: IRQ registration failed for QERR\n", 1593 rvu_get_pf(pf->pcifunc)); 1594 goto err_disable_napi; 1595 } 1596 1597 /* Enable QINT IRQ */ 1598 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1599 1600 /* Register CQ IRQ handlers */ 1601 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1602 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1603 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1604 1605 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1606 qidx); 1607 1608 err = request_irq(pci_irq_vector(pf->pdev, vec), 1609 otx2_cq_intr_handler, 0, irq_name, 1610 &qset->napi[qidx]); 1611 if (err) { 1612 dev_err(pf->dev, 1613 "RVUPF%d: IRQ registration failed for CQ%d\n", 1614 rvu_get_pf(pf->pcifunc), qidx); 1615 goto err_free_cints; 1616 } 1617 vec++; 1618 1619 otx2_config_irq_coalescing(pf, qidx); 1620 1621 /* Enable CQ IRQ */ 1622 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1623 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1624 } 1625 1626 otx2_set_cints_affinity(pf); 1627 1628 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1629 otx2_enable_rxvlan(pf, true); 1630 1631 /* When reinitializing enable time stamping if it is enabled before */ 1632 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1633 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1634 otx2_config_hw_tx_tstamp(pf, true); 1635 } 1636 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1637 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1638 otx2_config_hw_rx_tstamp(pf, true); 1639 } 1640 1641 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1642 /* 'intf_down' may be checked on any cpu */ 1643 smp_wmb(); 1644 1645 /* we have already received link status notification */ 1646 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1647 otx2_handle_link_event(pf); 1648 1649 /* Restore pause frame settings */ 1650 otx2_config_pause_frm(pf); 1651 1652 /* Install DMAC Filters */ 1653 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1654 otx2_dmacflt_reinstall_flows(pf); 1655 1656 err = otx2_rxtx_enable(pf, true); 1657 if (err) 1658 goto err_tx_stop_queues; 1659 1660 return 0; 1661 1662 err_tx_stop_queues: 1663 netif_tx_stop_all_queues(netdev); 1664 netif_carrier_off(netdev); 1665 pf->flags |= OTX2_FLAG_INTF_DOWN; 1666 err_free_cints: 1667 otx2_free_cints(pf, qidx); 1668 vec = pci_irq_vector(pf->pdev, 1669 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1670 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1671 synchronize_irq(vec); 1672 free_irq(vec, pf); 1673 err_disable_napi: 1674 otx2_disable_napi(pf); 1675 otx2_free_hw_resources(pf); 1676 err_free_mem: 1677 kfree(qset->sq); 1678 kfree(qset->cq); 1679 kfree(qset->rq); 1680 kfree(qset->napi); 1681 return err; 1682 } 1683 EXPORT_SYMBOL(otx2_open); 1684 1685 int otx2_stop(struct net_device *netdev) 1686 { 1687 struct otx2_nic *pf = netdev_priv(netdev); 1688 struct otx2_cq_poll *cq_poll = NULL; 1689 struct otx2_qset *qset = &pf->qset; 1690 struct otx2_rss_info *rss; 1691 int qidx, vec, wrk; 1692 1693 /* If the DOWN flag is set resources are already freed */ 1694 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1695 return 0; 1696 1697 netif_carrier_off(netdev); 1698 netif_tx_stop_all_queues(netdev); 1699 1700 pf->flags |= OTX2_FLAG_INTF_DOWN; 1701 /* 'intf_down' may be checked on any cpu */ 1702 smp_wmb(); 1703 1704 /* First stop packet Rx/Tx */ 1705 otx2_rxtx_enable(pf, false); 1706 1707 /* Clear RSS enable flag */ 1708 rss = &pf->hw.rss_info; 1709 rss->enable = false; 1710 1711 /* Cleanup Queue IRQ */ 1712 vec = pci_irq_vector(pf->pdev, 1713 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1714 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1715 synchronize_irq(vec); 1716 free_irq(vec, pf); 1717 1718 /* Cleanup CQ NAPI and IRQ */ 1719 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1720 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1721 /* Disable interrupt */ 1722 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1723 1724 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1725 1726 cq_poll = &qset->napi[qidx]; 1727 napi_synchronize(&cq_poll->napi); 1728 vec++; 1729 } 1730 1731 netif_tx_disable(netdev); 1732 1733 otx2_free_hw_resources(pf); 1734 otx2_free_cints(pf, pf->hw.cint_cnt); 1735 otx2_disable_napi(pf); 1736 1737 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1738 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1739 1740 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1741 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1742 devm_kfree(pf->dev, pf->refill_wrk); 1743 1744 kfree(qset->sq); 1745 kfree(qset->cq); 1746 kfree(qset->rq); 1747 kfree(qset->napi); 1748 /* Do not clear RQ/SQ ringsize settings */ 1749 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1750 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1751 return 0; 1752 } 1753 EXPORT_SYMBOL(otx2_stop); 1754 1755 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1756 { 1757 struct otx2_nic *pf = netdev_priv(netdev); 1758 int qidx = skb_get_queue_mapping(skb); 1759 struct otx2_snd_queue *sq; 1760 struct netdev_queue *txq; 1761 1762 /* Check for minimum and maximum packet length */ 1763 if (skb->len <= ETH_HLEN || 1764 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1765 dev_kfree_skb(skb); 1766 return NETDEV_TX_OK; 1767 } 1768 1769 sq = &pf->qset.sq[qidx]; 1770 txq = netdev_get_tx_queue(netdev, qidx); 1771 1772 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1773 netif_tx_stop_queue(txq); 1774 1775 /* Check again, incase SQBs got freed up */ 1776 smp_mb(); 1777 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1778 > sq->sqe_thresh) 1779 netif_tx_wake_queue(txq); 1780 1781 return NETDEV_TX_BUSY; 1782 } 1783 1784 return NETDEV_TX_OK; 1785 } 1786 1787 static netdev_features_t otx2_fix_features(struct net_device *dev, 1788 netdev_features_t features) 1789 { 1790 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1791 features |= NETIF_F_HW_VLAN_STAG_RX; 1792 else 1793 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1794 1795 return features; 1796 } 1797 1798 static void otx2_set_rx_mode(struct net_device *netdev) 1799 { 1800 struct otx2_nic *pf = netdev_priv(netdev); 1801 1802 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1803 } 1804 1805 static void otx2_do_set_rx_mode(struct work_struct *work) 1806 { 1807 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1808 struct net_device *netdev = pf->netdev; 1809 struct nix_rx_mode *req; 1810 bool promisc = false; 1811 1812 if (!(netdev->flags & IFF_UP)) 1813 return; 1814 1815 if ((netdev->flags & IFF_PROMISC) || 1816 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1817 promisc = true; 1818 } 1819 1820 /* Write unicast address to mcam entries or del from mcam */ 1821 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1822 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1823 1824 mutex_lock(&pf->mbox.lock); 1825 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1826 if (!req) { 1827 mutex_unlock(&pf->mbox.lock); 1828 return; 1829 } 1830 1831 req->mode = NIX_RX_MODE_UCAST; 1832 1833 if (promisc) 1834 req->mode |= NIX_RX_MODE_PROMISC; 1835 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1836 req->mode |= NIX_RX_MODE_ALLMULTI; 1837 1838 req->mode |= NIX_RX_MODE_USE_MCE; 1839 1840 otx2_sync_mbox_msg(&pf->mbox); 1841 mutex_unlock(&pf->mbox.lock); 1842 } 1843 1844 static int otx2_set_features(struct net_device *netdev, 1845 netdev_features_t features) 1846 { 1847 netdev_features_t changed = features ^ netdev->features; 1848 bool ntuple = !!(features & NETIF_F_NTUPLE); 1849 struct otx2_nic *pf = netdev_priv(netdev); 1850 bool tc = !!(features & NETIF_F_HW_TC); 1851 1852 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1853 return otx2_cgx_config_loopback(pf, 1854 features & NETIF_F_LOOPBACK); 1855 1856 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1857 return otx2_enable_rxvlan(pf, 1858 features & NETIF_F_HW_VLAN_CTAG_RX); 1859 1860 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1861 otx2_destroy_ntuple_flows(pf); 1862 1863 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1864 if (!pf->flow_cfg->max_flows) { 1865 netdev_err(netdev, 1866 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1867 return -EINVAL; 1868 } 1869 } 1870 1871 if ((changed & NETIF_F_HW_TC) && tc) { 1872 if (!pf->flow_cfg->max_flows) { 1873 netdev_err(netdev, 1874 "Can't enable TC, MCAM entries not allocated\n"); 1875 return -EINVAL; 1876 } 1877 } 1878 1879 if ((changed & NETIF_F_HW_TC) && !tc && 1880 pf->flow_cfg && pf->flow_cfg->nr_flows) { 1881 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1882 return -EBUSY; 1883 } 1884 1885 if ((changed & NETIF_F_NTUPLE) && ntuple && 1886 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1887 netdev_err(netdev, 1888 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1889 return -EINVAL; 1890 } 1891 1892 if ((changed & NETIF_F_HW_TC) && tc && 1893 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1894 netdev_err(netdev, 1895 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1896 return -EINVAL; 1897 } 1898 1899 return 0; 1900 } 1901 1902 static void otx2_reset_task(struct work_struct *work) 1903 { 1904 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1905 1906 if (!netif_running(pf->netdev)) 1907 return; 1908 1909 rtnl_lock(); 1910 otx2_stop(pf->netdev); 1911 pf->reset_count++; 1912 otx2_open(pf->netdev); 1913 netif_trans_update(pf->netdev); 1914 rtnl_unlock(); 1915 } 1916 1917 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1918 { 1919 struct msg_req *req; 1920 int err; 1921 1922 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1923 return 0; 1924 1925 mutex_lock(&pfvf->mbox.lock); 1926 if (enable) 1927 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1928 else 1929 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1930 if (!req) { 1931 mutex_unlock(&pfvf->mbox.lock); 1932 return -ENOMEM; 1933 } 1934 1935 err = otx2_sync_mbox_msg(&pfvf->mbox); 1936 if (err) { 1937 mutex_unlock(&pfvf->mbox.lock); 1938 return err; 1939 } 1940 1941 mutex_unlock(&pfvf->mbox.lock); 1942 if (enable) 1943 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1944 else 1945 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1946 return 0; 1947 } 1948 1949 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1950 { 1951 struct msg_req *req; 1952 int err; 1953 1954 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1955 return 0; 1956 1957 mutex_lock(&pfvf->mbox.lock); 1958 if (enable) 1959 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1960 else 1961 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1962 if (!req) { 1963 mutex_unlock(&pfvf->mbox.lock); 1964 return -ENOMEM; 1965 } 1966 1967 err = otx2_sync_mbox_msg(&pfvf->mbox); 1968 if (err) { 1969 mutex_unlock(&pfvf->mbox.lock); 1970 return err; 1971 } 1972 1973 mutex_unlock(&pfvf->mbox.lock); 1974 if (enable) 1975 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1976 else 1977 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1978 return 0; 1979 } 1980 1981 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1982 { 1983 struct otx2_nic *pfvf = netdev_priv(netdev); 1984 struct hwtstamp_config config; 1985 1986 if (!pfvf->ptp) 1987 return -ENODEV; 1988 1989 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1990 return -EFAULT; 1991 1992 /* reserved for future extensions */ 1993 if (config.flags) 1994 return -EINVAL; 1995 1996 switch (config.tx_type) { 1997 case HWTSTAMP_TX_OFF: 1998 otx2_config_hw_tx_tstamp(pfvf, false); 1999 break; 2000 case HWTSTAMP_TX_ON: 2001 otx2_config_hw_tx_tstamp(pfvf, true); 2002 break; 2003 default: 2004 return -ERANGE; 2005 } 2006 2007 switch (config.rx_filter) { 2008 case HWTSTAMP_FILTER_NONE: 2009 otx2_config_hw_rx_tstamp(pfvf, false); 2010 break; 2011 case HWTSTAMP_FILTER_ALL: 2012 case HWTSTAMP_FILTER_SOME: 2013 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2014 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2015 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2016 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2017 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2018 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2019 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2020 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2021 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2022 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2023 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2024 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2025 otx2_config_hw_rx_tstamp(pfvf, true); 2026 config.rx_filter = HWTSTAMP_FILTER_ALL; 2027 break; 2028 default: 2029 return -ERANGE; 2030 } 2031 2032 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2033 2034 return copy_to_user(ifr->ifr_data, &config, 2035 sizeof(config)) ? -EFAULT : 0; 2036 } 2037 2038 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2039 { 2040 struct otx2_nic *pfvf = netdev_priv(netdev); 2041 struct hwtstamp_config *cfg = &pfvf->tstamp; 2042 2043 switch (cmd) { 2044 case SIOCSHWTSTAMP: 2045 return otx2_config_hwtstamp(netdev, req); 2046 case SIOCGHWTSTAMP: 2047 return copy_to_user(req->ifr_data, cfg, 2048 sizeof(*cfg)) ? -EFAULT : 0; 2049 default: 2050 return -EOPNOTSUPP; 2051 } 2052 } 2053 2054 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2055 { 2056 struct npc_install_flow_req *req; 2057 int err; 2058 2059 mutex_lock(&pf->mbox.lock); 2060 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2061 if (!req) { 2062 err = -ENOMEM; 2063 goto out; 2064 } 2065 2066 ether_addr_copy(req->packet.dmac, mac); 2067 eth_broadcast_addr((u8 *)&req->mask.dmac); 2068 req->features = BIT_ULL(NPC_DMAC); 2069 req->channel = pf->hw.rx_chan_base; 2070 req->intf = NIX_INTF_RX; 2071 req->default_rule = 1; 2072 req->append = 1; 2073 req->vf = vf + 1; 2074 req->op = NIX_RX_ACTION_DEFAULT; 2075 2076 err = otx2_sync_mbox_msg(&pf->mbox); 2077 out: 2078 mutex_unlock(&pf->mbox.lock); 2079 return err; 2080 } 2081 2082 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2083 { 2084 struct otx2_nic *pf = netdev_priv(netdev); 2085 struct pci_dev *pdev = pf->pdev; 2086 struct otx2_vf_config *config; 2087 int ret; 2088 2089 if (!netif_running(netdev)) 2090 return -EAGAIN; 2091 2092 if (vf >= pf->total_vfs) 2093 return -EINVAL; 2094 2095 if (!is_valid_ether_addr(mac)) 2096 return -EINVAL; 2097 2098 config = &pf->vf_configs[vf]; 2099 ether_addr_copy(config->mac, mac); 2100 2101 ret = otx2_do_set_vf_mac(pf, vf, mac); 2102 if (ret == 0) 2103 dev_info(&pdev->dev, 2104 "Load/Reload VF driver\n"); 2105 2106 return ret; 2107 } 2108 2109 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2110 __be16 proto) 2111 { 2112 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2113 struct nix_vtag_config_rsp *vtag_rsp; 2114 struct npc_delete_flow_req *del_req; 2115 struct nix_vtag_config *vtag_req; 2116 struct npc_install_flow_req *req; 2117 struct otx2_vf_config *config; 2118 int err = 0; 2119 u32 idx; 2120 2121 config = &pf->vf_configs[vf]; 2122 2123 if (!vlan && !config->vlan) 2124 goto out; 2125 2126 mutex_lock(&pf->mbox.lock); 2127 2128 /* free old tx vtag entry */ 2129 if (config->vlan) { 2130 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2131 if (!vtag_req) { 2132 err = -ENOMEM; 2133 goto out; 2134 } 2135 vtag_req->cfg_type = 0; 2136 vtag_req->tx.free_vtag0 = 1; 2137 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2138 2139 err = otx2_sync_mbox_msg(&pf->mbox); 2140 if (err) 2141 goto out; 2142 } 2143 2144 if (!vlan && config->vlan) { 2145 /* rx */ 2146 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2147 if (!del_req) { 2148 err = -ENOMEM; 2149 goto out; 2150 } 2151 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2152 del_req->entry = 2153 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2154 err = otx2_sync_mbox_msg(&pf->mbox); 2155 if (err) 2156 goto out; 2157 2158 /* tx */ 2159 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2160 if (!del_req) { 2161 err = -ENOMEM; 2162 goto out; 2163 } 2164 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2165 del_req->entry = 2166 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2167 err = otx2_sync_mbox_msg(&pf->mbox); 2168 2169 goto out; 2170 } 2171 2172 /* rx */ 2173 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2174 if (!req) { 2175 err = -ENOMEM; 2176 goto out; 2177 } 2178 2179 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2180 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2181 req->packet.vlan_tci = htons(vlan); 2182 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2183 /* af fills the destination mac addr */ 2184 eth_broadcast_addr((u8 *)&req->mask.dmac); 2185 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2186 req->channel = pf->hw.rx_chan_base; 2187 req->intf = NIX_INTF_RX; 2188 req->vf = vf + 1; 2189 req->op = NIX_RX_ACTION_DEFAULT; 2190 req->vtag0_valid = true; 2191 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2192 req->set_cntr = 1; 2193 2194 err = otx2_sync_mbox_msg(&pf->mbox); 2195 if (err) 2196 goto out; 2197 2198 /* tx */ 2199 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2200 if (!vtag_req) { 2201 err = -ENOMEM; 2202 goto out; 2203 } 2204 2205 /* configure tx vtag params */ 2206 vtag_req->vtag_size = VTAGSIZE_T4; 2207 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2208 vtag_req->tx.cfg_vtag0 = 1; 2209 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2210 2211 err = otx2_sync_mbox_msg(&pf->mbox); 2212 if (err) 2213 goto out; 2214 2215 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2216 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2217 if (IS_ERR(vtag_rsp)) { 2218 err = PTR_ERR(vtag_rsp); 2219 goto out; 2220 } 2221 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2222 2223 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2224 if (!req) { 2225 err = -ENOMEM; 2226 goto out; 2227 } 2228 2229 eth_zero_addr((u8 *)&req->mask.dmac); 2230 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2231 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2232 req->features = BIT_ULL(NPC_DMAC); 2233 req->channel = pf->hw.tx_chan_base; 2234 req->intf = NIX_INTF_TX; 2235 req->vf = vf + 1; 2236 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2237 req->vtag0_def = vtag_rsp->vtag0_idx; 2238 req->vtag0_op = VTAG_INSERT; 2239 req->set_cntr = 1; 2240 2241 err = otx2_sync_mbox_msg(&pf->mbox); 2242 out: 2243 config->vlan = vlan; 2244 mutex_unlock(&pf->mbox.lock); 2245 return err; 2246 } 2247 2248 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2249 __be16 proto) 2250 { 2251 struct otx2_nic *pf = netdev_priv(netdev); 2252 struct pci_dev *pdev = pf->pdev; 2253 2254 if (!netif_running(netdev)) 2255 return -EAGAIN; 2256 2257 if (vf >= pci_num_vf(pdev)) 2258 return -EINVAL; 2259 2260 /* qos is currently unsupported */ 2261 if (vlan >= VLAN_N_VID || qos) 2262 return -EINVAL; 2263 2264 if (proto != htons(ETH_P_8021Q)) 2265 return -EPROTONOSUPPORT; 2266 2267 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2268 return -EOPNOTSUPP; 2269 2270 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2271 } 2272 2273 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2274 struct ifla_vf_info *ivi) 2275 { 2276 struct otx2_nic *pf = netdev_priv(netdev); 2277 struct pci_dev *pdev = pf->pdev; 2278 struct otx2_vf_config *config; 2279 2280 if (!netif_running(netdev)) 2281 return -EAGAIN; 2282 2283 if (vf >= pci_num_vf(pdev)) 2284 return -EINVAL; 2285 2286 config = &pf->vf_configs[vf]; 2287 ivi->vf = vf; 2288 ether_addr_copy(ivi->mac, config->mac); 2289 ivi->vlan = config->vlan; 2290 ivi->trusted = config->trusted; 2291 2292 return 0; 2293 } 2294 2295 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2296 int req_perm) 2297 { 2298 struct set_vf_perm *req; 2299 int rc; 2300 2301 mutex_lock(&pf->mbox.lock); 2302 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2303 if (!req) { 2304 rc = -ENOMEM; 2305 goto out; 2306 } 2307 2308 /* Let AF reset VF permissions as sriov is disabled */ 2309 if (req_perm == OTX2_RESET_VF_PERM) { 2310 req->flags |= RESET_VF_PERM; 2311 } else if (req_perm == OTX2_TRUSTED_VF) { 2312 if (pf->vf_configs[vf].trusted) 2313 req->flags |= VF_TRUSTED; 2314 } 2315 2316 req->vf = vf; 2317 rc = otx2_sync_mbox_msg(&pf->mbox); 2318 out: 2319 mutex_unlock(&pf->mbox.lock); 2320 return rc; 2321 } 2322 2323 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2324 bool enable) 2325 { 2326 struct otx2_nic *pf = netdev_priv(netdev); 2327 struct pci_dev *pdev = pf->pdev; 2328 int rc; 2329 2330 if (vf >= pci_num_vf(pdev)) 2331 return -EINVAL; 2332 2333 if (pf->vf_configs[vf].trusted == enable) 2334 return 0; 2335 2336 pf->vf_configs[vf].trusted = enable; 2337 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2338 2339 if (rc) 2340 pf->vf_configs[vf].trusted = !enable; 2341 else 2342 netdev_info(pf->netdev, "VF %d is %strusted\n", 2343 vf, enable ? "" : "not "); 2344 return rc; 2345 } 2346 2347 static const struct net_device_ops otx2_netdev_ops = { 2348 .ndo_open = otx2_open, 2349 .ndo_stop = otx2_stop, 2350 .ndo_start_xmit = otx2_xmit, 2351 .ndo_fix_features = otx2_fix_features, 2352 .ndo_set_mac_address = otx2_set_mac_address, 2353 .ndo_change_mtu = otx2_change_mtu, 2354 .ndo_set_rx_mode = otx2_set_rx_mode, 2355 .ndo_set_features = otx2_set_features, 2356 .ndo_tx_timeout = otx2_tx_timeout, 2357 .ndo_get_stats64 = otx2_get_stats64, 2358 .ndo_eth_ioctl = otx2_ioctl, 2359 .ndo_set_vf_mac = otx2_set_vf_mac, 2360 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2361 .ndo_get_vf_config = otx2_get_vf_config, 2362 .ndo_setup_tc = otx2_setup_tc, 2363 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2364 }; 2365 2366 static int otx2_wq_init(struct otx2_nic *pf) 2367 { 2368 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2369 if (!pf->otx2_wq) 2370 return -ENOMEM; 2371 2372 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode); 2373 INIT_WORK(&pf->reset_task, otx2_reset_task); 2374 return 0; 2375 } 2376 2377 static int otx2_check_pf_usable(struct otx2_nic *nic) 2378 { 2379 u64 rev; 2380 2381 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2382 rev = (rev >> 12) & 0xFF; 2383 /* Check if AF has setup revision for RVUM block, 2384 * otherwise this driver probe should be deferred 2385 * until AF driver comes up. 2386 */ 2387 if (!rev) { 2388 dev_warn(nic->dev, 2389 "AF is not initialized, deferring probe\n"); 2390 return -EPROBE_DEFER; 2391 } 2392 return 0; 2393 } 2394 2395 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2396 { 2397 struct otx2_hw *hw = &pf->hw; 2398 int num_vec, err; 2399 2400 /* NPA interrupts are inot registered, so alloc only 2401 * upto NIX vector offset. 2402 */ 2403 num_vec = hw->nix_msixoff; 2404 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2405 2406 otx2_disable_mbox_intr(pf); 2407 pci_free_irq_vectors(hw->pdev); 2408 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2409 if (err < 0) { 2410 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2411 __func__, num_vec); 2412 return err; 2413 } 2414 2415 return otx2_register_mbox_intr(pf, false); 2416 } 2417 2418 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2419 { 2420 int i; 2421 2422 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2423 sizeof(struct otx2_vf_config), 2424 GFP_KERNEL); 2425 if (!pf->vf_configs) 2426 return -ENOMEM; 2427 2428 for (i = 0; i < pf->total_vfs; i++) { 2429 pf->vf_configs[i].pf = pf; 2430 pf->vf_configs[i].intf_down = true; 2431 pf->vf_configs[i].trusted = false; 2432 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2433 otx2_vf_link_event_task); 2434 } 2435 2436 return 0; 2437 } 2438 2439 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2440 { 2441 int i; 2442 2443 if (!pf->vf_configs) 2444 return; 2445 2446 for (i = 0; i < pf->total_vfs; i++) { 2447 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2448 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2449 } 2450 } 2451 2452 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2453 { 2454 struct device *dev = &pdev->dev; 2455 struct net_device *netdev; 2456 struct otx2_nic *pf; 2457 struct otx2_hw *hw; 2458 int err, qcount; 2459 int num_vec; 2460 2461 err = pcim_enable_device(pdev); 2462 if (err) { 2463 dev_err(dev, "Failed to enable PCI device\n"); 2464 return err; 2465 } 2466 2467 err = pci_request_regions(pdev, DRV_NAME); 2468 if (err) { 2469 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2470 return err; 2471 } 2472 2473 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2474 if (err) { 2475 dev_err(dev, "DMA mask config failed, abort\n"); 2476 goto err_release_regions; 2477 } 2478 2479 pci_set_master(pdev); 2480 2481 /* Set number of queues */ 2482 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2483 2484 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2485 if (!netdev) { 2486 err = -ENOMEM; 2487 goto err_release_regions; 2488 } 2489 2490 pci_set_drvdata(pdev, netdev); 2491 SET_NETDEV_DEV(netdev, &pdev->dev); 2492 pf = netdev_priv(netdev); 2493 pf->netdev = netdev; 2494 pf->pdev = pdev; 2495 pf->dev = dev; 2496 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2497 pf->flags |= OTX2_FLAG_INTF_DOWN; 2498 2499 hw = &pf->hw; 2500 hw->pdev = pdev; 2501 hw->rx_queues = qcount; 2502 hw->tx_queues = qcount; 2503 hw->max_queues = qcount; 2504 2505 num_vec = pci_msix_vec_count(pdev); 2506 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2507 GFP_KERNEL); 2508 if (!hw->irq_name) { 2509 err = -ENOMEM; 2510 goto err_free_netdev; 2511 } 2512 2513 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2514 sizeof(cpumask_var_t), GFP_KERNEL); 2515 if (!hw->affinity_mask) { 2516 err = -ENOMEM; 2517 goto err_free_netdev; 2518 } 2519 2520 /* Map CSRs */ 2521 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2522 if (!pf->reg_base) { 2523 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2524 err = -ENOMEM; 2525 goto err_free_netdev; 2526 } 2527 2528 err = otx2_check_pf_usable(pf); 2529 if (err) 2530 goto err_free_netdev; 2531 2532 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2533 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2534 if (err < 0) { 2535 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2536 __func__, num_vec); 2537 goto err_free_netdev; 2538 } 2539 2540 otx2_setup_dev_hw_settings(pf); 2541 2542 /* Init PF <=> AF mailbox stuff */ 2543 err = otx2_pfaf_mbox_init(pf); 2544 if (err) 2545 goto err_free_irq_vectors; 2546 2547 /* Register mailbox interrupt */ 2548 err = otx2_register_mbox_intr(pf, true); 2549 if (err) 2550 goto err_mbox_destroy; 2551 2552 /* Request AF to attach NPA and NIX LFs to this PF. 2553 * NIX and NPA LFs are needed for this PF to function as a NIC. 2554 */ 2555 err = otx2_attach_npa_nix(pf); 2556 if (err) 2557 goto err_disable_mbox_intr; 2558 2559 err = otx2_realloc_msix_vectors(pf); 2560 if (err) 2561 goto err_detach_rsrc; 2562 2563 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2564 if (err) 2565 goto err_detach_rsrc; 2566 2567 err = cn10k_lmtst_init(pf); 2568 if (err) 2569 goto err_detach_rsrc; 2570 2571 /* Assign default mac address */ 2572 otx2_get_mac_from_af(netdev); 2573 2574 /* Don't check for error. Proceed without ptp */ 2575 otx2_ptp_init(pf); 2576 2577 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2578 * HW allocates buffer pointer from stack and uses it for DMA'ing 2579 * ingress packet. In some scenarios HW can free back allocated buffer 2580 * pointers to pool. This makes it impossible for SW to maintain a 2581 * parallel list where physical addresses of buffer pointers (IOVAs) 2582 * given to HW can be saved for later reference. 2583 * 2584 * So the only way to convert Rx packet's buffer address is to use 2585 * IOMMU's iova_to_phys() handler which translates the address by 2586 * walking through the translation tables. 2587 */ 2588 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2589 2590 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2591 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2592 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2593 NETIF_F_GSO_UDP_L4); 2594 netdev->features |= netdev->hw_features; 2595 2596 err = otx2_mcam_flow_init(pf); 2597 if (err) 2598 goto err_ptp_destroy; 2599 2600 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2601 netdev->hw_features |= NETIF_F_NTUPLE; 2602 2603 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2604 netdev->priv_flags |= IFF_UNICAST_FLT; 2605 2606 /* Support TSO on tag interface */ 2607 netdev->vlan_features |= netdev->features; 2608 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2609 NETIF_F_HW_VLAN_STAG_TX; 2610 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2611 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2612 NETIF_F_HW_VLAN_STAG_RX; 2613 netdev->features |= netdev->hw_features; 2614 2615 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2616 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2617 netdev->hw_features |= NETIF_F_HW_TC; 2618 2619 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2620 2621 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2622 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2623 2624 netdev->netdev_ops = &otx2_netdev_ops; 2625 2626 netdev->min_mtu = OTX2_MIN_MTU; 2627 netdev->max_mtu = otx2_get_max_mtu(pf); 2628 2629 err = register_netdev(netdev); 2630 if (err) { 2631 dev_err(dev, "Failed to register netdevice\n"); 2632 goto err_del_mcam_entries; 2633 } 2634 2635 err = otx2_wq_init(pf); 2636 if (err) 2637 goto err_unreg_netdev; 2638 2639 otx2_set_ethtool_ops(netdev); 2640 2641 err = otx2_init_tc(pf); 2642 if (err) 2643 goto err_mcam_flow_del; 2644 2645 err = otx2_register_dl(pf); 2646 if (err) 2647 goto err_mcam_flow_del; 2648 2649 /* Initialize SR-IOV resources */ 2650 err = otx2_sriov_vfcfg_init(pf); 2651 if (err) 2652 goto err_pf_sriov_init; 2653 2654 /* Enable link notifications */ 2655 otx2_cgx_config_linkevents(pf, true); 2656 2657 /* Enable pause frames by default */ 2658 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2659 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2660 2661 return 0; 2662 2663 err_pf_sriov_init: 2664 otx2_shutdown_tc(pf); 2665 err_mcam_flow_del: 2666 otx2_mcam_flow_del(pf); 2667 err_unreg_netdev: 2668 unregister_netdev(netdev); 2669 err_del_mcam_entries: 2670 otx2_mcam_flow_del(pf); 2671 err_ptp_destroy: 2672 otx2_ptp_destroy(pf); 2673 err_detach_rsrc: 2674 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2675 qmem_free(pf->dev, pf->dync_lmt); 2676 otx2_detach_resources(&pf->mbox); 2677 err_disable_mbox_intr: 2678 otx2_disable_mbox_intr(pf); 2679 err_mbox_destroy: 2680 otx2_pfaf_mbox_destroy(pf); 2681 err_free_irq_vectors: 2682 pci_free_irq_vectors(hw->pdev); 2683 err_free_netdev: 2684 pci_set_drvdata(pdev, NULL); 2685 free_netdev(netdev); 2686 err_release_regions: 2687 pci_release_regions(pdev); 2688 return err; 2689 } 2690 2691 static void otx2_vf_link_event_task(struct work_struct *work) 2692 { 2693 struct otx2_vf_config *config; 2694 struct cgx_link_info_msg *req; 2695 struct mbox_msghdr *msghdr; 2696 struct otx2_nic *pf; 2697 int vf_idx; 2698 2699 config = container_of(work, struct otx2_vf_config, 2700 link_event_work.work); 2701 vf_idx = config - config->pf->vf_configs; 2702 pf = config->pf; 2703 2704 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2705 sizeof(*req), sizeof(struct msg_rsp)); 2706 if (!msghdr) { 2707 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2708 return; 2709 } 2710 2711 req = (struct cgx_link_info_msg *)msghdr; 2712 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2713 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2714 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2715 2716 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2717 } 2718 2719 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2720 { 2721 struct net_device *netdev = pci_get_drvdata(pdev); 2722 struct otx2_nic *pf = netdev_priv(netdev); 2723 int ret; 2724 2725 /* Init PF <=> VF mailbox stuff */ 2726 ret = otx2_pfvf_mbox_init(pf, numvfs); 2727 if (ret) 2728 return ret; 2729 2730 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2731 if (ret) 2732 goto free_mbox; 2733 2734 ret = otx2_pf_flr_init(pf, numvfs); 2735 if (ret) 2736 goto free_intr; 2737 2738 ret = otx2_register_flr_me_intr(pf, numvfs); 2739 if (ret) 2740 goto free_flr; 2741 2742 ret = pci_enable_sriov(pdev, numvfs); 2743 if (ret) 2744 goto free_flr_intr; 2745 2746 return numvfs; 2747 free_flr_intr: 2748 otx2_disable_flr_me_intr(pf); 2749 free_flr: 2750 otx2_flr_wq_destroy(pf); 2751 free_intr: 2752 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2753 free_mbox: 2754 otx2_pfvf_mbox_destroy(pf); 2755 return ret; 2756 } 2757 2758 static int otx2_sriov_disable(struct pci_dev *pdev) 2759 { 2760 struct net_device *netdev = pci_get_drvdata(pdev); 2761 struct otx2_nic *pf = netdev_priv(netdev); 2762 int numvfs = pci_num_vf(pdev); 2763 2764 if (!numvfs) 2765 return 0; 2766 2767 pci_disable_sriov(pdev); 2768 2769 otx2_disable_flr_me_intr(pf); 2770 otx2_flr_wq_destroy(pf); 2771 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2772 otx2_pfvf_mbox_destroy(pf); 2773 2774 return 0; 2775 } 2776 2777 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2778 { 2779 if (numvfs == 0) 2780 return otx2_sriov_disable(pdev); 2781 else 2782 return otx2_sriov_enable(pdev, numvfs); 2783 } 2784 2785 static void otx2_remove(struct pci_dev *pdev) 2786 { 2787 struct net_device *netdev = pci_get_drvdata(pdev); 2788 struct otx2_nic *pf; 2789 2790 if (!netdev) 2791 return; 2792 2793 pf = netdev_priv(netdev); 2794 2795 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2796 2797 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2798 otx2_config_hw_tx_tstamp(pf, false); 2799 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2800 otx2_config_hw_rx_tstamp(pf, false); 2801 2802 cancel_work_sync(&pf->reset_task); 2803 /* Disable link notifications */ 2804 otx2_cgx_config_linkevents(pf, false); 2805 2806 otx2_unregister_dl(pf); 2807 unregister_netdev(netdev); 2808 otx2_sriov_disable(pf->pdev); 2809 otx2_sriov_vfcfg_cleanup(pf); 2810 if (pf->otx2_wq) 2811 destroy_workqueue(pf->otx2_wq); 2812 2813 otx2_ptp_destroy(pf); 2814 otx2_mcam_flow_del(pf); 2815 otx2_shutdown_tc(pf); 2816 otx2_detach_resources(&pf->mbox); 2817 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2818 qmem_free(pf->dev, pf->dync_lmt); 2819 otx2_disable_mbox_intr(pf); 2820 otx2_pfaf_mbox_destroy(pf); 2821 pci_free_irq_vectors(pf->pdev); 2822 pci_set_drvdata(pdev, NULL); 2823 free_netdev(netdev); 2824 2825 pci_release_regions(pdev); 2826 } 2827 2828 static struct pci_driver otx2_pf_driver = { 2829 .name = DRV_NAME, 2830 .id_table = otx2_pf_id_table, 2831 .probe = otx2_probe, 2832 .shutdown = otx2_remove, 2833 .remove = otx2_remove, 2834 .sriov_configure = otx2_sriov_configure 2835 }; 2836 2837 static int __init otx2_rvupf_init_module(void) 2838 { 2839 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2840 2841 return pci_register_driver(&otx2_pf_driver); 2842 } 2843 2844 static void __exit otx2_rvupf_cleanup_module(void) 2845 { 2846 pci_unregister_driver(&otx2_pf_driver); 2847 } 2848 2849 module_init(otx2_rvupf_init_module); 2850 module_exit(otx2_rvupf_cleanup_module); 2851