1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 19 #include "otx2_reg.h" 20 #include "otx2_common.h" 21 #include "otx2_txrx.h" 22 #include "otx2_struct.h" 23 #include "otx2_ptp.h" 24 #include "cn10k.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "rvu_nicpf" 28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 static void otx2_vf_link_event_task(struct work_struct *work); 42 43 enum { 44 TYPE_PFAF, 45 TYPE_PFVF, 46 }; 47 48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 50 51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 52 { 53 struct otx2_nic *pf = netdev_priv(netdev); 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 59 netdev->mtu); 60 return -EINVAL; 61 } 62 if (if_up) 63 otx2_stop(netdev); 64 65 netdev_info(netdev, "Changing MTU from %d to %d\n", 66 netdev->mtu, new_mtu); 67 netdev->mtu = new_mtu; 68 69 if (if_up) 70 err = otx2_open(netdev); 71 72 return err; 73 } 74 75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 76 { 77 int irq, vfs = pf->total_vfs; 78 79 /* Disable VFs ME interrupts */ 80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 82 free_irq(irq, pf); 83 84 /* Disable VFs FLR interrupts */ 85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 87 free_irq(irq, pf); 88 89 if (vfs <= 64) 90 return; 91 92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 94 free_irq(irq, pf); 95 96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 98 free_irq(irq, pf); 99 } 100 101 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 102 { 103 if (!pf->flr_wq) 104 return; 105 destroy_workqueue(pf->flr_wq); 106 pf->flr_wq = NULL; 107 devm_kfree(pf->dev, pf->flr_wrk); 108 } 109 110 static void otx2_flr_handler(struct work_struct *work) 111 { 112 struct flr_work *flrwork = container_of(work, struct flr_work, work); 113 struct otx2_nic *pf = flrwork->pf; 114 struct mbox *mbox = &pf->mbox; 115 struct msg_req *req; 116 int vf, reg = 0; 117 118 vf = flrwork - pf->flr_wrk; 119 120 mutex_lock(&mbox->lock); 121 req = otx2_mbox_alloc_msg_vf_flr(mbox); 122 if (!req) { 123 mutex_unlock(&mbox->lock); 124 return; 125 } 126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 128 129 if (!otx2_sync_mbox_msg(&pf->mbox)) { 130 if (vf >= 64) { 131 reg = 1; 132 vf = vf - 64; 133 } 134 /* clear transcation pending bit */ 135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 137 } 138 139 mutex_unlock(&mbox->lock); 140 } 141 142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 143 { 144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 145 int reg, dev, vf, start_vf, num_reg = 1; 146 u64 intr; 147 148 if (pf->total_vfs > 64) 149 num_reg = 2; 150 151 for (reg = 0; reg < num_reg; reg++) { 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 153 if (!intr) 154 continue; 155 start_vf = 64 * reg; 156 for (vf = 0; vf < 64; vf++) { 157 if (!(intr & BIT_ULL(vf))) 158 continue; 159 dev = vf + start_vf; 160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 161 /* Clear interrupt */ 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 163 /* Disable the interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 165 BIT_ULL(vf)); 166 } 167 } 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 172 { 173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 174 int vf, reg, num_reg = 1; 175 u64 intr; 176 177 if (pf->total_vfs > 64) 178 num_reg = 2; 179 180 for (reg = 0; reg < num_reg; reg++) { 181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 182 if (!intr) 183 continue; 184 for (vf = 0; vf < 64; vf++) { 185 if (!(intr & BIT_ULL(vf))) 186 continue; 187 /* clear trpend bit */ 188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 189 /* clear interrupt */ 190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 191 } 192 } 193 return IRQ_HANDLED; 194 } 195 196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 197 { 198 struct otx2_hw *hw = &pf->hw; 199 char *irq_name; 200 int ret; 201 202 /* Register ME interrupt handler*/ 203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 206 otx2_pf_me_intr_handler, 0, irq_name, pf); 207 if (ret) { 208 dev_err(pf->dev, 209 "RVUPF: IRQ registration failed for ME0\n"); 210 } 211 212 /* Register FLR interrupt handler */ 213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 216 otx2_pf_flr_intr_handler, 0, irq_name, pf); 217 if (ret) { 218 dev_err(pf->dev, 219 "RVUPF: IRQ registration failed for FLR0\n"); 220 return ret; 221 } 222 223 if (numvfs > 64) { 224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 226 rvu_get_pf(pf->pcifunc)); 227 ret = request_irq(pci_irq_vector 228 (pf->pdev, RVU_PF_INT_VEC_VFME1), 229 otx2_pf_me_intr_handler, 0, irq_name, pf); 230 if (ret) { 231 dev_err(pf->dev, 232 "RVUPF: IRQ registration failed for ME1\n"); 233 } 234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 236 rvu_get_pf(pf->pcifunc)); 237 ret = request_irq(pci_irq_vector 238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 239 otx2_pf_flr_intr_handler, 0, irq_name, pf); 240 if (ret) { 241 dev_err(pf->dev, 242 "RVUPF: IRQ registration failed for FLR1\n"); 243 return ret; 244 } 245 } 246 247 /* Enable ME interrupt for all VFs*/ 248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 250 251 /* Enable FLR interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 if (numvfs > 64) { 256 numvfs -= 64; 257 258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 260 INTR_MASK(numvfs)); 261 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 } 266 return 0; 267 } 268 269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 270 { 271 int vf; 272 273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 274 WQ_UNBOUND | WQ_HIGHPRI, 1); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 if (err) { 398 dev_warn(pf->dev, 399 "AF not responding to VF%d messages\n", vf); 400 /* restore PF mbase and exit */ 401 dst_mdev->mbase = pf->mbox.bbuf_base; 402 mutex_unlock(&pf->mbox.lock); 403 return err; 404 } 405 /* At this point, all the VF messages sent to AF are acked 406 * with proper responses and responses are copied to VF 407 * mailbox hence raise interrupt to VF. 408 */ 409 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 410 dst_mbox->mbox.rx_start); 411 req_hdr->num_msgs = num_msgs; 412 413 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 414 pf->mbox.bbuf_base, vf); 415 mutex_unlock(&pf->mbox.lock); 416 } else if (dir == MBOX_DIR_PFVF_UP) { 417 src_mdev = &src_mbox->dev[0]; 418 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 419 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 420 src_mbox->rx_start); 421 req_hdr->num_msgs = num_msgs; 422 423 dst_mbox = &pf->mbox_pfvf[0]; 424 dst_size = dst_mbox->mbox_up.tx_size - 425 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 426 /* Check if msgs fit into destination area */ 427 if (mbox_hdr->msg_size > dst_size) 428 return -EINVAL; 429 430 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 431 dst_mdev->mbase = src_mdev->mbase; 432 dst_mdev->msg_size = mbox_hdr->msg_size; 433 dst_mdev->num_msgs = mbox_hdr->num_msgs; 434 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 435 if (err) { 436 dev_warn(pf->dev, 437 "VF%d is not responding to mailbox\n", vf); 438 return err; 439 } 440 } else if (dir == MBOX_DIR_VFPF_UP) { 441 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 442 src_mbox->rx_start); 443 req_hdr->num_msgs = num_msgs; 444 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 445 &pf->mbox.mbox_up, 446 pf->mbox_pfvf[vf].bbuf_base, 447 0); 448 } 449 450 return 0; 451 } 452 453 static void otx2_pfvf_mbox_handler(struct work_struct *work) 454 { 455 struct mbox_msghdr *msg = NULL; 456 int offset, vf_idx, id, err; 457 struct otx2_mbox_dev *mdev; 458 struct mbox_hdr *req_hdr; 459 struct otx2_mbox *mbox; 460 struct mbox *vf_mbox; 461 struct otx2_nic *pf; 462 463 vf_mbox = container_of(work, struct mbox, mbox_wrk); 464 pf = vf_mbox->pfvf; 465 vf_idx = vf_mbox - pf->mbox_pfvf; 466 467 mbox = &pf->mbox_pfvf[0].mbox; 468 mdev = &mbox->dev[vf_idx]; 469 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 470 471 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 472 473 for (id = 0; id < vf_mbox->num_msgs; id++) { 474 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 475 offset); 476 477 if (msg->sig != OTX2_MBOX_REQ_SIG) 478 goto inval_msg; 479 480 /* Set VF's number in each of the msg */ 481 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 482 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 483 offset = msg->next_msgoff; 484 } 485 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 486 vf_mbox->num_msgs); 487 if (err) 488 goto inval_msg; 489 return; 490 491 inval_msg: 492 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 493 otx2_mbox_msg_send(mbox, vf_idx); 494 } 495 496 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 497 { 498 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 499 struct otx2_nic *pf = vf_mbox->pfvf; 500 struct otx2_mbox_dev *mdev; 501 int offset, id, vf_idx = 0; 502 struct mbox_hdr *rsp_hdr; 503 struct mbox_msghdr *msg; 504 struct otx2_mbox *mbox; 505 506 vf_idx = vf_mbox - pf->mbox_pfvf; 507 mbox = &pf->mbox_pfvf[0].mbox_up; 508 mdev = &mbox->dev[vf_idx]; 509 510 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 511 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 512 513 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 514 msg = mdev->mbase + offset; 515 516 if (msg->id >= MBOX_MSG_MAX) { 517 dev_err(pf->dev, 518 "Mbox msg with unknown ID 0x%x\n", msg->id); 519 goto end; 520 } 521 522 if (msg->sig != OTX2_MBOX_RSP_SIG) { 523 dev_err(pf->dev, 524 "Mbox msg with wrong signature %x, ID 0x%x\n", 525 msg->sig, msg->id); 526 goto end; 527 } 528 529 switch (msg->id) { 530 case MBOX_MSG_CGX_LINK_EVENT: 531 break; 532 default: 533 if (msg->rc) 534 dev_err(pf->dev, 535 "Mbox msg response has err %d, ID 0x%x\n", 536 msg->rc, msg->id); 537 break; 538 } 539 540 end: 541 offset = mbox->rx_start + msg->next_msgoff; 542 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 543 __otx2_mbox_reset(mbox, 0); 544 mdev->msgs_acked++; 545 } 546 } 547 548 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 549 { 550 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 551 int vfs = pf->total_vfs; 552 struct mbox *mbox; 553 u64 intr; 554 555 mbox = pf->mbox_pfvf; 556 /* Handle VF interrupts */ 557 if (vfs > 64) { 558 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 559 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 560 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 561 TYPE_PFVF); 562 vfs -= 64; 563 } 564 565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 567 568 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 569 570 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 571 572 return IRQ_HANDLED; 573 } 574 575 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 576 { 577 void __iomem *hwbase; 578 struct mbox *mbox; 579 int err, vf; 580 u64 base; 581 582 if (!numvfs) 583 return -EINVAL; 584 585 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 586 sizeof(struct mbox), GFP_KERNEL); 587 if (!pf->mbox_pfvf) 588 return -ENOMEM; 589 590 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 591 WQ_UNBOUND | WQ_HIGHPRI | 592 WQ_MEM_RECLAIM, 1); 593 if (!pf->mbox_pfvf_wq) 594 return -ENOMEM; 595 596 /* On CN10K platform, PF <-> VF mailbox region follows after 597 * PF <-> AF mailbox region. 598 */ 599 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 600 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 601 MBOX_SIZE; 602 else 603 base = readq((void __iomem *)((u64)pf->reg_base + 604 RVU_PF_VF_BAR4_ADDR)); 605 606 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 607 if (!hwbase) { 608 err = -ENOMEM; 609 goto free_wq; 610 } 611 612 mbox = &pf->mbox_pfvf[0]; 613 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 614 MBOX_DIR_PFVF, numvfs); 615 if (err) 616 goto free_iomem; 617 618 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF_UP, numvfs); 620 if (err) 621 goto free_iomem; 622 623 for (vf = 0; vf < numvfs; vf++) { 624 mbox->pfvf = pf; 625 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 626 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 627 mbox++; 628 } 629 630 return 0; 631 632 free_iomem: 633 if (hwbase) 634 iounmap(hwbase); 635 free_wq: 636 destroy_workqueue(pf->mbox_pfvf_wq); 637 return err; 638 } 639 640 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 641 { 642 struct mbox *mbox = &pf->mbox_pfvf[0]; 643 644 if (!mbox) 645 return; 646 647 if (pf->mbox_pfvf_wq) { 648 destroy_workqueue(pf->mbox_pfvf_wq); 649 pf->mbox_pfvf_wq = NULL; 650 } 651 652 if (mbox->mbox.hwbase) 653 iounmap(mbox->mbox.hwbase); 654 655 otx2_mbox_destroy(&mbox->mbox); 656 } 657 658 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 659 { 660 /* Clear PF <=> VF mailbox IRQ */ 661 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 663 664 /* Enable PF <=> VF mailbox IRQ */ 665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 666 if (numvfs > 64) { 667 numvfs -= 64; 668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 669 INTR_MASK(numvfs)); 670 } 671 } 672 673 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 674 { 675 int vector; 676 677 /* Disable PF <=> VF mailbox IRQ */ 678 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 679 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 680 681 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 682 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 683 free_irq(vector, pf); 684 685 if (numvfs > 64) { 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 688 free_irq(vector, pf); 689 } 690 } 691 692 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 693 { 694 struct otx2_hw *hw = &pf->hw; 695 char *irq_name; 696 int err; 697 698 /* Register MBOX0 interrupt handler */ 699 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 700 if (pf->pcifunc) 701 snprintf(irq_name, NAME_SIZE, 702 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 703 else 704 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 705 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 706 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 707 if (err) { 708 dev_err(pf->dev, 709 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 710 return err; 711 } 712 713 if (numvfs > 64) { 714 /* Register MBOX1 interrupt handler */ 715 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 716 if (pf->pcifunc) 717 snprintf(irq_name, NAME_SIZE, 718 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 719 else 720 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 721 err = request_irq(pci_irq_vector(pf->pdev, 722 RVU_PF_INT_VEC_VFPF_MBOX1), 723 otx2_pfvf_mbox_intr_handler, 724 0, irq_name, pf); 725 if (err) { 726 dev_err(pf->dev, 727 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 728 return err; 729 } 730 } 731 732 otx2_enable_pfvf_mbox_intr(pf, numvfs); 733 734 return 0; 735 } 736 737 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 738 struct mbox_msghdr *msg) 739 { 740 int devid; 741 742 if (msg->id >= MBOX_MSG_MAX) { 743 dev_err(pf->dev, 744 "Mbox msg with unknown ID 0x%x\n", msg->id); 745 return; 746 } 747 748 if (msg->sig != OTX2_MBOX_RSP_SIG) { 749 dev_err(pf->dev, 750 "Mbox msg with wrong signature %x, ID 0x%x\n", 751 msg->sig, msg->id); 752 return; 753 } 754 755 /* message response heading VF */ 756 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 757 if (devid) { 758 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 759 struct delayed_work *dwork; 760 761 switch (msg->id) { 762 case MBOX_MSG_NIX_LF_START_RX: 763 config->intf_down = false; 764 dwork = &config->link_event_work; 765 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 766 break; 767 case MBOX_MSG_NIX_LF_STOP_RX: 768 config->intf_down = true; 769 break; 770 } 771 772 return; 773 } 774 775 switch (msg->id) { 776 case MBOX_MSG_READY: 777 pf->pcifunc = msg->pcifunc; 778 break; 779 case MBOX_MSG_MSIX_OFFSET: 780 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 781 break; 782 case MBOX_MSG_NPA_LF_ALLOC: 783 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 784 break; 785 case MBOX_MSG_NIX_LF_ALLOC: 786 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 787 break; 788 case MBOX_MSG_NIX_TXSCH_ALLOC: 789 mbox_handler_nix_txsch_alloc(pf, 790 (struct nix_txsch_alloc_rsp *)msg); 791 break; 792 case MBOX_MSG_NIX_BP_ENABLE: 793 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 794 break; 795 case MBOX_MSG_CGX_STATS: 796 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 797 break; 798 case MBOX_MSG_CGX_FEC_STATS: 799 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 800 break; 801 default: 802 if (msg->rc) 803 dev_err(pf->dev, 804 "Mbox msg response has err %d, ID 0x%x\n", 805 msg->rc, msg->id); 806 break; 807 } 808 } 809 810 static void otx2_pfaf_mbox_handler(struct work_struct *work) 811 { 812 struct otx2_mbox_dev *mdev; 813 struct mbox_hdr *rsp_hdr; 814 struct mbox_msghdr *msg; 815 struct otx2_mbox *mbox; 816 struct mbox *af_mbox; 817 struct otx2_nic *pf; 818 int offset, id; 819 820 af_mbox = container_of(work, struct mbox, mbox_wrk); 821 mbox = &af_mbox->mbox; 822 mdev = &mbox->dev[0]; 823 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 824 825 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 826 pf = af_mbox->pfvf; 827 828 for (id = 0; id < af_mbox->num_msgs; id++) { 829 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 830 otx2_process_pfaf_mbox_msg(pf, msg); 831 offset = mbox->rx_start + msg->next_msgoff; 832 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 833 __otx2_mbox_reset(mbox, 0); 834 mdev->msgs_acked++; 835 } 836 837 } 838 839 static void otx2_handle_link_event(struct otx2_nic *pf) 840 { 841 struct cgx_link_user_info *linfo = &pf->linfo; 842 struct net_device *netdev = pf->netdev; 843 844 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 845 linfo->link_up ? "UP" : "DOWN", linfo->speed, 846 linfo->full_duplex ? "Full" : "Half"); 847 if (linfo->link_up) { 848 netif_carrier_on(netdev); 849 netif_tx_start_all_queues(netdev); 850 } else { 851 netif_tx_stop_all_queues(netdev); 852 netif_carrier_off(netdev); 853 } 854 } 855 856 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 857 struct cgx_link_info_msg *msg, 858 struct msg_rsp *rsp) 859 { 860 int i; 861 862 /* Copy the link info sent by AF */ 863 pf->linfo = msg->link_info; 864 865 /* notify VFs about link event */ 866 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 867 struct otx2_vf_config *config = &pf->vf_configs[i]; 868 struct delayed_work *dwork = &config->link_event_work; 869 870 if (config->intf_down) 871 continue; 872 873 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 874 } 875 876 /* interface has not been fully configured yet */ 877 if (pf->flags & OTX2_FLAG_INTF_DOWN) 878 return 0; 879 880 otx2_handle_link_event(pf); 881 return 0; 882 } 883 884 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 885 struct mbox_msghdr *req) 886 { 887 /* Check if valid, if not reply with a invalid msg */ 888 if (req->sig != OTX2_MBOX_REQ_SIG) { 889 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 890 return -ENODEV; 891 } 892 893 switch (req->id) { 894 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 895 case _id: { \ 896 struct _rsp_type *rsp; \ 897 int err; \ 898 \ 899 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 900 &pf->mbox.mbox_up, 0, \ 901 sizeof(struct _rsp_type)); \ 902 if (!rsp) \ 903 return -ENOMEM; \ 904 \ 905 rsp->hdr.id = _id; \ 906 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 907 rsp->hdr.pcifunc = 0; \ 908 rsp->hdr.rc = 0; \ 909 \ 910 err = otx2_mbox_up_handler_ ## _fn_name( \ 911 pf, (struct _req_type *)req, rsp); \ 912 return err; \ 913 } 914 MBOX_UP_CGX_MESSAGES 915 #undef M 916 break; 917 default: 918 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 919 return -ENODEV; 920 } 921 return 0; 922 } 923 924 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 925 { 926 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 927 struct otx2_mbox *mbox = &af_mbox->mbox_up; 928 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 929 struct otx2_nic *pf = af_mbox->pfvf; 930 int offset, id, devid = 0; 931 struct mbox_hdr *rsp_hdr; 932 struct mbox_msghdr *msg; 933 934 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 935 936 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 937 938 for (id = 0; id < af_mbox->up_num_msgs; id++) { 939 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 940 941 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 942 /* Skip processing VF's messages */ 943 if (!devid) 944 otx2_process_mbox_msg_up(pf, msg); 945 offset = mbox->rx_start + msg->next_msgoff; 946 } 947 if (devid) { 948 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 949 MBOX_DIR_PFVF_UP, devid - 1, 950 af_mbox->up_num_msgs); 951 return; 952 } 953 954 otx2_mbox_msg_send(mbox, 0); 955 } 956 957 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 958 { 959 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 960 struct mbox *mbox; 961 962 /* Clear the IRQ */ 963 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 964 965 mbox = &pf->mbox; 966 967 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 968 969 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 970 971 return IRQ_HANDLED; 972 } 973 974 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 975 { 976 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 977 978 /* Disable AF => PF mailbox IRQ */ 979 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 980 free_irq(vector, pf); 981 } 982 983 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 984 { 985 struct otx2_hw *hw = &pf->hw; 986 struct msg_req *req; 987 char *irq_name; 988 int err; 989 990 /* Register mailbox interrupt handler */ 991 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 992 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 993 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 994 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 995 if (err) { 996 dev_err(pf->dev, 997 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 998 return err; 999 } 1000 1001 /* Enable mailbox interrupt for msgs coming from AF. 1002 * First clear to avoid spurious interrupts, if any. 1003 */ 1004 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1005 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1006 1007 if (!probe_af) 1008 return 0; 1009 1010 /* Check mailbox communication with AF */ 1011 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1012 if (!req) { 1013 otx2_disable_mbox_intr(pf); 1014 return -ENOMEM; 1015 } 1016 err = otx2_sync_mbox_msg(&pf->mbox); 1017 if (err) { 1018 dev_warn(pf->dev, 1019 "AF not responding to mailbox, deferring probe\n"); 1020 otx2_disable_mbox_intr(pf); 1021 return -EPROBE_DEFER; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1028 { 1029 struct mbox *mbox = &pf->mbox; 1030 1031 if (pf->mbox_wq) { 1032 destroy_workqueue(pf->mbox_wq); 1033 pf->mbox_wq = NULL; 1034 } 1035 1036 if (mbox->mbox.hwbase) 1037 iounmap((void __iomem *)mbox->mbox.hwbase); 1038 1039 otx2_mbox_destroy(&mbox->mbox); 1040 otx2_mbox_destroy(&mbox->mbox_up); 1041 } 1042 1043 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1044 { 1045 struct mbox *mbox = &pf->mbox; 1046 void __iomem *hwbase; 1047 int err; 1048 1049 mbox->pfvf = pf; 1050 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1051 WQ_UNBOUND | WQ_HIGHPRI | 1052 WQ_MEM_RECLAIM, 1); 1053 if (!pf->mbox_wq) 1054 return -ENOMEM; 1055 1056 /* Mailbox is a reserved memory (in RAM) region shared between 1057 * admin function (i.e AF) and this PF, shouldn't be mapped as 1058 * device memory to allow unaligned accesses. 1059 */ 1060 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1061 MBOX_SIZE); 1062 if (!hwbase) { 1063 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1064 err = -ENOMEM; 1065 goto exit; 1066 } 1067 1068 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1069 MBOX_DIR_PFAF, 1); 1070 if (err) 1071 goto exit; 1072 1073 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1074 MBOX_DIR_PFAF_UP, 1); 1075 if (err) 1076 goto exit; 1077 1078 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1079 if (err) 1080 goto exit; 1081 1082 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1083 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1084 mutex_init(&mbox->lock); 1085 1086 return 0; 1087 exit: 1088 otx2_pfaf_mbox_destroy(pf); 1089 return err; 1090 } 1091 1092 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1093 { 1094 struct msg_req *msg; 1095 int err; 1096 1097 mutex_lock(&pf->mbox.lock); 1098 if (enable) 1099 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1100 else 1101 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1102 1103 if (!msg) { 1104 mutex_unlock(&pf->mbox.lock); 1105 return -ENOMEM; 1106 } 1107 1108 err = otx2_sync_mbox_msg(&pf->mbox); 1109 mutex_unlock(&pf->mbox.lock); 1110 return err; 1111 } 1112 1113 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1114 { 1115 struct msg_req *msg; 1116 int err; 1117 1118 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap, 1119 pf->flow_cfg->dmacflt_max_flows)) 1120 netdev_warn(pf->netdev, 1121 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1122 1123 mutex_lock(&pf->mbox.lock); 1124 if (enable) 1125 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1126 else 1127 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1128 1129 if (!msg) { 1130 mutex_unlock(&pf->mbox.lock); 1131 return -ENOMEM; 1132 } 1133 1134 err = otx2_sync_mbox_msg(&pf->mbox); 1135 mutex_unlock(&pf->mbox.lock); 1136 return err; 1137 } 1138 1139 int otx2_set_real_num_queues(struct net_device *netdev, 1140 int tx_queues, int rx_queues) 1141 { 1142 int err; 1143 1144 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1145 if (err) { 1146 netdev_err(netdev, 1147 "Failed to set no of Tx queues: %d\n", tx_queues); 1148 return err; 1149 } 1150 1151 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1152 if (err) 1153 netdev_err(netdev, 1154 "Failed to set no of Rx queues: %d\n", rx_queues); 1155 return err; 1156 } 1157 EXPORT_SYMBOL(otx2_set_real_num_queues); 1158 1159 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1160 { 1161 struct otx2_nic *pf = data; 1162 u64 val, *ptr; 1163 u64 qidx = 0; 1164 1165 /* CQ */ 1166 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1167 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1168 val = otx2_atomic64_add((qidx << 44), ptr); 1169 1170 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1171 (val & NIX_CQERRINT_BITS)); 1172 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1173 continue; 1174 1175 if (val & BIT_ULL(42)) { 1176 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1177 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1178 } else { 1179 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1180 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1181 qidx); 1182 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1183 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1184 qidx); 1185 } 1186 1187 schedule_work(&pf->reset_task); 1188 } 1189 1190 /* SQ */ 1191 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1192 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1193 val = otx2_atomic64_add((qidx << 44), ptr); 1194 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1195 (val & NIX_SQINT_BITS)); 1196 1197 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1198 continue; 1199 1200 if (val & BIT_ULL(42)) { 1201 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1202 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1203 } else { 1204 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1205 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1206 qidx, 1207 otx2_read64(pf, 1208 NIX_LF_SQ_OP_ERR_DBG)); 1209 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1210 BIT_ULL(44)); 1211 } 1212 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1213 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1214 qidx, 1215 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1216 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1217 BIT_ULL(44)); 1218 } 1219 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1220 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1221 qidx, 1222 otx2_read64(pf, 1223 NIX_LF_SEND_ERR_DBG)); 1224 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1225 BIT_ULL(44)); 1226 } 1227 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1228 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1229 qidx); 1230 } 1231 1232 schedule_work(&pf->reset_task); 1233 } 1234 1235 return IRQ_HANDLED; 1236 } 1237 1238 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1239 { 1240 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1241 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1242 int qidx = cq_poll->cint_idx; 1243 1244 /* Disable interrupts. 1245 * 1246 * Completion interrupts behave in a level-triggered interrupt 1247 * fashion, and hence have to be cleared only after it is serviced. 1248 */ 1249 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1250 1251 /* Schedule NAPI */ 1252 napi_schedule_irqoff(&cq_poll->napi); 1253 1254 return IRQ_HANDLED; 1255 } 1256 1257 static void otx2_disable_napi(struct otx2_nic *pf) 1258 { 1259 struct otx2_qset *qset = &pf->qset; 1260 struct otx2_cq_poll *cq_poll; 1261 int qidx; 1262 1263 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1264 cq_poll = &qset->napi[qidx]; 1265 napi_disable(&cq_poll->napi); 1266 netif_napi_del(&cq_poll->napi); 1267 } 1268 } 1269 1270 static void otx2_free_cq_res(struct otx2_nic *pf) 1271 { 1272 struct otx2_qset *qset = &pf->qset; 1273 struct otx2_cq_queue *cq; 1274 int qidx; 1275 1276 /* Disable CQs */ 1277 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1278 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1279 cq = &qset->cq[qidx]; 1280 qmem_free(pf->dev, cq->cqe); 1281 } 1282 } 1283 1284 static void otx2_free_sq_res(struct otx2_nic *pf) 1285 { 1286 struct otx2_qset *qset = &pf->qset; 1287 struct otx2_snd_queue *sq; 1288 int qidx; 1289 1290 /* Disable SQs */ 1291 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1292 /* Free SQB pointers */ 1293 otx2_sq_free_sqbs(pf); 1294 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1295 sq = &qset->sq[qidx]; 1296 qmem_free(pf->dev, sq->sqe); 1297 qmem_free(pf->dev, sq->tso_hdrs); 1298 kfree(sq->sg); 1299 kfree(sq->sqb_ptrs); 1300 } 1301 } 1302 1303 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1304 { 1305 int frame_size; 1306 int total_size; 1307 int rbuf_size; 1308 1309 /* The data transferred by NIX to memory consists of actual packet 1310 * plus additional data which has timestamp and/or EDSA/HIGIG2 1311 * headers if interface is configured in corresponding modes. 1312 * NIX transfers entire data using 6 segments/buffers and writes 1313 * a CQE_RX descriptor with those segment addresses. First segment 1314 * has additional data prepended to packet. Also software omits a 1315 * headroom of 128 bytes and sizeof(struct skb_shared_info) in 1316 * each segment. Hence the total size of memory needed 1317 * to receive a packet with 'mtu' is: 1318 * frame size = mtu + additional data; 1319 * memory = frame_size + (headroom + struct skb_shared_info size) * 6; 1320 * each receive buffer size = memory / 6; 1321 */ 1322 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1323 total_size = frame_size + (OTX2_HEAD_ROOM + 1324 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) * 6; 1325 rbuf_size = total_size / 6; 1326 1327 return ALIGN(rbuf_size, 2048); 1328 } 1329 1330 static int otx2_init_hw_resources(struct otx2_nic *pf) 1331 { 1332 struct nix_lf_free_req *free_req; 1333 struct mbox *mbox = &pf->mbox; 1334 struct otx2_hw *hw = &pf->hw; 1335 struct msg_req *req; 1336 int err = 0, lvl; 1337 1338 /* Set required NPA LF's pool counts 1339 * Auras and Pools are used in a 1:1 mapping, 1340 * so, aura count = pool count. 1341 */ 1342 hw->rqpool_cnt = hw->rx_queues; 1343 hw->sqpool_cnt = hw->tot_tx_queues; 1344 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1345 1346 pf->max_frs = pf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1347 1348 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1349 1350 mutex_lock(&mbox->lock); 1351 /* NPA init */ 1352 err = otx2_config_npa(pf); 1353 if (err) 1354 goto exit; 1355 1356 /* NIX init */ 1357 err = otx2_config_nix(pf); 1358 if (err) 1359 goto err_free_npa_lf; 1360 1361 /* Enable backpressure */ 1362 otx2_nix_config_bp(pf, true); 1363 1364 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1365 err = otx2_rq_aura_pool_init(pf); 1366 if (err) { 1367 mutex_unlock(&mbox->lock); 1368 goto err_free_nix_lf; 1369 } 1370 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1371 err = otx2_sq_aura_pool_init(pf); 1372 if (err) { 1373 mutex_unlock(&mbox->lock); 1374 goto err_free_rq_ptrs; 1375 } 1376 1377 err = otx2_txsch_alloc(pf); 1378 if (err) { 1379 mutex_unlock(&mbox->lock); 1380 goto err_free_sq_ptrs; 1381 } 1382 1383 err = otx2_config_nix_queues(pf); 1384 if (err) { 1385 mutex_unlock(&mbox->lock); 1386 goto err_free_txsch; 1387 } 1388 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1389 err = otx2_txschq_config(pf, lvl); 1390 if (err) { 1391 mutex_unlock(&mbox->lock); 1392 goto err_free_nix_queues; 1393 } 1394 } 1395 mutex_unlock(&mbox->lock); 1396 return err; 1397 1398 err_free_nix_queues: 1399 otx2_free_sq_res(pf); 1400 otx2_free_cq_res(pf); 1401 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1402 err_free_txsch: 1403 if (otx2_txschq_stop(pf)) 1404 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1405 err_free_sq_ptrs: 1406 otx2_sq_free_sqbs(pf); 1407 err_free_rq_ptrs: 1408 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1409 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1410 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1411 otx2_aura_pool_free(pf); 1412 err_free_nix_lf: 1413 mutex_lock(&mbox->lock); 1414 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1415 if (free_req) { 1416 free_req->flags = NIX_LF_DISABLE_FLOWS; 1417 if (otx2_sync_mbox_msg(mbox)) 1418 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1419 } 1420 err_free_npa_lf: 1421 /* Reset NPA LF */ 1422 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1423 if (req) { 1424 if (otx2_sync_mbox_msg(mbox)) 1425 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1426 } 1427 exit: 1428 mutex_unlock(&mbox->lock); 1429 return err; 1430 } 1431 1432 static void otx2_free_hw_resources(struct otx2_nic *pf) 1433 { 1434 struct otx2_qset *qset = &pf->qset; 1435 struct nix_lf_free_req *free_req; 1436 struct mbox *mbox = &pf->mbox; 1437 struct otx2_cq_queue *cq; 1438 struct msg_req *req; 1439 int qidx, err; 1440 1441 /* Ensure all SQE are processed */ 1442 otx2_sqb_flush(pf); 1443 1444 /* Stop transmission */ 1445 err = otx2_txschq_stop(pf); 1446 if (err) 1447 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1448 1449 mutex_lock(&mbox->lock); 1450 /* Disable backpressure */ 1451 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1452 otx2_nix_config_bp(pf, false); 1453 mutex_unlock(&mbox->lock); 1454 1455 /* Disable RQs */ 1456 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1457 1458 /*Dequeue all CQEs */ 1459 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1460 cq = &qset->cq[qidx]; 1461 if (cq->cq_type == CQ_RX) 1462 otx2_cleanup_rx_cqes(pf, cq); 1463 else 1464 otx2_cleanup_tx_cqes(pf, cq); 1465 } 1466 1467 otx2_free_sq_res(pf); 1468 1469 /* Free RQ buffer pointers*/ 1470 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1471 1472 otx2_free_cq_res(pf); 1473 1474 /* Free all ingress bandwidth profiles allocated */ 1475 cn10k_free_all_ipolicers(pf); 1476 1477 mutex_lock(&mbox->lock); 1478 /* Reset NIX LF */ 1479 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1480 if (free_req) { 1481 free_req->flags = NIX_LF_DISABLE_FLOWS; 1482 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1483 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1484 if (otx2_sync_mbox_msg(mbox)) 1485 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1486 } 1487 mutex_unlock(&mbox->lock); 1488 1489 /* Disable NPA Pool and Aura hw context */ 1490 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1491 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1492 otx2_aura_pool_free(pf); 1493 1494 mutex_lock(&mbox->lock); 1495 /* Reset NPA LF */ 1496 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1497 if (req) { 1498 if (otx2_sync_mbox_msg(mbox)) 1499 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1500 } 1501 mutex_unlock(&mbox->lock); 1502 } 1503 1504 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1505 { 1506 struct net_device *netdev = pf->netdev; 1507 struct nix_rx_mode *req; 1508 bool promisc = false; 1509 1510 if (!(netdev->flags & IFF_UP)) 1511 return; 1512 1513 if ((netdev->flags & IFF_PROMISC) || 1514 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1515 promisc = true; 1516 } 1517 1518 /* Write unicast address to mcam entries or del from mcam */ 1519 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1520 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1521 1522 mutex_lock(&pf->mbox.lock); 1523 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1524 if (!req) { 1525 mutex_unlock(&pf->mbox.lock); 1526 return; 1527 } 1528 1529 req->mode = NIX_RX_MODE_UCAST; 1530 1531 if (promisc) 1532 req->mode |= NIX_RX_MODE_PROMISC; 1533 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1534 req->mode |= NIX_RX_MODE_ALLMULTI; 1535 1536 req->mode |= NIX_RX_MODE_USE_MCE; 1537 1538 otx2_sync_mbox_msg(&pf->mbox); 1539 mutex_unlock(&pf->mbox.lock); 1540 } 1541 1542 int otx2_open(struct net_device *netdev) 1543 { 1544 struct otx2_nic *pf = netdev_priv(netdev); 1545 struct otx2_cq_poll *cq_poll = NULL; 1546 struct otx2_qset *qset = &pf->qset; 1547 int err = 0, qidx, vec; 1548 char *irq_name; 1549 1550 netif_carrier_off(netdev); 1551 1552 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1553 /* RQ and SQs are mapped to different CQs, 1554 * so find out max CQ IRQs (i.e CINTs) needed. 1555 */ 1556 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1557 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1558 if (!qset->napi) 1559 return -ENOMEM; 1560 1561 /* CQ size of RQ */ 1562 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1563 /* CQ size of SQ */ 1564 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1565 1566 err = -ENOMEM; 1567 qset->cq = kcalloc(pf->qset.cq_cnt, 1568 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1569 if (!qset->cq) 1570 goto err_free_mem; 1571 1572 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1573 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1574 if (!qset->sq) 1575 goto err_free_mem; 1576 1577 qset->rq = kcalloc(pf->hw.rx_queues, 1578 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1579 if (!qset->rq) 1580 goto err_free_mem; 1581 1582 err = otx2_init_hw_resources(pf); 1583 if (err) 1584 goto err_free_mem; 1585 1586 /* Register NAPI handler */ 1587 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1588 cq_poll = &qset->napi[qidx]; 1589 cq_poll->cint_idx = qidx; 1590 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1591 * 'cq_ids[0]' points to RQ's CQ and 1592 * 'cq_ids[1]' points to SQ's CQ and 1593 * 'cq_ids[2]' points to XDP's CQ and 1594 */ 1595 cq_poll->cq_ids[CQ_RX] = 1596 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1597 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1598 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1599 if (pf->xdp_prog) 1600 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1601 (qidx + pf->hw.rx_queues + 1602 pf->hw.tx_queues) : 1603 CINT_INVALID_CQ; 1604 else 1605 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1606 1607 cq_poll->dev = (void *)pf; 1608 netif_napi_add(netdev, &cq_poll->napi, 1609 otx2_napi_handler, NAPI_POLL_WEIGHT); 1610 napi_enable(&cq_poll->napi); 1611 } 1612 1613 /* Set maximum frame size allowed in HW */ 1614 err = otx2_hw_set_mtu(pf, netdev->mtu); 1615 if (err) 1616 goto err_disable_napi; 1617 1618 /* Setup segmentation algorithms, if failed, clear offload capability */ 1619 otx2_setup_segmentation(pf); 1620 1621 /* Initialize RSS */ 1622 err = otx2_rss_init(pf); 1623 if (err) 1624 goto err_disable_napi; 1625 1626 /* Register Queue IRQ handlers */ 1627 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1628 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1629 1630 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1631 1632 err = request_irq(pci_irq_vector(pf->pdev, vec), 1633 otx2_q_intr_handler, 0, irq_name, pf); 1634 if (err) { 1635 dev_err(pf->dev, 1636 "RVUPF%d: IRQ registration failed for QERR\n", 1637 rvu_get_pf(pf->pcifunc)); 1638 goto err_disable_napi; 1639 } 1640 1641 /* Enable QINT IRQ */ 1642 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1643 1644 /* Register CQ IRQ handlers */ 1645 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1646 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1647 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1648 1649 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1650 qidx); 1651 1652 err = request_irq(pci_irq_vector(pf->pdev, vec), 1653 otx2_cq_intr_handler, 0, irq_name, 1654 &qset->napi[qidx]); 1655 if (err) { 1656 dev_err(pf->dev, 1657 "RVUPF%d: IRQ registration failed for CQ%d\n", 1658 rvu_get_pf(pf->pcifunc), qidx); 1659 goto err_free_cints; 1660 } 1661 vec++; 1662 1663 otx2_config_irq_coalescing(pf, qidx); 1664 1665 /* Enable CQ IRQ */ 1666 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1667 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1668 } 1669 1670 otx2_set_cints_affinity(pf); 1671 1672 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1673 otx2_enable_rxvlan(pf, true); 1674 1675 /* When reinitializing enable time stamping if it is enabled before */ 1676 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1677 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1678 otx2_config_hw_tx_tstamp(pf, true); 1679 } 1680 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1681 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1682 otx2_config_hw_rx_tstamp(pf, true); 1683 } 1684 1685 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1686 /* 'intf_down' may be checked on any cpu */ 1687 smp_wmb(); 1688 1689 /* we have already received link status notification */ 1690 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1691 otx2_handle_link_event(pf); 1692 1693 /* Restore pause frame settings */ 1694 otx2_config_pause_frm(pf); 1695 1696 /* Install DMAC Filters */ 1697 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1698 otx2_dmacflt_reinstall_flows(pf); 1699 1700 err = otx2_rxtx_enable(pf, true); 1701 if (err) 1702 goto err_tx_stop_queues; 1703 1704 otx2_do_set_rx_mode(pf); 1705 1706 return 0; 1707 1708 err_tx_stop_queues: 1709 netif_tx_stop_all_queues(netdev); 1710 netif_carrier_off(netdev); 1711 pf->flags |= OTX2_FLAG_INTF_DOWN; 1712 err_free_cints: 1713 otx2_free_cints(pf, qidx); 1714 vec = pci_irq_vector(pf->pdev, 1715 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1716 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1717 synchronize_irq(vec); 1718 free_irq(vec, pf); 1719 err_disable_napi: 1720 otx2_disable_napi(pf); 1721 otx2_free_hw_resources(pf); 1722 err_free_mem: 1723 kfree(qset->sq); 1724 kfree(qset->cq); 1725 kfree(qset->rq); 1726 kfree(qset->napi); 1727 return err; 1728 } 1729 EXPORT_SYMBOL(otx2_open); 1730 1731 int otx2_stop(struct net_device *netdev) 1732 { 1733 struct otx2_nic *pf = netdev_priv(netdev); 1734 struct otx2_cq_poll *cq_poll = NULL; 1735 struct otx2_qset *qset = &pf->qset; 1736 struct otx2_rss_info *rss; 1737 int qidx, vec, wrk; 1738 1739 /* If the DOWN flag is set resources are already freed */ 1740 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1741 return 0; 1742 1743 netif_carrier_off(netdev); 1744 netif_tx_stop_all_queues(netdev); 1745 1746 pf->flags |= OTX2_FLAG_INTF_DOWN; 1747 /* 'intf_down' may be checked on any cpu */ 1748 smp_wmb(); 1749 1750 /* First stop packet Rx/Tx */ 1751 otx2_rxtx_enable(pf, false); 1752 1753 /* Clear RSS enable flag */ 1754 rss = &pf->hw.rss_info; 1755 rss->enable = false; 1756 1757 /* Cleanup Queue IRQ */ 1758 vec = pci_irq_vector(pf->pdev, 1759 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1760 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1761 synchronize_irq(vec); 1762 free_irq(vec, pf); 1763 1764 /* Cleanup CQ NAPI and IRQ */ 1765 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1766 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1767 /* Disable interrupt */ 1768 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1769 1770 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1771 1772 cq_poll = &qset->napi[qidx]; 1773 napi_synchronize(&cq_poll->napi); 1774 vec++; 1775 } 1776 1777 netif_tx_disable(netdev); 1778 1779 otx2_free_hw_resources(pf); 1780 otx2_free_cints(pf, pf->hw.cint_cnt); 1781 otx2_disable_napi(pf); 1782 1783 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1784 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1785 1786 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1787 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1788 devm_kfree(pf->dev, pf->refill_wrk); 1789 1790 kfree(qset->sq); 1791 kfree(qset->cq); 1792 kfree(qset->rq); 1793 kfree(qset->napi); 1794 /* Do not clear RQ/SQ ringsize settings */ 1795 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1796 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1797 return 0; 1798 } 1799 EXPORT_SYMBOL(otx2_stop); 1800 1801 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1802 { 1803 struct otx2_nic *pf = netdev_priv(netdev); 1804 int qidx = skb_get_queue_mapping(skb); 1805 struct otx2_snd_queue *sq; 1806 struct netdev_queue *txq; 1807 1808 /* Check for minimum and maximum packet length */ 1809 if (skb->len <= ETH_HLEN || 1810 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1811 dev_kfree_skb(skb); 1812 return NETDEV_TX_OK; 1813 } 1814 1815 sq = &pf->qset.sq[qidx]; 1816 txq = netdev_get_tx_queue(netdev, qidx); 1817 1818 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1819 netif_tx_stop_queue(txq); 1820 1821 /* Check again, incase SQBs got freed up */ 1822 smp_mb(); 1823 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1824 > sq->sqe_thresh) 1825 netif_tx_wake_queue(txq); 1826 1827 return NETDEV_TX_BUSY; 1828 } 1829 1830 return NETDEV_TX_OK; 1831 } 1832 1833 static netdev_features_t otx2_fix_features(struct net_device *dev, 1834 netdev_features_t features) 1835 { 1836 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1837 features |= NETIF_F_HW_VLAN_STAG_RX; 1838 else 1839 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1840 1841 return features; 1842 } 1843 1844 static void otx2_set_rx_mode(struct net_device *netdev) 1845 { 1846 struct otx2_nic *pf = netdev_priv(netdev); 1847 1848 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1849 } 1850 1851 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 1852 { 1853 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1854 1855 otx2_do_set_rx_mode(pf); 1856 } 1857 1858 static int otx2_set_features(struct net_device *netdev, 1859 netdev_features_t features) 1860 { 1861 netdev_features_t changed = features ^ netdev->features; 1862 bool ntuple = !!(features & NETIF_F_NTUPLE); 1863 struct otx2_nic *pf = netdev_priv(netdev); 1864 bool tc = !!(features & NETIF_F_HW_TC); 1865 1866 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1867 return otx2_cgx_config_loopback(pf, 1868 features & NETIF_F_LOOPBACK); 1869 1870 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1871 return otx2_enable_rxvlan(pf, 1872 features & NETIF_F_HW_VLAN_CTAG_RX); 1873 1874 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1875 otx2_destroy_ntuple_flows(pf); 1876 1877 if ((changed & NETIF_F_NTUPLE) && ntuple) { 1878 if (!pf->flow_cfg->max_flows) { 1879 netdev_err(netdev, 1880 "Can't enable NTUPLE, MCAM entries not allocated\n"); 1881 return -EINVAL; 1882 } 1883 } 1884 1885 if ((changed & NETIF_F_HW_TC) && tc) { 1886 if (!pf->flow_cfg->max_flows) { 1887 netdev_err(netdev, 1888 "Can't enable TC, MCAM entries not allocated\n"); 1889 return -EINVAL; 1890 } 1891 } 1892 1893 if ((changed & NETIF_F_HW_TC) && !tc && 1894 pf->flow_cfg && pf->flow_cfg->nr_flows) { 1895 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1896 return -EBUSY; 1897 } 1898 1899 if ((changed & NETIF_F_NTUPLE) && ntuple && 1900 (netdev->features & NETIF_F_HW_TC) && !(changed & NETIF_F_HW_TC)) { 1901 netdev_err(netdev, 1902 "Can't enable NTUPLE when TC is active, disable TC and retry\n"); 1903 return -EINVAL; 1904 } 1905 1906 if ((changed & NETIF_F_HW_TC) && tc && 1907 (netdev->features & NETIF_F_NTUPLE) && !(changed & NETIF_F_NTUPLE)) { 1908 netdev_err(netdev, 1909 "Can't enable TC when NTUPLE is active, disable NTUPLE and retry\n"); 1910 return -EINVAL; 1911 } 1912 1913 return 0; 1914 } 1915 1916 static void otx2_reset_task(struct work_struct *work) 1917 { 1918 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1919 1920 if (!netif_running(pf->netdev)) 1921 return; 1922 1923 rtnl_lock(); 1924 otx2_stop(pf->netdev); 1925 pf->reset_count++; 1926 otx2_open(pf->netdev); 1927 netif_trans_update(pf->netdev); 1928 rtnl_unlock(); 1929 } 1930 1931 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1932 { 1933 struct msg_req *req; 1934 int err; 1935 1936 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1937 return 0; 1938 1939 mutex_lock(&pfvf->mbox.lock); 1940 if (enable) 1941 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1942 else 1943 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1944 if (!req) { 1945 mutex_unlock(&pfvf->mbox.lock); 1946 return -ENOMEM; 1947 } 1948 1949 err = otx2_sync_mbox_msg(&pfvf->mbox); 1950 if (err) { 1951 mutex_unlock(&pfvf->mbox.lock); 1952 return err; 1953 } 1954 1955 mutex_unlock(&pfvf->mbox.lock); 1956 if (enable) 1957 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1958 else 1959 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1960 return 0; 1961 } 1962 1963 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1964 { 1965 struct msg_req *req; 1966 int err; 1967 1968 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1969 return 0; 1970 1971 mutex_lock(&pfvf->mbox.lock); 1972 if (enable) 1973 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1974 else 1975 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1976 if (!req) { 1977 mutex_unlock(&pfvf->mbox.lock); 1978 return -ENOMEM; 1979 } 1980 1981 err = otx2_sync_mbox_msg(&pfvf->mbox); 1982 if (err) { 1983 mutex_unlock(&pfvf->mbox.lock); 1984 return err; 1985 } 1986 1987 mutex_unlock(&pfvf->mbox.lock); 1988 if (enable) 1989 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1990 else 1991 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1992 return 0; 1993 } 1994 1995 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1996 { 1997 struct otx2_nic *pfvf = netdev_priv(netdev); 1998 struct hwtstamp_config config; 1999 2000 if (!pfvf->ptp) 2001 return -ENODEV; 2002 2003 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2004 return -EFAULT; 2005 2006 /* reserved for future extensions */ 2007 if (config.flags) 2008 return -EINVAL; 2009 2010 switch (config.tx_type) { 2011 case HWTSTAMP_TX_OFF: 2012 otx2_config_hw_tx_tstamp(pfvf, false); 2013 break; 2014 case HWTSTAMP_TX_ON: 2015 otx2_config_hw_tx_tstamp(pfvf, true); 2016 break; 2017 default: 2018 return -ERANGE; 2019 } 2020 2021 switch (config.rx_filter) { 2022 case HWTSTAMP_FILTER_NONE: 2023 otx2_config_hw_rx_tstamp(pfvf, false); 2024 break; 2025 case HWTSTAMP_FILTER_ALL: 2026 case HWTSTAMP_FILTER_SOME: 2027 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2028 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2029 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2030 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2031 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2032 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2033 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2034 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2035 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2036 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2037 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2038 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2039 otx2_config_hw_rx_tstamp(pfvf, true); 2040 config.rx_filter = HWTSTAMP_FILTER_ALL; 2041 break; 2042 default: 2043 return -ERANGE; 2044 } 2045 2046 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2047 2048 return copy_to_user(ifr->ifr_data, &config, 2049 sizeof(config)) ? -EFAULT : 0; 2050 } 2051 EXPORT_SYMBOL(otx2_config_hwtstamp); 2052 2053 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2054 { 2055 struct otx2_nic *pfvf = netdev_priv(netdev); 2056 struct hwtstamp_config *cfg = &pfvf->tstamp; 2057 2058 switch (cmd) { 2059 case SIOCSHWTSTAMP: 2060 return otx2_config_hwtstamp(netdev, req); 2061 case SIOCGHWTSTAMP: 2062 return copy_to_user(req->ifr_data, cfg, 2063 sizeof(*cfg)) ? -EFAULT : 0; 2064 default: 2065 return -EOPNOTSUPP; 2066 } 2067 } 2068 EXPORT_SYMBOL(otx2_ioctl); 2069 2070 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2071 { 2072 struct npc_install_flow_req *req; 2073 int err; 2074 2075 mutex_lock(&pf->mbox.lock); 2076 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2077 if (!req) { 2078 err = -ENOMEM; 2079 goto out; 2080 } 2081 2082 ether_addr_copy(req->packet.dmac, mac); 2083 eth_broadcast_addr((u8 *)&req->mask.dmac); 2084 req->features = BIT_ULL(NPC_DMAC); 2085 req->channel = pf->hw.rx_chan_base; 2086 req->intf = NIX_INTF_RX; 2087 req->default_rule = 1; 2088 req->append = 1; 2089 req->vf = vf + 1; 2090 req->op = NIX_RX_ACTION_DEFAULT; 2091 2092 err = otx2_sync_mbox_msg(&pf->mbox); 2093 out: 2094 mutex_unlock(&pf->mbox.lock); 2095 return err; 2096 } 2097 2098 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2099 { 2100 struct otx2_nic *pf = netdev_priv(netdev); 2101 struct pci_dev *pdev = pf->pdev; 2102 struct otx2_vf_config *config; 2103 int ret; 2104 2105 if (!netif_running(netdev)) 2106 return -EAGAIN; 2107 2108 if (vf >= pf->total_vfs) 2109 return -EINVAL; 2110 2111 if (!is_valid_ether_addr(mac)) 2112 return -EINVAL; 2113 2114 config = &pf->vf_configs[vf]; 2115 ether_addr_copy(config->mac, mac); 2116 2117 ret = otx2_do_set_vf_mac(pf, vf, mac); 2118 if (ret == 0) 2119 dev_info(&pdev->dev, 2120 "Load/Reload VF driver\n"); 2121 2122 return ret; 2123 } 2124 2125 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2126 __be16 proto) 2127 { 2128 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2129 struct nix_vtag_config_rsp *vtag_rsp; 2130 struct npc_delete_flow_req *del_req; 2131 struct nix_vtag_config *vtag_req; 2132 struct npc_install_flow_req *req; 2133 struct otx2_vf_config *config; 2134 int err = 0; 2135 u32 idx; 2136 2137 config = &pf->vf_configs[vf]; 2138 2139 if (!vlan && !config->vlan) 2140 goto out; 2141 2142 mutex_lock(&pf->mbox.lock); 2143 2144 /* free old tx vtag entry */ 2145 if (config->vlan) { 2146 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2147 if (!vtag_req) { 2148 err = -ENOMEM; 2149 goto out; 2150 } 2151 vtag_req->cfg_type = 0; 2152 vtag_req->tx.free_vtag0 = 1; 2153 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2154 2155 err = otx2_sync_mbox_msg(&pf->mbox); 2156 if (err) 2157 goto out; 2158 } 2159 2160 if (!vlan && config->vlan) { 2161 /* rx */ 2162 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2163 if (!del_req) { 2164 err = -ENOMEM; 2165 goto out; 2166 } 2167 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2168 del_req->entry = 2169 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2170 err = otx2_sync_mbox_msg(&pf->mbox); 2171 if (err) 2172 goto out; 2173 2174 /* tx */ 2175 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2176 if (!del_req) { 2177 err = -ENOMEM; 2178 goto out; 2179 } 2180 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2181 del_req->entry = 2182 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2183 err = otx2_sync_mbox_msg(&pf->mbox); 2184 2185 goto out; 2186 } 2187 2188 /* rx */ 2189 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2190 if (!req) { 2191 err = -ENOMEM; 2192 goto out; 2193 } 2194 2195 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2196 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2197 req->packet.vlan_tci = htons(vlan); 2198 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2199 /* af fills the destination mac addr */ 2200 eth_broadcast_addr((u8 *)&req->mask.dmac); 2201 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2202 req->channel = pf->hw.rx_chan_base; 2203 req->intf = NIX_INTF_RX; 2204 req->vf = vf + 1; 2205 req->op = NIX_RX_ACTION_DEFAULT; 2206 req->vtag0_valid = true; 2207 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2208 req->set_cntr = 1; 2209 2210 err = otx2_sync_mbox_msg(&pf->mbox); 2211 if (err) 2212 goto out; 2213 2214 /* tx */ 2215 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2216 if (!vtag_req) { 2217 err = -ENOMEM; 2218 goto out; 2219 } 2220 2221 /* configure tx vtag params */ 2222 vtag_req->vtag_size = VTAGSIZE_T4; 2223 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2224 vtag_req->tx.cfg_vtag0 = 1; 2225 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2226 2227 err = otx2_sync_mbox_msg(&pf->mbox); 2228 if (err) 2229 goto out; 2230 2231 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2232 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2233 if (IS_ERR(vtag_rsp)) { 2234 err = PTR_ERR(vtag_rsp); 2235 goto out; 2236 } 2237 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2238 2239 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2240 if (!req) { 2241 err = -ENOMEM; 2242 goto out; 2243 } 2244 2245 eth_zero_addr((u8 *)&req->mask.dmac); 2246 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2247 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2248 req->features = BIT_ULL(NPC_DMAC); 2249 req->channel = pf->hw.tx_chan_base; 2250 req->intf = NIX_INTF_TX; 2251 req->vf = vf + 1; 2252 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2253 req->vtag0_def = vtag_rsp->vtag0_idx; 2254 req->vtag0_op = VTAG_INSERT; 2255 req->set_cntr = 1; 2256 2257 err = otx2_sync_mbox_msg(&pf->mbox); 2258 out: 2259 config->vlan = vlan; 2260 mutex_unlock(&pf->mbox.lock); 2261 return err; 2262 } 2263 2264 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2265 __be16 proto) 2266 { 2267 struct otx2_nic *pf = netdev_priv(netdev); 2268 struct pci_dev *pdev = pf->pdev; 2269 2270 if (!netif_running(netdev)) 2271 return -EAGAIN; 2272 2273 if (vf >= pci_num_vf(pdev)) 2274 return -EINVAL; 2275 2276 /* qos is currently unsupported */ 2277 if (vlan >= VLAN_N_VID || qos) 2278 return -EINVAL; 2279 2280 if (proto != htons(ETH_P_8021Q)) 2281 return -EPROTONOSUPPORT; 2282 2283 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2284 return -EOPNOTSUPP; 2285 2286 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2287 } 2288 2289 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2290 struct ifla_vf_info *ivi) 2291 { 2292 struct otx2_nic *pf = netdev_priv(netdev); 2293 struct pci_dev *pdev = pf->pdev; 2294 struct otx2_vf_config *config; 2295 2296 if (!netif_running(netdev)) 2297 return -EAGAIN; 2298 2299 if (vf >= pci_num_vf(pdev)) 2300 return -EINVAL; 2301 2302 config = &pf->vf_configs[vf]; 2303 ivi->vf = vf; 2304 ether_addr_copy(ivi->mac, config->mac); 2305 ivi->vlan = config->vlan; 2306 ivi->trusted = config->trusted; 2307 2308 return 0; 2309 } 2310 2311 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2312 int qidx) 2313 { 2314 struct page *page; 2315 u64 dma_addr; 2316 int err = 0; 2317 2318 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2319 offset_in_page(xdpf->data), xdpf->len, 2320 DMA_TO_DEVICE); 2321 if (dma_mapping_error(pf->dev, dma_addr)) 2322 return -ENOMEM; 2323 2324 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2325 if (!err) { 2326 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2327 page = virt_to_page(xdpf->data); 2328 put_page(page); 2329 return -ENOMEM; 2330 } 2331 return 0; 2332 } 2333 2334 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2335 struct xdp_frame **frames, u32 flags) 2336 { 2337 struct otx2_nic *pf = netdev_priv(netdev); 2338 int qidx = smp_processor_id(); 2339 struct otx2_snd_queue *sq; 2340 int drops = 0, i; 2341 2342 if (!netif_running(netdev)) 2343 return -ENETDOWN; 2344 2345 qidx += pf->hw.tx_queues; 2346 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2347 2348 /* Abort xmit if xdp queue is not */ 2349 if (unlikely(!sq)) 2350 return -ENXIO; 2351 2352 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2353 return -EINVAL; 2354 2355 for (i = 0; i < n; i++) { 2356 struct xdp_frame *xdpf = frames[i]; 2357 int err; 2358 2359 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2360 if (err) 2361 drops++; 2362 } 2363 return n - drops; 2364 } 2365 2366 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2367 { 2368 struct net_device *dev = pf->netdev; 2369 bool if_up = netif_running(pf->netdev); 2370 struct bpf_prog *old_prog; 2371 2372 if (prog && dev->mtu > MAX_XDP_MTU) { 2373 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2374 return -EOPNOTSUPP; 2375 } 2376 2377 if (if_up) 2378 otx2_stop(pf->netdev); 2379 2380 old_prog = xchg(&pf->xdp_prog, prog); 2381 2382 if (old_prog) 2383 bpf_prog_put(old_prog); 2384 2385 if (pf->xdp_prog) 2386 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2387 2388 /* Network stack and XDP shared same rx queues. 2389 * Use separate tx queues for XDP and network stack. 2390 */ 2391 if (pf->xdp_prog) 2392 pf->hw.xdp_queues = pf->hw.rx_queues; 2393 else 2394 pf->hw.xdp_queues = 0; 2395 2396 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2397 2398 if (if_up) 2399 otx2_open(pf->netdev); 2400 2401 return 0; 2402 } 2403 2404 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2405 { 2406 struct otx2_nic *pf = netdev_priv(netdev); 2407 2408 switch (xdp->command) { 2409 case XDP_SETUP_PROG: 2410 return otx2_xdp_setup(pf, xdp->prog); 2411 default: 2412 return -EINVAL; 2413 } 2414 } 2415 2416 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2417 int req_perm) 2418 { 2419 struct set_vf_perm *req; 2420 int rc; 2421 2422 mutex_lock(&pf->mbox.lock); 2423 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2424 if (!req) { 2425 rc = -ENOMEM; 2426 goto out; 2427 } 2428 2429 /* Let AF reset VF permissions as sriov is disabled */ 2430 if (req_perm == OTX2_RESET_VF_PERM) { 2431 req->flags |= RESET_VF_PERM; 2432 } else if (req_perm == OTX2_TRUSTED_VF) { 2433 if (pf->vf_configs[vf].trusted) 2434 req->flags |= VF_TRUSTED; 2435 } 2436 2437 req->vf = vf; 2438 rc = otx2_sync_mbox_msg(&pf->mbox); 2439 out: 2440 mutex_unlock(&pf->mbox.lock); 2441 return rc; 2442 } 2443 2444 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2445 bool enable) 2446 { 2447 struct otx2_nic *pf = netdev_priv(netdev); 2448 struct pci_dev *pdev = pf->pdev; 2449 int rc; 2450 2451 if (vf >= pci_num_vf(pdev)) 2452 return -EINVAL; 2453 2454 if (pf->vf_configs[vf].trusted == enable) 2455 return 0; 2456 2457 pf->vf_configs[vf].trusted = enable; 2458 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2459 2460 if (rc) 2461 pf->vf_configs[vf].trusted = !enable; 2462 else 2463 netdev_info(pf->netdev, "VF %d is %strusted\n", 2464 vf, enable ? "" : "not "); 2465 return rc; 2466 } 2467 2468 static const struct net_device_ops otx2_netdev_ops = { 2469 .ndo_open = otx2_open, 2470 .ndo_stop = otx2_stop, 2471 .ndo_start_xmit = otx2_xmit, 2472 .ndo_fix_features = otx2_fix_features, 2473 .ndo_set_mac_address = otx2_set_mac_address, 2474 .ndo_change_mtu = otx2_change_mtu, 2475 .ndo_set_rx_mode = otx2_set_rx_mode, 2476 .ndo_set_features = otx2_set_features, 2477 .ndo_tx_timeout = otx2_tx_timeout, 2478 .ndo_get_stats64 = otx2_get_stats64, 2479 .ndo_eth_ioctl = otx2_ioctl, 2480 .ndo_set_vf_mac = otx2_set_vf_mac, 2481 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2482 .ndo_get_vf_config = otx2_get_vf_config, 2483 .ndo_bpf = otx2_xdp, 2484 .ndo_xdp_xmit = otx2_xdp_xmit, 2485 .ndo_setup_tc = otx2_setup_tc, 2486 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2487 }; 2488 2489 static int otx2_wq_init(struct otx2_nic *pf) 2490 { 2491 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2492 if (!pf->otx2_wq) 2493 return -ENOMEM; 2494 2495 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2496 INIT_WORK(&pf->reset_task, otx2_reset_task); 2497 return 0; 2498 } 2499 2500 static int otx2_check_pf_usable(struct otx2_nic *nic) 2501 { 2502 u64 rev; 2503 2504 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2505 rev = (rev >> 12) & 0xFF; 2506 /* Check if AF has setup revision for RVUM block, 2507 * otherwise this driver probe should be deferred 2508 * until AF driver comes up. 2509 */ 2510 if (!rev) { 2511 dev_warn(nic->dev, 2512 "AF is not initialized, deferring probe\n"); 2513 return -EPROBE_DEFER; 2514 } 2515 return 0; 2516 } 2517 2518 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2519 { 2520 struct otx2_hw *hw = &pf->hw; 2521 int num_vec, err; 2522 2523 /* NPA interrupts are inot registered, so alloc only 2524 * upto NIX vector offset. 2525 */ 2526 num_vec = hw->nix_msixoff; 2527 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2528 2529 otx2_disable_mbox_intr(pf); 2530 pci_free_irq_vectors(hw->pdev); 2531 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2532 if (err < 0) { 2533 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2534 __func__, num_vec); 2535 return err; 2536 } 2537 2538 return otx2_register_mbox_intr(pf, false); 2539 } 2540 2541 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2542 { 2543 int i; 2544 2545 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2546 sizeof(struct otx2_vf_config), 2547 GFP_KERNEL); 2548 if (!pf->vf_configs) 2549 return -ENOMEM; 2550 2551 for (i = 0; i < pf->total_vfs; i++) { 2552 pf->vf_configs[i].pf = pf; 2553 pf->vf_configs[i].intf_down = true; 2554 pf->vf_configs[i].trusted = false; 2555 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2556 otx2_vf_link_event_task); 2557 } 2558 2559 return 0; 2560 } 2561 2562 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2563 { 2564 int i; 2565 2566 if (!pf->vf_configs) 2567 return; 2568 2569 for (i = 0; i < pf->total_vfs; i++) { 2570 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2571 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2572 } 2573 } 2574 2575 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2576 { 2577 struct device *dev = &pdev->dev; 2578 struct net_device *netdev; 2579 struct otx2_nic *pf; 2580 struct otx2_hw *hw; 2581 int err, qcount; 2582 int num_vec; 2583 2584 err = pcim_enable_device(pdev); 2585 if (err) { 2586 dev_err(dev, "Failed to enable PCI device\n"); 2587 return err; 2588 } 2589 2590 err = pci_request_regions(pdev, DRV_NAME); 2591 if (err) { 2592 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2593 return err; 2594 } 2595 2596 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2597 if (err) { 2598 dev_err(dev, "DMA mask config failed, abort\n"); 2599 goto err_release_regions; 2600 } 2601 2602 pci_set_master(pdev); 2603 2604 /* Set number of queues */ 2605 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2606 2607 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2608 if (!netdev) { 2609 err = -ENOMEM; 2610 goto err_release_regions; 2611 } 2612 2613 pci_set_drvdata(pdev, netdev); 2614 SET_NETDEV_DEV(netdev, &pdev->dev); 2615 pf = netdev_priv(netdev); 2616 pf->netdev = netdev; 2617 pf->pdev = pdev; 2618 pf->dev = dev; 2619 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2620 pf->flags |= OTX2_FLAG_INTF_DOWN; 2621 2622 hw = &pf->hw; 2623 hw->pdev = pdev; 2624 hw->rx_queues = qcount; 2625 hw->tx_queues = qcount; 2626 hw->tot_tx_queues = qcount; 2627 hw->max_queues = qcount; 2628 2629 num_vec = pci_msix_vec_count(pdev); 2630 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2631 GFP_KERNEL); 2632 if (!hw->irq_name) { 2633 err = -ENOMEM; 2634 goto err_free_netdev; 2635 } 2636 2637 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2638 sizeof(cpumask_var_t), GFP_KERNEL); 2639 if (!hw->affinity_mask) { 2640 err = -ENOMEM; 2641 goto err_free_netdev; 2642 } 2643 2644 /* Map CSRs */ 2645 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2646 if (!pf->reg_base) { 2647 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2648 err = -ENOMEM; 2649 goto err_free_netdev; 2650 } 2651 2652 err = otx2_check_pf_usable(pf); 2653 if (err) 2654 goto err_free_netdev; 2655 2656 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2657 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2658 if (err < 0) { 2659 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2660 __func__, num_vec); 2661 goto err_free_netdev; 2662 } 2663 2664 otx2_setup_dev_hw_settings(pf); 2665 2666 /* Init PF <=> AF mailbox stuff */ 2667 err = otx2_pfaf_mbox_init(pf); 2668 if (err) 2669 goto err_free_irq_vectors; 2670 2671 /* Register mailbox interrupt */ 2672 err = otx2_register_mbox_intr(pf, true); 2673 if (err) 2674 goto err_mbox_destroy; 2675 2676 /* Request AF to attach NPA and NIX LFs to this PF. 2677 * NIX and NPA LFs are needed for this PF to function as a NIC. 2678 */ 2679 err = otx2_attach_npa_nix(pf); 2680 if (err) 2681 goto err_disable_mbox_intr; 2682 2683 err = otx2_realloc_msix_vectors(pf); 2684 if (err) 2685 goto err_detach_rsrc; 2686 2687 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2688 if (err) 2689 goto err_detach_rsrc; 2690 2691 err = cn10k_lmtst_init(pf); 2692 if (err) 2693 goto err_detach_rsrc; 2694 2695 /* Assign default mac address */ 2696 otx2_get_mac_from_af(netdev); 2697 2698 /* Don't check for error. Proceed without ptp */ 2699 otx2_ptp_init(pf); 2700 2701 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2702 * HW allocates buffer pointer from stack and uses it for DMA'ing 2703 * ingress packet. In some scenarios HW can free back allocated buffer 2704 * pointers to pool. This makes it impossible for SW to maintain a 2705 * parallel list where physical addresses of buffer pointers (IOVAs) 2706 * given to HW can be saved for later reference. 2707 * 2708 * So the only way to convert Rx packet's buffer address is to use 2709 * IOMMU's iova_to_phys() handler which translates the address by 2710 * walking through the translation tables. 2711 */ 2712 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2713 2714 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2715 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2716 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2717 NETIF_F_GSO_UDP_L4); 2718 netdev->features |= netdev->hw_features; 2719 2720 err = otx2_mcam_flow_init(pf); 2721 if (err) 2722 goto err_ptp_destroy; 2723 2724 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2725 netdev->hw_features |= NETIF_F_NTUPLE; 2726 2727 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2728 netdev->priv_flags |= IFF_UNICAST_FLT; 2729 2730 /* Support TSO on tag interface */ 2731 netdev->vlan_features |= netdev->features; 2732 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2733 NETIF_F_HW_VLAN_STAG_TX; 2734 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2735 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2736 NETIF_F_HW_VLAN_STAG_RX; 2737 netdev->features |= netdev->hw_features; 2738 2739 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2740 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2741 netdev->hw_features |= NETIF_F_HW_TC; 2742 2743 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2744 2745 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2746 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2747 2748 netdev->netdev_ops = &otx2_netdev_ops; 2749 2750 netdev->min_mtu = OTX2_MIN_MTU; 2751 netdev->max_mtu = otx2_get_max_mtu(pf); 2752 2753 err = register_netdev(netdev); 2754 if (err) { 2755 dev_err(dev, "Failed to register netdevice\n"); 2756 goto err_del_mcam_entries; 2757 } 2758 2759 err = otx2_wq_init(pf); 2760 if (err) 2761 goto err_unreg_netdev; 2762 2763 otx2_set_ethtool_ops(netdev); 2764 2765 err = otx2_init_tc(pf); 2766 if (err) 2767 goto err_mcam_flow_del; 2768 2769 err = otx2_register_dl(pf); 2770 if (err) 2771 goto err_mcam_flow_del; 2772 2773 /* Initialize SR-IOV resources */ 2774 err = otx2_sriov_vfcfg_init(pf); 2775 if (err) 2776 goto err_pf_sriov_init; 2777 2778 /* Enable link notifications */ 2779 otx2_cgx_config_linkevents(pf, true); 2780 2781 /* Enable pause frames by default */ 2782 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2783 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2784 2785 return 0; 2786 2787 err_pf_sriov_init: 2788 otx2_shutdown_tc(pf); 2789 err_mcam_flow_del: 2790 otx2_mcam_flow_del(pf); 2791 err_unreg_netdev: 2792 unregister_netdev(netdev); 2793 err_del_mcam_entries: 2794 otx2_mcam_flow_del(pf); 2795 err_ptp_destroy: 2796 otx2_ptp_destroy(pf); 2797 err_detach_rsrc: 2798 if (pf->hw.lmt_info) 2799 free_percpu(pf->hw.lmt_info); 2800 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2801 qmem_free(pf->dev, pf->dync_lmt); 2802 otx2_detach_resources(&pf->mbox); 2803 err_disable_mbox_intr: 2804 otx2_disable_mbox_intr(pf); 2805 err_mbox_destroy: 2806 otx2_pfaf_mbox_destroy(pf); 2807 err_free_irq_vectors: 2808 pci_free_irq_vectors(hw->pdev); 2809 err_free_netdev: 2810 pci_set_drvdata(pdev, NULL); 2811 free_netdev(netdev); 2812 err_release_regions: 2813 pci_release_regions(pdev); 2814 return err; 2815 } 2816 2817 static void otx2_vf_link_event_task(struct work_struct *work) 2818 { 2819 struct otx2_vf_config *config; 2820 struct cgx_link_info_msg *req; 2821 struct mbox_msghdr *msghdr; 2822 struct otx2_nic *pf; 2823 int vf_idx; 2824 2825 config = container_of(work, struct otx2_vf_config, 2826 link_event_work.work); 2827 vf_idx = config - config->pf->vf_configs; 2828 pf = config->pf; 2829 2830 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2831 sizeof(*req), sizeof(struct msg_rsp)); 2832 if (!msghdr) { 2833 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2834 return; 2835 } 2836 2837 req = (struct cgx_link_info_msg *)msghdr; 2838 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2839 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2840 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2841 2842 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2843 } 2844 2845 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2846 { 2847 struct net_device *netdev = pci_get_drvdata(pdev); 2848 struct otx2_nic *pf = netdev_priv(netdev); 2849 int ret; 2850 2851 /* Init PF <=> VF mailbox stuff */ 2852 ret = otx2_pfvf_mbox_init(pf, numvfs); 2853 if (ret) 2854 return ret; 2855 2856 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2857 if (ret) 2858 goto free_mbox; 2859 2860 ret = otx2_pf_flr_init(pf, numvfs); 2861 if (ret) 2862 goto free_intr; 2863 2864 ret = otx2_register_flr_me_intr(pf, numvfs); 2865 if (ret) 2866 goto free_flr; 2867 2868 ret = pci_enable_sriov(pdev, numvfs); 2869 if (ret) 2870 goto free_flr_intr; 2871 2872 return numvfs; 2873 free_flr_intr: 2874 otx2_disable_flr_me_intr(pf); 2875 free_flr: 2876 otx2_flr_wq_destroy(pf); 2877 free_intr: 2878 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2879 free_mbox: 2880 otx2_pfvf_mbox_destroy(pf); 2881 return ret; 2882 } 2883 2884 static int otx2_sriov_disable(struct pci_dev *pdev) 2885 { 2886 struct net_device *netdev = pci_get_drvdata(pdev); 2887 struct otx2_nic *pf = netdev_priv(netdev); 2888 int numvfs = pci_num_vf(pdev); 2889 2890 if (!numvfs) 2891 return 0; 2892 2893 pci_disable_sriov(pdev); 2894 2895 otx2_disable_flr_me_intr(pf); 2896 otx2_flr_wq_destroy(pf); 2897 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2898 otx2_pfvf_mbox_destroy(pf); 2899 2900 return 0; 2901 } 2902 2903 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2904 { 2905 if (numvfs == 0) 2906 return otx2_sriov_disable(pdev); 2907 else 2908 return otx2_sriov_enable(pdev, numvfs); 2909 } 2910 2911 static void otx2_remove(struct pci_dev *pdev) 2912 { 2913 struct net_device *netdev = pci_get_drvdata(pdev); 2914 struct otx2_nic *pf; 2915 2916 if (!netdev) 2917 return; 2918 2919 pf = netdev_priv(netdev); 2920 2921 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2922 2923 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2924 otx2_config_hw_tx_tstamp(pf, false); 2925 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2926 otx2_config_hw_rx_tstamp(pf, false); 2927 2928 cancel_work_sync(&pf->reset_task); 2929 /* Disable link notifications */ 2930 otx2_cgx_config_linkevents(pf, false); 2931 2932 otx2_unregister_dl(pf); 2933 unregister_netdev(netdev); 2934 otx2_sriov_disable(pf->pdev); 2935 otx2_sriov_vfcfg_cleanup(pf); 2936 if (pf->otx2_wq) 2937 destroy_workqueue(pf->otx2_wq); 2938 2939 otx2_ptp_destroy(pf); 2940 otx2_mcam_flow_del(pf); 2941 otx2_shutdown_tc(pf); 2942 otx2_detach_resources(&pf->mbox); 2943 if (pf->hw.lmt_info) 2944 free_percpu(pf->hw.lmt_info); 2945 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2946 qmem_free(pf->dev, pf->dync_lmt); 2947 otx2_disable_mbox_intr(pf); 2948 otx2_pfaf_mbox_destroy(pf); 2949 pci_free_irq_vectors(pf->pdev); 2950 pci_set_drvdata(pdev, NULL); 2951 free_netdev(netdev); 2952 2953 pci_release_regions(pdev); 2954 } 2955 2956 static struct pci_driver otx2_pf_driver = { 2957 .name = DRV_NAME, 2958 .id_table = otx2_pf_id_table, 2959 .probe = otx2_probe, 2960 .shutdown = otx2_remove, 2961 .remove = otx2_remove, 2962 .sriov_configure = otx2_sriov_configure 2963 }; 2964 2965 static int __init otx2_rvupf_init_module(void) 2966 { 2967 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2968 2969 return pci_register_driver(&otx2_pf_driver); 2970 } 2971 2972 static void __exit otx2_rvupf_cleanup_module(void) 2973 { 2974 pci_unregister_driver(&otx2_pf_driver); 2975 } 2976 2977 module_init(otx2_rvupf_init_module); 2978 module_exit(otx2_rvupf_cleanup_module); 2979