1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include "cn10k.h" 26 #include "qos.h" 27 #include <rvu_trace.h> 28 29 #define DRV_NAME "rvu_nicpf" 30 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 31 32 /* Supported devices */ 33 static const struct pci_device_id otx2_pf_id_table[] = { 34 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 35 { 0, } /* end of table */ 36 }; 37 38 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 39 MODULE_DESCRIPTION(DRV_STRING); 40 MODULE_LICENSE("GPL v2"); 41 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 42 43 static void otx2_vf_link_event_task(struct work_struct *work); 44 45 enum { 46 TYPE_PFAF, 47 TYPE_PFVF, 48 }; 49 50 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 51 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 52 53 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 54 { 55 struct otx2_nic *pf = netdev_priv(netdev); 56 bool if_up = netif_running(netdev); 57 int err = 0; 58 59 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 60 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 61 netdev->mtu); 62 return -EINVAL; 63 } 64 if (if_up) 65 otx2_stop(netdev); 66 67 netdev_info(netdev, "Changing MTU from %d to %d\n", 68 netdev->mtu, new_mtu); 69 netdev->mtu = new_mtu; 70 71 if (if_up) 72 err = otx2_open(netdev); 73 74 return err; 75 } 76 77 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 78 { 79 int irq, vfs = pf->total_vfs; 80 81 /* Disable VFs ME interrupts */ 82 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 83 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 84 free_irq(irq, pf); 85 86 /* Disable VFs FLR interrupts */ 87 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 88 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 89 free_irq(irq, pf); 90 91 if (vfs <= 64) 92 return; 93 94 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 95 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 96 free_irq(irq, pf); 97 98 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 99 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 100 free_irq(irq, pf); 101 } 102 103 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 104 { 105 if (!pf->flr_wq) 106 return; 107 destroy_workqueue(pf->flr_wq); 108 pf->flr_wq = NULL; 109 devm_kfree(pf->dev, pf->flr_wrk); 110 } 111 112 static void otx2_flr_handler(struct work_struct *work) 113 { 114 struct flr_work *flrwork = container_of(work, struct flr_work, work); 115 struct otx2_nic *pf = flrwork->pf; 116 struct mbox *mbox = &pf->mbox; 117 struct msg_req *req; 118 int vf, reg = 0; 119 120 vf = flrwork - pf->flr_wrk; 121 122 mutex_lock(&mbox->lock); 123 req = otx2_mbox_alloc_msg_vf_flr(mbox); 124 if (!req) { 125 mutex_unlock(&mbox->lock); 126 return; 127 } 128 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 129 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 130 131 if (!otx2_sync_mbox_msg(&pf->mbox)) { 132 if (vf >= 64) { 133 reg = 1; 134 vf = vf - 64; 135 } 136 /* clear transcation pending bit */ 137 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 138 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 139 } 140 141 mutex_unlock(&mbox->lock); 142 } 143 144 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 145 { 146 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 147 int reg, dev, vf, start_vf, num_reg = 1; 148 u64 intr; 149 150 if (pf->total_vfs > 64) 151 num_reg = 2; 152 153 for (reg = 0; reg < num_reg; reg++) { 154 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 155 if (!intr) 156 continue; 157 start_vf = 64 * reg; 158 for (vf = 0; vf < 64; vf++) { 159 if (!(intr & BIT_ULL(vf))) 160 continue; 161 dev = vf + start_vf; 162 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 163 /* Clear interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 165 /* Disable the interrupt */ 166 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 167 BIT_ULL(vf)); 168 } 169 } 170 return IRQ_HANDLED; 171 } 172 173 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 174 { 175 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 176 int vf, reg, num_reg = 1; 177 u64 intr; 178 179 if (pf->total_vfs > 64) 180 num_reg = 2; 181 182 for (reg = 0; reg < num_reg; reg++) { 183 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 184 if (!intr) 185 continue; 186 for (vf = 0; vf < 64; vf++) { 187 if (!(intr & BIT_ULL(vf))) 188 continue; 189 /* clear trpend bit */ 190 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 191 /* clear interrupt */ 192 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 193 } 194 } 195 return IRQ_HANDLED; 196 } 197 198 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 199 { 200 struct otx2_hw *hw = &pf->hw; 201 char *irq_name; 202 int ret; 203 204 /* Register ME interrupt handler*/ 205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 208 otx2_pf_me_intr_handler, 0, irq_name, pf); 209 if (ret) { 210 dev_err(pf->dev, 211 "RVUPF: IRQ registration failed for ME0\n"); 212 } 213 214 /* Register FLR interrupt handler */ 215 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 216 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 217 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 218 otx2_pf_flr_intr_handler, 0, irq_name, pf); 219 if (ret) { 220 dev_err(pf->dev, 221 "RVUPF: IRQ registration failed for FLR0\n"); 222 return ret; 223 } 224 225 if (numvfs > 64) { 226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 228 rvu_get_pf(pf->pcifunc)); 229 ret = request_irq(pci_irq_vector 230 (pf->pdev, RVU_PF_INT_VEC_VFME1), 231 otx2_pf_me_intr_handler, 0, irq_name, pf); 232 if (ret) { 233 dev_err(pf->dev, 234 "RVUPF: IRQ registration failed for ME1\n"); 235 } 236 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 237 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 238 rvu_get_pf(pf->pcifunc)); 239 ret = request_irq(pci_irq_vector 240 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 241 otx2_pf_flr_intr_handler, 0, irq_name, pf); 242 if (ret) { 243 dev_err(pf->dev, 244 "RVUPF: IRQ registration failed for FLR1\n"); 245 return ret; 246 } 247 } 248 249 /* Enable ME interrupt for all VFs*/ 250 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 252 253 /* Enable FLR interrupt for all VFs*/ 254 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 256 257 if (numvfs > 64) { 258 numvfs -= 64; 259 260 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 261 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 262 INTR_MASK(numvfs)); 263 264 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 265 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 266 INTR_MASK(numvfs)); 267 } 268 return 0; 269 } 270 271 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 272 { 273 int vf; 274 275 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 276 if (!pf->flr_wq) 277 return -ENOMEM; 278 279 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 280 sizeof(struct flr_work), GFP_KERNEL); 281 if (!pf->flr_wrk) { 282 destroy_workqueue(pf->flr_wq); 283 return -ENOMEM; 284 } 285 286 for (vf = 0; vf < num_vfs; vf++) { 287 pf->flr_wrk[vf].pf = pf; 288 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 289 } 290 291 return 0; 292 } 293 294 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 295 int first, int mdevs, u64 intr, int type) 296 { 297 struct otx2_mbox_dev *mdev; 298 struct otx2_mbox *mbox; 299 struct mbox_hdr *hdr; 300 int i; 301 302 for (i = first; i < mdevs; i++) { 303 /* start from 0 */ 304 if (!(intr & BIT_ULL(i - first))) 305 continue; 306 307 mbox = &mw->mbox; 308 mdev = &mbox->dev[i]; 309 if (type == TYPE_PFAF) 310 otx2_sync_mbox_bbuf(mbox, i); 311 hdr = mdev->mbase + mbox->rx_start; 312 /* The hdr->num_msgs is set to zero immediately in the interrupt 313 * handler to ensure that it holds a correct value next time 314 * when the interrupt handler is called. 315 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 316 * pf>mbox.up_num_msgs holds the data for use in 317 * pfaf_mbox_up_handler. 318 */ 319 if (hdr->num_msgs) { 320 mw[i].num_msgs = hdr->num_msgs; 321 hdr->num_msgs = 0; 322 if (type == TYPE_PFAF) 323 memset(mbox->hwbase + mbox->rx_start, 0, 324 ALIGN(sizeof(struct mbox_hdr), 325 sizeof(u64))); 326 327 queue_work(mbox_wq, &mw[i].mbox_wrk); 328 } 329 330 mbox = &mw->mbox_up; 331 mdev = &mbox->dev[i]; 332 if (type == TYPE_PFAF) 333 otx2_sync_mbox_bbuf(mbox, i); 334 hdr = mdev->mbase + mbox->rx_start; 335 if (hdr->num_msgs) { 336 mw[i].up_num_msgs = hdr->num_msgs; 337 hdr->num_msgs = 0; 338 if (type == TYPE_PFAF) 339 memset(mbox->hwbase + mbox->rx_start, 0, 340 ALIGN(sizeof(struct mbox_hdr), 341 sizeof(u64))); 342 343 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 344 } 345 } 346 } 347 348 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 349 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 350 int devid) 351 { 352 struct otx2_mbox_dev *src_mdev = mdev; 353 int offset; 354 355 /* Msgs are already copied, trigger VF's mbox irq */ 356 smp_wmb(); 357 358 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 359 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 360 361 /* Restore VF's mbox bounce buffer region address */ 362 src_mdev->mbase = bbuf_base; 363 } 364 365 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 366 struct otx2_mbox *src_mbox, 367 int dir, int vf, int num_msgs) 368 { 369 struct otx2_mbox_dev *src_mdev, *dst_mdev; 370 struct mbox_hdr *mbox_hdr; 371 struct mbox_hdr *req_hdr; 372 struct mbox *dst_mbox; 373 int dst_size, err; 374 375 if (dir == MBOX_DIR_PFAF) { 376 /* Set VF's mailbox memory as PF's bounce buffer memory, so 377 * that explicit copying of VF's msgs to PF=>AF mbox region 378 * and AF=>PF responses to VF's mbox region can be avoided. 379 */ 380 src_mdev = &src_mbox->dev[vf]; 381 mbox_hdr = src_mbox->hwbase + 382 src_mbox->rx_start + (vf * MBOX_SIZE); 383 384 dst_mbox = &pf->mbox; 385 dst_size = dst_mbox->mbox.tx_size - 386 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 387 /* Check if msgs fit into destination area and has valid size */ 388 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 389 return -EINVAL; 390 391 dst_mdev = &dst_mbox->mbox.dev[0]; 392 393 mutex_lock(&pf->mbox.lock); 394 dst_mdev->mbase = src_mdev->mbase; 395 dst_mdev->msg_size = mbox_hdr->msg_size; 396 dst_mdev->num_msgs = num_msgs; 397 err = otx2_sync_mbox_msg(dst_mbox); 398 /* Error code -EIO indicate there is a communication failure 399 * to the AF. Rest of the error codes indicate that AF processed 400 * VF messages and set the error codes in response messages 401 * (if any) so simply forward responses to VF. 402 */ 403 if (err == -EIO) { 404 dev_warn(pf->dev, 405 "AF not responding to VF%d messages\n", vf); 406 /* restore PF mbase and exit */ 407 dst_mdev->mbase = pf->mbox.bbuf_base; 408 mutex_unlock(&pf->mbox.lock); 409 return err; 410 } 411 /* At this point, all the VF messages sent to AF are acked 412 * with proper responses and responses are copied to VF 413 * mailbox hence raise interrupt to VF. 414 */ 415 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 416 dst_mbox->mbox.rx_start); 417 req_hdr->num_msgs = num_msgs; 418 419 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 420 pf->mbox.bbuf_base, vf); 421 mutex_unlock(&pf->mbox.lock); 422 } else if (dir == MBOX_DIR_PFVF_UP) { 423 src_mdev = &src_mbox->dev[0]; 424 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 425 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 426 src_mbox->rx_start); 427 req_hdr->num_msgs = num_msgs; 428 429 dst_mbox = &pf->mbox_pfvf[0]; 430 dst_size = dst_mbox->mbox_up.tx_size - 431 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 432 /* Check if msgs fit into destination area */ 433 if (mbox_hdr->msg_size > dst_size) 434 return -EINVAL; 435 436 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 437 dst_mdev->mbase = src_mdev->mbase; 438 dst_mdev->msg_size = mbox_hdr->msg_size; 439 dst_mdev->num_msgs = mbox_hdr->num_msgs; 440 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 441 if (err) { 442 dev_warn(pf->dev, 443 "VF%d is not responding to mailbox\n", vf); 444 return err; 445 } 446 } else if (dir == MBOX_DIR_VFPF_UP) { 447 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 448 src_mbox->rx_start); 449 req_hdr->num_msgs = num_msgs; 450 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 451 &pf->mbox.mbox_up, 452 pf->mbox_pfvf[vf].bbuf_base, 453 0); 454 } 455 456 return 0; 457 } 458 459 static void otx2_pfvf_mbox_handler(struct work_struct *work) 460 { 461 struct mbox_msghdr *msg = NULL; 462 int offset, vf_idx, id, err; 463 struct otx2_mbox_dev *mdev; 464 struct mbox_hdr *req_hdr; 465 struct otx2_mbox *mbox; 466 struct mbox *vf_mbox; 467 struct otx2_nic *pf; 468 469 vf_mbox = container_of(work, struct mbox, mbox_wrk); 470 pf = vf_mbox->pfvf; 471 vf_idx = vf_mbox - pf->mbox_pfvf; 472 473 mbox = &pf->mbox_pfvf[0].mbox; 474 mdev = &mbox->dev[vf_idx]; 475 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 476 477 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 478 479 for (id = 0; id < vf_mbox->num_msgs; id++) { 480 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 481 offset); 482 483 if (msg->sig != OTX2_MBOX_REQ_SIG) 484 goto inval_msg; 485 486 /* Set VF's number in each of the msg */ 487 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 488 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 489 offset = msg->next_msgoff; 490 } 491 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 492 vf_mbox->num_msgs); 493 if (err) 494 goto inval_msg; 495 return; 496 497 inval_msg: 498 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 499 otx2_mbox_msg_send(mbox, vf_idx); 500 } 501 502 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 503 { 504 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 505 struct otx2_nic *pf = vf_mbox->pfvf; 506 struct otx2_mbox_dev *mdev; 507 int offset, id, vf_idx = 0; 508 struct mbox_hdr *rsp_hdr; 509 struct mbox_msghdr *msg; 510 struct otx2_mbox *mbox; 511 512 vf_idx = vf_mbox - pf->mbox_pfvf; 513 mbox = &pf->mbox_pfvf[0].mbox_up; 514 mdev = &mbox->dev[vf_idx]; 515 516 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 517 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 518 519 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 520 msg = mdev->mbase + offset; 521 522 if (msg->id >= MBOX_MSG_MAX) { 523 dev_err(pf->dev, 524 "Mbox msg with unknown ID 0x%x\n", msg->id); 525 goto end; 526 } 527 528 if (msg->sig != OTX2_MBOX_RSP_SIG) { 529 dev_err(pf->dev, 530 "Mbox msg with wrong signature %x, ID 0x%x\n", 531 msg->sig, msg->id); 532 goto end; 533 } 534 535 switch (msg->id) { 536 case MBOX_MSG_CGX_LINK_EVENT: 537 break; 538 default: 539 if (msg->rc) 540 dev_err(pf->dev, 541 "Mbox msg response has err %d, ID 0x%x\n", 542 msg->rc, msg->id); 543 break; 544 } 545 546 end: 547 offset = mbox->rx_start + msg->next_msgoff; 548 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 549 __otx2_mbox_reset(mbox, 0); 550 mdev->msgs_acked++; 551 } 552 } 553 554 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 555 { 556 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 557 int vfs = pf->total_vfs; 558 struct mbox *mbox; 559 u64 intr; 560 561 mbox = pf->mbox_pfvf; 562 /* Handle VF interrupts */ 563 if (vfs > 64) { 564 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 565 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 566 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 567 TYPE_PFVF); 568 vfs -= 64; 569 } 570 571 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 572 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 573 574 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 575 576 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 577 578 return IRQ_HANDLED; 579 } 580 581 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 582 { 583 void __iomem *hwbase; 584 struct mbox *mbox; 585 int err, vf; 586 u64 base; 587 588 if (!numvfs) 589 return -EINVAL; 590 591 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 592 sizeof(struct mbox), GFP_KERNEL); 593 if (!pf->mbox_pfvf) 594 return -ENOMEM; 595 596 pf->mbox_pfvf_wq = alloc_ordered_workqueue("otx2_pfvf_mailbox", 597 WQ_HIGHPRI | WQ_MEM_RECLAIM); 598 if (!pf->mbox_pfvf_wq) 599 return -ENOMEM; 600 601 /* On CN10K platform, PF <-> VF mailbox region follows after 602 * PF <-> AF mailbox region. 603 */ 604 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 605 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 606 MBOX_SIZE; 607 else 608 base = readq((void __iomem *)((u64)pf->reg_base + 609 RVU_PF_VF_BAR4_ADDR)); 610 611 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 612 if (!hwbase) { 613 err = -ENOMEM; 614 goto free_wq; 615 } 616 617 mbox = &pf->mbox_pfvf[0]; 618 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF, numvfs); 620 if (err) 621 goto free_iomem; 622 623 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 624 MBOX_DIR_PFVF_UP, numvfs); 625 if (err) 626 goto free_iomem; 627 628 for (vf = 0; vf < numvfs; vf++) { 629 mbox->pfvf = pf; 630 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 631 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 632 mbox++; 633 } 634 635 return 0; 636 637 free_iomem: 638 if (hwbase) 639 iounmap(hwbase); 640 free_wq: 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 return err; 643 } 644 645 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 646 { 647 struct mbox *mbox = &pf->mbox_pfvf[0]; 648 649 if (!mbox) 650 return; 651 652 if (pf->mbox_pfvf_wq) { 653 destroy_workqueue(pf->mbox_pfvf_wq); 654 pf->mbox_pfvf_wq = NULL; 655 } 656 657 if (mbox->mbox.hwbase) 658 iounmap(mbox->mbox.hwbase); 659 660 otx2_mbox_destroy(&mbox->mbox); 661 } 662 663 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 664 { 665 /* Clear PF <=> VF mailbox IRQ */ 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 669 /* Enable PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 671 if (numvfs > 64) { 672 numvfs -= 64; 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 674 INTR_MASK(numvfs)); 675 } 676 } 677 678 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 679 { 680 int vector; 681 682 /* Disable PF <=> VF mailbox IRQ */ 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 685 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 688 free_irq(vector, pf); 689 690 if (numvfs > 64) { 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 692 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 693 free_irq(vector, pf); 694 } 695 } 696 697 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 698 { 699 struct otx2_hw *hw = &pf->hw; 700 char *irq_name; 701 int err; 702 703 /* Register MBOX0 interrupt handler */ 704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 705 if (pf->pcifunc) 706 snprintf(irq_name, NAME_SIZE, 707 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 708 else 709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 710 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 711 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 712 if (err) { 713 dev_err(pf->dev, 714 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 715 return err; 716 } 717 718 if (numvfs > 64) { 719 /* Register MBOX1 interrupt handler */ 720 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 721 if (pf->pcifunc) 722 snprintf(irq_name, NAME_SIZE, 723 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 724 else 725 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 726 err = request_irq(pci_irq_vector(pf->pdev, 727 RVU_PF_INT_VEC_VFPF_MBOX1), 728 otx2_pfvf_mbox_intr_handler, 729 0, irq_name, pf); 730 if (err) { 731 dev_err(pf->dev, 732 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 733 return err; 734 } 735 } 736 737 otx2_enable_pfvf_mbox_intr(pf, numvfs); 738 739 return 0; 740 } 741 742 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 743 struct mbox_msghdr *msg) 744 { 745 int devid; 746 747 if (msg->id >= MBOX_MSG_MAX) { 748 dev_err(pf->dev, 749 "Mbox msg with unknown ID 0x%x\n", msg->id); 750 return; 751 } 752 753 if (msg->sig != OTX2_MBOX_RSP_SIG) { 754 dev_err(pf->dev, 755 "Mbox msg with wrong signature %x, ID 0x%x\n", 756 msg->sig, msg->id); 757 return; 758 } 759 760 /* message response heading VF */ 761 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 762 if (devid) { 763 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 764 struct delayed_work *dwork; 765 766 switch (msg->id) { 767 case MBOX_MSG_NIX_LF_START_RX: 768 config->intf_down = false; 769 dwork = &config->link_event_work; 770 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 771 break; 772 case MBOX_MSG_NIX_LF_STOP_RX: 773 config->intf_down = true; 774 break; 775 } 776 777 return; 778 } 779 780 switch (msg->id) { 781 case MBOX_MSG_READY: 782 pf->pcifunc = msg->pcifunc; 783 break; 784 case MBOX_MSG_MSIX_OFFSET: 785 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 786 break; 787 case MBOX_MSG_NPA_LF_ALLOC: 788 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 789 break; 790 case MBOX_MSG_NIX_LF_ALLOC: 791 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 792 break; 793 case MBOX_MSG_NIX_BP_ENABLE: 794 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 795 break; 796 case MBOX_MSG_CGX_STATS: 797 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 798 break; 799 case MBOX_MSG_CGX_FEC_STATS: 800 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 801 break; 802 default: 803 if (msg->rc) 804 dev_err(pf->dev, 805 "Mbox msg response has err %d, ID 0x%x\n", 806 msg->rc, msg->id); 807 break; 808 } 809 } 810 811 static void otx2_pfaf_mbox_handler(struct work_struct *work) 812 { 813 struct otx2_mbox_dev *mdev; 814 struct mbox_hdr *rsp_hdr; 815 struct mbox_msghdr *msg; 816 struct otx2_mbox *mbox; 817 struct mbox *af_mbox; 818 struct otx2_nic *pf; 819 int offset, id; 820 821 af_mbox = container_of(work, struct mbox, mbox_wrk); 822 mbox = &af_mbox->mbox; 823 mdev = &mbox->dev[0]; 824 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 825 826 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 827 pf = af_mbox->pfvf; 828 829 for (id = 0; id < af_mbox->num_msgs; id++) { 830 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 831 otx2_process_pfaf_mbox_msg(pf, msg); 832 offset = mbox->rx_start + msg->next_msgoff; 833 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 834 __otx2_mbox_reset(mbox, 0); 835 mdev->msgs_acked++; 836 } 837 838 } 839 840 static void otx2_handle_link_event(struct otx2_nic *pf) 841 { 842 struct cgx_link_user_info *linfo = &pf->linfo; 843 struct net_device *netdev = pf->netdev; 844 845 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 846 linfo->link_up ? "UP" : "DOWN", linfo->speed, 847 linfo->full_duplex ? "Full" : "Half"); 848 if (linfo->link_up) { 849 netif_carrier_on(netdev); 850 netif_tx_start_all_queues(netdev); 851 } else { 852 netif_tx_stop_all_queues(netdev); 853 netif_carrier_off(netdev); 854 } 855 } 856 857 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 858 struct mcs_intr_info *event, 859 struct msg_rsp *rsp) 860 { 861 cn10k_handle_mcs_event(pf, event); 862 863 return 0; 864 } 865 866 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 867 struct cgx_link_info_msg *msg, 868 struct msg_rsp *rsp) 869 { 870 int i; 871 872 /* Copy the link info sent by AF */ 873 pf->linfo = msg->link_info; 874 875 /* notify VFs about link event */ 876 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 877 struct otx2_vf_config *config = &pf->vf_configs[i]; 878 struct delayed_work *dwork = &config->link_event_work; 879 880 if (config->intf_down) 881 continue; 882 883 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 884 } 885 886 /* interface has not been fully configured yet */ 887 if (pf->flags & OTX2_FLAG_INTF_DOWN) 888 return 0; 889 890 otx2_handle_link_event(pf); 891 return 0; 892 } 893 894 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 895 struct mbox_msghdr *req) 896 { 897 /* Check if valid, if not reply with a invalid msg */ 898 if (req->sig != OTX2_MBOX_REQ_SIG) { 899 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 900 return -ENODEV; 901 } 902 903 switch (req->id) { 904 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 905 case _id: { \ 906 struct _rsp_type *rsp; \ 907 int err; \ 908 \ 909 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 910 &pf->mbox.mbox_up, 0, \ 911 sizeof(struct _rsp_type)); \ 912 if (!rsp) \ 913 return -ENOMEM; \ 914 \ 915 rsp->hdr.id = _id; \ 916 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 917 rsp->hdr.pcifunc = 0; \ 918 rsp->hdr.rc = 0; \ 919 \ 920 err = otx2_mbox_up_handler_ ## _fn_name( \ 921 pf, (struct _req_type *)req, rsp); \ 922 return err; \ 923 } 924 MBOX_UP_CGX_MESSAGES 925 MBOX_UP_MCS_MESSAGES 926 #undef M 927 break; 928 default: 929 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 930 return -ENODEV; 931 } 932 return 0; 933 } 934 935 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 936 { 937 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 938 struct otx2_mbox *mbox = &af_mbox->mbox_up; 939 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 940 struct otx2_nic *pf = af_mbox->pfvf; 941 int offset, id, devid = 0; 942 struct mbox_hdr *rsp_hdr; 943 struct mbox_msghdr *msg; 944 945 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 946 947 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 948 949 for (id = 0; id < af_mbox->up_num_msgs; id++) { 950 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 951 952 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 953 /* Skip processing VF's messages */ 954 if (!devid) 955 otx2_process_mbox_msg_up(pf, msg); 956 offset = mbox->rx_start + msg->next_msgoff; 957 } 958 if (devid) { 959 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 960 MBOX_DIR_PFVF_UP, devid - 1, 961 af_mbox->up_num_msgs); 962 return; 963 } 964 965 otx2_mbox_msg_send(mbox, 0); 966 } 967 968 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 969 { 970 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 971 struct mbox *mbox; 972 973 /* Clear the IRQ */ 974 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 975 976 mbox = &pf->mbox; 977 978 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 979 980 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 981 982 return IRQ_HANDLED; 983 } 984 985 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 986 { 987 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 988 989 /* Disable AF => PF mailbox IRQ */ 990 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 991 free_irq(vector, pf); 992 } 993 994 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 995 { 996 struct otx2_hw *hw = &pf->hw; 997 struct msg_req *req; 998 char *irq_name; 999 int err; 1000 1001 /* Register mailbox interrupt handler */ 1002 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1003 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1004 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1005 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1006 if (err) { 1007 dev_err(pf->dev, 1008 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1009 return err; 1010 } 1011 1012 /* Enable mailbox interrupt for msgs coming from AF. 1013 * First clear to avoid spurious interrupts, if any. 1014 */ 1015 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1016 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1017 1018 if (!probe_af) 1019 return 0; 1020 1021 /* Check mailbox communication with AF */ 1022 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1023 if (!req) { 1024 otx2_disable_mbox_intr(pf); 1025 return -ENOMEM; 1026 } 1027 err = otx2_sync_mbox_msg(&pf->mbox); 1028 if (err) { 1029 dev_warn(pf->dev, 1030 "AF not responding to mailbox, deferring probe\n"); 1031 otx2_disable_mbox_intr(pf); 1032 return -EPROBE_DEFER; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1039 { 1040 struct mbox *mbox = &pf->mbox; 1041 1042 if (pf->mbox_wq) { 1043 destroy_workqueue(pf->mbox_wq); 1044 pf->mbox_wq = NULL; 1045 } 1046 1047 if (mbox->mbox.hwbase) 1048 iounmap((void __iomem *)mbox->mbox.hwbase); 1049 1050 otx2_mbox_destroy(&mbox->mbox); 1051 otx2_mbox_destroy(&mbox->mbox_up); 1052 } 1053 1054 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1055 { 1056 struct mbox *mbox = &pf->mbox; 1057 void __iomem *hwbase; 1058 int err; 1059 1060 mbox->pfvf = pf; 1061 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1062 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1063 if (!pf->mbox_wq) 1064 return -ENOMEM; 1065 1066 /* Mailbox is a reserved memory (in RAM) region shared between 1067 * admin function (i.e AF) and this PF, shouldn't be mapped as 1068 * device memory to allow unaligned accesses. 1069 */ 1070 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1071 MBOX_SIZE); 1072 if (!hwbase) { 1073 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1074 err = -ENOMEM; 1075 goto exit; 1076 } 1077 1078 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1079 MBOX_DIR_PFAF, 1); 1080 if (err) 1081 goto exit; 1082 1083 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1084 MBOX_DIR_PFAF_UP, 1); 1085 if (err) 1086 goto exit; 1087 1088 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1089 if (err) 1090 goto exit; 1091 1092 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1093 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1094 mutex_init(&mbox->lock); 1095 1096 return 0; 1097 exit: 1098 otx2_pfaf_mbox_destroy(pf); 1099 return err; 1100 } 1101 1102 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1103 { 1104 struct msg_req *msg; 1105 int err; 1106 1107 mutex_lock(&pf->mbox.lock); 1108 if (enable) 1109 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1110 else 1111 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1112 1113 if (!msg) { 1114 mutex_unlock(&pf->mbox.lock); 1115 return -ENOMEM; 1116 } 1117 1118 err = otx2_sync_mbox_msg(&pf->mbox); 1119 mutex_unlock(&pf->mbox.lock); 1120 return err; 1121 } 1122 1123 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1124 { 1125 struct msg_req *msg; 1126 int err; 1127 1128 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1129 pf->flow_cfg->dmacflt_max_flows)) 1130 netdev_warn(pf->netdev, 1131 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1132 1133 mutex_lock(&pf->mbox.lock); 1134 if (enable) 1135 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1136 else 1137 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1138 1139 if (!msg) { 1140 mutex_unlock(&pf->mbox.lock); 1141 return -ENOMEM; 1142 } 1143 1144 err = otx2_sync_mbox_msg(&pf->mbox); 1145 mutex_unlock(&pf->mbox.lock); 1146 return err; 1147 } 1148 1149 int otx2_set_real_num_queues(struct net_device *netdev, 1150 int tx_queues, int rx_queues) 1151 { 1152 int err; 1153 1154 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1155 if (err) { 1156 netdev_err(netdev, 1157 "Failed to set no of Tx queues: %d\n", tx_queues); 1158 return err; 1159 } 1160 1161 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1162 if (err) 1163 netdev_err(netdev, 1164 "Failed to set no of Rx queues: %d\n", rx_queues); 1165 return err; 1166 } 1167 EXPORT_SYMBOL(otx2_set_real_num_queues); 1168 1169 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1170 "NIX_SQOPERR_OOR", 1171 "NIX_SQOPERR_CTX_FAULT", 1172 "NIX_SQOPERR_CTX_POISON", 1173 "NIX_SQOPERR_DISABLED", 1174 "NIX_SQOPERR_SIZE_ERR", 1175 "NIX_SQOPERR_OFLOW", 1176 "NIX_SQOPERR_SQB_NULL", 1177 "NIX_SQOPERR_SQB_FAULT", 1178 "NIX_SQOPERR_SQE_SZ_ZERO", 1179 }; 1180 1181 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1182 "NIX_MNQERR_SQ_CTX_FAULT", 1183 "NIX_MNQERR_SQ_CTX_POISON", 1184 "NIX_MNQERR_SQB_FAULT", 1185 "NIX_MNQERR_SQB_POISON", 1186 "NIX_MNQERR_TOTAL_ERR", 1187 "NIX_MNQERR_LSO_ERR", 1188 "NIX_MNQERR_CQ_QUERY_ERR", 1189 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1190 "NIX_MNQERR_MAXLEN_ERR", 1191 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1192 }; 1193 1194 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1195 "NIX_SND_STATUS_GOOD", 1196 "NIX_SND_STATUS_SQ_CTX_FAULT", 1197 "NIX_SND_STATUS_SQ_CTX_POISON", 1198 "NIX_SND_STATUS_SQB_FAULT", 1199 "NIX_SND_STATUS_SQB_POISON", 1200 "NIX_SND_STATUS_HDR_ERR", 1201 "NIX_SND_STATUS_EXT_ERR", 1202 "NIX_SND_STATUS_JUMP_FAULT", 1203 "NIX_SND_STATUS_JUMP_POISON", 1204 "NIX_SND_STATUS_CRC_ERR", 1205 "NIX_SND_STATUS_IMM_ERR", 1206 "NIX_SND_STATUS_SG_ERR", 1207 "NIX_SND_STATUS_MEM_ERR", 1208 "NIX_SND_STATUS_INVALID_SUBDC", 1209 "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1210 "NIX_SND_STATUS_DATA_FAULT", 1211 "NIX_SND_STATUS_DATA_POISON", 1212 "NIX_SND_STATUS_NPC_DROP_ACTION", 1213 "NIX_SND_STATUS_LOCK_VIOL", 1214 "NIX_SND_STATUS_NPC_UCAST_CHAN_ERR", 1215 "NIX_SND_STATUS_NPC_MCAST_CHAN_ERR", 1216 "NIX_SND_STATUS_NPC_MCAST_ABORT", 1217 "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1218 "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1219 "NIX_SND_STATUS_SEND_STATS_ERR", 1220 }; 1221 1222 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1223 { 1224 struct otx2_nic *pf = data; 1225 struct otx2_snd_queue *sq; 1226 u64 val, *ptr; 1227 u64 qidx = 0; 1228 1229 /* CQ */ 1230 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1231 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1232 val = otx2_atomic64_add((qidx << 44), ptr); 1233 1234 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1235 (val & NIX_CQERRINT_BITS)); 1236 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1237 continue; 1238 1239 if (val & BIT_ULL(42)) { 1240 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1241 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1242 } else { 1243 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1244 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1245 qidx); 1246 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1247 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1248 qidx); 1249 } 1250 1251 schedule_work(&pf->reset_task); 1252 } 1253 1254 /* SQ */ 1255 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1256 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1257 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1258 1259 sq = &pf->qset.sq[qidx]; 1260 if (!sq->sqb_ptrs) 1261 continue; 1262 1263 /* Below debug registers captures first errors corresponding to 1264 * those registers. We don't have to check against SQ qid as 1265 * these are fatal errors. 1266 */ 1267 1268 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1269 val = otx2_atomic64_add((qidx << 44), ptr); 1270 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1271 (val & NIX_SQINT_BITS)); 1272 1273 if (val & BIT_ULL(42)) { 1274 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1275 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1276 goto done; 1277 } 1278 1279 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1280 if (!(sq_op_err_dbg & BIT(44))) 1281 goto chk_mnq_err_dbg; 1282 1283 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1284 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n", 1285 qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]); 1286 1287 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1288 1289 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1290 goto chk_mnq_err_dbg; 1291 1292 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1293 * TODO: But we are in irq context. How to call mbox functions which does sleep 1294 */ 1295 1296 chk_mnq_err_dbg: 1297 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1298 if (!(mnq_err_dbg & BIT(44))) 1299 goto chk_snd_err_dbg; 1300 1301 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1302 netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n", 1303 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]); 1304 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1305 1306 chk_snd_err_dbg: 1307 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1308 if (snd_err_dbg & BIT(44)) { 1309 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1310 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n", 1311 qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]); 1312 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1313 } 1314 1315 done: 1316 /* Print values and reset */ 1317 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1318 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1319 qidx); 1320 1321 schedule_work(&pf->reset_task); 1322 } 1323 1324 return IRQ_HANDLED; 1325 } 1326 1327 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1328 { 1329 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1330 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1331 int qidx = cq_poll->cint_idx; 1332 1333 /* Disable interrupts. 1334 * 1335 * Completion interrupts behave in a level-triggered interrupt 1336 * fashion, and hence have to be cleared only after it is serviced. 1337 */ 1338 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1339 1340 /* Schedule NAPI */ 1341 pf->napi_events++; 1342 napi_schedule_irqoff(&cq_poll->napi); 1343 1344 return IRQ_HANDLED; 1345 } 1346 1347 static void otx2_disable_napi(struct otx2_nic *pf) 1348 { 1349 struct otx2_qset *qset = &pf->qset; 1350 struct otx2_cq_poll *cq_poll; 1351 int qidx; 1352 1353 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1354 cq_poll = &qset->napi[qidx]; 1355 cancel_work_sync(&cq_poll->dim.work); 1356 napi_disable(&cq_poll->napi); 1357 netif_napi_del(&cq_poll->napi); 1358 } 1359 } 1360 1361 static void otx2_free_cq_res(struct otx2_nic *pf) 1362 { 1363 struct otx2_qset *qset = &pf->qset; 1364 struct otx2_cq_queue *cq; 1365 int qidx; 1366 1367 /* Disable CQs */ 1368 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1369 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1370 cq = &qset->cq[qidx]; 1371 qmem_free(pf->dev, cq->cqe); 1372 } 1373 } 1374 1375 static void otx2_free_sq_res(struct otx2_nic *pf) 1376 { 1377 struct otx2_qset *qset = &pf->qset; 1378 struct otx2_snd_queue *sq; 1379 int qidx; 1380 1381 /* Disable SQs */ 1382 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1383 /* Free SQB pointers */ 1384 otx2_sq_free_sqbs(pf); 1385 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1386 sq = &qset->sq[qidx]; 1387 /* Skip freeing Qos queues if they are not initialized */ 1388 if (!sq->sqe) 1389 continue; 1390 qmem_free(pf->dev, sq->sqe); 1391 qmem_free(pf->dev, sq->tso_hdrs); 1392 kfree(sq->sg); 1393 kfree(sq->sqb_ptrs); 1394 } 1395 } 1396 1397 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1398 { 1399 int frame_size; 1400 int total_size; 1401 int rbuf_size; 1402 1403 if (pf->hw.rbuf_len) 1404 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1405 1406 /* The data transferred by NIX to memory consists of actual packet 1407 * plus additional data which has timestamp and/or EDSA/HIGIG2 1408 * headers if interface is configured in corresponding modes. 1409 * NIX transfers entire data using 6 segments/buffers and writes 1410 * a CQE_RX descriptor with those segment addresses. First segment 1411 * has additional data prepended to packet. Also software omits a 1412 * headroom of 128 bytes in each segment. Hence the total size of 1413 * memory needed to receive a packet with 'mtu' is: 1414 * frame size = mtu + additional data; 1415 * memory = frame_size + headroom * 6; 1416 * each receive buffer size = memory / 6; 1417 */ 1418 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1419 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1420 rbuf_size = total_size / 6; 1421 1422 return ALIGN(rbuf_size, 2048); 1423 } 1424 1425 static int otx2_init_hw_resources(struct otx2_nic *pf) 1426 { 1427 struct nix_lf_free_req *free_req; 1428 struct mbox *mbox = &pf->mbox; 1429 struct otx2_hw *hw = &pf->hw; 1430 struct msg_req *req; 1431 int err = 0, lvl; 1432 1433 /* Set required NPA LF's pool counts 1434 * Auras and Pools are used in a 1:1 mapping, 1435 * so, aura count = pool count. 1436 */ 1437 hw->rqpool_cnt = hw->rx_queues; 1438 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1439 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1440 1441 /* Maximum hardware supported transmit length */ 1442 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1443 1444 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1445 1446 mutex_lock(&mbox->lock); 1447 /* NPA init */ 1448 err = otx2_config_npa(pf); 1449 if (err) 1450 goto exit; 1451 1452 /* NIX init */ 1453 err = otx2_config_nix(pf); 1454 if (err) 1455 goto err_free_npa_lf; 1456 1457 /* Enable backpressure for CGX mapped PF/VFs */ 1458 if (!is_otx2_lbkvf(pf->pdev)) 1459 otx2_nix_config_bp(pf, true); 1460 1461 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1462 err = otx2_rq_aura_pool_init(pf); 1463 if (err) { 1464 mutex_unlock(&mbox->lock); 1465 goto err_free_nix_lf; 1466 } 1467 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1468 err = otx2_sq_aura_pool_init(pf); 1469 if (err) { 1470 mutex_unlock(&mbox->lock); 1471 goto err_free_rq_ptrs; 1472 } 1473 1474 err = otx2_txsch_alloc(pf); 1475 if (err) { 1476 mutex_unlock(&mbox->lock); 1477 goto err_free_sq_ptrs; 1478 } 1479 1480 #ifdef CONFIG_DCB 1481 if (pf->pfc_en) { 1482 err = otx2_pfc_txschq_alloc(pf); 1483 if (err) { 1484 mutex_unlock(&mbox->lock); 1485 goto err_free_sq_ptrs; 1486 } 1487 } 1488 #endif 1489 1490 err = otx2_config_nix_queues(pf); 1491 if (err) { 1492 mutex_unlock(&mbox->lock); 1493 goto err_free_txsch; 1494 } 1495 1496 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1497 err = otx2_txschq_config(pf, lvl, 0, false); 1498 if (err) { 1499 mutex_unlock(&mbox->lock); 1500 goto err_free_nix_queues; 1501 } 1502 } 1503 1504 #ifdef CONFIG_DCB 1505 if (pf->pfc_en) { 1506 err = otx2_pfc_txschq_config(pf); 1507 if (err) { 1508 mutex_unlock(&mbox->lock); 1509 goto err_free_nix_queues; 1510 } 1511 } 1512 #endif 1513 1514 mutex_unlock(&mbox->lock); 1515 return err; 1516 1517 err_free_nix_queues: 1518 otx2_free_sq_res(pf); 1519 otx2_free_cq_res(pf); 1520 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1521 err_free_txsch: 1522 otx2_txschq_stop(pf); 1523 err_free_sq_ptrs: 1524 otx2_sq_free_sqbs(pf); 1525 err_free_rq_ptrs: 1526 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1527 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1528 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1529 otx2_aura_pool_free(pf); 1530 err_free_nix_lf: 1531 mutex_lock(&mbox->lock); 1532 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1533 if (free_req) { 1534 free_req->flags = NIX_LF_DISABLE_FLOWS; 1535 if (otx2_sync_mbox_msg(mbox)) 1536 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1537 } 1538 err_free_npa_lf: 1539 /* Reset NPA LF */ 1540 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1541 if (req) { 1542 if (otx2_sync_mbox_msg(mbox)) 1543 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1544 } 1545 exit: 1546 mutex_unlock(&mbox->lock); 1547 return err; 1548 } 1549 1550 static void otx2_free_hw_resources(struct otx2_nic *pf) 1551 { 1552 struct otx2_qset *qset = &pf->qset; 1553 struct nix_lf_free_req *free_req; 1554 struct mbox *mbox = &pf->mbox; 1555 struct otx2_cq_queue *cq; 1556 struct otx2_pool *pool; 1557 struct msg_req *req; 1558 int pool_id; 1559 int qidx; 1560 1561 /* Ensure all SQE are processed */ 1562 otx2_sqb_flush(pf); 1563 1564 /* Stop transmission */ 1565 otx2_txschq_stop(pf); 1566 1567 #ifdef CONFIG_DCB 1568 if (pf->pfc_en) 1569 otx2_pfc_txschq_stop(pf); 1570 #endif 1571 1572 otx2_clean_qos_queues(pf); 1573 1574 mutex_lock(&mbox->lock); 1575 /* Disable backpressure */ 1576 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1577 otx2_nix_config_bp(pf, false); 1578 mutex_unlock(&mbox->lock); 1579 1580 /* Disable RQs */ 1581 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1582 1583 /*Dequeue all CQEs */ 1584 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1585 cq = &qset->cq[qidx]; 1586 if (cq->cq_type == CQ_RX) 1587 otx2_cleanup_rx_cqes(pf, cq, qidx); 1588 else 1589 otx2_cleanup_tx_cqes(pf, cq); 1590 } 1591 1592 otx2_free_sq_res(pf); 1593 1594 /* Free RQ buffer pointers*/ 1595 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1596 1597 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1598 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1599 pool = &pf->qset.pool[pool_id]; 1600 page_pool_destroy(pool->page_pool); 1601 pool->page_pool = NULL; 1602 } 1603 1604 otx2_free_cq_res(pf); 1605 1606 /* Free all ingress bandwidth profiles allocated */ 1607 cn10k_free_all_ipolicers(pf); 1608 1609 mutex_lock(&mbox->lock); 1610 /* Reset NIX LF */ 1611 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1612 if (free_req) { 1613 free_req->flags = NIX_LF_DISABLE_FLOWS; 1614 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1615 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1616 if (otx2_sync_mbox_msg(mbox)) 1617 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1618 } 1619 mutex_unlock(&mbox->lock); 1620 1621 /* Disable NPA Pool and Aura hw context */ 1622 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1623 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1624 otx2_aura_pool_free(pf); 1625 1626 mutex_lock(&mbox->lock); 1627 /* Reset NPA LF */ 1628 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1629 if (req) { 1630 if (otx2_sync_mbox_msg(mbox)) 1631 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1632 } 1633 mutex_unlock(&mbox->lock); 1634 } 1635 1636 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1637 { 1638 struct net_device *netdev = pf->netdev; 1639 struct nix_rx_mode *req; 1640 bool promisc = false; 1641 1642 if (!(netdev->flags & IFF_UP)) 1643 return; 1644 1645 if ((netdev->flags & IFF_PROMISC) || 1646 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1647 promisc = true; 1648 } 1649 1650 /* Write unicast address to mcam entries or del from mcam */ 1651 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1652 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1653 1654 mutex_lock(&pf->mbox.lock); 1655 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1656 if (!req) { 1657 mutex_unlock(&pf->mbox.lock); 1658 return; 1659 } 1660 1661 req->mode = NIX_RX_MODE_UCAST; 1662 1663 if (promisc) 1664 req->mode |= NIX_RX_MODE_PROMISC; 1665 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1666 req->mode |= NIX_RX_MODE_ALLMULTI; 1667 1668 req->mode |= NIX_RX_MODE_USE_MCE; 1669 1670 otx2_sync_mbox_msg(&pf->mbox); 1671 mutex_unlock(&pf->mbox.lock); 1672 } 1673 1674 static void otx2_dim_work(struct work_struct *w) 1675 { 1676 struct dim_cq_moder cur_moder; 1677 struct otx2_cq_poll *cq_poll; 1678 struct otx2_nic *pfvf; 1679 struct dim *dim; 1680 1681 dim = container_of(w, struct dim, work); 1682 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1683 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1684 pfvf = (struct otx2_nic *)cq_poll->dev; 1685 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1686 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1687 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1688 NAPI_POLL_WEIGHT : cur_moder.pkts; 1689 dim->state = DIM_START_MEASURE; 1690 } 1691 1692 int otx2_open(struct net_device *netdev) 1693 { 1694 struct otx2_nic *pf = netdev_priv(netdev); 1695 struct otx2_cq_poll *cq_poll = NULL; 1696 struct otx2_qset *qset = &pf->qset; 1697 int err = 0, qidx, vec; 1698 char *irq_name; 1699 1700 netif_carrier_off(netdev); 1701 1702 /* RQ and SQs are mapped to different CQs, 1703 * so find out max CQ IRQs (i.e CINTs) needed. 1704 */ 1705 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1706 pf->hw.tc_tx_queues); 1707 1708 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1709 1710 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1711 if (!qset->napi) 1712 return -ENOMEM; 1713 1714 /* CQ size of RQ */ 1715 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1716 /* CQ size of SQ */ 1717 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1718 1719 err = -ENOMEM; 1720 qset->cq = kcalloc(pf->qset.cq_cnt, 1721 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1722 if (!qset->cq) 1723 goto err_free_mem; 1724 1725 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1726 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1727 if (!qset->sq) 1728 goto err_free_mem; 1729 1730 qset->rq = kcalloc(pf->hw.rx_queues, 1731 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1732 if (!qset->rq) 1733 goto err_free_mem; 1734 1735 err = otx2_init_hw_resources(pf); 1736 if (err) 1737 goto err_free_mem; 1738 1739 /* Register NAPI handler */ 1740 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1741 cq_poll = &qset->napi[qidx]; 1742 cq_poll->cint_idx = qidx; 1743 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1744 * 'cq_ids[0]' points to RQ's CQ and 1745 * 'cq_ids[1]' points to SQ's CQ and 1746 * 'cq_ids[2]' points to XDP's CQ and 1747 */ 1748 cq_poll->cq_ids[CQ_RX] = 1749 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1750 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1751 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1752 if (pf->xdp_prog) 1753 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1754 (qidx + pf->hw.rx_queues + 1755 pf->hw.tx_queues) : 1756 CINT_INVALID_CQ; 1757 else 1758 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1759 1760 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1761 (qidx + pf->hw.rx_queues + 1762 pf->hw.non_qos_queues) : 1763 CINT_INVALID_CQ; 1764 1765 cq_poll->dev = (void *)pf; 1766 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1767 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1768 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1769 napi_enable(&cq_poll->napi); 1770 } 1771 1772 /* Set maximum frame size allowed in HW */ 1773 err = otx2_hw_set_mtu(pf, netdev->mtu); 1774 if (err) 1775 goto err_disable_napi; 1776 1777 /* Setup segmentation algorithms, if failed, clear offload capability */ 1778 otx2_setup_segmentation(pf); 1779 1780 /* Initialize RSS */ 1781 err = otx2_rss_init(pf); 1782 if (err) 1783 goto err_disable_napi; 1784 1785 /* Register Queue IRQ handlers */ 1786 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1787 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1788 1789 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1790 1791 err = request_irq(pci_irq_vector(pf->pdev, vec), 1792 otx2_q_intr_handler, 0, irq_name, pf); 1793 if (err) { 1794 dev_err(pf->dev, 1795 "RVUPF%d: IRQ registration failed for QERR\n", 1796 rvu_get_pf(pf->pcifunc)); 1797 goto err_disable_napi; 1798 } 1799 1800 /* Enable QINT IRQ */ 1801 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1802 1803 /* Register CQ IRQ handlers */ 1804 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1805 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1806 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1807 1808 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1809 qidx); 1810 1811 err = request_irq(pci_irq_vector(pf->pdev, vec), 1812 otx2_cq_intr_handler, 0, irq_name, 1813 &qset->napi[qidx]); 1814 if (err) { 1815 dev_err(pf->dev, 1816 "RVUPF%d: IRQ registration failed for CQ%d\n", 1817 rvu_get_pf(pf->pcifunc), qidx); 1818 goto err_free_cints; 1819 } 1820 vec++; 1821 1822 otx2_config_irq_coalescing(pf, qidx); 1823 1824 /* Enable CQ IRQ */ 1825 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1826 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1827 } 1828 1829 otx2_set_cints_affinity(pf); 1830 1831 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1832 otx2_enable_rxvlan(pf, true); 1833 1834 /* When reinitializing enable time stamping if it is enabled before */ 1835 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1836 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1837 otx2_config_hw_tx_tstamp(pf, true); 1838 } 1839 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1840 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1841 otx2_config_hw_rx_tstamp(pf, true); 1842 } 1843 1844 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1845 /* 'intf_down' may be checked on any cpu */ 1846 smp_wmb(); 1847 1848 /* Enable QoS configuration before starting tx queues */ 1849 otx2_qos_config_txschq(pf); 1850 1851 /* we have already received link status notification */ 1852 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1853 otx2_handle_link_event(pf); 1854 1855 /* Install DMAC Filters */ 1856 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1857 otx2_dmacflt_reinstall_flows(pf); 1858 1859 err = otx2_rxtx_enable(pf, true); 1860 /* If a mbox communication error happens at this point then interface 1861 * will end up in a state such that it is in down state but hardware 1862 * mcam entries are enabled to receive the packets. Hence disable the 1863 * packet I/O. 1864 */ 1865 if (err == EIO) 1866 goto err_disable_rxtx; 1867 else if (err) 1868 goto err_tx_stop_queues; 1869 1870 otx2_do_set_rx_mode(pf); 1871 1872 return 0; 1873 1874 err_disable_rxtx: 1875 otx2_rxtx_enable(pf, false); 1876 err_tx_stop_queues: 1877 netif_tx_stop_all_queues(netdev); 1878 netif_carrier_off(netdev); 1879 pf->flags |= OTX2_FLAG_INTF_DOWN; 1880 err_free_cints: 1881 otx2_free_cints(pf, qidx); 1882 vec = pci_irq_vector(pf->pdev, 1883 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1884 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1885 free_irq(vec, pf); 1886 err_disable_napi: 1887 otx2_disable_napi(pf); 1888 otx2_free_hw_resources(pf); 1889 err_free_mem: 1890 kfree(qset->sq); 1891 kfree(qset->cq); 1892 kfree(qset->rq); 1893 kfree(qset->napi); 1894 return err; 1895 } 1896 EXPORT_SYMBOL(otx2_open); 1897 1898 int otx2_stop(struct net_device *netdev) 1899 { 1900 struct otx2_nic *pf = netdev_priv(netdev); 1901 struct otx2_cq_poll *cq_poll = NULL; 1902 struct otx2_qset *qset = &pf->qset; 1903 struct otx2_rss_info *rss; 1904 int qidx, vec, wrk; 1905 1906 /* If the DOWN flag is set resources are already freed */ 1907 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1908 return 0; 1909 1910 netif_carrier_off(netdev); 1911 netif_tx_stop_all_queues(netdev); 1912 1913 pf->flags |= OTX2_FLAG_INTF_DOWN; 1914 /* 'intf_down' may be checked on any cpu */ 1915 smp_wmb(); 1916 1917 /* First stop packet Rx/Tx */ 1918 otx2_rxtx_enable(pf, false); 1919 1920 /* Clear RSS enable flag */ 1921 rss = &pf->hw.rss_info; 1922 rss->enable = false; 1923 1924 /* Cleanup Queue IRQ */ 1925 vec = pci_irq_vector(pf->pdev, 1926 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1927 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1928 free_irq(vec, pf); 1929 1930 /* Cleanup CQ NAPI and IRQ */ 1931 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1932 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1933 /* Disable interrupt */ 1934 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1935 1936 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1937 1938 cq_poll = &qset->napi[qidx]; 1939 napi_synchronize(&cq_poll->napi); 1940 vec++; 1941 } 1942 1943 netif_tx_disable(netdev); 1944 1945 otx2_free_hw_resources(pf); 1946 otx2_free_cints(pf, pf->hw.cint_cnt); 1947 otx2_disable_napi(pf); 1948 1949 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1950 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1951 1952 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1953 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1954 devm_kfree(pf->dev, pf->refill_wrk); 1955 1956 kfree(qset->sq); 1957 kfree(qset->cq); 1958 kfree(qset->rq); 1959 kfree(qset->napi); 1960 /* Do not clear RQ/SQ ringsize settings */ 1961 memset_startat(qset, 0, sqe_cnt); 1962 return 0; 1963 } 1964 EXPORT_SYMBOL(otx2_stop); 1965 1966 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1967 { 1968 struct otx2_nic *pf = netdev_priv(netdev); 1969 int qidx = skb_get_queue_mapping(skb); 1970 struct otx2_snd_queue *sq; 1971 struct netdev_queue *txq; 1972 int sq_idx; 1973 1974 /* XDP SQs are not mapped with TXQs 1975 * advance qid to derive correct sq mapped with QOS 1976 */ 1977 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 1978 1979 /* Check for minimum and maximum packet length */ 1980 if (skb->len <= ETH_HLEN || 1981 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1982 dev_kfree_skb(skb); 1983 return NETDEV_TX_OK; 1984 } 1985 1986 sq = &pf->qset.sq[sq_idx]; 1987 txq = netdev_get_tx_queue(netdev, qidx); 1988 1989 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1990 netif_tx_stop_queue(txq); 1991 1992 /* Check again, incase SQBs got freed up */ 1993 smp_mb(); 1994 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1995 > sq->sqe_thresh) 1996 netif_tx_wake_queue(txq); 1997 1998 return NETDEV_TX_BUSY; 1999 } 2000 2001 return NETDEV_TX_OK; 2002 } 2003 2004 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2005 u16 htb_maj_id) 2006 { 2007 u16 classid; 2008 2009 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2010 classid = TC_H_MIN(skb->priority); 2011 else 2012 classid = READ_ONCE(pf->qos.defcls); 2013 2014 if (!classid) 2015 return 0; 2016 2017 return otx2_get_txq_by_classid(pf, classid); 2018 } 2019 2020 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2021 struct net_device *sb_dev) 2022 { 2023 struct otx2_nic *pf = netdev_priv(netdev); 2024 bool qos_enabled; 2025 #ifdef CONFIG_DCB 2026 u8 vlan_prio; 2027 #endif 2028 int txq; 2029 2030 qos_enabled = (netdev->real_num_tx_queues > pf->hw.tx_queues) ? true : false; 2031 if (unlikely(qos_enabled)) { 2032 /* This smp_load_acquire() pairs with smp_store_release() in 2033 * otx2_qos_root_add() called from htb offload root creation 2034 */ 2035 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2036 2037 if (unlikely(htb_maj_id)) { 2038 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2039 if (txq > 0) 2040 return txq; 2041 goto process_pfc; 2042 } 2043 } 2044 2045 process_pfc: 2046 #ifdef CONFIG_DCB 2047 if (!skb_vlan_tag_present(skb)) 2048 goto pick_tx; 2049 2050 vlan_prio = skb->vlan_tci >> 13; 2051 if ((vlan_prio > pf->hw.tx_queues - 1) || 2052 !pf->pfc_alloc_status[vlan_prio]) 2053 goto pick_tx; 2054 2055 return vlan_prio; 2056 2057 pick_tx: 2058 #endif 2059 txq = netdev_pick_tx(netdev, skb, NULL); 2060 if (unlikely(qos_enabled)) 2061 return txq % pf->hw.tx_queues; 2062 2063 return txq; 2064 } 2065 EXPORT_SYMBOL(otx2_select_queue); 2066 2067 static netdev_features_t otx2_fix_features(struct net_device *dev, 2068 netdev_features_t features) 2069 { 2070 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2071 features |= NETIF_F_HW_VLAN_STAG_RX; 2072 else 2073 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2074 2075 return features; 2076 } 2077 2078 static void otx2_set_rx_mode(struct net_device *netdev) 2079 { 2080 struct otx2_nic *pf = netdev_priv(netdev); 2081 2082 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2083 } 2084 2085 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2086 { 2087 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2088 2089 otx2_do_set_rx_mode(pf); 2090 } 2091 2092 static int otx2_set_features(struct net_device *netdev, 2093 netdev_features_t features) 2094 { 2095 netdev_features_t changed = features ^ netdev->features; 2096 struct otx2_nic *pf = netdev_priv(netdev); 2097 2098 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2099 return otx2_cgx_config_loopback(pf, 2100 features & NETIF_F_LOOPBACK); 2101 2102 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2103 return otx2_enable_rxvlan(pf, 2104 features & NETIF_F_HW_VLAN_CTAG_RX); 2105 2106 return otx2_handle_ntuple_tc_features(netdev, features); 2107 } 2108 2109 static void otx2_reset_task(struct work_struct *work) 2110 { 2111 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2112 2113 if (!netif_running(pf->netdev)) 2114 return; 2115 2116 rtnl_lock(); 2117 otx2_stop(pf->netdev); 2118 pf->reset_count++; 2119 otx2_open(pf->netdev); 2120 netif_trans_update(pf->netdev); 2121 rtnl_unlock(); 2122 } 2123 2124 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2125 { 2126 struct msg_req *req; 2127 int err; 2128 2129 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2130 return 0; 2131 2132 mutex_lock(&pfvf->mbox.lock); 2133 if (enable) 2134 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2135 else 2136 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2137 if (!req) { 2138 mutex_unlock(&pfvf->mbox.lock); 2139 return -ENOMEM; 2140 } 2141 2142 err = otx2_sync_mbox_msg(&pfvf->mbox); 2143 if (err) { 2144 mutex_unlock(&pfvf->mbox.lock); 2145 return err; 2146 } 2147 2148 mutex_unlock(&pfvf->mbox.lock); 2149 if (enable) 2150 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2151 else 2152 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2153 return 0; 2154 } 2155 2156 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2157 { 2158 struct msg_req *req; 2159 int err; 2160 2161 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2162 return 0; 2163 2164 mutex_lock(&pfvf->mbox.lock); 2165 if (enable) 2166 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2167 else 2168 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2169 if (!req) { 2170 mutex_unlock(&pfvf->mbox.lock); 2171 return -ENOMEM; 2172 } 2173 2174 err = otx2_sync_mbox_msg(&pfvf->mbox); 2175 if (err) { 2176 mutex_unlock(&pfvf->mbox.lock); 2177 return err; 2178 } 2179 2180 mutex_unlock(&pfvf->mbox.lock); 2181 if (enable) 2182 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2183 else 2184 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2185 return 0; 2186 } 2187 2188 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2189 { 2190 struct otx2_nic *pfvf = netdev_priv(netdev); 2191 struct hwtstamp_config config; 2192 2193 if (!pfvf->ptp) 2194 return -ENODEV; 2195 2196 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2197 return -EFAULT; 2198 2199 switch (config.tx_type) { 2200 case HWTSTAMP_TX_OFF: 2201 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2202 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2203 2204 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2205 otx2_config_hw_tx_tstamp(pfvf, false); 2206 break; 2207 case HWTSTAMP_TX_ONESTEP_SYNC: 2208 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2209 return -ERANGE; 2210 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2211 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2212 msecs_to_jiffies(500)); 2213 fallthrough; 2214 case HWTSTAMP_TX_ON: 2215 otx2_config_hw_tx_tstamp(pfvf, true); 2216 break; 2217 default: 2218 return -ERANGE; 2219 } 2220 2221 switch (config.rx_filter) { 2222 case HWTSTAMP_FILTER_NONE: 2223 otx2_config_hw_rx_tstamp(pfvf, false); 2224 break; 2225 case HWTSTAMP_FILTER_ALL: 2226 case HWTSTAMP_FILTER_SOME: 2227 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2228 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2229 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2230 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2231 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2232 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2233 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2234 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2235 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2236 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2237 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2238 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2239 otx2_config_hw_rx_tstamp(pfvf, true); 2240 config.rx_filter = HWTSTAMP_FILTER_ALL; 2241 break; 2242 default: 2243 return -ERANGE; 2244 } 2245 2246 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2247 2248 return copy_to_user(ifr->ifr_data, &config, 2249 sizeof(config)) ? -EFAULT : 0; 2250 } 2251 EXPORT_SYMBOL(otx2_config_hwtstamp); 2252 2253 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2254 { 2255 struct otx2_nic *pfvf = netdev_priv(netdev); 2256 struct hwtstamp_config *cfg = &pfvf->tstamp; 2257 2258 switch (cmd) { 2259 case SIOCSHWTSTAMP: 2260 return otx2_config_hwtstamp(netdev, req); 2261 case SIOCGHWTSTAMP: 2262 return copy_to_user(req->ifr_data, cfg, 2263 sizeof(*cfg)) ? -EFAULT : 0; 2264 default: 2265 return -EOPNOTSUPP; 2266 } 2267 } 2268 EXPORT_SYMBOL(otx2_ioctl); 2269 2270 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2271 { 2272 struct npc_install_flow_req *req; 2273 int err; 2274 2275 mutex_lock(&pf->mbox.lock); 2276 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2277 if (!req) { 2278 err = -ENOMEM; 2279 goto out; 2280 } 2281 2282 ether_addr_copy(req->packet.dmac, mac); 2283 eth_broadcast_addr((u8 *)&req->mask.dmac); 2284 req->features = BIT_ULL(NPC_DMAC); 2285 req->channel = pf->hw.rx_chan_base; 2286 req->intf = NIX_INTF_RX; 2287 req->default_rule = 1; 2288 req->append = 1; 2289 req->vf = vf + 1; 2290 req->op = NIX_RX_ACTION_DEFAULT; 2291 2292 err = otx2_sync_mbox_msg(&pf->mbox); 2293 out: 2294 mutex_unlock(&pf->mbox.lock); 2295 return err; 2296 } 2297 2298 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2299 { 2300 struct otx2_nic *pf = netdev_priv(netdev); 2301 struct pci_dev *pdev = pf->pdev; 2302 struct otx2_vf_config *config; 2303 int ret; 2304 2305 if (!netif_running(netdev)) 2306 return -EAGAIN; 2307 2308 if (vf >= pf->total_vfs) 2309 return -EINVAL; 2310 2311 if (!is_valid_ether_addr(mac)) 2312 return -EINVAL; 2313 2314 config = &pf->vf_configs[vf]; 2315 ether_addr_copy(config->mac, mac); 2316 2317 ret = otx2_do_set_vf_mac(pf, vf, mac); 2318 if (ret == 0) 2319 dev_info(&pdev->dev, 2320 "Load/Reload VF driver\n"); 2321 2322 return ret; 2323 } 2324 2325 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2326 __be16 proto) 2327 { 2328 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2329 struct nix_vtag_config_rsp *vtag_rsp; 2330 struct npc_delete_flow_req *del_req; 2331 struct nix_vtag_config *vtag_req; 2332 struct npc_install_flow_req *req; 2333 struct otx2_vf_config *config; 2334 int err = 0; 2335 u32 idx; 2336 2337 config = &pf->vf_configs[vf]; 2338 2339 if (!vlan && !config->vlan) 2340 goto out; 2341 2342 mutex_lock(&pf->mbox.lock); 2343 2344 /* free old tx vtag entry */ 2345 if (config->vlan) { 2346 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2347 if (!vtag_req) { 2348 err = -ENOMEM; 2349 goto out; 2350 } 2351 vtag_req->cfg_type = 0; 2352 vtag_req->tx.free_vtag0 = 1; 2353 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2354 2355 err = otx2_sync_mbox_msg(&pf->mbox); 2356 if (err) 2357 goto out; 2358 } 2359 2360 if (!vlan && config->vlan) { 2361 /* rx */ 2362 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2363 if (!del_req) { 2364 err = -ENOMEM; 2365 goto out; 2366 } 2367 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2368 del_req->entry = 2369 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2370 err = otx2_sync_mbox_msg(&pf->mbox); 2371 if (err) 2372 goto out; 2373 2374 /* tx */ 2375 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2376 if (!del_req) { 2377 err = -ENOMEM; 2378 goto out; 2379 } 2380 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2381 del_req->entry = 2382 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2383 err = otx2_sync_mbox_msg(&pf->mbox); 2384 2385 goto out; 2386 } 2387 2388 /* rx */ 2389 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2390 if (!req) { 2391 err = -ENOMEM; 2392 goto out; 2393 } 2394 2395 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2396 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2397 req->packet.vlan_tci = htons(vlan); 2398 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2399 /* af fills the destination mac addr */ 2400 eth_broadcast_addr((u8 *)&req->mask.dmac); 2401 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2402 req->channel = pf->hw.rx_chan_base; 2403 req->intf = NIX_INTF_RX; 2404 req->vf = vf + 1; 2405 req->op = NIX_RX_ACTION_DEFAULT; 2406 req->vtag0_valid = true; 2407 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2408 req->set_cntr = 1; 2409 2410 err = otx2_sync_mbox_msg(&pf->mbox); 2411 if (err) 2412 goto out; 2413 2414 /* tx */ 2415 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2416 if (!vtag_req) { 2417 err = -ENOMEM; 2418 goto out; 2419 } 2420 2421 /* configure tx vtag params */ 2422 vtag_req->vtag_size = VTAGSIZE_T4; 2423 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2424 vtag_req->tx.cfg_vtag0 = 1; 2425 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2426 2427 err = otx2_sync_mbox_msg(&pf->mbox); 2428 if (err) 2429 goto out; 2430 2431 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2432 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2433 if (IS_ERR(vtag_rsp)) { 2434 err = PTR_ERR(vtag_rsp); 2435 goto out; 2436 } 2437 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2438 2439 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2440 if (!req) { 2441 err = -ENOMEM; 2442 goto out; 2443 } 2444 2445 eth_zero_addr((u8 *)&req->mask.dmac); 2446 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2447 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2448 req->features = BIT_ULL(NPC_DMAC); 2449 req->channel = pf->hw.tx_chan_base; 2450 req->intf = NIX_INTF_TX; 2451 req->vf = vf + 1; 2452 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2453 req->vtag0_def = vtag_rsp->vtag0_idx; 2454 req->vtag0_op = VTAG_INSERT; 2455 req->set_cntr = 1; 2456 2457 err = otx2_sync_mbox_msg(&pf->mbox); 2458 out: 2459 config->vlan = vlan; 2460 mutex_unlock(&pf->mbox.lock); 2461 return err; 2462 } 2463 2464 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2465 __be16 proto) 2466 { 2467 struct otx2_nic *pf = netdev_priv(netdev); 2468 struct pci_dev *pdev = pf->pdev; 2469 2470 if (!netif_running(netdev)) 2471 return -EAGAIN; 2472 2473 if (vf >= pci_num_vf(pdev)) 2474 return -EINVAL; 2475 2476 /* qos is currently unsupported */ 2477 if (vlan >= VLAN_N_VID || qos) 2478 return -EINVAL; 2479 2480 if (proto != htons(ETH_P_8021Q)) 2481 return -EPROTONOSUPPORT; 2482 2483 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2484 return -EOPNOTSUPP; 2485 2486 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2487 } 2488 2489 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2490 struct ifla_vf_info *ivi) 2491 { 2492 struct otx2_nic *pf = netdev_priv(netdev); 2493 struct pci_dev *pdev = pf->pdev; 2494 struct otx2_vf_config *config; 2495 2496 if (!netif_running(netdev)) 2497 return -EAGAIN; 2498 2499 if (vf >= pci_num_vf(pdev)) 2500 return -EINVAL; 2501 2502 config = &pf->vf_configs[vf]; 2503 ivi->vf = vf; 2504 ether_addr_copy(ivi->mac, config->mac); 2505 ivi->vlan = config->vlan; 2506 ivi->trusted = config->trusted; 2507 2508 return 0; 2509 } 2510 2511 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2512 int qidx) 2513 { 2514 struct page *page; 2515 u64 dma_addr; 2516 int err = 0; 2517 2518 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2519 offset_in_page(xdpf->data), xdpf->len, 2520 DMA_TO_DEVICE); 2521 if (dma_mapping_error(pf->dev, dma_addr)) 2522 return -ENOMEM; 2523 2524 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2525 if (!err) { 2526 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2527 page = virt_to_page(xdpf->data); 2528 put_page(page); 2529 return -ENOMEM; 2530 } 2531 return 0; 2532 } 2533 2534 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2535 struct xdp_frame **frames, u32 flags) 2536 { 2537 struct otx2_nic *pf = netdev_priv(netdev); 2538 int qidx = smp_processor_id(); 2539 struct otx2_snd_queue *sq; 2540 int drops = 0, i; 2541 2542 if (!netif_running(netdev)) 2543 return -ENETDOWN; 2544 2545 qidx += pf->hw.tx_queues; 2546 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2547 2548 /* Abort xmit if xdp queue is not */ 2549 if (unlikely(!sq)) 2550 return -ENXIO; 2551 2552 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2553 return -EINVAL; 2554 2555 for (i = 0; i < n; i++) { 2556 struct xdp_frame *xdpf = frames[i]; 2557 int err; 2558 2559 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2560 if (err) 2561 drops++; 2562 } 2563 return n - drops; 2564 } 2565 2566 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2567 { 2568 struct net_device *dev = pf->netdev; 2569 bool if_up = netif_running(pf->netdev); 2570 struct bpf_prog *old_prog; 2571 2572 if (prog && dev->mtu > MAX_XDP_MTU) { 2573 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2574 return -EOPNOTSUPP; 2575 } 2576 2577 if (if_up) 2578 otx2_stop(pf->netdev); 2579 2580 old_prog = xchg(&pf->xdp_prog, prog); 2581 2582 if (old_prog) 2583 bpf_prog_put(old_prog); 2584 2585 if (pf->xdp_prog) 2586 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2587 2588 /* Network stack and XDP shared same rx queues. 2589 * Use separate tx queues for XDP and network stack. 2590 */ 2591 if (pf->xdp_prog) { 2592 pf->hw.xdp_queues = pf->hw.rx_queues; 2593 xdp_features_set_redirect_target(dev, false); 2594 } else { 2595 pf->hw.xdp_queues = 0; 2596 xdp_features_clear_redirect_target(dev); 2597 } 2598 2599 pf->hw.non_qos_queues += pf->hw.xdp_queues; 2600 2601 if (if_up) 2602 otx2_open(pf->netdev); 2603 2604 return 0; 2605 } 2606 2607 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2608 { 2609 struct otx2_nic *pf = netdev_priv(netdev); 2610 2611 switch (xdp->command) { 2612 case XDP_SETUP_PROG: 2613 return otx2_xdp_setup(pf, xdp->prog); 2614 default: 2615 return -EINVAL; 2616 } 2617 } 2618 2619 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2620 int req_perm) 2621 { 2622 struct set_vf_perm *req; 2623 int rc; 2624 2625 mutex_lock(&pf->mbox.lock); 2626 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2627 if (!req) { 2628 rc = -ENOMEM; 2629 goto out; 2630 } 2631 2632 /* Let AF reset VF permissions as sriov is disabled */ 2633 if (req_perm == OTX2_RESET_VF_PERM) { 2634 req->flags |= RESET_VF_PERM; 2635 } else if (req_perm == OTX2_TRUSTED_VF) { 2636 if (pf->vf_configs[vf].trusted) 2637 req->flags |= VF_TRUSTED; 2638 } 2639 2640 req->vf = vf; 2641 rc = otx2_sync_mbox_msg(&pf->mbox); 2642 out: 2643 mutex_unlock(&pf->mbox.lock); 2644 return rc; 2645 } 2646 2647 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2648 bool enable) 2649 { 2650 struct otx2_nic *pf = netdev_priv(netdev); 2651 struct pci_dev *pdev = pf->pdev; 2652 int rc; 2653 2654 if (vf >= pci_num_vf(pdev)) 2655 return -EINVAL; 2656 2657 if (pf->vf_configs[vf].trusted == enable) 2658 return 0; 2659 2660 pf->vf_configs[vf].trusted = enable; 2661 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2662 2663 if (rc) 2664 pf->vf_configs[vf].trusted = !enable; 2665 else 2666 netdev_info(pf->netdev, "VF %d is %strusted\n", 2667 vf, enable ? "" : "not "); 2668 return rc; 2669 } 2670 2671 static const struct net_device_ops otx2_netdev_ops = { 2672 .ndo_open = otx2_open, 2673 .ndo_stop = otx2_stop, 2674 .ndo_start_xmit = otx2_xmit, 2675 .ndo_select_queue = otx2_select_queue, 2676 .ndo_fix_features = otx2_fix_features, 2677 .ndo_set_mac_address = otx2_set_mac_address, 2678 .ndo_change_mtu = otx2_change_mtu, 2679 .ndo_set_rx_mode = otx2_set_rx_mode, 2680 .ndo_set_features = otx2_set_features, 2681 .ndo_tx_timeout = otx2_tx_timeout, 2682 .ndo_get_stats64 = otx2_get_stats64, 2683 .ndo_eth_ioctl = otx2_ioctl, 2684 .ndo_set_vf_mac = otx2_set_vf_mac, 2685 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2686 .ndo_get_vf_config = otx2_get_vf_config, 2687 .ndo_bpf = otx2_xdp, 2688 .ndo_xdp_xmit = otx2_xdp_xmit, 2689 .ndo_setup_tc = otx2_setup_tc, 2690 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2691 }; 2692 2693 static int otx2_wq_init(struct otx2_nic *pf) 2694 { 2695 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2696 if (!pf->otx2_wq) 2697 return -ENOMEM; 2698 2699 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2700 INIT_WORK(&pf->reset_task, otx2_reset_task); 2701 return 0; 2702 } 2703 2704 static int otx2_check_pf_usable(struct otx2_nic *nic) 2705 { 2706 u64 rev; 2707 2708 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2709 rev = (rev >> 12) & 0xFF; 2710 /* Check if AF has setup revision for RVUM block, 2711 * otherwise this driver probe should be deferred 2712 * until AF driver comes up. 2713 */ 2714 if (!rev) { 2715 dev_warn(nic->dev, 2716 "AF is not initialized, deferring probe\n"); 2717 return -EPROBE_DEFER; 2718 } 2719 return 0; 2720 } 2721 2722 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2723 { 2724 struct otx2_hw *hw = &pf->hw; 2725 int num_vec, err; 2726 2727 /* NPA interrupts are inot registered, so alloc only 2728 * upto NIX vector offset. 2729 */ 2730 num_vec = hw->nix_msixoff; 2731 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2732 2733 otx2_disable_mbox_intr(pf); 2734 pci_free_irq_vectors(hw->pdev); 2735 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2736 if (err < 0) { 2737 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2738 __func__, num_vec); 2739 return err; 2740 } 2741 2742 return otx2_register_mbox_intr(pf, false); 2743 } 2744 2745 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2746 { 2747 int i; 2748 2749 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2750 sizeof(struct otx2_vf_config), 2751 GFP_KERNEL); 2752 if (!pf->vf_configs) 2753 return -ENOMEM; 2754 2755 for (i = 0; i < pf->total_vfs; i++) { 2756 pf->vf_configs[i].pf = pf; 2757 pf->vf_configs[i].intf_down = true; 2758 pf->vf_configs[i].trusted = false; 2759 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2760 otx2_vf_link_event_task); 2761 } 2762 2763 return 0; 2764 } 2765 2766 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2767 { 2768 int i; 2769 2770 if (!pf->vf_configs) 2771 return; 2772 2773 for (i = 0; i < pf->total_vfs; i++) { 2774 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2775 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2776 } 2777 } 2778 2779 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2780 { 2781 struct device *dev = &pdev->dev; 2782 int err, qcount, qos_txqs; 2783 struct net_device *netdev; 2784 struct otx2_nic *pf; 2785 struct otx2_hw *hw; 2786 int num_vec; 2787 2788 err = pcim_enable_device(pdev); 2789 if (err) { 2790 dev_err(dev, "Failed to enable PCI device\n"); 2791 return err; 2792 } 2793 2794 err = pci_request_regions(pdev, DRV_NAME); 2795 if (err) { 2796 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2797 return err; 2798 } 2799 2800 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2801 if (err) { 2802 dev_err(dev, "DMA mask config failed, abort\n"); 2803 goto err_release_regions; 2804 } 2805 2806 pci_set_master(pdev); 2807 2808 /* Set number of queues */ 2809 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2810 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 2811 2812 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 2813 if (!netdev) { 2814 err = -ENOMEM; 2815 goto err_release_regions; 2816 } 2817 2818 pci_set_drvdata(pdev, netdev); 2819 SET_NETDEV_DEV(netdev, &pdev->dev); 2820 pf = netdev_priv(netdev); 2821 pf->netdev = netdev; 2822 pf->pdev = pdev; 2823 pf->dev = dev; 2824 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2825 pf->flags |= OTX2_FLAG_INTF_DOWN; 2826 2827 hw = &pf->hw; 2828 hw->pdev = pdev; 2829 hw->rx_queues = qcount; 2830 hw->tx_queues = qcount; 2831 hw->non_qos_queues = qcount; 2832 hw->max_queues = qcount; 2833 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2834 /* Use CQE of 128 byte descriptor size by default */ 2835 hw->xqe_size = 128; 2836 2837 num_vec = pci_msix_vec_count(pdev); 2838 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2839 GFP_KERNEL); 2840 if (!hw->irq_name) { 2841 err = -ENOMEM; 2842 goto err_free_netdev; 2843 } 2844 2845 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2846 sizeof(cpumask_var_t), GFP_KERNEL); 2847 if (!hw->affinity_mask) { 2848 err = -ENOMEM; 2849 goto err_free_netdev; 2850 } 2851 2852 /* Map CSRs */ 2853 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2854 if (!pf->reg_base) { 2855 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2856 err = -ENOMEM; 2857 goto err_free_netdev; 2858 } 2859 2860 err = otx2_check_pf_usable(pf); 2861 if (err) 2862 goto err_free_netdev; 2863 2864 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2865 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2866 if (err < 0) { 2867 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2868 __func__, num_vec); 2869 goto err_free_netdev; 2870 } 2871 2872 otx2_setup_dev_hw_settings(pf); 2873 2874 /* Init PF <=> AF mailbox stuff */ 2875 err = otx2_pfaf_mbox_init(pf); 2876 if (err) 2877 goto err_free_irq_vectors; 2878 2879 /* Register mailbox interrupt */ 2880 err = otx2_register_mbox_intr(pf, true); 2881 if (err) 2882 goto err_mbox_destroy; 2883 2884 /* Request AF to attach NPA and NIX LFs to this PF. 2885 * NIX and NPA LFs are needed for this PF to function as a NIC. 2886 */ 2887 err = otx2_attach_npa_nix(pf); 2888 if (err) 2889 goto err_disable_mbox_intr; 2890 2891 err = otx2_realloc_msix_vectors(pf); 2892 if (err) 2893 goto err_detach_rsrc; 2894 2895 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2896 if (err) 2897 goto err_detach_rsrc; 2898 2899 err = cn10k_lmtst_init(pf); 2900 if (err) 2901 goto err_detach_rsrc; 2902 2903 /* Assign default mac address */ 2904 otx2_get_mac_from_af(netdev); 2905 2906 /* Don't check for error. Proceed without ptp */ 2907 otx2_ptp_init(pf); 2908 2909 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2910 * HW allocates buffer pointer from stack and uses it for DMA'ing 2911 * ingress packet. In some scenarios HW can free back allocated buffer 2912 * pointers to pool. This makes it impossible for SW to maintain a 2913 * parallel list where physical addresses of buffer pointers (IOVAs) 2914 * given to HW can be saved for later reference. 2915 * 2916 * So the only way to convert Rx packet's buffer address is to use 2917 * IOMMU's iova_to_phys() handler which translates the address by 2918 * walking through the translation tables. 2919 */ 2920 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2921 2922 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2923 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2924 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2925 NETIF_F_GSO_UDP_L4); 2926 netdev->features |= netdev->hw_features; 2927 2928 err = otx2_mcam_flow_init(pf); 2929 if (err) 2930 goto err_ptp_destroy; 2931 2932 err = cn10k_mcs_init(pf); 2933 if (err) 2934 goto err_del_mcam_entries; 2935 2936 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2937 netdev->hw_features |= NETIF_F_NTUPLE; 2938 2939 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2940 netdev->priv_flags |= IFF_UNICAST_FLT; 2941 2942 /* Support TSO on tag interface */ 2943 netdev->vlan_features |= netdev->features; 2944 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2945 NETIF_F_HW_VLAN_STAG_TX; 2946 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2947 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2948 NETIF_F_HW_VLAN_STAG_RX; 2949 netdev->features |= netdev->hw_features; 2950 2951 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2952 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2953 netdev->hw_features |= NETIF_F_HW_TC; 2954 2955 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2956 2957 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2958 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2959 2960 netdev->netdev_ops = &otx2_netdev_ops; 2961 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 2962 2963 netdev->min_mtu = OTX2_MIN_MTU; 2964 netdev->max_mtu = otx2_get_max_mtu(pf); 2965 2966 err = register_netdev(netdev); 2967 if (err) { 2968 dev_err(dev, "Failed to register netdevice\n"); 2969 goto err_mcs_free; 2970 } 2971 2972 err = otx2_wq_init(pf); 2973 if (err) 2974 goto err_unreg_netdev; 2975 2976 otx2_set_ethtool_ops(netdev); 2977 2978 err = otx2_init_tc(pf); 2979 if (err) 2980 goto err_mcam_flow_del; 2981 2982 err = otx2_register_dl(pf); 2983 if (err) 2984 goto err_mcam_flow_del; 2985 2986 /* Initialize SR-IOV resources */ 2987 err = otx2_sriov_vfcfg_init(pf); 2988 if (err) 2989 goto err_pf_sriov_init; 2990 2991 /* Enable link notifications */ 2992 otx2_cgx_config_linkevents(pf, true); 2993 2994 #ifdef CONFIG_DCB 2995 err = otx2_dcbnl_set_ops(netdev); 2996 if (err) 2997 goto err_pf_sriov_init; 2998 #endif 2999 3000 otx2_qos_init(pf, qos_txqs); 3001 3002 return 0; 3003 3004 err_pf_sriov_init: 3005 otx2_shutdown_tc(pf); 3006 err_mcam_flow_del: 3007 otx2_mcam_flow_del(pf); 3008 err_unreg_netdev: 3009 unregister_netdev(netdev); 3010 err_mcs_free: 3011 cn10k_mcs_free(pf); 3012 err_del_mcam_entries: 3013 otx2_mcam_flow_del(pf); 3014 err_ptp_destroy: 3015 otx2_ptp_destroy(pf); 3016 err_detach_rsrc: 3017 if (pf->hw.lmt_info) 3018 free_percpu(pf->hw.lmt_info); 3019 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3020 qmem_free(pf->dev, pf->dync_lmt); 3021 otx2_detach_resources(&pf->mbox); 3022 err_disable_mbox_intr: 3023 otx2_disable_mbox_intr(pf); 3024 err_mbox_destroy: 3025 otx2_pfaf_mbox_destroy(pf); 3026 err_free_irq_vectors: 3027 pci_free_irq_vectors(hw->pdev); 3028 err_free_netdev: 3029 pci_set_drvdata(pdev, NULL); 3030 free_netdev(netdev); 3031 err_release_regions: 3032 pci_release_regions(pdev); 3033 return err; 3034 } 3035 3036 static void otx2_vf_link_event_task(struct work_struct *work) 3037 { 3038 struct otx2_vf_config *config; 3039 struct cgx_link_info_msg *req; 3040 struct mbox_msghdr *msghdr; 3041 struct otx2_nic *pf; 3042 int vf_idx; 3043 3044 config = container_of(work, struct otx2_vf_config, 3045 link_event_work.work); 3046 vf_idx = config - config->pf->vf_configs; 3047 pf = config->pf; 3048 3049 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3050 sizeof(*req), sizeof(struct msg_rsp)); 3051 if (!msghdr) { 3052 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3053 return; 3054 } 3055 3056 req = (struct cgx_link_info_msg *)msghdr; 3057 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3058 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3059 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3060 3061 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3062 } 3063 3064 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3065 { 3066 struct net_device *netdev = pci_get_drvdata(pdev); 3067 struct otx2_nic *pf = netdev_priv(netdev); 3068 int ret; 3069 3070 /* Init PF <=> VF mailbox stuff */ 3071 ret = otx2_pfvf_mbox_init(pf, numvfs); 3072 if (ret) 3073 return ret; 3074 3075 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3076 if (ret) 3077 goto free_mbox; 3078 3079 ret = otx2_pf_flr_init(pf, numvfs); 3080 if (ret) 3081 goto free_intr; 3082 3083 ret = otx2_register_flr_me_intr(pf, numvfs); 3084 if (ret) 3085 goto free_flr; 3086 3087 ret = pci_enable_sriov(pdev, numvfs); 3088 if (ret) 3089 goto free_flr_intr; 3090 3091 return numvfs; 3092 free_flr_intr: 3093 otx2_disable_flr_me_intr(pf); 3094 free_flr: 3095 otx2_flr_wq_destroy(pf); 3096 free_intr: 3097 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3098 free_mbox: 3099 otx2_pfvf_mbox_destroy(pf); 3100 return ret; 3101 } 3102 3103 static int otx2_sriov_disable(struct pci_dev *pdev) 3104 { 3105 struct net_device *netdev = pci_get_drvdata(pdev); 3106 struct otx2_nic *pf = netdev_priv(netdev); 3107 int numvfs = pci_num_vf(pdev); 3108 3109 if (!numvfs) 3110 return 0; 3111 3112 pci_disable_sriov(pdev); 3113 3114 otx2_disable_flr_me_intr(pf); 3115 otx2_flr_wq_destroy(pf); 3116 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3117 otx2_pfvf_mbox_destroy(pf); 3118 3119 return 0; 3120 } 3121 3122 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3123 { 3124 if (numvfs == 0) 3125 return otx2_sriov_disable(pdev); 3126 else 3127 return otx2_sriov_enable(pdev, numvfs); 3128 } 3129 3130 static void otx2_remove(struct pci_dev *pdev) 3131 { 3132 struct net_device *netdev = pci_get_drvdata(pdev); 3133 struct otx2_nic *pf; 3134 3135 if (!netdev) 3136 return; 3137 3138 pf = netdev_priv(netdev); 3139 3140 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3141 3142 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3143 otx2_config_hw_tx_tstamp(pf, false); 3144 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3145 otx2_config_hw_rx_tstamp(pf, false); 3146 3147 /* Disable 802.3x pause frames */ 3148 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3149 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3150 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3151 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3152 otx2_config_pause_frm(pf); 3153 } 3154 3155 #ifdef CONFIG_DCB 3156 /* Disable PFC config */ 3157 if (pf->pfc_en) { 3158 pf->pfc_en = 0; 3159 otx2_config_priority_flow_ctrl(pf); 3160 } 3161 #endif 3162 cancel_work_sync(&pf->reset_task); 3163 /* Disable link notifications */ 3164 otx2_cgx_config_linkevents(pf, false); 3165 3166 otx2_unregister_dl(pf); 3167 unregister_netdev(netdev); 3168 cn10k_mcs_free(pf); 3169 otx2_sriov_disable(pf->pdev); 3170 otx2_sriov_vfcfg_cleanup(pf); 3171 if (pf->otx2_wq) 3172 destroy_workqueue(pf->otx2_wq); 3173 3174 otx2_ptp_destroy(pf); 3175 otx2_mcam_flow_del(pf); 3176 otx2_shutdown_tc(pf); 3177 otx2_shutdown_qos(pf); 3178 otx2_detach_resources(&pf->mbox); 3179 if (pf->hw.lmt_info) 3180 free_percpu(pf->hw.lmt_info); 3181 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3182 qmem_free(pf->dev, pf->dync_lmt); 3183 otx2_disable_mbox_intr(pf); 3184 otx2_pfaf_mbox_destroy(pf); 3185 pci_free_irq_vectors(pf->pdev); 3186 pci_set_drvdata(pdev, NULL); 3187 free_netdev(netdev); 3188 3189 pci_release_regions(pdev); 3190 } 3191 3192 static struct pci_driver otx2_pf_driver = { 3193 .name = DRV_NAME, 3194 .id_table = otx2_pf_id_table, 3195 .probe = otx2_probe, 3196 .shutdown = otx2_remove, 3197 .remove = otx2_remove, 3198 .sriov_configure = otx2_sriov_configure 3199 }; 3200 3201 static int __init otx2_rvupf_init_module(void) 3202 { 3203 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3204 3205 return pci_register_driver(&otx2_pf_driver); 3206 } 3207 3208 static void __exit otx2_rvupf_cleanup_module(void) 3209 { 3210 pci_unregister_driver(&otx2_pf_driver); 3211 } 3212 3213 module_init(otx2_rvupf_init_module); 3214 module_exit(otx2_rvupf_cleanup_module); 3215