1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of.h> 16 #include <linux/if_vlan.h> 17 #include <linux/iommu.h> 18 #include <net/ip.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include "cn10k.h" 26 #include <rvu_trace.h> 27 28 #define DRV_NAME "rvu_nicpf" 29 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 30 31 /* Supported devices */ 32 static const struct pci_device_id otx2_pf_id_table[] = { 33 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 34 { 0, } /* end of table */ 35 }; 36 37 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 38 MODULE_DESCRIPTION(DRV_STRING); 39 MODULE_LICENSE("GPL v2"); 40 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 41 42 static void otx2_vf_link_event_task(struct work_struct *work); 43 44 enum { 45 TYPE_PFAF, 46 TYPE_PFVF, 47 }; 48 49 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 50 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 51 52 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 53 { 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (if_up) 58 otx2_stop(netdev); 59 60 netdev_info(netdev, "Changing MTU from %d to %d\n", 61 netdev->mtu, new_mtu); 62 netdev->mtu = new_mtu; 63 64 if (if_up) 65 err = otx2_open(netdev); 66 67 return err; 68 } 69 70 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 71 { 72 int irq, vfs = pf->total_vfs; 73 74 /* Disable VFs ME interrupts */ 75 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 76 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 77 free_irq(irq, pf); 78 79 /* Disable VFs FLR interrupts */ 80 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 82 free_irq(irq, pf); 83 84 if (vfs <= 64) 85 return; 86 87 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 88 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 89 free_irq(irq, pf); 90 91 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 92 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 93 free_irq(irq, pf); 94 } 95 96 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 97 { 98 if (!pf->flr_wq) 99 return; 100 destroy_workqueue(pf->flr_wq); 101 pf->flr_wq = NULL; 102 devm_kfree(pf->dev, pf->flr_wrk); 103 } 104 105 static void otx2_flr_handler(struct work_struct *work) 106 { 107 struct flr_work *flrwork = container_of(work, struct flr_work, work); 108 struct otx2_nic *pf = flrwork->pf; 109 struct mbox *mbox = &pf->mbox; 110 struct msg_req *req; 111 int vf, reg = 0; 112 113 vf = flrwork - pf->flr_wrk; 114 115 mutex_lock(&mbox->lock); 116 req = otx2_mbox_alloc_msg_vf_flr(mbox); 117 if (!req) { 118 mutex_unlock(&mbox->lock); 119 return; 120 } 121 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 122 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 123 124 if (!otx2_sync_mbox_msg(&pf->mbox)) { 125 if (vf >= 64) { 126 reg = 1; 127 vf = vf - 64; 128 } 129 /* clear transcation pending bit */ 130 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 131 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 132 } 133 134 mutex_unlock(&mbox->lock); 135 } 136 137 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 138 { 139 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 140 int reg, dev, vf, start_vf, num_reg = 1; 141 u64 intr; 142 143 if (pf->total_vfs > 64) 144 num_reg = 2; 145 146 for (reg = 0; reg < num_reg; reg++) { 147 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 148 if (!intr) 149 continue; 150 start_vf = 64 * reg; 151 for (vf = 0; vf < 64; vf++) { 152 if (!(intr & BIT_ULL(vf))) 153 continue; 154 dev = vf + start_vf; 155 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 156 /* Clear interrupt */ 157 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 158 /* Disable the interrupt */ 159 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 160 BIT_ULL(vf)); 161 } 162 } 163 return IRQ_HANDLED; 164 } 165 166 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 167 { 168 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 169 int vf, reg, num_reg = 1; 170 u64 intr; 171 172 if (pf->total_vfs > 64) 173 num_reg = 2; 174 175 for (reg = 0; reg < num_reg; reg++) { 176 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 177 if (!intr) 178 continue; 179 for (vf = 0; vf < 64; vf++) { 180 if (!(intr & BIT_ULL(vf))) 181 continue; 182 /* clear trpend bit */ 183 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 184 /* clear interrupt */ 185 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 186 } 187 } 188 return IRQ_HANDLED; 189 } 190 191 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 192 { 193 struct otx2_hw *hw = &pf->hw; 194 char *irq_name; 195 int ret; 196 197 /* Register ME interrupt handler*/ 198 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 199 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 200 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 201 otx2_pf_me_intr_handler, 0, irq_name, pf); 202 if (ret) { 203 dev_err(pf->dev, 204 "RVUPF: IRQ registration failed for ME0\n"); 205 } 206 207 /* Register FLR interrupt handler */ 208 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 209 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 210 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 211 otx2_pf_flr_intr_handler, 0, irq_name, pf); 212 if (ret) { 213 dev_err(pf->dev, 214 "RVUPF: IRQ registration failed for FLR0\n"); 215 return ret; 216 } 217 218 if (numvfs > 64) { 219 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 220 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 221 rvu_get_pf(pf->pcifunc)); 222 ret = request_irq(pci_irq_vector 223 (pf->pdev, RVU_PF_INT_VEC_VFME1), 224 otx2_pf_me_intr_handler, 0, irq_name, pf); 225 if (ret) { 226 dev_err(pf->dev, 227 "RVUPF: IRQ registration failed for ME1\n"); 228 } 229 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 230 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 231 rvu_get_pf(pf->pcifunc)); 232 ret = request_irq(pci_irq_vector 233 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 234 otx2_pf_flr_intr_handler, 0, irq_name, pf); 235 if (ret) { 236 dev_err(pf->dev, 237 "RVUPF: IRQ registration failed for FLR1\n"); 238 return ret; 239 } 240 } 241 242 /* Enable ME interrupt for all VFs*/ 243 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 244 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 245 246 /* Enable FLR interrupt for all VFs*/ 247 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 248 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 249 250 if (numvfs > 64) { 251 numvfs -= 64; 252 253 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 255 INTR_MASK(numvfs)); 256 257 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 258 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 259 INTR_MASK(numvfs)); 260 } 261 return 0; 262 } 263 264 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 265 { 266 int vf; 267 268 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 269 WQ_UNBOUND | WQ_HIGHPRI, 1); 270 if (!pf->flr_wq) 271 return -ENOMEM; 272 273 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 274 sizeof(struct flr_work), GFP_KERNEL); 275 if (!pf->flr_wrk) { 276 destroy_workqueue(pf->flr_wq); 277 return -ENOMEM; 278 } 279 280 for (vf = 0; vf < num_vfs; vf++) { 281 pf->flr_wrk[vf].pf = pf; 282 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 283 } 284 285 return 0; 286 } 287 288 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 289 int first, int mdevs, u64 intr, int type) 290 { 291 struct otx2_mbox_dev *mdev; 292 struct otx2_mbox *mbox; 293 struct mbox_hdr *hdr; 294 int i; 295 296 for (i = first; i < mdevs; i++) { 297 /* start from 0 */ 298 if (!(intr & BIT_ULL(i - first))) 299 continue; 300 301 mbox = &mw->mbox; 302 mdev = &mbox->dev[i]; 303 if (type == TYPE_PFAF) 304 otx2_sync_mbox_bbuf(mbox, i); 305 hdr = mdev->mbase + mbox->rx_start; 306 /* The hdr->num_msgs is set to zero immediately in the interrupt 307 * handler to ensure that it holds a correct value next time 308 * when the interrupt handler is called. 309 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 310 * pf>mbox.up_num_msgs holds the data for use in 311 * pfaf_mbox_up_handler. 312 */ 313 if (hdr->num_msgs) { 314 mw[i].num_msgs = hdr->num_msgs; 315 hdr->num_msgs = 0; 316 if (type == TYPE_PFAF) 317 memset(mbox->hwbase + mbox->rx_start, 0, 318 ALIGN(sizeof(struct mbox_hdr), 319 sizeof(u64))); 320 321 queue_work(mbox_wq, &mw[i].mbox_wrk); 322 } 323 324 mbox = &mw->mbox_up; 325 mdev = &mbox->dev[i]; 326 if (type == TYPE_PFAF) 327 otx2_sync_mbox_bbuf(mbox, i); 328 hdr = mdev->mbase + mbox->rx_start; 329 if (hdr->num_msgs) { 330 mw[i].up_num_msgs = hdr->num_msgs; 331 hdr->num_msgs = 0; 332 if (type == TYPE_PFAF) 333 memset(mbox->hwbase + mbox->rx_start, 0, 334 ALIGN(sizeof(struct mbox_hdr), 335 sizeof(u64))); 336 337 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 338 } 339 } 340 } 341 342 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 343 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 344 int devid) 345 { 346 struct otx2_mbox_dev *src_mdev = mdev; 347 int offset; 348 349 /* Msgs are already copied, trigger VF's mbox irq */ 350 smp_wmb(); 351 352 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 353 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 354 355 /* Restore VF's mbox bounce buffer region address */ 356 src_mdev->mbase = bbuf_base; 357 } 358 359 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 360 struct otx2_mbox *src_mbox, 361 int dir, int vf, int num_msgs) 362 { 363 struct otx2_mbox_dev *src_mdev, *dst_mdev; 364 struct mbox_hdr *mbox_hdr; 365 struct mbox_hdr *req_hdr; 366 struct mbox *dst_mbox; 367 int dst_size, err; 368 369 if (dir == MBOX_DIR_PFAF) { 370 /* Set VF's mailbox memory as PF's bounce buffer memory, so 371 * that explicit copying of VF's msgs to PF=>AF mbox region 372 * and AF=>PF responses to VF's mbox region can be avoided. 373 */ 374 src_mdev = &src_mbox->dev[vf]; 375 mbox_hdr = src_mbox->hwbase + 376 src_mbox->rx_start + (vf * MBOX_SIZE); 377 378 dst_mbox = &pf->mbox; 379 dst_size = dst_mbox->mbox.tx_size - 380 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 381 /* Check if msgs fit into destination area and has valid size */ 382 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 383 return -EINVAL; 384 385 dst_mdev = &dst_mbox->mbox.dev[0]; 386 387 mutex_lock(&pf->mbox.lock); 388 dst_mdev->mbase = src_mdev->mbase; 389 dst_mdev->msg_size = mbox_hdr->msg_size; 390 dst_mdev->num_msgs = num_msgs; 391 err = otx2_sync_mbox_msg(dst_mbox); 392 if (err) { 393 dev_warn(pf->dev, 394 "AF not responding to VF%d messages\n", vf); 395 /* restore PF mbase and exit */ 396 dst_mdev->mbase = pf->mbox.bbuf_base; 397 mutex_unlock(&pf->mbox.lock); 398 return err; 399 } 400 /* At this point, all the VF messages sent to AF are acked 401 * with proper responses and responses are copied to VF 402 * mailbox hence raise interrupt to VF. 403 */ 404 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 405 dst_mbox->mbox.rx_start); 406 req_hdr->num_msgs = num_msgs; 407 408 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 409 pf->mbox.bbuf_base, vf); 410 mutex_unlock(&pf->mbox.lock); 411 } else if (dir == MBOX_DIR_PFVF_UP) { 412 src_mdev = &src_mbox->dev[0]; 413 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 414 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 415 src_mbox->rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 dst_mbox = &pf->mbox_pfvf[0]; 419 dst_size = dst_mbox->mbox_up.tx_size - 420 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 421 /* Check if msgs fit into destination area */ 422 if (mbox_hdr->msg_size > dst_size) 423 return -EINVAL; 424 425 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 426 dst_mdev->mbase = src_mdev->mbase; 427 dst_mdev->msg_size = mbox_hdr->msg_size; 428 dst_mdev->num_msgs = mbox_hdr->num_msgs; 429 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 430 if (err) { 431 dev_warn(pf->dev, 432 "VF%d is not responding to mailbox\n", vf); 433 return err; 434 } 435 } else if (dir == MBOX_DIR_VFPF_UP) { 436 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 437 src_mbox->rx_start); 438 req_hdr->num_msgs = num_msgs; 439 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 440 &pf->mbox.mbox_up, 441 pf->mbox_pfvf[vf].bbuf_base, 442 0); 443 } 444 445 return 0; 446 } 447 448 static void otx2_pfvf_mbox_handler(struct work_struct *work) 449 { 450 struct mbox_msghdr *msg = NULL; 451 int offset, vf_idx, id, err; 452 struct otx2_mbox_dev *mdev; 453 struct mbox_hdr *req_hdr; 454 struct otx2_mbox *mbox; 455 struct mbox *vf_mbox; 456 struct otx2_nic *pf; 457 458 vf_mbox = container_of(work, struct mbox, mbox_wrk); 459 pf = vf_mbox->pfvf; 460 vf_idx = vf_mbox - pf->mbox_pfvf; 461 462 mbox = &pf->mbox_pfvf[0].mbox; 463 mdev = &mbox->dev[vf_idx]; 464 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 465 466 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 467 468 for (id = 0; id < vf_mbox->num_msgs; id++) { 469 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 470 offset); 471 472 if (msg->sig != OTX2_MBOX_REQ_SIG) 473 goto inval_msg; 474 475 /* Set VF's number in each of the msg */ 476 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 477 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 478 offset = msg->next_msgoff; 479 } 480 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 481 vf_mbox->num_msgs); 482 if (err) 483 goto inval_msg; 484 return; 485 486 inval_msg: 487 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 488 otx2_mbox_msg_send(mbox, vf_idx); 489 } 490 491 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 492 { 493 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 494 struct otx2_nic *pf = vf_mbox->pfvf; 495 struct otx2_mbox_dev *mdev; 496 int offset, id, vf_idx = 0; 497 struct mbox_hdr *rsp_hdr; 498 struct mbox_msghdr *msg; 499 struct otx2_mbox *mbox; 500 501 vf_idx = vf_mbox - pf->mbox_pfvf; 502 mbox = &pf->mbox_pfvf[0].mbox_up; 503 mdev = &mbox->dev[vf_idx]; 504 505 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 506 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 507 508 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 509 msg = mdev->mbase + offset; 510 511 if (msg->id >= MBOX_MSG_MAX) { 512 dev_err(pf->dev, 513 "Mbox msg with unknown ID 0x%x\n", msg->id); 514 goto end; 515 } 516 517 if (msg->sig != OTX2_MBOX_RSP_SIG) { 518 dev_err(pf->dev, 519 "Mbox msg with wrong signature %x, ID 0x%x\n", 520 msg->sig, msg->id); 521 goto end; 522 } 523 524 switch (msg->id) { 525 case MBOX_MSG_CGX_LINK_EVENT: 526 break; 527 default: 528 if (msg->rc) 529 dev_err(pf->dev, 530 "Mbox msg response has err %d, ID 0x%x\n", 531 msg->rc, msg->id); 532 break; 533 } 534 535 end: 536 offset = mbox->rx_start + msg->next_msgoff; 537 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 538 __otx2_mbox_reset(mbox, 0); 539 mdev->msgs_acked++; 540 } 541 } 542 543 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 544 { 545 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 546 int vfs = pf->total_vfs; 547 struct mbox *mbox; 548 u64 intr; 549 550 mbox = pf->mbox_pfvf; 551 /* Handle VF interrupts */ 552 if (vfs > 64) { 553 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 554 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 555 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 556 TYPE_PFVF); 557 vfs -= 64; 558 } 559 560 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 561 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 562 563 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 564 565 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 566 567 return IRQ_HANDLED; 568 } 569 570 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 571 { 572 void __iomem *hwbase; 573 struct mbox *mbox; 574 int err, vf; 575 u64 base; 576 577 if (!numvfs) 578 return -EINVAL; 579 580 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 581 sizeof(struct mbox), GFP_KERNEL); 582 if (!pf->mbox_pfvf) 583 return -ENOMEM; 584 585 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 586 WQ_UNBOUND | WQ_HIGHPRI | 587 WQ_MEM_RECLAIM, 1); 588 if (!pf->mbox_pfvf_wq) 589 return -ENOMEM; 590 591 /* On CN10K platform, PF <-> VF mailbox region follows after 592 * PF <-> AF mailbox region. 593 */ 594 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 595 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 596 MBOX_SIZE; 597 else 598 base = readq((void __iomem *)((u64)pf->reg_base + 599 RVU_PF_VF_BAR4_ADDR)); 600 601 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 602 if (!hwbase) { 603 err = -ENOMEM; 604 goto free_wq; 605 } 606 607 mbox = &pf->mbox_pfvf[0]; 608 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 609 MBOX_DIR_PFVF, numvfs); 610 if (err) 611 goto free_iomem; 612 613 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 614 MBOX_DIR_PFVF_UP, numvfs); 615 if (err) 616 goto free_iomem; 617 618 for (vf = 0; vf < numvfs; vf++) { 619 mbox->pfvf = pf; 620 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 621 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 622 mbox++; 623 } 624 625 return 0; 626 627 free_iomem: 628 if (hwbase) 629 iounmap(hwbase); 630 free_wq: 631 destroy_workqueue(pf->mbox_pfvf_wq); 632 return err; 633 } 634 635 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 636 { 637 struct mbox *mbox = &pf->mbox_pfvf[0]; 638 639 if (!mbox) 640 return; 641 642 if (pf->mbox_pfvf_wq) { 643 destroy_workqueue(pf->mbox_pfvf_wq); 644 pf->mbox_pfvf_wq = NULL; 645 } 646 647 if (mbox->mbox.hwbase) 648 iounmap(mbox->mbox.hwbase); 649 650 otx2_mbox_destroy(&mbox->mbox); 651 } 652 653 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 654 { 655 /* Clear PF <=> VF mailbox IRQ */ 656 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 657 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 658 659 /* Enable PF <=> VF mailbox IRQ */ 660 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 661 if (numvfs > 64) { 662 numvfs -= 64; 663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 664 INTR_MASK(numvfs)); 665 } 666 } 667 668 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 669 { 670 int vector; 671 672 /* Disable PF <=> VF mailbox IRQ */ 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 675 676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 677 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 678 free_irq(vector, pf); 679 680 if (numvfs > 64) { 681 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 682 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 683 free_irq(vector, pf); 684 } 685 } 686 687 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 688 { 689 struct otx2_hw *hw = &pf->hw; 690 char *irq_name; 691 int err; 692 693 /* Register MBOX0 interrupt handler */ 694 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 695 if (pf->pcifunc) 696 snprintf(irq_name, NAME_SIZE, 697 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 698 else 699 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 700 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 701 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 702 if (err) { 703 dev_err(pf->dev, 704 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 705 return err; 706 } 707 708 if (numvfs > 64) { 709 /* Register MBOX1 interrupt handler */ 710 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 711 if (pf->pcifunc) 712 snprintf(irq_name, NAME_SIZE, 713 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 714 else 715 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 716 err = request_irq(pci_irq_vector(pf->pdev, 717 RVU_PF_INT_VEC_VFPF_MBOX1), 718 otx2_pfvf_mbox_intr_handler, 719 0, irq_name, pf); 720 if (err) { 721 dev_err(pf->dev, 722 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 723 return err; 724 } 725 } 726 727 otx2_enable_pfvf_mbox_intr(pf, numvfs); 728 729 return 0; 730 } 731 732 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 733 struct mbox_msghdr *msg) 734 { 735 int devid; 736 737 if (msg->id >= MBOX_MSG_MAX) { 738 dev_err(pf->dev, 739 "Mbox msg with unknown ID 0x%x\n", msg->id); 740 return; 741 } 742 743 if (msg->sig != OTX2_MBOX_RSP_SIG) { 744 dev_err(pf->dev, 745 "Mbox msg with wrong signature %x, ID 0x%x\n", 746 msg->sig, msg->id); 747 return; 748 } 749 750 /* message response heading VF */ 751 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 752 if (devid) { 753 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 754 struct delayed_work *dwork; 755 756 switch (msg->id) { 757 case MBOX_MSG_NIX_LF_START_RX: 758 config->intf_down = false; 759 dwork = &config->link_event_work; 760 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 761 break; 762 case MBOX_MSG_NIX_LF_STOP_RX: 763 config->intf_down = true; 764 break; 765 } 766 767 return; 768 } 769 770 switch (msg->id) { 771 case MBOX_MSG_READY: 772 pf->pcifunc = msg->pcifunc; 773 break; 774 case MBOX_MSG_MSIX_OFFSET: 775 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 776 break; 777 case MBOX_MSG_NPA_LF_ALLOC: 778 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 779 break; 780 case MBOX_MSG_NIX_LF_ALLOC: 781 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 782 break; 783 case MBOX_MSG_NIX_TXSCH_ALLOC: 784 mbox_handler_nix_txsch_alloc(pf, 785 (struct nix_txsch_alloc_rsp *)msg); 786 break; 787 case MBOX_MSG_NIX_BP_ENABLE: 788 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 789 break; 790 case MBOX_MSG_CGX_STATS: 791 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 792 break; 793 case MBOX_MSG_CGX_FEC_STATS: 794 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 795 break; 796 default: 797 if (msg->rc) 798 dev_err(pf->dev, 799 "Mbox msg response has err %d, ID 0x%x\n", 800 msg->rc, msg->id); 801 break; 802 } 803 } 804 805 static void otx2_pfaf_mbox_handler(struct work_struct *work) 806 { 807 struct otx2_mbox_dev *mdev; 808 struct mbox_hdr *rsp_hdr; 809 struct mbox_msghdr *msg; 810 struct otx2_mbox *mbox; 811 struct mbox *af_mbox; 812 struct otx2_nic *pf; 813 int offset, id; 814 815 af_mbox = container_of(work, struct mbox, mbox_wrk); 816 mbox = &af_mbox->mbox; 817 mdev = &mbox->dev[0]; 818 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 819 820 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 821 pf = af_mbox->pfvf; 822 823 for (id = 0; id < af_mbox->num_msgs; id++) { 824 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 825 otx2_process_pfaf_mbox_msg(pf, msg); 826 offset = mbox->rx_start + msg->next_msgoff; 827 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 828 __otx2_mbox_reset(mbox, 0); 829 mdev->msgs_acked++; 830 } 831 832 } 833 834 static void otx2_handle_link_event(struct otx2_nic *pf) 835 { 836 struct cgx_link_user_info *linfo = &pf->linfo; 837 struct net_device *netdev = pf->netdev; 838 839 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 840 linfo->link_up ? "UP" : "DOWN", linfo->speed, 841 linfo->full_duplex ? "Full" : "Half"); 842 if (linfo->link_up) { 843 netif_carrier_on(netdev); 844 netif_tx_start_all_queues(netdev); 845 } else { 846 netif_tx_stop_all_queues(netdev); 847 netif_carrier_off(netdev); 848 } 849 } 850 851 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 852 struct cgx_link_info_msg *msg, 853 struct msg_rsp *rsp) 854 { 855 int i; 856 857 /* Copy the link info sent by AF */ 858 pf->linfo = msg->link_info; 859 860 /* notify VFs about link event */ 861 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 862 struct otx2_vf_config *config = &pf->vf_configs[i]; 863 struct delayed_work *dwork = &config->link_event_work; 864 865 if (config->intf_down) 866 continue; 867 868 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 869 } 870 871 /* interface has not been fully configured yet */ 872 if (pf->flags & OTX2_FLAG_INTF_DOWN) 873 return 0; 874 875 otx2_handle_link_event(pf); 876 return 0; 877 } 878 879 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 880 struct mbox_msghdr *req) 881 { 882 /* Check if valid, if not reply with a invalid msg */ 883 if (req->sig != OTX2_MBOX_REQ_SIG) { 884 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 885 return -ENODEV; 886 } 887 888 switch (req->id) { 889 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 890 case _id: { \ 891 struct _rsp_type *rsp; \ 892 int err; \ 893 \ 894 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 895 &pf->mbox.mbox_up, 0, \ 896 sizeof(struct _rsp_type)); \ 897 if (!rsp) \ 898 return -ENOMEM; \ 899 \ 900 rsp->hdr.id = _id; \ 901 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 902 rsp->hdr.pcifunc = 0; \ 903 rsp->hdr.rc = 0; \ 904 \ 905 err = otx2_mbox_up_handler_ ## _fn_name( \ 906 pf, (struct _req_type *)req, rsp); \ 907 return err; \ 908 } 909 MBOX_UP_CGX_MESSAGES 910 #undef M 911 break; 912 default: 913 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 914 return -ENODEV; 915 } 916 return 0; 917 } 918 919 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 920 { 921 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 922 struct otx2_mbox *mbox = &af_mbox->mbox_up; 923 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 924 struct otx2_nic *pf = af_mbox->pfvf; 925 int offset, id, devid = 0; 926 struct mbox_hdr *rsp_hdr; 927 struct mbox_msghdr *msg; 928 929 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 930 931 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 932 933 for (id = 0; id < af_mbox->up_num_msgs; id++) { 934 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 935 936 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 937 /* Skip processing VF's messages */ 938 if (!devid) 939 otx2_process_mbox_msg_up(pf, msg); 940 offset = mbox->rx_start + msg->next_msgoff; 941 } 942 if (devid) { 943 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 944 MBOX_DIR_PFVF_UP, devid - 1, 945 af_mbox->up_num_msgs); 946 return; 947 } 948 949 otx2_mbox_msg_send(mbox, 0); 950 } 951 952 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 953 { 954 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 955 struct mbox *mbox; 956 957 /* Clear the IRQ */ 958 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 959 960 mbox = &pf->mbox; 961 962 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 963 964 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 965 966 return IRQ_HANDLED; 967 } 968 969 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 970 { 971 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 972 973 /* Disable AF => PF mailbox IRQ */ 974 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 975 free_irq(vector, pf); 976 } 977 978 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 979 { 980 struct otx2_hw *hw = &pf->hw; 981 struct msg_req *req; 982 char *irq_name; 983 int err; 984 985 /* Register mailbox interrupt handler */ 986 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 987 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 988 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 989 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 990 if (err) { 991 dev_err(pf->dev, 992 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 993 return err; 994 } 995 996 /* Enable mailbox interrupt for msgs coming from AF. 997 * First clear to avoid spurious interrupts, if any. 998 */ 999 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1000 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1001 1002 if (!probe_af) 1003 return 0; 1004 1005 /* Check mailbox communication with AF */ 1006 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1007 if (!req) { 1008 otx2_disable_mbox_intr(pf); 1009 return -ENOMEM; 1010 } 1011 err = otx2_sync_mbox_msg(&pf->mbox); 1012 if (err) { 1013 dev_warn(pf->dev, 1014 "AF not responding to mailbox, deferring probe\n"); 1015 otx2_disable_mbox_intr(pf); 1016 return -EPROBE_DEFER; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1023 { 1024 struct mbox *mbox = &pf->mbox; 1025 1026 if (pf->mbox_wq) { 1027 destroy_workqueue(pf->mbox_wq); 1028 pf->mbox_wq = NULL; 1029 } 1030 1031 if (mbox->mbox.hwbase) 1032 iounmap((void __iomem *)mbox->mbox.hwbase); 1033 1034 otx2_mbox_destroy(&mbox->mbox); 1035 otx2_mbox_destroy(&mbox->mbox_up); 1036 } 1037 1038 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1039 { 1040 struct mbox *mbox = &pf->mbox; 1041 void __iomem *hwbase; 1042 int err; 1043 1044 mbox->pfvf = pf; 1045 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1046 WQ_UNBOUND | WQ_HIGHPRI | 1047 WQ_MEM_RECLAIM, 1); 1048 if (!pf->mbox_wq) 1049 return -ENOMEM; 1050 1051 /* Mailbox is a reserved memory (in RAM) region shared between 1052 * admin function (i.e AF) and this PF, shouldn't be mapped as 1053 * device memory to allow unaligned accesses. 1054 */ 1055 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1056 MBOX_SIZE); 1057 if (!hwbase) { 1058 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1059 err = -ENOMEM; 1060 goto exit; 1061 } 1062 1063 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1064 MBOX_DIR_PFAF, 1); 1065 if (err) 1066 goto exit; 1067 1068 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1069 MBOX_DIR_PFAF_UP, 1); 1070 if (err) 1071 goto exit; 1072 1073 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1074 if (err) 1075 goto exit; 1076 1077 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1078 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1079 mutex_init(&mbox->lock); 1080 1081 return 0; 1082 exit: 1083 otx2_pfaf_mbox_destroy(pf); 1084 return err; 1085 } 1086 1087 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1088 { 1089 struct msg_req *msg; 1090 int err; 1091 1092 mutex_lock(&pf->mbox.lock); 1093 if (enable) 1094 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1095 else 1096 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1097 1098 if (!msg) { 1099 mutex_unlock(&pf->mbox.lock); 1100 return -ENOMEM; 1101 } 1102 1103 err = otx2_sync_mbox_msg(&pf->mbox); 1104 mutex_unlock(&pf->mbox.lock); 1105 return err; 1106 } 1107 1108 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1109 { 1110 struct msg_req *msg; 1111 int err; 1112 1113 mutex_lock(&pf->mbox.lock); 1114 if (enable) 1115 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1116 else 1117 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1118 1119 if (!msg) { 1120 mutex_unlock(&pf->mbox.lock); 1121 return -ENOMEM; 1122 } 1123 1124 err = otx2_sync_mbox_msg(&pf->mbox); 1125 mutex_unlock(&pf->mbox.lock); 1126 return err; 1127 } 1128 1129 int otx2_set_real_num_queues(struct net_device *netdev, 1130 int tx_queues, int rx_queues) 1131 { 1132 int err; 1133 1134 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1135 if (err) { 1136 netdev_err(netdev, 1137 "Failed to set no of Tx queues: %d\n", tx_queues); 1138 return err; 1139 } 1140 1141 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1142 if (err) 1143 netdev_err(netdev, 1144 "Failed to set no of Rx queues: %d\n", rx_queues); 1145 return err; 1146 } 1147 EXPORT_SYMBOL(otx2_set_real_num_queues); 1148 1149 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1150 { 1151 struct otx2_nic *pf = data; 1152 u64 val, *ptr; 1153 u64 qidx = 0; 1154 1155 /* CQ */ 1156 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1157 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1158 val = otx2_atomic64_add((qidx << 44), ptr); 1159 1160 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1161 (val & NIX_CQERRINT_BITS)); 1162 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1163 continue; 1164 1165 if (val & BIT_ULL(42)) { 1166 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1167 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1168 } else { 1169 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1170 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1171 qidx); 1172 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1173 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1174 qidx); 1175 } 1176 1177 schedule_work(&pf->reset_task); 1178 } 1179 1180 /* SQ */ 1181 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1182 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1183 val = otx2_atomic64_add((qidx << 44), ptr); 1184 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1185 (val & NIX_SQINT_BITS)); 1186 1187 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1188 continue; 1189 1190 if (val & BIT_ULL(42)) { 1191 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1192 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1193 } else { 1194 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1195 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1196 qidx, 1197 otx2_read64(pf, 1198 NIX_LF_SQ_OP_ERR_DBG)); 1199 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1200 BIT_ULL(44)); 1201 } 1202 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1203 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1204 qidx, 1205 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1206 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1207 BIT_ULL(44)); 1208 } 1209 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1210 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1211 qidx, 1212 otx2_read64(pf, 1213 NIX_LF_SEND_ERR_DBG)); 1214 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1215 BIT_ULL(44)); 1216 } 1217 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1218 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1219 qidx); 1220 } 1221 1222 schedule_work(&pf->reset_task); 1223 } 1224 1225 return IRQ_HANDLED; 1226 } 1227 1228 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1229 { 1230 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1231 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1232 int qidx = cq_poll->cint_idx; 1233 1234 /* Disable interrupts. 1235 * 1236 * Completion interrupts behave in a level-triggered interrupt 1237 * fashion, and hence have to be cleared only after it is serviced. 1238 */ 1239 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1240 1241 /* Schedule NAPI */ 1242 napi_schedule_irqoff(&cq_poll->napi); 1243 1244 return IRQ_HANDLED; 1245 } 1246 1247 static void otx2_disable_napi(struct otx2_nic *pf) 1248 { 1249 struct otx2_qset *qset = &pf->qset; 1250 struct otx2_cq_poll *cq_poll; 1251 int qidx; 1252 1253 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1254 cq_poll = &qset->napi[qidx]; 1255 napi_disable(&cq_poll->napi); 1256 netif_napi_del(&cq_poll->napi); 1257 } 1258 } 1259 1260 static void otx2_free_cq_res(struct otx2_nic *pf) 1261 { 1262 struct otx2_qset *qset = &pf->qset; 1263 struct otx2_cq_queue *cq; 1264 int qidx; 1265 1266 /* Disable CQs */ 1267 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1268 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1269 cq = &qset->cq[qidx]; 1270 qmem_free(pf->dev, cq->cqe); 1271 } 1272 } 1273 1274 static void otx2_free_sq_res(struct otx2_nic *pf) 1275 { 1276 struct otx2_qset *qset = &pf->qset; 1277 struct otx2_snd_queue *sq; 1278 int qidx; 1279 1280 /* Disable SQs */ 1281 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1282 /* Free SQB pointers */ 1283 otx2_sq_free_sqbs(pf); 1284 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1285 sq = &qset->sq[qidx]; 1286 qmem_free(pf->dev, sq->sqe); 1287 qmem_free(pf->dev, sq->tso_hdrs); 1288 kfree(sq->sg); 1289 kfree(sq->sqb_ptrs); 1290 } 1291 } 1292 1293 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1294 { 1295 int frame_size; 1296 int total_size; 1297 int rbuf_size; 1298 1299 /* The data transferred by NIX to memory consists of actual packet 1300 * plus additional data which has timestamp and/or EDSA/HIGIG2 1301 * headers if interface is configured in corresponding modes. 1302 * NIX transfers entire data using 6 segments/buffers and writes 1303 * a CQE_RX descriptor with those segment addresses. First segment 1304 * has additional data prepended to packet. Also software omits a 1305 * headroom of 128 bytes and sizeof(struct skb_shared_info) in 1306 * each segment. Hence the total size of memory needed 1307 * to receive a packet with 'mtu' is: 1308 * frame size = mtu + additional data; 1309 * memory = frame_size + (headroom + struct skb_shared_info size) * 6; 1310 * each receive buffer size = memory / 6; 1311 */ 1312 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1313 total_size = frame_size + (OTX2_HEAD_ROOM + 1314 OTX2_DATA_ALIGN(sizeof(struct skb_shared_info))) * 6; 1315 rbuf_size = total_size / 6; 1316 1317 return ALIGN(rbuf_size, 2048); 1318 } 1319 1320 static int otx2_init_hw_resources(struct otx2_nic *pf) 1321 { 1322 struct nix_lf_free_req *free_req; 1323 struct mbox *mbox = &pf->mbox; 1324 struct otx2_hw *hw = &pf->hw; 1325 struct msg_req *req; 1326 int err = 0, lvl; 1327 1328 /* Set required NPA LF's pool counts 1329 * Auras and Pools are used in a 1:1 mapping, 1330 * so, aura count = pool count. 1331 */ 1332 hw->rqpool_cnt = hw->rx_queues; 1333 hw->sqpool_cnt = hw->tx_queues; 1334 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1335 1336 pf->max_frs = pf->netdev->mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1337 1338 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1339 1340 mutex_lock(&mbox->lock); 1341 /* NPA init */ 1342 err = otx2_config_npa(pf); 1343 if (err) 1344 goto exit; 1345 1346 /* NIX init */ 1347 err = otx2_config_nix(pf); 1348 if (err) 1349 goto err_free_npa_lf; 1350 1351 /* Enable backpressure */ 1352 otx2_nix_config_bp(pf, true); 1353 1354 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1355 err = otx2_rq_aura_pool_init(pf); 1356 if (err) { 1357 mutex_unlock(&mbox->lock); 1358 goto err_free_nix_lf; 1359 } 1360 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1361 err = otx2_sq_aura_pool_init(pf); 1362 if (err) { 1363 mutex_unlock(&mbox->lock); 1364 goto err_free_rq_ptrs; 1365 } 1366 1367 err = otx2_txsch_alloc(pf); 1368 if (err) { 1369 mutex_unlock(&mbox->lock); 1370 goto err_free_sq_ptrs; 1371 } 1372 1373 err = otx2_config_nix_queues(pf); 1374 if (err) { 1375 mutex_unlock(&mbox->lock); 1376 goto err_free_txsch; 1377 } 1378 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1379 err = otx2_txschq_config(pf, lvl); 1380 if (err) { 1381 mutex_unlock(&mbox->lock); 1382 goto err_free_nix_queues; 1383 } 1384 } 1385 mutex_unlock(&mbox->lock); 1386 return err; 1387 1388 err_free_nix_queues: 1389 otx2_free_sq_res(pf); 1390 otx2_free_cq_res(pf); 1391 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1392 err_free_txsch: 1393 if (otx2_txschq_stop(pf)) 1394 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1395 err_free_sq_ptrs: 1396 otx2_sq_free_sqbs(pf); 1397 err_free_rq_ptrs: 1398 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1399 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1400 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1401 otx2_aura_pool_free(pf); 1402 err_free_nix_lf: 1403 mutex_lock(&mbox->lock); 1404 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1405 if (free_req) { 1406 free_req->flags = NIX_LF_DISABLE_FLOWS; 1407 if (otx2_sync_mbox_msg(mbox)) 1408 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1409 } 1410 err_free_npa_lf: 1411 /* Reset NPA LF */ 1412 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1413 if (req) { 1414 if (otx2_sync_mbox_msg(mbox)) 1415 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1416 } 1417 exit: 1418 mutex_unlock(&mbox->lock); 1419 return err; 1420 } 1421 1422 static void otx2_free_hw_resources(struct otx2_nic *pf) 1423 { 1424 struct otx2_qset *qset = &pf->qset; 1425 struct nix_lf_free_req *free_req; 1426 struct mbox *mbox = &pf->mbox; 1427 struct otx2_cq_queue *cq; 1428 struct msg_req *req; 1429 int qidx, err; 1430 1431 /* Ensure all SQE are processed */ 1432 otx2_sqb_flush(pf); 1433 1434 /* Stop transmission */ 1435 err = otx2_txschq_stop(pf); 1436 if (err) 1437 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1438 1439 mutex_lock(&mbox->lock); 1440 /* Disable backpressure */ 1441 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1442 otx2_nix_config_bp(pf, false); 1443 mutex_unlock(&mbox->lock); 1444 1445 /* Disable RQs */ 1446 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1447 1448 /*Dequeue all CQEs */ 1449 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1450 cq = &qset->cq[qidx]; 1451 if (cq->cq_type == CQ_RX) 1452 otx2_cleanup_rx_cqes(pf, cq); 1453 else 1454 otx2_cleanup_tx_cqes(pf, cq); 1455 } 1456 1457 otx2_free_sq_res(pf); 1458 1459 /* Free RQ buffer pointers*/ 1460 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1461 1462 otx2_free_cq_res(pf); 1463 1464 /* Free all ingress bandwidth profiles allocated */ 1465 cn10k_free_all_ipolicers(pf); 1466 1467 mutex_lock(&mbox->lock); 1468 /* Reset NIX LF */ 1469 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1470 if (free_req) { 1471 free_req->flags = NIX_LF_DISABLE_FLOWS; 1472 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1473 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1474 if (otx2_sync_mbox_msg(mbox)) 1475 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1476 } 1477 mutex_unlock(&mbox->lock); 1478 1479 /* Disable NPA Pool and Aura hw context */ 1480 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1481 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1482 otx2_aura_pool_free(pf); 1483 1484 mutex_lock(&mbox->lock); 1485 /* Reset NPA LF */ 1486 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1487 if (req) { 1488 if (otx2_sync_mbox_msg(mbox)) 1489 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1490 } 1491 mutex_unlock(&mbox->lock); 1492 } 1493 1494 int otx2_open(struct net_device *netdev) 1495 { 1496 struct otx2_nic *pf = netdev_priv(netdev); 1497 struct otx2_cq_poll *cq_poll = NULL; 1498 struct otx2_qset *qset = &pf->qset; 1499 int err = 0, qidx, vec; 1500 char *irq_name; 1501 1502 netif_carrier_off(netdev); 1503 1504 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues; 1505 /* RQ and SQs are mapped to different CQs, 1506 * so find out max CQ IRQs (i.e CINTs) needed. 1507 */ 1508 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1509 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1510 if (!qset->napi) 1511 return -ENOMEM; 1512 1513 /* CQ size of RQ */ 1514 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1515 /* CQ size of SQ */ 1516 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1517 1518 err = -ENOMEM; 1519 qset->cq = kcalloc(pf->qset.cq_cnt, 1520 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1521 if (!qset->cq) 1522 goto err_free_mem; 1523 1524 qset->sq = kcalloc(pf->hw.tx_queues, 1525 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1526 if (!qset->sq) 1527 goto err_free_mem; 1528 1529 qset->rq = kcalloc(pf->hw.rx_queues, 1530 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1531 if (!qset->rq) 1532 goto err_free_mem; 1533 1534 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) { 1535 /* Reserve LMT lines for NPA AURA batch free */ 1536 pf->hw.npa_lmt_base = (__force u64 *)pf->hw.lmt_base; 1537 /* Reserve LMT lines for NIX TX */ 1538 pf->hw.nix_lmt_base = (__force u64 *)((u64)pf->hw.npa_lmt_base + 1539 (NIX_LMTID_BASE * LMT_LINE_SIZE)); 1540 } 1541 1542 err = otx2_init_hw_resources(pf); 1543 if (err) 1544 goto err_free_mem; 1545 1546 /* Register NAPI handler */ 1547 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1548 cq_poll = &qset->napi[qidx]; 1549 cq_poll->cint_idx = qidx; 1550 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1551 * 'cq_ids[0]' points to RQ's CQ and 1552 * 'cq_ids[1]' points to SQ's CQ and 1553 */ 1554 cq_poll->cq_ids[CQ_RX] = 1555 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1556 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1557 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1558 cq_poll->dev = (void *)pf; 1559 netif_napi_add(netdev, &cq_poll->napi, 1560 otx2_napi_handler, NAPI_POLL_WEIGHT); 1561 napi_enable(&cq_poll->napi); 1562 } 1563 1564 /* Set maximum frame size allowed in HW */ 1565 err = otx2_hw_set_mtu(pf, netdev->mtu); 1566 if (err) 1567 goto err_disable_napi; 1568 1569 /* Setup segmentation algorithms, if failed, clear offload capability */ 1570 otx2_setup_segmentation(pf); 1571 1572 /* Initialize RSS */ 1573 err = otx2_rss_init(pf); 1574 if (err) 1575 goto err_disable_napi; 1576 1577 /* Register Queue IRQ handlers */ 1578 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1579 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1580 1581 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1582 1583 err = request_irq(pci_irq_vector(pf->pdev, vec), 1584 otx2_q_intr_handler, 0, irq_name, pf); 1585 if (err) { 1586 dev_err(pf->dev, 1587 "RVUPF%d: IRQ registration failed for QERR\n", 1588 rvu_get_pf(pf->pcifunc)); 1589 goto err_disable_napi; 1590 } 1591 1592 /* Enable QINT IRQ */ 1593 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1594 1595 /* Register CQ IRQ handlers */ 1596 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1597 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1598 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1599 1600 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1601 qidx); 1602 1603 err = request_irq(pci_irq_vector(pf->pdev, vec), 1604 otx2_cq_intr_handler, 0, irq_name, 1605 &qset->napi[qidx]); 1606 if (err) { 1607 dev_err(pf->dev, 1608 "RVUPF%d: IRQ registration failed for CQ%d\n", 1609 rvu_get_pf(pf->pcifunc), qidx); 1610 goto err_free_cints; 1611 } 1612 vec++; 1613 1614 otx2_config_irq_coalescing(pf, qidx); 1615 1616 /* Enable CQ IRQ */ 1617 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1618 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1619 } 1620 1621 otx2_set_cints_affinity(pf); 1622 1623 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1624 otx2_enable_rxvlan(pf, true); 1625 1626 /* When reinitializing enable time stamping if it is enabled before */ 1627 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1628 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1629 otx2_config_hw_tx_tstamp(pf, true); 1630 } 1631 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1632 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1633 otx2_config_hw_rx_tstamp(pf, true); 1634 } 1635 1636 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1637 /* 'intf_down' may be checked on any cpu */ 1638 smp_wmb(); 1639 1640 /* we have already received link status notification */ 1641 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1642 otx2_handle_link_event(pf); 1643 1644 /* Restore pause frame settings */ 1645 otx2_config_pause_frm(pf); 1646 1647 err = otx2_rxtx_enable(pf, true); 1648 if (err) 1649 goto err_tx_stop_queues; 1650 1651 return 0; 1652 1653 err_tx_stop_queues: 1654 netif_tx_stop_all_queues(netdev); 1655 netif_carrier_off(netdev); 1656 err_free_cints: 1657 otx2_free_cints(pf, qidx); 1658 vec = pci_irq_vector(pf->pdev, 1659 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1660 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1661 synchronize_irq(vec); 1662 free_irq(vec, pf); 1663 err_disable_napi: 1664 otx2_disable_napi(pf); 1665 otx2_free_hw_resources(pf); 1666 err_free_mem: 1667 kfree(qset->sq); 1668 kfree(qset->cq); 1669 kfree(qset->rq); 1670 kfree(qset->napi); 1671 return err; 1672 } 1673 EXPORT_SYMBOL(otx2_open); 1674 1675 int otx2_stop(struct net_device *netdev) 1676 { 1677 struct otx2_nic *pf = netdev_priv(netdev); 1678 struct otx2_cq_poll *cq_poll = NULL; 1679 struct otx2_qset *qset = &pf->qset; 1680 struct otx2_rss_info *rss; 1681 int qidx, vec, wrk; 1682 1683 netif_carrier_off(netdev); 1684 netif_tx_stop_all_queues(netdev); 1685 1686 pf->flags |= OTX2_FLAG_INTF_DOWN; 1687 /* 'intf_down' may be checked on any cpu */ 1688 smp_wmb(); 1689 1690 /* First stop packet Rx/Tx */ 1691 otx2_rxtx_enable(pf, false); 1692 1693 /* Clear RSS enable flag */ 1694 rss = &pf->hw.rss_info; 1695 rss->enable = false; 1696 1697 /* Cleanup Queue IRQ */ 1698 vec = pci_irq_vector(pf->pdev, 1699 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1700 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1701 synchronize_irq(vec); 1702 free_irq(vec, pf); 1703 1704 /* Cleanup CQ NAPI and IRQ */ 1705 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1706 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1707 /* Disable interrupt */ 1708 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1709 1710 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1711 1712 cq_poll = &qset->napi[qidx]; 1713 napi_synchronize(&cq_poll->napi); 1714 vec++; 1715 } 1716 1717 netif_tx_disable(netdev); 1718 1719 otx2_free_hw_resources(pf); 1720 otx2_free_cints(pf, pf->hw.cint_cnt); 1721 otx2_disable_napi(pf); 1722 1723 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1724 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1725 1726 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1727 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1728 devm_kfree(pf->dev, pf->refill_wrk); 1729 1730 kfree(qset->sq); 1731 kfree(qset->cq); 1732 kfree(qset->rq); 1733 kfree(qset->napi); 1734 /* Do not clear RQ/SQ ringsize settings */ 1735 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1736 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1737 return 0; 1738 } 1739 EXPORT_SYMBOL(otx2_stop); 1740 1741 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1742 { 1743 struct otx2_nic *pf = netdev_priv(netdev); 1744 int qidx = skb_get_queue_mapping(skb); 1745 struct otx2_snd_queue *sq; 1746 struct netdev_queue *txq; 1747 1748 /* Check for minimum and maximum packet length */ 1749 if (skb->len <= ETH_HLEN || 1750 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1751 dev_kfree_skb(skb); 1752 return NETDEV_TX_OK; 1753 } 1754 1755 sq = &pf->qset.sq[qidx]; 1756 txq = netdev_get_tx_queue(netdev, qidx); 1757 1758 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1759 netif_tx_stop_queue(txq); 1760 1761 /* Check again, incase SQBs got freed up */ 1762 smp_mb(); 1763 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1764 > sq->sqe_thresh) 1765 netif_tx_wake_queue(txq); 1766 1767 return NETDEV_TX_BUSY; 1768 } 1769 1770 return NETDEV_TX_OK; 1771 } 1772 1773 static netdev_features_t otx2_fix_features(struct net_device *dev, 1774 netdev_features_t features) 1775 { 1776 /* check if n-tuple filters are ON */ 1777 if ((features & NETIF_F_HW_TC) && (dev->features & NETIF_F_NTUPLE)) { 1778 netdev_info(dev, "Disabling n-tuple filters\n"); 1779 features &= ~NETIF_F_NTUPLE; 1780 } 1781 1782 /* check if tc hw offload is ON */ 1783 if ((features & NETIF_F_NTUPLE) && (dev->features & NETIF_F_HW_TC)) { 1784 netdev_info(dev, "Disabling TC hardware offload\n"); 1785 features &= ~NETIF_F_HW_TC; 1786 } 1787 1788 return features; 1789 } 1790 1791 static void otx2_set_rx_mode(struct net_device *netdev) 1792 { 1793 struct otx2_nic *pf = netdev_priv(netdev); 1794 1795 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1796 } 1797 1798 static void otx2_do_set_rx_mode(struct work_struct *work) 1799 { 1800 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1801 struct net_device *netdev = pf->netdev; 1802 struct nix_rx_mode *req; 1803 bool promisc = false; 1804 1805 if (!(netdev->flags & IFF_UP)) 1806 return; 1807 1808 if ((netdev->flags & IFF_PROMISC) || 1809 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1810 promisc = true; 1811 } 1812 1813 /* Write unicast address to mcam entries or del from mcam */ 1814 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1815 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1816 1817 mutex_lock(&pf->mbox.lock); 1818 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1819 if (!req) { 1820 mutex_unlock(&pf->mbox.lock); 1821 return; 1822 } 1823 1824 req->mode = NIX_RX_MODE_UCAST; 1825 1826 if (promisc) 1827 req->mode |= NIX_RX_MODE_PROMISC; 1828 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1829 req->mode |= NIX_RX_MODE_ALLMULTI; 1830 1831 req->mode |= NIX_RX_MODE_USE_MCE; 1832 1833 otx2_sync_mbox_msg(&pf->mbox); 1834 mutex_unlock(&pf->mbox.lock); 1835 } 1836 1837 static int otx2_set_features(struct net_device *netdev, 1838 netdev_features_t features) 1839 { 1840 netdev_features_t changed = features ^ netdev->features; 1841 bool ntuple = !!(features & NETIF_F_NTUPLE); 1842 struct otx2_nic *pf = netdev_priv(netdev); 1843 1844 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1845 return otx2_cgx_config_loopback(pf, 1846 features & NETIF_F_LOOPBACK); 1847 1848 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1849 return otx2_enable_rxvlan(pf, 1850 features & NETIF_F_HW_VLAN_CTAG_RX); 1851 1852 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1853 otx2_destroy_ntuple_flows(pf); 1854 1855 if ((netdev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1856 pf->tc_info.num_entries) { 1857 netdev_err(netdev, "Can't disable TC hardware offload while flows are active\n"); 1858 return -EBUSY; 1859 } 1860 1861 return 0; 1862 } 1863 1864 static void otx2_reset_task(struct work_struct *work) 1865 { 1866 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1867 1868 if (!netif_running(pf->netdev)) 1869 return; 1870 1871 rtnl_lock(); 1872 otx2_stop(pf->netdev); 1873 pf->reset_count++; 1874 otx2_open(pf->netdev); 1875 netif_trans_update(pf->netdev); 1876 rtnl_unlock(); 1877 } 1878 1879 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1880 { 1881 struct msg_req *req; 1882 int err; 1883 1884 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1885 return 0; 1886 1887 mutex_lock(&pfvf->mbox.lock); 1888 if (enable) 1889 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1890 else 1891 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1892 if (!req) { 1893 mutex_unlock(&pfvf->mbox.lock); 1894 return -ENOMEM; 1895 } 1896 1897 err = otx2_sync_mbox_msg(&pfvf->mbox); 1898 if (err) { 1899 mutex_unlock(&pfvf->mbox.lock); 1900 return err; 1901 } 1902 1903 mutex_unlock(&pfvf->mbox.lock); 1904 if (enable) 1905 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1906 else 1907 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1908 return 0; 1909 } 1910 1911 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1912 { 1913 struct msg_req *req; 1914 int err; 1915 1916 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1917 return 0; 1918 1919 mutex_lock(&pfvf->mbox.lock); 1920 if (enable) 1921 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1922 else 1923 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1924 if (!req) { 1925 mutex_unlock(&pfvf->mbox.lock); 1926 return -ENOMEM; 1927 } 1928 1929 err = otx2_sync_mbox_msg(&pfvf->mbox); 1930 if (err) { 1931 mutex_unlock(&pfvf->mbox.lock); 1932 return err; 1933 } 1934 1935 mutex_unlock(&pfvf->mbox.lock); 1936 if (enable) 1937 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1938 else 1939 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1940 return 0; 1941 } 1942 1943 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1944 { 1945 struct otx2_nic *pfvf = netdev_priv(netdev); 1946 struct hwtstamp_config config; 1947 1948 if (!pfvf->ptp) 1949 return -ENODEV; 1950 1951 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1952 return -EFAULT; 1953 1954 /* reserved for future extensions */ 1955 if (config.flags) 1956 return -EINVAL; 1957 1958 switch (config.tx_type) { 1959 case HWTSTAMP_TX_OFF: 1960 otx2_config_hw_tx_tstamp(pfvf, false); 1961 break; 1962 case HWTSTAMP_TX_ON: 1963 otx2_config_hw_tx_tstamp(pfvf, true); 1964 break; 1965 default: 1966 return -ERANGE; 1967 } 1968 1969 switch (config.rx_filter) { 1970 case HWTSTAMP_FILTER_NONE: 1971 otx2_config_hw_rx_tstamp(pfvf, false); 1972 break; 1973 case HWTSTAMP_FILTER_ALL: 1974 case HWTSTAMP_FILTER_SOME: 1975 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1976 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1977 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1978 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1979 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1980 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1981 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1982 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1983 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1984 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1985 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1986 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1987 otx2_config_hw_rx_tstamp(pfvf, true); 1988 config.rx_filter = HWTSTAMP_FILTER_ALL; 1989 break; 1990 default: 1991 return -ERANGE; 1992 } 1993 1994 memcpy(&pfvf->tstamp, &config, sizeof(config)); 1995 1996 return copy_to_user(ifr->ifr_data, &config, 1997 sizeof(config)) ? -EFAULT : 0; 1998 } 1999 2000 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2001 { 2002 struct otx2_nic *pfvf = netdev_priv(netdev); 2003 struct hwtstamp_config *cfg = &pfvf->tstamp; 2004 2005 switch (cmd) { 2006 case SIOCSHWTSTAMP: 2007 return otx2_config_hwtstamp(netdev, req); 2008 case SIOCGHWTSTAMP: 2009 return copy_to_user(req->ifr_data, cfg, 2010 sizeof(*cfg)) ? -EFAULT : 0; 2011 default: 2012 return -EOPNOTSUPP; 2013 } 2014 } 2015 2016 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2017 { 2018 struct npc_install_flow_req *req; 2019 int err; 2020 2021 mutex_lock(&pf->mbox.lock); 2022 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2023 if (!req) { 2024 err = -ENOMEM; 2025 goto out; 2026 } 2027 2028 ether_addr_copy(req->packet.dmac, mac); 2029 eth_broadcast_addr((u8 *)&req->mask.dmac); 2030 req->features = BIT_ULL(NPC_DMAC); 2031 req->channel = pf->hw.rx_chan_base; 2032 req->intf = NIX_INTF_RX; 2033 req->default_rule = 1; 2034 req->append = 1; 2035 req->vf = vf + 1; 2036 req->op = NIX_RX_ACTION_DEFAULT; 2037 2038 err = otx2_sync_mbox_msg(&pf->mbox); 2039 out: 2040 mutex_unlock(&pf->mbox.lock); 2041 return err; 2042 } 2043 2044 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2045 { 2046 struct otx2_nic *pf = netdev_priv(netdev); 2047 struct pci_dev *pdev = pf->pdev; 2048 struct otx2_vf_config *config; 2049 int ret; 2050 2051 if (!netif_running(netdev)) 2052 return -EAGAIN; 2053 2054 if (vf >= pf->total_vfs) 2055 return -EINVAL; 2056 2057 if (!is_valid_ether_addr(mac)) 2058 return -EINVAL; 2059 2060 config = &pf->vf_configs[vf]; 2061 ether_addr_copy(config->mac, mac); 2062 2063 ret = otx2_do_set_vf_mac(pf, vf, mac); 2064 if (ret == 0) 2065 dev_info(&pdev->dev, 2066 "Load/Reload VF driver\n"); 2067 2068 return ret; 2069 } 2070 2071 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2072 __be16 proto) 2073 { 2074 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2075 struct nix_vtag_config_rsp *vtag_rsp; 2076 struct npc_delete_flow_req *del_req; 2077 struct nix_vtag_config *vtag_req; 2078 struct npc_install_flow_req *req; 2079 struct otx2_vf_config *config; 2080 int err = 0; 2081 u32 idx; 2082 2083 config = &pf->vf_configs[vf]; 2084 2085 if (!vlan && !config->vlan) 2086 goto out; 2087 2088 mutex_lock(&pf->mbox.lock); 2089 2090 /* free old tx vtag entry */ 2091 if (config->vlan) { 2092 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2093 if (!vtag_req) { 2094 err = -ENOMEM; 2095 goto out; 2096 } 2097 vtag_req->cfg_type = 0; 2098 vtag_req->tx.free_vtag0 = 1; 2099 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2100 2101 err = otx2_sync_mbox_msg(&pf->mbox); 2102 if (err) 2103 goto out; 2104 } 2105 2106 if (!vlan && config->vlan) { 2107 /* rx */ 2108 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2109 if (!del_req) { 2110 err = -ENOMEM; 2111 goto out; 2112 } 2113 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2114 del_req->entry = 2115 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2116 err = otx2_sync_mbox_msg(&pf->mbox); 2117 if (err) 2118 goto out; 2119 2120 /* tx */ 2121 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2122 if (!del_req) { 2123 err = -ENOMEM; 2124 goto out; 2125 } 2126 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2127 del_req->entry = 2128 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2129 err = otx2_sync_mbox_msg(&pf->mbox); 2130 2131 goto out; 2132 } 2133 2134 /* rx */ 2135 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2136 if (!req) { 2137 err = -ENOMEM; 2138 goto out; 2139 } 2140 2141 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2142 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2143 req->packet.vlan_tci = htons(vlan); 2144 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2145 /* af fills the destination mac addr */ 2146 eth_broadcast_addr((u8 *)&req->mask.dmac); 2147 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2148 req->channel = pf->hw.rx_chan_base; 2149 req->intf = NIX_INTF_RX; 2150 req->vf = vf + 1; 2151 req->op = NIX_RX_ACTION_DEFAULT; 2152 req->vtag0_valid = true; 2153 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2154 req->set_cntr = 1; 2155 2156 err = otx2_sync_mbox_msg(&pf->mbox); 2157 if (err) 2158 goto out; 2159 2160 /* tx */ 2161 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2162 if (!vtag_req) { 2163 err = -ENOMEM; 2164 goto out; 2165 } 2166 2167 /* configure tx vtag params */ 2168 vtag_req->vtag_size = VTAGSIZE_T4; 2169 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2170 vtag_req->tx.cfg_vtag0 = 1; 2171 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2172 2173 err = otx2_sync_mbox_msg(&pf->mbox); 2174 if (err) 2175 goto out; 2176 2177 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2178 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2179 if (IS_ERR(vtag_rsp)) { 2180 err = PTR_ERR(vtag_rsp); 2181 goto out; 2182 } 2183 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2184 2185 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2186 if (!req) { 2187 err = -ENOMEM; 2188 goto out; 2189 } 2190 2191 eth_zero_addr((u8 *)&req->mask.dmac); 2192 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2193 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2194 req->features = BIT_ULL(NPC_DMAC); 2195 req->channel = pf->hw.tx_chan_base; 2196 req->intf = NIX_INTF_TX; 2197 req->vf = vf + 1; 2198 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2199 req->vtag0_def = vtag_rsp->vtag0_idx; 2200 req->vtag0_op = VTAG_INSERT; 2201 req->set_cntr = 1; 2202 2203 err = otx2_sync_mbox_msg(&pf->mbox); 2204 out: 2205 config->vlan = vlan; 2206 mutex_unlock(&pf->mbox.lock); 2207 return err; 2208 } 2209 2210 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2211 __be16 proto) 2212 { 2213 struct otx2_nic *pf = netdev_priv(netdev); 2214 struct pci_dev *pdev = pf->pdev; 2215 2216 if (!netif_running(netdev)) 2217 return -EAGAIN; 2218 2219 if (vf >= pci_num_vf(pdev)) 2220 return -EINVAL; 2221 2222 /* qos is currently unsupported */ 2223 if (vlan >= VLAN_N_VID || qos) 2224 return -EINVAL; 2225 2226 if (proto != htons(ETH_P_8021Q)) 2227 return -EPROTONOSUPPORT; 2228 2229 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2230 return -EOPNOTSUPP; 2231 2232 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2233 } 2234 2235 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2236 struct ifla_vf_info *ivi) 2237 { 2238 struct otx2_nic *pf = netdev_priv(netdev); 2239 struct pci_dev *pdev = pf->pdev; 2240 struct otx2_vf_config *config; 2241 2242 if (!netif_running(netdev)) 2243 return -EAGAIN; 2244 2245 if (vf >= pci_num_vf(pdev)) 2246 return -EINVAL; 2247 2248 config = &pf->vf_configs[vf]; 2249 ivi->vf = vf; 2250 ether_addr_copy(ivi->mac, config->mac); 2251 ivi->vlan = config->vlan; 2252 ivi->trusted = config->trusted; 2253 2254 return 0; 2255 } 2256 2257 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2258 int req_perm) 2259 { 2260 struct set_vf_perm *req; 2261 int rc; 2262 2263 mutex_lock(&pf->mbox.lock); 2264 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2265 if (!req) { 2266 rc = -ENOMEM; 2267 goto out; 2268 } 2269 2270 /* Let AF reset VF permissions as sriov is disabled */ 2271 if (req_perm == OTX2_RESET_VF_PERM) { 2272 req->flags |= RESET_VF_PERM; 2273 } else if (req_perm == OTX2_TRUSTED_VF) { 2274 if (pf->vf_configs[vf].trusted) 2275 req->flags |= VF_TRUSTED; 2276 } 2277 2278 req->vf = vf; 2279 rc = otx2_sync_mbox_msg(&pf->mbox); 2280 out: 2281 mutex_unlock(&pf->mbox.lock); 2282 return rc; 2283 } 2284 2285 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2286 bool enable) 2287 { 2288 struct otx2_nic *pf = netdev_priv(netdev); 2289 struct pci_dev *pdev = pf->pdev; 2290 int rc; 2291 2292 if (vf >= pci_num_vf(pdev)) 2293 return -EINVAL; 2294 2295 if (pf->vf_configs[vf].trusted == enable) 2296 return 0; 2297 2298 pf->vf_configs[vf].trusted = enable; 2299 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2300 2301 if (rc) 2302 pf->vf_configs[vf].trusted = !enable; 2303 else 2304 netdev_info(pf->netdev, "VF %d is %strusted\n", 2305 vf, enable ? "" : "not "); 2306 return rc; 2307 } 2308 2309 static const struct net_device_ops otx2_netdev_ops = { 2310 .ndo_open = otx2_open, 2311 .ndo_stop = otx2_stop, 2312 .ndo_start_xmit = otx2_xmit, 2313 .ndo_fix_features = otx2_fix_features, 2314 .ndo_set_mac_address = otx2_set_mac_address, 2315 .ndo_change_mtu = otx2_change_mtu, 2316 .ndo_set_rx_mode = otx2_set_rx_mode, 2317 .ndo_set_features = otx2_set_features, 2318 .ndo_tx_timeout = otx2_tx_timeout, 2319 .ndo_get_stats64 = otx2_get_stats64, 2320 .ndo_do_ioctl = otx2_ioctl, 2321 .ndo_set_vf_mac = otx2_set_vf_mac, 2322 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2323 .ndo_get_vf_config = otx2_get_vf_config, 2324 .ndo_setup_tc = otx2_setup_tc, 2325 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2326 }; 2327 2328 static int otx2_wq_init(struct otx2_nic *pf) 2329 { 2330 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2331 if (!pf->otx2_wq) 2332 return -ENOMEM; 2333 2334 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode); 2335 INIT_WORK(&pf->reset_task, otx2_reset_task); 2336 return 0; 2337 } 2338 2339 static int otx2_check_pf_usable(struct otx2_nic *nic) 2340 { 2341 u64 rev; 2342 2343 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2344 rev = (rev >> 12) & 0xFF; 2345 /* Check if AF has setup revision for RVUM block, 2346 * otherwise this driver probe should be deferred 2347 * until AF driver comes up. 2348 */ 2349 if (!rev) { 2350 dev_warn(nic->dev, 2351 "AF is not initialized, deferring probe\n"); 2352 return -EPROBE_DEFER; 2353 } 2354 return 0; 2355 } 2356 2357 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2358 { 2359 struct otx2_hw *hw = &pf->hw; 2360 int num_vec, err; 2361 2362 /* NPA interrupts are inot registered, so alloc only 2363 * upto NIX vector offset. 2364 */ 2365 num_vec = hw->nix_msixoff; 2366 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2367 2368 otx2_disable_mbox_intr(pf); 2369 pci_free_irq_vectors(hw->pdev); 2370 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2371 if (err < 0) { 2372 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2373 __func__, num_vec); 2374 return err; 2375 } 2376 2377 return otx2_register_mbox_intr(pf, false); 2378 } 2379 2380 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2381 { 2382 int i; 2383 2384 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2385 sizeof(struct otx2_vf_config), 2386 GFP_KERNEL); 2387 if (!pf->vf_configs) 2388 return -ENOMEM; 2389 2390 for (i = 0; i < pf->total_vfs; i++) { 2391 pf->vf_configs[i].pf = pf; 2392 pf->vf_configs[i].intf_down = true; 2393 pf->vf_configs[i].trusted = false; 2394 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2395 otx2_vf_link_event_task); 2396 } 2397 2398 return 0; 2399 } 2400 2401 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2402 { 2403 int i; 2404 2405 if (!pf->vf_configs) 2406 return; 2407 2408 for (i = 0; i < pf->total_vfs; i++) { 2409 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2410 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2411 } 2412 } 2413 2414 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2415 { 2416 struct device *dev = &pdev->dev; 2417 struct net_device *netdev; 2418 struct otx2_nic *pf; 2419 struct otx2_hw *hw; 2420 int err, qcount; 2421 int num_vec; 2422 2423 err = pcim_enable_device(pdev); 2424 if (err) { 2425 dev_err(dev, "Failed to enable PCI device\n"); 2426 return err; 2427 } 2428 2429 err = pci_request_regions(pdev, DRV_NAME); 2430 if (err) { 2431 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2432 return err; 2433 } 2434 2435 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2436 if (err) { 2437 dev_err(dev, "DMA mask config failed, abort\n"); 2438 goto err_release_regions; 2439 } 2440 2441 pci_set_master(pdev); 2442 2443 /* Set number of queues */ 2444 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2445 2446 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2447 if (!netdev) { 2448 err = -ENOMEM; 2449 goto err_release_regions; 2450 } 2451 2452 pci_set_drvdata(pdev, netdev); 2453 SET_NETDEV_DEV(netdev, &pdev->dev); 2454 pf = netdev_priv(netdev); 2455 pf->netdev = netdev; 2456 pf->pdev = pdev; 2457 pf->dev = dev; 2458 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2459 pf->flags |= OTX2_FLAG_INTF_DOWN; 2460 2461 hw = &pf->hw; 2462 hw->pdev = pdev; 2463 hw->rx_queues = qcount; 2464 hw->tx_queues = qcount; 2465 hw->max_queues = qcount; 2466 2467 num_vec = pci_msix_vec_count(pdev); 2468 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2469 GFP_KERNEL); 2470 if (!hw->irq_name) { 2471 err = -ENOMEM; 2472 goto err_free_netdev; 2473 } 2474 2475 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2476 sizeof(cpumask_var_t), GFP_KERNEL); 2477 if (!hw->affinity_mask) { 2478 err = -ENOMEM; 2479 goto err_free_netdev; 2480 } 2481 2482 /* Map CSRs */ 2483 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2484 if (!pf->reg_base) { 2485 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2486 err = -ENOMEM; 2487 goto err_free_netdev; 2488 } 2489 2490 err = otx2_check_pf_usable(pf); 2491 if (err) 2492 goto err_free_netdev; 2493 2494 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2495 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2496 if (err < 0) { 2497 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2498 __func__, num_vec); 2499 goto err_free_netdev; 2500 } 2501 2502 otx2_setup_dev_hw_settings(pf); 2503 2504 /* Init PF <=> AF mailbox stuff */ 2505 err = otx2_pfaf_mbox_init(pf); 2506 if (err) 2507 goto err_free_irq_vectors; 2508 2509 /* Register mailbox interrupt */ 2510 err = otx2_register_mbox_intr(pf, true); 2511 if (err) 2512 goto err_mbox_destroy; 2513 2514 /* Request AF to attach NPA and NIX LFs to this PF. 2515 * NIX and NPA LFs are needed for this PF to function as a NIC. 2516 */ 2517 err = otx2_attach_npa_nix(pf); 2518 if (err) 2519 goto err_disable_mbox_intr; 2520 2521 err = otx2_realloc_msix_vectors(pf); 2522 if (err) 2523 goto err_detach_rsrc; 2524 2525 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2526 if (err) 2527 goto err_detach_rsrc; 2528 2529 err = cn10k_pf_lmtst_init(pf); 2530 if (err) 2531 goto err_detach_rsrc; 2532 2533 /* Assign default mac address */ 2534 otx2_get_mac_from_af(netdev); 2535 2536 /* Don't check for error. Proceed without ptp */ 2537 otx2_ptp_init(pf); 2538 2539 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2540 * HW allocates buffer pointer from stack and uses it for DMA'ing 2541 * ingress packet. In some scenarios HW can free back allocated buffer 2542 * pointers to pool. This makes it impossible for SW to maintain a 2543 * parallel list where physical addresses of buffer pointers (IOVAs) 2544 * given to HW can be saved for later reference. 2545 * 2546 * So the only way to convert Rx packet's buffer address is to use 2547 * IOMMU's iova_to_phys() handler which translates the address by 2548 * walking through the translation tables. 2549 */ 2550 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2551 2552 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2553 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2554 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2555 NETIF_F_GSO_UDP_L4); 2556 netdev->features |= netdev->hw_features; 2557 2558 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2559 2560 err = otx2_mcam_flow_init(pf); 2561 if (err) 2562 goto err_ptp_destroy; 2563 2564 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2565 netdev->hw_features |= NETIF_F_NTUPLE; 2566 2567 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2568 netdev->priv_flags |= IFF_UNICAST_FLT; 2569 2570 /* Support TSO on tag interface */ 2571 netdev->vlan_features |= netdev->features; 2572 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2573 NETIF_F_HW_VLAN_STAG_TX; 2574 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2575 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2576 NETIF_F_HW_VLAN_STAG_RX; 2577 netdev->features |= netdev->hw_features; 2578 2579 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2580 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2581 netdev->hw_features |= NETIF_F_HW_TC; 2582 2583 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2584 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2585 2586 netdev->netdev_ops = &otx2_netdev_ops; 2587 2588 /* MTU range: 64 - 9190 */ 2589 netdev->min_mtu = OTX2_MIN_MTU; 2590 netdev->max_mtu = otx2_get_max_mtu(pf); 2591 2592 err = register_netdev(netdev); 2593 if (err) { 2594 dev_err(dev, "Failed to register netdevice\n"); 2595 goto err_del_mcam_entries; 2596 } 2597 2598 err = otx2_wq_init(pf); 2599 if (err) 2600 goto err_unreg_netdev; 2601 2602 otx2_set_ethtool_ops(netdev); 2603 2604 err = otx2_init_tc(pf); 2605 if (err) 2606 goto err_mcam_flow_del; 2607 2608 /* Initialize SR-IOV resources */ 2609 err = otx2_sriov_vfcfg_init(pf); 2610 if (err) 2611 goto err_pf_sriov_init; 2612 2613 /* Enable link notifications */ 2614 otx2_cgx_config_linkevents(pf, true); 2615 2616 /* Enable pause frames by default */ 2617 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2618 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2619 2620 return 0; 2621 2622 err_pf_sriov_init: 2623 otx2_shutdown_tc(pf); 2624 err_mcam_flow_del: 2625 otx2_mcam_flow_del(pf); 2626 err_unreg_netdev: 2627 unregister_netdev(netdev); 2628 err_del_mcam_entries: 2629 otx2_mcam_flow_del(pf); 2630 err_ptp_destroy: 2631 otx2_ptp_destroy(pf); 2632 err_detach_rsrc: 2633 if (hw->lmt_base) 2634 iounmap(hw->lmt_base); 2635 otx2_detach_resources(&pf->mbox); 2636 err_disable_mbox_intr: 2637 otx2_disable_mbox_intr(pf); 2638 err_mbox_destroy: 2639 otx2_pfaf_mbox_destroy(pf); 2640 err_free_irq_vectors: 2641 pci_free_irq_vectors(hw->pdev); 2642 err_free_netdev: 2643 pci_set_drvdata(pdev, NULL); 2644 free_netdev(netdev); 2645 err_release_regions: 2646 pci_release_regions(pdev); 2647 return err; 2648 } 2649 2650 static void otx2_vf_link_event_task(struct work_struct *work) 2651 { 2652 struct otx2_vf_config *config; 2653 struct cgx_link_info_msg *req; 2654 struct mbox_msghdr *msghdr; 2655 struct otx2_nic *pf; 2656 int vf_idx; 2657 2658 config = container_of(work, struct otx2_vf_config, 2659 link_event_work.work); 2660 vf_idx = config - config->pf->vf_configs; 2661 pf = config->pf; 2662 2663 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2664 sizeof(*req), sizeof(struct msg_rsp)); 2665 if (!msghdr) { 2666 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2667 return; 2668 } 2669 2670 req = (struct cgx_link_info_msg *)msghdr; 2671 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2672 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2673 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2674 2675 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2676 } 2677 2678 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2679 { 2680 struct net_device *netdev = pci_get_drvdata(pdev); 2681 struct otx2_nic *pf = netdev_priv(netdev); 2682 int ret; 2683 2684 /* Init PF <=> VF mailbox stuff */ 2685 ret = otx2_pfvf_mbox_init(pf, numvfs); 2686 if (ret) 2687 return ret; 2688 2689 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2690 if (ret) 2691 goto free_mbox; 2692 2693 ret = otx2_pf_flr_init(pf, numvfs); 2694 if (ret) 2695 goto free_intr; 2696 2697 ret = otx2_register_flr_me_intr(pf, numvfs); 2698 if (ret) 2699 goto free_flr; 2700 2701 ret = pci_enable_sriov(pdev, numvfs); 2702 if (ret) 2703 goto free_flr_intr; 2704 2705 return numvfs; 2706 free_flr_intr: 2707 otx2_disable_flr_me_intr(pf); 2708 free_flr: 2709 otx2_flr_wq_destroy(pf); 2710 free_intr: 2711 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2712 free_mbox: 2713 otx2_pfvf_mbox_destroy(pf); 2714 return ret; 2715 } 2716 2717 static int otx2_sriov_disable(struct pci_dev *pdev) 2718 { 2719 struct net_device *netdev = pci_get_drvdata(pdev); 2720 struct otx2_nic *pf = netdev_priv(netdev); 2721 int numvfs = pci_num_vf(pdev); 2722 2723 if (!numvfs) 2724 return 0; 2725 2726 pci_disable_sriov(pdev); 2727 2728 otx2_disable_flr_me_intr(pf); 2729 otx2_flr_wq_destroy(pf); 2730 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2731 otx2_pfvf_mbox_destroy(pf); 2732 2733 return 0; 2734 } 2735 2736 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2737 { 2738 if (numvfs == 0) 2739 return otx2_sriov_disable(pdev); 2740 else 2741 return otx2_sriov_enable(pdev, numvfs); 2742 } 2743 2744 static void otx2_remove(struct pci_dev *pdev) 2745 { 2746 struct net_device *netdev = pci_get_drvdata(pdev); 2747 struct otx2_nic *pf; 2748 2749 if (!netdev) 2750 return; 2751 2752 pf = netdev_priv(netdev); 2753 2754 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2755 2756 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2757 otx2_config_hw_tx_tstamp(pf, false); 2758 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2759 otx2_config_hw_rx_tstamp(pf, false); 2760 2761 cancel_work_sync(&pf->reset_task); 2762 /* Disable link notifications */ 2763 otx2_cgx_config_linkevents(pf, false); 2764 2765 unregister_netdev(netdev); 2766 otx2_sriov_disable(pf->pdev); 2767 otx2_sriov_vfcfg_cleanup(pf); 2768 if (pf->otx2_wq) 2769 destroy_workqueue(pf->otx2_wq); 2770 2771 otx2_ptp_destroy(pf); 2772 otx2_mcam_flow_del(pf); 2773 otx2_shutdown_tc(pf); 2774 otx2_detach_resources(&pf->mbox); 2775 if (pf->hw.lmt_base) 2776 iounmap(pf->hw.lmt_base); 2777 2778 otx2_disable_mbox_intr(pf); 2779 otx2_pfaf_mbox_destroy(pf); 2780 pci_free_irq_vectors(pf->pdev); 2781 pci_set_drvdata(pdev, NULL); 2782 free_netdev(netdev); 2783 2784 pci_release_regions(pdev); 2785 } 2786 2787 static struct pci_driver otx2_pf_driver = { 2788 .name = DRV_NAME, 2789 .id_table = otx2_pf_id_table, 2790 .probe = otx2_probe, 2791 .shutdown = otx2_remove, 2792 .remove = otx2_remove, 2793 .sriov_configure = otx2_sriov_configure 2794 }; 2795 2796 static int __init otx2_rvupf_init_module(void) 2797 { 2798 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2799 2800 return pci_register_driver(&otx2_pf_driver); 2801 } 2802 2803 static void __exit otx2_rvupf_cleanup_module(void) 2804 { 2805 pci_unregister_driver(&otx2_pf_driver); 2806 } 2807 2808 module_init(otx2_rvupf_init_module); 2809 module_exit(otx2_rvupf_cleanup_module); 2810