1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 19 #include "otx2_reg.h" 20 #include "otx2_common.h" 21 #include "otx2_txrx.h" 22 #include "otx2_struct.h" 23 #include "otx2_ptp.h" 24 #include "cn10k.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "rvu_nicpf" 28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 static void otx2_vf_link_event_task(struct work_struct *work); 42 43 enum { 44 TYPE_PFAF, 45 TYPE_PFVF, 46 }; 47 48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 50 51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 52 { 53 struct otx2_nic *pf = netdev_priv(netdev); 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 59 netdev->mtu); 60 return -EINVAL; 61 } 62 if (if_up) 63 otx2_stop(netdev); 64 65 netdev_info(netdev, "Changing MTU from %d to %d\n", 66 netdev->mtu, new_mtu); 67 netdev->mtu = new_mtu; 68 69 if (if_up) 70 err = otx2_open(netdev); 71 72 return err; 73 } 74 75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 76 { 77 int irq, vfs = pf->total_vfs; 78 79 /* Disable VFs ME interrupts */ 80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 82 free_irq(irq, pf); 83 84 /* Disable VFs FLR interrupts */ 85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 87 free_irq(irq, pf); 88 89 if (vfs <= 64) 90 return; 91 92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 94 free_irq(irq, pf); 95 96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 98 free_irq(irq, pf); 99 } 100 101 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 102 { 103 if (!pf->flr_wq) 104 return; 105 destroy_workqueue(pf->flr_wq); 106 pf->flr_wq = NULL; 107 devm_kfree(pf->dev, pf->flr_wrk); 108 } 109 110 static void otx2_flr_handler(struct work_struct *work) 111 { 112 struct flr_work *flrwork = container_of(work, struct flr_work, work); 113 struct otx2_nic *pf = flrwork->pf; 114 struct mbox *mbox = &pf->mbox; 115 struct msg_req *req; 116 int vf, reg = 0; 117 118 vf = flrwork - pf->flr_wrk; 119 120 mutex_lock(&mbox->lock); 121 req = otx2_mbox_alloc_msg_vf_flr(mbox); 122 if (!req) { 123 mutex_unlock(&mbox->lock); 124 return; 125 } 126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 128 129 if (!otx2_sync_mbox_msg(&pf->mbox)) { 130 if (vf >= 64) { 131 reg = 1; 132 vf = vf - 64; 133 } 134 /* clear transcation pending bit */ 135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 137 } 138 139 mutex_unlock(&mbox->lock); 140 } 141 142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 143 { 144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 145 int reg, dev, vf, start_vf, num_reg = 1; 146 u64 intr; 147 148 if (pf->total_vfs > 64) 149 num_reg = 2; 150 151 for (reg = 0; reg < num_reg; reg++) { 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 153 if (!intr) 154 continue; 155 start_vf = 64 * reg; 156 for (vf = 0; vf < 64; vf++) { 157 if (!(intr & BIT_ULL(vf))) 158 continue; 159 dev = vf + start_vf; 160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 161 /* Clear interrupt */ 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 163 /* Disable the interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 165 BIT_ULL(vf)); 166 } 167 } 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 172 { 173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 174 int vf, reg, num_reg = 1; 175 u64 intr; 176 177 if (pf->total_vfs > 64) 178 num_reg = 2; 179 180 for (reg = 0; reg < num_reg; reg++) { 181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 182 if (!intr) 183 continue; 184 for (vf = 0; vf < 64; vf++) { 185 if (!(intr & BIT_ULL(vf))) 186 continue; 187 /* clear trpend bit */ 188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 189 /* clear interrupt */ 190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 191 } 192 } 193 return IRQ_HANDLED; 194 } 195 196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 197 { 198 struct otx2_hw *hw = &pf->hw; 199 char *irq_name; 200 int ret; 201 202 /* Register ME interrupt handler*/ 203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 206 otx2_pf_me_intr_handler, 0, irq_name, pf); 207 if (ret) { 208 dev_err(pf->dev, 209 "RVUPF: IRQ registration failed for ME0\n"); 210 } 211 212 /* Register FLR interrupt handler */ 213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 216 otx2_pf_flr_intr_handler, 0, irq_name, pf); 217 if (ret) { 218 dev_err(pf->dev, 219 "RVUPF: IRQ registration failed for FLR0\n"); 220 return ret; 221 } 222 223 if (numvfs > 64) { 224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 226 rvu_get_pf(pf->pcifunc)); 227 ret = request_irq(pci_irq_vector 228 (pf->pdev, RVU_PF_INT_VEC_VFME1), 229 otx2_pf_me_intr_handler, 0, irq_name, pf); 230 if (ret) { 231 dev_err(pf->dev, 232 "RVUPF: IRQ registration failed for ME1\n"); 233 } 234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 236 rvu_get_pf(pf->pcifunc)); 237 ret = request_irq(pci_irq_vector 238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 239 otx2_pf_flr_intr_handler, 0, irq_name, pf); 240 if (ret) { 241 dev_err(pf->dev, 242 "RVUPF: IRQ registration failed for FLR1\n"); 243 return ret; 244 } 245 } 246 247 /* Enable ME interrupt for all VFs*/ 248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 250 251 /* Enable FLR interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 if (numvfs > 64) { 256 numvfs -= 64; 257 258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 260 INTR_MASK(numvfs)); 261 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 } 266 return 0; 267 } 268 269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 270 { 271 int vf; 272 273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 274 WQ_UNBOUND | WQ_HIGHPRI, 1); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 /* Error code -EIO indicate there is a communication failure 398 * to the AF. Rest of the error codes indicate that AF processed 399 * VF messages and set the error codes in response messages 400 * (if any) so simply forward responses to VF. 401 */ 402 if (err == -EIO) { 403 dev_warn(pf->dev, 404 "AF not responding to VF%d messages\n", vf); 405 /* restore PF mbase and exit */ 406 dst_mdev->mbase = pf->mbox.bbuf_base; 407 mutex_unlock(&pf->mbox.lock); 408 return err; 409 } 410 /* At this point, all the VF messages sent to AF are acked 411 * with proper responses and responses are copied to VF 412 * mailbox hence raise interrupt to VF. 413 */ 414 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 415 dst_mbox->mbox.rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 419 pf->mbox.bbuf_base, vf); 420 mutex_unlock(&pf->mbox.lock); 421 } else if (dir == MBOX_DIR_PFVF_UP) { 422 src_mdev = &src_mbox->dev[0]; 423 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 424 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 425 src_mbox->rx_start); 426 req_hdr->num_msgs = num_msgs; 427 428 dst_mbox = &pf->mbox_pfvf[0]; 429 dst_size = dst_mbox->mbox_up.tx_size - 430 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 431 /* Check if msgs fit into destination area */ 432 if (mbox_hdr->msg_size > dst_size) 433 return -EINVAL; 434 435 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 436 dst_mdev->mbase = src_mdev->mbase; 437 dst_mdev->msg_size = mbox_hdr->msg_size; 438 dst_mdev->num_msgs = mbox_hdr->num_msgs; 439 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 440 if (err) { 441 dev_warn(pf->dev, 442 "VF%d is not responding to mailbox\n", vf); 443 return err; 444 } 445 } else if (dir == MBOX_DIR_VFPF_UP) { 446 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 447 src_mbox->rx_start); 448 req_hdr->num_msgs = num_msgs; 449 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 450 &pf->mbox.mbox_up, 451 pf->mbox_pfvf[vf].bbuf_base, 452 0); 453 } 454 455 return 0; 456 } 457 458 static void otx2_pfvf_mbox_handler(struct work_struct *work) 459 { 460 struct mbox_msghdr *msg = NULL; 461 int offset, vf_idx, id, err; 462 struct otx2_mbox_dev *mdev; 463 struct mbox_hdr *req_hdr; 464 struct otx2_mbox *mbox; 465 struct mbox *vf_mbox; 466 struct otx2_nic *pf; 467 468 vf_mbox = container_of(work, struct mbox, mbox_wrk); 469 pf = vf_mbox->pfvf; 470 vf_idx = vf_mbox - pf->mbox_pfvf; 471 472 mbox = &pf->mbox_pfvf[0].mbox; 473 mdev = &mbox->dev[vf_idx]; 474 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 475 476 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 477 478 for (id = 0; id < vf_mbox->num_msgs; id++) { 479 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 480 offset); 481 482 if (msg->sig != OTX2_MBOX_REQ_SIG) 483 goto inval_msg; 484 485 /* Set VF's number in each of the msg */ 486 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 487 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 488 offset = msg->next_msgoff; 489 } 490 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 491 vf_mbox->num_msgs); 492 if (err) 493 goto inval_msg; 494 return; 495 496 inval_msg: 497 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 498 otx2_mbox_msg_send(mbox, vf_idx); 499 } 500 501 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 502 { 503 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 504 struct otx2_nic *pf = vf_mbox->pfvf; 505 struct otx2_mbox_dev *mdev; 506 int offset, id, vf_idx = 0; 507 struct mbox_hdr *rsp_hdr; 508 struct mbox_msghdr *msg; 509 struct otx2_mbox *mbox; 510 511 vf_idx = vf_mbox - pf->mbox_pfvf; 512 mbox = &pf->mbox_pfvf[0].mbox_up; 513 mdev = &mbox->dev[vf_idx]; 514 515 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 516 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 517 518 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 519 msg = mdev->mbase + offset; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(pf->dev, 523 "Mbox msg with unknown ID 0x%x\n", msg->id); 524 goto end; 525 } 526 527 if (msg->sig != OTX2_MBOX_RSP_SIG) { 528 dev_err(pf->dev, 529 "Mbox msg with wrong signature %x, ID 0x%x\n", 530 msg->sig, msg->id); 531 goto end; 532 } 533 534 switch (msg->id) { 535 case MBOX_MSG_CGX_LINK_EVENT: 536 break; 537 default: 538 if (msg->rc) 539 dev_err(pf->dev, 540 "Mbox msg response has err %d, ID 0x%x\n", 541 msg->rc, msg->id); 542 break; 543 } 544 545 end: 546 offset = mbox->rx_start + msg->next_msgoff; 547 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 548 __otx2_mbox_reset(mbox, 0); 549 mdev->msgs_acked++; 550 } 551 } 552 553 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 554 { 555 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 556 int vfs = pf->total_vfs; 557 struct mbox *mbox; 558 u64 intr; 559 560 mbox = pf->mbox_pfvf; 561 /* Handle VF interrupts */ 562 if (vfs > 64) { 563 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 564 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 566 TYPE_PFVF); 567 vfs -= 64; 568 } 569 570 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 571 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 572 573 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 574 575 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 576 577 return IRQ_HANDLED; 578 } 579 580 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 581 { 582 void __iomem *hwbase; 583 struct mbox *mbox; 584 int err, vf; 585 u64 base; 586 587 if (!numvfs) 588 return -EINVAL; 589 590 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 591 sizeof(struct mbox), GFP_KERNEL); 592 if (!pf->mbox_pfvf) 593 return -ENOMEM; 594 595 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 596 WQ_UNBOUND | WQ_HIGHPRI | 597 WQ_MEM_RECLAIM, 1); 598 if (!pf->mbox_pfvf_wq) 599 return -ENOMEM; 600 601 /* On CN10K platform, PF <-> VF mailbox region follows after 602 * PF <-> AF mailbox region. 603 */ 604 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 605 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 606 MBOX_SIZE; 607 else 608 base = readq((void __iomem *)((u64)pf->reg_base + 609 RVU_PF_VF_BAR4_ADDR)); 610 611 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 612 if (!hwbase) { 613 err = -ENOMEM; 614 goto free_wq; 615 } 616 617 mbox = &pf->mbox_pfvf[0]; 618 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF, numvfs); 620 if (err) 621 goto free_iomem; 622 623 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 624 MBOX_DIR_PFVF_UP, numvfs); 625 if (err) 626 goto free_iomem; 627 628 for (vf = 0; vf < numvfs; vf++) { 629 mbox->pfvf = pf; 630 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 631 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 632 mbox++; 633 } 634 635 return 0; 636 637 free_iomem: 638 if (hwbase) 639 iounmap(hwbase); 640 free_wq: 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 return err; 643 } 644 645 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 646 { 647 struct mbox *mbox = &pf->mbox_pfvf[0]; 648 649 if (!mbox) 650 return; 651 652 if (pf->mbox_pfvf_wq) { 653 destroy_workqueue(pf->mbox_pfvf_wq); 654 pf->mbox_pfvf_wq = NULL; 655 } 656 657 if (mbox->mbox.hwbase) 658 iounmap(mbox->mbox.hwbase); 659 660 otx2_mbox_destroy(&mbox->mbox); 661 } 662 663 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 664 { 665 /* Clear PF <=> VF mailbox IRQ */ 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 669 /* Enable PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 671 if (numvfs > 64) { 672 numvfs -= 64; 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 674 INTR_MASK(numvfs)); 675 } 676 } 677 678 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 679 { 680 int vector; 681 682 /* Disable PF <=> VF mailbox IRQ */ 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 685 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 688 free_irq(vector, pf); 689 690 if (numvfs > 64) { 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 692 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 693 free_irq(vector, pf); 694 } 695 } 696 697 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 698 { 699 struct otx2_hw *hw = &pf->hw; 700 char *irq_name; 701 int err; 702 703 /* Register MBOX0 interrupt handler */ 704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 705 if (pf->pcifunc) 706 snprintf(irq_name, NAME_SIZE, 707 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 708 else 709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 710 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 711 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 712 if (err) { 713 dev_err(pf->dev, 714 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 715 return err; 716 } 717 718 if (numvfs > 64) { 719 /* Register MBOX1 interrupt handler */ 720 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 721 if (pf->pcifunc) 722 snprintf(irq_name, NAME_SIZE, 723 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 724 else 725 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 726 err = request_irq(pci_irq_vector(pf->pdev, 727 RVU_PF_INT_VEC_VFPF_MBOX1), 728 otx2_pfvf_mbox_intr_handler, 729 0, irq_name, pf); 730 if (err) { 731 dev_err(pf->dev, 732 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 733 return err; 734 } 735 } 736 737 otx2_enable_pfvf_mbox_intr(pf, numvfs); 738 739 return 0; 740 } 741 742 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 743 struct mbox_msghdr *msg) 744 { 745 int devid; 746 747 if (msg->id >= MBOX_MSG_MAX) { 748 dev_err(pf->dev, 749 "Mbox msg with unknown ID 0x%x\n", msg->id); 750 return; 751 } 752 753 if (msg->sig != OTX2_MBOX_RSP_SIG) { 754 dev_err(pf->dev, 755 "Mbox msg with wrong signature %x, ID 0x%x\n", 756 msg->sig, msg->id); 757 return; 758 } 759 760 /* message response heading VF */ 761 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 762 if (devid) { 763 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 764 struct delayed_work *dwork; 765 766 switch (msg->id) { 767 case MBOX_MSG_NIX_LF_START_RX: 768 config->intf_down = false; 769 dwork = &config->link_event_work; 770 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 771 break; 772 case MBOX_MSG_NIX_LF_STOP_RX: 773 config->intf_down = true; 774 break; 775 } 776 777 return; 778 } 779 780 switch (msg->id) { 781 case MBOX_MSG_READY: 782 pf->pcifunc = msg->pcifunc; 783 break; 784 case MBOX_MSG_MSIX_OFFSET: 785 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 786 break; 787 case MBOX_MSG_NPA_LF_ALLOC: 788 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 789 break; 790 case MBOX_MSG_NIX_LF_ALLOC: 791 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 792 break; 793 case MBOX_MSG_NIX_TXSCH_ALLOC: 794 mbox_handler_nix_txsch_alloc(pf, 795 (struct nix_txsch_alloc_rsp *)msg); 796 break; 797 case MBOX_MSG_NIX_BP_ENABLE: 798 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_STATS: 801 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 802 break; 803 case MBOX_MSG_CGX_FEC_STATS: 804 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 805 break; 806 default: 807 if (msg->rc) 808 dev_err(pf->dev, 809 "Mbox msg response has err %d, ID 0x%x\n", 810 msg->rc, msg->id); 811 break; 812 } 813 } 814 815 static void otx2_pfaf_mbox_handler(struct work_struct *work) 816 { 817 struct otx2_mbox_dev *mdev; 818 struct mbox_hdr *rsp_hdr; 819 struct mbox_msghdr *msg; 820 struct otx2_mbox *mbox; 821 struct mbox *af_mbox; 822 struct otx2_nic *pf; 823 int offset, id; 824 825 af_mbox = container_of(work, struct mbox, mbox_wrk); 826 mbox = &af_mbox->mbox; 827 mdev = &mbox->dev[0]; 828 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 829 830 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 831 pf = af_mbox->pfvf; 832 833 for (id = 0; id < af_mbox->num_msgs; id++) { 834 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 835 otx2_process_pfaf_mbox_msg(pf, msg); 836 offset = mbox->rx_start + msg->next_msgoff; 837 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 838 __otx2_mbox_reset(mbox, 0); 839 mdev->msgs_acked++; 840 } 841 842 } 843 844 static void otx2_handle_link_event(struct otx2_nic *pf) 845 { 846 struct cgx_link_user_info *linfo = &pf->linfo; 847 struct net_device *netdev = pf->netdev; 848 849 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 850 linfo->link_up ? "UP" : "DOWN", linfo->speed, 851 linfo->full_duplex ? "Full" : "Half"); 852 if (linfo->link_up) { 853 netif_carrier_on(netdev); 854 netif_tx_start_all_queues(netdev); 855 } else { 856 netif_tx_stop_all_queues(netdev); 857 netif_carrier_off(netdev); 858 } 859 } 860 861 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 862 struct cgx_link_info_msg *msg, 863 struct msg_rsp *rsp) 864 { 865 int i; 866 867 /* Copy the link info sent by AF */ 868 pf->linfo = msg->link_info; 869 870 /* notify VFs about link event */ 871 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 872 struct otx2_vf_config *config = &pf->vf_configs[i]; 873 struct delayed_work *dwork = &config->link_event_work; 874 875 if (config->intf_down) 876 continue; 877 878 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 879 } 880 881 /* interface has not been fully configured yet */ 882 if (pf->flags & OTX2_FLAG_INTF_DOWN) 883 return 0; 884 885 otx2_handle_link_event(pf); 886 return 0; 887 } 888 889 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 890 struct mbox_msghdr *req) 891 { 892 /* Check if valid, if not reply with a invalid msg */ 893 if (req->sig != OTX2_MBOX_REQ_SIG) { 894 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 895 return -ENODEV; 896 } 897 898 switch (req->id) { 899 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 900 case _id: { \ 901 struct _rsp_type *rsp; \ 902 int err; \ 903 \ 904 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 905 &pf->mbox.mbox_up, 0, \ 906 sizeof(struct _rsp_type)); \ 907 if (!rsp) \ 908 return -ENOMEM; \ 909 \ 910 rsp->hdr.id = _id; \ 911 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 912 rsp->hdr.pcifunc = 0; \ 913 rsp->hdr.rc = 0; \ 914 \ 915 err = otx2_mbox_up_handler_ ## _fn_name( \ 916 pf, (struct _req_type *)req, rsp); \ 917 return err; \ 918 } 919 MBOX_UP_CGX_MESSAGES 920 #undef M 921 break; 922 default: 923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 924 return -ENODEV; 925 } 926 return 0; 927 } 928 929 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 930 { 931 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 932 struct otx2_mbox *mbox = &af_mbox->mbox_up; 933 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 934 struct otx2_nic *pf = af_mbox->pfvf; 935 int offset, id, devid = 0; 936 struct mbox_hdr *rsp_hdr; 937 struct mbox_msghdr *msg; 938 939 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 940 941 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 942 943 for (id = 0; id < af_mbox->up_num_msgs; id++) { 944 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 945 946 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 947 /* Skip processing VF's messages */ 948 if (!devid) 949 otx2_process_mbox_msg_up(pf, msg); 950 offset = mbox->rx_start + msg->next_msgoff; 951 } 952 if (devid) { 953 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 954 MBOX_DIR_PFVF_UP, devid - 1, 955 af_mbox->up_num_msgs); 956 return; 957 } 958 959 otx2_mbox_msg_send(mbox, 0); 960 } 961 962 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 963 { 964 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 965 struct mbox *mbox; 966 967 /* Clear the IRQ */ 968 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 969 970 mbox = &pf->mbox; 971 972 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 973 974 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 975 976 return IRQ_HANDLED; 977 } 978 979 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 980 { 981 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 982 983 /* Disable AF => PF mailbox IRQ */ 984 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 985 free_irq(vector, pf); 986 } 987 988 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 989 { 990 struct otx2_hw *hw = &pf->hw; 991 struct msg_req *req; 992 char *irq_name; 993 int err; 994 995 /* Register mailbox interrupt handler */ 996 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 997 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 998 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 999 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1000 if (err) { 1001 dev_err(pf->dev, 1002 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1003 return err; 1004 } 1005 1006 /* Enable mailbox interrupt for msgs coming from AF. 1007 * First clear to avoid spurious interrupts, if any. 1008 */ 1009 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1010 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1011 1012 if (!probe_af) 1013 return 0; 1014 1015 /* Check mailbox communication with AF */ 1016 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1017 if (!req) { 1018 otx2_disable_mbox_intr(pf); 1019 return -ENOMEM; 1020 } 1021 err = otx2_sync_mbox_msg(&pf->mbox); 1022 if (err) { 1023 dev_warn(pf->dev, 1024 "AF not responding to mailbox, deferring probe\n"); 1025 otx2_disable_mbox_intr(pf); 1026 return -EPROBE_DEFER; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1033 { 1034 struct mbox *mbox = &pf->mbox; 1035 1036 if (pf->mbox_wq) { 1037 destroy_workqueue(pf->mbox_wq); 1038 pf->mbox_wq = NULL; 1039 } 1040 1041 if (mbox->mbox.hwbase) 1042 iounmap((void __iomem *)mbox->mbox.hwbase); 1043 1044 otx2_mbox_destroy(&mbox->mbox); 1045 otx2_mbox_destroy(&mbox->mbox_up); 1046 } 1047 1048 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1049 { 1050 struct mbox *mbox = &pf->mbox; 1051 void __iomem *hwbase; 1052 int err; 1053 1054 mbox->pfvf = pf; 1055 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1056 WQ_UNBOUND | WQ_HIGHPRI | 1057 WQ_MEM_RECLAIM, 1); 1058 if (!pf->mbox_wq) 1059 return -ENOMEM; 1060 1061 /* Mailbox is a reserved memory (in RAM) region shared between 1062 * admin function (i.e AF) and this PF, shouldn't be mapped as 1063 * device memory to allow unaligned accesses. 1064 */ 1065 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1066 MBOX_SIZE); 1067 if (!hwbase) { 1068 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1069 err = -ENOMEM; 1070 goto exit; 1071 } 1072 1073 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1074 MBOX_DIR_PFAF, 1); 1075 if (err) 1076 goto exit; 1077 1078 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1079 MBOX_DIR_PFAF_UP, 1); 1080 if (err) 1081 goto exit; 1082 1083 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1084 if (err) 1085 goto exit; 1086 1087 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1088 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1089 mutex_init(&mbox->lock); 1090 1091 return 0; 1092 exit: 1093 otx2_pfaf_mbox_destroy(pf); 1094 return err; 1095 } 1096 1097 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1098 { 1099 struct msg_req *msg; 1100 int err; 1101 1102 mutex_lock(&pf->mbox.lock); 1103 if (enable) 1104 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1105 else 1106 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1107 1108 if (!msg) { 1109 mutex_unlock(&pf->mbox.lock); 1110 return -ENOMEM; 1111 } 1112 1113 err = otx2_sync_mbox_msg(&pf->mbox); 1114 mutex_unlock(&pf->mbox.lock); 1115 return err; 1116 } 1117 1118 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1119 { 1120 struct msg_req *msg; 1121 int err; 1122 1123 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1124 pf->flow_cfg->dmacflt_max_flows)) 1125 netdev_warn(pf->netdev, 1126 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1127 1128 mutex_lock(&pf->mbox.lock); 1129 if (enable) 1130 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1131 else 1132 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1133 1134 if (!msg) { 1135 mutex_unlock(&pf->mbox.lock); 1136 return -ENOMEM; 1137 } 1138 1139 err = otx2_sync_mbox_msg(&pf->mbox); 1140 mutex_unlock(&pf->mbox.lock); 1141 return err; 1142 } 1143 1144 int otx2_set_real_num_queues(struct net_device *netdev, 1145 int tx_queues, int rx_queues) 1146 { 1147 int err; 1148 1149 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1150 if (err) { 1151 netdev_err(netdev, 1152 "Failed to set no of Tx queues: %d\n", tx_queues); 1153 return err; 1154 } 1155 1156 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1157 if (err) 1158 netdev_err(netdev, 1159 "Failed to set no of Rx queues: %d\n", rx_queues); 1160 return err; 1161 } 1162 EXPORT_SYMBOL(otx2_set_real_num_queues); 1163 1164 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1165 { 1166 struct otx2_nic *pf = data; 1167 u64 val, *ptr; 1168 u64 qidx = 0; 1169 1170 /* CQ */ 1171 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1172 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1173 val = otx2_atomic64_add((qidx << 44), ptr); 1174 1175 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1176 (val & NIX_CQERRINT_BITS)); 1177 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1178 continue; 1179 1180 if (val & BIT_ULL(42)) { 1181 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1182 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1183 } else { 1184 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1185 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1186 qidx); 1187 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1188 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1189 qidx); 1190 } 1191 1192 schedule_work(&pf->reset_task); 1193 } 1194 1195 /* SQ */ 1196 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1197 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1198 val = otx2_atomic64_add((qidx << 44), ptr); 1199 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1200 (val & NIX_SQINT_BITS)); 1201 1202 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1203 continue; 1204 1205 if (val & BIT_ULL(42)) { 1206 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1207 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1208 } else { 1209 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1210 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1211 qidx, 1212 otx2_read64(pf, 1213 NIX_LF_SQ_OP_ERR_DBG)); 1214 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1215 BIT_ULL(44)); 1216 } 1217 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1218 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1219 qidx, 1220 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1221 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1222 BIT_ULL(44)); 1223 } 1224 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1225 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1226 qidx, 1227 otx2_read64(pf, 1228 NIX_LF_SEND_ERR_DBG)); 1229 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1230 BIT_ULL(44)); 1231 } 1232 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1233 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1234 qidx); 1235 } 1236 1237 schedule_work(&pf->reset_task); 1238 } 1239 1240 return IRQ_HANDLED; 1241 } 1242 1243 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1244 { 1245 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1246 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1247 int qidx = cq_poll->cint_idx; 1248 1249 /* Disable interrupts. 1250 * 1251 * Completion interrupts behave in a level-triggered interrupt 1252 * fashion, and hence have to be cleared only after it is serviced. 1253 */ 1254 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1255 1256 /* Schedule NAPI */ 1257 pf->napi_events++; 1258 napi_schedule_irqoff(&cq_poll->napi); 1259 1260 return IRQ_HANDLED; 1261 } 1262 1263 static void otx2_disable_napi(struct otx2_nic *pf) 1264 { 1265 struct otx2_qset *qset = &pf->qset; 1266 struct otx2_cq_poll *cq_poll; 1267 int qidx; 1268 1269 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1270 cq_poll = &qset->napi[qidx]; 1271 cancel_work_sync(&cq_poll->dim.work); 1272 napi_disable(&cq_poll->napi); 1273 netif_napi_del(&cq_poll->napi); 1274 } 1275 } 1276 1277 static void otx2_free_cq_res(struct otx2_nic *pf) 1278 { 1279 struct otx2_qset *qset = &pf->qset; 1280 struct otx2_cq_queue *cq; 1281 int qidx; 1282 1283 /* Disable CQs */ 1284 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1285 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1286 cq = &qset->cq[qidx]; 1287 qmem_free(pf->dev, cq->cqe); 1288 } 1289 } 1290 1291 static void otx2_free_sq_res(struct otx2_nic *pf) 1292 { 1293 struct otx2_qset *qset = &pf->qset; 1294 struct otx2_snd_queue *sq; 1295 int qidx; 1296 1297 /* Disable SQs */ 1298 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1299 /* Free SQB pointers */ 1300 otx2_sq_free_sqbs(pf); 1301 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1302 sq = &qset->sq[qidx]; 1303 qmem_free(pf->dev, sq->sqe); 1304 qmem_free(pf->dev, sq->tso_hdrs); 1305 kfree(sq->sg); 1306 kfree(sq->sqb_ptrs); 1307 } 1308 } 1309 1310 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1311 { 1312 int frame_size; 1313 int total_size; 1314 int rbuf_size; 1315 1316 if (pf->hw.rbuf_len) 1317 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1318 1319 /* The data transferred by NIX to memory consists of actual packet 1320 * plus additional data which has timestamp and/or EDSA/HIGIG2 1321 * headers if interface is configured in corresponding modes. 1322 * NIX transfers entire data using 6 segments/buffers and writes 1323 * a CQE_RX descriptor with those segment addresses. First segment 1324 * has additional data prepended to packet. Also software omits a 1325 * headroom of 128 bytes in each segment. Hence the total size of 1326 * memory needed to receive a packet with 'mtu' is: 1327 * frame size = mtu + additional data; 1328 * memory = frame_size + headroom * 6; 1329 * each receive buffer size = memory / 6; 1330 */ 1331 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1332 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1333 rbuf_size = total_size / 6; 1334 1335 return ALIGN(rbuf_size, 2048); 1336 } 1337 1338 static int otx2_init_hw_resources(struct otx2_nic *pf) 1339 { 1340 struct nix_lf_free_req *free_req; 1341 struct mbox *mbox = &pf->mbox; 1342 struct otx2_hw *hw = &pf->hw; 1343 struct msg_req *req; 1344 int err = 0, lvl; 1345 1346 /* Set required NPA LF's pool counts 1347 * Auras and Pools are used in a 1:1 mapping, 1348 * so, aura count = pool count. 1349 */ 1350 hw->rqpool_cnt = hw->rx_queues; 1351 hw->sqpool_cnt = hw->tot_tx_queues; 1352 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1353 1354 /* Maximum hardware supported transmit length */ 1355 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1356 1357 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1358 1359 mutex_lock(&mbox->lock); 1360 /* NPA init */ 1361 err = otx2_config_npa(pf); 1362 if (err) 1363 goto exit; 1364 1365 /* NIX init */ 1366 err = otx2_config_nix(pf); 1367 if (err) 1368 goto err_free_npa_lf; 1369 1370 /* Enable backpressure */ 1371 otx2_nix_config_bp(pf, true); 1372 1373 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1374 err = otx2_rq_aura_pool_init(pf); 1375 if (err) { 1376 mutex_unlock(&mbox->lock); 1377 goto err_free_nix_lf; 1378 } 1379 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1380 err = otx2_sq_aura_pool_init(pf); 1381 if (err) { 1382 mutex_unlock(&mbox->lock); 1383 goto err_free_rq_ptrs; 1384 } 1385 1386 err = otx2_txsch_alloc(pf); 1387 if (err) { 1388 mutex_unlock(&mbox->lock); 1389 goto err_free_sq_ptrs; 1390 } 1391 1392 #ifdef CONFIG_DCB 1393 if (pf->pfc_en) { 1394 err = otx2_pfc_txschq_alloc(pf); 1395 if (err) { 1396 mutex_unlock(&mbox->lock); 1397 goto err_free_sq_ptrs; 1398 } 1399 } 1400 #endif 1401 1402 err = otx2_config_nix_queues(pf); 1403 if (err) { 1404 mutex_unlock(&mbox->lock); 1405 goto err_free_txsch; 1406 } 1407 1408 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1409 err = otx2_txschq_config(pf, lvl, 0, false); 1410 if (err) { 1411 mutex_unlock(&mbox->lock); 1412 goto err_free_nix_queues; 1413 } 1414 } 1415 1416 #ifdef CONFIG_DCB 1417 if (pf->pfc_en) { 1418 err = otx2_pfc_txschq_config(pf); 1419 if (err) { 1420 mutex_unlock(&mbox->lock); 1421 goto err_free_nix_queues; 1422 } 1423 } 1424 #endif 1425 1426 mutex_unlock(&mbox->lock); 1427 return err; 1428 1429 err_free_nix_queues: 1430 otx2_free_sq_res(pf); 1431 otx2_free_cq_res(pf); 1432 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1433 err_free_txsch: 1434 if (otx2_txschq_stop(pf)) 1435 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1436 err_free_sq_ptrs: 1437 otx2_sq_free_sqbs(pf); 1438 err_free_rq_ptrs: 1439 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1440 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1441 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1442 otx2_aura_pool_free(pf); 1443 err_free_nix_lf: 1444 mutex_lock(&mbox->lock); 1445 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1446 if (free_req) { 1447 free_req->flags = NIX_LF_DISABLE_FLOWS; 1448 if (otx2_sync_mbox_msg(mbox)) 1449 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1450 } 1451 err_free_npa_lf: 1452 /* Reset NPA LF */ 1453 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1454 if (req) { 1455 if (otx2_sync_mbox_msg(mbox)) 1456 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1457 } 1458 exit: 1459 mutex_unlock(&mbox->lock); 1460 return err; 1461 } 1462 1463 static void otx2_free_hw_resources(struct otx2_nic *pf) 1464 { 1465 struct otx2_qset *qset = &pf->qset; 1466 struct nix_lf_free_req *free_req; 1467 struct mbox *mbox = &pf->mbox; 1468 struct otx2_cq_queue *cq; 1469 struct msg_req *req; 1470 int qidx, err; 1471 1472 /* Ensure all SQE are processed */ 1473 otx2_sqb_flush(pf); 1474 1475 /* Stop transmission */ 1476 err = otx2_txschq_stop(pf); 1477 if (err) 1478 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1479 1480 #ifdef CONFIG_DCB 1481 if (pf->pfc_en) 1482 otx2_pfc_txschq_stop(pf); 1483 #endif 1484 1485 mutex_lock(&mbox->lock); 1486 /* Disable backpressure */ 1487 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1488 otx2_nix_config_bp(pf, false); 1489 mutex_unlock(&mbox->lock); 1490 1491 /* Disable RQs */ 1492 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1493 1494 /*Dequeue all CQEs */ 1495 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1496 cq = &qset->cq[qidx]; 1497 if (cq->cq_type == CQ_RX) 1498 otx2_cleanup_rx_cqes(pf, cq); 1499 else 1500 otx2_cleanup_tx_cqes(pf, cq); 1501 } 1502 1503 otx2_free_sq_res(pf); 1504 1505 /* Free RQ buffer pointers*/ 1506 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1507 1508 otx2_free_cq_res(pf); 1509 1510 /* Free all ingress bandwidth profiles allocated */ 1511 cn10k_free_all_ipolicers(pf); 1512 1513 mutex_lock(&mbox->lock); 1514 /* Reset NIX LF */ 1515 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1516 if (free_req) { 1517 free_req->flags = NIX_LF_DISABLE_FLOWS; 1518 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1519 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1520 if (otx2_sync_mbox_msg(mbox)) 1521 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1522 } 1523 mutex_unlock(&mbox->lock); 1524 1525 /* Disable NPA Pool and Aura hw context */ 1526 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1527 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1528 otx2_aura_pool_free(pf); 1529 1530 mutex_lock(&mbox->lock); 1531 /* Reset NPA LF */ 1532 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1533 if (req) { 1534 if (otx2_sync_mbox_msg(mbox)) 1535 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1536 } 1537 mutex_unlock(&mbox->lock); 1538 } 1539 1540 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1541 { 1542 struct net_device *netdev = pf->netdev; 1543 struct nix_rx_mode *req; 1544 bool promisc = false; 1545 1546 if (!(netdev->flags & IFF_UP)) 1547 return; 1548 1549 if ((netdev->flags & IFF_PROMISC) || 1550 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1551 promisc = true; 1552 } 1553 1554 /* Write unicast address to mcam entries or del from mcam */ 1555 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1556 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1557 1558 mutex_lock(&pf->mbox.lock); 1559 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1560 if (!req) { 1561 mutex_unlock(&pf->mbox.lock); 1562 return; 1563 } 1564 1565 req->mode = NIX_RX_MODE_UCAST; 1566 1567 if (promisc) 1568 req->mode |= NIX_RX_MODE_PROMISC; 1569 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1570 req->mode |= NIX_RX_MODE_ALLMULTI; 1571 1572 req->mode |= NIX_RX_MODE_USE_MCE; 1573 1574 otx2_sync_mbox_msg(&pf->mbox); 1575 mutex_unlock(&pf->mbox.lock); 1576 } 1577 1578 static void otx2_dim_work(struct work_struct *w) 1579 { 1580 struct dim_cq_moder cur_moder; 1581 struct otx2_cq_poll *cq_poll; 1582 struct otx2_nic *pfvf; 1583 struct dim *dim; 1584 1585 dim = container_of(w, struct dim, work); 1586 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1587 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1588 pfvf = (struct otx2_nic *)cq_poll->dev; 1589 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1590 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1591 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1592 NAPI_POLL_WEIGHT : cur_moder.pkts; 1593 dim->state = DIM_START_MEASURE; 1594 } 1595 1596 int otx2_open(struct net_device *netdev) 1597 { 1598 struct otx2_nic *pf = netdev_priv(netdev); 1599 struct otx2_cq_poll *cq_poll = NULL; 1600 struct otx2_qset *qset = &pf->qset; 1601 int err = 0, qidx, vec; 1602 char *irq_name; 1603 1604 netif_carrier_off(netdev); 1605 1606 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1607 /* RQ and SQs are mapped to different CQs, 1608 * so find out max CQ IRQs (i.e CINTs) needed. 1609 */ 1610 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1611 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1612 if (!qset->napi) 1613 return -ENOMEM; 1614 1615 /* CQ size of RQ */ 1616 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1617 /* CQ size of SQ */ 1618 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1619 1620 err = -ENOMEM; 1621 qset->cq = kcalloc(pf->qset.cq_cnt, 1622 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1623 if (!qset->cq) 1624 goto err_free_mem; 1625 1626 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1627 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1628 if (!qset->sq) 1629 goto err_free_mem; 1630 1631 qset->rq = kcalloc(pf->hw.rx_queues, 1632 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1633 if (!qset->rq) 1634 goto err_free_mem; 1635 1636 err = otx2_init_hw_resources(pf); 1637 if (err) 1638 goto err_free_mem; 1639 1640 /* Register NAPI handler */ 1641 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1642 cq_poll = &qset->napi[qidx]; 1643 cq_poll->cint_idx = qidx; 1644 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1645 * 'cq_ids[0]' points to RQ's CQ and 1646 * 'cq_ids[1]' points to SQ's CQ and 1647 * 'cq_ids[2]' points to XDP's CQ and 1648 */ 1649 cq_poll->cq_ids[CQ_RX] = 1650 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1651 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1652 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1653 if (pf->xdp_prog) 1654 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1655 (qidx + pf->hw.rx_queues + 1656 pf->hw.tx_queues) : 1657 CINT_INVALID_CQ; 1658 else 1659 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1660 1661 cq_poll->dev = (void *)pf; 1662 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1663 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1664 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1665 napi_enable(&cq_poll->napi); 1666 } 1667 1668 /* Set maximum frame size allowed in HW */ 1669 err = otx2_hw_set_mtu(pf, netdev->mtu); 1670 if (err) 1671 goto err_disable_napi; 1672 1673 /* Setup segmentation algorithms, if failed, clear offload capability */ 1674 otx2_setup_segmentation(pf); 1675 1676 /* Initialize RSS */ 1677 err = otx2_rss_init(pf); 1678 if (err) 1679 goto err_disable_napi; 1680 1681 /* Register Queue IRQ handlers */ 1682 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1683 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1684 1685 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1686 1687 err = request_irq(pci_irq_vector(pf->pdev, vec), 1688 otx2_q_intr_handler, 0, irq_name, pf); 1689 if (err) { 1690 dev_err(pf->dev, 1691 "RVUPF%d: IRQ registration failed for QERR\n", 1692 rvu_get_pf(pf->pcifunc)); 1693 goto err_disable_napi; 1694 } 1695 1696 /* Enable QINT IRQ */ 1697 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1698 1699 /* Register CQ IRQ handlers */ 1700 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1701 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1702 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1703 1704 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1705 qidx); 1706 1707 err = request_irq(pci_irq_vector(pf->pdev, vec), 1708 otx2_cq_intr_handler, 0, irq_name, 1709 &qset->napi[qidx]); 1710 if (err) { 1711 dev_err(pf->dev, 1712 "RVUPF%d: IRQ registration failed for CQ%d\n", 1713 rvu_get_pf(pf->pcifunc), qidx); 1714 goto err_free_cints; 1715 } 1716 vec++; 1717 1718 otx2_config_irq_coalescing(pf, qidx); 1719 1720 /* Enable CQ IRQ */ 1721 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1722 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1723 } 1724 1725 otx2_set_cints_affinity(pf); 1726 1727 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1728 otx2_enable_rxvlan(pf, true); 1729 1730 /* When reinitializing enable time stamping if it is enabled before */ 1731 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1732 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1733 otx2_config_hw_tx_tstamp(pf, true); 1734 } 1735 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1736 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1737 otx2_config_hw_rx_tstamp(pf, true); 1738 } 1739 1740 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1741 /* 'intf_down' may be checked on any cpu */ 1742 smp_wmb(); 1743 1744 /* we have already received link status notification */ 1745 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1746 otx2_handle_link_event(pf); 1747 1748 /* Install DMAC Filters */ 1749 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1750 otx2_dmacflt_reinstall_flows(pf); 1751 1752 err = otx2_rxtx_enable(pf, true); 1753 if (err) 1754 goto err_tx_stop_queues; 1755 1756 otx2_do_set_rx_mode(pf); 1757 1758 return 0; 1759 1760 err_tx_stop_queues: 1761 netif_tx_stop_all_queues(netdev); 1762 netif_carrier_off(netdev); 1763 pf->flags |= OTX2_FLAG_INTF_DOWN; 1764 err_free_cints: 1765 otx2_free_cints(pf, qidx); 1766 vec = pci_irq_vector(pf->pdev, 1767 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1768 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1769 free_irq(vec, pf); 1770 err_disable_napi: 1771 otx2_disable_napi(pf); 1772 otx2_free_hw_resources(pf); 1773 err_free_mem: 1774 kfree(qset->sq); 1775 kfree(qset->cq); 1776 kfree(qset->rq); 1777 kfree(qset->napi); 1778 return err; 1779 } 1780 EXPORT_SYMBOL(otx2_open); 1781 1782 int otx2_stop(struct net_device *netdev) 1783 { 1784 struct otx2_nic *pf = netdev_priv(netdev); 1785 struct otx2_cq_poll *cq_poll = NULL; 1786 struct otx2_qset *qset = &pf->qset; 1787 struct otx2_rss_info *rss; 1788 int qidx, vec, wrk; 1789 1790 /* If the DOWN flag is set resources are already freed */ 1791 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1792 return 0; 1793 1794 netif_carrier_off(netdev); 1795 netif_tx_stop_all_queues(netdev); 1796 1797 pf->flags |= OTX2_FLAG_INTF_DOWN; 1798 /* 'intf_down' may be checked on any cpu */ 1799 smp_wmb(); 1800 1801 /* First stop packet Rx/Tx */ 1802 otx2_rxtx_enable(pf, false); 1803 1804 /* Clear RSS enable flag */ 1805 rss = &pf->hw.rss_info; 1806 rss->enable = false; 1807 1808 /* Cleanup Queue IRQ */ 1809 vec = pci_irq_vector(pf->pdev, 1810 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1811 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1812 free_irq(vec, pf); 1813 1814 /* Cleanup CQ NAPI and IRQ */ 1815 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1816 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1817 /* Disable interrupt */ 1818 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1819 1820 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1821 1822 cq_poll = &qset->napi[qidx]; 1823 napi_synchronize(&cq_poll->napi); 1824 vec++; 1825 } 1826 1827 netif_tx_disable(netdev); 1828 1829 otx2_free_hw_resources(pf); 1830 otx2_free_cints(pf, pf->hw.cint_cnt); 1831 otx2_disable_napi(pf); 1832 1833 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1834 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1835 1836 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1837 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1838 devm_kfree(pf->dev, pf->refill_wrk); 1839 1840 kfree(qset->sq); 1841 kfree(qset->cq); 1842 kfree(qset->rq); 1843 kfree(qset->napi); 1844 /* Do not clear RQ/SQ ringsize settings */ 1845 memset_startat(qset, 0, sqe_cnt); 1846 return 0; 1847 } 1848 EXPORT_SYMBOL(otx2_stop); 1849 1850 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1851 { 1852 struct otx2_nic *pf = netdev_priv(netdev); 1853 int qidx = skb_get_queue_mapping(skb); 1854 struct otx2_snd_queue *sq; 1855 struct netdev_queue *txq; 1856 1857 /* Check for minimum and maximum packet length */ 1858 if (skb->len <= ETH_HLEN || 1859 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1860 dev_kfree_skb(skb); 1861 return NETDEV_TX_OK; 1862 } 1863 1864 sq = &pf->qset.sq[qidx]; 1865 txq = netdev_get_tx_queue(netdev, qidx); 1866 1867 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1868 netif_tx_stop_queue(txq); 1869 1870 /* Check again, incase SQBs got freed up */ 1871 smp_mb(); 1872 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1873 > sq->sqe_thresh) 1874 netif_tx_wake_queue(txq); 1875 1876 return NETDEV_TX_BUSY; 1877 } 1878 1879 return NETDEV_TX_OK; 1880 } 1881 1882 static u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1883 struct net_device *sb_dev) 1884 { 1885 #ifdef CONFIG_DCB 1886 struct otx2_nic *pf = netdev_priv(netdev); 1887 u8 vlan_prio; 1888 #endif 1889 1890 #ifdef CONFIG_DCB 1891 if (!skb->vlan_present) 1892 goto pick_tx; 1893 1894 vlan_prio = skb->vlan_tci >> 13; 1895 if ((vlan_prio > pf->hw.tx_queues - 1) || 1896 !pf->pfc_alloc_status[vlan_prio]) 1897 goto pick_tx; 1898 1899 return vlan_prio; 1900 1901 pick_tx: 1902 #endif 1903 return netdev_pick_tx(netdev, skb, NULL); 1904 } 1905 1906 static netdev_features_t otx2_fix_features(struct net_device *dev, 1907 netdev_features_t features) 1908 { 1909 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1910 features |= NETIF_F_HW_VLAN_STAG_RX; 1911 else 1912 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1913 1914 return features; 1915 } 1916 1917 static void otx2_set_rx_mode(struct net_device *netdev) 1918 { 1919 struct otx2_nic *pf = netdev_priv(netdev); 1920 1921 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1922 } 1923 1924 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 1925 { 1926 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1927 1928 otx2_do_set_rx_mode(pf); 1929 } 1930 1931 static int otx2_set_features(struct net_device *netdev, 1932 netdev_features_t features) 1933 { 1934 netdev_features_t changed = features ^ netdev->features; 1935 struct otx2_nic *pf = netdev_priv(netdev); 1936 1937 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1938 return otx2_cgx_config_loopback(pf, 1939 features & NETIF_F_LOOPBACK); 1940 1941 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1942 return otx2_enable_rxvlan(pf, 1943 features & NETIF_F_HW_VLAN_CTAG_RX); 1944 1945 return otx2_handle_ntuple_tc_features(netdev, features); 1946 } 1947 1948 static void otx2_reset_task(struct work_struct *work) 1949 { 1950 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1951 1952 if (!netif_running(pf->netdev)) 1953 return; 1954 1955 rtnl_lock(); 1956 otx2_stop(pf->netdev); 1957 pf->reset_count++; 1958 otx2_open(pf->netdev); 1959 netif_trans_update(pf->netdev); 1960 rtnl_unlock(); 1961 } 1962 1963 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1964 { 1965 struct msg_req *req; 1966 int err; 1967 1968 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1969 return 0; 1970 1971 mutex_lock(&pfvf->mbox.lock); 1972 if (enable) 1973 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1974 else 1975 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1976 if (!req) { 1977 mutex_unlock(&pfvf->mbox.lock); 1978 return -ENOMEM; 1979 } 1980 1981 err = otx2_sync_mbox_msg(&pfvf->mbox); 1982 if (err) { 1983 mutex_unlock(&pfvf->mbox.lock); 1984 return err; 1985 } 1986 1987 mutex_unlock(&pfvf->mbox.lock); 1988 if (enable) 1989 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1990 else 1991 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1992 return 0; 1993 } 1994 1995 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1996 { 1997 struct msg_req *req; 1998 int err; 1999 2000 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2001 return 0; 2002 2003 mutex_lock(&pfvf->mbox.lock); 2004 if (enable) 2005 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2006 else 2007 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2008 if (!req) { 2009 mutex_unlock(&pfvf->mbox.lock); 2010 return -ENOMEM; 2011 } 2012 2013 err = otx2_sync_mbox_msg(&pfvf->mbox); 2014 if (err) { 2015 mutex_unlock(&pfvf->mbox.lock); 2016 return err; 2017 } 2018 2019 mutex_unlock(&pfvf->mbox.lock); 2020 if (enable) 2021 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2022 else 2023 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2024 return 0; 2025 } 2026 2027 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2028 { 2029 struct otx2_nic *pfvf = netdev_priv(netdev); 2030 struct hwtstamp_config config; 2031 2032 if (!pfvf->ptp) 2033 return -ENODEV; 2034 2035 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2036 return -EFAULT; 2037 2038 switch (config.tx_type) { 2039 case HWTSTAMP_TX_OFF: 2040 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2041 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2042 2043 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2044 otx2_config_hw_tx_tstamp(pfvf, false); 2045 break; 2046 case HWTSTAMP_TX_ONESTEP_SYNC: 2047 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2048 return -ERANGE; 2049 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2050 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2051 msecs_to_jiffies(500)); 2052 fallthrough; 2053 case HWTSTAMP_TX_ON: 2054 otx2_config_hw_tx_tstamp(pfvf, true); 2055 break; 2056 default: 2057 return -ERANGE; 2058 } 2059 2060 switch (config.rx_filter) { 2061 case HWTSTAMP_FILTER_NONE: 2062 otx2_config_hw_rx_tstamp(pfvf, false); 2063 break; 2064 case HWTSTAMP_FILTER_ALL: 2065 case HWTSTAMP_FILTER_SOME: 2066 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2067 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2068 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2069 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2070 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2071 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2072 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2073 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2074 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2075 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2076 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2077 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2078 otx2_config_hw_rx_tstamp(pfvf, true); 2079 config.rx_filter = HWTSTAMP_FILTER_ALL; 2080 break; 2081 default: 2082 return -ERANGE; 2083 } 2084 2085 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2086 2087 return copy_to_user(ifr->ifr_data, &config, 2088 sizeof(config)) ? -EFAULT : 0; 2089 } 2090 EXPORT_SYMBOL(otx2_config_hwtstamp); 2091 2092 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2093 { 2094 struct otx2_nic *pfvf = netdev_priv(netdev); 2095 struct hwtstamp_config *cfg = &pfvf->tstamp; 2096 2097 switch (cmd) { 2098 case SIOCSHWTSTAMP: 2099 return otx2_config_hwtstamp(netdev, req); 2100 case SIOCGHWTSTAMP: 2101 return copy_to_user(req->ifr_data, cfg, 2102 sizeof(*cfg)) ? -EFAULT : 0; 2103 default: 2104 return -EOPNOTSUPP; 2105 } 2106 } 2107 EXPORT_SYMBOL(otx2_ioctl); 2108 2109 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2110 { 2111 struct npc_install_flow_req *req; 2112 int err; 2113 2114 mutex_lock(&pf->mbox.lock); 2115 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2116 if (!req) { 2117 err = -ENOMEM; 2118 goto out; 2119 } 2120 2121 ether_addr_copy(req->packet.dmac, mac); 2122 eth_broadcast_addr((u8 *)&req->mask.dmac); 2123 req->features = BIT_ULL(NPC_DMAC); 2124 req->channel = pf->hw.rx_chan_base; 2125 req->intf = NIX_INTF_RX; 2126 req->default_rule = 1; 2127 req->append = 1; 2128 req->vf = vf + 1; 2129 req->op = NIX_RX_ACTION_DEFAULT; 2130 2131 err = otx2_sync_mbox_msg(&pf->mbox); 2132 out: 2133 mutex_unlock(&pf->mbox.lock); 2134 return err; 2135 } 2136 2137 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2138 { 2139 struct otx2_nic *pf = netdev_priv(netdev); 2140 struct pci_dev *pdev = pf->pdev; 2141 struct otx2_vf_config *config; 2142 int ret; 2143 2144 if (!netif_running(netdev)) 2145 return -EAGAIN; 2146 2147 if (vf >= pf->total_vfs) 2148 return -EINVAL; 2149 2150 if (!is_valid_ether_addr(mac)) 2151 return -EINVAL; 2152 2153 config = &pf->vf_configs[vf]; 2154 ether_addr_copy(config->mac, mac); 2155 2156 ret = otx2_do_set_vf_mac(pf, vf, mac); 2157 if (ret == 0) 2158 dev_info(&pdev->dev, 2159 "Load/Reload VF driver\n"); 2160 2161 return ret; 2162 } 2163 2164 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2165 __be16 proto) 2166 { 2167 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2168 struct nix_vtag_config_rsp *vtag_rsp; 2169 struct npc_delete_flow_req *del_req; 2170 struct nix_vtag_config *vtag_req; 2171 struct npc_install_flow_req *req; 2172 struct otx2_vf_config *config; 2173 int err = 0; 2174 u32 idx; 2175 2176 config = &pf->vf_configs[vf]; 2177 2178 if (!vlan && !config->vlan) 2179 goto out; 2180 2181 mutex_lock(&pf->mbox.lock); 2182 2183 /* free old tx vtag entry */ 2184 if (config->vlan) { 2185 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2186 if (!vtag_req) { 2187 err = -ENOMEM; 2188 goto out; 2189 } 2190 vtag_req->cfg_type = 0; 2191 vtag_req->tx.free_vtag0 = 1; 2192 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2193 2194 err = otx2_sync_mbox_msg(&pf->mbox); 2195 if (err) 2196 goto out; 2197 } 2198 2199 if (!vlan && config->vlan) { 2200 /* rx */ 2201 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2202 if (!del_req) { 2203 err = -ENOMEM; 2204 goto out; 2205 } 2206 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2207 del_req->entry = 2208 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2209 err = otx2_sync_mbox_msg(&pf->mbox); 2210 if (err) 2211 goto out; 2212 2213 /* tx */ 2214 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2215 if (!del_req) { 2216 err = -ENOMEM; 2217 goto out; 2218 } 2219 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2220 del_req->entry = 2221 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2222 err = otx2_sync_mbox_msg(&pf->mbox); 2223 2224 goto out; 2225 } 2226 2227 /* rx */ 2228 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2229 if (!req) { 2230 err = -ENOMEM; 2231 goto out; 2232 } 2233 2234 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2235 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2236 req->packet.vlan_tci = htons(vlan); 2237 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2238 /* af fills the destination mac addr */ 2239 eth_broadcast_addr((u8 *)&req->mask.dmac); 2240 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2241 req->channel = pf->hw.rx_chan_base; 2242 req->intf = NIX_INTF_RX; 2243 req->vf = vf + 1; 2244 req->op = NIX_RX_ACTION_DEFAULT; 2245 req->vtag0_valid = true; 2246 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2247 req->set_cntr = 1; 2248 2249 err = otx2_sync_mbox_msg(&pf->mbox); 2250 if (err) 2251 goto out; 2252 2253 /* tx */ 2254 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2255 if (!vtag_req) { 2256 err = -ENOMEM; 2257 goto out; 2258 } 2259 2260 /* configure tx vtag params */ 2261 vtag_req->vtag_size = VTAGSIZE_T4; 2262 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2263 vtag_req->tx.cfg_vtag0 = 1; 2264 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2265 2266 err = otx2_sync_mbox_msg(&pf->mbox); 2267 if (err) 2268 goto out; 2269 2270 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2271 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2272 if (IS_ERR(vtag_rsp)) { 2273 err = PTR_ERR(vtag_rsp); 2274 goto out; 2275 } 2276 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2277 2278 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2279 if (!req) { 2280 err = -ENOMEM; 2281 goto out; 2282 } 2283 2284 eth_zero_addr((u8 *)&req->mask.dmac); 2285 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2286 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2287 req->features = BIT_ULL(NPC_DMAC); 2288 req->channel = pf->hw.tx_chan_base; 2289 req->intf = NIX_INTF_TX; 2290 req->vf = vf + 1; 2291 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2292 req->vtag0_def = vtag_rsp->vtag0_idx; 2293 req->vtag0_op = VTAG_INSERT; 2294 req->set_cntr = 1; 2295 2296 err = otx2_sync_mbox_msg(&pf->mbox); 2297 out: 2298 config->vlan = vlan; 2299 mutex_unlock(&pf->mbox.lock); 2300 return err; 2301 } 2302 2303 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2304 __be16 proto) 2305 { 2306 struct otx2_nic *pf = netdev_priv(netdev); 2307 struct pci_dev *pdev = pf->pdev; 2308 2309 if (!netif_running(netdev)) 2310 return -EAGAIN; 2311 2312 if (vf >= pci_num_vf(pdev)) 2313 return -EINVAL; 2314 2315 /* qos is currently unsupported */ 2316 if (vlan >= VLAN_N_VID || qos) 2317 return -EINVAL; 2318 2319 if (proto != htons(ETH_P_8021Q)) 2320 return -EPROTONOSUPPORT; 2321 2322 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2323 return -EOPNOTSUPP; 2324 2325 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2326 } 2327 2328 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2329 struct ifla_vf_info *ivi) 2330 { 2331 struct otx2_nic *pf = netdev_priv(netdev); 2332 struct pci_dev *pdev = pf->pdev; 2333 struct otx2_vf_config *config; 2334 2335 if (!netif_running(netdev)) 2336 return -EAGAIN; 2337 2338 if (vf >= pci_num_vf(pdev)) 2339 return -EINVAL; 2340 2341 config = &pf->vf_configs[vf]; 2342 ivi->vf = vf; 2343 ether_addr_copy(ivi->mac, config->mac); 2344 ivi->vlan = config->vlan; 2345 ivi->trusted = config->trusted; 2346 2347 return 0; 2348 } 2349 2350 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2351 int qidx) 2352 { 2353 struct page *page; 2354 u64 dma_addr; 2355 int err = 0; 2356 2357 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2358 offset_in_page(xdpf->data), xdpf->len, 2359 DMA_TO_DEVICE); 2360 if (dma_mapping_error(pf->dev, dma_addr)) 2361 return -ENOMEM; 2362 2363 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2364 if (!err) { 2365 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2366 page = virt_to_page(xdpf->data); 2367 put_page(page); 2368 return -ENOMEM; 2369 } 2370 return 0; 2371 } 2372 2373 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2374 struct xdp_frame **frames, u32 flags) 2375 { 2376 struct otx2_nic *pf = netdev_priv(netdev); 2377 int qidx = smp_processor_id(); 2378 struct otx2_snd_queue *sq; 2379 int drops = 0, i; 2380 2381 if (!netif_running(netdev)) 2382 return -ENETDOWN; 2383 2384 qidx += pf->hw.tx_queues; 2385 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2386 2387 /* Abort xmit if xdp queue is not */ 2388 if (unlikely(!sq)) 2389 return -ENXIO; 2390 2391 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2392 return -EINVAL; 2393 2394 for (i = 0; i < n; i++) { 2395 struct xdp_frame *xdpf = frames[i]; 2396 int err; 2397 2398 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2399 if (err) 2400 drops++; 2401 } 2402 return n - drops; 2403 } 2404 2405 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2406 { 2407 struct net_device *dev = pf->netdev; 2408 bool if_up = netif_running(pf->netdev); 2409 struct bpf_prog *old_prog; 2410 2411 if (prog && dev->mtu > MAX_XDP_MTU) { 2412 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2413 return -EOPNOTSUPP; 2414 } 2415 2416 if (if_up) 2417 otx2_stop(pf->netdev); 2418 2419 old_prog = xchg(&pf->xdp_prog, prog); 2420 2421 if (old_prog) 2422 bpf_prog_put(old_prog); 2423 2424 if (pf->xdp_prog) 2425 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2426 2427 /* Network stack and XDP shared same rx queues. 2428 * Use separate tx queues for XDP and network stack. 2429 */ 2430 if (pf->xdp_prog) 2431 pf->hw.xdp_queues = pf->hw.rx_queues; 2432 else 2433 pf->hw.xdp_queues = 0; 2434 2435 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2436 2437 if (if_up) 2438 otx2_open(pf->netdev); 2439 2440 return 0; 2441 } 2442 2443 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2444 { 2445 struct otx2_nic *pf = netdev_priv(netdev); 2446 2447 switch (xdp->command) { 2448 case XDP_SETUP_PROG: 2449 return otx2_xdp_setup(pf, xdp->prog); 2450 default: 2451 return -EINVAL; 2452 } 2453 } 2454 2455 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2456 int req_perm) 2457 { 2458 struct set_vf_perm *req; 2459 int rc; 2460 2461 mutex_lock(&pf->mbox.lock); 2462 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2463 if (!req) { 2464 rc = -ENOMEM; 2465 goto out; 2466 } 2467 2468 /* Let AF reset VF permissions as sriov is disabled */ 2469 if (req_perm == OTX2_RESET_VF_PERM) { 2470 req->flags |= RESET_VF_PERM; 2471 } else if (req_perm == OTX2_TRUSTED_VF) { 2472 if (pf->vf_configs[vf].trusted) 2473 req->flags |= VF_TRUSTED; 2474 } 2475 2476 req->vf = vf; 2477 rc = otx2_sync_mbox_msg(&pf->mbox); 2478 out: 2479 mutex_unlock(&pf->mbox.lock); 2480 return rc; 2481 } 2482 2483 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2484 bool enable) 2485 { 2486 struct otx2_nic *pf = netdev_priv(netdev); 2487 struct pci_dev *pdev = pf->pdev; 2488 int rc; 2489 2490 if (vf >= pci_num_vf(pdev)) 2491 return -EINVAL; 2492 2493 if (pf->vf_configs[vf].trusted == enable) 2494 return 0; 2495 2496 pf->vf_configs[vf].trusted = enable; 2497 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2498 2499 if (rc) 2500 pf->vf_configs[vf].trusted = !enable; 2501 else 2502 netdev_info(pf->netdev, "VF %d is %strusted\n", 2503 vf, enable ? "" : "not "); 2504 return rc; 2505 } 2506 2507 static const struct net_device_ops otx2_netdev_ops = { 2508 .ndo_open = otx2_open, 2509 .ndo_stop = otx2_stop, 2510 .ndo_start_xmit = otx2_xmit, 2511 .ndo_select_queue = otx2_select_queue, 2512 .ndo_fix_features = otx2_fix_features, 2513 .ndo_set_mac_address = otx2_set_mac_address, 2514 .ndo_change_mtu = otx2_change_mtu, 2515 .ndo_set_rx_mode = otx2_set_rx_mode, 2516 .ndo_set_features = otx2_set_features, 2517 .ndo_tx_timeout = otx2_tx_timeout, 2518 .ndo_get_stats64 = otx2_get_stats64, 2519 .ndo_eth_ioctl = otx2_ioctl, 2520 .ndo_set_vf_mac = otx2_set_vf_mac, 2521 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2522 .ndo_get_vf_config = otx2_get_vf_config, 2523 .ndo_bpf = otx2_xdp, 2524 .ndo_xdp_xmit = otx2_xdp_xmit, 2525 .ndo_setup_tc = otx2_setup_tc, 2526 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2527 }; 2528 2529 static int otx2_wq_init(struct otx2_nic *pf) 2530 { 2531 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2532 if (!pf->otx2_wq) 2533 return -ENOMEM; 2534 2535 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2536 INIT_WORK(&pf->reset_task, otx2_reset_task); 2537 return 0; 2538 } 2539 2540 static int otx2_check_pf_usable(struct otx2_nic *nic) 2541 { 2542 u64 rev; 2543 2544 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2545 rev = (rev >> 12) & 0xFF; 2546 /* Check if AF has setup revision for RVUM block, 2547 * otherwise this driver probe should be deferred 2548 * until AF driver comes up. 2549 */ 2550 if (!rev) { 2551 dev_warn(nic->dev, 2552 "AF is not initialized, deferring probe\n"); 2553 return -EPROBE_DEFER; 2554 } 2555 return 0; 2556 } 2557 2558 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2559 { 2560 struct otx2_hw *hw = &pf->hw; 2561 int num_vec, err; 2562 2563 /* NPA interrupts are inot registered, so alloc only 2564 * upto NIX vector offset. 2565 */ 2566 num_vec = hw->nix_msixoff; 2567 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2568 2569 otx2_disable_mbox_intr(pf); 2570 pci_free_irq_vectors(hw->pdev); 2571 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2572 if (err < 0) { 2573 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2574 __func__, num_vec); 2575 return err; 2576 } 2577 2578 return otx2_register_mbox_intr(pf, false); 2579 } 2580 2581 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2582 { 2583 int i; 2584 2585 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2586 sizeof(struct otx2_vf_config), 2587 GFP_KERNEL); 2588 if (!pf->vf_configs) 2589 return -ENOMEM; 2590 2591 for (i = 0; i < pf->total_vfs; i++) { 2592 pf->vf_configs[i].pf = pf; 2593 pf->vf_configs[i].intf_down = true; 2594 pf->vf_configs[i].trusted = false; 2595 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2596 otx2_vf_link_event_task); 2597 } 2598 2599 return 0; 2600 } 2601 2602 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2603 { 2604 int i; 2605 2606 if (!pf->vf_configs) 2607 return; 2608 2609 for (i = 0; i < pf->total_vfs; i++) { 2610 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2611 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2612 } 2613 } 2614 2615 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2616 { 2617 struct device *dev = &pdev->dev; 2618 struct net_device *netdev; 2619 struct otx2_nic *pf; 2620 struct otx2_hw *hw; 2621 int err, qcount; 2622 int num_vec; 2623 2624 err = pcim_enable_device(pdev); 2625 if (err) { 2626 dev_err(dev, "Failed to enable PCI device\n"); 2627 return err; 2628 } 2629 2630 err = pci_request_regions(pdev, DRV_NAME); 2631 if (err) { 2632 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2633 return err; 2634 } 2635 2636 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2637 if (err) { 2638 dev_err(dev, "DMA mask config failed, abort\n"); 2639 goto err_release_regions; 2640 } 2641 2642 pci_set_master(pdev); 2643 2644 /* Set number of queues */ 2645 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2646 2647 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2648 if (!netdev) { 2649 err = -ENOMEM; 2650 goto err_release_regions; 2651 } 2652 2653 pci_set_drvdata(pdev, netdev); 2654 SET_NETDEV_DEV(netdev, &pdev->dev); 2655 pf = netdev_priv(netdev); 2656 pf->netdev = netdev; 2657 pf->pdev = pdev; 2658 pf->dev = dev; 2659 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2660 pf->flags |= OTX2_FLAG_INTF_DOWN; 2661 2662 hw = &pf->hw; 2663 hw->pdev = pdev; 2664 hw->rx_queues = qcount; 2665 hw->tx_queues = qcount; 2666 hw->tot_tx_queues = qcount; 2667 hw->max_queues = qcount; 2668 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2669 /* Use CQE of 128 byte descriptor size by default */ 2670 hw->xqe_size = 128; 2671 2672 num_vec = pci_msix_vec_count(pdev); 2673 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2674 GFP_KERNEL); 2675 if (!hw->irq_name) { 2676 err = -ENOMEM; 2677 goto err_free_netdev; 2678 } 2679 2680 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2681 sizeof(cpumask_var_t), GFP_KERNEL); 2682 if (!hw->affinity_mask) { 2683 err = -ENOMEM; 2684 goto err_free_netdev; 2685 } 2686 2687 /* Map CSRs */ 2688 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2689 if (!pf->reg_base) { 2690 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2691 err = -ENOMEM; 2692 goto err_free_netdev; 2693 } 2694 2695 err = otx2_check_pf_usable(pf); 2696 if (err) 2697 goto err_free_netdev; 2698 2699 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2700 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2701 if (err < 0) { 2702 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2703 __func__, num_vec); 2704 goto err_free_netdev; 2705 } 2706 2707 otx2_setup_dev_hw_settings(pf); 2708 2709 /* Init PF <=> AF mailbox stuff */ 2710 err = otx2_pfaf_mbox_init(pf); 2711 if (err) 2712 goto err_free_irq_vectors; 2713 2714 /* Register mailbox interrupt */ 2715 err = otx2_register_mbox_intr(pf, true); 2716 if (err) 2717 goto err_mbox_destroy; 2718 2719 /* Request AF to attach NPA and NIX LFs to this PF. 2720 * NIX and NPA LFs are needed for this PF to function as a NIC. 2721 */ 2722 err = otx2_attach_npa_nix(pf); 2723 if (err) 2724 goto err_disable_mbox_intr; 2725 2726 err = otx2_realloc_msix_vectors(pf); 2727 if (err) 2728 goto err_detach_rsrc; 2729 2730 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2731 if (err) 2732 goto err_detach_rsrc; 2733 2734 err = cn10k_lmtst_init(pf); 2735 if (err) 2736 goto err_detach_rsrc; 2737 2738 /* Assign default mac address */ 2739 otx2_get_mac_from_af(netdev); 2740 2741 /* Don't check for error. Proceed without ptp */ 2742 otx2_ptp_init(pf); 2743 2744 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2745 * HW allocates buffer pointer from stack and uses it for DMA'ing 2746 * ingress packet. In some scenarios HW can free back allocated buffer 2747 * pointers to pool. This makes it impossible for SW to maintain a 2748 * parallel list where physical addresses of buffer pointers (IOVAs) 2749 * given to HW can be saved for later reference. 2750 * 2751 * So the only way to convert Rx packet's buffer address is to use 2752 * IOMMU's iova_to_phys() handler which translates the address by 2753 * walking through the translation tables. 2754 */ 2755 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2756 2757 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2758 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2759 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2760 NETIF_F_GSO_UDP_L4); 2761 netdev->features |= netdev->hw_features; 2762 2763 err = otx2_mcam_flow_init(pf); 2764 if (err) 2765 goto err_ptp_destroy; 2766 2767 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2768 netdev->hw_features |= NETIF_F_NTUPLE; 2769 2770 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2771 netdev->priv_flags |= IFF_UNICAST_FLT; 2772 2773 /* Support TSO on tag interface */ 2774 netdev->vlan_features |= netdev->features; 2775 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2776 NETIF_F_HW_VLAN_STAG_TX; 2777 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2778 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2779 NETIF_F_HW_VLAN_STAG_RX; 2780 netdev->features |= netdev->hw_features; 2781 2782 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2783 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2784 netdev->hw_features |= NETIF_F_HW_TC; 2785 2786 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2787 2788 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2789 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2790 2791 netdev->netdev_ops = &otx2_netdev_ops; 2792 2793 netdev->min_mtu = OTX2_MIN_MTU; 2794 netdev->max_mtu = otx2_get_max_mtu(pf); 2795 2796 err = register_netdev(netdev); 2797 if (err) { 2798 dev_err(dev, "Failed to register netdevice\n"); 2799 goto err_del_mcam_entries; 2800 } 2801 2802 err = otx2_wq_init(pf); 2803 if (err) 2804 goto err_unreg_netdev; 2805 2806 otx2_set_ethtool_ops(netdev); 2807 2808 err = otx2_init_tc(pf); 2809 if (err) 2810 goto err_mcam_flow_del; 2811 2812 err = otx2_register_dl(pf); 2813 if (err) 2814 goto err_mcam_flow_del; 2815 2816 /* Initialize SR-IOV resources */ 2817 err = otx2_sriov_vfcfg_init(pf); 2818 if (err) 2819 goto err_pf_sriov_init; 2820 2821 /* Enable link notifications */ 2822 otx2_cgx_config_linkevents(pf, true); 2823 2824 #ifdef CONFIG_DCB 2825 err = otx2_dcbnl_set_ops(netdev); 2826 if (err) 2827 goto err_pf_sriov_init; 2828 #endif 2829 2830 return 0; 2831 2832 err_pf_sriov_init: 2833 otx2_shutdown_tc(pf); 2834 err_mcam_flow_del: 2835 otx2_mcam_flow_del(pf); 2836 err_unreg_netdev: 2837 unregister_netdev(netdev); 2838 err_del_mcam_entries: 2839 otx2_mcam_flow_del(pf); 2840 err_ptp_destroy: 2841 otx2_ptp_destroy(pf); 2842 err_detach_rsrc: 2843 if (pf->hw.lmt_info) 2844 free_percpu(pf->hw.lmt_info); 2845 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2846 qmem_free(pf->dev, pf->dync_lmt); 2847 otx2_detach_resources(&pf->mbox); 2848 err_disable_mbox_intr: 2849 otx2_disable_mbox_intr(pf); 2850 err_mbox_destroy: 2851 otx2_pfaf_mbox_destroy(pf); 2852 err_free_irq_vectors: 2853 pci_free_irq_vectors(hw->pdev); 2854 err_free_netdev: 2855 pci_set_drvdata(pdev, NULL); 2856 free_netdev(netdev); 2857 err_release_regions: 2858 pci_release_regions(pdev); 2859 return err; 2860 } 2861 2862 static void otx2_vf_link_event_task(struct work_struct *work) 2863 { 2864 struct otx2_vf_config *config; 2865 struct cgx_link_info_msg *req; 2866 struct mbox_msghdr *msghdr; 2867 struct otx2_nic *pf; 2868 int vf_idx; 2869 2870 config = container_of(work, struct otx2_vf_config, 2871 link_event_work.work); 2872 vf_idx = config - config->pf->vf_configs; 2873 pf = config->pf; 2874 2875 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2876 sizeof(*req), sizeof(struct msg_rsp)); 2877 if (!msghdr) { 2878 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2879 return; 2880 } 2881 2882 req = (struct cgx_link_info_msg *)msghdr; 2883 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2884 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2885 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2886 2887 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2888 } 2889 2890 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2891 { 2892 struct net_device *netdev = pci_get_drvdata(pdev); 2893 struct otx2_nic *pf = netdev_priv(netdev); 2894 int ret; 2895 2896 /* Init PF <=> VF mailbox stuff */ 2897 ret = otx2_pfvf_mbox_init(pf, numvfs); 2898 if (ret) 2899 return ret; 2900 2901 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2902 if (ret) 2903 goto free_mbox; 2904 2905 ret = otx2_pf_flr_init(pf, numvfs); 2906 if (ret) 2907 goto free_intr; 2908 2909 ret = otx2_register_flr_me_intr(pf, numvfs); 2910 if (ret) 2911 goto free_flr; 2912 2913 ret = pci_enable_sriov(pdev, numvfs); 2914 if (ret) 2915 goto free_flr_intr; 2916 2917 return numvfs; 2918 free_flr_intr: 2919 otx2_disable_flr_me_intr(pf); 2920 free_flr: 2921 otx2_flr_wq_destroy(pf); 2922 free_intr: 2923 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2924 free_mbox: 2925 otx2_pfvf_mbox_destroy(pf); 2926 return ret; 2927 } 2928 2929 static int otx2_sriov_disable(struct pci_dev *pdev) 2930 { 2931 struct net_device *netdev = pci_get_drvdata(pdev); 2932 struct otx2_nic *pf = netdev_priv(netdev); 2933 int numvfs = pci_num_vf(pdev); 2934 2935 if (!numvfs) 2936 return 0; 2937 2938 pci_disable_sriov(pdev); 2939 2940 otx2_disable_flr_me_intr(pf); 2941 otx2_flr_wq_destroy(pf); 2942 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2943 otx2_pfvf_mbox_destroy(pf); 2944 2945 return 0; 2946 } 2947 2948 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2949 { 2950 if (numvfs == 0) 2951 return otx2_sriov_disable(pdev); 2952 else 2953 return otx2_sriov_enable(pdev, numvfs); 2954 } 2955 2956 static void otx2_remove(struct pci_dev *pdev) 2957 { 2958 struct net_device *netdev = pci_get_drvdata(pdev); 2959 struct otx2_nic *pf; 2960 2961 if (!netdev) 2962 return; 2963 2964 pf = netdev_priv(netdev); 2965 2966 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2967 2968 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2969 otx2_config_hw_tx_tstamp(pf, false); 2970 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2971 otx2_config_hw_rx_tstamp(pf, false); 2972 2973 /* Disable 802.3x pause frames */ 2974 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 2975 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 2976 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 2977 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 2978 otx2_config_pause_frm(pf); 2979 } 2980 2981 #ifdef CONFIG_DCB 2982 /* Disable PFC config */ 2983 if (pf->pfc_en) { 2984 pf->pfc_en = 0; 2985 otx2_config_priority_flow_ctrl(pf); 2986 } 2987 #endif 2988 cancel_work_sync(&pf->reset_task); 2989 /* Disable link notifications */ 2990 otx2_cgx_config_linkevents(pf, false); 2991 2992 otx2_unregister_dl(pf); 2993 unregister_netdev(netdev); 2994 otx2_sriov_disable(pf->pdev); 2995 otx2_sriov_vfcfg_cleanup(pf); 2996 if (pf->otx2_wq) 2997 destroy_workqueue(pf->otx2_wq); 2998 2999 otx2_ptp_destroy(pf); 3000 otx2_mcam_flow_del(pf); 3001 otx2_shutdown_tc(pf); 3002 otx2_detach_resources(&pf->mbox); 3003 if (pf->hw.lmt_info) 3004 free_percpu(pf->hw.lmt_info); 3005 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3006 qmem_free(pf->dev, pf->dync_lmt); 3007 otx2_disable_mbox_intr(pf); 3008 otx2_pfaf_mbox_destroy(pf); 3009 pci_free_irq_vectors(pf->pdev); 3010 pci_set_drvdata(pdev, NULL); 3011 free_netdev(netdev); 3012 3013 pci_release_regions(pdev); 3014 } 3015 3016 static struct pci_driver otx2_pf_driver = { 3017 .name = DRV_NAME, 3018 .id_table = otx2_pf_id_table, 3019 .probe = otx2_probe, 3020 .shutdown = otx2_remove, 3021 .remove = otx2_remove, 3022 .sriov_configure = otx2_sriov_configure 3023 }; 3024 3025 static int __init otx2_rvupf_init_module(void) 3026 { 3027 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3028 3029 return pci_register_driver(&otx2_pf_driver); 3030 } 3031 3032 static void __exit otx2_rvupf_cleanup_module(void) 3033 { 3034 pci_unregister_driver(&otx2_pf_driver); 3035 } 3036 3037 module_init(otx2_rvupf_init_module); 3038 module_exit(otx2_rvupf_cleanup_module); 3039