1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include "cn10k.h" 26 #include <rvu_trace.h> 27 28 #define DRV_NAME "rvu_nicpf" 29 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 30 31 /* Supported devices */ 32 static const struct pci_device_id otx2_pf_id_table[] = { 33 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 34 { 0, } /* end of table */ 35 }; 36 37 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 38 MODULE_DESCRIPTION(DRV_STRING); 39 MODULE_LICENSE("GPL v2"); 40 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 41 42 static void otx2_vf_link_event_task(struct work_struct *work); 43 44 enum { 45 TYPE_PFAF, 46 TYPE_PFVF, 47 }; 48 49 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 50 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 51 52 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 53 { 54 struct otx2_nic *pf = netdev_priv(netdev); 55 bool if_up = netif_running(netdev); 56 int err = 0; 57 58 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 59 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 60 netdev->mtu); 61 return -EINVAL; 62 } 63 if (if_up) 64 otx2_stop(netdev); 65 66 netdev_info(netdev, "Changing MTU from %d to %d\n", 67 netdev->mtu, new_mtu); 68 netdev->mtu = new_mtu; 69 70 if (if_up) 71 err = otx2_open(netdev); 72 73 return err; 74 } 75 76 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 77 { 78 int irq, vfs = pf->total_vfs; 79 80 /* Disable VFs ME interrupts */ 81 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 82 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 83 free_irq(irq, pf); 84 85 /* Disable VFs FLR interrupts */ 86 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 87 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 88 free_irq(irq, pf); 89 90 if (vfs <= 64) 91 return; 92 93 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 94 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 95 free_irq(irq, pf); 96 97 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 98 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 99 free_irq(irq, pf); 100 } 101 102 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 103 { 104 if (!pf->flr_wq) 105 return; 106 destroy_workqueue(pf->flr_wq); 107 pf->flr_wq = NULL; 108 devm_kfree(pf->dev, pf->flr_wrk); 109 } 110 111 static void otx2_flr_handler(struct work_struct *work) 112 { 113 struct flr_work *flrwork = container_of(work, struct flr_work, work); 114 struct otx2_nic *pf = flrwork->pf; 115 struct mbox *mbox = &pf->mbox; 116 struct msg_req *req; 117 int vf, reg = 0; 118 119 vf = flrwork - pf->flr_wrk; 120 121 mutex_lock(&mbox->lock); 122 req = otx2_mbox_alloc_msg_vf_flr(mbox); 123 if (!req) { 124 mutex_unlock(&mbox->lock); 125 return; 126 } 127 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 128 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 129 130 if (!otx2_sync_mbox_msg(&pf->mbox)) { 131 if (vf >= 64) { 132 reg = 1; 133 vf = vf - 64; 134 } 135 /* clear transcation pending bit */ 136 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 137 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 138 } 139 140 mutex_unlock(&mbox->lock); 141 } 142 143 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 144 { 145 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 146 int reg, dev, vf, start_vf, num_reg = 1; 147 u64 intr; 148 149 if (pf->total_vfs > 64) 150 num_reg = 2; 151 152 for (reg = 0; reg < num_reg; reg++) { 153 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 154 if (!intr) 155 continue; 156 start_vf = 64 * reg; 157 for (vf = 0; vf < 64; vf++) { 158 if (!(intr & BIT_ULL(vf))) 159 continue; 160 dev = vf + start_vf; 161 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 162 /* Clear interrupt */ 163 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 164 /* Disable the interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 166 BIT_ULL(vf)); 167 } 168 } 169 return IRQ_HANDLED; 170 } 171 172 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 173 { 174 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 175 int vf, reg, num_reg = 1; 176 u64 intr; 177 178 if (pf->total_vfs > 64) 179 num_reg = 2; 180 181 for (reg = 0; reg < num_reg; reg++) { 182 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 183 if (!intr) 184 continue; 185 for (vf = 0; vf < 64; vf++) { 186 if (!(intr & BIT_ULL(vf))) 187 continue; 188 /* clear trpend bit */ 189 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 190 /* clear interrupt */ 191 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 192 } 193 } 194 return IRQ_HANDLED; 195 } 196 197 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 198 { 199 struct otx2_hw *hw = &pf->hw; 200 char *irq_name; 201 int ret; 202 203 /* Register ME interrupt handler*/ 204 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 205 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 206 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 207 otx2_pf_me_intr_handler, 0, irq_name, pf); 208 if (ret) { 209 dev_err(pf->dev, 210 "RVUPF: IRQ registration failed for ME0\n"); 211 } 212 213 /* Register FLR interrupt handler */ 214 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 215 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 216 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 217 otx2_pf_flr_intr_handler, 0, irq_name, pf); 218 if (ret) { 219 dev_err(pf->dev, 220 "RVUPF: IRQ registration failed for FLR0\n"); 221 return ret; 222 } 223 224 if (numvfs > 64) { 225 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 226 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 227 rvu_get_pf(pf->pcifunc)); 228 ret = request_irq(pci_irq_vector 229 (pf->pdev, RVU_PF_INT_VEC_VFME1), 230 otx2_pf_me_intr_handler, 0, irq_name, pf); 231 if (ret) { 232 dev_err(pf->dev, 233 "RVUPF: IRQ registration failed for ME1\n"); 234 } 235 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 236 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 237 rvu_get_pf(pf->pcifunc)); 238 ret = request_irq(pci_irq_vector 239 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 240 otx2_pf_flr_intr_handler, 0, irq_name, pf); 241 if (ret) { 242 dev_err(pf->dev, 243 "RVUPF: IRQ registration failed for FLR1\n"); 244 return ret; 245 } 246 } 247 248 /* Enable ME interrupt for all VFs*/ 249 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 250 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 251 252 /* Enable FLR interrupt for all VFs*/ 253 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 255 256 if (numvfs > 64) { 257 numvfs -= 64; 258 259 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 260 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 261 INTR_MASK(numvfs)); 262 263 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 264 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 265 INTR_MASK(numvfs)); 266 } 267 return 0; 268 } 269 270 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 271 { 272 int vf; 273 274 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 275 WQ_UNBOUND | WQ_HIGHPRI, 1); 276 if (!pf->flr_wq) 277 return -ENOMEM; 278 279 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 280 sizeof(struct flr_work), GFP_KERNEL); 281 if (!pf->flr_wrk) { 282 destroy_workqueue(pf->flr_wq); 283 return -ENOMEM; 284 } 285 286 for (vf = 0; vf < num_vfs; vf++) { 287 pf->flr_wrk[vf].pf = pf; 288 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 289 } 290 291 return 0; 292 } 293 294 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 295 int first, int mdevs, u64 intr, int type) 296 { 297 struct otx2_mbox_dev *mdev; 298 struct otx2_mbox *mbox; 299 struct mbox_hdr *hdr; 300 int i; 301 302 for (i = first; i < mdevs; i++) { 303 /* start from 0 */ 304 if (!(intr & BIT_ULL(i - first))) 305 continue; 306 307 mbox = &mw->mbox; 308 mdev = &mbox->dev[i]; 309 if (type == TYPE_PFAF) 310 otx2_sync_mbox_bbuf(mbox, i); 311 hdr = mdev->mbase + mbox->rx_start; 312 /* The hdr->num_msgs is set to zero immediately in the interrupt 313 * handler to ensure that it holds a correct value next time 314 * when the interrupt handler is called. 315 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 316 * pf>mbox.up_num_msgs holds the data for use in 317 * pfaf_mbox_up_handler. 318 */ 319 if (hdr->num_msgs) { 320 mw[i].num_msgs = hdr->num_msgs; 321 hdr->num_msgs = 0; 322 if (type == TYPE_PFAF) 323 memset(mbox->hwbase + mbox->rx_start, 0, 324 ALIGN(sizeof(struct mbox_hdr), 325 sizeof(u64))); 326 327 queue_work(mbox_wq, &mw[i].mbox_wrk); 328 } 329 330 mbox = &mw->mbox_up; 331 mdev = &mbox->dev[i]; 332 if (type == TYPE_PFAF) 333 otx2_sync_mbox_bbuf(mbox, i); 334 hdr = mdev->mbase + mbox->rx_start; 335 if (hdr->num_msgs) { 336 mw[i].up_num_msgs = hdr->num_msgs; 337 hdr->num_msgs = 0; 338 if (type == TYPE_PFAF) 339 memset(mbox->hwbase + mbox->rx_start, 0, 340 ALIGN(sizeof(struct mbox_hdr), 341 sizeof(u64))); 342 343 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 344 } 345 } 346 } 347 348 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 349 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 350 int devid) 351 { 352 struct otx2_mbox_dev *src_mdev = mdev; 353 int offset; 354 355 /* Msgs are already copied, trigger VF's mbox irq */ 356 smp_wmb(); 357 358 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 359 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 360 361 /* Restore VF's mbox bounce buffer region address */ 362 src_mdev->mbase = bbuf_base; 363 } 364 365 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 366 struct otx2_mbox *src_mbox, 367 int dir, int vf, int num_msgs) 368 { 369 struct otx2_mbox_dev *src_mdev, *dst_mdev; 370 struct mbox_hdr *mbox_hdr; 371 struct mbox_hdr *req_hdr; 372 struct mbox *dst_mbox; 373 int dst_size, err; 374 375 if (dir == MBOX_DIR_PFAF) { 376 /* Set VF's mailbox memory as PF's bounce buffer memory, so 377 * that explicit copying of VF's msgs to PF=>AF mbox region 378 * and AF=>PF responses to VF's mbox region can be avoided. 379 */ 380 src_mdev = &src_mbox->dev[vf]; 381 mbox_hdr = src_mbox->hwbase + 382 src_mbox->rx_start + (vf * MBOX_SIZE); 383 384 dst_mbox = &pf->mbox; 385 dst_size = dst_mbox->mbox.tx_size - 386 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 387 /* Check if msgs fit into destination area and has valid size */ 388 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 389 return -EINVAL; 390 391 dst_mdev = &dst_mbox->mbox.dev[0]; 392 393 mutex_lock(&pf->mbox.lock); 394 dst_mdev->mbase = src_mdev->mbase; 395 dst_mdev->msg_size = mbox_hdr->msg_size; 396 dst_mdev->num_msgs = num_msgs; 397 err = otx2_sync_mbox_msg(dst_mbox); 398 /* Error code -EIO indicate there is a communication failure 399 * to the AF. Rest of the error codes indicate that AF processed 400 * VF messages and set the error codes in response messages 401 * (if any) so simply forward responses to VF. 402 */ 403 if (err == -EIO) { 404 dev_warn(pf->dev, 405 "AF not responding to VF%d messages\n", vf); 406 /* restore PF mbase and exit */ 407 dst_mdev->mbase = pf->mbox.bbuf_base; 408 mutex_unlock(&pf->mbox.lock); 409 return err; 410 } 411 /* At this point, all the VF messages sent to AF are acked 412 * with proper responses and responses are copied to VF 413 * mailbox hence raise interrupt to VF. 414 */ 415 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 416 dst_mbox->mbox.rx_start); 417 req_hdr->num_msgs = num_msgs; 418 419 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 420 pf->mbox.bbuf_base, vf); 421 mutex_unlock(&pf->mbox.lock); 422 } else if (dir == MBOX_DIR_PFVF_UP) { 423 src_mdev = &src_mbox->dev[0]; 424 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 425 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 426 src_mbox->rx_start); 427 req_hdr->num_msgs = num_msgs; 428 429 dst_mbox = &pf->mbox_pfvf[0]; 430 dst_size = dst_mbox->mbox_up.tx_size - 431 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 432 /* Check if msgs fit into destination area */ 433 if (mbox_hdr->msg_size > dst_size) 434 return -EINVAL; 435 436 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 437 dst_mdev->mbase = src_mdev->mbase; 438 dst_mdev->msg_size = mbox_hdr->msg_size; 439 dst_mdev->num_msgs = mbox_hdr->num_msgs; 440 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 441 if (err) { 442 dev_warn(pf->dev, 443 "VF%d is not responding to mailbox\n", vf); 444 return err; 445 } 446 } else if (dir == MBOX_DIR_VFPF_UP) { 447 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 448 src_mbox->rx_start); 449 req_hdr->num_msgs = num_msgs; 450 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 451 &pf->mbox.mbox_up, 452 pf->mbox_pfvf[vf].bbuf_base, 453 0); 454 } 455 456 return 0; 457 } 458 459 static void otx2_pfvf_mbox_handler(struct work_struct *work) 460 { 461 struct mbox_msghdr *msg = NULL; 462 int offset, vf_idx, id, err; 463 struct otx2_mbox_dev *mdev; 464 struct mbox_hdr *req_hdr; 465 struct otx2_mbox *mbox; 466 struct mbox *vf_mbox; 467 struct otx2_nic *pf; 468 469 vf_mbox = container_of(work, struct mbox, mbox_wrk); 470 pf = vf_mbox->pfvf; 471 vf_idx = vf_mbox - pf->mbox_pfvf; 472 473 mbox = &pf->mbox_pfvf[0].mbox; 474 mdev = &mbox->dev[vf_idx]; 475 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 476 477 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 478 479 for (id = 0; id < vf_mbox->num_msgs; id++) { 480 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 481 offset); 482 483 if (msg->sig != OTX2_MBOX_REQ_SIG) 484 goto inval_msg; 485 486 /* Set VF's number in each of the msg */ 487 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 488 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 489 offset = msg->next_msgoff; 490 } 491 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 492 vf_mbox->num_msgs); 493 if (err) 494 goto inval_msg; 495 return; 496 497 inval_msg: 498 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 499 otx2_mbox_msg_send(mbox, vf_idx); 500 } 501 502 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 503 { 504 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 505 struct otx2_nic *pf = vf_mbox->pfvf; 506 struct otx2_mbox_dev *mdev; 507 int offset, id, vf_idx = 0; 508 struct mbox_hdr *rsp_hdr; 509 struct mbox_msghdr *msg; 510 struct otx2_mbox *mbox; 511 512 vf_idx = vf_mbox - pf->mbox_pfvf; 513 mbox = &pf->mbox_pfvf[0].mbox_up; 514 mdev = &mbox->dev[vf_idx]; 515 516 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 517 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 518 519 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 520 msg = mdev->mbase + offset; 521 522 if (msg->id >= MBOX_MSG_MAX) { 523 dev_err(pf->dev, 524 "Mbox msg with unknown ID 0x%x\n", msg->id); 525 goto end; 526 } 527 528 if (msg->sig != OTX2_MBOX_RSP_SIG) { 529 dev_err(pf->dev, 530 "Mbox msg with wrong signature %x, ID 0x%x\n", 531 msg->sig, msg->id); 532 goto end; 533 } 534 535 switch (msg->id) { 536 case MBOX_MSG_CGX_LINK_EVENT: 537 break; 538 default: 539 if (msg->rc) 540 dev_err(pf->dev, 541 "Mbox msg response has err %d, ID 0x%x\n", 542 msg->rc, msg->id); 543 break; 544 } 545 546 end: 547 offset = mbox->rx_start + msg->next_msgoff; 548 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 549 __otx2_mbox_reset(mbox, 0); 550 mdev->msgs_acked++; 551 } 552 } 553 554 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 555 { 556 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 557 int vfs = pf->total_vfs; 558 struct mbox *mbox; 559 u64 intr; 560 561 mbox = pf->mbox_pfvf; 562 /* Handle VF interrupts */ 563 if (vfs > 64) { 564 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 565 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 566 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 567 TYPE_PFVF); 568 vfs -= 64; 569 } 570 571 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 572 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 573 574 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 575 576 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 577 578 return IRQ_HANDLED; 579 } 580 581 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 582 { 583 void __iomem *hwbase; 584 struct mbox *mbox; 585 int err, vf; 586 u64 base; 587 588 if (!numvfs) 589 return -EINVAL; 590 591 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 592 sizeof(struct mbox), GFP_KERNEL); 593 if (!pf->mbox_pfvf) 594 return -ENOMEM; 595 596 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 597 WQ_UNBOUND | WQ_HIGHPRI | 598 WQ_MEM_RECLAIM, 1); 599 if (!pf->mbox_pfvf_wq) 600 return -ENOMEM; 601 602 /* On CN10K platform, PF <-> VF mailbox region follows after 603 * PF <-> AF mailbox region. 604 */ 605 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 606 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 607 MBOX_SIZE; 608 else 609 base = readq((void __iomem *)((u64)pf->reg_base + 610 RVU_PF_VF_BAR4_ADDR)); 611 612 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 613 if (!hwbase) { 614 err = -ENOMEM; 615 goto free_wq; 616 } 617 618 mbox = &pf->mbox_pfvf[0]; 619 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 620 MBOX_DIR_PFVF, numvfs); 621 if (err) 622 goto free_iomem; 623 624 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 625 MBOX_DIR_PFVF_UP, numvfs); 626 if (err) 627 goto free_iomem; 628 629 for (vf = 0; vf < numvfs; vf++) { 630 mbox->pfvf = pf; 631 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 632 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 633 mbox++; 634 } 635 636 return 0; 637 638 free_iomem: 639 if (hwbase) 640 iounmap(hwbase); 641 free_wq: 642 destroy_workqueue(pf->mbox_pfvf_wq); 643 return err; 644 } 645 646 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 647 { 648 struct mbox *mbox = &pf->mbox_pfvf[0]; 649 650 if (!mbox) 651 return; 652 653 if (pf->mbox_pfvf_wq) { 654 destroy_workqueue(pf->mbox_pfvf_wq); 655 pf->mbox_pfvf_wq = NULL; 656 } 657 658 if (mbox->mbox.hwbase) 659 iounmap(mbox->mbox.hwbase); 660 661 otx2_mbox_destroy(&mbox->mbox); 662 } 663 664 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 665 { 666 /* Clear PF <=> VF mailbox IRQ */ 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 668 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 669 670 /* Enable PF <=> VF mailbox IRQ */ 671 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 672 if (numvfs > 64) { 673 numvfs -= 64; 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 675 INTR_MASK(numvfs)); 676 } 677 } 678 679 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 680 { 681 int vector; 682 683 /* Disable PF <=> VF mailbox IRQ */ 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 685 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 686 687 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 688 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 689 free_irq(vector, pf); 690 691 if (numvfs > 64) { 692 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 693 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 694 free_irq(vector, pf); 695 } 696 } 697 698 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 699 { 700 struct otx2_hw *hw = &pf->hw; 701 char *irq_name; 702 int err; 703 704 /* Register MBOX0 interrupt handler */ 705 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 706 if (pf->pcifunc) 707 snprintf(irq_name, NAME_SIZE, 708 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 709 else 710 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 711 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 712 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 713 if (err) { 714 dev_err(pf->dev, 715 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 716 return err; 717 } 718 719 if (numvfs > 64) { 720 /* Register MBOX1 interrupt handler */ 721 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 722 if (pf->pcifunc) 723 snprintf(irq_name, NAME_SIZE, 724 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 725 else 726 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 727 err = request_irq(pci_irq_vector(pf->pdev, 728 RVU_PF_INT_VEC_VFPF_MBOX1), 729 otx2_pfvf_mbox_intr_handler, 730 0, irq_name, pf); 731 if (err) { 732 dev_err(pf->dev, 733 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 734 return err; 735 } 736 } 737 738 otx2_enable_pfvf_mbox_intr(pf, numvfs); 739 740 return 0; 741 } 742 743 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 744 struct mbox_msghdr *msg) 745 { 746 int devid; 747 748 if (msg->id >= MBOX_MSG_MAX) { 749 dev_err(pf->dev, 750 "Mbox msg with unknown ID 0x%x\n", msg->id); 751 return; 752 } 753 754 if (msg->sig != OTX2_MBOX_RSP_SIG) { 755 dev_err(pf->dev, 756 "Mbox msg with wrong signature %x, ID 0x%x\n", 757 msg->sig, msg->id); 758 return; 759 } 760 761 /* message response heading VF */ 762 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 763 if (devid) { 764 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 765 struct delayed_work *dwork; 766 767 switch (msg->id) { 768 case MBOX_MSG_NIX_LF_START_RX: 769 config->intf_down = false; 770 dwork = &config->link_event_work; 771 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 772 break; 773 case MBOX_MSG_NIX_LF_STOP_RX: 774 config->intf_down = true; 775 break; 776 } 777 778 return; 779 } 780 781 switch (msg->id) { 782 case MBOX_MSG_READY: 783 pf->pcifunc = msg->pcifunc; 784 break; 785 case MBOX_MSG_MSIX_OFFSET: 786 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 787 break; 788 case MBOX_MSG_NPA_LF_ALLOC: 789 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 790 break; 791 case MBOX_MSG_NIX_LF_ALLOC: 792 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 793 break; 794 case MBOX_MSG_NIX_TXSCH_ALLOC: 795 mbox_handler_nix_txsch_alloc(pf, 796 (struct nix_txsch_alloc_rsp *)msg); 797 break; 798 case MBOX_MSG_NIX_BP_ENABLE: 799 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 800 break; 801 case MBOX_MSG_CGX_STATS: 802 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 803 break; 804 case MBOX_MSG_CGX_FEC_STATS: 805 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 806 break; 807 default: 808 if (msg->rc) 809 dev_err(pf->dev, 810 "Mbox msg response has err %d, ID 0x%x\n", 811 msg->rc, msg->id); 812 break; 813 } 814 } 815 816 static void otx2_pfaf_mbox_handler(struct work_struct *work) 817 { 818 struct otx2_mbox_dev *mdev; 819 struct mbox_hdr *rsp_hdr; 820 struct mbox_msghdr *msg; 821 struct otx2_mbox *mbox; 822 struct mbox *af_mbox; 823 struct otx2_nic *pf; 824 int offset, id; 825 826 af_mbox = container_of(work, struct mbox, mbox_wrk); 827 mbox = &af_mbox->mbox; 828 mdev = &mbox->dev[0]; 829 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 830 831 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 832 pf = af_mbox->pfvf; 833 834 for (id = 0; id < af_mbox->num_msgs; id++) { 835 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 836 otx2_process_pfaf_mbox_msg(pf, msg); 837 offset = mbox->rx_start + msg->next_msgoff; 838 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 839 __otx2_mbox_reset(mbox, 0); 840 mdev->msgs_acked++; 841 } 842 843 } 844 845 static void otx2_handle_link_event(struct otx2_nic *pf) 846 { 847 struct cgx_link_user_info *linfo = &pf->linfo; 848 struct net_device *netdev = pf->netdev; 849 850 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 851 linfo->link_up ? "UP" : "DOWN", linfo->speed, 852 linfo->full_duplex ? "Full" : "Half"); 853 if (linfo->link_up) { 854 netif_carrier_on(netdev); 855 netif_tx_start_all_queues(netdev); 856 } else { 857 netif_tx_stop_all_queues(netdev); 858 netif_carrier_off(netdev); 859 } 860 } 861 862 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 863 struct mcs_intr_info *event, 864 struct msg_rsp *rsp) 865 { 866 cn10k_handle_mcs_event(pf, event); 867 868 return 0; 869 } 870 871 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 872 struct cgx_link_info_msg *msg, 873 struct msg_rsp *rsp) 874 { 875 int i; 876 877 /* Copy the link info sent by AF */ 878 pf->linfo = msg->link_info; 879 880 /* notify VFs about link event */ 881 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 882 struct otx2_vf_config *config = &pf->vf_configs[i]; 883 struct delayed_work *dwork = &config->link_event_work; 884 885 if (config->intf_down) 886 continue; 887 888 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 889 } 890 891 /* interface has not been fully configured yet */ 892 if (pf->flags & OTX2_FLAG_INTF_DOWN) 893 return 0; 894 895 otx2_handle_link_event(pf); 896 return 0; 897 } 898 899 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 900 struct mbox_msghdr *req) 901 { 902 /* Check if valid, if not reply with a invalid msg */ 903 if (req->sig != OTX2_MBOX_REQ_SIG) { 904 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 905 return -ENODEV; 906 } 907 908 switch (req->id) { 909 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 910 case _id: { \ 911 struct _rsp_type *rsp; \ 912 int err; \ 913 \ 914 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 915 &pf->mbox.mbox_up, 0, \ 916 sizeof(struct _rsp_type)); \ 917 if (!rsp) \ 918 return -ENOMEM; \ 919 \ 920 rsp->hdr.id = _id; \ 921 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 922 rsp->hdr.pcifunc = 0; \ 923 rsp->hdr.rc = 0; \ 924 \ 925 err = otx2_mbox_up_handler_ ## _fn_name( \ 926 pf, (struct _req_type *)req, rsp); \ 927 return err; \ 928 } 929 MBOX_UP_CGX_MESSAGES 930 MBOX_UP_MCS_MESSAGES 931 #undef M 932 break; 933 default: 934 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 935 return -ENODEV; 936 } 937 return 0; 938 } 939 940 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 941 { 942 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 943 struct otx2_mbox *mbox = &af_mbox->mbox_up; 944 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 945 struct otx2_nic *pf = af_mbox->pfvf; 946 int offset, id, devid = 0; 947 struct mbox_hdr *rsp_hdr; 948 struct mbox_msghdr *msg; 949 950 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 951 952 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 953 954 for (id = 0; id < af_mbox->up_num_msgs; id++) { 955 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 956 957 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 958 /* Skip processing VF's messages */ 959 if (!devid) 960 otx2_process_mbox_msg_up(pf, msg); 961 offset = mbox->rx_start + msg->next_msgoff; 962 } 963 if (devid) { 964 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 965 MBOX_DIR_PFVF_UP, devid - 1, 966 af_mbox->up_num_msgs); 967 return; 968 } 969 970 otx2_mbox_msg_send(mbox, 0); 971 } 972 973 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 974 { 975 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 976 struct mbox *mbox; 977 978 /* Clear the IRQ */ 979 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 980 981 mbox = &pf->mbox; 982 983 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 984 985 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 986 987 return IRQ_HANDLED; 988 } 989 990 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 991 { 992 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 993 994 /* Disable AF => PF mailbox IRQ */ 995 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 996 free_irq(vector, pf); 997 } 998 999 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1000 { 1001 struct otx2_hw *hw = &pf->hw; 1002 struct msg_req *req; 1003 char *irq_name; 1004 int err; 1005 1006 /* Register mailbox interrupt handler */ 1007 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1008 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1009 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1010 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1011 if (err) { 1012 dev_err(pf->dev, 1013 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1014 return err; 1015 } 1016 1017 /* Enable mailbox interrupt for msgs coming from AF. 1018 * First clear to avoid spurious interrupts, if any. 1019 */ 1020 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1021 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1022 1023 if (!probe_af) 1024 return 0; 1025 1026 /* Check mailbox communication with AF */ 1027 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1028 if (!req) { 1029 otx2_disable_mbox_intr(pf); 1030 return -ENOMEM; 1031 } 1032 err = otx2_sync_mbox_msg(&pf->mbox); 1033 if (err) { 1034 dev_warn(pf->dev, 1035 "AF not responding to mailbox, deferring probe\n"); 1036 otx2_disable_mbox_intr(pf); 1037 return -EPROBE_DEFER; 1038 } 1039 1040 return 0; 1041 } 1042 1043 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1044 { 1045 struct mbox *mbox = &pf->mbox; 1046 1047 if (pf->mbox_wq) { 1048 destroy_workqueue(pf->mbox_wq); 1049 pf->mbox_wq = NULL; 1050 } 1051 1052 if (mbox->mbox.hwbase) 1053 iounmap((void __iomem *)mbox->mbox.hwbase); 1054 1055 otx2_mbox_destroy(&mbox->mbox); 1056 otx2_mbox_destroy(&mbox->mbox_up); 1057 } 1058 1059 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1060 { 1061 struct mbox *mbox = &pf->mbox; 1062 void __iomem *hwbase; 1063 int err; 1064 1065 mbox->pfvf = pf; 1066 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1067 WQ_UNBOUND | WQ_HIGHPRI | 1068 WQ_MEM_RECLAIM, 1); 1069 if (!pf->mbox_wq) 1070 return -ENOMEM; 1071 1072 /* Mailbox is a reserved memory (in RAM) region shared between 1073 * admin function (i.e AF) and this PF, shouldn't be mapped as 1074 * device memory to allow unaligned accesses. 1075 */ 1076 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1077 MBOX_SIZE); 1078 if (!hwbase) { 1079 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1080 err = -ENOMEM; 1081 goto exit; 1082 } 1083 1084 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1085 MBOX_DIR_PFAF, 1); 1086 if (err) 1087 goto exit; 1088 1089 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1090 MBOX_DIR_PFAF_UP, 1); 1091 if (err) 1092 goto exit; 1093 1094 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1095 if (err) 1096 goto exit; 1097 1098 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1099 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1100 mutex_init(&mbox->lock); 1101 1102 return 0; 1103 exit: 1104 otx2_pfaf_mbox_destroy(pf); 1105 return err; 1106 } 1107 1108 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1109 { 1110 struct msg_req *msg; 1111 int err; 1112 1113 mutex_lock(&pf->mbox.lock); 1114 if (enable) 1115 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1116 else 1117 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1118 1119 if (!msg) { 1120 mutex_unlock(&pf->mbox.lock); 1121 return -ENOMEM; 1122 } 1123 1124 err = otx2_sync_mbox_msg(&pf->mbox); 1125 mutex_unlock(&pf->mbox.lock); 1126 return err; 1127 } 1128 1129 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1130 { 1131 struct msg_req *msg; 1132 int err; 1133 1134 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1135 pf->flow_cfg->dmacflt_max_flows)) 1136 netdev_warn(pf->netdev, 1137 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1138 1139 mutex_lock(&pf->mbox.lock); 1140 if (enable) 1141 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1142 else 1143 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1144 1145 if (!msg) { 1146 mutex_unlock(&pf->mbox.lock); 1147 return -ENOMEM; 1148 } 1149 1150 err = otx2_sync_mbox_msg(&pf->mbox); 1151 mutex_unlock(&pf->mbox.lock); 1152 return err; 1153 } 1154 1155 int otx2_set_real_num_queues(struct net_device *netdev, 1156 int tx_queues, int rx_queues) 1157 { 1158 int err; 1159 1160 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1161 if (err) { 1162 netdev_err(netdev, 1163 "Failed to set no of Tx queues: %d\n", tx_queues); 1164 return err; 1165 } 1166 1167 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1168 if (err) 1169 netdev_err(netdev, 1170 "Failed to set no of Rx queues: %d\n", rx_queues); 1171 return err; 1172 } 1173 EXPORT_SYMBOL(otx2_set_real_num_queues); 1174 1175 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1176 "NIX_SQOPERR_OOR", 1177 "NIX_SQOPERR_CTX_FAULT", 1178 "NIX_SQOPERR_CTX_POISON", 1179 "NIX_SQOPERR_DISABLED", 1180 "NIX_SQOPERR_SIZE_ERR", 1181 "NIX_SQOPERR_OFLOW", 1182 "NIX_SQOPERR_SQB_NULL", 1183 "NIX_SQOPERR_SQB_FAULT", 1184 "NIX_SQOPERR_SQE_SZ_ZERO", 1185 }; 1186 1187 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1188 "NIX_MNQERR_SQ_CTX_FAULT", 1189 "NIX_MNQERR_SQ_CTX_POISON", 1190 "NIX_MNQERR_SQB_FAULT", 1191 "NIX_MNQERR_SQB_POISON", 1192 "NIX_MNQERR_TOTAL_ERR", 1193 "NIX_MNQERR_LSO_ERR", 1194 "NIX_MNQERR_CQ_QUERY_ERR", 1195 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1196 "NIX_MNQERR_MAXLEN_ERR", 1197 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1198 }; 1199 1200 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1201 "NIX_SND_STATUS_GOOD", 1202 "NIX_SND_STATUS_SQ_CTX_FAULT", 1203 "NIX_SND_STATUS_SQ_CTX_POISON", 1204 "NIX_SND_STATUS_SQB_FAULT", 1205 "NIX_SND_STATUS_SQB_POISON", 1206 "NIX_SND_STATUS_HDR_ERR", 1207 "NIX_SND_STATUS_EXT_ERR", 1208 "NIX_SND_STATUS_JUMP_FAULT", 1209 "NIX_SND_STATUS_JUMP_POISON", 1210 "NIX_SND_STATUS_CRC_ERR", 1211 "NIX_SND_STATUS_IMM_ERR", 1212 "NIX_SND_STATUS_SG_ERR", 1213 "NIX_SND_STATUS_MEM_ERR", 1214 "NIX_SND_STATUS_INVALID_SUBDC", 1215 "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1216 "NIX_SND_STATUS_DATA_FAULT", 1217 "NIX_SND_STATUS_DATA_POISON", 1218 "NIX_SND_STATUS_NPC_DROP_ACTION", 1219 "NIX_SND_STATUS_LOCK_VIOL", 1220 "NIX_SND_STATUS_NPC_UCAST_CHAN_ERR", 1221 "NIX_SND_STATUS_NPC_MCAST_CHAN_ERR", 1222 "NIX_SND_STATUS_NPC_MCAST_ABORT", 1223 "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1224 "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1225 "NIX_SND_STATUS_SEND_STATS_ERR", 1226 }; 1227 1228 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1229 { 1230 struct otx2_nic *pf = data; 1231 u64 val, *ptr; 1232 u64 qidx = 0; 1233 1234 /* CQ */ 1235 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1236 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1237 val = otx2_atomic64_add((qidx << 44), ptr); 1238 1239 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1240 (val & NIX_CQERRINT_BITS)); 1241 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1242 continue; 1243 1244 if (val & BIT_ULL(42)) { 1245 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1246 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1247 } else { 1248 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1249 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1250 qidx); 1251 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1252 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1253 qidx); 1254 } 1255 1256 schedule_work(&pf->reset_task); 1257 } 1258 1259 /* SQ */ 1260 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1261 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1262 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1263 1264 /* Below debug registers captures first errors corresponding to 1265 * those registers. We don't have to check against SQ qid as 1266 * these are fatal errors. 1267 */ 1268 1269 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1270 val = otx2_atomic64_add((qidx << 44), ptr); 1271 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1272 (val & NIX_SQINT_BITS)); 1273 1274 if (val & BIT_ULL(42)) { 1275 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1276 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1277 goto done; 1278 } 1279 1280 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1281 if (!(sq_op_err_dbg & BIT(44))) 1282 goto chk_mnq_err_dbg; 1283 1284 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1285 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n", 1286 qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]); 1287 1288 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1289 1290 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1291 goto chk_mnq_err_dbg; 1292 1293 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1294 * TODO: But we are in irq context. How to call mbox functions which does sleep 1295 */ 1296 1297 chk_mnq_err_dbg: 1298 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1299 if (!(mnq_err_dbg & BIT(44))) 1300 goto chk_snd_err_dbg; 1301 1302 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1303 netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n", 1304 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]); 1305 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1306 1307 chk_snd_err_dbg: 1308 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1309 if (snd_err_dbg & BIT(44)) { 1310 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1311 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n", 1312 qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]); 1313 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1314 } 1315 1316 done: 1317 /* Print values and reset */ 1318 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1319 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1320 qidx); 1321 1322 schedule_work(&pf->reset_task); 1323 } 1324 1325 return IRQ_HANDLED; 1326 } 1327 1328 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1329 { 1330 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1331 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1332 int qidx = cq_poll->cint_idx; 1333 1334 /* Disable interrupts. 1335 * 1336 * Completion interrupts behave in a level-triggered interrupt 1337 * fashion, and hence have to be cleared only after it is serviced. 1338 */ 1339 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1340 1341 /* Schedule NAPI */ 1342 pf->napi_events++; 1343 napi_schedule_irqoff(&cq_poll->napi); 1344 1345 return IRQ_HANDLED; 1346 } 1347 1348 static void otx2_disable_napi(struct otx2_nic *pf) 1349 { 1350 struct otx2_qset *qset = &pf->qset; 1351 struct otx2_cq_poll *cq_poll; 1352 int qidx; 1353 1354 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1355 cq_poll = &qset->napi[qidx]; 1356 cancel_work_sync(&cq_poll->dim.work); 1357 napi_disable(&cq_poll->napi); 1358 netif_napi_del(&cq_poll->napi); 1359 } 1360 } 1361 1362 static void otx2_free_cq_res(struct otx2_nic *pf) 1363 { 1364 struct otx2_qset *qset = &pf->qset; 1365 struct otx2_cq_queue *cq; 1366 int qidx; 1367 1368 /* Disable CQs */ 1369 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1370 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1371 cq = &qset->cq[qidx]; 1372 qmem_free(pf->dev, cq->cqe); 1373 } 1374 } 1375 1376 static void otx2_free_sq_res(struct otx2_nic *pf) 1377 { 1378 struct otx2_qset *qset = &pf->qset; 1379 struct otx2_snd_queue *sq; 1380 int qidx; 1381 1382 /* Disable SQs */ 1383 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1384 /* Free SQB pointers */ 1385 otx2_sq_free_sqbs(pf); 1386 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1387 sq = &qset->sq[qidx]; 1388 qmem_free(pf->dev, sq->sqe); 1389 qmem_free(pf->dev, sq->tso_hdrs); 1390 kfree(sq->sg); 1391 kfree(sq->sqb_ptrs); 1392 } 1393 } 1394 1395 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1396 { 1397 int frame_size; 1398 int total_size; 1399 int rbuf_size; 1400 1401 if (pf->hw.rbuf_len) 1402 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1403 1404 /* The data transferred by NIX to memory consists of actual packet 1405 * plus additional data which has timestamp and/or EDSA/HIGIG2 1406 * headers if interface is configured in corresponding modes. 1407 * NIX transfers entire data using 6 segments/buffers and writes 1408 * a CQE_RX descriptor with those segment addresses. First segment 1409 * has additional data prepended to packet. Also software omits a 1410 * headroom of 128 bytes in each segment. Hence the total size of 1411 * memory needed to receive a packet with 'mtu' is: 1412 * frame size = mtu + additional data; 1413 * memory = frame_size + headroom * 6; 1414 * each receive buffer size = memory / 6; 1415 */ 1416 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1417 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1418 rbuf_size = total_size / 6; 1419 1420 return ALIGN(rbuf_size, 2048); 1421 } 1422 1423 static int otx2_init_hw_resources(struct otx2_nic *pf) 1424 { 1425 struct nix_lf_free_req *free_req; 1426 struct mbox *mbox = &pf->mbox; 1427 struct otx2_hw *hw = &pf->hw; 1428 struct msg_req *req; 1429 int err = 0, lvl; 1430 1431 /* Set required NPA LF's pool counts 1432 * Auras and Pools are used in a 1:1 mapping, 1433 * so, aura count = pool count. 1434 */ 1435 hw->rqpool_cnt = hw->rx_queues; 1436 hw->sqpool_cnt = hw->tot_tx_queues; 1437 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1438 1439 /* Maximum hardware supported transmit length */ 1440 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1441 1442 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1443 1444 mutex_lock(&mbox->lock); 1445 /* NPA init */ 1446 err = otx2_config_npa(pf); 1447 if (err) 1448 goto exit; 1449 1450 /* NIX init */ 1451 err = otx2_config_nix(pf); 1452 if (err) 1453 goto err_free_npa_lf; 1454 1455 /* Enable backpressure */ 1456 otx2_nix_config_bp(pf, true); 1457 1458 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1459 err = otx2_rq_aura_pool_init(pf); 1460 if (err) { 1461 mutex_unlock(&mbox->lock); 1462 goto err_free_nix_lf; 1463 } 1464 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1465 err = otx2_sq_aura_pool_init(pf); 1466 if (err) { 1467 mutex_unlock(&mbox->lock); 1468 goto err_free_rq_ptrs; 1469 } 1470 1471 err = otx2_txsch_alloc(pf); 1472 if (err) { 1473 mutex_unlock(&mbox->lock); 1474 goto err_free_sq_ptrs; 1475 } 1476 1477 #ifdef CONFIG_DCB 1478 if (pf->pfc_en) { 1479 err = otx2_pfc_txschq_alloc(pf); 1480 if (err) { 1481 mutex_unlock(&mbox->lock); 1482 goto err_free_sq_ptrs; 1483 } 1484 } 1485 #endif 1486 1487 err = otx2_config_nix_queues(pf); 1488 if (err) { 1489 mutex_unlock(&mbox->lock); 1490 goto err_free_txsch; 1491 } 1492 1493 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1494 err = otx2_txschq_config(pf, lvl, 0, false); 1495 if (err) { 1496 mutex_unlock(&mbox->lock); 1497 goto err_free_nix_queues; 1498 } 1499 } 1500 1501 #ifdef CONFIG_DCB 1502 if (pf->pfc_en) { 1503 err = otx2_pfc_txschq_config(pf); 1504 if (err) { 1505 mutex_unlock(&mbox->lock); 1506 goto err_free_nix_queues; 1507 } 1508 } 1509 #endif 1510 1511 mutex_unlock(&mbox->lock); 1512 return err; 1513 1514 err_free_nix_queues: 1515 otx2_free_sq_res(pf); 1516 otx2_free_cq_res(pf); 1517 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1518 err_free_txsch: 1519 if (otx2_txschq_stop(pf)) 1520 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1521 err_free_sq_ptrs: 1522 otx2_sq_free_sqbs(pf); 1523 err_free_rq_ptrs: 1524 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1525 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1526 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1527 otx2_aura_pool_free(pf); 1528 err_free_nix_lf: 1529 mutex_lock(&mbox->lock); 1530 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1531 if (free_req) { 1532 free_req->flags = NIX_LF_DISABLE_FLOWS; 1533 if (otx2_sync_mbox_msg(mbox)) 1534 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1535 } 1536 err_free_npa_lf: 1537 /* Reset NPA LF */ 1538 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1539 if (req) { 1540 if (otx2_sync_mbox_msg(mbox)) 1541 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1542 } 1543 exit: 1544 mutex_unlock(&mbox->lock); 1545 return err; 1546 } 1547 1548 static void otx2_free_hw_resources(struct otx2_nic *pf) 1549 { 1550 struct otx2_qset *qset = &pf->qset; 1551 struct nix_lf_free_req *free_req; 1552 struct mbox *mbox = &pf->mbox; 1553 struct otx2_cq_queue *cq; 1554 struct msg_req *req; 1555 int qidx, err; 1556 1557 /* Ensure all SQE are processed */ 1558 otx2_sqb_flush(pf); 1559 1560 /* Stop transmission */ 1561 err = otx2_txschq_stop(pf); 1562 if (err) 1563 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1564 1565 #ifdef CONFIG_DCB 1566 if (pf->pfc_en) 1567 otx2_pfc_txschq_stop(pf); 1568 #endif 1569 1570 mutex_lock(&mbox->lock); 1571 /* Disable backpressure */ 1572 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1573 otx2_nix_config_bp(pf, false); 1574 mutex_unlock(&mbox->lock); 1575 1576 /* Disable RQs */ 1577 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1578 1579 /*Dequeue all CQEs */ 1580 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1581 cq = &qset->cq[qidx]; 1582 if (cq->cq_type == CQ_RX) 1583 otx2_cleanup_rx_cqes(pf, cq); 1584 else 1585 otx2_cleanup_tx_cqes(pf, cq); 1586 } 1587 1588 otx2_free_sq_res(pf); 1589 1590 /* Free RQ buffer pointers*/ 1591 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1592 1593 otx2_free_cq_res(pf); 1594 1595 /* Free all ingress bandwidth profiles allocated */ 1596 cn10k_free_all_ipolicers(pf); 1597 1598 mutex_lock(&mbox->lock); 1599 /* Reset NIX LF */ 1600 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1601 if (free_req) { 1602 free_req->flags = NIX_LF_DISABLE_FLOWS; 1603 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1604 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1605 if (otx2_sync_mbox_msg(mbox)) 1606 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1607 } 1608 mutex_unlock(&mbox->lock); 1609 1610 /* Disable NPA Pool and Aura hw context */ 1611 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1612 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1613 otx2_aura_pool_free(pf); 1614 1615 mutex_lock(&mbox->lock); 1616 /* Reset NPA LF */ 1617 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1618 if (req) { 1619 if (otx2_sync_mbox_msg(mbox)) 1620 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1621 } 1622 mutex_unlock(&mbox->lock); 1623 } 1624 1625 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1626 { 1627 struct net_device *netdev = pf->netdev; 1628 struct nix_rx_mode *req; 1629 bool promisc = false; 1630 1631 if (!(netdev->flags & IFF_UP)) 1632 return; 1633 1634 if ((netdev->flags & IFF_PROMISC) || 1635 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1636 promisc = true; 1637 } 1638 1639 /* Write unicast address to mcam entries or del from mcam */ 1640 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1641 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1642 1643 mutex_lock(&pf->mbox.lock); 1644 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1645 if (!req) { 1646 mutex_unlock(&pf->mbox.lock); 1647 return; 1648 } 1649 1650 req->mode = NIX_RX_MODE_UCAST; 1651 1652 if (promisc) 1653 req->mode |= NIX_RX_MODE_PROMISC; 1654 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1655 req->mode |= NIX_RX_MODE_ALLMULTI; 1656 1657 req->mode |= NIX_RX_MODE_USE_MCE; 1658 1659 otx2_sync_mbox_msg(&pf->mbox); 1660 mutex_unlock(&pf->mbox.lock); 1661 } 1662 1663 static void otx2_dim_work(struct work_struct *w) 1664 { 1665 struct dim_cq_moder cur_moder; 1666 struct otx2_cq_poll *cq_poll; 1667 struct otx2_nic *pfvf; 1668 struct dim *dim; 1669 1670 dim = container_of(w, struct dim, work); 1671 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1672 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1673 pfvf = (struct otx2_nic *)cq_poll->dev; 1674 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1675 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1676 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1677 NAPI_POLL_WEIGHT : cur_moder.pkts; 1678 dim->state = DIM_START_MEASURE; 1679 } 1680 1681 int otx2_open(struct net_device *netdev) 1682 { 1683 struct otx2_nic *pf = netdev_priv(netdev); 1684 struct otx2_cq_poll *cq_poll = NULL; 1685 struct otx2_qset *qset = &pf->qset; 1686 int err = 0, qidx, vec; 1687 char *irq_name; 1688 1689 netif_carrier_off(netdev); 1690 1691 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1692 /* RQ and SQs are mapped to different CQs, 1693 * so find out max CQ IRQs (i.e CINTs) needed. 1694 */ 1695 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1696 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1697 if (!qset->napi) 1698 return -ENOMEM; 1699 1700 /* CQ size of RQ */ 1701 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1702 /* CQ size of SQ */ 1703 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1704 1705 err = -ENOMEM; 1706 qset->cq = kcalloc(pf->qset.cq_cnt, 1707 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1708 if (!qset->cq) 1709 goto err_free_mem; 1710 1711 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1712 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1713 if (!qset->sq) 1714 goto err_free_mem; 1715 1716 qset->rq = kcalloc(pf->hw.rx_queues, 1717 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1718 if (!qset->rq) 1719 goto err_free_mem; 1720 1721 err = otx2_init_hw_resources(pf); 1722 if (err) 1723 goto err_free_mem; 1724 1725 /* Register NAPI handler */ 1726 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1727 cq_poll = &qset->napi[qidx]; 1728 cq_poll->cint_idx = qidx; 1729 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1730 * 'cq_ids[0]' points to RQ's CQ and 1731 * 'cq_ids[1]' points to SQ's CQ and 1732 * 'cq_ids[2]' points to XDP's CQ and 1733 */ 1734 cq_poll->cq_ids[CQ_RX] = 1735 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1736 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1737 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1738 if (pf->xdp_prog) 1739 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1740 (qidx + pf->hw.rx_queues + 1741 pf->hw.tx_queues) : 1742 CINT_INVALID_CQ; 1743 else 1744 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1745 1746 cq_poll->dev = (void *)pf; 1747 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1748 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1749 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1750 napi_enable(&cq_poll->napi); 1751 } 1752 1753 /* Set maximum frame size allowed in HW */ 1754 err = otx2_hw_set_mtu(pf, netdev->mtu); 1755 if (err) 1756 goto err_disable_napi; 1757 1758 /* Setup segmentation algorithms, if failed, clear offload capability */ 1759 otx2_setup_segmentation(pf); 1760 1761 /* Initialize RSS */ 1762 err = otx2_rss_init(pf); 1763 if (err) 1764 goto err_disable_napi; 1765 1766 /* Register Queue IRQ handlers */ 1767 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1768 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1769 1770 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1771 1772 err = request_irq(pci_irq_vector(pf->pdev, vec), 1773 otx2_q_intr_handler, 0, irq_name, pf); 1774 if (err) { 1775 dev_err(pf->dev, 1776 "RVUPF%d: IRQ registration failed for QERR\n", 1777 rvu_get_pf(pf->pcifunc)); 1778 goto err_disable_napi; 1779 } 1780 1781 /* Enable QINT IRQ */ 1782 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1783 1784 /* Register CQ IRQ handlers */ 1785 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1786 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1787 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1788 1789 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1790 qidx); 1791 1792 err = request_irq(pci_irq_vector(pf->pdev, vec), 1793 otx2_cq_intr_handler, 0, irq_name, 1794 &qset->napi[qidx]); 1795 if (err) { 1796 dev_err(pf->dev, 1797 "RVUPF%d: IRQ registration failed for CQ%d\n", 1798 rvu_get_pf(pf->pcifunc), qidx); 1799 goto err_free_cints; 1800 } 1801 vec++; 1802 1803 otx2_config_irq_coalescing(pf, qidx); 1804 1805 /* Enable CQ IRQ */ 1806 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1807 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1808 } 1809 1810 otx2_set_cints_affinity(pf); 1811 1812 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1813 otx2_enable_rxvlan(pf, true); 1814 1815 /* When reinitializing enable time stamping if it is enabled before */ 1816 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1817 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1818 otx2_config_hw_tx_tstamp(pf, true); 1819 } 1820 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1821 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1822 otx2_config_hw_rx_tstamp(pf, true); 1823 } 1824 1825 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1826 /* 'intf_down' may be checked on any cpu */ 1827 smp_wmb(); 1828 1829 /* we have already received link status notification */ 1830 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1831 otx2_handle_link_event(pf); 1832 1833 /* Install DMAC Filters */ 1834 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1835 otx2_dmacflt_reinstall_flows(pf); 1836 1837 err = otx2_rxtx_enable(pf, true); 1838 /* If a mbox communication error happens at this point then interface 1839 * will end up in a state such that it is in down state but hardware 1840 * mcam entries are enabled to receive the packets. Hence disable the 1841 * packet I/O. 1842 */ 1843 if (err == EIO) 1844 goto err_disable_rxtx; 1845 else if (err) 1846 goto err_tx_stop_queues; 1847 1848 otx2_do_set_rx_mode(pf); 1849 1850 return 0; 1851 1852 err_disable_rxtx: 1853 otx2_rxtx_enable(pf, false); 1854 err_tx_stop_queues: 1855 netif_tx_stop_all_queues(netdev); 1856 netif_carrier_off(netdev); 1857 pf->flags |= OTX2_FLAG_INTF_DOWN; 1858 err_free_cints: 1859 otx2_free_cints(pf, qidx); 1860 vec = pci_irq_vector(pf->pdev, 1861 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1862 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1863 free_irq(vec, pf); 1864 err_disable_napi: 1865 otx2_disable_napi(pf); 1866 otx2_free_hw_resources(pf); 1867 err_free_mem: 1868 kfree(qset->sq); 1869 kfree(qset->cq); 1870 kfree(qset->rq); 1871 kfree(qset->napi); 1872 return err; 1873 } 1874 EXPORT_SYMBOL(otx2_open); 1875 1876 int otx2_stop(struct net_device *netdev) 1877 { 1878 struct otx2_nic *pf = netdev_priv(netdev); 1879 struct otx2_cq_poll *cq_poll = NULL; 1880 struct otx2_qset *qset = &pf->qset; 1881 struct otx2_rss_info *rss; 1882 int qidx, vec, wrk; 1883 1884 /* If the DOWN flag is set resources are already freed */ 1885 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1886 return 0; 1887 1888 netif_carrier_off(netdev); 1889 netif_tx_stop_all_queues(netdev); 1890 1891 pf->flags |= OTX2_FLAG_INTF_DOWN; 1892 /* 'intf_down' may be checked on any cpu */ 1893 smp_wmb(); 1894 1895 /* First stop packet Rx/Tx */ 1896 otx2_rxtx_enable(pf, false); 1897 1898 /* Clear RSS enable flag */ 1899 rss = &pf->hw.rss_info; 1900 rss->enable = false; 1901 1902 /* Cleanup Queue IRQ */ 1903 vec = pci_irq_vector(pf->pdev, 1904 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1905 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1906 free_irq(vec, pf); 1907 1908 /* Cleanup CQ NAPI and IRQ */ 1909 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1910 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1911 /* Disable interrupt */ 1912 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1913 1914 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1915 1916 cq_poll = &qset->napi[qidx]; 1917 napi_synchronize(&cq_poll->napi); 1918 vec++; 1919 } 1920 1921 netif_tx_disable(netdev); 1922 1923 otx2_free_hw_resources(pf); 1924 otx2_free_cints(pf, pf->hw.cint_cnt); 1925 otx2_disable_napi(pf); 1926 1927 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1928 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1929 1930 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1931 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1932 devm_kfree(pf->dev, pf->refill_wrk); 1933 1934 kfree(qset->sq); 1935 kfree(qset->cq); 1936 kfree(qset->rq); 1937 kfree(qset->napi); 1938 /* Do not clear RQ/SQ ringsize settings */ 1939 memset_startat(qset, 0, sqe_cnt); 1940 return 0; 1941 } 1942 EXPORT_SYMBOL(otx2_stop); 1943 1944 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1945 { 1946 struct otx2_nic *pf = netdev_priv(netdev); 1947 int qidx = skb_get_queue_mapping(skb); 1948 struct otx2_snd_queue *sq; 1949 struct netdev_queue *txq; 1950 1951 /* Check for minimum and maximum packet length */ 1952 if (skb->len <= ETH_HLEN || 1953 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1954 dev_kfree_skb(skb); 1955 return NETDEV_TX_OK; 1956 } 1957 1958 sq = &pf->qset.sq[qidx]; 1959 txq = netdev_get_tx_queue(netdev, qidx); 1960 1961 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1962 netif_tx_stop_queue(txq); 1963 1964 /* Check again, incase SQBs got freed up */ 1965 smp_mb(); 1966 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1967 > sq->sqe_thresh) 1968 netif_tx_wake_queue(txq); 1969 1970 return NETDEV_TX_BUSY; 1971 } 1972 1973 return NETDEV_TX_OK; 1974 } 1975 1976 static u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1977 struct net_device *sb_dev) 1978 { 1979 #ifdef CONFIG_DCB 1980 struct otx2_nic *pf = netdev_priv(netdev); 1981 u8 vlan_prio; 1982 #endif 1983 1984 #ifdef CONFIG_DCB 1985 if (!skb_vlan_tag_present(skb)) 1986 goto pick_tx; 1987 1988 vlan_prio = skb->vlan_tci >> 13; 1989 if ((vlan_prio > pf->hw.tx_queues - 1) || 1990 !pf->pfc_alloc_status[vlan_prio]) 1991 goto pick_tx; 1992 1993 return vlan_prio; 1994 1995 pick_tx: 1996 #endif 1997 return netdev_pick_tx(netdev, skb, NULL); 1998 } 1999 2000 static netdev_features_t otx2_fix_features(struct net_device *dev, 2001 netdev_features_t features) 2002 { 2003 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2004 features |= NETIF_F_HW_VLAN_STAG_RX; 2005 else 2006 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2007 2008 return features; 2009 } 2010 2011 static void otx2_set_rx_mode(struct net_device *netdev) 2012 { 2013 struct otx2_nic *pf = netdev_priv(netdev); 2014 2015 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2016 } 2017 2018 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2019 { 2020 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2021 2022 otx2_do_set_rx_mode(pf); 2023 } 2024 2025 static int otx2_set_features(struct net_device *netdev, 2026 netdev_features_t features) 2027 { 2028 netdev_features_t changed = features ^ netdev->features; 2029 struct otx2_nic *pf = netdev_priv(netdev); 2030 2031 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2032 return otx2_cgx_config_loopback(pf, 2033 features & NETIF_F_LOOPBACK); 2034 2035 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2036 return otx2_enable_rxvlan(pf, 2037 features & NETIF_F_HW_VLAN_CTAG_RX); 2038 2039 return otx2_handle_ntuple_tc_features(netdev, features); 2040 } 2041 2042 static void otx2_reset_task(struct work_struct *work) 2043 { 2044 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2045 2046 if (!netif_running(pf->netdev)) 2047 return; 2048 2049 rtnl_lock(); 2050 otx2_stop(pf->netdev); 2051 pf->reset_count++; 2052 otx2_open(pf->netdev); 2053 netif_trans_update(pf->netdev); 2054 rtnl_unlock(); 2055 } 2056 2057 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2058 { 2059 struct msg_req *req; 2060 int err; 2061 2062 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2063 return 0; 2064 2065 mutex_lock(&pfvf->mbox.lock); 2066 if (enable) 2067 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2068 else 2069 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2070 if (!req) { 2071 mutex_unlock(&pfvf->mbox.lock); 2072 return -ENOMEM; 2073 } 2074 2075 err = otx2_sync_mbox_msg(&pfvf->mbox); 2076 if (err) { 2077 mutex_unlock(&pfvf->mbox.lock); 2078 return err; 2079 } 2080 2081 mutex_unlock(&pfvf->mbox.lock); 2082 if (enable) 2083 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2084 else 2085 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2086 return 0; 2087 } 2088 2089 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2090 { 2091 struct msg_req *req; 2092 int err; 2093 2094 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2095 return 0; 2096 2097 mutex_lock(&pfvf->mbox.lock); 2098 if (enable) 2099 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2100 else 2101 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2102 if (!req) { 2103 mutex_unlock(&pfvf->mbox.lock); 2104 return -ENOMEM; 2105 } 2106 2107 err = otx2_sync_mbox_msg(&pfvf->mbox); 2108 if (err) { 2109 mutex_unlock(&pfvf->mbox.lock); 2110 return err; 2111 } 2112 2113 mutex_unlock(&pfvf->mbox.lock); 2114 if (enable) 2115 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2116 else 2117 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2118 return 0; 2119 } 2120 2121 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2122 { 2123 struct otx2_nic *pfvf = netdev_priv(netdev); 2124 struct hwtstamp_config config; 2125 2126 if (!pfvf->ptp) 2127 return -ENODEV; 2128 2129 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2130 return -EFAULT; 2131 2132 switch (config.tx_type) { 2133 case HWTSTAMP_TX_OFF: 2134 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2135 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2136 2137 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2138 otx2_config_hw_tx_tstamp(pfvf, false); 2139 break; 2140 case HWTSTAMP_TX_ONESTEP_SYNC: 2141 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2142 return -ERANGE; 2143 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2144 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2145 msecs_to_jiffies(500)); 2146 fallthrough; 2147 case HWTSTAMP_TX_ON: 2148 otx2_config_hw_tx_tstamp(pfvf, true); 2149 break; 2150 default: 2151 return -ERANGE; 2152 } 2153 2154 switch (config.rx_filter) { 2155 case HWTSTAMP_FILTER_NONE: 2156 otx2_config_hw_rx_tstamp(pfvf, false); 2157 break; 2158 case HWTSTAMP_FILTER_ALL: 2159 case HWTSTAMP_FILTER_SOME: 2160 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2161 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2162 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2163 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2164 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2165 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2166 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2167 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2168 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2169 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2170 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2171 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2172 otx2_config_hw_rx_tstamp(pfvf, true); 2173 config.rx_filter = HWTSTAMP_FILTER_ALL; 2174 break; 2175 default: 2176 return -ERANGE; 2177 } 2178 2179 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2180 2181 return copy_to_user(ifr->ifr_data, &config, 2182 sizeof(config)) ? -EFAULT : 0; 2183 } 2184 EXPORT_SYMBOL(otx2_config_hwtstamp); 2185 2186 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2187 { 2188 struct otx2_nic *pfvf = netdev_priv(netdev); 2189 struct hwtstamp_config *cfg = &pfvf->tstamp; 2190 2191 switch (cmd) { 2192 case SIOCSHWTSTAMP: 2193 return otx2_config_hwtstamp(netdev, req); 2194 case SIOCGHWTSTAMP: 2195 return copy_to_user(req->ifr_data, cfg, 2196 sizeof(*cfg)) ? -EFAULT : 0; 2197 default: 2198 return -EOPNOTSUPP; 2199 } 2200 } 2201 EXPORT_SYMBOL(otx2_ioctl); 2202 2203 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2204 { 2205 struct npc_install_flow_req *req; 2206 int err; 2207 2208 mutex_lock(&pf->mbox.lock); 2209 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2210 if (!req) { 2211 err = -ENOMEM; 2212 goto out; 2213 } 2214 2215 ether_addr_copy(req->packet.dmac, mac); 2216 eth_broadcast_addr((u8 *)&req->mask.dmac); 2217 req->features = BIT_ULL(NPC_DMAC); 2218 req->channel = pf->hw.rx_chan_base; 2219 req->intf = NIX_INTF_RX; 2220 req->default_rule = 1; 2221 req->append = 1; 2222 req->vf = vf + 1; 2223 req->op = NIX_RX_ACTION_DEFAULT; 2224 2225 err = otx2_sync_mbox_msg(&pf->mbox); 2226 out: 2227 mutex_unlock(&pf->mbox.lock); 2228 return err; 2229 } 2230 2231 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2232 { 2233 struct otx2_nic *pf = netdev_priv(netdev); 2234 struct pci_dev *pdev = pf->pdev; 2235 struct otx2_vf_config *config; 2236 int ret; 2237 2238 if (!netif_running(netdev)) 2239 return -EAGAIN; 2240 2241 if (vf >= pf->total_vfs) 2242 return -EINVAL; 2243 2244 if (!is_valid_ether_addr(mac)) 2245 return -EINVAL; 2246 2247 config = &pf->vf_configs[vf]; 2248 ether_addr_copy(config->mac, mac); 2249 2250 ret = otx2_do_set_vf_mac(pf, vf, mac); 2251 if (ret == 0) 2252 dev_info(&pdev->dev, 2253 "Load/Reload VF driver\n"); 2254 2255 return ret; 2256 } 2257 2258 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2259 __be16 proto) 2260 { 2261 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2262 struct nix_vtag_config_rsp *vtag_rsp; 2263 struct npc_delete_flow_req *del_req; 2264 struct nix_vtag_config *vtag_req; 2265 struct npc_install_flow_req *req; 2266 struct otx2_vf_config *config; 2267 int err = 0; 2268 u32 idx; 2269 2270 config = &pf->vf_configs[vf]; 2271 2272 if (!vlan && !config->vlan) 2273 goto out; 2274 2275 mutex_lock(&pf->mbox.lock); 2276 2277 /* free old tx vtag entry */ 2278 if (config->vlan) { 2279 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2280 if (!vtag_req) { 2281 err = -ENOMEM; 2282 goto out; 2283 } 2284 vtag_req->cfg_type = 0; 2285 vtag_req->tx.free_vtag0 = 1; 2286 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2287 2288 err = otx2_sync_mbox_msg(&pf->mbox); 2289 if (err) 2290 goto out; 2291 } 2292 2293 if (!vlan && config->vlan) { 2294 /* rx */ 2295 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2296 if (!del_req) { 2297 err = -ENOMEM; 2298 goto out; 2299 } 2300 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2301 del_req->entry = 2302 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2303 err = otx2_sync_mbox_msg(&pf->mbox); 2304 if (err) 2305 goto out; 2306 2307 /* tx */ 2308 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2309 if (!del_req) { 2310 err = -ENOMEM; 2311 goto out; 2312 } 2313 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2314 del_req->entry = 2315 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2316 err = otx2_sync_mbox_msg(&pf->mbox); 2317 2318 goto out; 2319 } 2320 2321 /* rx */ 2322 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2323 if (!req) { 2324 err = -ENOMEM; 2325 goto out; 2326 } 2327 2328 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2329 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2330 req->packet.vlan_tci = htons(vlan); 2331 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2332 /* af fills the destination mac addr */ 2333 eth_broadcast_addr((u8 *)&req->mask.dmac); 2334 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2335 req->channel = pf->hw.rx_chan_base; 2336 req->intf = NIX_INTF_RX; 2337 req->vf = vf + 1; 2338 req->op = NIX_RX_ACTION_DEFAULT; 2339 req->vtag0_valid = true; 2340 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2341 req->set_cntr = 1; 2342 2343 err = otx2_sync_mbox_msg(&pf->mbox); 2344 if (err) 2345 goto out; 2346 2347 /* tx */ 2348 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2349 if (!vtag_req) { 2350 err = -ENOMEM; 2351 goto out; 2352 } 2353 2354 /* configure tx vtag params */ 2355 vtag_req->vtag_size = VTAGSIZE_T4; 2356 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2357 vtag_req->tx.cfg_vtag0 = 1; 2358 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2359 2360 err = otx2_sync_mbox_msg(&pf->mbox); 2361 if (err) 2362 goto out; 2363 2364 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2365 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2366 if (IS_ERR(vtag_rsp)) { 2367 err = PTR_ERR(vtag_rsp); 2368 goto out; 2369 } 2370 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2371 2372 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2373 if (!req) { 2374 err = -ENOMEM; 2375 goto out; 2376 } 2377 2378 eth_zero_addr((u8 *)&req->mask.dmac); 2379 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2380 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2381 req->features = BIT_ULL(NPC_DMAC); 2382 req->channel = pf->hw.tx_chan_base; 2383 req->intf = NIX_INTF_TX; 2384 req->vf = vf + 1; 2385 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2386 req->vtag0_def = vtag_rsp->vtag0_idx; 2387 req->vtag0_op = VTAG_INSERT; 2388 req->set_cntr = 1; 2389 2390 err = otx2_sync_mbox_msg(&pf->mbox); 2391 out: 2392 config->vlan = vlan; 2393 mutex_unlock(&pf->mbox.lock); 2394 return err; 2395 } 2396 2397 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2398 __be16 proto) 2399 { 2400 struct otx2_nic *pf = netdev_priv(netdev); 2401 struct pci_dev *pdev = pf->pdev; 2402 2403 if (!netif_running(netdev)) 2404 return -EAGAIN; 2405 2406 if (vf >= pci_num_vf(pdev)) 2407 return -EINVAL; 2408 2409 /* qos is currently unsupported */ 2410 if (vlan >= VLAN_N_VID || qos) 2411 return -EINVAL; 2412 2413 if (proto != htons(ETH_P_8021Q)) 2414 return -EPROTONOSUPPORT; 2415 2416 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2417 return -EOPNOTSUPP; 2418 2419 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2420 } 2421 2422 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2423 struct ifla_vf_info *ivi) 2424 { 2425 struct otx2_nic *pf = netdev_priv(netdev); 2426 struct pci_dev *pdev = pf->pdev; 2427 struct otx2_vf_config *config; 2428 2429 if (!netif_running(netdev)) 2430 return -EAGAIN; 2431 2432 if (vf >= pci_num_vf(pdev)) 2433 return -EINVAL; 2434 2435 config = &pf->vf_configs[vf]; 2436 ivi->vf = vf; 2437 ether_addr_copy(ivi->mac, config->mac); 2438 ivi->vlan = config->vlan; 2439 ivi->trusted = config->trusted; 2440 2441 return 0; 2442 } 2443 2444 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2445 int qidx) 2446 { 2447 struct page *page; 2448 u64 dma_addr; 2449 int err = 0; 2450 2451 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2452 offset_in_page(xdpf->data), xdpf->len, 2453 DMA_TO_DEVICE); 2454 if (dma_mapping_error(pf->dev, dma_addr)) 2455 return -ENOMEM; 2456 2457 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2458 if (!err) { 2459 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2460 page = virt_to_page(xdpf->data); 2461 put_page(page); 2462 return -ENOMEM; 2463 } 2464 return 0; 2465 } 2466 2467 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2468 struct xdp_frame **frames, u32 flags) 2469 { 2470 struct otx2_nic *pf = netdev_priv(netdev); 2471 int qidx = smp_processor_id(); 2472 struct otx2_snd_queue *sq; 2473 int drops = 0, i; 2474 2475 if (!netif_running(netdev)) 2476 return -ENETDOWN; 2477 2478 qidx += pf->hw.tx_queues; 2479 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2480 2481 /* Abort xmit if xdp queue is not */ 2482 if (unlikely(!sq)) 2483 return -ENXIO; 2484 2485 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2486 return -EINVAL; 2487 2488 for (i = 0; i < n; i++) { 2489 struct xdp_frame *xdpf = frames[i]; 2490 int err; 2491 2492 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2493 if (err) 2494 drops++; 2495 } 2496 return n - drops; 2497 } 2498 2499 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2500 { 2501 struct net_device *dev = pf->netdev; 2502 bool if_up = netif_running(pf->netdev); 2503 struct bpf_prog *old_prog; 2504 2505 if (prog && dev->mtu > MAX_XDP_MTU) { 2506 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2507 return -EOPNOTSUPP; 2508 } 2509 2510 if (if_up) 2511 otx2_stop(pf->netdev); 2512 2513 old_prog = xchg(&pf->xdp_prog, prog); 2514 2515 if (old_prog) 2516 bpf_prog_put(old_prog); 2517 2518 if (pf->xdp_prog) 2519 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2520 2521 /* Network stack and XDP shared same rx queues. 2522 * Use separate tx queues for XDP and network stack. 2523 */ 2524 if (pf->xdp_prog) { 2525 pf->hw.xdp_queues = pf->hw.rx_queues; 2526 xdp_features_set_redirect_target(dev, false); 2527 } else { 2528 pf->hw.xdp_queues = 0; 2529 xdp_features_clear_redirect_target(dev); 2530 } 2531 2532 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2533 2534 if (if_up) 2535 otx2_open(pf->netdev); 2536 2537 return 0; 2538 } 2539 2540 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2541 { 2542 struct otx2_nic *pf = netdev_priv(netdev); 2543 2544 switch (xdp->command) { 2545 case XDP_SETUP_PROG: 2546 return otx2_xdp_setup(pf, xdp->prog); 2547 default: 2548 return -EINVAL; 2549 } 2550 } 2551 2552 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2553 int req_perm) 2554 { 2555 struct set_vf_perm *req; 2556 int rc; 2557 2558 mutex_lock(&pf->mbox.lock); 2559 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2560 if (!req) { 2561 rc = -ENOMEM; 2562 goto out; 2563 } 2564 2565 /* Let AF reset VF permissions as sriov is disabled */ 2566 if (req_perm == OTX2_RESET_VF_PERM) { 2567 req->flags |= RESET_VF_PERM; 2568 } else if (req_perm == OTX2_TRUSTED_VF) { 2569 if (pf->vf_configs[vf].trusted) 2570 req->flags |= VF_TRUSTED; 2571 } 2572 2573 req->vf = vf; 2574 rc = otx2_sync_mbox_msg(&pf->mbox); 2575 out: 2576 mutex_unlock(&pf->mbox.lock); 2577 return rc; 2578 } 2579 2580 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2581 bool enable) 2582 { 2583 struct otx2_nic *pf = netdev_priv(netdev); 2584 struct pci_dev *pdev = pf->pdev; 2585 int rc; 2586 2587 if (vf >= pci_num_vf(pdev)) 2588 return -EINVAL; 2589 2590 if (pf->vf_configs[vf].trusted == enable) 2591 return 0; 2592 2593 pf->vf_configs[vf].trusted = enable; 2594 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2595 2596 if (rc) 2597 pf->vf_configs[vf].trusted = !enable; 2598 else 2599 netdev_info(pf->netdev, "VF %d is %strusted\n", 2600 vf, enable ? "" : "not "); 2601 return rc; 2602 } 2603 2604 static const struct net_device_ops otx2_netdev_ops = { 2605 .ndo_open = otx2_open, 2606 .ndo_stop = otx2_stop, 2607 .ndo_start_xmit = otx2_xmit, 2608 .ndo_select_queue = otx2_select_queue, 2609 .ndo_fix_features = otx2_fix_features, 2610 .ndo_set_mac_address = otx2_set_mac_address, 2611 .ndo_change_mtu = otx2_change_mtu, 2612 .ndo_set_rx_mode = otx2_set_rx_mode, 2613 .ndo_set_features = otx2_set_features, 2614 .ndo_tx_timeout = otx2_tx_timeout, 2615 .ndo_get_stats64 = otx2_get_stats64, 2616 .ndo_eth_ioctl = otx2_ioctl, 2617 .ndo_set_vf_mac = otx2_set_vf_mac, 2618 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2619 .ndo_get_vf_config = otx2_get_vf_config, 2620 .ndo_bpf = otx2_xdp, 2621 .ndo_xdp_xmit = otx2_xdp_xmit, 2622 .ndo_setup_tc = otx2_setup_tc, 2623 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2624 }; 2625 2626 static int otx2_wq_init(struct otx2_nic *pf) 2627 { 2628 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2629 if (!pf->otx2_wq) 2630 return -ENOMEM; 2631 2632 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2633 INIT_WORK(&pf->reset_task, otx2_reset_task); 2634 return 0; 2635 } 2636 2637 static int otx2_check_pf_usable(struct otx2_nic *nic) 2638 { 2639 u64 rev; 2640 2641 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2642 rev = (rev >> 12) & 0xFF; 2643 /* Check if AF has setup revision for RVUM block, 2644 * otherwise this driver probe should be deferred 2645 * until AF driver comes up. 2646 */ 2647 if (!rev) { 2648 dev_warn(nic->dev, 2649 "AF is not initialized, deferring probe\n"); 2650 return -EPROBE_DEFER; 2651 } 2652 return 0; 2653 } 2654 2655 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2656 { 2657 struct otx2_hw *hw = &pf->hw; 2658 int num_vec, err; 2659 2660 /* NPA interrupts are inot registered, so alloc only 2661 * upto NIX vector offset. 2662 */ 2663 num_vec = hw->nix_msixoff; 2664 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2665 2666 otx2_disable_mbox_intr(pf); 2667 pci_free_irq_vectors(hw->pdev); 2668 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2669 if (err < 0) { 2670 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2671 __func__, num_vec); 2672 return err; 2673 } 2674 2675 return otx2_register_mbox_intr(pf, false); 2676 } 2677 2678 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2679 { 2680 int i; 2681 2682 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2683 sizeof(struct otx2_vf_config), 2684 GFP_KERNEL); 2685 if (!pf->vf_configs) 2686 return -ENOMEM; 2687 2688 for (i = 0; i < pf->total_vfs; i++) { 2689 pf->vf_configs[i].pf = pf; 2690 pf->vf_configs[i].intf_down = true; 2691 pf->vf_configs[i].trusted = false; 2692 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2693 otx2_vf_link_event_task); 2694 } 2695 2696 return 0; 2697 } 2698 2699 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2700 { 2701 int i; 2702 2703 if (!pf->vf_configs) 2704 return; 2705 2706 for (i = 0; i < pf->total_vfs; i++) { 2707 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2708 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2709 } 2710 } 2711 2712 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2713 { 2714 struct device *dev = &pdev->dev; 2715 struct net_device *netdev; 2716 struct otx2_nic *pf; 2717 struct otx2_hw *hw; 2718 int err, qcount; 2719 int num_vec; 2720 2721 err = pcim_enable_device(pdev); 2722 if (err) { 2723 dev_err(dev, "Failed to enable PCI device\n"); 2724 return err; 2725 } 2726 2727 err = pci_request_regions(pdev, DRV_NAME); 2728 if (err) { 2729 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2730 return err; 2731 } 2732 2733 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2734 if (err) { 2735 dev_err(dev, "DMA mask config failed, abort\n"); 2736 goto err_release_regions; 2737 } 2738 2739 pci_set_master(pdev); 2740 2741 /* Set number of queues */ 2742 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2743 2744 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2745 if (!netdev) { 2746 err = -ENOMEM; 2747 goto err_release_regions; 2748 } 2749 2750 pci_set_drvdata(pdev, netdev); 2751 SET_NETDEV_DEV(netdev, &pdev->dev); 2752 pf = netdev_priv(netdev); 2753 pf->netdev = netdev; 2754 pf->pdev = pdev; 2755 pf->dev = dev; 2756 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2757 pf->flags |= OTX2_FLAG_INTF_DOWN; 2758 2759 hw = &pf->hw; 2760 hw->pdev = pdev; 2761 hw->rx_queues = qcount; 2762 hw->tx_queues = qcount; 2763 hw->tot_tx_queues = qcount; 2764 hw->max_queues = qcount; 2765 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2766 /* Use CQE of 128 byte descriptor size by default */ 2767 hw->xqe_size = 128; 2768 2769 num_vec = pci_msix_vec_count(pdev); 2770 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2771 GFP_KERNEL); 2772 if (!hw->irq_name) { 2773 err = -ENOMEM; 2774 goto err_free_netdev; 2775 } 2776 2777 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2778 sizeof(cpumask_var_t), GFP_KERNEL); 2779 if (!hw->affinity_mask) { 2780 err = -ENOMEM; 2781 goto err_free_netdev; 2782 } 2783 2784 /* Map CSRs */ 2785 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2786 if (!pf->reg_base) { 2787 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2788 err = -ENOMEM; 2789 goto err_free_netdev; 2790 } 2791 2792 err = otx2_check_pf_usable(pf); 2793 if (err) 2794 goto err_free_netdev; 2795 2796 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2797 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2798 if (err < 0) { 2799 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2800 __func__, num_vec); 2801 goto err_free_netdev; 2802 } 2803 2804 otx2_setup_dev_hw_settings(pf); 2805 2806 /* Init PF <=> AF mailbox stuff */ 2807 err = otx2_pfaf_mbox_init(pf); 2808 if (err) 2809 goto err_free_irq_vectors; 2810 2811 /* Register mailbox interrupt */ 2812 err = otx2_register_mbox_intr(pf, true); 2813 if (err) 2814 goto err_mbox_destroy; 2815 2816 /* Request AF to attach NPA and NIX LFs to this PF. 2817 * NIX and NPA LFs are needed for this PF to function as a NIC. 2818 */ 2819 err = otx2_attach_npa_nix(pf); 2820 if (err) 2821 goto err_disable_mbox_intr; 2822 2823 err = otx2_realloc_msix_vectors(pf); 2824 if (err) 2825 goto err_detach_rsrc; 2826 2827 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2828 if (err) 2829 goto err_detach_rsrc; 2830 2831 err = cn10k_lmtst_init(pf); 2832 if (err) 2833 goto err_detach_rsrc; 2834 2835 /* Assign default mac address */ 2836 otx2_get_mac_from_af(netdev); 2837 2838 /* Don't check for error. Proceed without ptp */ 2839 otx2_ptp_init(pf); 2840 2841 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2842 * HW allocates buffer pointer from stack and uses it for DMA'ing 2843 * ingress packet. In some scenarios HW can free back allocated buffer 2844 * pointers to pool. This makes it impossible for SW to maintain a 2845 * parallel list where physical addresses of buffer pointers (IOVAs) 2846 * given to HW can be saved for later reference. 2847 * 2848 * So the only way to convert Rx packet's buffer address is to use 2849 * IOMMU's iova_to_phys() handler which translates the address by 2850 * walking through the translation tables. 2851 */ 2852 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2853 2854 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2855 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2856 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2857 NETIF_F_GSO_UDP_L4); 2858 netdev->features |= netdev->hw_features; 2859 2860 err = otx2_mcam_flow_init(pf); 2861 if (err) 2862 goto err_ptp_destroy; 2863 2864 err = cn10k_mcs_init(pf); 2865 if (err) 2866 goto err_del_mcam_entries; 2867 2868 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2869 netdev->hw_features |= NETIF_F_NTUPLE; 2870 2871 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2872 netdev->priv_flags |= IFF_UNICAST_FLT; 2873 2874 /* Support TSO on tag interface */ 2875 netdev->vlan_features |= netdev->features; 2876 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2877 NETIF_F_HW_VLAN_STAG_TX; 2878 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2879 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2880 NETIF_F_HW_VLAN_STAG_RX; 2881 netdev->features |= netdev->hw_features; 2882 2883 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2884 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2885 netdev->hw_features |= NETIF_F_HW_TC; 2886 2887 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2888 2889 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2890 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2891 2892 netdev->netdev_ops = &otx2_netdev_ops; 2893 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 2894 2895 netdev->min_mtu = OTX2_MIN_MTU; 2896 netdev->max_mtu = otx2_get_max_mtu(pf); 2897 2898 err = register_netdev(netdev); 2899 if (err) { 2900 dev_err(dev, "Failed to register netdevice\n"); 2901 goto err_mcs_free; 2902 } 2903 2904 err = otx2_wq_init(pf); 2905 if (err) 2906 goto err_unreg_netdev; 2907 2908 otx2_set_ethtool_ops(netdev); 2909 2910 err = otx2_init_tc(pf); 2911 if (err) 2912 goto err_mcam_flow_del; 2913 2914 err = otx2_register_dl(pf); 2915 if (err) 2916 goto err_mcam_flow_del; 2917 2918 /* Initialize SR-IOV resources */ 2919 err = otx2_sriov_vfcfg_init(pf); 2920 if (err) 2921 goto err_pf_sriov_init; 2922 2923 /* Enable link notifications */ 2924 otx2_cgx_config_linkevents(pf, true); 2925 2926 #ifdef CONFIG_DCB 2927 err = otx2_dcbnl_set_ops(netdev); 2928 if (err) 2929 goto err_pf_sriov_init; 2930 #endif 2931 2932 return 0; 2933 2934 err_pf_sriov_init: 2935 otx2_shutdown_tc(pf); 2936 err_mcam_flow_del: 2937 otx2_mcam_flow_del(pf); 2938 err_unreg_netdev: 2939 unregister_netdev(netdev); 2940 err_mcs_free: 2941 cn10k_mcs_free(pf); 2942 err_del_mcam_entries: 2943 otx2_mcam_flow_del(pf); 2944 err_ptp_destroy: 2945 otx2_ptp_destroy(pf); 2946 err_detach_rsrc: 2947 if (pf->hw.lmt_info) 2948 free_percpu(pf->hw.lmt_info); 2949 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2950 qmem_free(pf->dev, pf->dync_lmt); 2951 otx2_detach_resources(&pf->mbox); 2952 err_disable_mbox_intr: 2953 otx2_disable_mbox_intr(pf); 2954 err_mbox_destroy: 2955 otx2_pfaf_mbox_destroy(pf); 2956 err_free_irq_vectors: 2957 pci_free_irq_vectors(hw->pdev); 2958 err_free_netdev: 2959 pci_set_drvdata(pdev, NULL); 2960 free_netdev(netdev); 2961 err_release_regions: 2962 pci_release_regions(pdev); 2963 return err; 2964 } 2965 2966 static void otx2_vf_link_event_task(struct work_struct *work) 2967 { 2968 struct otx2_vf_config *config; 2969 struct cgx_link_info_msg *req; 2970 struct mbox_msghdr *msghdr; 2971 struct otx2_nic *pf; 2972 int vf_idx; 2973 2974 config = container_of(work, struct otx2_vf_config, 2975 link_event_work.work); 2976 vf_idx = config - config->pf->vf_configs; 2977 pf = config->pf; 2978 2979 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2980 sizeof(*req), sizeof(struct msg_rsp)); 2981 if (!msghdr) { 2982 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2983 return; 2984 } 2985 2986 req = (struct cgx_link_info_msg *)msghdr; 2987 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2988 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2989 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2990 2991 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2992 } 2993 2994 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2995 { 2996 struct net_device *netdev = pci_get_drvdata(pdev); 2997 struct otx2_nic *pf = netdev_priv(netdev); 2998 int ret; 2999 3000 /* Init PF <=> VF mailbox stuff */ 3001 ret = otx2_pfvf_mbox_init(pf, numvfs); 3002 if (ret) 3003 return ret; 3004 3005 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3006 if (ret) 3007 goto free_mbox; 3008 3009 ret = otx2_pf_flr_init(pf, numvfs); 3010 if (ret) 3011 goto free_intr; 3012 3013 ret = otx2_register_flr_me_intr(pf, numvfs); 3014 if (ret) 3015 goto free_flr; 3016 3017 ret = pci_enable_sriov(pdev, numvfs); 3018 if (ret) 3019 goto free_flr_intr; 3020 3021 return numvfs; 3022 free_flr_intr: 3023 otx2_disable_flr_me_intr(pf); 3024 free_flr: 3025 otx2_flr_wq_destroy(pf); 3026 free_intr: 3027 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3028 free_mbox: 3029 otx2_pfvf_mbox_destroy(pf); 3030 return ret; 3031 } 3032 3033 static int otx2_sriov_disable(struct pci_dev *pdev) 3034 { 3035 struct net_device *netdev = pci_get_drvdata(pdev); 3036 struct otx2_nic *pf = netdev_priv(netdev); 3037 int numvfs = pci_num_vf(pdev); 3038 3039 if (!numvfs) 3040 return 0; 3041 3042 pci_disable_sriov(pdev); 3043 3044 otx2_disable_flr_me_intr(pf); 3045 otx2_flr_wq_destroy(pf); 3046 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3047 otx2_pfvf_mbox_destroy(pf); 3048 3049 return 0; 3050 } 3051 3052 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3053 { 3054 if (numvfs == 0) 3055 return otx2_sriov_disable(pdev); 3056 else 3057 return otx2_sriov_enable(pdev, numvfs); 3058 } 3059 3060 static void otx2_remove(struct pci_dev *pdev) 3061 { 3062 struct net_device *netdev = pci_get_drvdata(pdev); 3063 struct otx2_nic *pf; 3064 3065 if (!netdev) 3066 return; 3067 3068 pf = netdev_priv(netdev); 3069 3070 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3071 3072 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3073 otx2_config_hw_tx_tstamp(pf, false); 3074 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3075 otx2_config_hw_rx_tstamp(pf, false); 3076 3077 /* Disable 802.3x pause frames */ 3078 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3079 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3080 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3081 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3082 otx2_config_pause_frm(pf); 3083 } 3084 3085 #ifdef CONFIG_DCB 3086 /* Disable PFC config */ 3087 if (pf->pfc_en) { 3088 pf->pfc_en = 0; 3089 otx2_config_priority_flow_ctrl(pf); 3090 } 3091 #endif 3092 cancel_work_sync(&pf->reset_task); 3093 /* Disable link notifications */ 3094 otx2_cgx_config_linkevents(pf, false); 3095 3096 otx2_unregister_dl(pf); 3097 unregister_netdev(netdev); 3098 cn10k_mcs_free(pf); 3099 otx2_sriov_disable(pf->pdev); 3100 otx2_sriov_vfcfg_cleanup(pf); 3101 if (pf->otx2_wq) 3102 destroy_workqueue(pf->otx2_wq); 3103 3104 otx2_ptp_destroy(pf); 3105 otx2_mcam_flow_del(pf); 3106 otx2_shutdown_tc(pf); 3107 otx2_detach_resources(&pf->mbox); 3108 if (pf->hw.lmt_info) 3109 free_percpu(pf->hw.lmt_info); 3110 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3111 qmem_free(pf->dev, pf->dync_lmt); 3112 otx2_disable_mbox_intr(pf); 3113 otx2_pfaf_mbox_destroy(pf); 3114 pci_free_irq_vectors(pf->pdev); 3115 pci_set_drvdata(pdev, NULL); 3116 free_netdev(netdev); 3117 3118 pci_release_regions(pdev); 3119 } 3120 3121 static struct pci_driver otx2_pf_driver = { 3122 .name = DRV_NAME, 3123 .id_table = otx2_pf_id_table, 3124 .probe = otx2_probe, 3125 .shutdown = otx2_remove, 3126 .remove = otx2_remove, 3127 .sriov_configure = otx2_sriov_configure 3128 }; 3129 3130 static int __init otx2_rvupf_init_module(void) 3131 { 3132 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3133 3134 return pci_register_driver(&otx2_pf_driver); 3135 } 3136 3137 static void __exit otx2_rvupf_cleanup_module(void) 3138 { 3139 pci_unregister_driver(&otx2_pf_driver); 3140 } 3141 3142 module_init(otx2_rvupf_init_module); 3143 module_exit(otx2_rvupf_cleanup_module); 3144