1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of.h> 16 #include <linux/if_vlan.h> 17 #include <linux/iommu.h> 18 #include <net/ip.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "octeontx2-nicpf" 28 #define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 enum { 42 TYPE_PFAF, 43 TYPE_PFVF, 44 }; 45 46 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 47 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 48 49 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 50 { 51 bool if_up = netif_running(netdev); 52 int err = 0; 53 54 if (if_up) 55 otx2_stop(netdev); 56 57 netdev_info(netdev, "Changing MTU from %d to %d\n", 58 netdev->mtu, new_mtu); 59 netdev->mtu = new_mtu; 60 61 if (if_up) 62 err = otx2_open(netdev); 63 64 return err; 65 } 66 67 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 68 { 69 int irq, vfs = pf->total_vfs; 70 71 /* Disable VFs ME interrupts */ 72 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 74 free_irq(irq, pf); 75 76 /* Disable VFs FLR interrupts */ 77 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 79 free_irq(irq, pf); 80 81 if (vfs <= 64) 82 return; 83 84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 86 free_irq(irq, pf); 87 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 90 free_irq(irq, pf); 91 } 92 93 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 94 { 95 if (!pf->flr_wq) 96 return; 97 destroy_workqueue(pf->flr_wq); 98 pf->flr_wq = NULL; 99 devm_kfree(pf->dev, pf->flr_wrk); 100 } 101 102 static void otx2_flr_handler(struct work_struct *work) 103 { 104 struct flr_work *flrwork = container_of(work, struct flr_work, work); 105 struct otx2_nic *pf = flrwork->pf; 106 struct mbox *mbox = &pf->mbox; 107 struct msg_req *req; 108 int vf, reg = 0; 109 110 vf = flrwork - pf->flr_wrk; 111 112 mutex_lock(&mbox->lock); 113 req = otx2_mbox_alloc_msg_vf_flr(mbox); 114 if (!req) { 115 mutex_unlock(&mbox->lock); 116 return; 117 } 118 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 119 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 120 121 if (!otx2_sync_mbox_msg(&pf->mbox)) { 122 if (vf >= 64) { 123 reg = 1; 124 vf = vf - 64; 125 } 126 /* clear transcation pending bit */ 127 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 128 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 129 } 130 131 mutex_unlock(&mbox->lock); 132 } 133 134 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 135 { 136 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 137 int reg, dev, vf, start_vf, num_reg = 1; 138 u64 intr; 139 140 if (pf->total_vfs > 64) 141 num_reg = 2; 142 143 for (reg = 0; reg < num_reg; reg++) { 144 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 145 if (!intr) 146 continue; 147 start_vf = 64 * reg; 148 for (vf = 0; vf < 64; vf++) { 149 if (!(intr & BIT_ULL(vf))) 150 continue; 151 dev = vf + start_vf; 152 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 153 /* Clear interrupt */ 154 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 155 /* Disable the interrupt */ 156 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 157 BIT_ULL(vf)); 158 } 159 } 160 return IRQ_HANDLED; 161 } 162 163 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 164 { 165 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 166 int vf, reg, num_reg = 1; 167 u64 intr; 168 169 if (pf->total_vfs > 64) 170 num_reg = 2; 171 172 for (reg = 0; reg < num_reg; reg++) { 173 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 174 if (!intr) 175 continue; 176 for (vf = 0; vf < 64; vf++) { 177 if (!(intr & BIT_ULL(vf))) 178 continue; 179 /* clear trpend bit */ 180 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 181 /* clear interrupt */ 182 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 183 } 184 } 185 return IRQ_HANDLED; 186 } 187 188 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 189 { 190 struct otx2_hw *hw = &pf->hw; 191 char *irq_name; 192 int ret; 193 194 /* Register ME interrupt handler*/ 195 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 196 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 197 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 198 otx2_pf_me_intr_handler, 0, irq_name, pf); 199 if (ret) { 200 dev_err(pf->dev, 201 "RVUPF: IRQ registration failed for ME0\n"); 202 } 203 204 /* Register FLR interrupt handler */ 205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 208 otx2_pf_flr_intr_handler, 0, irq_name, pf); 209 if (ret) { 210 dev_err(pf->dev, 211 "RVUPF: IRQ registration failed for FLR0\n"); 212 return ret; 213 } 214 215 if (numvfs > 64) { 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 218 rvu_get_pf(pf->pcifunc)); 219 ret = request_irq(pci_irq_vector 220 (pf->pdev, RVU_PF_INT_VEC_VFME1), 221 otx2_pf_me_intr_handler, 0, irq_name, pf); 222 if (ret) { 223 dev_err(pf->dev, 224 "RVUPF: IRQ registration failed for ME1\n"); 225 } 226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 228 rvu_get_pf(pf->pcifunc)); 229 ret = request_irq(pci_irq_vector 230 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 231 otx2_pf_flr_intr_handler, 0, irq_name, pf); 232 if (ret) { 233 dev_err(pf->dev, 234 "RVUPF: IRQ registration failed for FLR1\n"); 235 return ret; 236 } 237 } 238 239 /* Enable ME interrupt for all VFs*/ 240 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 241 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 242 243 /* Enable FLR interrupt for all VFs*/ 244 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 245 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 246 247 if (numvfs > 64) { 248 numvfs -= 64; 249 250 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 252 INTR_MASK(numvfs)); 253 254 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 256 INTR_MASK(numvfs)); 257 } 258 return 0; 259 } 260 261 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 262 { 263 int vf; 264 265 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 266 WQ_UNBOUND | WQ_HIGHPRI, 1); 267 if (!pf->flr_wq) 268 return -ENOMEM; 269 270 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 271 sizeof(struct flr_work), GFP_KERNEL); 272 if (!pf->flr_wrk) { 273 destroy_workqueue(pf->flr_wq); 274 return -ENOMEM; 275 } 276 277 for (vf = 0; vf < num_vfs; vf++) { 278 pf->flr_wrk[vf].pf = pf; 279 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 280 } 281 282 return 0; 283 } 284 285 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 286 int first, int mdevs, u64 intr, int type) 287 { 288 struct otx2_mbox_dev *mdev; 289 struct otx2_mbox *mbox; 290 struct mbox_hdr *hdr; 291 int i; 292 293 for (i = first; i < mdevs; i++) { 294 /* start from 0 */ 295 if (!(intr & BIT_ULL(i - first))) 296 continue; 297 298 mbox = &mw->mbox; 299 mdev = &mbox->dev[i]; 300 if (type == TYPE_PFAF) 301 otx2_sync_mbox_bbuf(mbox, i); 302 hdr = mdev->mbase + mbox->rx_start; 303 /* The hdr->num_msgs is set to zero immediately in the interrupt 304 * handler to ensure that it holds a correct value next time 305 * when the interrupt handler is called. 306 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 307 * pf>mbox.up_num_msgs holds the data for use in 308 * pfaf_mbox_up_handler. 309 */ 310 if (hdr->num_msgs) { 311 mw[i].num_msgs = hdr->num_msgs; 312 hdr->num_msgs = 0; 313 if (type == TYPE_PFAF) 314 memset(mbox->hwbase + mbox->rx_start, 0, 315 ALIGN(sizeof(struct mbox_hdr), 316 sizeof(u64))); 317 318 queue_work(mbox_wq, &mw[i].mbox_wrk); 319 } 320 321 mbox = &mw->mbox_up; 322 mdev = &mbox->dev[i]; 323 if (type == TYPE_PFAF) 324 otx2_sync_mbox_bbuf(mbox, i); 325 hdr = mdev->mbase + mbox->rx_start; 326 if (hdr->num_msgs) { 327 mw[i].up_num_msgs = hdr->num_msgs; 328 hdr->num_msgs = 0; 329 if (type == TYPE_PFAF) 330 memset(mbox->hwbase + mbox->rx_start, 0, 331 ALIGN(sizeof(struct mbox_hdr), 332 sizeof(u64))); 333 334 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 335 } 336 } 337 } 338 339 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 340 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 341 int devid) 342 { 343 struct otx2_mbox_dev *src_mdev = mdev; 344 int offset; 345 346 /* Msgs are already copied, trigger VF's mbox irq */ 347 smp_wmb(); 348 349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 350 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 351 352 /* Restore VF's mbox bounce buffer region address */ 353 src_mdev->mbase = bbuf_base; 354 } 355 356 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 357 struct otx2_mbox *src_mbox, 358 int dir, int vf, int num_msgs) 359 { 360 struct otx2_mbox_dev *src_mdev, *dst_mdev; 361 struct mbox_hdr *mbox_hdr; 362 struct mbox_hdr *req_hdr; 363 struct mbox *dst_mbox; 364 int dst_size, err; 365 366 if (dir == MBOX_DIR_PFAF) { 367 /* Set VF's mailbox memory as PF's bounce buffer memory, so 368 * that explicit copying of VF's msgs to PF=>AF mbox region 369 * and AF=>PF responses to VF's mbox region can be avoided. 370 */ 371 src_mdev = &src_mbox->dev[vf]; 372 mbox_hdr = src_mbox->hwbase + 373 src_mbox->rx_start + (vf * MBOX_SIZE); 374 375 dst_mbox = &pf->mbox; 376 dst_size = dst_mbox->mbox.tx_size - 377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 378 /* Check if msgs fit into destination area */ 379 if (mbox_hdr->msg_size > dst_size) 380 return -EINVAL; 381 382 dst_mdev = &dst_mbox->mbox.dev[0]; 383 384 mutex_lock(&pf->mbox.lock); 385 dst_mdev->mbase = src_mdev->mbase; 386 dst_mdev->msg_size = mbox_hdr->msg_size; 387 dst_mdev->num_msgs = num_msgs; 388 err = otx2_sync_mbox_msg(dst_mbox); 389 if (err) { 390 dev_warn(pf->dev, 391 "AF not responding to VF%d messages\n", vf); 392 /* restore PF mbase and exit */ 393 dst_mdev->mbase = pf->mbox.bbuf_base; 394 mutex_unlock(&pf->mbox.lock); 395 return err; 396 } 397 /* At this point, all the VF messages sent to AF are acked 398 * with proper responses and responses are copied to VF 399 * mailbox hence raise interrupt to VF. 400 */ 401 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 402 dst_mbox->mbox.rx_start); 403 req_hdr->num_msgs = num_msgs; 404 405 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 406 pf->mbox.bbuf_base, vf); 407 mutex_unlock(&pf->mbox.lock); 408 } else if (dir == MBOX_DIR_PFVF_UP) { 409 src_mdev = &src_mbox->dev[0]; 410 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 411 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 412 src_mbox->rx_start); 413 req_hdr->num_msgs = num_msgs; 414 415 dst_mbox = &pf->mbox_pfvf[0]; 416 dst_size = dst_mbox->mbox_up.tx_size - 417 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 418 /* Check if msgs fit into destination area */ 419 if (mbox_hdr->msg_size > dst_size) 420 return -EINVAL; 421 422 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 423 dst_mdev->mbase = src_mdev->mbase; 424 dst_mdev->msg_size = mbox_hdr->msg_size; 425 dst_mdev->num_msgs = mbox_hdr->num_msgs; 426 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 427 if (err) { 428 dev_warn(pf->dev, 429 "VF%d is not responding to mailbox\n", vf); 430 return err; 431 } 432 } else if (dir == MBOX_DIR_VFPF_UP) { 433 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 434 src_mbox->rx_start); 435 req_hdr->num_msgs = num_msgs; 436 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 437 &pf->mbox.mbox_up, 438 pf->mbox_pfvf[vf].bbuf_base, 439 0); 440 } 441 442 return 0; 443 } 444 445 static void otx2_pfvf_mbox_handler(struct work_struct *work) 446 { 447 struct mbox_msghdr *msg = NULL; 448 int offset, vf_idx, id, err; 449 struct otx2_mbox_dev *mdev; 450 struct mbox_hdr *req_hdr; 451 struct otx2_mbox *mbox; 452 struct mbox *vf_mbox; 453 struct otx2_nic *pf; 454 455 vf_mbox = container_of(work, struct mbox, mbox_wrk); 456 pf = vf_mbox->pfvf; 457 vf_idx = vf_mbox - pf->mbox_pfvf; 458 459 mbox = &pf->mbox_pfvf[0].mbox; 460 mdev = &mbox->dev[vf_idx]; 461 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 462 463 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 464 465 for (id = 0; id < vf_mbox->num_msgs; id++) { 466 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 467 offset); 468 469 if (msg->sig != OTX2_MBOX_REQ_SIG) 470 goto inval_msg; 471 472 /* Set VF's number in each of the msg */ 473 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 474 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 475 offset = msg->next_msgoff; 476 } 477 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 478 vf_mbox->num_msgs); 479 if (err) 480 goto inval_msg; 481 return; 482 483 inval_msg: 484 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 485 otx2_mbox_msg_send(mbox, vf_idx); 486 } 487 488 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 489 { 490 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 491 struct otx2_nic *pf = vf_mbox->pfvf; 492 struct otx2_mbox_dev *mdev; 493 int offset, id, vf_idx = 0; 494 struct mbox_hdr *rsp_hdr; 495 struct mbox_msghdr *msg; 496 struct otx2_mbox *mbox; 497 498 vf_idx = vf_mbox - pf->mbox_pfvf; 499 mbox = &pf->mbox_pfvf[0].mbox_up; 500 mdev = &mbox->dev[vf_idx]; 501 502 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 503 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 504 505 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 506 msg = mdev->mbase + offset; 507 508 if (msg->id >= MBOX_MSG_MAX) { 509 dev_err(pf->dev, 510 "Mbox msg with unknown ID 0x%x\n", msg->id); 511 goto end; 512 } 513 514 if (msg->sig != OTX2_MBOX_RSP_SIG) { 515 dev_err(pf->dev, 516 "Mbox msg with wrong signature %x, ID 0x%x\n", 517 msg->sig, msg->id); 518 goto end; 519 } 520 521 switch (msg->id) { 522 case MBOX_MSG_CGX_LINK_EVENT: 523 break; 524 default: 525 if (msg->rc) 526 dev_err(pf->dev, 527 "Mbox msg response has err %d, ID 0x%x\n", 528 msg->rc, msg->id); 529 break; 530 } 531 532 end: 533 offset = mbox->rx_start + msg->next_msgoff; 534 mdev->msgs_acked++; 535 } 536 537 otx2_mbox_reset(mbox, vf_idx); 538 } 539 540 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 541 { 542 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 543 int vfs = pf->total_vfs; 544 struct mbox *mbox; 545 u64 intr; 546 547 mbox = pf->mbox_pfvf; 548 /* Handle VF interrupts */ 549 if (vfs > 64) { 550 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 551 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 552 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 553 TYPE_PFVF); 554 vfs -= 64; 555 } 556 557 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 558 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 559 560 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 561 562 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 563 564 return IRQ_HANDLED; 565 } 566 567 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 568 { 569 void __iomem *hwbase; 570 struct mbox *mbox; 571 int err, vf; 572 u64 base; 573 574 if (!numvfs) 575 return -EINVAL; 576 577 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 578 sizeof(struct mbox), GFP_KERNEL); 579 if (!pf->mbox_pfvf) 580 return -ENOMEM; 581 582 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 583 WQ_UNBOUND | WQ_HIGHPRI | 584 WQ_MEM_RECLAIM, 1); 585 if (!pf->mbox_pfvf_wq) 586 return -ENOMEM; 587 588 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR)); 589 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 590 591 if (!hwbase) { 592 err = -ENOMEM; 593 goto free_wq; 594 } 595 596 mbox = &pf->mbox_pfvf[0]; 597 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 598 MBOX_DIR_PFVF, numvfs); 599 if (err) 600 goto free_iomem; 601 602 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 603 MBOX_DIR_PFVF_UP, numvfs); 604 if (err) 605 goto free_iomem; 606 607 for (vf = 0; vf < numvfs; vf++) { 608 mbox->pfvf = pf; 609 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 610 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 611 mbox++; 612 } 613 614 return 0; 615 616 free_iomem: 617 if (hwbase) 618 iounmap(hwbase); 619 free_wq: 620 destroy_workqueue(pf->mbox_pfvf_wq); 621 return err; 622 } 623 624 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 625 { 626 struct mbox *mbox = &pf->mbox_pfvf[0]; 627 628 if (!mbox) 629 return; 630 631 if (pf->mbox_pfvf_wq) { 632 destroy_workqueue(pf->mbox_pfvf_wq); 633 pf->mbox_pfvf_wq = NULL; 634 } 635 636 if (mbox->mbox.hwbase) 637 iounmap(mbox->mbox.hwbase); 638 639 otx2_mbox_destroy(&mbox->mbox); 640 } 641 642 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 643 { 644 /* Clear PF <=> VF mailbox IRQ */ 645 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 646 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 647 648 /* Enable PF <=> VF mailbox IRQ */ 649 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 650 if (numvfs > 64) { 651 numvfs -= 64; 652 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 653 INTR_MASK(numvfs)); 654 } 655 } 656 657 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 658 { 659 int vector; 660 661 /* Disable PF <=> VF mailbox IRQ */ 662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 664 665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 666 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 667 free_irq(vector, pf); 668 669 if (numvfs > 64) { 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 671 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 672 free_irq(vector, pf); 673 } 674 } 675 676 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 677 { 678 struct otx2_hw *hw = &pf->hw; 679 char *irq_name; 680 int err; 681 682 /* Register MBOX0 interrupt handler */ 683 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 684 if (pf->pcifunc) 685 snprintf(irq_name, NAME_SIZE, 686 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 687 else 688 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 689 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 690 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 691 if (err) { 692 dev_err(pf->dev, 693 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 694 return err; 695 } 696 697 if (numvfs > 64) { 698 /* Register MBOX1 interrupt handler */ 699 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 700 if (pf->pcifunc) 701 snprintf(irq_name, NAME_SIZE, 702 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 703 else 704 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 705 err = request_irq(pci_irq_vector(pf->pdev, 706 RVU_PF_INT_VEC_VFPF_MBOX1), 707 otx2_pfvf_mbox_intr_handler, 708 0, irq_name, pf); 709 if (err) { 710 dev_err(pf->dev, 711 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 712 return err; 713 } 714 } 715 716 otx2_enable_pfvf_mbox_intr(pf, numvfs); 717 718 return 0; 719 } 720 721 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 722 struct mbox_msghdr *msg) 723 { 724 int devid; 725 726 if (msg->id >= MBOX_MSG_MAX) { 727 dev_err(pf->dev, 728 "Mbox msg with unknown ID 0x%x\n", msg->id); 729 return; 730 } 731 732 if (msg->sig != OTX2_MBOX_RSP_SIG) { 733 dev_err(pf->dev, 734 "Mbox msg with wrong signature %x, ID 0x%x\n", 735 msg->sig, msg->id); 736 return; 737 } 738 739 /* message response heading VF */ 740 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 741 if (devid) { 742 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 743 struct delayed_work *dwork; 744 745 switch (msg->id) { 746 case MBOX_MSG_NIX_LF_START_RX: 747 config->intf_down = false; 748 dwork = &config->link_event_work; 749 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 750 break; 751 case MBOX_MSG_NIX_LF_STOP_RX: 752 config->intf_down = true; 753 break; 754 } 755 756 return; 757 } 758 759 switch (msg->id) { 760 case MBOX_MSG_READY: 761 pf->pcifunc = msg->pcifunc; 762 break; 763 case MBOX_MSG_MSIX_OFFSET: 764 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 765 break; 766 case MBOX_MSG_NPA_LF_ALLOC: 767 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 768 break; 769 case MBOX_MSG_NIX_LF_ALLOC: 770 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 771 break; 772 case MBOX_MSG_NIX_TXSCH_ALLOC: 773 mbox_handler_nix_txsch_alloc(pf, 774 (struct nix_txsch_alloc_rsp *)msg); 775 break; 776 case MBOX_MSG_NIX_BP_ENABLE: 777 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 778 break; 779 case MBOX_MSG_CGX_STATS: 780 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 781 break; 782 default: 783 if (msg->rc) 784 dev_err(pf->dev, 785 "Mbox msg response has err %d, ID 0x%x\n", 786 msg->rc, msg->id); 787 break; 788 } 789 } 790 791 static void otx2_pfaf_mbox_handler(struct work_struct *work) 792 { 793 struct otx2_mbox_dev *mdev; 794 struct mbox_hdr *rsp_hdr; 795 struct mbox_msghdr *msg; 796 struct otx2_mbox *mbox; 797 struct mbox *af_mbox; 798 struct otx2_nic *pf; 799 int offset, id; 800 801 af_mbox = container_of(work, struct mbox, mbox_wrk); 802 mbox = &af_mbox->mbox; 803 mdev = &mbox->dev[0]; 804 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 805 806 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 807 pf = af_mbox->pfvf; 808 809 for (id = 0; id < af_mbox->num_msgs; id++) { 810 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 811 otx2_process_pfaf_mbox_msg(pf, msg); 812 offset = mbox->rx_start + msg->next_msgoff; 813 mdev->msgs_acked++; 814 } 815 816 otx2_mbox_reset(mbox, 0); 817 } 818 819 static void otx2_handle_link_event(struct otx2_nic *pf) 820 { 821 struct cgx_link_user_info *linfo = &pf->linfo; 822 struct net_device *netdev = pf->netdev; 823 824 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 825 linfo->link_up ? "UP" : "DOWN", linfo->speed, 826 linfo->full_duplex ? "Full" : "Half"); 827 if (linfo->link_up) { 828 netif_carrier_on(netdev); 829 netif_tx_start_all_queues(netdev); 830 } else { 831 netif_tx_stop_all_queues(netdev); 832 netif_carrier_off(netdev); 833 } 834 } 835 836 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 837 struct cgx_link_info_msg *msg, 838 struct msg_rsp *rsp) 839 { 840 int i; 841 842 /* Copy the link info sent by AF */ 843 pf->linfo = msg->link_info; 844 845 /* notify VFs about link event */ 846 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 847 struct otx2_vf_config *config = &pf->vf_configs[i]; 848 struct delayed_work *dwork = &config->link_event_work; 849 850 if (config->intf_down) 851 continue; 852 853 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 854 } 855 856 /* interface has not been fully configured yet */ 857 if (pf->flags & OTX2_FLAG_INTF_DOWN) 858 return 0; 859 860 otx2_handle_link_event(pf); 861 return 0; 862 } 863 864 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 865 struct mbox_msghdr *req) 866 { 867 /* Check if valid, if not reply with a invalid msg */ 868 if (req->sig != OTX2_MBOX_REQ_SIG) { 869 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 870 return -ENODEV; 871 } 872 873 switch (req->id) { 874 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 875 case _id: { \ 876 struct _rsp_type *rsp; \ 877 int err; \ 878 \ 879 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 880 &pf->mbox.mbox_up, 0, \ 881 sizeof(struct _rsp_type)); \ 882 if (!rsp) \ 883 return -ENOMEM; \ 884 \ 885 rsp->hdr.id = _id; \ 886 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 887 rsp->hdr.pcifunc = 0; \ 888 rsp->hdr.rc = 0; \ 889 \ 890 err = otx2_mbox_up_handler_ ## _fn_name( \ 891 pf, (struct _req_type *)req, rsp); \ 892 return err; \ 893 } 894 MBOX_UP_CGX_MESSAGES 895 #undef M 896 break; 897 default: 898 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 899 return -ENODEV; 900 } 901 return 0; 902 } 903 904 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 905 { 906 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 907 struct otx2_mbox *mbox = &af_mbox->mbox_up; 908 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 909 struct otx2_nic *pf = af_mbox->pfvf; 910 int offset, id, devid = 0; 911 struct mbox_hdr *rsp_hdr; 912 struct mbox_msghdr *msg; 913 914 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 915 916 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 917 918 for (id = 0; id < af_mbox->up_num_msgs; id++) { 919 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 920 921 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 922 /* Skip processing VF's messages */ 923 if (!devid) 924 otx2_process_mbox_msg_up(pf, msg); 925 offset = mbox->rx_start + msg->next_msgoff; 926 } 927 if (devid) { 928 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 929 MBOX_DIR_PFVF_UP, devid - 1, 930 af_mbox->up_num_msgs); 931 return; 932 } 933 934 otx2_mbox_msg_send(mbox, 0); 935 } 936 937 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 938 { 939 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 940 struct mbox *mbox; 941 942 /* Clear the IRQ */ 943 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 944 945 mbox = &pf->mbox; 946 947 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 948 949 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 950 951 return IRQ_HANDLED; 952 } 953 954 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 955 { 956 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 957 958 /* Disable AF => PF mailbox IRQ */ 959 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 960 free_irq(vector, pf); 961 } 962 963 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 964 { 965 struct otx2_hw *hw = &pf->hw; 966 struct msg_req *req; 967 char *irq_name; 968 int err; 969 970 /* Register mailbox interrupt handler */ 971 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 972 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 973 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 974 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 975 if (err) { 976 dev_err(pf->dev, 977 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 978 return err; 979 } 980 981 /* Enable mailbox interrupt for msgs coming from AF. 982 * First clear to avoid spurious interrupts, if any. 983 */ 984 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 985 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 986 987 if (!probe_af) 988 return 0; 989 990 /* Check mailbox communication with AF */ 991 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 992 if (!req) { 993 otx2_disable_mbox_intr(pf); 994 return -ENOMEM; 995 } 996 err = otx2_sync_mbox_msg(&pf->mbox); 997 if (err) { 998 dev_warn(pf->dev, 999 "AF not responding to mailbox, deferring probe\n"); 1000 otx2_disable_mbox_intr(pf); 1001 return -EPROBE_DEFER; 1002 } 1003 1004 return 0; 1005 } 1006 1007 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1008 { 1009 struct mbox *mbox = &pf->mbox; 1010 1011 if (pf->mbox_wq) { 1012 destroy_workqueue(pf->mbox_wq); 1013 pf->mbox_wq = NULL; 1014 } 1015 1016 if (mbox->mbox.hwbase) 1017 iounmap((void __iomem *)mbox->mbox.hwbase); 1018 1019 otx2_mbox_destroy(&mbox->mbox); 1020 otx2_mbox_destroy(&mbox->mbox_up); 1021 } 1022 1023 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1024 { 1025 struct mbox *mbox = &pf->mbox; 1026 void __iomem *hwbase; 1027 int err; 1028 1029 mbox->pfvf = pf; 1030 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1031 WQ_UNBOUND | WQ_HIGHPRI | 1032 WQ_MEM_RECLAIM, 1); 1033 if (!pf->mbox_wq) 1034 return -ENOMEM; 1035 1036 /* Mailbox is a reserved memory (in RAM) region shared between 1037 * admin function (i.e AF) and this PF, shouldn't be mapped as 1038 * device memory to allow unaligned accesses. 1039 */ 1040 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1041 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM)); 1042 if (!hwbase) { 1043 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1044 err = -ENOMEM; 1045 goto exit; 1046 } 1047 1048 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1049 MBOX_DIR_PFAF, 1); 1050 if (err) 1051 goto exit; 1052 1053 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1054 MBOX_DIR_PFAF_UP, 1); 1055 if (err) 1056 goto exit; 1057 1058 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1059 if (err) 1060 goto exit; 1061 1062 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1063 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1064 mutex_init(&mbox->lock); 1065 1066 return 0; 1067 exit: 1068 otx2_pfaf_mbox_destroy(pf); 1069 return err; 1070 } 1071 1072 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1073 { 1074 struct msg_req *msg; 1075 int err; 1076 1077 mutex_lock(&pf->mbox.lock); 1078 if (enable) 1079 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1080 else 1081 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1082 1083 if (!msg) { 1084 mutex_unlock(&pf->mbox.lock); 1085 return -ENOMEM; 1086 } 1087 1088 err = otx2_sync_mbox_msg(&pf->mbox); 1089 mutex_unlock(&pf->mbox.lock); 1090 return err; 1091 } 1092 1093 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1094 { 1095 struct msg_req *msg; 1096 int err; 1097 1098 mutex_lock(&pf->mbox.lock); 1099 if (enable) 1100 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1101 else 1102 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1103 1104 if (!msg) { 1105 mutex_unlock(&pf->mbox.lock); 1106 return -ENOMEM; 1107 } 1108 1109 err = otx2_sync_mbox_msg(&pf->mbox); 1110 mutex_unlock(&pf->mbox.lock); 1111 return err; 1112 } 1113 1114 int otx2_set_real_num_queues(struct net_device *netdev, 1115 int tx_queues, int rx_queues) 1116 { 1117 int err; 1118 1119 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1120 if (err) { 1121 netdev_err(netdev, 1122 "Failed to set no of Tx queues: %d\n", tx_queues); 1123 return err; 1124 } 1125 1126 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1127 if (err) 1128 netdev_err(netdev, 1129 "Failed to set no of Rx queues: %d\n", rx_queues); 1130 return err; 1131 } 1132 EXPORT_SYMBOL(otx2_set_real_num_queues); 1133 1134 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1135 { 1136 struct otx2_nic *pf = data; 1137 u64 val, *ptr; 1138 u64 qidx = 0; 1139 1140 /* CQ */ 1141 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1142 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1143 val = otx2_atomic64_add((qidx << 44), ptr); 1144 1145 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1146 (val & NIX_CQERRINT_BITS)); 1147 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1148 continue; 1149 1150 if (val & BIT_ULL(42)) { 1151 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1152 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1153 } else { 1154 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1155 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1156 qidx); 1157 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1158 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1159 qidx); 1160 } 1161 1162 schedule_work(&pf->reset_task); 1163 } 1164 1165 /* SQ */ 1166 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1167 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1168 val = otx2_atomic64_add((qidx << 44), ptr); 1169 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1170 (val & NIX_SQINT_BITS)); 1171 1172 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1173 continue; 1174 1175 if (val & BIT_ULL(42)) { 1176 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1177 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1178 } else { 1179 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1180 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1181 qidx, 1182 otx2_read64(pf, 1183 NIX_LF_SQ_OP_ERR_DBG)); 1184 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1185 BIT_ULL(44)); 1186 } 1187 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1188 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1189 qidx, 1190 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1191 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1192 BIT_ULL(44)); 1193 } 1194 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1195 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1196 qidx, 1197 otx2_read64(pf, 1198 NIX_LF_SEND_ERR_DBG)); 1199 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1200 BIT_ULL(44)); 1201 } 1202 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1203 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1204 qidx); 1205 } 1206 1207 schedule_work(&pf->reset_task); 1208 } 1209 1210 return IRQ_HANDLED; 1211 } 1212 1213 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1214 { 1215 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1216 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1217 int qidx = cq_poll->cint_idx; 1218 1219 /* Disable interrupts. 1220 * 1221 * Completion interrupts behave in a level-triggered interrupt 1222 * fashion, and hence have to be cleared only after it is serviced. 1223 */ 1224 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1225 1226 /* Schedule NAPI */ 1227 napi_schedule_irqoff(&cq_poll->napi); 1228 1229 return IRQ_HANDLED; 1230 } 1231 1232 static void otx2_disable_napi(struct otx2_nic *pf) 1233 { 1234 struct otx2_qset *qset = &pf->qset; 1235 struct otx2_cq_poll *cq_poll; 1236 int qidx; 1237 1238 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1239 cq_poll = &qset->napi[qidx]; 1240 napi_disable(&cq_poll->napi); 1241 netif_napi_del(&cq_poll->napi); 1242 } 1243 } 1244 1245 static void otx2_free_cq_res(struct otx2_nic *pf) 1246 { 1247 struct otx2_qset *qset = &pf->qset; 1248 struct otx2_cq_queue *cq; 1249 int qidx; 1250 1251 /* Disable CQs */ 1252 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1253 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1254 cq = &qset->cq[qidx]; 1255 qmem_free(pf->dev, cq->cqe); 1256 } 1257 } 1258 1259 static void otx2_free_sq_res(struct otx2_nic *pf) 1260 { 1261 struct otx2_qset *qset = &pf->qset; 1262 struct otx2_snd_queue *sq; 1263 int qidx; 1264 1265 /* Disable SQs */ 1266 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1267 /* Free SQB pointers */ 1268 otx2_sq_free_sqbs(pf); 1269 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1270 sq = &qset->sq[qidx]; 1271 qmem_free(pf->dev, sq->sqe); 1272 qmem_free(pf->dev, sq->tso_hdrs); 1273 kfree(sq->sg); 1274 kfree(sq->sqb_ptrs); 1275 } 1276 } 1277 1278 static int otx2_init_hw_resources(struct otx2_nic *pf) 1279 { 1280 struct mbox *mbox = &pf->mbox; 1281 struct otx2_hw *hw = &pf->hw; 1282 struct msg_req *req; 1283 int err = 0, lvl; 1284 1285 /* Set required NPA LF's pool counts 1286 * Auras and Pools are used in a 1:1 mapping, 1287 * so, aura count = pool count. 1288 */ 1289 hw->rqpool_cnt = hw->rx_queues; 1290 hw->sqpool_cnt = hw->tx_queues; 1291 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1292 1293 /* Get the size of receive buffers to allocate */ 1294 pf->rbsize = RCV_FRAG_LEN(OTX2_HW_TIMESTAMP_LEN + pf->netdev->mtu + 1295 OTX2_ETH_HLEN); 1296 1297 mutex_lock(&mbox->lock); 1298 /* NPA init */ 1299 err = otx2_config_npa(pf); 1300 if (err) 1301 goto exit; 1302 1303 /* NIX init */ 1304 err = otx2_config_nix(pf); 1305 if (err) 1306 goto err_free_npa_lf; 1307 1308 /* Enable backpressure */ 1309 otx2_nix_config_bp(pf, true); 1310 1311 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1312 err = otx2_rq_aura_pool_init(pf); 1313 if (err) { 1314 mutex_unlock(&mbox->lock); 1315 goto err_free_nix_lf; 1316 } 1317 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1318 err = otx2_sq_aura_pool_init(pf); 1319 if (err) { 1320 mutex_unlock(&mbox->lock); 1321 goto err_free_rq_ptrs; 1322 } 1323 1324 err = otx2_txsch_alloc(pf); 1325 if (err) { 1326 mutex_unlock(&mbox->lock); 1327 goto err_free_sq_ptrs; 1328 } 1329 1330 err = otx2_config_nix_queues(pf); 1331 if (err) { 1332 mutex_unlock(&mbox->lock); 1333 goto err_free_txsch; 1334 } 1335 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1336 err = otx2_txschq_config(pf, lvl); 1337 if (err) { 1338 mutex_unlock(&mbox->lock); 1339 goto err_free_nix_queues; 1340 } 1341 } 1342 mutex_unlock(&mbox->lock); 1343 return err; 1344 1345 err_free_nix_queues: 1346 otx2_free_sq_res(pf); 1347 otx2_free_cq_res(pf); 1348 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1349 err_free_txsch: 1350 if (otx2_txschq_stop(pf)) 1351 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1352 err_free_sq_ptrs: 1353 otx2_sq_free_sqbs(pf); 1354 err_free_rq_ptrs: 1355 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1356 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1357 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1358 otx2_aura_pool_free(pf); 1359 err_free_nix_lf: 1360 mutex_lock(&mbox->lock); 1361 req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1362 if (req) { 1363 if (otx2_sync_mbox_msg(mbox)) 1364 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1365 } 1366 err_free_npa_lf: 1367 /* Reset NPA LF */ 1368 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1369 if (req) { 1370 if (otx2_sync_mbox_msg(mbox)) 1371 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1372 } 1373 exit: 1374 mutex_unlock(&mbox->lock); 1375 return err; 1376 } 1377 1378 static void otx2_free_hw_resources(struct otx2_nic *pf) 1379 { 1380 struct otx2_qset *qset = &pf->qset; 1381 struct mbox *mbox = &pf->mbox; 1382 struct otx2_cq_queue *cq; 1383 struct msg_req *req; 1384 int qidx, err; 1385 1386 /* Ensure all SQE are processed */ 1387 otx2_sqb_flush(pf); 1388 1389 /* Stop transmission */ 1390 err = otx2_txschq_stop(pf); 1391 if (err) 1392 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1393 1394 mutex_lock(&mbox->lock); 1395 /* Disable backpressure */ 1396 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1397 otx2_nix_config_bp(pf, false); 1398 mutex_unlock(&mbox->lock); 1399 1400 /* Disable RQs */ 1401 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1402 1403 /*Dequeue all CQEs */ 1404 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1405 cq = &qset->cq[qidx]; 1406 if (cq->cq_type == CQ_RX) 1407 otx2_cleanup_rx_cqes(pf, cq); 1408 else 1409 otx2_cleanup_tx_cqes(pf, cq); 1410 } 1411 1412 otx2_free_sq_res(pf); 1413 1414 /* Free RQ buffer pointers*/ 1415 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1416 1417 otx2_free_cq_res(pf); 1418 1419 mutex_lock(&mbox->lock); 1420 /* Reset NIX LF */ 1421 req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1422 if (req) { 1423 if (otx2_sync_mbox_msg(mbox)) 1424 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1425 } 1426 mutex_unlock(&mbox->lock); 1427 1428 /* Disable NPA Pool and Aura hw context */ 1429 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1430 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1431 otx2_aura_pool_free(pf); 1432 1433 mutex_lock(&mbox->lock); 1434 /* Reset NPA LF */ 1435 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1436 if (req) { 1437 if (otx2_sync_mbox_msg(mbox)) 1438 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1439 } 1440 mutex_unlock(&mbox->lock); 1441 } 1442 1443 int otx2_open(struct net_device *netdev) 1444 { 1445 struct otx2_nic *pf = netdev_priv(netdev); 1446 struct otx2_cq_poll *cq_poll = NULL; 1447 struct otx2_qset *qset = &pf->qset; 1448 int err = 0, qidx, vec; 1449 char *irq_name; 1450 1451 netif_carrier_off(netdev); 1452 1453 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues; 1454 /* RQ and SQs are mapped to different CQs, 1455 * so find out max CQ IRQs (i.e CINTs) needed. 1456 */ 1457 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1458 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1459 if (!qset->napi) 1460 return -ENOMEM; 1461 1462 /* CQ size of RQ */ 1463 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1464 /* CQ size of SQ */ 1465 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1466 1467 err = -ENOMEM; 1468 qset->cq = kcalloc(pf->qset.cq_cnt, 1469 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1470 if (!qset->cq) 1471 goto err_free_mem; 1472 1473 qset->sq = kcalloc(pf->hw.tx_queues, 1474 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1475 if (!qset->sq) 1476 goto err_free_mem; 1477 1478 qset->rq = kcalloc(pf->hw.rx_queues, 1479 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1480 if (!qset->rq) 1481 goto err_free_mem; 1482 1483 err = otx2_init_hw_resources(pf); 1484 if (err) 1485 goto err_free_mem; 1486 1487 /* Register NAPI handler */ 1488 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1489 cq_poll = &qset->napi[qidx]; 1490 cq_poll->cint_idx = qidx; 1491 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1492 * 'cq_ids[0]' points to RQ's CQ and 1493 * 'cq_ids[1]' points to SQ's CQ and 1494 */ 1495 cq_poll->cq_ids[CQ_RX] = 1496 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1497 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1498 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1499 cq_poll->dev = (void *)pf; 1500 netif_napi_add(netdev, &cq_poll->napi, 1501 otx2_napi_handler, NAPI_POLL_WEIGHT); 1502 napi_enable(&cq_poll->napi); 1503 } 1504 1505 /* Set maximum frame size allowed in HW */ 1506 err = otx2_hw_set_mtu(pf, netdev->mtu); 1507 if (err) 1508 goto err_disable_napi; 1509 1510 /* Setup segmentation algorithms, if failed, clear offload capability */ 1511 otx2_setup_segmentation(pf); 1512 1513 /* Initialize RSS */ 1514 err = otx2_rss_init(pf); 1515 if (err) 1516 goto err_disable_napi; 1517 1518 /* Register Queue IRQ handlers */ 1519 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1520 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1521 1522 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1523 1524 err = request_irq(pci_irq_vector(pf->pdev, vec), 1525 otx2_q_intr_handler, 0, irq_name, pf); 1526 if (err) { 1527 dev_err(pf->dev, 1528 "RVUPF%d: IRQ registration failed for QERR\n", 1529 rvu_get_pf(pf->pcifunc)); 1530 goto err_disable_napi; 1531 } 1532 1533 /* Enable QINT IRQ */ 1534 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1535 1536 /* Register CQ IRQ handlers */ 1537 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1538 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1539 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1540 1541 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1542 qidx); 1543 1544 err = request_irq(pci_irq_vector(pf->pdev, vec), 1545 otx2_cq_intr_handler, 0, irq_name, 1546 &qset->napi[qidx]); 1547 if (err) { 1548 dev_err(pf->dev, 1549 "RVUPF%d: IRQ registration failed for CQ%d\n", 1550 rvu_get_pf(pf->pcifunc), qidx); 1551 goto err_free_cints; 1552 } 1553 vec++; 1554 1555 otx2_config_irq_coalescing(pf, qidx); 1556 1557 /* Enable CQ IRQ */ 1558 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1559 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1560 } 1561 1562 otx2_set_cints_affinity(pf); 1563 1564 /* When reinitializing enable time stamping if it is enabled before */ 1565 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1566 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1567 otx2_config_hw_tx_tstamp(pf, true); 1568 } 1569 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1570 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1571 otx2_config_hw_rx_tstamp(pf, true); 1572 } 1573 1574 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1575 /* 'intf_down' may be checked on any cpu */ 1576 smp_wmb(); 1577 1578 /* we have already received link status notification */ 1579 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1580 otx2_handle_link_event(pf); 1581 1582 /* Restore pause frame settings */ 1583 otx2_config_pause_frm(pf); 1584 1585 err = otx2_rxtx_enable(pf, true); 1586 if (err) 1587 goto err_free_cints; 1588 1589 return 0; 1590 1591 err_free_cints: 1592 otx2_free_cints(pf, qidx); 1593 vec = pci_irq_vector(pf->pdev, 1594 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1595 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1596 synchronize_irq(vec); 1597 free_irq(vec, pf); 1598 err_disable_napi: 1599 otx2_disable_napi(pf); 1600 otx2_free_hw_resources(pf); 1601 err_free_mem: 1602 kfree(qset->sq); 1603 kfree(qset->cq); 1604 kfree(qset->rq); 1605 kfree(qset->napi); 1606 return err; 1607 } 1608 EXPORT_SYMBOL(otx2_open); 1609 1610 int otx2_stop(struct net_device *netdev) 1611 { 1612 struct otx2_nic *pf = netdev_priv(netdev); 1613 struct otx2_cq_poll *cq_poll = NULL; 1614 struct otx2_qset *qset = &pf->qset; 1615 int qidx, vec, wrk; 1616 1617 netif_carrier_off(netdev); 1618 netif_tx_stop_all_queues(netdev); 1619 1620 pf->flags |= OTX2_FLAG_INTF_DOWN; 1621 /* 'intf_down' may be checked on any cpu */ 1622 smp_wmb(); 1623 1624 /* First stop packet Rx/Tx */ 1625 otx2_rxtx_enable(pf, false); 1626 1627 /* Cleanup Queue IRQ */ 1628 vec = pci_irq_vector(pf->pdev, 1629 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1630 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1631 synchronize_irq(vec); 1632 free_irq(vec, pf); 1633 1634 /* Cleanup CQ NAPI and IRQ */ 1635 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1636 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1637 /* Disable interrupt */ 1638 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1639 1640 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1641 1642 cq_poll = &qset->napi[qidx]; 1643 napi_synchronize(&cq_poll->napi); 1644 vec++; 1645 } 1646 1647 netif_tx_disable(netdev); 1648 1649 otx2_free_hw_resources(pf); 1650 otx2_free_cints(pf, pf->hw.cint_cnt); 1651 otx2_disable_napi(pf); 1652 1653 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1654 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1655 1656 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1657 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1658 devm_kfree(pf->dev, pf->refill_wrk); 1659 1660 kfree(qset->sq); 1661 kfree(qset->cq); 1662 kfree(qset->rq); 1663 kfree(qset->napi); 1664 /* Do not clear RQ/SQ ringsize settings */ 1665 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1666 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1667 return 0; 1668 } 1669 EXPORT_SYMBOL(otx2_stop); 1670 1671 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1672 { 1673 struct otx2_nic *pf = netdev_priv(netdev); 1674 int qidx = skb_get_queue_mapping(skb); 1675 struct otx2_snd_queue *sq; 1676 struct netdev_queue *txq; 1677 1678 /* Check for minimum and maximum packet length */ 1679 if (skb->len <= ETH_HLEN || 1680 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1681 dev_kfree_skb(skb); 1682 return NETDEV_TX_OK; 1683 } 1684 1685 sq = &pf->qset.sq[qidx]; 1686 txq = netdev_get_tx_queue(netdev, qidx); 1687 1688 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1689 netif_tx_stop_queue(txq); 1690 1691 /* Check again, incase SQBs got freed up */ 1692 smp_mb(); 1693 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1694 > sq->sqe_thresh) 1695 netif_tx_wake_queue(txq); 1696 1697 return NETDEV_TX_BUSY; 1698 } 1699 1700 return NETDEV_TX_OK; 1701 } 1702 1703 static void otx2_set_rx_mode(struct net_device *netdev) 1704 { 1705 struct otx2_nic *pf = netdev_priv(netdev); 1706 1707 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1708 } 1709 1710 static void otx2_do_set_rx_mode(struct work_struct *work) 1711 { 1712 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1713 struct net_device *netdev = pf->netdev; 1714 struct nix_rx_mode *req; 1715 1716 if (!(netdev->flags & IFF_UP)) 1717 return; 1718 1719 mutex_lock(&pf->mbox.lock); 1720 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1721 if (!req) { 1722 mutex_unlock(&pf->mbox.lock); 1723 return; 1724 } 1725 1726 req->mode = NIX_RX_MODE_UCAST; 1727 1728 /* We don't support MAC address filtering yet */ 1729 if (netdev->flags & IFF_PROMISC) 1730 req->mode |= NIX_RX_MODE_PROMISC; 1731 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1732 req->mode |= NIX_RX_MODE_ALLMULTI; 1733 1734 otx2_sync_mbox_msg(&pf->mbox); 1735 mutex_unlock(&pf->mbox.lock); 1736 } 1737 1738 static int otx2_set_features(struct net_device *netdev, 1739 netdev_features_t features) 1740 { 1741 netdev_features_t changed = features ^ netdev->features; 1742 struct otx2_nic *pf = netdev_priv(netdev); 1743 1744 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1745 return otx2_cgx_config_loopback(pf, 1746 features & NETIF_F_LOOPBACK); 1747 return 0; 1748 } 1749 1750 static void otx2_reset_task(struct work_struct *work) 1751 { 1752 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1753 1754 if (!netif_running(pf->netdev)) 1755 return; 1756 1757 rtnl_lock(); 1758 otx2_stop(pf->netdev); 1759 pf->reset_count++; 1760 otx2_open(pf->netdev); 1761 netif_trans_update(pf->netdev); 1762 rtnl_unlock(); 1763 } 1764 1765 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1766 { 1767 struct msg_req *req; 1768 int err; 1769 1770 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1771 return 0; 1772 1773 mutex_lock(&pfvf->mbox.lock); 1774 if (enable) 1775 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1776 else 1777 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1778 if (!req) { 1779 mutex_unlock(&pfvf->mbox.lock); 1780 return -ENOMEM; 1781 } 1782 1783 err = otx2_sync_mbox_msg(&pfvf->mbox); 1784 if (err) { 1785 mutex_unlock(&pfvf->mbox.lock); 1786 return err; 1787 } 1788 1789 mutex_unlock(&pfvf->mbox.lock); 1790 if (enable) 1791 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1792 else 1793 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1794 return 0; 1795 } 1796 1797 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1798 { 1799 struct msg_req *req; 1800 int err; 1801 1802 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1803 return 0; 1804 1805 mutex_lock(&pfvf->mbox.lock); 1806 if (enable) 1807 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1808 else 1809 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1810 if (!req) { 1811 mutex_unlock(&pfvf->mbox.lock); 1812 return -ENOMEM; 1813 } 1814 1815 err = otx2_sync_mbox_msg(&pfvf->mbox); 1816 if (err) { 1817 mutex_unlock(&pfvf->mbox.lock); 1818 return err; 1819 } 1820 1821 mutex_unlock(&pfvf->mbox.lock); 1822 if (enable) 1823 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1824 else 1825 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1826 return 0; 1827 } 1828 1829 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1830 { 1831 struct otx2_nic *pfvf = netdev_priv(netdev); 1832 struct hwtstamp_config config; 1833 1834 if (!pfvf->ptp) 1835 return -ENODEV; 1836 1837 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1838 return -EFAULT; 1839 1840 /* reserved for future extensions */ 1841 if (config.flags) 1842 return -EINVAL; 1843 1844 switch (config.tx_type) { 1845 case HWTSTAMP_TX_OFF: 1846 otx2_config_hw_tx_tstamp(pfvf, false); 1847 break; 1848 case HWTSTAMP_TX_ON: 1849 otx2_config_hw_tx_tstamp(pfvf, true); 1850 break; 1851 default: 1852 return -ERANGE; 1853 } 1854 1855 switch (config.rx_filter) { 1856 case HWTSTAMP_FILTER_NONE: 1857 otx2_config_hw_rx_tstamp(pfvf, false); 1858 break; 1859 case HWTSTAMP_FILTER_ALL: 1860 case HWTSTAMP_FILTER_SOME: 1861 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1862 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1863 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1864 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1865 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1866 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1867 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1868 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1869 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1870 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1871 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1872 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1873 otx2_config_hw_rx_tstamp(pfvf, true); 1874 config.rx_filter = HWTSTAMP_FILTER_ALL; 1875 break; 1876 default: 1877 return -ERANGE; 1878 } 1879 1880 memcpy(&pfvf->tstamp, &config, sizeof(config)); 1881 1882 return copy_to_user(ifr->ifr_data, &config, 1883 sizeof(config)) ? -EFAULT : 0; 1884 } 1885 1886 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 1887 { 1888 struct otx2_nic *pfvf = netdev_priv(netdev); 1889 struct hwtstamp_config *cfg = &pfvf->tstamp; 1890 1891 switch (cmd) { 1892 case SIOCSHWTSTAMP: 1893 return otx2_config_hwtstamp(netdev, req); 1894 case SIOCGHWTSTAMP: 1895 return copy_to_user(req->ifr_data, cfg, 1896 sizeof(*cfg)) ? -EFAULT : 0; 1897 default: 1898 return -EOPNOTSUPP; 1899 } 1900 } 1901 1902 static const struct net_device_ops otx2_netdev_ops = { 1903 .ndo_open = otx2_open, 1904 .ndo_stop = otx2_stop, 1905 .ndo_start_xmit = otx2_xmit, 1906 .ndo_set_mac_address = otx2_set_mac_address, 1907 .ndo_change_mtu = otx2_change_mtu, 1908 .ndo_set_rx_mode = otx2_set_rx_mode, 1909 .ndo_set_features = otx2_set_features, 1910 .ndo_tx_timeout = otx2_tx_timeout, 1911 .ndo_get_stats64 = otx2_get_stats64, 1912 .ndo_do_ioctl = otx2_ioctl, 1913 }; 1914 1915 static int otx2_wq_init(struct otx2_nic *pf) 1916 { 1917 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 1918 if (!pf->otx2_wq) 1919 return -ENOMEM; 1920 1921 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode); 1922 INIT_WORK(&pf->reset_task, otx2_reset_task); 1923 return 0; 1924 } 1925 1926 static int otx2_check_pf_usable(struct otx2_nic *nic) 1927 { 1928 u64 rev; 1929 1930 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 1931 rev = (rev >> 12) & 0xFF; 1932 /* Check if AF has setup revision for RVUM block, 1933 * otherwise this driver probe should be deferred 1934 * until AF driver comes up. 1935 */ 1936 if (!rev) { 1937 dev_warn(nic->dev, 1938 "AF is not initialized, deferring probe\n"); 1939 return -EPROBE_DEFER; 1940 } 1941 return 0; 1942 } 1943 1944 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 1945 { 1946 struct otx2_hw *hw = &pf->hw; 1947 int num_vec, err; 1948 1949 /* NPA interrupts are inot registered, so alloc only 1950 * upto NIX vector offset. 1951 */ 1952 num_vec = hw->nix_msixoff; 1953 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 1954 1955 otx2_disable_mbox_intr(pf); 1956 pci_free_irq_vectors(hw->pdev); 1957 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 1958 if (err < 0) { 1959 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 1960 __func__, num_vec); 1961 return err; 1962 } 1963 1964 return otx2_register_mbox_intr(pf, false); 1965 } 1966 1967 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1968 { 1969 struct device *dev = &pdev->dev; 1970 struct net_device *netdev; 1971 struct otx2_nic *pf; 1972 struct otx2_hw *hw; 1973 int err, qcount; 1974 int num_vec; 1975 1976 err = pcim_enable_device(pdev); 1977 if (err) { 1978 dev_err(dev, "Failed to enable PCI device\n"); 1979 return err; 1980 } 1981 1982 err = pci_request_regions(pdev, DRV_NAME); 1983 if (err) { 1984 dev_err(dev, "PCI request regions failed 0x%x\n", err); 1985 return err; 1986 } 1987 1988 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 1989 if (err) { 1990 dev_err(dev, "DMA mask config failed, abort\n"); 1991 goto err_release_regions; 1992 } 1993 1994 pci_set_master(pdev); 1995 1996 /* Set number of queues */ 1997 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 1998 1999 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2000 if (!netdev) { 2001 err = -ENOMEM; 2002 goto err_release_regions; 2003 } 2004 2005 pci_set_drvdata(pdev, netdev); 2006 SET_NETDEV_DEV(netdev, &pdev->dev); 2007 pf = netdev_priv(netdev); 2008 pf->netdev = netdev; 2009 pf->pdev = pdev; 2010 pf->dev = dev; 2011 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2012 pf->flags |= OTX2_FLAG_INTF_DOWN; 2013 2014 hw = &pf->hw; 2015 hw->pdev = pdev; 2016 hw->rx_queues = qcount; 2017 hw->tx_queues = qcount; 2018 hw->max_queues = qcount; 2019 2020 num_vec = pci_msix_vec_count(pdev); 2021 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2022 GFP_KERNEL); 2023 if (!hw->irq_name) { 2024 err = -ENOMEM; 2025 goto err_free_netdev; 2026 } 2027 2028 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2029 sizeof(cpumask_var_t), GFP_KERNEL); 2030 if (!hw->affinity_mask) { 2031 err = -ENOMEM; 2032 goto err_free_netdev; 2033 } 2034 2035 /* Map CSRs */ 2036 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2037 if (!pf->reg_base) { 2038 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2039 err = -ENOMEM; 2040 goto err_free_netdev; 2041 } 2042 2043 err = otx2_check_pf_usable(pf); 2044 if (err) 2045 goto err_free_netdev; 2046 2047 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2048 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2049 if (err < 0) { 2050 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2051 __func__, num_vec); 2052 goto err_free_netdev; 2053 } 2054 2055 /* Init PF <=> AF mailbox stuff */ 2056 err = otx2_pfaf_mbox_init(pf); 2057 if (err) 2058 goto err_free_irq_vectors; 2059 2060 /* Register mailbox interrupt */ 2061 err = otx2_register_mbox_intr(pf, true); 2062 if (err) 2063 goto err_mbox_destroy; 2064 2065 /* Request AF to attach NPA and NIX LFs to this PF. 2066 * NIX and NPA LFs are needed for this PF to function as a NIC. 2067 */ 2068 err = otx2_attach_npa_nix(pf); 2069 if (err) 2070 goto err_disable_mbox_intr; 2071 2072 err = otx2_realloc_msix_vectors(pf); 2073 if (err) 2074 goto err_detach_rsrc; 2075 2076 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2077 if (err) 2078 goto err_detach_rsrc; 2079 2080 otx2_setup_dev_hw_settings(pf); 2081 2082 /* Assign default mac address */ 2083 otx2_get_mac_from_af(netdev); 2084 2085 /* Don't check for error. Proceed without ptp */ 2086 otx2_ptp_init(pf); 2087 2088 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2089 * HW allocates buffer pointer from stack and uses it for DMA'ing 2090 * ingress packet. In some scenarios HW can free back allocated buffer 2091 * pointers to pool. This makes it impossible for SW to maintain a 2092 * parallel list where physical addresses of buffer pointers (IOVAs) 2093 * given to HW can be saved for later reference. 2094 * 2095 * So the only way to convert Rx packet's buffer address is to use 2096 * IOMMU's iova_to_phys() handler which translates the address by 2097 * walking through the translation tables. 2098 */ 2099 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2100 2101 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2102 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2103 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2104 NETIF_F_GSO_UDP_L4); 2105 netdev->features |= netdev->hw_features; 2106 2107 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2108 2109 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2110 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2111 2112 netdev->netdev_ops = &otx2_netdev_ops; 2113 2114 /* MTU range: 64 - 9190 */ 2115 netdev->min_mtu = OTX2_MIN_MTU; 2116 netdev->max_mtu = OTX2_MAX_MTU; 2117 2118 err = register_netdev(netdev); 2119 if (err) { 2120 dev_err(dev, "Failed to register netdevice\n"); 2121 goto err_ptp_destroy; 2122 } 2123 2124 err = otx2_wq_init(pf); 2125 if (err) 2126 goto err_unreg_netdev; 2127 2128 otx2_set_ethtool_ops(netdev); 2129 2130 /* Enable link notifications */ 2131 otx2_cgx_config_linkevents(pf, true); 2132 2133 /* Enable pause frames by default */ 2134 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2135 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2136 2137 return 0; 2138 2139 err_unreg_netdev: 2140 unregister_netdev(netdev); 2141 err_ptp_destroy: 2142 otx2_ptp_destroy(pf); 2143 err_detach_rsrc: 2144 otx2_detach_resources(&pf->mbox); 2145 err_disable_mbox_intr: 2146 otx2_disable_mbox_intr(pf); 2147 err_mbox_destroy: 2148 otx2_pfaf_mbox_destroy(pf); 2149 err_free_irq_vectors: 2150 pci_free_irq_vectors(hw->pdev); 2151 err_free_netdev: 2152 pci_set_drvdata(pdev, NULL); 2153 free_netdev(netdev); 2154 err_release_regions: 2155 pci_release_regions(pdev); 2156 return err; 2157 } 2158 2159 static void otx2_vf_link_event_task(struct work_struct *work) 2160 { 2161 struct otx2_vf_config *config; 2162 struct cgx_link_info_msg *req; 2163 struct mbox_msghdr *msghdr; 2164 struct otx2_nic *pf; 2165 int vf_idx; 2166 2167 config = container_of(work, struct otx2_vf_config, 2168 link_event_work.work); 2169 vf_idx = config - config->pf->vf_configs; 2170 pf = config->pf; 2171 2172 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2173 sizeof(*req), sizeof(struct msg_rsp)); 2174 if (!msghdr) { 2175 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2176 return; 2177 } 2178 2179 req = (struct cgx_link_info_msg *)msghdr; 2180 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2181 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2182 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2183 2184 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2185 } 2186 2187 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2188 { 2189 struct net_device *netdev = pci_get_drvdata(pdev); 2190 struct otx2_nic *pf = netdev_priv(netdev); 2191 int ret, i; 2192 2193 /* Init PF <=> VF mailbox stuff */ 2194 ret = otx2_pfvf_mbox_init(pf, numvfs); 2195 if (ret) 2196 return ret; 2197 2198 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2199 if (ret) 2200 goto free_mbox; 2201 2202 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config), 2203 GFP_KERNEL); 2204 if (!pf->vf_configs) { 2205 ret = -ENOMEM; 2206 goto free_intr; 2207 } 2208 2209 for (i = 0; i < numvfs; i++) { 2210 pf->vf_configs[i].pf = pf; 2211 pf->vf_configs[i].intf_down = true; 2212 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2213 otx2_vf_link_event_task); 2214 } 2215 2216 ret = otx2_pf_flr_init(pf, numvfs); 2217 if (ret) 2218 goto free_configs; 2219 2220 ret = otx2_register_flr_me_intr(pf, numvfs); 2221 if (ret) 2222 goto free_flr; 2223 2224 ret = pci_enable_sriov(pdev, numvfs); 2225 if (ret) 2226 goto free_flr_intr; 2227 2228 return numvfs; 2229 free_flr_intr: 2230 otx2_disable_flr_me_intr(pf); 2231 free_flr: 2232 otx2_flr_wq_destroy(pf); 2233 free_configs: 2234 kfree(pf->vf_configs); 2235 free_intr: 2236 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2237 free_mbox: 2238 otx2_pfvf_mbox_destroy(pf); 2239 return ret; 2240 } 2241 2242 static int otx2_sriov_disable(struct pci_dev *pdev) 2243 { 2244 struct net_device *netdev = pci_get_drvdata(pdev); 2245 struct otx2_nic *pf = netdev_priv(netdev); 2246 int numvfs = pci_num_vf(pdev); 2247 int i; 2248 2249 if (!numvfs) 2250 return 0; 2251 2252 pci_disable_sriov(pdev); 2253 2254 for (i = 0; i < pci_num_vf(pdev); i++) 2255 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2256 kfree(pf->vf_configs); 2257 2258 otx2_disable_flr_me_intr(pf); 2259 otx2_flr_wq_destroy(pf); 2260 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2261 otx2_pfvf_mbox_destroy(pf); 2262 2263 return 0; 2264 } 2265 2266 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2267 { 2268 if (numvfs == 0) 2269 return otx2_sriov_disable(pdev); 2270 else 2271 return otx2_sriov_enable(pdev, numvfs); 2272 } 2273 2274 static void otx2_remove(struct pci_dev *pdev) 2275 { 2276 struct net_device *netdev = pci_get_drvdata(pdev); 2277 struct otx2_nic *pf; 2278 2279 if (!netdev) 2280 return; 2281 2282 pf = netdev_priv(netdev); 2283 2284 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2285 otx2_config_hw_tx_tstamp(pf, false); 2286 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2287 otx2_config_hw_rx_tstamp(pf, false); 2288 2289 cancel_work_sync(&pf->reset_task); 2290 /* Disable link notifications */ 2291 otx2_cgx_config_linkevents(pf, false); 2292 2293 unregister_netdev(netdev); 2294 otx2_sriov_disable(pf->pdev); 2295 if (pf->otx2_wq) 2296 destroy_workqueue(pf->otx2_wq); 2297 2298 otx2_ptp_destroy(pf); 2299 otx2_detach_resources(&pf->mbox); 2300 otx2_disable_mbox_intr(pf); 2301 otx2_pfaf_mbox_destroy(pf); 2302 pci_free_irq_vectors(pf->pdev); 2303 pci_set_drvdata(pdev, NULL); 2304 free_netdev(netdev); 2305 2306 pci_release_regions(pdev); 2307 } 2308 2309 static struct pci_driver otx2_pf_driver = { 2310 .name = DRV_NAME, 2311 .id_table = otx2_pf_id_table, 2312 .probe = otx2_probe, 2313 .shutdown = otx2_remove, 2314 .remove = otx2_remove, 2315 .sriov_configure = otx2_sriov_configure 2316 }; 2317 2318 static int __init otx2_rvupf_init_module(void) 2319 { 2320 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2321 2322 return pci_register_driver(&otx2_pf_driver); 2323 } 2324 2325 static void __exit otx2_rvupf_cleanup_module(void) 2326 { 2327 pci_unregister_driver(&otx2_pf_driver); 2328 } 2329 2330 module_init(otx2_rvupf_init_module); 2331 module_exit(otx2_rvupf_cleanup_module); 2332