1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 30 #define DRV_NAME "rvu_nicpf" 31 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 32 33 /* Supported devices */ 34 static const struct pci_device_id otx2_pf_id_table[] = { 35 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 36 { 0, } /* end of table */ 37 }; 38 39 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 40 MODULE_DESCRIPTION(DRV_STRING); 41 MODULE_LICENSE("GPL v2"); 42 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 43 44 static void otx2_vf_link_event_task(struct work_struct *work); 45 46 enum { 47 TYPE_PFAF, 48 TYPE_PFVF, 49 }; 50 51 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 52 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 53 54 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 55 { 56 struct otx2_nic *pf = netdev_priv(netdev); 57 bool if_up = netif_running(netdev); 58 int err = 0; 59 60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 61 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 62 netdev->mtu); 63 return -EINVAL; 64 } 65 if (if_up) 66 otx2_stop(netdev); 67 68 netdev_info(netdev, "Changing MTU from %d to %d\n", 69 netdev->mtu, new_mtu); 70 netdev->mtu = new_mtu; 71 72 if (if_up) 73 err = otx2_open(netdev); 74 75 return err; 76 } 77 78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 79 { 80 int irq, vfs = pf->total_vfs; 81 82 /* Disable VFs ME interrupts */ 83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 85 free_irq(irq, pf); 86 87 /* Disable VFs FLR interrupts */ 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 90 free_irq(irq, pf); 91 92 if (vfs <= 64) 93 return; 94 95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 97 free_irq(irq, pf); 98 99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 101 free_irq(irq, pf); 102 } 103 104 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 105 { 106 if (!pf->flr_wq) 107 return; 108 destroy_workqueue(pf->flr_wq); 109 pf->flr_wq = NULL; 110 devm_kfree(pf->dev, pf->flr_wrk); 111 } 112 113 static void otx2_flr_handler(struct work_struct *work) 114 { 115 struct flr_work *flrwork = container_of(work, struct flr_work, work); 116 struct otx2_nic *pf = flrwork->pf; 117 struct mbox *mbox = &pf->mbox; 118 struct msg_req *req; 119 int vf, reg = 0; 120 121 vf = flrwork - pf->flr_wrk; 122 123 mutex_lock(&mbox->lock); 124 req = otx2_mbox_alloc_msg_vf_flr(mbox); 125 if (!req) { 126 mutex_unlock(&mbox->lock); 127 return; 128 } 129 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 130 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 131 132 if (!otx2_sync_mbox_msg(&pf->mbox)) { 133 if (vf >= 64) { 134 reg = 1; 135 vf = vf - 64; 136 } 137 /* clear transcation pending bit */ 138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 140 } 141 142 mutex_unlock(&mbox->lock); 143 } 144 145 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 146 { 147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 148 int reg, dev, vf, start_vf, num_reg = 1; 149 u64 intr; 150 151 if (pf->total_vfs > 64) 152 num_reg = 2; 153 154 for (reg = 0; reg < num_reg; reg++) { 155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 156 if (!intr) 157 continue; 158 start_vf = 64 * reg; 159 for (vf = 0; vf < 64; vf++) { 160 if (!(intr & BIT_ULL(vf))) 161 continue; 162 dev = vf + start_vf; 163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 164 /* Clear interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 166 /* Disable the interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 168 BIT_ULL(vf)); 169 } 170 } 171 return IRQ_HANDLED; 172 } 173 174 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 175 { 176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 177 int vf, reg, num_reg = 1; 178 u64 intr; 179 180 if (pf->total_vfs > 64) 181 num_reg = 2; 182 183 for (reg = 0; reg < num_reg; reg++) { 184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 185 if (!intr) 186 continue; 187 for (vf = 0; vf < 64; vf++) { 188 if (!(intr & BIT_ULL(vf))) 189 continue; 190 /* clear trpend bit */ 191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 192 /* clear interrupt */ 193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 194 } 195 } 196 return IRQ_HANDLED; 197 } 198 199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 200 { 201 struct otx2_hw *hw = &pf->hw; 202 char *irq_name; 203 int ret; 204 205 /* Register ME interrupt handler*/ 206 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 209 otx2_pf_me_intr_handler, 0, irq_name, pf); 210 if (ret) { 211 dev_err(pf->dev, 212 "RVUPF: IRQ registration failed for ME0\n"); 213 } 214 215 /* Register FLR interrupt handler */ 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 219 otx2_pf_flr_intr_handler, 0, irq_name, pf); 220 if (ret) { 221 dev_err(pf->dev, 222 "RVUPF: IRQ registration failed for FLR0\n"); 223 return ret; 224 } 225 226 if (numvfs > 64) { 227 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 228 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 229 rvu_get_pf(pf->pcifunc)); 230 ret = request_irq(pci_irq_vector 231 (pf->pdev, RVU_PF_INT_VEC_VFME1), 232 otx2_pf_me_intr_handler, 0, irq_name, pf); 233 if (ret) { 234 dev_err(pf->dev, 235 "RVUPF: IRQ registration failed for ME1\n"); 236 } 237 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 238 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 239 rvu_get_pf(pf->pcifunc)); 240 ret = request_irq(pci_irq_vector 241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 242 otx2_pf_flr_intr_handler, 0, irq_name, pf); 243 if (ret) { 244 dev_err(pf->dev, 245 "RVUPF: IRQ registration failed for FLR1\n"); 246 return ret; 247 } 248 } 249 250 /* Enable ME interrupt for all VFs*/ 251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 253 254 /* Enable FLR interrupt for all VFs*/ 255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 257 258 if (numvfs > 64) { 259 numvfs -= 64; 260 261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 263 INTR_MASK(numvfs)); 264 265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 267 INTR_MASK(numvfs)); 268 } 269 return 0; 270 } 271 272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 273 { 274 int vf; 275 276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 277 if (!pf->flr_wq) 278 return -ENOMEM; 279 280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 281 sizeof(struct flr_work), GFP_KERNEL); 282 if (!pf->flr_wrk) { 283 destroy_workqueue(pf->flr_wq); 284 return -ENOMEM; 285 } 286 287 for (vf = 0; vf < num_vfs; vf++) { 288 pf->flr_wrk[vf].pf = pf; 289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 290 } 291 292 return 0; 293 } 294 295 static void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 296 int first, int mdevs, u64 intr) 297 { 298 struct otx2_mbox_dev *mdev; 299 struct otx2_mbox *mbox; 300 struct mbox_hdr *hdr; 301 int i; 302 303 for (i = first; i < mdevs; i++) { 304 /* start from 0 */ 305 if (!(intr & BIT_ULL(i - first))) 306 continue; 307 308 mbox = &mw->mbox; 309 mdev = &mbox->dev[i]; 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. pf->mw[i].num_msgs 314 * holds the data for use in otx2_pfvf_mbox_handler and 315 * pf->mw[i].up_num_msgs holds the data for use in 316 * otx2_pfvf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 queue_work(mbox_wq, &mw[i].mbox_wrk); 322 } 323 324 mbox = &mw->mbox_up; 325 mdev = &mbox->dev[i]; 326 hdr = mdev->mbase + mbox->rx_start; 327 if (hdr->num_msgs) { 328 mw[i].up_num_msgs = hdr->num_msgs; 329 hdr->num_msgs = 0; 330 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 331 } 332 } 333 } 334 335 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 336 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 337 int devid) 338 { 339 struct otx2_mbox_dev *src_mdev = mdev; 340 int offset; 341 342 /* Msgs are already copied, trigger VF's mbox irq */ 343 smp_wmb(); 344 345 otx2_mbox_wait_for_zero(pfvf_mbox, devid); 346 347 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 348 writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset); 349 350 /* Restore VF's mbox bounce buffer region address */ 351 src_mdev->mbase = bbuf_base; 352 } 353 354 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 355 struct otx2_mbox *src_mbox, 356 int dir, int vf, int num_msgs) 357 { 358 struct otx2_mbox_dev *src_mdev, *dst_mdev; 359 struct mbox_hdr *mbox_hdr; 360 struct mbox_hdr *req_hdr; 361 struct mbox *dst_mbox; 362 int dst_size, err; 363 364 if (dir == MBOX_DIR_PFAF) { 365 /* Set VF's mailbox memory as PF's bounce buffer memory, so 366 * that explicit copying of VF's msgs to PF=>AF mbox region 367 * and AF=>PF responses to VF's mbox region can be avoided. 368 */ 369 src_mdev = &src_mbox->dev[vf]; 370 mbox_hdr = src_mbox->hwbase + 371 src_mbox->rx_start + (vf * MBOX_SIZE); 372 373 dst_mbox = &pf->mbox; 374 dst_size = dst_mbox->mbox.tx_size - 375 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 376 /* Check if msgs fit into destination area and has valid size */ 377 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 378 return -EINVAL; 379 380 dst_mdev = &dst_mbox->mbox.dev[0]; 381 382 mutex_lock(&pf->mbox.lock); 383 dst_mdev->mbase = src_mdev->mbase; 384 dst_mdev->msg_size = mbox_hdr->msg_size; 385 dst_mdev->num_msgs = num_msgs; 386 err = otx2_sync_mbox_msg(dst_mbox); 387 /* Error code -EIO indicate there is a communication failure 388 * to the AF. Rest of the error codes indicate that AF processed 389 * VF messages and set the error codes in response messages 390 * (if any) so simply forward responses to VF. 391 */ 392 if (err == -EIO) { 393 dev_warn(pf->dev, 394 "AF not responding to VF%d messages\n", vf); 395 /* restore PF mbase and exit */ 396 dst_mdev->mbase = pf->mbox.bbuf_base; 397 mutex_unlock(&pf->mbox.lock); 398 return err; 399 } 400 /* At this point, all the VF messages sent to AF are acked 401 * with proper responses and responses are copied to VF 402 * mailbox hence raise interrupt to VF. 403 */ 404 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 405 dst_mbox->mbox.rx_start); 406 req_hdr->num_msgs = num_msgs; 407 408 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 409 pf->mbox.bbuf_base, vf); 410 mutex_unlock(&pf->mbox.lock); 411 } else if (dir == MBOX_DIR_PFVF_UP) { 412 src_mdev = &src_mbox->dev[0]; 413 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 414 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 415 src_mbox->rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 dst_mbox = &pf->mbox_pfvf[0]; 419 dst_size = dst_mbox->mbox_up.tx_size - 420 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 421 /* Check if msgs fit into destination area */ 422 if (mbox_hdr->msg_size > dst_size) 423 return -EINVAL; 424 425 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 426 dst_mdev->mbase = src_mdev->mbase; 427 dst_mdev->msg_size = mbox_hdr->msg_size; 428 dst_mdev->num_msgs = mbox_hdr->num_msgs; 429 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 430 if (err) { 431 dev_warn(pf->dev, 432 "VF%d is not responding to mailbox\n", vf); 433 return err; 434 } 435 } else if (dir == MBOX_DIR_VFPF_UP) { 436 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 437 src_mbox->rx_start); 438 req_hdr->num_msgs = num_msgs; 439 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 440 &pf->mbox.mbox_up, 441 pf->mbox_pfvf[vf].bbuf_base, 442 0); 443 } 444 445 return 0; 446 } 447 448 static void otx2_pfvf_mbox_handler(struct work_struct *work) 449 { 450 struct mbox_msghdr *msg = NULL; 451 int offset, vf_idx, id, err; 452 struct otx2_mbox_dev *mdev; 453 struct mbox_hdr *req_hdr; 454 struct otx2_mbox *mbox; 455 struct mbox *vf_mbox; 456 struct otx2_nic *pf; 457 458 vf_mbox = container_of(work, struct mbox, mbox_wrk); 459 pf = vf_mbox->pfvf; 460 vf_idx = vf_mbox - pf->mbox_pfvf; 461 462 mbox = &pf->mbox_pfvf[0].mbox; 463 mdev = &mbox->dev[vf_idx]; 464 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 465 466 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 467 468 for (id = 0; id < vf_mbox->num_msgs; id++) { 469 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 470 offset); 471 472 if (msg->sig != OTX2_MBOX_REQ_SIG) 473 goto inval_msg; 474 475 /* Set VF's number in each of the msg */ 476 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 477 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 478 offset = msg->next_msgoff; 479 } 480 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 481 vf_mbox->num_msgs); 482 if (err) 483 goto inval_msg; 484 return; 485 486 inval_msg: 487 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 488 otx2_mbox_msg_send(mbox, vf_idx); 489 } 490 491 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 492 { 493 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 494 struct otx2_nic *pf = vf_mbox->pfvf; 495 struct otx2_mbox_dev *mdev; 496 int offset, id, vf_idx = 0; 497 struct mbox_hdr *rsp_hdr; 498 struct mbox_msghdr *msg; 499 struct otx2_mbox *mbox; 500 501 vf_idx = vf_mbox - pf->mbox_pfvf; 502 mbox = &pf->mbox_pfvf[0].mbox_up; 503 mdev = &mbox->dev[vf_idx]; 504 505 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 506 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 507 508 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 509 msg = mdev->mbase + offset; 510 511 if (msg->id >= MBOX_MSG_MAX) { 512 dev_err(pf->dev, 513 "Mbox msg with unknown ID 0x%x\n", msg->id); 514 goto end; 515 } 516 517 if (msg->sig != OTX2_MBOX_RSP_SIG) { 518 dev_err(pf->dev, 519 "Mbox msg with wrong signature %x, ID 0x%x\n", 520 msg->sig, msg->id); 521 goto end; 522 } 523 524 switch (msg->id) { 525 case MBOX_MSG_CGX_LINK_EVENT: 526 break; 527 default: 528 if (msg->rc) 529 dev_err(pf->dev, 530 "Mbox msg response has err %d, ID 0x%x\n", 531 msg->rc, msg->id); 532 break; 533 } 534 535 end: 536 offset = mbox->rx_start + msg->next_msgoff; 537 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 538 __otx2_mbox_reset(mbox, vf_idx); 539 mdev->msgs_acked++; 540 } 541 } 542 543 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 544 { 545 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 546 int vfs = pf->total_vfs; 547 struct mbox *mbox; 548 u64 intr; 549 550 mbox = pf->mbox_pfvf; 551 /* Handle VF interrupts */ 552 if (vfs > 64) { 553 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 554 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 555 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr); 556 if (intr) 557 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 558 vfs = 64; 559 } 560 561 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 562 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 563 564 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr); 565 566 if (intr) 567 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 568 569 return IRQ_HANDLED; 570 } 571 572 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 573 { 574 void __iomem *hwbase; 575 struct mbox *mbox; 576 int err, vf; 577 u64 base; 578 579 if (!numvfs) 580 return -EINVAL; 581 582 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 583 sizeof(struct mbox), GFP_KERNEL); 584 if (!pf->mbox_pfvf) 585 return -ENOMEM; 586 587 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 588 WQ_UNBOUND | WQ_HIGHPRI | 589 WQ_MEM_RECLAIM, 0); 590 if (!pf->mbox_pfvf_wq) 591 return -ENOMEM; 592 593 /* On CN10K platform, PF <-> VF mailbox region follows after 594 * PF <-> AF mailbox region. 595 */ 596 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 597 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 598 MBOX_SIZE; 599 else 600 base = readq((void __iomem *)((u64)pf->reg_base + 601 RVU_PF_VF_BAR4_ADDR)); 602 603 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 604 if (!hwbase) { 605 err = -ENOMEM; 606 goto free_wq; 607 } 608 609 mbox = &pf->mbox_pfvf[0]; 610 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 611 MBOX_DIR_PFVF, numvfs); 612 if (err) 613 goto free_iomem; 614 615 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 616 MBOX_DIR_PFVF_UP, numvfs); 617 if (err) 618 goto free_iomem; 619 620 for (vf = 0; vf < numvfs; vf++) { 621 mbox->pfvf = pf; 622 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 623 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 624 mbox++; 625 } 626 627 return 0; 628 629 free_iomem: 630 if (hwbase) 631 iounmap(hwbase); 632 free_wq: 633 destroy_workqueue(pf->mbox_pfvf_wq); 634 return err; 635 } 636 637 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 638 { 639 struct mbox *mbox = &pf->mbox_pfvf[0]; 640 641 if (!mbox) 642 return; 643 644 if (pf->mbox_pfvf_wq) { 645 destroy_workqueue(pf->mbox_pfvf_wq); 646 pf->mbox_pfvf_wq = NULL; 647 } 648 649 if (mbox->mbox.hwbase) 650 iounmap(mbox->mbox.hwbase); 651 652 otx2_mbox_destroy(&mbox->mbox); 653 } 654 655 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 656 { 657 /* Clear PF <=> VF mailbox IRQ */ 658 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 659 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 660 661 /* Enable PF <=> VF mailbox IRQ */ 662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 663 if (numvfs > 64) { 664 numvfs -= 64; 665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 666 INTR_MASK(numvfs)); 667 } 668 } 669 670 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 671 { 672 int vector; 673 674 /* Disable PF <=> VF mailbox IRQ */ 675 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 676 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 677 678 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 679 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 680 free_irq(vector, pf); 681 682 if (numvfs > 64) { 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 684 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 685 free_irq(vector, pf); 686 } 687 } 688 689 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 690 { 691 struct otx2_hw *hw = &pf->hw; 692 char *irq_name; 693 int err; 694 695 /* Register MBOX0 interrupt handler */ 696 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 697 if (pf->pcifunc) 698 snprintf(irq_name, NAME_SIZE, 699 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 700 else 701 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 702 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 703 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 704 if (err) { 705 dev_err(pf->dev, 706 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 707 return err; 708 } 709 710 if (numvfs > 64) { 711 /* Register MBOX1 interrupt handler */ 712 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 713 if (pf->pcifunc) 714 snprintf(irq_name, NAME_SIZE, 715 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 716 else 717 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 718 err = request_irq(pci_irq_vector(pf->pdev, 719 RVU_PF_INT_VEC_VFPF_MBOX1), 720 otx2_pfvf_mbox_intr_handler, 721 0, irq_name, pf); 722 if (err) { 723 dev_err(pf->dev, 724 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 725 return err; 726 } 727 } 728 729 otx2_enable_pfvf_mbox_intr(pf, numvfs); 730 731 return 0; 732 } 733 734 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 735 struct mbox_msghdr *msg) 736 { 737 int devid; 738 739 if (msg->id >= MBOX_MSG_MAX) { 740 dev_err(pf->dev, 741 "Mbox msg with unknown ID 0x%x\n", msg->id); 742 return; 743 } 744 745 if (msg->sig != OTX2_MBOX_RSP_SIG) { 746 dev_err(pf->dev, 747 "Mbox msg with wrong signature %x, ID 0x%x\n", 748 msg->sig, msg->id); 749 return; 750 } 751 752 /* message response heading VF */ 753 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 754 if (devid) { 755 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 756 struct delayed_work *dwork; 757 758 switch (msg->id) { 759 case MBOX_MSG_NIX_LF_START_RX: 760 config->intf_down = false; 761 dwork = &config->link_event_work; 762 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 763 break; 764 case MBOX_MSG_NIX_LF_STOP_RX: 765 config->intf_down = true; 766 break; 767 } 768 769 return; 770 } 771 772 switch (msg->id) { 773 case MBOX_MSG_READY: 774 pf->pcifunc = msg->pcifunc; 775 break; 776 case MBOX_MSG_MSIX_OFFSET: 777 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 778 break; 779 case MBOX_MSG_NPA_LF_ALLOC: 780 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 781 break; 782 case MBOX_MSG_NIX_LF_ALLOC: 783 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 784 break; 785 case MBOX_MSG_NIX_BP_ENABLE: 786 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 787 break; 788 case MBOX_MSG_CGX_STATS: 789 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 790 break; 791 case MBOX_MSG_CGX_FEC_STATS: 792 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 793 break; 794 default: 795 if (msg->rc) 796 dev_err(pf->dev, 797 "Mbox msg response has err %d, ID 0x%x\n", 798 msg->rc, msg->id); 799 break; 800 } 801 } 802 803 static void otx2_pfaf_mbox_handler(struct work_struct *work) 804 { 805 struct otx2_mbox_dev *mdev; 806 struct mbox_hdr *rsp_hdr; 807 struct mbox_msghdr *msg; 808 struct otx2_mbox *mbox; 809 struct mbox *af_mbox; 810 struct otx2_nic *pf; 811 int offset, id; 812 u16 num_msgs; 813 814 af_mbox = container_of(work, struct mbox, mbox_wrk); 815 mbox = &af_mbox->mbox; 816 mdev = &mbox->dev[0]; 817 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 818 num_msgs = rsp_hdr->num_msgs; 819 820 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 821 pf = af_mbox->pfvf; 822 823 for (id = 0; id < num_msgs; id++) { 824 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 825 otx2_process_pfaf_mbox_msg(pf, msg); 826 offset = mbox->rx_start + msg->next_msgoff; 827 if (mdev->msgs_acked == (num_msgs - 1)) 828 __otx2_mbox_reset(mbox, 0); 829 mdev->msgs_acked++; 830 } 831 832 } 833 834 static void otx2_handle_link_event(struct otx2_nic *pf) 835 { 836 struct cgx_link_user_info *linfo = &pf->linfo; 837 struct net_device *netdev = pf->netdev; 838 839 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 840 linfo->link_up ? "UP" : "DOWN", linfo->speed, 841 linfo->full_duplex ? "Full" : "Half"); 842 if (linfo->link_up) { 843 netif_carrier_on(netdev); 844 netif_tx_start_all_queues(netdev); 845 } else { 846 netif_tx_stop_all_queues(netdev); 847 netif_carrier_off(netdev); 848 } 849 } 850 851 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 852 struct mcs_intr_info *event, 853 struct msg_rsp *rsp) 854 { 855 cn10k_handle_mcs_event(pf, event); 856 857 return 0; 858 } 859 860 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 861 struct cgx_link_info_msg *msg, 862 struct msg_rsp *rsp) 863 { 864 int i; 865 866 /* Copy the link info sent by AF */ 867 pf->linfo = msg->link_info; 868 869 /* notify VFs about link event */ 870 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 871 struct otx2_vf_config *config = &pf->vf_configs[i]; 872 struct delayed_work *dwork = &config->link_event_work; 873 874 if (config->intf_down) 875 continue; 876 877 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 878 } 879 880 /* interface has not been fully configured yet */ 881 if (pf->flags & OTX2_FLAG_INTF_DOWN) 882 return 0; 883 884 otx2_handle_link_event(pf); 885 return 0; 886 } 887 888 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 889 struct mbox_msghdr *req) 890 { 891 /* Check if valid, if not reply with a invalid msg */ 892 if (req->sig != OTX2_MBOX_REQ_SIG) { 893 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 894 return -ENODEV; 895 } 896 897 switch (req->id) { 898 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 899 case _id: { \ 900 struct _rsp_type *rsp; \ 901 int err; \ 902 \ 903 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 904 &pf->mbox.mbox_up, 0, \ 905 sizeof(struct _rsp_type)); \ 906 if (!rsp) \ 907 return -ENOMEM; \ 908 \ 909 rsp->hdr.id = _id; \ 910 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 911 rsp->hdr.pcifunc = 0; \ 912 rsp->hdr.rc = 0; \ 913 \ 914 err = otx2_mbox_up_handler_ ## _fn_name( \ 915 pf, (struct _req_type *)req, rsp); \ 916 return err; \ 917 } 918 MBOX_UP_CGX_MESSAGES 919 MBOX_UP_MCS_MESSAGES 920 #undef M 921 break; 922 default: 923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 924 return -ENODEV; 925 } 926 return 0; 927 } 928 929 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 930 { 931 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 932 struct otx2_mbox *mbox = &af_mbox->mbox_up; 933 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 934 struct otx2_nic *pf = af_mbox->pfvf; 935 int offset, id, devid = 0; 936 struct mbox_hdr *rsp_hdr; 937 struct mbox_msghdr *msg; 938 u16 num_msgs; 939 940 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 941 num_msgs = rsp_hdr->num_msgs; 942 943 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 944 945 for (id = 0; id < num_msgs; id++) { 946 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 947 948 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 949 /* Skip processing VF's messages */ 950 if (!devid) 951 otx2_process_mbox_msg_up(pf, msg); 952 offset = mbox->rx_start + msg->next_msgoff; 953 } 954 /* Forward to VF iff VFs are really present */ 955 if (devid && pci_num_vf(pf->pdev)) { 956 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 957 MBOX_DIR_PFVF_UP, devid - 1, 958 num_msgs); 959 return; 960 } 961 962 otx2_mbox_msg_send(mbox, 0); 963 } 964 965 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 966 { 967 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 968 struct mbox *mw = &pf->mbox; 969 struct otx2_mbox_dev *mdev; 970 struct otx2_mbox *mbox; 971 struct mbox_hdr *hdr; 972 u64 mbox_data; 973 974 /* Clear the IRQ */ 975 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 976 977 978 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0); 979 980 if (mbox_data & MBOX_UP_MSG) { 981 mbox_data &= ~MBOX_UP_MSG; 982 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 983 984 mbox = &mw->mbox_up; 985 mdev = &mbox->dev[0]; 986 otx2_sync_mbox_bbuf(mbox, 0); 987 988 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 989 if (hdr->num_msgs) 990 queue_work(pf->mbox_wq, &mw->mbox_up_wrk); 991 992 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF", 993 BIT_ULL(0)); 994 } 995 996 if (mbox_data & MBOX_DOWN_MSG) { 997 mbox_data &= ~MBOX_DOWN_MSG; 998 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 999 1000 mbox = &mw->mbox; 1001 mdev = &mbox->dev[0]; 1002 otx2_sync_mbox_bbuf(mbox, 0); 1003 1004 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1005 if (hdr->num_msgs) 1006 queue_work(pf->mbox_wq, &mw->mbox_wrk); 1007 1008 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF", 1009 BIT_ULL(0)); 1010 } 1011 1012 return IRQ_HANDLED; 1013 } 1014 1015 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 1016 { 1017 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1018 1019 /* Disable AF => PF mailbox IRQ */ 1020 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 1021 free_irq(vector, pf); 1022 } 1023 1024 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1025 { 1026 struct otx2_hw *hw = &pf->hw; 1027 struct msg_req *req; 1028 char *irq_name; 1029 int err; 1030 1031 /* Register mailbox interrupt handler */ 1032 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1033 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1034 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1035 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1036 if (err) { 1037 dev_err(pf->dev, 1038 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1039 return err; 1040 } 1041 1042 /* Enable mailbox interrupt for msgs coming from AF. 1043 * First clear to avoid spurious interrupts, if any. 1044 */ 1045 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1046 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1047 1048 if (!probe_af) 1049 return 0; 1050 1051 /* Check mailbox communication with AF */ 1052 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1053 if (!req) { 1054 otx2_disable_mbox_intr(pf); 1055 return -ENOMEM; 1056 } 1057 err = otx2_sync_mbox_msg(&pf->mbox); 1058 if (err) { 1059 dev_warn(pf->dev, 1060 "AF not responding to mailbox, deferring probe\n"); 1061 otx2_disable_mbox_intr(pf); 1062 return -EPROBE_DEFER; 1063 } 1064 1065 return 0; 1066 } 1067 1068 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1069 { 1070 struct mbox *mbox = &pf->mbox; 1071 1072 if (pf->mbox_wq) { 1073 destroy_workqueue(pf->mbox_wq); 1074 pf->mbox_wq = NULL; 1075 } 1076 1077 if (mbox->mbox.hwbase) 1078 iounmap((void __iomem *)mbox->mbox.hwbase); 1079 1080 otx2_mbox_destroy(&mbox->mbox); 1081 otx2_mbox_destroy(&mbox->mbox_up); 1082 } 1083 1084 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1085 { 1086 struct mbox *mbox = &pf->mbox; 1087 void __iomem *hwbase; 1088 int err; 1089 1090 mbox->pfvf = pf; 1091 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1092 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1093 if (!pf->mbox_wq) 1094 return -ENOMEM; 1095 1096 /* Mailbox is a reserved memory (in RAM) region shared between 1097 * admin function (i.e AF) and this PF, shouldn't be mapped as 1098 * device memory to allow unaligned accesses. 1099 */ 1100 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1101 MBOX_SIZE); 1102 if (!hwbase) { 1103 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1104 err = -ENOMEM; 1105 goto exit; 1106 } 1107 1108 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1109 MBOX_DIR_PFAF, 1); 1110 if (err) 1111 goto exit; 1112 1113 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1114 MBOX_DIR_PFAF_UP, 1); 1115 if (err) 1116 goto exit; 1117 1118 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1119 if (err) 1120 goto exit; 1121 1122 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1123 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1124 mutex_init(&mbox->lock); 1125 1126 return 0; 1127 exit: 1128 otx2_pfaf_mbox_destroy(pf); 1129 return err; 1130 } 1131 1132 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1133 { 1134 struct msg_req *msg; 1135 int err; 1136 1137 mutex_lock(&pf->mbox.lock); 1138 if (enable) 1139 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1140 else 1141 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1142 1143 if (!msg) { 1144 mutex_unlock(&pf->mbox.lock); 1145 return -ENOMEM; 1146 } 1147 1148 err = otx2_sync_mbox_msg(&pf->mbox); 1149 mutex_unlock(&pf->mbox.lock); 1150 return err; 1151 } 1152 1153 int otx2_reset_mac_stats(struct otx2_nic *pfvf) 1154 { 1155 struct msg_req *req; 1156 int err; 1157 1158 mutex_lock(&pfvf->mbox.lock); 1159 req = otx2_mbox_alloc_msg_cgx_stats_rst(&pfvf->mbox); 1160 if (!req) { 1161 mutex_unlock(&pfvf->mbox.lock); 1162 return -ENOMEM; 1163 } 1164 1165 err = otx2_sync_mbox_msg(&pfvf->mbox); 1166 mutex_unlock(&pfvf->mbox.lock); 1167 return err; 1168 } 1169 1170 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1171 { 1172 struct msg_req *msg; 1173 int err; 1174 1175 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1176 pf->flow_cfg->dmacflt_max_flows)) 1177 netdev_warn(pf->netdev, 1178 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1179 1180 mutex_lock(&pf->mbox.lock); 1181 if (enable) 1182 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1183 else 1184 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1185 1186 if (!msg) { 1187 mutex_unlock(&pf->mbox.lock); 1188 return -ENOMEM; 1189 } 1190 1191 err = otx2_sync_mbox_msg(&pf->mbox); 1192 mutex_unlock(&pf->mbox.lock); 1193 return err; 1194 } 1195 1196 int otx2_set_real_num_queues(struct net_device *netdev, 1197 int tx_queues, int rx_queues) 1198 { 1199 int err; 1200 1201 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1202 if (err) { 1203 netdev_err(netdev, 1204 "Failed to set no of Tx queues: %d\n", tx_queues); 1205 return err; 1206 } 1207 1208 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1209 if (err) 1210 netdev_err(netdev, 1211 "Failed to set no of Rx queues: %d\n", rx_queues); 1212 return err; 1213 } 1214 EXPORT_SYMBOL(otx2_set_real_num_queues); 1215 1216 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1217 "NIX_SQOPERR_OOR", 1218 "NIX_SQOPERR_CTX_FAULT", 1219 "NIX_SQOPERR_CTX_POISON", 1220 "NIX_SQOPERR_DISABLED", 1221 "NIX_SQOPERR_SIZE_ERR", 1222 "NIX_SQOPERR_OFLOW", 1223 "NIX_SQOPERR_SQB_NULL", 1224 "NIX_SQOPERR_SQB_FAULT", 1225 "NIX_SQOPERR_SQE_SZ_ZERO", 1226 }; 1227 1228 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1229 "NIX_MNQERR_SQ_CTX_FAULT", 1230 "NIX_MNQERR_SQ_CTX_POISON", 1231 "NIX_MNQERR_SQB_FAULT", 1232 "NIX_MNQERR_SQB_POISON", 1233 "NIX_MNQERR_TOTAL_ERR", 1234 "NIX_MNQERR_LSO_ERR", 1235 "NIX_MNQERR_CQ_QUERY_ERR", 1236 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1237 "NIX_MNQERR_MAXLEN_ERR", 1238 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1239 }; 1240 1241 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1242 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1243 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1244 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1245 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1246 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1247 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1248 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1249 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1250 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1251 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1252 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1253 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1254 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1255 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1256 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1257 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1258 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1259 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1260 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1261 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1262 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1263 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1264 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1265 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1266 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1267 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1268 }; 1269 1270 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1271 { 1272 struct otx2_nic *pf = data; 1273 struct otx2_snd_queue *sq; 1274 u64 val, *ptr; 1275 u64 qidx = 0; 1276 1277 /* CQ */ 1278 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1279 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1280 val = otx2_atomic64_add((qidx << 44), ptr); 1281 1282 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1283 (val & NIX_CQERRINT_BITS)); 1284 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1285 continue; 1286 1287 if (val & BIT_ULL(42)) { 1288 netdev_err(pf->netdev, 1289 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1290 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1291 } else { 1292 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1293 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1294 qidx); 1295 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1296 netdev_err(pf->netdev, 1297 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1298 qidx); 1299 } 1300 1301 schedule_work(&pf->reset_task); 1302 } 1303 1304 /* SQ */ 1305 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1306 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1307 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1308 1309 sq = &pf->qset.sq[qidx]; 1310 if (!sq->sqb_ptrs) 1311 continue; 1312 1313 /* Below debug registers captures first errors corresponding to 1314 * those registers. We don't have to check against SQ qid as 1315 * these are fatal errors. 1316 */ 1317 1318 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1319 val = otx2_atomic64_add((qidx << 44), ptr); 1320 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1321 (val & NIX_SQINT_BITS)); 1322 1323 if (val & BIT_ULL(42)) { 1324 netdev_err(pf->netdev, 1325 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1326 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1327 goto done; 1328 } 1329 1330 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1331 if (!(sq_op_err_dbg & BIT(44))) 1332 goto chk_mnq_err_dbg; 1333 1334 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1335 netdev_err(pf->netdev, 1336 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1337 qidx, sq_op_err_dbg, 1338 nix_sqoperr_e_str[sq_op_err_code], 1339 sq_op_err_code); 1340 1341 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1342 1343 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1344 goto chk_mnq_err_dbg; 1345 1346 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1347 * TODO: But we are in irq context. How to call mbox functions which does sleep 1348 */ 1349 1350 chk_mnq_err_dbg: 1351 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1352 if (!(mnq_err_dbg & BIT(44))) 1353 goto chk_snd_err_dbg; 1354 1355 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1356 netdev_err(pf->netdev, 1357 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1358 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1359 mnq_err_code); 1360 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1361 1362 chk_snd_err_dbg: 1363 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1364 if (snd_err_dbg & BIT(44)) { 1365 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1366 netdev_err(pf->netdev, 1367 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1368 qidx, snd_err_dbg, 1369 nix_snd_status_e_str[snd_err_code], 1370 snd_err_code); 1371 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1372 } 1373 1374 done: 1375 /* Print values and reset */ 1376 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1377 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1378 qidx); 1379 1380 schedule_work(&pf->reset_task); 1381 } 1382 1383 return IRQ_HANDLED; 1384 } 1385 1386 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1387 { 1388 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1389 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1390 int qidx = cq_poll->cint_idx; 1391 1392 /* Disable interrupts. 1393 * 1394 * Completion interrupts behave in a level-triggered interrupt 1395 * fashion, and hence have to be cleared only after it is serviced. 1396 */ 1397 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1398 1399 /* Schedule NAPI */ 1400 pf->napi_events++; 1401 napi_schedule_irqoff(&cq_poll->napi); 1402 1403 return IRQ_HANDLED; 1404 } 1405 1406 static void otx2_disable_napi(struct otx2_nic *pf) 1407 { 1408 struct otx2_qset *qset = &pf->qset; 1409 struct otx2_cq_poll *cq_poll; 1410 int qidx; 1411 1412 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1413 cq_poll = &qset->napi[qidx]; 1414 cancel_work_sync(&cq_poll->dim.work); 1415 napi_disable(&cq_poll->napi); 1416 netif_napi_del(&cq_poll->napi); 1417 } 1418 } 1419 1420 static void otx2_free_cq_res(struct otx2_nic *pf) 1421 { 1422 struct otx2_qset *qset = &pf->qset; 1423 struct otx2_cq_queue *cq; 1424 int qidx; 1425 1426 /* Disable CQs */ 1427 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1428 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1429 cq = &qset->cq[qidx]; 1430 qmem_free(pf->dev, cq->cqe); 1431 } 1432 } 1433 1434 static void otx2_free_sq_res(struct otx2_nic *pf) 1435 { 1436 struct otx2_qset *qset = &pf->qset; 1437 struct otx2_snd_queue *sq; 1438 int qidx; 1439 1440 /* Disable SQs */ 1441 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1442 /* Free SQB pointers */ 1443 otx2_sq_free_sqbs(pf); 1444 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1445 sq = &qset->sq[qidx]; 1446 /* Skip freeing Qos queues if they are not initialized */ 1447 if (!sq->sqe) 1448 continue; 1449 qmem_free(pf->dev, sq->sqe); 1450 qmem_free(pf->dev, sq->tso_hdrs); 1451 kfree(sq->sg); 1452 kfree(sq->sqb_ptrs); 1453 } 1454 } 1455 1456 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1457 { 1458 int frame_size; 1459 int total_size; 1460 int rbuf_size; 1461 1462 if (pf->hw.rbuf_len) 1463 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1464 1465 /* The data transferred by NIX to memory consists of actual packet 1466 * plus additional data which has timestamp and/or EDSA/HIGIG2 1467 * headers if interface is configured in corresponding modes. 1468 * NIX transfers entire data using 6 segments/buffers and writes 1469 * a CQE_RX descriptor with those segment addresses. First segment 1470 * has additional data prepended to packet. Also software omits a 1471 * headroom of 128 bytes in each segment. Hence the total size of 1472 * memory needed to receive a packet with 'mtu' is: 1473 * frame size = mtu + additional data; 1474 * memory = frame_size + headroom * 6; 1475 * each receive buffer size = memory / 6; 1476 */ 1477 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1478 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1479 rbuf_size = total_size / 6; 1480 1481 return ALIGN(rbuf_size, 2048); 1482 } 1483 1484 static int otx2_init_hw_resources(struct otx2_nic *pf) 1485 { 1486 struct nix_lf_free_req *free_req; 1487 struct mbox *mbox = &pf->mbox; 1488 struct otx2_hw *hw = &pf->hw; 1489 struct msg_req *req; 1490 int err = 0, lvl; 1491 1492 /* Set required NPA LF's pool counts 1493 * Auras and Pools are used in a 1:1 mapping, 1494 * so, aura count = pool count. 1495 */ 1496 hw->rqpool_cnt = hw->rx_queues; 1497 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1498 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1499 1500 /* Maximum hardware supported transmit length */ 1501 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1502 1503 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1504 1505 mutex_lock(&mbox->lock); 1506 /* NPA init */ 1507 err = otx2_config_npa(pf); 1508 if (err) 1509 goto exit; 1510 1511 /* NIX init */ 1512 err = otx2_config_nix(pf); 1513 if (err) 1514 goto err_free_npa_lf; 1515 1516 /* Enable backpressure for CGX mapped PF/VFs */ 1517 if (!is_otx2_lbkvf(pf->pdev)) 1518 otx2_nix_config_bp(pf, true); 1519 1520 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1521 err = otx2_rq_aura_pool_init(pf); 1522 if (err) { 1523 mutex_unlock(&mbox->lock); 1524 goto err_free_nix_lf; 1525 } 1526 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1527 err = otx2_sq_aura_pool_init(pf); 1528 if (err) { 1529 mutex_unlock(&mbox->lock); 1530 goto err_free_rq_ptrs; 1531 } 1532 1533 err = otx2_txsch_alloc(pf); 1534 if (err) { 1535 mutex_unlock(&mbox->lock); 1536 goto err_free_sq_ptrs; 1537 } 1538 1539 #ifdef CONFIG_DCB 1540 if (pf->pfc_en) { 1541 err = otx2_pfc_txschq_alloc(pf); 1542 if (err) { 1543 mutex_unlock(&mbox->lock); 1544 goto err_free_sq_ptrs; 1545 } 1546 } 1547 #endif 1548 1549 err = otx2_config_nix_queues(pf); 1550 if (err) { 1551 mutex_unlock(&mbox->lock); 1552 goto err_free_txsch; 1553 } 1554 1555 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1556 err = otx2_txschq_config(pf, lvl, 0, false); 1557 if (err) { 1558 mutex_unlock(&mbox->lock); 1559 goto err_free_nix_queues; 1560 } 1561 } 1562 1563 #ifdef CONFIG_DCB 1564 if (pf->pfc_en) { 1565 err = otx2_pfc_txschq_config(pf); 1566 if (err) { 1567 mutex_unlock(&mbox->lock); 1568 goto err_free_nix_queues; 1569 } 1570 } 1571 #endif 1572 1573 mutex_unlock(&mbox->lock); 1574 return err; 1575 1576 err_free_nix_queues: 1577 otx2_free_sq_res(pf); 1578 otx2_free_cq_res(pf); 1579 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1580 err_free_txsch: 1581 otx2_txschq_stop(pf); 1582 err_free_sq_ptrs: 1583 otx2_sq_free_sqbs(pf); 1584 err_free_rq_ptrs: 1585 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1586 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1587 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1588 otx2_aura_pool_free(pf); 1589 err_free_nix_lf: 1590 mutex_lock(&mbox->lock); 1591 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1592 if (free_req) { 1593 free_req->flags = NIX_LF_DISABLE_FLOWS; 1594 if (otx2_sync_mbox_msg(mbox)) 1595 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1596 } 1597 err_free_npa_lf: 1598 /* Reset NPA LF */ 1599 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1600 if (req) { 1601 if (otx2_sync_mbox_msg(mbox)) 1602 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1603 } 1604 exit: 1605 mutex_unlock(&mbox->lock); 1606 return err; 1607 } 1608 1609 static void otx2_free_hw_resources(struct otx2_nic *pf) 1610 { 1611 struct otx2_qset *qset = &pf->qset; 1612 struct nix_lf_free_req *free_req; 1613 struct mbox *mbox = &pf->mbox; 1614 struct otx2_cq_queue *cq; 1615 struct otx2_pool *pool; 1616 struct msg_req *req; 1617 int pool_id; 1618 int qidx; 1619 1620 /* Ensure all SQE are processed */ 1621 otx2_sqb_flush(pf); 1622 1623 /* Stop transmission */ 1624 otx2_txschq_stop(pf); 1625 1626 #ifdef CONFIG_DCB 1627 if (pf->pfc_en) 1628 otx2_pfc_txschq_stop(pf); 1629 #endif 1630 1631 otx2_clean_qos_queues(pf); 1632 1633 mutex_lock(&mbox->lock); 1634 /* Disable backpressure */ 1635 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1636 otx2_nix_config_bp(pf, false); 1637 mutex_unlock(&mbox->lock); 1638 1639 /* Disable RQs */ 1640 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1641 1642 /*Dequeue all CQEs */ 1643 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1644 cq = &qset->cq[qidx]; 1645 if (cq->cq_type == CQ_RX) 1646 otx2_cleanup_rx_cqes(pf, cq, qidx); 1647 else 1648 otx2_cleanup_tx_cqes(pf, cq); 1649 } 1650 otx2_free_pending_sqe(pf); 1651 1652 otx2_free_sq_res(pf); 1653 1654 /* Free RQ buffer pointers*/ 1655 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1656 1657 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1658 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1659 pool = &pf->qset.pool[pool_id]; 1660 page_pool_destroy(pool->page_pool); 1661 pool->page_pool = NULL; 1662 } 1663 1664 otx2_free_cq_res(pf); 1665 1666 /* Free all ingress bandwidth profiles allocated */ 1667 cn10k_free_all_ipolicers(pf); 1668 1669 mutex_lock(&mbox->lock); 1670 /* Reset NIX LF */ 1671 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1672 if (free_req) { 1673 free_req->flags = NIX_LF_DISABLE_FLOWS; 1674 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1675 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1676 if (otx2_sync_mbox_msg(mbox)) 1677 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1678 } 1679 mutex_unlock(&mbox->lock); 1680 1681 /* Disable NPA Pool and Aura hw context */ 1682 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1683 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1684 otx2_aura_pool_free(pf); 1685 1686 mutex_lock(&mbox->lock); 1687 /* Reset NPA LF */ 1688 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1689 if (req) { 1690 if (otx2_sync_mbox_msg(mbox)) 1691 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1692 } 1693 mutex_unlock(&mbox->lock); 1694 } 1695 1696 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) 1697 { 1698 int vf; 1699 1700 /* The AF driver will determine whether to allow the VF netdev or not */ 1701 if (is_otx2_vf(pfvf->pcifunc)) 1702 return true; 1703 1704 /* check if there are any trusted VFs associated with the PF netdev */ 1705 for (vf = 0; vf < pci_num_vf(pfvf->pdev); vf++) 1706 if (pfvf->vf_configs[vf].trusted) 1707 return true; 1708 return false; 1709 } 1710 1711 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1712 { 1713 struct net_device *netdev = pf->netdev; 1714 struct nix_rx_mode *req; 1715 bool promisc = false; 1716 1717 if (!(netdev->flags & IFF_UP)) 1718 return; 1719 1720 if ((netdev->flags & IFF_PROMISC) || 1721 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1722 promisc = true; 1723 } 1724 1725 /* Write unicast address to mcam entries or del from mcam */ 1726 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1727 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1728 1729 mutex_lock(&pf->mbox.lock); 1730 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1731 if (!req) { 1732 mutex_unlock(&pf->mbox.lock); 1733 return; 1734 } 1735 1736 req->mode = NIX_RX_MODE_UCAST; 1737 1738 if (promisc) 1739 req->mode |= NIX_RX_MODE_PROMISC; 1740 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1741 req->mode |= NIX_RX_MODE_ALLMULTI; 1742 1743 if (otx2_promisc_use_mce_list(pf)) 1744 req->mode |= NIX_RX_MODE_USE_MCE; 1745 1746 otx2_sync_mbox_msg(&pf->mbox); 1747 mutex_unlock(&pf->mbox.lock); 1748 } 1749 1750 static void otx2_set_irq_coalesce(struct otx2_nic *pfvf) 1751 { 1752 int cint; 1753 1754 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++) 1755 otx2_config_irq_coalescing(pfvf, cint); 1756 } 1757 1758 static void otx2_dim_work(struct work_struct *w) 1759 { 1760 struct dim_cq_moder cur_moder; 1761 struct otx2_cq_poll *cq_poll; 1762 struct otx2_nic *pfvf; 1763 struct dim *dim; 1764 1765 dim = container_of(w, struct dim, work); 1766 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1767 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1768 pfvf = (struct otx2_nic *)cq_poll->dev; 1769 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1770 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1771 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1772 NAPI_POLL_WEIGHT : cur_moder.pkts; 1773 otx2_set_irq_coalesce(pfvf); 1774 dim->state = DIM_START_MEASURE; 1775 } 1776 1777 int otx2_open(struct net_device *netdev) 1778 { 1779 struct otx2_nic *pf = netdev_priv(netdev); 1780 struct otx2_cq_poll *cq_poll = NULL; 1781 struct otx2_qset *qset = &pf->qset; 1782 int err = 0, qidx, vec; 1783 char *irq_name; 1784 1785 netif_carrier_off(netdev); 1786 1787 /* RQ and SQs are mapped to different CQs, 1788 * so find out max CQ IRQs (i.e CINTs) needed. 1789 */ 1790 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues; 1791 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1792 pf->hw.tc_tx_queues); 1793 1794 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1795 1796 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1797 if (!qset->napi) 1798 return -ENOMEM; 1799 1800 /* CQ size of RQ */ 1801 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1802 /* CQ size of SQ */ 1803 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1804 1805 err = -ENOMEM; 1806 qset->cq = kcalloc(pf->qset.cq_cnt, 1807 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1808 if (!qset->cq) 1809 goto err_free_mem; 1810 1811 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1812 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1813 if (!qset->sq) 1814 goto err_free_mem; 1815 1816 qset->rq = kcalloc(pf->hw.rx_queues, 1817 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1818 if (!qset->rq) 1819 goto err_free_mem; 1820 1821 err = otx2_init_hw_resources(pf); 1822 if (err) 1823 goto err_free_mem; 1824 1825 /* Register NAPI handler */ 1826 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1827 cq_poll = &qset->napi[qidx]; 1828 cq_poll->cint_idx = qidx; 1829 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1830 * 'cq_ids[0]' points to RQ's CQ and 1831 * 'cq_ids[1]' points to SQ's CQ and 1832 * 'cq_ids[2]' points to XDP's CQ and 1833 */ 1834 cq_poll->cq_ids[CQ_RX] = 1835 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1836 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1837 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1838 if (pf->xdp_prog) 1839 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1840 (qidx + pf->hw.rx_queues + 1841 pf->hw.tx_queues) : 1842 CINT_INVALID_CQ; 1843 else 1844 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1845 1846 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1847 (qidx + pf->hw.rx_queues + 1848 pf->hw.non_qos_queues) : 1849 CINT_INVALID_CQ; 1850 1851 cq_poll->dev = (void *)pf; 1852 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1853 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1854 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1855 napi_enable(&cq_poll->napi); 1856 } 1857 1858 /* Set maximum frame size allowed in HW */ 1859 err = otx2_hw_set_mtu(pf, netdev->mtu); 1860 if (err) 1861 goto err_disable_napi; 1862 1863 /* Setup segmentation algorithms, if failed, clear offload capability */ 1864 otx2_setup_segmentation(pf); 1865 1866 /* Initialize RSS */ 1867 err = otx2_rss_init(pf); 1868 if (err) 1869 goto err_disable_napi; 1870 1871 /* Register Queue IRQ handlers */ 1872 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1873 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1874 1875 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1876 1877 err = request_irq(pci_irq_vector(pf->pdev, vec), 1878 otx2_q_intr_handler, 0, irq_name, pf); 1879 if (err) { 1880 dev_err(pf->dev, 1881 "RVUPF%d: IRQ registration failed for QERR\n", 1882 rvu_get_pf(pf->pcifunc)); 1883 goto err_disable_napi; 1884 } 1885 1886 /* Enable QINT IRQ */ 1887 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1888 1889 /* Register CQ IRQ handlers */ 1890 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1891 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1892 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1893 1894 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1895 qidx); 1896 1897 err = request_irq(pci_irq_vector(pf->pdev, vec), 1898 otx2_cq_intr_handler, 0, irq_name, 1899 &qset->napi[qidx]); 1900 if (err) { 1901 dev_err(pf->dev, 1902 "RVUPF%d: IRQ registration failed for CQ%d\n", 1903 rvu_get_pf(pf->pcifunc), qidx); 1904 goto err_free_cints; 1905 } 1906 vec++; 1907 1908 otx2_config_irq_coalescing(pf, qidx); 1909 1910 /* Enable CQ IRQ */ 1911 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1912 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1913 } 1914 1915 otx2_set_cints_affinity(pf); 1916 1917 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1918 otx2_enable_rxvlan(pf, true); 1919 1920 /* When reinitializing enable time stamping if it is enabled before */ 1921 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1922 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1923 otx2_config_hw_tx_tstamp(pf, true); 1924 } 1925 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1926 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1927 otx2_config_hw_rx_tstamp(pf, true); 1928 } 1929 1930 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1931 /* 'intf_down' may be checked on any cpu */ 1932 smp_wmb(); 1933 1934 /* Enable QoS configuration before starting tx queues */ 1935 otx2_qos_config_txschq(pf); 1936 1937 /* we have already received link status notification */ 1938 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1939 otx2_handle_link_event(pf); 1940 1941 /* Install DMAC Filters */ 1942 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1943 otx2_dmacflt_reinstall_flows(pf); 1944 1945 otx2_tc_apply_ingress_police_rules(pf); 1946 1947 err = otx2_rxtx_enable(pf, true); 1948 /* If a mbox communication error happens at this point then interface 1949 * will end up in a state such that it is in down state but hardware 1950 * mcam entries are enabled to receive the packets. Hence disable the 1951 * packet I/O. 1952 */ 1953 if (err == -EIO) 1954 goto err_disable_rxtx; 1955 else if (err) 1956 goto err_tx_stop_queues; 1957 1958 otx2_do_set_rx_mode(pf); 1959 1960 return 0; 1961 1962 err_disable_rxtx: 1963 otx2_rxtx_enable(pf, false); 1964 err_tx_stop_queues: 1965 netif_tx_stop_all_queues(netdev); 1966 netif_carrier_off(netdev); 1967 pf->flags |= OTX2_FLAG_INTF_DOWN; 1968 err_free_cints: 1969 otx2_free_cints(pf, qidx); 1970 vec = pci_irq_vector(pf->pdev, 1971 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1972 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1973 free_irq(vec, pf); 1974 err_disable_napi: 1975 otx2_disable_napi(pf); 1976 otx2_free_hw_resources(pf); 1977 err_free_mem: 1978 kfree(qset->sq); 1979 kfree(qset->cq); 1980 kfree(qset->rq); 1981 kfree(qset->napi); 1982 return err; 1983 } 1984 EXPORT_SYMBOL(otx2_open); 1985 1986 int otx2_stop(struct net_device *netdev) 1987 { 1988 struct otx2_nic *pf = netdev_priv(netdev); 1989 struct otx2_cq_poll *cq_poll = NULL; 1990 struct otx2_qset *qset = &pf->qset; 1991 struct otx2_rss_info *rss; 1992 int qidx, vec, wrk; 1993 1994 /* If the DOWN flag is set resources are already freed */ 1995 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1996 return 0; 1997 1998 netif_carrier_off(netdev); 1999 netif_tx_stop_all_queues(netdev); 2000 2001 pf->flags |= OTX2_FLAG_INTF_DOWN; 2002 /* 'intf_down' may be checked on any cpu */ 2003 smp_wmb(); 2004 2005 /* First stop packet Rx/Tx */ 2006 otx2_rxtx_enable(pf, false); 2007 2008 /* Clear RSS enable flag */ 2009 rss = &pf->hw.rss_info; 2010 rss->enable = false; 2011 if (!netif_is_rxfh_configured(netdev)) 2012 kfree(rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 2013 2014 /* Cleanup Queue IRQ */ 2015 vec = pci_irq_vector(pf->pdev, 2016 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2017 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2018 free_irq(vec, pf); 2019 2020 /* Cleanup CQ NAPI and IRQ */ 2021 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2022 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2023 /* Disable interrupt */ 2024 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 2025 2026 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 2027 2028 cq_poll = &qset->napi[qidx]; 2029 napi_synchronize(&cq_poll->napi); 2030 vec++; 2031 } 2032 2033 netif_tx_disable(netdev); 2034 2035 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 2036 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 2037 devm_kfree(pf->dev, pf->refill_wrk); 2038 2039 otx2_free_hw_resources(pf); 2040 otx2_free_cints(pf, pf->hw.cint_cnt); 2041 otx2_disable_napi(pf); 2042 2043 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2044 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2045 2046 2047 kfree(qset->sq); 2048 kfree(qset->cq); 2049 kfree(qset->rq); 2050 kfree(qset->napi); 2051 /* Do not clear RQ/SQ ringsize settings */ 2052 memset_startat(qset, 0, sqe_cnt); 2053 return 0; 2054 } 2055 EXPORT_SYMBOL(otx2_stop); 2056 2057 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 2058 { 2059 struct otx2_nic *pf = netdev_priv(netdev); 2060 int qidx = skb_get_queue_mapping(skb); 2061 struct otx2_snd_queue *sq; 2062 struct netdev_queue *txq; 2063 int sq_idx; 2064 2065 /* XDP SQs are not mapped with TXQs 2066 * advance qid to derive correct sq mapped with QOS 2067 */ 2068 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2069 2070 /* Check for minimum and maximum packet length */ 2071 if (skb->len <= ETH_HLEN || 2072 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2073 dev_kfree_skb(skb); 2074 return NETDEV_TX_OK; 2075 } 2076 2077 sq = &pf->qset.sq[sq_idx]; 2078 txq = netdev_get_tx_queue(netdev, qidx); 2079 2080 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 2081 netif_tx_stop_queue(txq); 2082 2083 /* Check again, incase SQBs got freed up */ 2084 smp_mb(); 2085 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2086 > sq->sqe_thresh) 2087 netif_tx_wake_queue(txq); 2088 2089 return NETDEV_TX_BUSY; 2090 } 2091 2092 return NETDEV_TX_OK; 2093 } 2094 2095 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2096 u16 htb_maj_id) 2097 { 2098 u16 classid; 2099 2100 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2101 classid = TC_H_MIN(skb->priority); 2102 else 2103 classid = READ_ONCE(pf->qos.defcls); 2104 2105 if (!classid) 2106 return 0; 2107 2108 return otx2_get_txq_by_classid(pf, classid); 2109 } 2110 2111 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2112 struct net_device *sb_dev) 2113 { 2114 struct otx2_nic *pf = netdev_priv(netdev); 2115 bool qos_enabled; 2116 #ifdef CONFIG_DCB 2117 u8 vlan_prio; 2118 #endif 2119 int txq; 2120 2121 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2122 if (unlikely(qos_enabled)) { 2123 /* This smp_load_acquire() pairs with smp_store_release() in 2124 * otx2_qos_root_add() called from htb offload root creation 2125 */ 2126 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2127 2128 if (unlikely(htb_maj_id)) { 2129 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2130 if (txq > 0) 2131 return txq; 2132 goto process_pfc; 2133 } 2134 } 2135 2136 process_pfc: 2137 #ifdef CONFIG_DCB 2138 if (!skb_vlan_tag_present(skb)) 2139 goto pick_tx; 2140 2141 vlan_prio = skb->vlan_tci >> 13; 2142 if ((vlan_prio > pf->hw.tx_queues - 1) || 2143 !pf->pfc_alloc_status[vlan_prio]) 2144 goto pick_tx; 2145 2146 return vlan_prio; 2147 2148 pick_tx: 2149 #endif 2150 txq = netdev_pick_tx(netdev, skb, NULL); 2151 if (unlikely(qos_enabled)) 2152 return txq % pf->hw.tx_queues; 2153 2154 return txq; 2155 } 2156 EXPORT_SYMBOL(otx2_select_queue); 2157 2158 static netdev_features_t otx2_fix_features(struct net_device *dev, 2159 netdev_features_t features) 2160 { 2161 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2162 features |= NETIF_F_HW_VLAN_STAG_RX; 2163 else 2164 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2165 2166 return features; 2167 } 2168 2169 static void otx2_set_rx_mode(struct net_device *netdev) 2170 { 2171 struct otx2_nic *pf = netdev_priv(netdev); 2172 2173 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2174 } 2175 2176 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2177 { 2178 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2179 2180 otx2_do_set_rx_mode(pf); 2181 } 2182 2183 static int otx2_set_features(struct net_device *netdev, 2184 netdev_features_t features) 2185 { 2186 netdev_features_t changed = features ^ netdev->features; 2187 struct otx2_nic *pf = netdev_priv(netdev); 2188 2189 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2190 return otx2_cgx_config_loopback(pf, 2191 features & NETIF_F_LOOPBACK); 2192 2193 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2194 return otx2_enable_rxvlan(pf, 2195 features & NETIF_F_HW_VLAN_CTAG_RX); 2196 2197 return otx2_handle_ntuple_tc_features(netdev, features); 2198 } 2199 2200 static void otx2_reset_task(struct work_struct *work) 2201 { 2202 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2203 2204 if (!netif_running(pf->netdev)) 2205 return; 2206 2207 rtnl_lock(); 2208 otx2_stop(pf->netdev); 2209 pf->reset_count++; 2210 otx2_open(pf->netdev); 2211 netif_trans_update(pf->netdev); 2212 rtnl_unlock(); 2213 } 2214 2215 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2216 { 2217 struct msg_req *req; 2218 int err; 2219 2220 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2221 return 0; 2222 2223 mutex_lock(&pfvf->mbox.lock); 2224 if (enable) 2225 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2226 else 2227 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2228 if (!req) { 2229 mutex_unlock(&pfvf->mbox.lock); 2230 return -ENOMEM; 2231 } 2232 2233 err = otx2_sync_mbox_msg(&pfvf->mbox); 2234 if (err) { 2235 mutex_unlock(&pfvf->mbox.lock); 2236 return err; 2237 } 2238 2239 mutex_unlock(&pfvf->mbox.lock); 2240 if (enable) 2241 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2242 else 2243 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2244 return 0; 2245 } 2246 2247 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2248 { 2249 struct msg_req *req; 2250 int err; 2251 2252 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2253 return 0; 2254 2255 mutex_lock(&pfvf->mbox.lock); 2256 if (enable) 2257 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2258 else 2259 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2260 if (!req) { 2261 mutex_unlock(&pfvf->mbox.lock); 2262 return -ENOMEM; 2263 } 2264 2265 err = otx2_sync_mbox_msg(&pfvf->mbox); 2266 if (err) { 2267 mutex_unlock(&pfvf->mbox.lock); 2268 return err; 2269 } 2270 2271 mutex_unlock(&pfvf->mbox.lock); 2272 if (enable) 2273 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2274 else 2275 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2276 return 0; 2277 } 2278 2279 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2280 { 2281 struct otx2_nic *pfvf = netdev_priv(netdev); 2282 struct hwtstamp_config config; 2283 2284 if (!pfvf->ptp) 2285 return -ENODEV; 2286 2287 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2288 return -EFAULT; 2289 2290 switch (config.tx_type) { 2291 case HWTSTAMP_TX_OFF: 2292 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2293 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2294 2295 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2296 otx2_config_hw_tx_tstamp(pfvf, false); 2297 break; 2298 case HWTSTAMP_TX_ONESTEP_SYNC: 2299 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2300 return -ERANGE; 2301 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2302 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2303 msecs_to_jiffies(500)); 2304 fallthrough; 2305 case HWTSTAMP_TX_ON: 2306 otx2_config_hw_tx_tstamp(pfvf, true); 2307 break; 2308 default: 2309 return -ERANGE; 2310 } 2311 2312 switch (config.rx_filter) { 2313 case HWTSTAMP_FILTER_NONE: 2314 otx2_config_hw_rx_tstamp(pfvf, false); 2315 break; 2316 case HWTSTAMP_FILTER_ALL: 2317 case HWTSTAMP_FILTER_SOME: 2318 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2319 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2320 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2321 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2322 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2323 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2324 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2325 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2326 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2327 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2328 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2329 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2330 otx2_config_hw_rx_tstamp(pfvf, true); 2331 config.rx_filter = HWTSTAMP_FILTER_ALL; 2332 break; 2333 default: 2334 return -ERANGE; 2335 } 2336 2337 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2338 2339 return copy_to_user(ifr->ifr_data, &config, 2340 sizeof(config)) ? -EFAULT : 0; 2341 } 2342 EXPORT_SYMBOL(otx2_config_hwtstamp); 2343 2344 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2345 { 2346 struct otx2_nic *pfvf = netdev_priv(netdev); 2347 struct hwtstamp_config *cfg = &pfvf->tstamp; 2348 2349 switch (cmd) { 2350 case SIOCSHWTSTAMP: 2351 return otx2_config_hwtstamp(netdev, req); 2352 case SIOCGHWTSTAMP: 2353 return copy_to_user(req->ifr_data, cfg, 2354 sizeof(*cfg)) ? -EFAULT : 0; 2355 default: 2356 return -EOPNOTSUPP; 2357 } 2358 } 2359 EXPORT_SYMBOL(otx2_ioctl); 2360 2361 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2362 { 2363 struct npc_install_flow_req *req; 2364 int err; 2365 2366 mutex_lock(&pf->mbox.lock); 2367 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2368 if (!req) { 2369 err = -ENOMEM; 2370 goto out; 2371 } 2372 2373 ether_addr_copy(req->packet.dmac, mac); 2374 eth_broadcast_addr((u8 *)&req->mask.dmac); 2375 req->features = BIT_ULL(NPC_DMAC); 2376 req->channel = pf->hw.rx_chan_base; 2377 req->intf = NIX_INTF_RX; 2378 req->default_rule = 1; 2379 req->append = 1; 2380 req->vf = vf + 1; 2381 req->op = NIX_RX_ACTION_DEFAULT; 2382 2383 err = otx2_sync_mbox_msg(&pf->mbox); 2384 out: 2385 mutex_unlock(&pf->mbox.lock); 2386 return err; 2387 } 2388 2389 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2390 { 2391 struct otx2_nic *pf = netdev_priv(netdev); 2392 struct pci_dev *pdev = pf->pdev; 2393 struct otx2_vf_config *config; 2394 int ret; 2395 2396 if (!netif_running(netdev)) 2397 return -EAGAIN; 2398 2399 if (vf >= pf->total_vfs) 2400 return -EINVAL; 2401 2402 if (!is_valid_ether_addr(mac)) 2403 return -EINVAL; 2404 2405 config = &pf->vf_configs[vf]; 2406 ether_addr_copy(config->mac, mac); 2407 2408 ret = otx2_do_set_vf_mac(pf, vf, mac); 2409 if (ret == 0) 2410 dev_info(&pdev->dev, 2411 "Load/Reload VF driver\n"); 2412 2413 return ret; 2414 } 2415 2416 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2417 __be16 proto) 2418 { 2419 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2420 struct nix_vtag_config_rsp *vtag_rsp; 2421 struct npc_delete_flow_req *del_req; 2422 struct nix_vtag_config *vtag_req; 2423 struct npc_install_flow_req *req; 2424 struct otx2_vf_config *config; 2425 int err = 0; 2426 u32 idx; 2427 2428 config = &pf->vf_configs[vf]; 2429 2430 if (!vlan && !config->vlan) 2431 goto out; 2432 2433 mutex_lock(&pf->mbox.lock); 2434 2435 /* free old tx vtag entry */ 2436 if (config->vlan) { 2437 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2438 if (!vtag_req) { 2439 err = -ENOMEM; 2440 goto out; 2441 } 2442 vtag_req->cfg_type = 0; 2443 vtag_req->tx.free_vtag0 = 1; 2444 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2445 2446 err = otx2_sync_mbox_msg(&pf->mbox); 2447 if (err) 2448 goto out; 2449 } 2450 2451 if (!vlan && config->vlan) { 2452 /* rx */ 2453 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2454 if (!del_req) { 2455 err = -ENOMEM; 2456 goto out; 2457 } 2458 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2459 del_req->entry = 2460 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2461 err = otx2_sync_mbox_msg(&pf->mbox); 2462 if (err) 2463 goto out; 2464 2465 /* tx */ 2466 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2467 if (!del_req) { 2468 err = -ENOMEM; 2469 goto out; 2470 } 2471 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2472 del_req->entry = 2473 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2474 err = otx2_sync_mbox_msg(&pf->mbox); 2475 2476 goto out; 2477 } 2478 2479 /* rx */ 2480 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2481 if (!req) { 2482 err = -ENOMEM; 2483 goto out; 2484 } 2485 2486 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2487 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2488 req->packet.vlan_tci = htons(vlan); 2489 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2490 /* af fills the destination mac addr */ 2491 eth_broadcast_addr((u8 *)&req->mask.dmac); 2492 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2493 req->channel = pf->hw.rx_chan_base; 2494 req->intf = NIX_INTF_RX; 2495 req->vf = vf + 1; 2496 req->op = NIX_RX_ACTION_DEFAULT; 2497 req->vtag0_valid = true; 2498 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2499 req->set_cntr = 1; 2500 2501 err = otx2_sync_mbox_msg(&pf->mbox); 2502 if (err) 2503 goto out; 2504 2505 /* tx */ 2506 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2507 if (!vtag_req) { 2508 err = -ENOMEM; 2509 goto out; 2510 } 2511 2512 /* configure tx vtag params */ 2513 vtag_req->vtag_size = VTAGSIZE_T4; 2514 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2515 vtag_req->tx.cfg_vtag0 = 1; 2516 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2517 2518 err = otx2_sync_mbox_msg(&pf->mbox); 2519 if (err) 2520 goto out; 2521 2522 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2523 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2524 if (IS_ERR(vtag_rsp)) { 2525 err = PTR_ERR(vtag_rsp); 2526 goto out; 2527 } 2528 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2529 2530 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2531 if (!req) { 2532 err = -ENOMEM; 2533 goto out; 2534 } 2535 2536 eth_zero_addr((u8 *)&req->mask.dmac); 2537 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2538 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2539 req->features = BIT_ULL(NPC_DMAC); 2540 req->channel = pf->hw.tx_chan_base; 2541 req->intf = NIX_INTF_TX; 2542 req->vf = vf + 1; 2543 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2544 req->vtag0_def = vtag_rsp->vtag0_idx; 2545 req->vtag0_op = VTAG_INSERT; 2546 req->set_cntr = 1; 2547 2548 err = otx2_sync_mbox_msg(&pf->mbox); 2549 out: 2550 config->vlan = vlan; 2551 mutex_unlock(&pf->mbox.lock); 2552 return err; 2553 } 2554 2555 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2556 __be16 proto) 2557 { 2558 struct otx2_nic *pf = netdev_priv(netdev); 2559 struct pci_dev *pdev = pf->pdev; 2560 2561 if (!netif_running(netdev)) 2562 return -EAGAIN; 2563 2564 if (vf >= pci_num_vf(pdev)) 2565 return -EINVAL; 2566 2567 /* qos is currently unsupported */ 2568 if (vlan >= VLAN_N_VID || qos) 2569 return -EINVAL; 2570 2571 if (proto != htons(ETH_P_8021Q)) 2572 return -EPROTONOSUPPORT; 2573 2574 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2575 return -EOPNOTSUPP; 2576 2577 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2578 } 2579 2580 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2581 struct ifla_vf_info *ivi) 2582 { 2583 struct otx2_nic *pf = netdev_priv(netdev); 2584 struct pci_dev *pdev = pf->pdev; 2585 struct otx2_vf_config *config; 2586 2587 if (!netif_running(netdev)) 2588 return -EAGAIN; 2589 2590 if (vf >= pci_num_vf(pdev)) 2591 return -EINVAL; 2592 2593 config = &pf->vf_configs[vf]; 2594 ivi->vf = vf; 2595 ether_addr_copy(ivi->mac, config->mac); 2596 ivi->vlan = config->vlan; 2597 ivi->trusted = config->trusted; 2598 2599 return 0; 2600 } 2601 2602 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2603 int qidx) 2604 { 2605 struct page *page; 2606 u64 dma_addr; 2607 int err = 0; 2608 2609 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2610 offset_in_page(xdpf->data), xdpf->len, 2611 DMA_TO_DEVICE); 2612 if (dma_mapping_error(pf->dev, dma_addr)) 2613 return -ENOMEM; 2614 2615 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2616 if (!err) { 2617 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2618 page = virt_to_page(xdpf->data); 2619 put_page(page); 2620 return -ENOMEM; 2621 } 2622 return 0; 2623 } 2624 2625 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2626 struct xdp_frame **frames, u32 flags) 2627 { 2628 struct otx2_nic *pf = netdev_priv(netdev); 2629 int qidx = smp_processor_id(); 2630 struct otx2_snd_queue *sq; 2631 int drops = 0, i; 2632 2633 if (!netif_running(netdev)) 2634 return -ENETDOWN; 2635 2636 qidx += pf->hw.tx_queues; 2637 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2638 2639 /* Abort xmit if xdp queue is not */ 2640 if (unlikely(!sq)) 2641 return -ENXIO; 2642 2643 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2644 return -EINVAL; 2645 2646 for (i = 0; i < n; i++) { 2647 struct xdp_frame *xdpf = frames[i]; 2648 int err; 2649 2650 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2651 if (err) 2652 drops++; 2653 } 2654 return n - drops; 2655 } 2656 2657 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2658 { 2659 struct net_device *dev = pf->netdev; 2660 bool if_up = netif_running(pf->netdev); 2661 struct bpf_prog *old_prog; 2662 2663 if (prog && dev->mtu > MAX_XDP_MTU) { 2664 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2665 return -EOPNOTSUPP; 2666 } 2667 2668 if (if_up) 2669 otx2_stop(pf->netdev); 2670 2671 old_prog = xchg(&pf->xdp_prog, prog); 2672 2673 if (old_prog) 2674 bpf_prog_put(old_prog); 2675 2676 if (pf->xdp_prog) 2677 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2678 2679 /* Network stack and XDP shared same rx queues. 2680 * Use separate tx queues for XDP and network stack. 2681 */ 2682 if (pf->xdp_prog) { 2683 pf->hw.xdp_queues = pf->hw.rx_queues; 2684 xdp_features_set_redirect_target(dev, false); 2685 } else { 2686 pf->hw.xdp_queues = 0; 2687 xdp_features_clear_redirect_target(dev); 2688 } 2689 2690 if (if_up) 2691 otx2_open(pf->netdev); 2692 2693 return 0; 2694 } 2695 2696 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2697 { 2698 struct otx2_nic *pf = netdev_priv(netdev); 2699 2700 switch (xdp->command) { 2701 case XDP_SETUP_PROG: 2702 return otx2_xdp_setup(pf, xdp->prog); 2703 default: 2704 return -EINVAL; 2705 } 2706 } 2707 2708 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2709 int req_perm) 2710 { 2711 struct set_vf_perm *req; 2712 int rc; 2713 2714 mutex_lock(&pf->mbox.lock); 2715 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2716 if (!req) { 2717 rc = -ENOMEM; 2718 goto out; 2719 } 2720 2721 /* Let AF reset VF permissions as sriov is disabled */ 2722 if (req_perm == OTX2_RESET_VF_PERM) { 2723 req->flags |= RESET_VF_PERM; 2724 } else if (req_perm == OTX2_TRUSTED_VF) { 2725 if (pf->vf_configs[vf].trusted) 2726 req->flags |= VF_TRUSTED; 2727 } 2728 2729 req->vf = vf; 2730 rc = otx2_sync_mbox_msg(&pf->mbox); 2731 out: 2732 mutex_unlock(&pf->mbox.lock); 2733 return rc; 2734 } 2735 2736 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2737 bool enable) 2738 { 2739 struct otx2_nic *pf = netdev_priv(netdev); 2740 struct pci_dev *pdev = pf->pdev; 2741 int rc; 2742 2743 if (vf >= pci_num_vf(pdev)) 2744 return -EINVAL; 2745 2746 if (pf->vf_configs[vf].trusted == enable) 2747 return 0; 2748 2749 pf->vf_configs[vf].trusted = enable; 2750 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2751 2752 if (rc) { 2753 pf->vf_configs[vf].trusted = !enable; 2754 } else { 2755 netdev_info(pf->netdev, "VF %d is %strusted\n", 2756 vf, enable ? "" : "not "); 2757 otx2_set_rx_mode(netdev); 2758 } 2759 2760 return rc; 2761 } 2762 2763 static const struct net_device_ops otx2_netdev_ops = { 2764 .ndo_open = otx2_open, 2765 .ndo_stop = otx2_stop, 2766 .ndo_start_xmit = otx2_xmit, 2767 .ndo_select_queue = otx2_select_queue, 2768 .ndo_fix_features = otx2_fix_features, 2769 .ndo_set_mac_address = otx2_set_mac_address, 2770 .ndo_change_mtu = otx2_change_mtu, 2771 .ndo_set_rx_mode = otx2_set_rx_mode, 2772 .ndo_set_features = otx2_set_features, 2773 .ndo_tx_timeout = otx2_tx_timeout, 2774 .ndo_get_stats64 = otx2_get_stats64, 2775 .ndo_eth_ioctl = otx2_ioctl, 2776 .ndo_set_vf_mac = otx2_set_vf_mac, 2777 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2778 .ndo_get_vf_config = otx2_get_vf_config, 2779 .ndo_bpf = otx2_xdp, 2780 .ndo_xdp_xmit = otx2_xdp_xmit, 2781 .ndo_setup_tc = otx2_setup_tc, 2782 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2783 }; 2784 2785 static int otx2_wq_init(struct otx2_nic *pf) 2786 { 2787 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2788 if (!pf->otx2_wq) 2789 return -ENOMEM; 2790 2791 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2792 INIT_WORK(&pf->reset_task, otx2_reset_task); 2793 return 0; 2794 } 2795 2796 static int otx2_check_pf_usable(struct otx2_nic *nic) 2797 { 2798 u64 rev; 2799 2800 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2801 rev = (rev >> 12) & 0xFF; 2802 /* Check if AF has setup revision for RVUM block, 2803 * otherwise this driver probe should be deferred 2804 * until AF driver comes up. 2805 */ 2806 if (!rev) { 2807 dev_warn(nic->dev, 2808 "AF is not initialized, deferring probe\n"); 2809 return -EPROBE_DEFER; 2810 } 2811 return 0; 2812 } 2813 2814 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2815 { 2816 struct otx2_hw *hw = &pf->hw; 2817 int num_vec, err; 2818 2819 /* NPA interrupts are inot registered, so alloc only 2820 * upto NIX vector offset. 2821 */ 2822 num_vec = hw->nix_msixoff; 2823 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2824 2825 otx2_disable_mbox_intr(pf); 2826 pci_free_irq_vectors(hw->pdev); 2827 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2828 if (err < 0) { 2829 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2830 __func__, num_vec); 2831 return err; 2832 } 2833 2834 return otx2_register_mbox_intr(pf, false); 2835 } 2836 2837 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2838 { 2839 int i; 2840 2841 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2842 sizeof(struct otx2_vf_config), 2843 GFP_KERNEL); 2844 if (!pf->vf_configs) 2845 return -ENOMEM; 2846 2847 for (i = 0; i < pf->total_vfs; i++) { 2848 pf->vf_configs[i].pf = pf; 2849 pf->vf_configs[i].intf_down = true; 2850 pf->vf_configs[i].trusted = false; 2851 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2852 otx2_vf_link_event_task); 2853 } 2854 2855 return 0; 2856 } 2857 2858 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2859 { 2860 int i; 2861 2862 if (!pf->vf_configs) 2863 return; 2864 2865 for (i = 0; i < pf->total_vfs; i++) { 2866 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2867 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2868 } 2869 } 2870 2871 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2872 { 2873 struct device *dev = &pdev->dev; 2874 int err, qcount, qos_txqs; 2875 struct net_device *netdev; 2876 struct otx2_nic *pf; 2877 struct otx2_hw *hw; 2878 int num_vec; 2879 2880 err = pcim_enable_device(pdev); 2881 if (err) { 2882 dev_err(dev, "Failed to enable PCI device\n"); 2883 return err; 2884 } 2885 2886 err = pci_request_regions(pdev, DRV_NAME); 2887 if (err) { 2888 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2889 return err; 2890 } 2891 2892 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2893 if (err) { 2894 dev_err(dev, "DMA mask config failed, abort\n"); 2895 goto err_release_regions; 2896 } 2897 2898 pci_set_master(pdev); 2899 2900 /* Set number of queues */ 2901 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2902 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 2903 2904 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 2905 if (!netdev) { 2906 err = -ENOMEM; 2907 goto err_release_regions; 2908 } 2909 2910 pci_set_drvdata(pdev, netdev); 2911 SET_NETDEV_DEV(netdev, &pdev->dev); 2912 pf = netdev_priv(netdev); 2913 pf->netdev = netdev; 2914 pf->pdev = pdev; 2915 pf->dev = dev; 2916 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2917 pf->flags |= OTX2_FLAG_INTF_DOWN; 2918 2919 hw = &pf->hw; 2920 hw->pdev = pdev; 2921 hw->rx_queues = qcount; 2922 hw->tx_queues = qcount; 2923 hw->non_qos_queues = qcount; 2924 hw->max_queues = qcount; 2925 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2926 /* Use CQE of 128 byte descriptor size by default */ 2927 hw->xqe_size = 128; 2928 2929 num_vec = pci_msix_vec_count(pdev); 2930 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2931 GFP_KERNEL); 2932 if (!hw->irq_name) { 2933 err = -ENOMEM; 2934 goto err_free_netdev; 2935 } 2936 2937 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2938 sizeof(cpumask_var_t), GFP_KERNEL); 2939 if (!hw->affinity_mask) { 2940 err = -ENOMEM; 2941 goto err_free_netdev; 2942 } 2943 2944 /* Map CSRs */ 2945 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2946 if (!pf->reg_base) { 2947 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2948 err = -ENOMEM; 2949 goto err_free_netdev; 2950 } 2951 2952 err = otx2_check_pf_usable(pf); 2953 if (err) 2954 goto err_free_netdev; 2955 2956 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2957 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2958 if (err < 0) { 2959 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2960 __func__, num_vec); 2961 goto err_free_netdev; 2962 } 2963 2964 otx2_setup_dev_hw_settings(pf); 2965 2966 /* Init PF <=> AF mailbox stuff */ 2967 err = otx2_pfaf_mbox_init(pf); 2968 if (err) 2969 goto err_free_irq_vectors; 2970 2971 /* Register mailbox interrupt */ 2972 err = otx2_register_mbox_intr(pf, true); 2973 if (err) 2974 goto err_mbox_destroy; 2975 2976 /* Request AF to attach NPA and NIX LFs to this PF. 2977 * NIX and NPA LFs are needed for this PF to function as a NIC. 2978 */ 2979 err = otx2_attach_npa_nix(pf); 2980 if (err) 2981 goto err_disable_mbox_intr; 2982 2983 err = otx2_realloc_msix_vectors(pf); 2984 if (err) 2985 goto err_detach_rsrc; 2986 2987 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2988 if (err) 2989 goto err_detach_rsrc; 2990 2991 err = cn10k_lmtst_init(pf); 2992 if (err) 2993 goto err_detach_rsrc; 2994 2995 /* Assign default mac address */ 2996 otx2_get_mac_from_af(netdev); 2997 2998 /* Don't check for error. Proceed without ptp */ 2999 otx2_ptp_init(pf); 3000 3001 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 3002 * HW allocates buffer pointer from stack and uses it for DMA'ing 3003 * ingress packet. In some scenarios HW can free back allocated buffer 3004 * pointers to pool. This makes it impossible for SW to maintain a 3005 * parallel list where physical addresses of buffer pointers (IOVAs) 3006 * given to HW can be saved for later reference. 3007 * 3008 * So the only way to convert Rx packet's buffer address is to use 3009 * IOMMU's iova_to_phys() handler which translates the address by 3010 * walking through the translation tables. 3011 */ 3012 pf->iommu_domain = iommu_get_domain_for_dev(dev); 3013 3014 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 3015 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 3016 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 3017 NETIF_F_GSO_UDP_L4); 3018 netdev->features |= netdev->hw_features; 3019 3020 err = otx2_mcam_flow_init(pf); 3021 if (err) 3022 goto err_ptp_destroy; 3023 3024 err = cn10k_mcs_init(pf); 3025 if (err) 3026 goto err_del_mcam_entries; 3027 3028 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 3029 netdev->hw_features |= NETIF_F_NTUPLE; 3030 3031 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 3032 netdev->priv_flags |= IFF_UNICAST_FLT; 3033 3034 /* Support TSO on tag interface */ 3035 netdev->vlan_features |= netdev->features; 3036 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3037 NETIF_F_HW_VLAN_STAG_TX; 3038 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 3039 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 3040 NETIF_F_HW_VLAN_STAG_RX; 3041 netdev->features |= netdev->hw_features; 3042 3043 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 3044 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 3045 netdev->hw_features |= NETIF_F_HW_TC; 3046 3047 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 3048 3049 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 3050 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 3051 3052 netdev->netdev_ops = &otx2_netdev_ops; 3053 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 3054 3055 netdev->min_mtu = OTX2_MIN_MTU; 3056 netdev->max_mtu = otx2_get_max_mtu(pf); 3057 3058 /* reset CGX/RPM MAC stats */ 3059 otx2_reset_mac_stats(pf); 3060 3061 err = register_netdev(netdev); 3062 if (err) { 3063 dev_err(dev, "Failed to register netdevice\n"); 3064 goto err_mcs_free; 3065 } 3066 3067 err = otx2_wq_init(pf); 3068 if (err) 3069 goto err_unreg_netdev; 3070 3071 otx2_set_ethtool_ops(netdev); 3072 3073 err = otx2_init_tc(pf); 3074 if (err) 3075 goto err_mcam_flow_del; 3076 3077 err = otx2_register_dl(pf); 3078 if (err) 3079 goto err_mcam_flow_del; 3080 3081 /* Initialize SR-IOV resources */ 3082 err = otx2_sriov_vfcfg_init(pf); 3083 if (err) 3084 goto err_pf_sriov_init; 3085 3086 /* Enable link notifications */ 3087 otx2_cgx_config_linkevents(pf, true); 3088 3089 #ifdef CONFIG_DCB 3090 err = otx2_dcbnl_set_ops(netdev); 3091 if (err) 3092 goto err_pf_sriov_init; 3093 #endif 3094 3095 otx2_qos_init(pf, qos_txqs); 3096 3097 return 0; 3098 3099 err_pf_sriov_init: 3100 otx2_shutdown_tc(pf); 3101 err_mcam_flow_del: 3102 otx2_mcam_flow_del(pf); 3103 err_unreg_netdev: 3104 unregister_netdev(netdev); 3105 err_mcs_free: 3106 cn10k_mcs_free(pf); 3107 err_del_mcam_entries: 3108 otx2_mcam_flow_del(pf); 3109 err_ptp_destroy: 3110 otx2_ptp_destroy(pf); 3111 err_detach_rsrc: 3112 if (pf->hw.lmt_info) 3113 free_percpu(pf->hw.lmt_info); 3114 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3115 qmem_free(pf->dev, pf->dync_lmt); 3116 otx2_detach_resources(&pf->mbox); 3117 err_disable_mbox_intr: 3118 otx2_disable_mbox_intr(pf); 3119 err_mbox_destroy: 3120 otx2_pfaf_mbox_destroy(pf); 3121 err_free_irq_vectors: 3122 pci_free_irq_vectors(hw->pdev); 3123 err_free_netdev: 3124 pci_set_drvdata(pdev, NULL); 3125 free_netdev(netdev); 3126 err_release_regions: 3127 pci_release_regions(pdev); 3128 return err; 3129 } 3130 3131 static void otx2_vf_link_event_task(struct work_struct *work) 3132 { 3133 struct otx2_vf_config *config; 3134 struct cgx_link_info_msg *req; 3135 struct mbox_msghdr *msghdr; 3136 struct delayed_work *dwork; 3137 struct otx2_nic *pf; 3138 int vf_idx; 3139 3140 config = container_of(work, struct otx2_vf_config, 3141 link_event_work.work); 3142 vf_idx = config - config->pf->vf_configs; 3143 pf = config->pf; 3144 3145 if (config->intf_down) 3146 return; 3147 3148 mutex_lock(&pf->mbox.lock); 3149 3150 dwork = &config->link_event_work; 3151 3152 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) { 3153 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 3154 mutex_unlock(&pf->mbox.lock); 3155 return; 3156 } 3157 3158 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3159 sizeof(*req), sizeof(struct msg_rsp)); 3160 if (!msghdr) { 3161 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3162 mutex_unlock(&pf->mbox.lock); 3163 return; 3164 } 3165 3166 req = (struct cgx_link_info_msg *)msghdr; 3167 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3168 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3169 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3170 3171 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx); 3172 3173 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3174 3175 mutex_unlock(&pf->mbox.lock); 3176 } 3177 3178 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3179 { 3180 struct net_device *netdev = pci_get_drvdata(pdev); 3181 struct otx2_nic *pf = netdev_priv(netdev); 3182 int ret; 3183 3184 /* Init PF <=> VF mailbox stuff */ 3185 ret = otx2_pfvf_mbox_init(pf, numvfs); 3186 if (ret) 3187 return ret; 3188 3189 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3190 if (ret) 3191 goto free_mbox; 3192 3193 ret = otx2_pf_flr_init(pf, numvfs); 3194 if (ret) 3195 goto free_intr; 3196 3197 ret = otx2_register_flr_me_intr(pf, numvfs); 3198 if (ret) 3199 goto free_flr; 3200 3201 ret = pci_enable_sriov(pdev, numvfs); 3202 if (ret) 3203 goto free_flr_intr; 3204 3205 return numvfs; 3206 free_flr_intr: 3207 otx2_disable_flr_me_intr(pf); 3208 free_flr: 3209 otx2_flr_wq_destroy(pf); 3210 free_intr: 3211 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3212 free_mbox: 3213 otx2_pfvf_mbox_destroy(pf); 3214 return ret; 3215 } 3216 3217 static int otx2_sriov_disable(struct pci_dev *pdev) 3218 { 3219 struct net_device *netdev = pci_get_drvdata(pdev); 3220 struct otx2_nic *pf = netdev_priv(netdev); 3221 int numvfs = pci_num_vf(pdev); 3222 3223 if (!numvfs) 3224 return 0; 3225 3226 pci_disable_sriov(pdev); 3227 3228 otx2_disable_flr_me_intr(pf); 3229 otx2_flr_wq_destroy(pf); 3230 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3231 otx2_pfvf_mbox_destroy(pf); 3232 3233 return 0; 3234 } 3235 3236 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3237 { 3238 if (numvfs == 0) 3239 return otx2_sriov_disable(pdev); 3240 else 3241 return otx2_sriov_enable(pdev, numvfs); 3242 } 3243 3244 static void otx2_remove(struct pci_dev *pdev) 3245 { 3246 struct net_device *netdev = pci_get_drvdata(pdev); 3247 struct otx2_nic *pf; 3248 3249 if (!netdev) 3250 return; 3251 3252 pf = netdev_priv(netdev); 3253 3254 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3255 3256 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3257 otx2_config_hw_tx_tstamp(pf, false); 3258 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3259 otx2_config_hw_rx_tstamp(pf, false); 3260 3261 /* Disable 802.3x pause frames */ 3262 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3263 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3264 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3265 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3266 otx2_config_pause_frm(pf); 3267 } 3268 3269 #ifdef CONFIG_DCB 3270 /* Disable PFC config */ 3271 if (pf->pfc_en) { 3272 pf->pfc_en = 0; 3273 otx2_config_priority_flow_ctrl(pf); 3274 } 3275 #endif 3276 cancel_work_sync(&pf->reset_task); 3277 /* Disable link notifications */ 3278 otx2_cgx_config_linkevents(pf, false); 3279 3280 otx2_unregister_dl(pf); 3281 unregister_netdev(netdev); 3282 cn10k_mcs_free(pf); 3283 otx2_sriov_disable(pf->pdev); 3284 otx2_sriov_vfcfg_cleanup(pf); 3285 if (pf->otx2_wq) 3286 destroy_workqueue(pf->otx2_wq); 3287 3288 otx2_ptp_destroy(pf); 3289 otx2_mcam_flow_del(pf); 3290 otx2_shutdown_tc(pf); 3291 otx2_shutdown_qos(pf); 3292 otx2_detach_resources(&pf->mbox); 3293 if (pf->hw.lmt_info) 3294 free_percpu(pf->hw.lmt_info); 3295 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3296 qmem_free(pf->dev, pf->dync_lmt); 3297 otx2_disable_mbox_intr(pf); 3298 otx2_pfaf_mbox_destroy(pf); 3299 pci_free_irq_vectors(pf->pdev); 3300 pci_set_drvdata(pdev, NULL); 3301 free_netdev(netdev); 3302 3303 pci_release_regions(pdev); 3304 } 3305 3306 static struct pci_driver otx2_pf_driver = { 3307 .name = DRV_NAME, 3308 .id_table = otx2_pf_id_table, 3309 .probe = otx2_probe, 3310 .shutdown = otx2_remove, 3311 .remove = otx2_remove, 3312 .sriov_configure = otx2_sriov_configure 3313 }; 3314 3315 static int __init otx2_rvupf_init_module(void) 3316 { 3317 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3318 3319 return pci_register_driver(&otx2_pf_driver); 3320 } 3321 3322 static void __exit otx2_rvupf_cleanup_module(void) 3323 { 3324 pci_unregister_driver(&otx2_pf_driver); 3325 } 3326 3327 module_init(otx2_rvupf_init_module); 3328 module_exit(otx2_rvupf_cleanup_module); 3329