1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include "cn10k.h" 26 #include <rvu_trace.h> 27 28 #define DRV_NAME "rvu_nicpf" 29 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 30 31 /* Supported devices */ 32 static const struct pci_device_id otx2_pf_id_table[] = { 33 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 34 { 0, } /* end of table */ 35 }; 36 37 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 38 MODULE_DESCRIPTION(DRV_STRING); 39 MODULE_LICENSE("GPL v2"); 40 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 41 42 static void otx2_vf_link_event_task(struct work_struct *work); 43 44 enum { 45 TYPE_PFAF, 46 TYPE_PFVF, 47 }; 48 49 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 50 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 51 52 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 53 { 54 struct otx2_nic *pf = netdev_priv(netdev); 55 bool if_up = netif_running(netdev); 56 int err = 0; 57 58 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 59 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 60 netdev->mtu); 61 return -EINVAL; 62 } 63 if (if_up) 64 otx2_stop(netdev); 65 66 netdev_info(netdev, "Changing MTU from %d to %d\n", 67 netdev->mtu, new_mtu); 68 netdev->mtu = new_mtu; 69 70 if (if_up) 71 err = otx2_open(netdev); 72 73 return err; 74 } 75 76 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 77 { 78 int irq, vfs = pf->total_vfs; 79 80 /* Disable VFs ME interrupts */ 81 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 82 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 83 free_irq(irq, pf); 84 85 /* Disable VFs FLR interrupts */ 86 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 87 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 88 free_irq(irq, pf); 89 90 if (vfs <= 64) 91 return; 92 93 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 94 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 95 free_irq(irq, pf); 96 97 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 98 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 99 free_irq(irq, pf); 100 } 101 102 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 103 { 104 if (!pf->flr_wq) 105 return; 106 destroy_workqueue(pf->flr_wq); 107 pf->flr_wq = NULL; 108 devm_kfree(pf->dev, pf->flr_wrk); 109 } 110 111 static void otx2_flr_handler(struct work_struct *work) 112 { 113 struct flr_work *flrwork = container_of(work, struct flr_work, work); 114 struct otx2_nic *pf = flrwork->pf; 115 struct mbox *mbox = &pf->mbox; 116 struct msg_req *req; 117 int vf, reg = 0; 118 119 vf = flrwork - pf->flr_wrk; 120 121 mutex_lock(&mbox->lock); 122 req = otx2_mbox_alloc_msg_vf_flr(mbox); 123 if (!req) { 124 mutex_unlock(&mbox->lock); 125 return; 126 } 127 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 128 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 129 130 if (!otx2_sync_mbox_msg(&pf->mbox)) { 131 if (vf >= 64) { 132 reg = 1; 133 vf = vf - 64; 134 } 135 /* clear transcation pending bit */ 136 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 137 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 138 } 139 140 mutex_unlock(&mbox->lock); 141 } 142 143 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 144 { 145 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 146 int reg, dev, vf, start_vf, num_reg = 1; 147 u64 intr; 148 149 if (pf->total_vfs > 64) 150 num_reg = 2; 151 152 for (reg = 0; reg < num_reg; reg++) { 153 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 154 if (!intr) 155 continue; 156 start_vf = 64 * reg; 157 for (vf = 0; vf < 64; vf++) { 158 if (!(intr & BIT_ULL(vf))) 159 continue; 160 dev = vf + start_vf; 161 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 162 /* Clear interrupt */ 163 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 164 /* Disable the interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 166 BIT_ULL(vf)); 167 } 168 } 169 return IRQ_HANDLED; 170 } 171 172 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 173 { 174 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 175 int vf, reg, num_reg = 1; 176 u64 intr; 177 178 if (pf->total_vfs > 64) 179 num_reg = 2; 180 181 for (reg = 0; reg < num_reg; reg++) { 182 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 183 if (!intr) 184 continue; 185 for (vf = 0; vf < 64; vf++) { 186 if (!(intr & BIT_ULL(vf))) 187 continue; 188 /* clear trpend bit */ 189 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 190 /* clear interrupt */ 191 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 192 } 193 } 194 return IRQ_HANDLED; 195 } 196 197 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 198 { 199 struct otx2_hw *hw = &pf->hw; 200 char *irq_name; 201 int ret; 202 203 /* Register ME interrupt handler*/ 204 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 205 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 206 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 207 otx2_pf_me_intr_handler, 0, irq_name, pf); 208 if (ret) { 209 dev_err(pf->dev, 210 "RVUPF: IRQ registration failed for ME0\n"); 211 } 212 213 /* Register FLR interrupt handler */ 214 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 215 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 216 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 217 otx2_pf_flr_intr_handler, 0, irq_name, pf); 218 if (ret) { 219 dev_err(pf->dev, 220 "RVUPF: IRQ registration failed for FLR0\n"); 221 return ret; 222 } 223 224 if (numvfs > 64) { 225 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 226 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 227 rvu_get_pf(pf->pcifunc)); 228 ret = request_irq(pci_irq_vector 229 (pf->pdev, RVU_PF_INT_VEC_VFME1), 230 otx2_pf_me_intr_handler, 0, irq_name, pf); 231 if (ret) { 232 dev_err(pf->dev, 233 "RVUPF: IRQ registration failed for ME1\n"); 234 } 235 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 236 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 237 rvu_get_pf(pf->pcifunc)); 238 ret = request_irq(pci_irq_vector 239 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 240 otx2_pf_flr_intr_handler, 0, irq_name, pf); 241 if (ret) { 242 dev_err(pf->dev, 243 "RVUPF: IRQ registration failed for FLR1\n"); 244 return ret; 245 } 246 } 247 248 /* Enable ME interrupt for all VFs*/ 249 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 250 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 251 252 /* Enable FLR interrupt for all VFs*/ 253 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 254 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 255 256 if (numvfs > 64) { 257 numvfs -= 64; 258 259 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 260 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 261 INTR_MASK(numvfs)); 262 263 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 264 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 265 INTR_MASK(numvfs)); 266 } 267 return 0; 268 } 269 270 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 271 { 272 int vf; 273 274 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 /* Error code -EIO indicate there is a communication failure 398 * to the AF. Rest of the error codes indicate that AF processed 399 * VF messages and set the error codes in response messages 400 * (if any) so simply forward responses to VF. 401 */ 402 if (err == -EIO) { 403 dev_warn(pf->dev, 404 "AF not responding to VF%d messages\n", vf); 405 /* restore PF mbase and exit */ 406 dst_mdev->mbase = pf->mbox.bbuf_base; 407 mutex_unlock(&pf->mbox.lock); 408 return err; 409 } 410 /* At this point, all the VF messages sent to AF are acked 411 * with proper responses and responses are copied to VF 412 * mailbox hence raise interrupt to VF. 413 */ 414 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 415 dst_mbox->mbox.rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 419 pf->mbox.bbuf_base, vf); 420 mutex_unlock(&pf->mbox.lock); 421 } else if (dir == MBOX_DIR_PFVF_UP) { 422 src_mdev = &src_mbox->dev[0]; 423 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 424 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 425 src_mbox->rx_start); 426 req_hdr->num_msgs = num_msgs; 427 428 dst_mbox = &pf->mbox_pfvf[0]; 429 dst_size = dst_mbox->mbox_up.tx_size - 430 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 431 /* Check if msgs fit into destination area */ 432 if (mbox_hdr->msg_size > dst_size) 433 return -EINVAL; 434 435 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 436 dst_mdev->mbase = src_mdev->mbase; 437 dst_mdev->msg_size = mbox_hdr->msg_size; 438 dst_mdev->num_msgs = mbox_hdr->num_msgs; 439 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 440 if (err) { 441 dev_warn(pf->dev, 442 "VF%d is not responding to mailbox\n", vf); 443 return err; 444 } 445 } else if (dir == MBOX_DIR_VFPF_UP) { 446 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 447 src_mbox->rx_start); 448 req_hdr->num_msgs = num_msgs; 449 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 450 &pf->mbox.mbox_up, 451 pf->mbox_pfvf[vf].bbuf_base, 452 0); 453 } 454 455 return 0; 456 } 457 458 static void otx2_pfvf_mbox_handler(struct work_struct *work) 459 { 460 struct mbox_msghdr *msg = NULL; 461 int offset, vf_idx, id, err; 462 struct otx2_mbox_dev *mdev; 463 struct mbox_hdr *req_hdr; 464 struct otx2_mbox *mbox; 465 struct mbox *vf_mbox; 466 struct otx2_nic *pf; 467 468 vf_mbox = container_of(work, struct mbox, mbox_wrk); 469 pf = vf_mbox->pfvf; 470 vf_idx = vf_mbox - pf->mbox_pfvf; 471 472 mbox = &pf->mbox_pfvf[0].mbox; 473 mdev = &mbox->dev[vf_idx]; 474 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 475 476 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 477 478 for (id = 0; id < vf_mbox->num_msgs; id++) { 479 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 480 offset); 481 482 if (msg->sig != OTX2_MBOX_REQ_SIG) 483 goto inval_msg; 484 485 /* Set VF's number in each of the msg */ 486 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 487 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 488 offset = msg->next_msgoff; 489 } 490 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 491 vf_mbox->num_msgs); 492 if (err) 493 goto inval_msg; 494 return; 495 496 inval_msg: 497 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 498 otx2_mbox_msg_send(mbox, vf_idx); 499 } 500 501 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 502 { 503 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 504 struct otx2_nic *pf = vf_mbox->pfvf; 505 struct otx2_mbox_dev *mdev; 506 int offset, id, vf_idx = 0; 507 struct mbox_hdr *rsp_hdr; 508 struct mbox_msghdr *msg; 509 struct otx2_mbox *mbox; 510 511 vf_idx = vf_mbox - pf->mbox_pfvf; 512 mbox = &pf->mbox_pfvf[0].mbox_up; 513 mdev = &mbox->dev[vf_idx]; 514 515 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 516 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 517 518 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 519 msg = mdev->mbase + offset; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(pf->dev, 523 "Mbox msg with unknown ID 0x%x\n", msg->id); 524 goto end; 525 } 526 527 if (msg->sig != OTX2_MBOX_RSP_SIG) { 528 dev_err(pf->dev, 529 "Mbox msg with wrong signature %x, ID 0x%x\n", 530 msg->sig, msg->id); 531 goto end; 532 } 533 534 switch (msg->id) { 535 case MBOX_MSG_CGX_LINK_EVENT: 536 break; 537 default: 538 if (msg->rc) 539 dev_err(pf->dev, 540 "Mbox msg response has err %d, ID 0x%x\n", 541 msg->rc, msg->id); 542 break; 543 } 544 545 end: 546 offset = mbox->rx_start + msg->next_msgoff; 547 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 548 __otx2_mbox_reset(mbox, 0); 549 mdev->msgs_acked++; 550 } 551 } 552 553 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 554 { 555 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 556 int vfs = pf->total_vfs; 557 struct mbox *mbox; 558 u64 intr; 559 560 mbox = pf->mbox_pfvf; 561 /* Handle VF interrupts */ 562 if (vfs > 64) { 563 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 564 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 566 TYPE_PFVF); 567 vfs -= 64; 568 } 569 570 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 571 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 572 573 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 574 575 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 576 577 return IRQ_HANDLED; 578 } 579 580 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 581 { 582 void __iomem *hwbase; 583 struct mbox *mbox; 584 int err, vf; 585 u64 base; 586 587 if (!numvfs) 588 return -EINVAL; 589 590 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 591 sizeof(struct mbox), GFP_KERNEL); 592 if (!pf->mbox_pfvf) 593 return -ENOMEM; 594 595 pf->mbox_pfvf_wq = alloc_ordered_workqueue("otx2_pfvf_mailbox", 596 WQ_HIGHPRI | WQ_MEM_RECLAIM); 597 if (!pf->mbox_pfvf_wq) 598 return -ENOMEM; 599 600 /* On CN10K platform, PF <-> VF mailbox region follows after 601 * PF <-> AF mailbox region. 602 */ 603 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 604 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 605 MBOX_SIZE; 606 else 607 base = readq((void __iomem *)((u64)pf->reg_base + 608 RVU_PF_VF_BAR4_ADDR)); 609 610 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 611 if (!hwbase) { 612 err = -ENOMEM; 613 goto free_wq; 614 } 615 616 mbox = &pf->mbox_pfvf[0]; 617 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 618 MBOX_DIR_PFVF, numvfs); 619 if (err) 620 goto free_iomem; 621 622 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 623 MBOX_DIR_PFVF_UP, numvfs); 624 if (err) 625 goto free_iomem; 626 627 for (vf = 0; vf < numvfs; vf++) { 628 mbox->pfvf = pf; 629 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 630 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 631 mbox++; 632 } 633 634 return 0; 635 636 free_iomem: 637 if (hwbase) 638 iounmap(hwbase); 639 free_wq: 640 destroy_workqueue(pf->mbox_pfvf_wq); 641 return err; 642 } 643 644 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 645 { 646 struct mbox *mbox = &pf->mbox_pfvf[0]; 647 648 if (!mbox) 649 return; 650 651 if (pf->mbox_pfvf_wq) { 652 destroy_workqueue(pf->mbox_pfvf_wq); 653 pf->mbox_pfvf_wq = NULL; 654 } 655 656 if (mbox->mbox.hwbase) 657 iounmap(mbox->mbox.hwbase); 658 659 otx2_mbox_destroy(&mbox->mbox); 660 } 661 662 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 663 { 664 /* Clear PF <=> VF mailbox IRQ */ 665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 667 668 /* Enable PF <=> VF mailbox IRQ */ 669 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 670 if (numvfs > 64) { 671 numvfs -= 64; 672 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 673 INTR_MASK(numvfs)); 674 } 675 } 676 677 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 678 { 679 int vector; 680 681 /* Disable PF <=> VF mailbox IRQ */ 682 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 684 685 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 686 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 687 free_irq(vector, pf); 688 689 if (numvfs > 64) { 690 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 691 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 692 free_irq(vector, pf); 693 } 694 } 695 696 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 697 { 698 struct otx2_hw *hw = &pf->hw; 699 char *irq_name; 700 int err; 701 702 /* Register MBOX0 interrupt handler */ 703 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 704 if (pf->pcifunc) 705 snprintf(irq_name, NAME_SIZE, 706 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 707 else 708 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 709 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 710 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 711 if (err) { 712 dev_err(pf->dev, 713 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 714 return err; 715 } 716 717 if (numvfs > 64) { 718 /* Register MBOX1 interrupt handler */ 719 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 720 if (pf->pcifunc) 721 snprintf(irq_name, NAME_SIZE, 722 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 723 else 724 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 725 err = request_irq(pci_irq_vector(pf->pdev, 726 RVU_PF_INT_VEC_VFPF_MBOX1), 727 otx2_pfvf_mbox_intr_handler, 728 0, irq_name, pf); 729 if (err) { 730 dev_err(pf->dev, 731 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 732 return err; 733 } 734 } 735 736 otx2_enable_pfvf_mbox_intr(pf, numvfs); 737 738 return 0; 739 } 740 741 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 742 struct mbox_msghdr *msg) 743 { 744 int devid; 745 746 if (msg->id >= MBOX_MSG_MAX) { 747 dev_err(pf->dev, 748 "Mbox msg with unknown ID 0x%x\n", msg->id); 749 return; 750 } 751 752 if (msg->sig != OTX2_MBOX_RSP_SIG) { 753 dev_err(pf->dev, 754 "Mbox msg with wrong signature %x, ID 0x%x\n", 755 msg->sig, msg->id); 756 return; 757 } 758 759 /* message response heading VF */ 760 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 761 if (devid) { 762 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 763 struct delayed_work *dwork; 764 765 switch (msg->id) { 766 case MBOX_MSG_NIX_LF_START_RX: 767 config->intf_down = false; 768 dwork = &config->link_event_work; 769 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 770 break; 771 case MBOX_MSG_NIX_LF_STOP_RX: 772 config->intf_down = true; 773 break; 774 } 775 776 return; 777 } 778 779 switch (msg->id) { 780 case MBOX_MSG_READY: 781 pf->pcifunc = msg->pcifunc; 782 break; 783 case MBOX_MSG_MSIX_OFFSET: 784 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 785 break; 786 case MBOX_MSG_NPA_LF_ALLOC: 787 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 788 break; 789 case MBOX_MSG_NIX_LF_ALLOC: 790 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 791 break; 792 case MBOX_MSG_NIX_TXSCH_ALLOC: 793 mbox_handler_nix_txsch_alloc(pf, 794 (struct nix_txsch_alloc_rsp *)msg); 795 break; 796 case MBOX_MSG_NIX_BP_ENABLE: 797 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 798 break; 799 case MBOX_MSG_CGX_STATS: 800 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 801 break; 802 case MBOX_MSG_CGX_FEC_STATS: 803 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 804 break; 805 default: 806 if (msg->rc) 807 dev_err(pf->dev, 808 "Mbox msg response has err %d, ID 0x%x\n", 809 msg->rc, msg->id); 810 break; 811 } 812 } 813 814 static void otx2_pfaf_mbox_handler(struct work_struct *work) 815 { 816 struct otx2_mbox_dev *mdev; 817 struct mbox_hdr *rsp_hdr; 818 struct mbox_msghdr *msg; 819 struct otx2_mbox *mbox; 820 struct mbox *af_mbox; 821 struct otx2_nic *pf; 822 int offset, id; 823 824 af_mbox = container_of(work, struct mbox, mbox_wrk); 825 mbox = &af_mbox->mbox; 826 mdev = &mbox->dev[0]; 827 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 828 829 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 830 pf = af_mbox->pfvf; 831 832 for (id = 0; id < af_mbox->num_msgs; id++) { 833 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 834 otx2_process_pfaf_mbox_msg(pf, msg); 835 offset = mbox->rx_start + msg->next_msgoff; 836 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 837 __otx2_mbox_reset(mbox, 0); 838 mdev->msgs_acked++; 839 } 840 841 } 842 843 static void otx2_handle_link_event(struct otx2_nic *pf) 844 { 845 struct cgx_link_user_info *linfo = &pf->linfo; 846 struct net_device *netdev = pf->netdev; 847 848 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 849 linfo->link_up ? "UP" : "DOWN", linfo->speed, 850 linfo->full_duplex ? "Full" : "Half"); 851 if (linfo->link_up) { 852 netif_carrier_on(netdev); 853 netif_tx_start_all_queues(netdev); 854 } else { 855 netif_tx_stop_all_queues(netdev); 856 netif_carrier_off(netdev); 857 } 858 } 859 860 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 861 struct mcs_intr_info *event, 862 struct msg_rsp *rsp) 863 { 864 cn10k_handle_mcs_event(pf, event); 865 866 return 0; 867 } 868 869 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 870 struct cgx_link_info_msg *msg, 871 struct msg_rsp *rsp) 872 { 873 int i; 874 875 /* Copy the link info sent by AF */ 876 pf->linfo = msg->link_info; 877 878 /* notify VFs about link event */ 879 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 880 struct otx2_vf_config *config = &pf->vf_configs[i]; 881 struct delayed_work *dwork = &config->link_event_work; 882 883 if (config->intf_down) 884 continue; 885 886 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 887 } 888 889 /* interface has not been fully configured yet */ 890 if (pf->flags & OTX2_FLAG_INTF_DOWN) 891 return 0; 892 893 otx2_handle_link_event(pf); 894 return 0; 895 } 896 897 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 898 struct mbox_msghdr *req) 899 { 900 /* Check if valid, if not reply with a invalid msg */ 901 if (req->sig != OTX2_MBOX_REQ_SIG) { 902 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 903 return -ENODEV; 904 } 905 906 switch (req->id) { 907 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 908 case _id: { \ 909 struct _rsp_type *rsp; \ 910 int err; \ 911 \ 912 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 913 &pf->mbox.mbox_up, 0, \ 914 sizeof(struct _rsp_type)); \ 915 if (!rsp) \ 916 return -ENOMEM; \ 917 \ 918 rsp->hdr.id = _id; \ 919 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 920 rsp->hdr.pcifunc = 0; \ 921 rsp->hdr.rc = 0; \ 922 \ 923 err = otx2_mbox_up_handler_ ## _fn_name( \ 924 pf, (struct _req_type *)req, rsp); \ 925 return err; \ 926 } 927 MBOX_UP_CGX_MESSAGES 928 MBOX_UP_MCS_MESSAGES 929 #undef M 930 break; 931 default: 932 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 933 return -ENODEV; 934 } 935 return 0; 936 } 937 938 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 939 { 940 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 941 struct otx2_mbox *mbox = &af_mbox->mbox_up; 942 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 943 struct otx2_nic *pf = af_mbox->pfvf; 944 int offset, id, devid = 0; 945 struct mbox_hdr *rsp_hdr; 946 struct mbox_msghdr *msg; 947 948 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 949 950 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 951 952 for (id = 0; id < af_mbox->up_num_msgs; id++) { 953 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 954 955 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 956 /* Skip processing VF's messages */ 957 if (!devid) 958 otx2_process_mbox_msg_up(pf, msg); 959 offset = mbox->rx_start + msg->next_msgoff; 960 } 961 if (devid) { 962 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 963 MBOX_DIR_PFVF_UP, devid - 1, 964 af_mbox->up_num_msgs); 965 return; 966 } 967 968 otx2_mbox_msg_send(mbox, 0); 969 } 970 971 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 972 { 973 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 974 struct mbox *mbox; 975 976 /* Clear the IRQ */ 977 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 978 979 mbox = &pf->mbox; 980 981 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 982 983 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 984 985 return IRQ_HANDLED; 986 } 987 988 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 989 { 990 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 991 992 /* Disable AF => PF mailbox IRQ */ 993 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 994 free_irq(vector, pf); 995 } 996 997 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 998 { 999 struct otx2_hw *hw = &pf->hw; 1000 struct msg_req *req; 1001 char *irq_name; 1002 int err; 1003 1004 /* Register mailbox interrupt handler */ 1005 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1006 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1007 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1008 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1009 if (err) { 1010 dev_err(pf->dev, 1011 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1012 return err; 1013 } 1014 1015 /* Enable mailbox interrupt for msgs coming from AF. 1016 * First clear to avoid spurious interrupts, if any. 1017 */ 1018 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1019 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1020 1021 if (!probe_af) 1022 return 0; 1023 1024 /* Check mailbox communication with AF */ 1025 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1026 if (!req) { 1027 otx2_disable_mbox_intr(pf); 1028 return -ENOMEM; 1029 } 1030 err = otx2_sync_mbox_msg(&pf->mbox); 1031 if (err) { 1032 dev_warn(pf->dev, 1033 "AF not responding to mailbox, deferring probe\n"); 1034 otx2_disable_mbox_intr(pf); 1035 return -EPROBE_DEFER; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1042 { 1043 struct mbox *mbox = &pf->mbox; 1044 1045 if (pf->mbox_wq) { 1046 destroy_workqueue(pf->mbox_wq); 1047 pf->mbox_wq = NULL; 1048 } 1049 1050 if (mbox->mbox.hwbase) 1051 iounmap((void __iomem *)mbox->mbox.hwbase); 1052 1053 otx2_mbox_destroy(&mbox->mbox); 1054 otx2_mbox_destroy(&mbox->mbox_up); 1055 } 1056 1057 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1058 { 1059 struct mbox *mbox = &pf->mbox; 1060 void __iomem *hwbase; 1061 int err; 1062 1063 mbox->pfvf = pf; 1064 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1065 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1066 if (!pf->mbox_wq) 1067 return -ENOMEM; 1068 1069 /* Mailbox is a reserved memory (in RAM) region shared between 1070 * admin function (i.e AF) and this PF, shouldn't be mapped as 1071 * device memory to allow unaligned accesses. 1072 */ 1073 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1074 MBOX_SIZE); 1075 if (!hwbase) { 1076 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1077 err = -ENOMEM; 1078 goto exit; 1079 } 1080 1081 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1082 MBOX_DIR_PFAF, 1); 1083 if (err) 1084 goto exit; 1085 1086 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1087 MBOX_DIR_PFAF_UP, 1); 1088 if (err) 1089 goto exit; 1090 1091 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1092 if (err) 1093 goto exit; 1094 1095 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1096 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1097 mutex_init(&mbox->lock); 1098 1099 return 0; 1100 exit: 1101 otx2_pfaf_mbox_destroy(pf); 1102 return err; 1103 } 1104 1105 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1106 { 1107 struct msg_req *msg; 1108 int err; 1109 1110 mutex_lock(&pf->mbox.lock); 1111 if (enable) 1112 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1113 else 1114 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1115 1116 if (!msg) { 1117 mutex_unlock(&pf->mbox.lock); 1118 return -ENOMEM; 1119 } 1120 1121 err = otx2_sync_mbox_msg(&pf->mbox); 1122 mutex_unlock(&pf->mbox.lock); 1123 return err; 1124 } 1125 1126 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1127 { 1128 struct msg_req *msg; 1129 int err; 1130 1131 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1132 pf->flow_cfg->dmacflt_max_flows)) 1133 netdev_warn(pf->netdev, 1134 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1135 1136 mutex_lock(&pf->mbox.lock); 1137 if (enable) 1138 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1139 else 1140 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1141 1142 if (!msg) { 1143 mutex_unlock(&pf->mbox.lock); 1144 return -ENOMEM; 1145 } 1146 1147 err = otx2_sync_mbox_msg(&pf->mbox); 1148 mutex_unlock(&pf->mbox.lock); 1149 return err; 1150 } 1151 1152 int otx2_set_real_num_queues(struct net_device *netdev, 1153 int tx_queues, int rx_queues) 1154 { 1155 int err; 1156 1157 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1158 if (err) { 1159 netdev_err(netdev, 1160 "Failed to set no of Tx queues: %d\n", tx_queues); 1161 return err; 1162 } 1163 1164 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1165 if (err) 1166 netdev_err(netdev, 1167 "Failed to set no of Rx queues: %d\n", rx_queues); 1168 return err; 1169 } 1170 EXPORT_SYMBOL(otx2_set_real_num_queues); 1171 1172 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1173 "NIX_SQOPERR_OOR", 1174 "NIX_SQOPERR_CTX_FAULT", 1175 "NIX_SQOPERR_CTX_POISON", 1176 "NIX_SQOPERR_DISABLED", 1177 "NIX_SQOPERR_SIZE_ERR", 1178 "NIX_SQOPERR_OFLOW", 1179 "NIX_SQOPERR_SQB_NULL", 1180 "NIX_SQOPERR_SQB_FAULT", 1181 "NIX_SQOPERR_SQE_SZ_ZERO", 1182 }; 1183 1184 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1185 "NIX_MNQERR_SQ_CTX_FAULT", 1186 "NIX_MNQERR_SQ_CTX_POISON", 1187 "NIX_MNQERR_SQB_FAULT", 1188 "NIX_MNQERR_SQB_POISON", 1189 "NIX_MNQERR_TOTAL_ERR", 1190 "NIX_MNQERR_LSO_ERR", 1191 "NIX_MNQERR_CQ_QUERY_ERR", 1192 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1193 "NIX_MNQERR_MAXLEN_ERR", 1194 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1195 }; 1196 1197 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1198 "NIX_SND_STATUS_GOOD", 1199 "NIX_SND_STATUS_SQ_CTX_FAULT", 1200 "NIX_SND_STATUS_SQ_CTX_POISON", 1201 "NIX_SND_STATUS_SQB_FAULT", 1202 "NIX_SND_STATUS_SQB_POISON", 1203 "NIX_SND_STATUS_HDR_ERR", 1204 "NIX_SND_STATUS_EXT_ERR", 1205 "NIX_SND_STATUS_JUMP_FAULT", 1206 "NIX_SND_STATUS_JUMP_POISON", 1207 "NIX_SND_STATUS_CRC_ERR", 1208 "NIX_SND_STATUS_IMM_ERR", 1209 "NIX_SND_STATUS_SG_ERR", 1210 "NIX_SND_STATUS_MEM_ERR", 1211 "NIX_SND_STATUS_INVALID_SUBDC", 1212 "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1213 "NIX_SND_STATUS_DATA_FAULT", 1214 "NIX_SND_STATUS_DATA_POISON", 1215 "NIX_SND_STATUS_NPC_DROP_ACTION", 1216 "NIX_SND_STATUS_LOCK_VIOL", 1217 "NIX_SND_STATUS_NPC_UCAST_CHAN_ERR", 1218 "NIX_SND_STATUS_NPC_MCAST_CHAN_ERR", 1219 "NIX_SND_STATUS_NPC_MCAST_ABORT", 1220 "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1221 "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1222 "NIX_SND_STATUS_SEND_STATS_ERR", 1223 }; 1224 1225 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1226 { 1227 struct otx2_nic *pf = data; 1228 u64 val, *ptr; 1229 u64 qidx = 0; 1230 1231 /* CQ */ 1232 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1233 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1234 val = otx2_atomic64_add((qidx << 44), ptr); 1235 1236 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1237 (val & NIX_CQERRINT_BITS)); 1238 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1239 continue; 1240 1241 if (val & BIT_ULL(42)) { 1242 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1243 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1244 } else { 1245 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1246 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1247 qidx); 1248 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1249 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1250 qidx); 1251 } 1252 1253 schedule_work(&pf->reset_task); 1254 } 1255 1256 /* SQ */ 1257 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1258 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1259 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1260 1261 /* Below debug registers captures first errors corresponding to 1262 * those registers. We don't have to check against SQ qid as 1263 * these are fatal errors. 1264 */ 1265 1266 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1267 val = otx2_atomic64_add((qidx << 44), ptr); 1268 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1269 (val & NIX_SQINT_BITS)); 1270 1271 if (val & BIT_ULL(42)) { 1272 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1273 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1274 goto done; 1275 } 1276 1277 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1278 if (!(sq_op_err_dbg & BIT(44))) 1279 goto chk_mnq_err_dbg; 1280 1281 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1282 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(%llx) err=%s\n", 1283 qidx, sq_op_err_dbg, nix_sqoperr_e_str[sq_op_err_code]); 1284 1285 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1286 1287 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1288 goto chk_mnq_err_dbg; 1289 1290 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1291 * TODO: But we are in irq context. How to call mbox functions which does sleep 1292 */ 1293 1294 chk_mnq_err_dbg: 1295 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1296 if (!(mnq_err_dbg & BIT(44))) 1297 goto chk_snd_err_dbg; 1298 1299 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1300 netdev_err(pf->netdev, "SQ%lld: NIX_LF_MNQ_ERR_DBG(%llx) err=%s\n", 1301 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code]); 1302 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1303 1304 chk_snd_err_dbg: 1305 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1306 if (snd_err_dbg & BIT(44)) { 1307 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1308 netdev_err(pf->netdev, "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s\n", 1309 qidx, snd_err_dbg, nix_snd_status_e_str[snd_err_code]); 1310 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1311 } 1312 1313 done: 1314 /* Print values and reset */ 1315 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1316 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1317 qidx); 1318 1319 schedule_work(&pf->reset_task); 1320 } 1321 1322 return IRQ_HANDLED; 1323 } 1324 1325 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1326 { 1327 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1328 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1329 int qidx = cq_poll->cint_idx; 1330 1331 /* Disable interrupts. 1332 * 1333 * Completion interrupts behave in a level-triggered interrupt 1334 * fashion, and hence have to be cleared only after it is serviced. 1335 */ 1336 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1337 1338 /* Schedule NAPI */ 1339 pf->napi_events++; 1340 napi_schedule_irqoff(&cq_poll->napi); 1341 1342 return IRQ_HANDLED; 1343 } 1344 1345 static void otx2_disable_napi(struct otx2_nic *pf) 1346 { 1347 struct otx2_qset *qset = &pf->qset; 1348 struct otx2_cq_poll *cq_poll; 1349 int qidx; 1350 1351 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1352 cq_poll = &qset->napi[qidx]; 1353 cancel_work_sync(&cq_poll->dim.work); 1354 napi_disable(&cq_poll->napi); 1355 netif_napi_del(&cq_poll->napi); 1356 } 1357 } 1358 1359 static void otx2_free_cq_res(struct otx2_nic *pf) 1360 { 1361 struct otx2_qset *qset = &pf->qset; 1362 struct otx2_cq_queue *cq; 1363 int qidx; 1364 1365 /* Disable CQs */ 1366 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1367 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1368 cq = &qset->cq[qidx]; 1369 qmem_free(pf->dev, cq->cqe); 1370 } 1371 } 1372 1373 static void otx2_free_sq_res(struct otx2_nic *pf) 1374 { 1375 struct otx2_qset *qset = &pf->qset; 1376 struct otx2_snd_queue *sq; 1377 int qidx; 1378 1379 /* Disable SQs */ 1380 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1381 /* Free SQB pointers */ 1382 otx2_sq_free_sqbs(pf); 1383 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1384 sq = &qset->sq[qidx]; 1385 qmem_free(pf->dev, sq->sqe); 1386 qmem_free(pf->dev, sq->tso_hdrs); 1387 kfree(sq->sg); 1388 kfree(sq->sqb_ptrs); 1389 } 1390 } 1391 1392 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1393 { 1394 int frame_size; 1395 int total_size; 1396 int rbuf_size; 1397 1398 if (pf->hw.rbuf_len) 1399 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1400 1401 /* The data transferred by NIX to memory consists of actual packet 1402 * plus additional data which has timestamp and/or EDSA/HIGIG2 1403 * headers if interface is configured in corresponding modes. 1404 * NIX transfers entire data using 6 segments/buffers and writes 1405 * a CQE_RX descriptor with those segment addresses. First segment 1406 * has additional data prepended to packet. Also software omits a 1407 * headroom of 128 bytes in each segment. Hence the total size of 1408 * memory needed to receive a packet with 'mtu' is: 1409 * frame size = mtu + additional data; 1410 * memory = frame_size + headroom * 6; 1411 * each receive buffer size = memory / 6; 1412 */ 1413 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1414 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1415 rbuf_size = total_size / 6; 1416 1417 return ALIGN(rbuf_size, 2048); 1418 } 1419 1420 static int otx2_init_hw_resources(struct otx2_nic *pf) 1421 { 1422 struct nix_lf_free_req *free_req; 1423 struct mbox *mbox = &pf->mbox; 1424 struct otx2_hw *hw = &pf->hw; 1425 struct msg_req *req; 1426 int err = 0, lvl; 1427 1428 /* Set required NPA LF's pool counts 1429 * Auras and Pools are used in a 1:1 mapping, 1430 * so, aura count = pool count. 1431 */ 1432 hw->rqpool_cnt = hw->rx_queues; 1433 hw->sqpool_cnt = hw->tot_tx_queues; 1434 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1435 1436 /* Maximum hardware supported transmit length */ 1437 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1438 1439 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1440 1441 mutex_lock(&mbox->lock); 1442 /* NPA init */ 1443 err = otx2_config_npa(pf); 1444 if (err) 1445 goto exit; 1446 1447 /* NIX init */ 1448 err = otx2_config_nix(pf); 1449 if (err) 1450 goto err_free_npa_lf; 1451 1452 /* Enable backpressure */ 1453 otx2_nix_config_bp(pf, true); 1454 1455 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1456 err = otx2_rq_aura_pool_init(pf); 1457 if (err) { 1458 mutex_unlock(&mbox->lock); 1459 goto err_free_nix_lf; 1460 } 1461 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1462 err = otx2_sq_aura_pool_init(pf); 1463 if (err) { 1464 mutex_unlock(&mbox->lock); 1465 goto err_free_rq_ptrs; 1466 } 1467 1468 err = otx2_txsch_alloc(pf); 1469 if (err) { 1470 mutex_unlock(&mbox->lock); 1471 goto err_free_sq_ptrs; 1472 } 1473 1474 #ifdef CONFIG_DCB 1475 if (pf->pfc_en) { 1476 err = otx2_pfc_txschq_alloc(pf); 1477 if (err) { 1478 mutex_unlock(&mbox->lock); 1479 goto err_free_sq_ptrs; 1480 } 1481 } 1482 #endif 1483 1484 err = otx2_config_nix_queues(pf); 1485 if (err) { 1486 mutex_unlock(&mbox->lock); 1487 goto err_free_txsch; 1488 } 1489 1490 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1491 err = otx2_txschq_config(pf, lvl, 0, false); 1492 if (err) { 1493 mutex_unlock(&mbox->lock); 1494 goto err_free_nix_queues; 1495 } 1496 } 1497 1498 #ifdef CONFIG_DCB 1499 if (pf->pfc_en) { 1500 err = otx2_pfc_txschq_config(pf); 1501 if (err) { 1502 mutex_unlock(&mbox->lock); 1503 goto err_free_nix_queues; 1504 } 1505 } 1506 #endif 1507 1508 mutex_unlock(&mbox->lock); 1509 return err; 1510 1511 err_free_nix_queues: 1512 otx2_free_sq_res(pf); 1513 otx2_free_cq_res(pf); 1514 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1515 err_free_txsch: 1516 if (otx2_txschq_stop(pf)) 1517 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1518 err_free_sq_ptrs: 1519 otx2_sq_free_sqbs(pf); 1520 err_free_rq_ptrs: 1521 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1522 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1523 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1524 otx2_aura_pool_free(pf); 1525 err_free_nix_lf: 1526 mutex_lock(&mbox->lock); 1527 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1528 if (free_req) { 1529 free_req->flags = NIX_LF_DISABLE_FLOWS; 1530 if (otx2_sync_mbox_msg(mbox)) 1531 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1532 } 1533 err_free_npa_lf: 1534 /* Reset NPA LF */ 1535 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1536 if (req) { 1537 if (otx2_sync_mbox_msg(mbox)) 1538 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1539 } 1540 exit: 1541 mutex_unlock(&mbox->lock); 1542 return err; 1543 } 1544 1545 static void otx2_free_hw_resources(struct otx2_nic *pf) 1546 { 1547 struct otx2_qset *qset = &pf->qset; 1548 struct nix_lf_free_req *free_req; 1549 struct mbox *mbox = &pf->mbox; 1550 struct otx2_cq_queue *cq; 1551 struct msg_req *req; 1552 int qidx, err; 1553 1554 /* Ensure all SQE are processed */ 1555 otx2_sqb_flush(pf); 1556 1557 /* Stop transmission */ 1558 err = otx2_txschq_stop(pf); 1559 if (err) 1560 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1561 1562 #ifdef CONFIG_DCB 1563 if (pf->pfc_en) 1564 otx2_pfc_txschq_stop(pf); 1565 #endif 1566 1567 mutex_lock(&mbox->lock); 1568 /* Disable backpressure */ 1569 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1570 otx2_nix_config_bp(pf, false); 1571 mutex_unlock(&mbox->lock); 1572 1573 /* Disable RQs */ 1574 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1575 1576 /*Dequeue all CQEs */ 1577 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1578 cq = &qset->cq[qidx]; 1579 if (cq->cq_type == CQ_RX) 1580 otx2_cleanup_rx_cqes(pf, cq); 1581 else 1582 otx2_cleanup_tx_cqes(pf, cq); 1583 } 1584 1585 otx2_free_sq_res(pf); 1586 1587 /* Free RQ buffer pointers*/ 1588 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1589 1590 otx2_free_cq_res(pf); 1591 1592 /* Free all ingress bandwidth profiles allocated */ 1593 cn10k_free_all_ipolicers(pf); 1594 1595 mutex_lock(&mbox->lock); 1596 /* Reset NIX LF */ 1597 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1598 if (free_req) { 1599 free_req->flags = NIX_LF_DISABLE_FLOWS; 1600 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1601 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1602 if (otx2_sync_mbox_msg(mbox)) 1603 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1604 } 1605 mutex_unlock(&mbox->lock); 1606 1607 /* Disable NPA Pool and Aura hw context */ 1608 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1609 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1610 otx2_aura_pool_free(pf); 1611 1612 mutex_lock(&mbox->lock); 1613 /* Reset NPA LF */ 1614 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1615 if (req) { 1616 if (otx2_sync_mbox_msg(mbox)) 1617 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1618 } 1619 mutex_unlock(&mbox->lock); 1620 } 1621 1622 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1623 { 1624 struct net_device *netdev = pf->netdev; 1625 struct nix_rx_mode *req; 1626 bool promisc = false; 1627 1628 if (!(netdev->flags & IFF_UP)) 1629 return; 1630 1631 if ((netdev->flags & IFF_PROMISC) || 1632 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1633 promisc = true; 1634 } 1635 1636 /* Write unicast address to mcam entries or del from mcam */ 1637 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1638 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1639 1640 mutex_lock(&pf->mbox.lock); 1641 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1642 if (!req) { 1643 mutex_unlock(&pf->mbox.lock); 1644 return; 1645 } 1646 1647 req->mode = NIX_RX_MODE_UCAST; 1648 1649 if (promisc) 1650 req->mode |= NIX_RX_MODE_PROMISC; 1651 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1652 req->mode |= NIX_RX_MODE_ALLMULTI; 1653 1654 req->mode |= NIX_RX_MODE_USE_MCE; 1655 1656 otx2_sync_mbox_msg(&pf->mbox); 1657 mutex_unlock(&pf->mbox.lock); 1658 } 1659 1660 static void otx2_dim_work(struct work_struct *w) 1661 { 1662 struct dim_cq_moder cur_moder; 1663 struct otx2_cq_poll *cq_poll; 1664 struct otx2_nic *pfvf; 1665 struct dim *dim; 1666 1667 dim = container_of(w, struct dim, work); 1668 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1669 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1670 pfvf = (struct otx2_nic *)cq_poll->dev; 1671 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1672 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1673 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1674 NAPI_POLL_WEIGHT : cur_moder.pkts; 1675 dim->state = DIM_START_MEASURE; 1676 } 1677 1678 int otx2_open(struct net_device *netdev) 1679 { 1680 struct otx2_nic *pf = netdev_priv(netdev); 1681 struct otx2_cq_poll *cq_poll = NULL; 1682 struct otx2_qset *qset = &pf->qset; 1683 int err = 0, qidx, vec; 1684 char *irq_name; 1685 1686 netif_carrier_off(netdev); 1687 1688 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1689 /* RQ and SQs are mapped to different CQs, 1690 * so find out max CQ IRQs (i.e CINTs) needed. 1691 */ 1692 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1693 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1694 if (!qset->napi) 1695 return -ENOMEM; 1696 1697 /* CQ size of RQ */ 1698 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1699 /* CQ size of SQ */ 1700 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1701 1702 err = -ENOMEM; 1703 qset->cq = kcalloc(pf->qset.cq_cnt, 1704 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1705 if (!qset->cq) 1706 goto err_free_mem; 1707 1708 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1709 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1710 if (!qset->sq) 1711 goto err_free_mem; 1712 1713 qset->rq = kcalloc(pf->hw.rx_queues, 1714 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1715 if (!qset->rq) 1716 goto err_free_mem; 1717 1718 err = otx2_init_hw_resources(pf); 1719 if (err) 1720 goto err_free_mem; 1721 1722 /* Register NAPI handler */ 1723 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1724 cq_poll = &qset->napi[qidx]; 1725 cq_poll->cint_idx = qidx; 1726 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1727 * 'cq_ids[0]' points to RQ's CQ and 1728 * 'cq_ids[1]' points to SQ's CQ and 1729 * 'cq_ids[2]' points to XDP's CQ and 1730 */ 1731 cq_poll->cq_ids[CQ_RX] = 1732 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1733 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1734 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1735 if (pf->xdp_prog) 1736 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1737 (qidx + pf->hw.rx_queues + 1738 pf->hw.tx_queues) : 1739 CINT_INVALID_CQ; 1740 else 1741 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1742 1743 cq_poll->dev = (void *)pf; 1744 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1745 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1746 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1747 napi_enable(&cq_poll->napi); 1748 } 1749 1750 /* Set maximum frame size allowed in HW */ 1751 err = otx2_hw_set_mtu(pf, netdev->mtu); 1752 if (err) 1753 goto err_disable_napi; 1754 1755 /* Setup segmentation algorithms, if failed, clear offload capability */ 1756 otx2_setup_segmentation(pf); 1757 1758 /* Initialize RSS */ 1759 err = otx2_rss_init(pf); 1760 if (err) 1761 goto err_disable_napi; 1762 1763 /* Register Queue IRQ handlers */ 1764 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1765 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1766 1767 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1768 1769 err = request_irq(pci_irq_vector(pf->pdev, vec), 1770 otx2_q_intr_handler, 0, irq_name, pf); 1771 if (err) { 1772 dev_err(pf->dev, 1773 "RVUPF%d: IRQ registration failed for QERR\n", 1774 rvu_get_pf(pf->pcifunc)); 1775 goto err_disable_napi; 1776 } 1777 1778 /* Enable QINT IRQ */ 1779 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1780 1781 /* Register CQ IRQ handlers */ 1782 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1783 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1784 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1785 1786 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1787 qidx); 1788 1789 err = request_irq(pci_irq_vector(pf->pdev, vec), 1790 otx2_cq_intr_handler, 0, irq_name, 1791 &qset->napi[qidx]); 1792 if (err) { 1793 dev_err(pf->dev, 1794 "RVUPF%d: IRQ registration failed for CQ%d\n", 1795 rvu_get_pf(pf->pcifunc), qidx); 1796 goto err_free_cints; 1797 } 1798 vec++; 1799 1800 otx2_config_irq_coalescing(pf, qidx); 1801 1802 /* Enable CQ IRQ */ 1803 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1804 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1805 } 1806 1807 otx2_set_cints_affinity(pf); 1808 1809 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1810 otx2_enable_rxvlan(pf, true); 1811 1812 /* When reinitializing enable time stamping if it is enabled before */ 1813 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1814 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1815 otx2_config_hw_tx_tstamp(pf, true); 1816 } 1817 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1818 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1819 otx2_config_hw_rx_tstamp(pf, true); 1820 } 1821 1822 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1823 /* 'intf_down' may be checked on any cpu */ 1824 smp_wmb(); 1825 1826 /* we have already received link status notification */ 1827 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1828 otx2_handle_link_event(pf); 1829 1830 /* Install DMAC Filters */ 1831 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1832 otx2_dmacflt_reinstall_flows(pf); 1833 1834 err = otx2_rxtx_enable(pf, true); 1835 /* If a mbox communication error happens at this point then interface 1836 * will end up in a state such that it is in down state but hardware 1837 * mcam entries are enabled to receive the packets. Hence disable the 1838 * packet I/O. 1839 */ 1840 if (err == EIO) 1841 goto err_disable_rxtx; 1842 else if (err) 1843 goto err_tx_stop_queues; 1844 1845 otx2_do_set_rx_mode(pf); 1846 1847 return 0; 1848 1849 err_disable_rxtx: 1850 otx2_rxtx_enable(pf, false); 1851 err_tx_stop_queues: 1852 netif_tx_stop_all_queues(netdev); 1853 netif_carrier_off(netdev); 1854 pf->flags |= OTX2_FLAG_INTF_DOWN; 1855 err_free_cints: 1856 otx2_free_cints(pf, qidx); 1857 vec = pci_irq_vector(pf->pdev, 1858 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1859 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1860 free_irq(vec, pf); 1861 err_disable_napi: 1862 otx2_disable_napi(pf); 1863 otx2_free_hw_resources(pf); 1864 err_free_mem: 1865 kfree(qset->sq); 1866 kfree(qset->cq); 1867 kfree(qset->rq); 1868 kfree(qset->napi); 1869 return err; 1870 } 1871 EXPORT_SYMBOL(otx2_open); 1872 1873 int otx2_stop(struct net_device *netdev) 1874 { 1875 struct otx2_nic *pf = netdev_priv(netdev); 1876 struct otx2_cq_poll *cq_poll = NULL; 1877 struct otx2_qset *qset = &pf->qset; 1878 struct otx2_rss_info *rss; 1879 int qidx, vec, wrk; 1880 1881 /* If the DOWN flag is set resources are already freed */ 1882 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1883 return 0; 1884 1885 netif_carrier_off(netdev); 1886 netif_tx_stop_all_queues(netdev); 1887 1888 pf->flags |= OTX2_FLAG_INTF_DOWN; 1889 /* 'intf_down' may be checked on any cpu */ 1890 smp_wmb(); 1891 1892 /* First stop packet Rx/Tx */ 1893 otx2_rxtx_enable(pf, false); 1894 1895 /* Clear RSS enable flag */ 1896 rss = &pf->hw.rss_info; 1897 rss->enable = false; 1898 1899 /* Cleanup Queue IRQ */ 1900 vec = pci_irq_vector(pf->pdev, 1901 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1902 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1903 free_irq(vec, pf); 1904 1905 /* Cleanup CQ NAPI and IRQ */ 1906 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1907 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1908 /* Disable interrupt */ 1909 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1910 1911 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1912 1913 cq_poll = &qset->napi[qidx]; 1914 napi_synchronize(&cq_poll->napi); 1915 vec++; 1916 } 1917 1918 netif_tx_disable(netdev); 1919 1920 otx2_free_hw_resources(pf); 1921 otx2_free_cints(pf, pf->hw.cint_cnt); 1922 otx2_disable_napi(pf); 1923 1924 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1925 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1926 1927 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1928 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1929 devm_kfree(pf->dev, pf->refill_wrk); 1930 1931 kfree(qset->sq); 1932 kfree(qset->cq); 1933 kfree(qset->rq); 1934 kfree(qset->napi); 1935 /* Do not clear RQ/SQ ringsize settings */ 1936 memset_startat(qset, 0, sqe_cnt); 1937 return 0; 1938 } 1939 EXPORT_SYMBOL(otx2_stop); 1940 1941 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1942 { 1943 struct otx2_nic *pf = netdev_priv(netdev); 1944 int qidx = skb_get_queue_mapping(skb); 1945 struct otx2_snd_queue *sq; 1946 struct netdev_queue *txq; 1947 1948 /* Check for minimum and maximum packet length */ 1949 if (skb->len <= ETH_HLEN || 1950 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1951 dev_kfree_skb(skb); 1952 return NETDEV_TX_OK; 1953 } 1954 1955 sq = &pf->qset.sq[qidx]; 1956 txq = netdev_get_tx_queue(netdev, qidx); 1957 1958 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1959 netif_tx_stop_queue(txq); 1960 1961 /* Check again, incase SQBs got freed up */ 1962 smp_mb(); 1963 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1964 > sq->sqe_thresh) 1965 netif_tx_wake_queue(txq); 1966 1967 return NETDEV_TX_BUSY; 1968 } 1969 1970 return NETDEV_TX_OK; 1971 } 1972 1973 static u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1974 struct net_device *sb_dev) 1975 { 1976 #ifdef CONFIG_DCB 1977 struct otx2_nic *pf = netdev_priv(netdev); 1978 u8 vlan_prio; 1979 #endif 1980 1981 #ifdef CONFIG_DCB 1982 if (!skb_vlan_tag_present(skb)) 1983 goto pick_tx; 1984 1985 vlan_prio = skb->vlan_tci >> 13; 1986 if ((vlan_prio > pf->hw.tx_queues - 1) || 1987 !pf->pfc_alloc_status[vlan_prio]) 1988 goto pick_tx; 1989 1990 return vlan_prio; 1991 1992 pick_tx: 1993 #endif 1994 return netdev_pick_tx(netdev, skb, NULL); 1995 } 1996 1997 static netdev_features_t otx2_fix_features(struct net_device *dev, 1998 netdev_features_t features) 1999 { 2000 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2001 features |= NETIF_F_HW_VLAN_STAG_RX; 2002 else 2003 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2004 2005 return features; 2006 } 2007 2008 static void otx2_set_rx_mode(struct net_device *netdev) 2009 { 2010 struct otx2_nic *pf = netdev_priv(netdev); 2011 2012 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2013 } 2014 2015 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2016 { 2017 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2018 2019 otx2_do_set_rx_mode(pf); 2020 } 2021 2022 static int otx2_set_features(struct net_device *netdev, 2023 netdev_features_t features) 2024 { 2025 netdev_features_t changed = features ^ netdev->features; 2026 struct otx2_nic *pf = netdev_priv(netdev); 2027 2028 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2029 return otx2_cgx_config_loopback(pf, 2030 features & NETIF_F_LOOPBACK); 2031 2032 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2033 return otx2_enable_rxvlan(pf, 2034 features & NETIF_F_HW_VLAN_CTAG_RX); 2035 2036 return otx2_handle_ntuple_tc_features(netdev, features); 2037 } 2038 2039 static void otx2_reset_task(struct work_struct *work) 2040 { 2041 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2042 2043 if (!netif_running(pf->netdev)) 2044 return; 2045 2046 rtnl_lock(); 2047 otx2_stop(pf->netdev); 2048 pf->reset_count++; 2049 otx2_open(pf->netdev); 2050 netif_trans_update(pf->netdev); 2051 rtnl_unlock(); 2052 } 2053 2054 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2055 { 2056 struct msg_req *req; 2057 int err; 2058 2059 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2060 return 0; 2061 2062 mutex_lock(&pfvf->mbox.lock); 2063 if (enable) 2064 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2065 else 2066 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2067 if (!req) { 2068 mutex_unlock(&pfvf->mbox.lock); 2069 return -ENOMEM; 2070 } 2071 2072 err = otx2_sync_mbox_msg(&pfvf->mbox); 2073 if (err) { 2074 mutex_unlock(&pfvf->mbox.lock); 2075 return err; 2076 } 2077 2078 mutex_unlock(&pfvf->mbox.lock); 2079 if (enable) 2080 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2081 else 2082 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2083 return 0; 2084 } 2085 2086 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2087 { 2088 struct msg_req *req; 2089 int err; 2090 2091 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2092 return 0; 2093 2094 mutex_lock(&pfvf->mbox.lock); 2095 if (enable) 2096 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2097 else 2098 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2099 if (!req) { 2100 mutex_unlock(&pfvf->mbox.lock); 2101 return -ENOMEM; 2102 } 2103 2104 err = otx2_sync_mbox_msg(&pfvf->mbox); 2105 if (err) { 2106 mutex_unlock(&pfvf->mbox.lock); 2107 return err; 2108 } 2109 2110 mutex_unlock(&pfvf->mbox.lock); 2111 if (enable) 2112 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2113 else 2114 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2115 return 0; 2116 } 2117 2118 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2119 { 2120 struct otx2_nic *pfvf = netdev_priv(netdev); 2121 struct hwtstamp_config config; 2122 2123 if (!pfvf->ptp) 2124 return -ENODEV; 2125 2126 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2127 return -EFAULT; 2128 2129 switch (config.tx_type) { 2130 case HWTSTAMP_TX_OFF: 2131 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2132 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2133 2134 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2135 otx2_config_hw_tx_tstamp(pfvf, false); 2136 break; 2137 case HWTSTAMP_TX_ONESTEP_SYNC: 2138 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2139 return -ERANGE; 2140 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2141 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2142 msecs_to_jiffies(500)); 2143 fallthrough; 2144 case HWTSTAMP_TX_ON: 2145 otx2_config_hw_tx_tstamp(pfvf, true); 2146 break; 2147 default: 2148 return -ERANGE; 2149 } 2150 2151 switch (config.rx_filter) { 2152 case HWTSTAMP_FILTER_NONE: 2153 otx2_config_hw_rx_tstamp(pfvf, false); 2154 break; 2155 case HWTSTAMP_FILTER_ALL: 2156 case HWTSTAMP_FILTER_SOME: 2157 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2158 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2159 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2160 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2161 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2162 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2163 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2164 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2165 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2166 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2167 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2168 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2169 otx2_config_hw_rx_tstamp(pfvf, true); 2170 config.rx_filter = HWTSTAMP_FILTER_ALL; 2171 break; 2172 default: 2173 return -ERANGE; 2174 } 2175 2176 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2177 2178 return copy_to_user(ifr->ifr_data, &config, 2179 sizeof(config)) ? -EFAULT : 0; 2180 } 2181 EXPORT_SYMBOL(otx2_config_hwtstamp); 2182 2183 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2184 { 2185 struct otx2_nic *pfvf = netdev_priv(netdev); 2186 struct hwtstamp_config *cfg = &pfvf->tstamp; 2187 2188 switch (cmd) { 2189 case SIOCSHWTSTAMP: 2190 return otx2_config_hwtstamp(netdev, req); 2191 case SIOCGHWTSTAMP: 2192 return copy_to_user(req->ifr_data, cfg, 2193 sizeof(*cfg)) ? -EFAULT : 0; 2194 default: 2195 return -EOPNOTSUPP; 2196 } 2197 } 2198 EXPORT_SYMBOL(otx2_ioctl); 2199 2200 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2201 { 2202 struct npc_install_flow_req *req; 2203 int err; 2204 2205 mutex_lock(&pf->mbox.lock); 2206 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2207 if (!req) { 2208 err = -ENOMEM; 2209 goto out; 2210 } 2211 2212 ether_addr_copy(req->packet.dmac, mac); 2213 eth_broadcast_addr((u8 *)&req->mask.dmac); 2214 req->features = BIT_ULL(NPC_DMAC); 2215 req->channel = pf->hw.rx_chan_base; 2216 req->intf = NIX_INTF_RX; 2217 req->default_rule = 1; 2218 req->append = 1; 2219 req->vf = vf + 1; 2220 req->op = NIX_RX_ACTION_DEFAULT; 2221 2222 err = otx2_sync_mbox_msg(&pf->mbox); 2223 out: 2224 mutex_unlock(&pf->mbox.lock); 2225 return err; 2226 } 2227 2228 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2229 { 2230 struct otx2_nic *pf = netdev_priv(netdev); 2231 struct pci_dev *pdev = pf->pdev; 2232 struct otx2_vf_config *config; 2233 int ret; 2234 2235 if (!netif_running(netdev)) 2236 return -EAGAIN; 2237 2238 if (vf >= pf->total_vfs) 2239 return -EINVAL; 2240 2241 if (!is_valid_ether_addr(mac)) 2242 return -EINVAL; 2243 2244 config = &pf->vf_configs[vf]; 2245 ether_addr_copy(config->mac, mac); 2246 2247 ret = otx2_do_set_vf_mac(pf, vf, mac); 2248 if (ret == 0) 2249 dev_info(&pdev->dev, 2250 "Load/Reload VF driver\n"); 2251 2252 return ret; 2253 } 2254 2255 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2256 __be16 proto) 2257 { 2258 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2259 struct nix_vtag_config_rsp *vtag_rsp; 2260 struct npc_delete_flow_req *del_req; 2261 struct nix_vtag_config *vtag_req; 2262 struct npc_install_flow_req *req; 2263 struct otx2_vf_config *config; 2264 int err = 0; 2265 u32 idx; 2266 2267 config = &pf->vf_configs[vf]; 2268 2269 if (!vlan && !config->vlan) 2270 goto out; 2271 2272 mutex_lock(&pf->mbox.lock); 2273 2274 /* free old tx vtag entry */ 2275 if (config->vlan) { 2276 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2277 if (!vtag_req) { 2278 err = -ENOMEM; 2279 goto out; 2280 } 2281 vtag_req->cfg_type = 0; 2282 vtag_req->tx.free_vtag0 = 1; 2283 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2284 2285 err = otx2_sync_mbox_msg(&pf->mbox); 2286 if (err) 2287 goto out; 2288 } 2289 2290 if (!vlan && config->vlan) { 2291 /* rx */ 2292 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2293 if (!del_req) { 2294 err = -ENOMEM; 2295 goto out; 2296 } 2297 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2298 del_req->entry = 2299 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2300 err = otx2_sync_mbox_msg(&pf->mbox); 2301 if (err) 2302 goto out; 2303 2304 /* tx */ 2305 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2306 if (!del_req) { 2307 err = -ENOMEM; 2308 goto out; 2309 } 2310 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2311 del_req->entry = 2312 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2313 err = otx2_sync_mbox_msg(&pf->mbox); 2314 2315 goto out; 2316 } 2317 2318 /* rx */ 2319 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2320 if (!req) { 2321 err = -ENOMEM; 2322 goto out; 2323 } 2324 2325 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2326 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2327 req->packet.vlan_tci = htons(vlan); 2328 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2329 /* af fills the destination mac addr */ 2330 eth_broadcast_addr((u8 *)&req->mask.dmac); 2331 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2332 req->channel = pf->hw.rx_chan_base; 2333 req->intf = NIX_INTF_RX; 2334 req->vf = vf + 1; 2335 req->op = NIX_RX_ACTION_DEFAULT; 2336 req->vtag0_valid = true; 2337 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2338 req->set_cntr = 1; 2339 2340 err = otx2_sync_mbox_msg(&pf->mbox); 2341 if (err) 2342 goto out; 2343 2344 /* tx */ 2345 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2346 if (!vtag_req) { 2347 err = -ENOMEM; 2348 goto out; 2349 } 2350 2351 /* configure tx vtag params */ 2352 vtag_req->vtag_size = VTAGSIZE_T4; 2353 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2354 vtag_req->tx.cfg_vtag0 = 1; 2355 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2356 2357 err = otx2_sync_mbox_msg(&pf->mbox); 2358 if (err) 2359 goto out; 2360 2361 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2362 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2363 if (IS_ERR(vtag_rsp)) { 2364 err = PTR_ERR(vtag_rsp); 2365 goto out; 2366 } 2367 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2368 2369 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2370 if (!req) { 2371 err = -ENOMEM; 2372 goto out; 2373 } 2374 2375 eth_zero_addr((u8 *)&req->mask.dmac); 2376 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2377 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2378 req->features = BIT_ULL(NPC_DMAC); 2379 req->channel = pf->hw.tx_chan_base; 2380 req->intf = NIX_INTF_TX; 2381 req->vf = vf + 1; 2382 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2383 req->vtag0_def = vtag_rsp->vtag0_idx; 2384 req->vtag0_op = VTAG_INSERT; 2385 req->set_cntr = 1; 2386 2387 err = otx2_sync_mbox_msg(&pf->mbox); 2388 out: 2389 config->vlan = vlan; 2390 mutex_unlock(&pf->mbox.lock); 2391 return err; 2392 } 2393 2394 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2395 __be16 proto) 2396 { 2397 struct otx2_nic *pf = netdev_priv(netdev); 2398 struct pci_dev *pdev = pf->pdev; 2399 2400 if (!netif_running(netdev)) 2401 return -EAGAIN; 2402 2403 if (vf >= pci_num_vf(pdev)) 2404 return -EINVAL; 2405 2406 /* qos is currently unsupported */ 2407 if (vlan >= VLAN_N_VID || qos) 2408 return -EINVAL; 2409 2410 if (proto != htons(ETH_P_8021Q)) 2411 return -EPROTONOSUPPORT; 2412 2413 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2414 return -EOPNOTSUPP; 2415 2416 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2417 } 2418 2419 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2420 struct ifla_vf_info *ivi) 2421 { 2422 struct otx2_nic *pf = netdev_priv(netdev); 2423 struct pci_dev *pdev = pf->pdev; 2424 struct otx2_vf_config *config; 2425 2426 if (!netif_running(netdev)) 2427 return -EAGAIN; 2428 2429 if (vf >= pci_num_vf(pdev)) 2430 return -EINVAL; 2431 2432 config = &pf->vf_configs[vf]; 2433 ivi->vf = vf; 2434 ether_addr_copy(ivi->mac, config->mac); 2435 ivi->vlan = config->vlan; 2436 ivi->trusted = config->trusted; 2437 2438 return 0; 2439 } 2440 2441 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2442 int qidx) 2443 { 2444 struct page *page; 2445 u64 dma_addr; 2446 int err = 0; 2447 2448 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2449 offset_in_page(xdpf->data), xdpf->len, 2450 DMA_TO_DEVICE); 2451 if (dma_mapping_error(pf->dev, dma_addr)) 2452 return -ENOMEM; 2453 2454 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2455 if (!err) { 2456 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2457 page = virt_to_page(xdpf->data); 2458 put_page(page); 2459 return -ENOMEM; 2460 } 2461 return 0; 2462 } 2463 2464 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2465 struct xdp_frame **frames, u32 flags) 2466 { 2467 struct otx2_nic *pf = netdev_priv(netdev); 2468 int qidx = smp_processor_id(); 2469 struct otx2_snd_queue *sq; 2470 int drops = 0, i; 2471 2472 if (!netif_running(netdev)) 2473 return -ENETDOWN; 2474 2475 qidx += pf->hw.tx_queues; 2476 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2477 2478 /* Abort xmit if xdp queue is not */ 2479 if (unlikely(!sq)) 2480 return -ENXIO; 2481 2482 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2483 return -EINVAL; 2484 2485 for (i = 0; i < n; i++) { 2486 struct xdp_frame *xdpf = frames[i]; 2487 int err; 2488 2489 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2490 if (err) 2491 drops++; 2492 } 2493 return n - drops; 2494 } 2495 2496 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2497 { 2498 struct net_device *dev = pf->netdev; 2499 bool if_up = netif_running(pf->netdev); 2500 struct bpf_prog *old_prog; 2501 2502 if (prog && dev->mtu > MAX_XDP_MTU) { 2503 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2504 return -EOPNOTSUPP; 2505 } 2506 2507 if (if_up) 2508 otx2_stop(pf->netdev); 2509 2510 old_prog = xchg(&pf->xdp_prog, prog); 2511 2512 if (old_prog) 2513 bpf_prog_put(old_prog); 2514 2515 if (pf->xdp_prog) 2516 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2517 2518 /* Network stack and XDP shared same rx queues. 2519 * Use separate tx queues for XDP and network stack. 2520 */ 2521 if (pf->xdp_prog) { 2522 pf->hw.xdp_queues = pf->hw.rx_queues; 2523 xdp_features_set_redirect_target(dev, false); 2524 } else { 2525 pf->hw.xdp_queues = 0; 2526 xdp_features_clear_redirect_target(dev); 2527 } 2528 2529 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2530 2531 if (if_up) 2532 otx2_open(pf->netdev); 2533 2534 return 0; 2535 } 2536 2537 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2538 { 2539 struct otx2_nic *pf = netdev_priv(netdev); 2540 2541 switch (xdp->command) { 2542 case XDP_SETUP_PROG: 2543 return otx2_xdp_setup(pf, xdp->prog); 2544 default: 2545 return -EINVAL; 2546 } 2547 } 2548 2549 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2550 int req_perm) 2551 { 2552 struct set_vf_perm *req; 2553 int rc; 2554 2555 mutex_lock(&pf->mbox.lock); 2556 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2557 if (!req) { 2558 rc = -ENOMEM; 2559 goto out; 2560 } 2561 2562 /* Let AF reset VF permissions as sriov is disabled */ 2563 if (req_perm == OTX2_RESET_VF_PERM) { 2564 req->flags |= RESET_VF_PERM; 2565 } else if (req_perm == OTX2_TRUSTED_VF) { 2566 if (pf->vf_configs[vf].trusted) 2567 req->flags |= VF_TRUSTED; 2568 } 2569 2570 req->vf = vf; 2571 rc = otx2_sync_mbox_msg(&pf->mbox); 2572 out: 2573 mutex_unlock(&pf->mbox.lock); 2574 return rc; 2575 } 2576 2577 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2578 bool enable) 2579 { 2580 struct otx2_nic *pf = netdev_priv(netdev); 2581 struct pci_dev *pdev = pf->pdev; 2582 int rc; 2583 2584 if (vf >= pci_num_vf(pdev)) 2585 return -EINVAL; 2586 2587 if (pf->vf_configs[vf].trusted == enable) 2588 return 0; 2589 2590 pf->vf_configs[vf].trusted = enable; 2591 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2592 2593 if (rc) 2594 pf->vf_configs[vf].trusted = !enable; 2595 else 2596 netdev_info(pf->netdev, "VF %d is %strusted\n", 2597 vf, enable ? "" : "not "); 2598 return rc; 2599 } 2600 2601 static const struct net_device_ops otx2_netdev_ops = { 2602 .ndo_open = otx2_open, 2603 .ndo_stop = otx2_stop, 2604 .ndo_start_xmit = otx2_xmit, 2605 .ndo_select_queue = otx2_select_queue, 2606 .ndo_fix_features = otx2_fix_features, 2607 .ndo_set_mac_address = otx2_set_mac_address, 2608 .ndo_change_mtu = otx2_change_mtu, 2609 .ndo_set_rx_mode = otx2_set_rx_mode, 2610 .ndo_set_features = otx2_set_features, 2611 .ndo_tx_timeout = otx2_tx_timeout, 2612 .ndo_get_stats64 = otx2_get_stats64, 2613 .ndo_eth_ioctl = otx2_ioctl, 2614 .ndo_set_vf_mac = otx2_set_vf_mac, 2615 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2616 .ndo_get_vf_config = otx2_get_vf_config, 2617 .ndo_bpf = otx2_xdp, 2618 .ndo_xdp_xmit = otx2_xdp_xmit, 2619 .ndo_setup_tc = otx2_setup_tc, 2620 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2621 }; 2622 2623 static int otx2_wq_init(struct otx2_nic *pf) 2624 { 2625 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2626 if (!pf->otx2_wq) 2627 return -ENOMEM; 2628 2629 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2630 INIT_WORK(&pf->reset_task, otx2_reset_task); 2631 return 0; 2632 } 2633 2634 static int otx2_check_pf_usable(struct otx2_nic *nic) 2635 { 2636 u64 rev; 2637 2638 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2639 rev = (rev >> 12) & 0xFF; 2640 /* Check if AF has setup revision for RVUM block, 2641 * otherwise this driver probe should be deferred 2642 * until AF driver comes up. 2643 */ 2644 if (!rev) { 2645 dev_warn(nic->dev, 2646 "AF is not initialized, deferring probe\n"); 2647 return -EPROBE_DEFER; 2648 } 2649 return 0; 2650 } 2651 2652 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2653 { 2654 struct otx2_hw *hw = &pf->hw; 2655 int num_vec, err; 2656 2657 /* NPA interrupts are inot registered, so alloc only 2658 * upto NIX vector offset. 2659 */ 2660 num_vec = hw->nix_msixoff; 2661 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2662 2663 otx2_disable_mbox_intr(pf); 2664 pci_free_irq_vectors(hw->pdev); 2665 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2666 if (err < 0) { 2667 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2668 __func__, num_vec); 2669 return err; 2670 } 2671 2672 return otx2_register_mbox_intr(pf, false); 2673 } 2674 2675 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2676 { 2677 int i; 2678 2679 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2680 sizeof(struct otx2_vf_config), 2681 GFP_KERNEL); 2682 if (!pf->vf_configs) 2683 return -ENOMEM; 2684 2685 for (i = 0; i < pf->total_vfs; i++) { 2686 pf->vf_configs[i].pf = pf; 2687 pf->vf_configs[i].intf_down = true; 2688 pf->vf_configs[i].trusted = false; 2689 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2690 otx2_vf_link_event_task); 2691 } 2692 2693 return 0; 2694 } 2695 2696 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2697 { 2698 int i; 2699 2700 if (!pf->vf_configs) 2701 return; 2702 2703 for (i = 0; i < pf->total_vfs; i++) { 2704 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2705 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2706 } 2707 } 2708 2709 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2710 { 2711 struct device *dev = &pdev->dev; 2712 struct net_device *netdev; 2713 struct otx2_nic *pf; 2714 struct otx2_hw *hw; 2715 int err, qcount; 2716 int num_vec; 2717 2718 err = pcim_enable_device(pdev); 2719 if (err) { 2720 dev_err(dev, "Failed to enable PCI device\n"); 2721 return err; 2722 } 2723 2724 err = pci_request_regions(pdev, DRV_NAME); 2725 if (err) { 2726 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2727 return err; 2728 } 2729 2730 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2731 if (err) { 2732 dev_err(dev, "DMA mask config failed, abort\n"); 2733 goto err_release_regions; 2734 } 2735 2736 pci_set_master(pdev); 2737 2738 /* Set number of queues */ 2739 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2740 2741 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2742 if (!netdev) { 2743 err = -ENOMEM; 2744 goto err_release_regions; 2745 } 2746 2747 pci_set_drvdata(pdev, netdev); 2748 SET_NETDEV_DEV(netdev, &pdev->dev); 2749 pf = netdev_priv(netdev); 2750 pf->netdev = netdev; 2751 pf->pdev = pdev; 2752 pf->dev = dev; 2753 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2754 pf->flags |= OTX2_FLAG_INTF_DOWN; 2755 2756 hw = &pf->hw; 2757 hw->pdev = pdev; 2758 hw->rx_queues = qcount; 2759 hw->tx_queues = qcount; 2760 hw->tot_tx_queues = qcount; 2761 hw->max_queues = qcount; 2762 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2763 /* Use CQE of 128 byte descriptor size by default */ 2764 hw->xqe_size = 128; 2765 2766 num_vec = pci_msix_vec_count(pdev); 2767 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2768 GFP_KERNEL); 2769 if (!hw->irq_name) { 2770 err = -ENOMEM; 2771 goto err_free_netdev; 2772 } 2773 2774 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2775 sizeof(cpumask_var_t), GFP_KERNEL); 2776 if (!hw->affinity_mask) { 2777 err = -ENOMEM; 2778 goto err_free_netdev; 2779 } 2780 2781 /* Map CSRs */ 2782 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2783 if (!pf->reg_base) { 2784 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2785 err = -ENOMEM; 2786 goto err_free_netdev; 2787 } 2788 2789 err = otx2_check_pf_usable(pf); 2790 if (err) 2791 goto err_free_netdev; 2792 2793 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2794 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2795 if (err < 0) { 2796 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2797 __func__, num_vec); 2798 goto err_free_netdev; 2799 } 2800 2801 otx2_setup_dev_hw_settings(pf); 2802 2803 /* Init PF <=> AF mailbox stuff */ 2804 err = otx2_pfaf_mbox_init(pf); 2805 if (err) 2806 goto err_free_irq_vectors; 2807 2808 /* Register mailbox interrupt */ 2809 err = otx2_register_mbox_intr(pf, true); 2810 if (err) 2811 goto err_mbox_destroy; 2812 2813 /* Request AF to attach NPA and NIX LFs to this PF. 2814 * NIX and NPA LFs are needed for this PF to function as a NIC. 2815 */ 2816 err = otx2_attach_npa_nix(pf); 2817 if (err) 2818 goto err_disable_mbox_intr; 2819 2820 err = otx2_realloc_msix_vectors(pf); 2821 if (err) 2822 goto err_detach_rsrc; 2823 2824 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2825 if (err) 2826 goto err_detach_rsrc; 2827 2828 err = cn10k_lmtst_init(pf); 2829 if (err) 2830 goto err_detach_rsrc; 2831 2832 /* Assign default mac address */ 2833 otx2_get_mac_from_af(netdev); 2834 2835 /* Don't check for error. Proceed without ptp */ 2836 otx2_ptp_init(pf); 2837 2838 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2839 * HW allocates buffer pointer from stack and uses it for DMA'ing 2840 * ingress packet. In some scenarios HW can free back allocated buffer 2841 * pointers to pool. This makes it impossible for SW to maintain a 2842 * parallel list where physical addresses of buffer pointers (IOVAs) 2843 * given to HW can be saved for later reference. 2844 * 2845 * So the only way to convert Rx packet's buffer address is to use 2846 * IOMMU's iova_to_phys() handler which translates the address by 2847 * walking through the translation tables. 2848 */ 2849 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2850 2851 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2852 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2853 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2854 NETIF_F_GSO_UDP_L4); 2855 netdev->features |= netdev->hw_features; 2856 2857 err = otx2_mcam_flow_init(pf); 2858 if (err) 2859 goto err_ptp_destroy; 2860 2861 err = cn10k_mcs_init(pf); 2862 if (err) 2863 goto err_del_mcam_entries; 2864 2865 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2866 netdev->hw_features |= NETIF_F_NTUPLE; 2867 2868 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2869 netdev->priv_flags |= IFF_UNICAST_FLT; 2870 2871 /* Support TSO on tag interface */ 2872 netdev->vlan_features |= netdev->features; 2873 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2874 NETIF_F_HW_VLAN_STAG_TX; 2875 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2876 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2877 NETIF_F_HW_VLAN_STAG_RX; 2878 netdev->features |= netdev->hw_features; 2879 2880 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2881 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2882 netdev->hw_features |= NETIF_F_HW_TC; 2883 2884 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2885 2886 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2887 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2888 2889 netdev->netdev_ops = &otx2_netdev_ops; 2890 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 2891 2892 netdev->min_mtu = OTX2_MIN_MTU; 2893 netdev->max_mtu = otx2_get_max_mtu(pf); 2894 2895 err = register_netdev(netdev); 2896 if (err) { 2897 dev_err(dev, "Failed to register netdevice\n"); 2898 goto err_mcs_free; 2899 } 2900 2901 err = otx2_wq_init(pf); 2902 if (err) 2903 goto err_unreg_netdev; 2904 2905 otx2_set_ethtool_ops(netdev); 2906 2907 err = otx2_init_tc(pf); 2908 if (err) 2909 goto err_mcam_flow_del; 2910 2911 err = otx2_register_dl(pf); 2912 if (err) 2913 goto err_mcam_flow_del; 2914 2915 /* Initialize SR-IOV resources */ 2916 err = otx2_sriov_vfcfg_init(pf); 2917 if (err) 2918 goto err_pf_sriov_init; 2919 2920 /* Enable link notifications */ 2921 otx2_cgx_config_linkevents(pf, true); 2922 2923 #ifdef CONFIG_DCB 2924 err = otx2_dcbnl_set_ops(netdev); 2925 if (err) 2926 goto err_pf_sriov_init; 2927 #endif 2928 2929 return 0; 2930 2931 err_pf_sriov_init: 2932 otx2_shutdown_tc(pf); 2933 err_mcam_flow_del: 2934 otx2_mcam_flow_del(pf); 2935 err_unreg_netdev: 2936 unregister_netdev(netdev); 2937 err_mcs_free: 2938 cn10k_mcs_free(pf); 2939 err_del_mcam_entries: 2940 otx2_mcam_flow_del(pf); 2941 err_ptp_destroy: 2942 otx2_ptp_destroy(pf); 2943 err_detach_rsrc: 2944 if (pf->hw.lmt_info) 2945 free_percpu(pf->hw.lmt_info); 2946 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2947 qmem_free(pf->dev, pf->dync_lmt); 2948 otx2_detach_resources(&pf->mbox); 2949 err_disable_mbox_intr: 2950 otx2_disable_mbox_intr(pf); 2951 err_mbox_destroy: 2952 otx2_pfaf_mbox_destroy(pf); 2953 err_free_irq_vectors: 2954 pci_free_irq_vectors(hw->pdev); 2955 err_free_netdev: 2956 pci_set_drvdata(pdev, NULL); 2957 free_netdev(netdev); 2958 err_release_regions: 2959 pci_release_regions(pdev); 2960 return err; 2961 } 2962 2963 static void otx2_vf_link_event_task(struct work_struct *work) 2964 { 2965 struct otx2_vf_config *config; 2966 struct cgx_link_info_msg *req; 2967 struct mbox_msghdr *msghdr; 2968 struct otx2_nic *pf; 2969 int vf_idx; 2970 2971 config = container_of(work, struct otx2_vf_config, 2972 link_event_work.work); 2973 vf_idx = config - config->pf->vf_configs; 2974 pf = config->pf; 2975 2976 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2977 sizeof(*req), sizeof(struct msg_rsp)); 2978 if (!msghdr) { 2979 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2980 return; 2981 } 2982 2983 req = (struct cgx_link_info_msg *)msghdr; 2984 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2985 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2986 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2987 2988 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2989 } 2990 2991 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2992 { 2993 struct net_device *netdev = pci_get_drvdata(pdev); 2994 struct otx2_nic *pf = netdev_priv(netdev); 2995 int ret; 2996 2997 /* Init PF <=> VF mailbox stuff */ 2998 ret = otx2_pfvf_mbox_init(pf, numvfs); 2999 if (ret) 3000 return ret; 3001 3002 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3003 if (ret) 3004 goto free_mbox; 3005 3006 ret = otx2_pf_flr_init(pf, numvfs); 3007 if (ret) 3008 goto free_intr; 3009 3010 ret = otx2_register_flr_me_intr(pf, numvfs); 3011 if (ret) 3012 goto free_flr; 3013 3014 ret = pci_enable_sriov(pdev, numvfs); 3015 if (ret) 3016 goto free_flr_intr; 3017 3018 return numvfs; 3019 free_flr_intr: 3020 otx2_disable_flr_me_intr(pf); 3021 free_flr: 3022 otx2_flr_wq_destroy(pf); 3023 free_intr: 3024 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3025 free_mbox: 3026 otx2_pfvf_mbox_destroy(pf); 3027 return ret; 3028 } 3029 3030 static int otx2_sriov_disable(struct pci_dev *pdev) 3031 { 3032 struct net_device *netdev = pci_get_drvdata(pdev); 3033 struct otx2_nic *pf = netdev_priv(netdev); 3034 int numvfs = pci_num_vf(pdev); 3035 3036 if (!numvfs) 3037 return 0; 3038 3039 pci_disable_sriov(pdev); 3040 3041 otx2_disable_flr_me_intr(pf); 3042 otx2_flr_wq_destroy(pf); 3043 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3044 otx2_pfvf_mbox_destroy(pf); 3045 3046 return 0; 3047 } 3048 3049 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3050 { 3051 if (numvfs == 0) 3052 return otx2_sriov_disable(pdev); 3053 else 3054 return otx2_sriov_enable(pdev, numvfs); 3055 } 3056 3057 static void otx2_remove(struct pci_dev *pdev) 3058 { 3059 struct net_device *netdev = pci_get_drvdata(pdev); 3060 struct otx2_nic *pf; 3061 3062 if (!netdev) 3063 return; 3064 3065 pf = netdev_priv(netdev); 3066 3067 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3068 3069 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3070 otx2_config_hw_tx_tstamp(pf, false); 3071 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3072 otx2_config_hw_rx_tstamp(pf, false); 3073 3074 /* Disable 802.3x pause frames */ 3075 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3076 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3077 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3078 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3079 otx2_config_pause_frm(pf); 3080 } 3081 3082 #ifdef CONFIG_DCB 3083 /* Disable PFC config */ 3084 if (pf->pfc_en) { 3085 pf->pfc_en = 0; 3086 otx2_config_priority_flow_ctrl(pf); 3087 } 3088 #endif 3089 cancel_work_sync(&pf->reset_task); 3090 /* Disable link notifications */ 3091 otx2_cgx_config_linkevents(pf, false); 3092 3093 otx2_unregister_dl(pf); 3094 unregister_netdev(netdev); 3095 cn10k_mcs_free(pf); 3096 otx2_sriov_disable(pf->pdev); 3097 otx2_sriov_vfcfg_cleanup(pf); 3098 if (pf->otx2_wq) 3099 destroy_workqueue(pf->otx2_wq); 3100 3101 otx2_ptp_destroy(pf); 3102 otx2_mcam_flow_del(pf); 3103 otx2_shutdown_tc(pf); 3104 otx2_detach_resources(&pf->mbox); 3105 if (pf->hw.lmt_info) 3106 free_percpu(pf->hw.lmt_info); 3107 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3108 qmem_free(pf->dev, pf->dync_lmt); 3109 otx2_disable_mbox_intr(pf); 3110 otx2_pfaf_mbox_destroy(pf); 3111 pci_free_irq_vectors(pf->pdev); 3112 pci_set_drvdata(pdev, NULL); 3113 free_netdev(netdev); 3114 3115 pci_release_regions(pdev); 3116 } 3117 3118 static struct pci_driver otx2_pf_driver = { 3119 .name = DRV_NAME, 3120 .id_table = otx2_pf_id_table, 3121 .probe = otx2_probe, 3122 .shutdown = otx2_remove, 3123 .remove = otx2_remove, 3124 .sriov_configure = otx2_sriov_configure 3125 }; 3126 3127 static int __init otx2_rvupf_init_module(void) 3128 { 3129 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3130 3131 return pci_register_driver(&otx2_pf_driver); 3132 } 3133 3134 static void __exit otx2_rvupf_cleanup_module(void) 3135 { 3136 pci_unregister_driver(&otx2_pf_driver); 3137 } 3138 3139 module_init(otx2_rvupf_init_module); 3140 module_exit(otx2_rvupf_cleanup_module); 3141