1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Physcial Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/pci.h> 14 #include <linux/etherdevice.h> 15 #include <linux/of.h> 16 #include <linux/if_vlan.h> 17 #include <linux/iommu.h> 18 #include <net/ip.h> 19 20 #include "otx2_reg.h" 21 #include "otx2_common.h" 22 #include "otx2_txrx.h" 23 #include "otx2_struct.h" 24 #include "otx2_ptp.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "octeontx2-nicpf" 28 #define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 enum { 42 TYPE_PFAF, 43 TYPE_PFVF, 44 }; 45 46 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 47 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 48 49 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 50 { 51 bool if_up = netif_running(netdev); 52 int err = 0; 53 54 if (if_up) 55 otx2_stop(netdev); 56 57 netdev_info(netdev, "Changing MTU from %d to %d\n", 58 netdev->mtu, new_mtu); 59 netdev->mtu = new_mtu; 60 61 if (if_up) 62 err = otx2_open(netdev); 63 64 return err; 65 } 66 67 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 68 { 69 int irq, vfs = pf->total_vfs; 70 71 /* Disable VFs ME interrupts */ 72 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 73 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 74 free_irq(irq, pf); 75 76 /* Disable VFs FLR interrupts */ 77 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 78 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 79 free_irq(irq, pf); 80 81 if (vfs <= 64) 82 return; 83 84 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 85 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 86 free_irq(irq, pf); 87 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 90 free_irq(irq, pf); 91 } 92 93 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 94 { 95 if (!pf->flr_wq) 96 return; 97 destroy_workqueue(pf->flr_wq); 98 pf->flr_wq = NULL; 99 devm_kfree(pf->dev, pf->flr_wrk); 100 } 101 102 static void otx2_flr_handler(struct work_struct *work) 103 { 104 struct flr_work *flrwork = container_of(work, struct flr_work, work); 105 struct otx2_nic *pf = flrwork->pf; 106 struct mbox *mbox = &pf->mbox; 107 struct msg_req *req; 108 int vf, reg = 0; 109 110 vf = flrwork - pf->flr_wrk; 111 112 mutex_lock(&mbox->lock); 113 req = otx2_mbox_alloc_msg_vf_flr(mbox); 114 if (!req) { 115 mutex_unlock(&mbox->lock); 116 return; 117 } 118 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 119 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 120 121 if (!otx2_sync_mbox_msg(&pf->mbox)) { 122 if (vf >= 64) { 123 reg = 1; 124 vf = vf - 64; 125 } 126 /* clear transcation pending bit */ 127 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 128 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 129 } 130 131 mutex_unlock(&mbox->lock); 132 } 133 134 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 135 { 136 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 137 int reg, dev, vf, start_vf, num_reg = 1; 138 u64 intr; 139 140 if (pf->total_vfs > 64) 141 num_reg = 2; 142 143 for (reg = 0; reg < num_reg; reg++) { 144 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 145 if (!intr) 146 continue; 147 start_vf = 64 * reg; 148 for (vf = 0; vf < 64; vf++) { 149 if (!(intr & BIT_ULL(vf))) 150 continue; 151 dev = vf + start_vf; 152 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 153 /* Clear interrupt */ 154 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 155 /* Disable the interrupt */ 156 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 157 BIT_ULL(vf)); 158 } 159 } 160 return IRQ_HANDLED; 161 } 162 163 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 164 { 165 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 166 int vf, reg, num_reg = 1; 167 u64 intr; 168 169 if (pf->total_vfs > 64) 170 num_reg = 2; 171 172 for (reg = 0; reg < num_reg; reg++) { 173 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 174 if (!intr) 175 continue; 176 for (vf = 0; vf < 64; vf++) { 177 if (!(intr & BIT_ULL(vf))) 178 continue; 179 /* clear trpend bit */ 180 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 181 /* clear interrupt */ 182 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 183 } 184 } 185 return IRQ_HANDLED; 186 } 187 188 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 189 { 190 struct otx2_hw *hw = &pf->hw; 191 char *irq_name; 192 int ret; 193 194 /* Register ME interrupt handler*/ 195 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 196 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 197 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 198 otx2_pf_me_intr_handler, 0, irq_name, pf); 199 if (ret) { 200 dev_err(pf->dev, 201 "RVUPF: IRQ registration failed for ME0\n"); 202 } 203 204 /* Register FLR interrupt handler */ 205 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 206 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 207 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 208 otx2_pf_flr_intr_handler, 0, irq_name, pf); 209 if (ret) { 210 dev_err(pf->dev, 211 "RVUPF: IRQ registration failed for FLR0\n"); 212 return ret; 213 } 214 215 if (numvfs > 64) { 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 218 rvu_get_pf(pf->pcifunc)); 219 ret = request_irq(pci_irq_vector 220 (pf->pdev, RVU_PF_INT_VEC_VFME1), 221 otx2_pf_me_intr_handler, 0, irq_name, pf); 222 if (ret) { 223 dev_err(pf->dev, 224 "RVUPF: IRQ registration failed for ME1\n"); 225 } 226 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 227 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 228 rvu_get_pf(pf->pcifunc)); 229 ret = request_irq(pci_irq_vector 230 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 231 otx2_pf_flr_intr_handler, 0, irq_name, pf); 232 if (ret) { 233 dev_err(pf->dev, 234 "RVUPF: IRQ registration failed for FLR1\n"); 235 return ret; 236 } 237 } 238 239 /* Enable ME interrupt for all VFs*/ 240 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 241 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 242 243 /* Enable FLR interrupt for all VFs*/ 244 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 245 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 246 247 if (numvfs > 64) { 248 numvfs -= 64; 249 250 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 251 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 252 INTR_MASK(numvfs)); 253 254 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 255 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 256 INTR_MASK(numvfs)); 257 } 258 return 0; 259 } 260 261 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 262 { 263 int vf; 264 265 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 266 WQ_UNBOUND | WQ_HIGHPRI, 1); 267 if (!pf->flr_wq) 268 return -ENOMEM; 269 270 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 271 sizeof(struct flr_work), GFP_KERNEL); 272 if (!pf->flr_wrk) { 273 destroy_workqueue(pf->flr_wq); 274 return -ENOMEM; 275 } 276 277 for (vf = 0; vf < num_vfs; vf++) { 278 pf->flr_wrk[vf].pf = pf; 279 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 280 } 281 282 return 0; 283 } 284 285 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 286 int first, int mdevs, u64 intr, int type) 287 { 288 struct otx2_mbox_dev *mdev; 289 struct otx2_mbox *mbox; 290 struct mbox_hdr *hdr; 291 int i; 292 293 for (i = first; i < mdevs; i++) { 294 /* start from 0 */ 295 if (!(intr & BIT_ULL(i - first))) 296 continue; 297 298 mbox = &mw->mbox; 299 mdev = &mbox->dev[i]; 300 if (type == TYPE_PFAF) 301 otx2_sync_mbox_bbuf(mbox, i); 302 hdr = mdev->mbase + mbox->rx_start; 303 /* The hdr->num_msgs is set to zero immediately in the interrupt 304 * handler to ensure that it holds a correct value next time 305 * when the interrupt handler is called. 306 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 307 * pf>mbox.up_num_msgs holds the data for use in 308 * pfaf_mbox_up_handler. 309 */ 310 if (hdr->num_msgs) { 311 mw[i].num_msgs = hdr->num_msgs; 312 hdr->num_msgs = 0; 313 if (type == TYPE_PFAF) 314 memset(mbox->hwbase + mbox->rx_start, 0, 315 ALIGN(sizeof(struct mbox_hdr), 316 sizeof(u64))); 317 318 queue_work(mbox_wq, &mw[i].mbox_wrk); 319 } 320 321 mbox = &mw->mbox_up; 322 mdev = &mbox->dev[i]; 323 if (type == TYPE_PFAF) 324 otx2_sync_mbox_bbuf(mbox, i); 325 hdr = mdev->mbase + mbox->rx_start; 326 if (hdr->num_msgs) { 327 mw[i].up_num_msgs = hdr->num_msgs; 328 hdr->num_msgs = 0; 329 if (type == TYPE_PFAF) 330 memset(mbox->hwbase + mbox->rx_start, 0, 331 ALIGN(sizeof(struct mbox_hdr), 332 sizeof(u64))); 333 334 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 335 } 336 } 337 } 338 339 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 340 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 341 int devid) 342 { 343 struct otx2_mbox_dev *src_mdev = mdev; 344 int offset; 345 346 /* Msgs are already copied, trigger VF's mbox irq */ 347 smp_wmb(); 348 349 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 350 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 351 352 /* Restore VF's mbox bounce buffer region address */ 353 src_mdev->mbase = bbuf_base; 354 } 355 356 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 357 struct otx2_mbox *src_mbox, 358 int dir, int vf, int num_msgs) 359 { 360 struct otx2_mbox_dev *src_mdev, *dst_mdev; 361 struct mbox_hdr *mbox_hdr; 362 struct mbox_hdr *req_hdr; 363 struct mbox *dst_mbox; 364 int dst_size, err; 365 366 if (dir == MBOX_DIR_PFAF) { 367 /* Set VF's mailbox memory as PF's bounce buffer memory, so 368 * that explicit copying of VF's msgs to PF=>AF mbox region 369 * and AF=>PF responses to VF's mbox region can be avoided. 370 */ 371 src_mdev = &src_mbox->dev[vf]; 372 mbox_hdr = src_mbox->hwbase + 373 src_mbox->rx_start + (vf * MBOX_SIZE); 374 375 dst_mbox = &pf->mbox; 376 dst_size = dst_mbox->mbox.tx_size - 377 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 378 /* Check if msgs fit into destination area and has valid size */ 379 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 380 return -EINVAL; 381 382 dst_mdev = &dst_mbox->mbox.dev[0]; 383 384 mutex_lock(&pf->mbox.lock); 385 dst_mdev->mbase = src_mdev->mbase; 386 dst_mdev->msg_size = mbox_hdr->msg_size; 387 dst_mdev->num_msgs = num_msgs; 388 err = otx2_sync_mbox_msg(dst_mbox); 389 if (err) { 390 dev_warn(pf->dev, 391 "AF not responding to VF%d messages\n", vf); 392 /* restore PF mbase and exit */ 393 dst_mdev->mbase = pf->mbox.bbuf_base; 394 mutex_unlock(&pf->mbox.lock); 395 return err; 396 } 397 /* At this point, all the VF messages sent to AF are acked 398 * with proper responses and responses are copied to VF 399 * mailbox hence raise interrupt to VF. 400 */ 401 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 402 dst_mbox->mbox.rx_start); 403 req_hdr->num_msgs = num_msgs; 404 405 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 406 pf->mbox.bbuf_base, vf); 407 mutex_unlock(&pf->mbox.lock); 408 } else if (dir == MBOX_DIR_PFVF_UP) { 409 src_mdev = &src_mbox->dev[0]; 410 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 411 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 412 src_mbox->rx_start); 413 req_hdr->num_msgs = num_msgs; 414 415 dst_mbox = &pf->mbox_pfvf[0]; 416 dst_size = dst_mbox->mbox_up.tx_size - 417 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 418 /* Check if msgs fit into destination area */ 419 if (mbox_hdr->msg_size > dst_size) 420 return -EINVAL; 421 422 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 423 dst_mdev->mbase = src_mdev->mbase; 424 dst_mdev->msg_size = mbox_hdr->msg_size; 425 dst_mdev->num_msgs = mbox_hdr->num_msgs; 426 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 427 if (err) { 428 dev_warn(pf->dev, 429 "VF%d is not responding to mailbox\n", vf); 430 return err; 431 } 432 } else if (dir == MBOX_DIR_VFPF_UP) { 433 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 434 src_mbox->rx_start); 435 req_hdr->num_msgs = num_msgs; 436 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 437 &pf->mbox.mbox_up, 438 pf->mbox_pfvf[vf].bbuf_base, 439 0); 440 } 441 442 return 0; 443 } 444 445 static void otx2_pfvf_mbox_handler(struct work_struct *work) 446 { 447 struct mbox_msghdr *msg = NULL; 448 int offset, vf_idx, id, err; 449 struct otx2_mbox_dev *mdev; 450 struct mbox_hdr *req_hdr; 451 struct otx2_mbox *mbox; 452 struct mbox *vf_mbox; 453 struct otx2_nic *pf; 454 455 vf_mbox = container_of(work, struct mbox, mbox_wrk); 456 pf = vf_mbox->pfvf; 457 vf_idx = vf_mbox - pf->mbox_pfvf; 458 459 mbox = &pf->mbox_pfvf[0].mbox; 460 mdev = &mbox->dev[vf_idx]; 461 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 462 463 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 464 465 for (id = 0; id < vf_mbox->num_msgs; id++) { 466 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 467 offset); 468 469 if (msg->sig != OTX2_MBOX_REQ_SIG) 470 goto inval_msg; 471 472 /* Set VF's number in each of the msg */ 473 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 474 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 475 offset = msg->next_msgoff; 476 } 477 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 478 vf_mbox->num_msgs); 479 if (err) 480 goto inval_msg; 481 return; 482 483 inval_msg: 484 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 485 otx2_mbox_msg_send(mbox, vf_idx); 486 } 487 488 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 489 { 490 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 491 struct otx2_nic *pf = vf_mbox->pfvf; 492 struct otx2_mbox_dev *mdev; 493 int offset, id, vf_idx = 0; 494 struct mbox_hdr *rsp_hdr; 495 struct mbox_msghdr *msg; 496 struct otx2_mbox *mbox; 497 498 vf_idx = vf_mbox - pf->mbox_pfvf; 499 mbox = &pf->mbox_pfvf[0].mbox_up; 500 mdev = &mbox->dev[vf_idx]; 501 502 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 503 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 504 505 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 506 msg = mdev->mbase + offset; 507 508 if (msg->id >= MBOX_MSG_MAX) { 509 dev_err(pf->dev, 510 "Mbox msg with unknown ID 0x%x\n", msg->id); 511 goto end; 512 } 513 514 if (msg->sig != OTX2_MBOX_RSP_SIG) { 515 dev_err(pf->dev, 516 "Mbox msg with wrong signature %x, ID 0x%x\n", 517 msg->sig, msg->id); 518 goto end; 519 } 520 521 switch (msg->id) { 522 case MBOX_MSG_CGX_LINK_EVENT: 523 break; 524 default: 525 if (msg->rc) 526 dev_err(pf->dev, 527 "Mbox msg response has err %d, ID 0x%x\n", 528 msg->rc, msg->id); 529 break; 530 } 531 532 end: 533 offset = mbox->rx_start + msg->next_msgoff; 534 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 535 __otx2_mbox_reset(mbox, 0); 536 mdev->msgs_acked++; 537 } 538 } 539 540 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 541 { 542 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 543 int vfs = pf->total_vfs; 544 struct mbox *mbox; 545 u64 intr; 546 547 mbox = pf->mbox_pfvf; 548 /* Handle VF interrupts */ 549 if (vfs > 64) { 550 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 551 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 552 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 553 TYPE_PFVF); 554 vfs -= 64; 555 } 556 557 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 558 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 559 560 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 561 562 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 563 564 return IRQ_HANDLED; 565 } 566 567 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 568 { 569 void __iomem *hwbase; 570 struct mbox *mbox; 571 int err, vf; 572 u64 base; 573 574 if (!numvfs) 575 return -EINVAL; 576 577 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 578 sizeof(struct mbox), GFP_KERNEL); 579 if (!pf->mbox_pfvf) 580 return -ENOMEM; 581 582 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 583 WQ_UNBOUND | WQ_HIGHPRI | 584 WQ_MEM_RECLAIM, 1); 585 if (!pf->mbox_pfvf_wq) 586 return -ENOMEM; 587 588 base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR)); 589 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 590 591 if (!hwbase) { 592 err = -ENOMEM; 593 goto free_wq; 594 } 595 596 mbox = &pf->mbox_pfvf[0]; 597 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 598 MBOX_DIR_PFVF, numvfs); 599 if (err) 600 goto free_iomem; 601 602 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 603 MBOX_DIR_PFVF_UP, numvfs); 604 if (err) 605 goto free_iomem; 606 607 for (vf = 0; vf < numvfs; vf++) { 608 mbox->pfvf = pf; 609 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 610 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 611 mbox++; 612 } 613 614 return 0; 615 616 free_iomem: 617 if (hwbase) 618 iounmap(hwbase); 619 free_wq: 620 destroy_workqueue(pf->mbox_pfvf_wq); 621 return err; 622 } 623 624 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 625 { 626 struct mbox *mbox = &pf->mbox_pfvf[0]; 627 628 if (!mbox) 629 return; 630 631 if (pf->mbox_pfvf_wq) { 632 destroy_workqueue(pf->mbox_pfvf_wq); 633 pf->mbox_pfvf_wq = NULL; 634 } 635 636 if (mbox->mbox.hwbase) 637 iounmap(mbox->mbox.hwbase); 638 639 otx2_mbox_destroy(&mbox->mbox); 640 } 641 642 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 643 { 644 /* Clear PF <=> VF mailbox IRQ */ 645 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 646 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 647 648 /* Enable PF <=> VF mailbox IRQ */ 649 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 650 if (numvfs > 64) { 651 numvfs -= 64; 652 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 653 INTR_MASK(numvfs)); 654 } 655 } 656 657 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 658 { 659 int vector; 660 661 /* Disable PF <=> VF mailbox IRQ */ 662 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 663 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 664 665 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 666 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 667 free_irq(vector, pf); 668 669 if (numvfs > 64) { 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 671 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 672 free_irq(vector, pf); 673 } 674 } 675 676 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 677 { 678 struct otx2_hw *hw = &pf->hw; 679 char *irq_name; 680 int err; 681 682 /* Register MBOX0 interrupt handler */ 683 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 684 if (pf->pcifunc) 685 snprintf(irq_name, NAME_SIZE, 686 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 687 else 688 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 689 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 690 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 691 if (err) { 692 dev_err(pf->dev, 693 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 694 return err; 695 } 696 697 if (numvfs > 64) { 698 /* Register MBOX1 interrupt handler */ 699 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 700 if (pf->pcifunc) 701 snprintf(irq_name, NAME_SIZE, 702 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 703 else 704 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 705 err = request_irq(pci_irq_vector(pf->pdev, 706 RVU_PF_INT_VEC_VFPF_MBOX1), 707 otx2_pfvf_mbox_intr_handler, 708 0, irq_name, pf); 709 if (err) { 710 dev_err(pf->dev, 711 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 712 return err; 713 } 714 } 715 716 otx2_enable_pfvf_mbox_intr(pf, numvfs); 717 718 return 0; 719 } 720 721 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 722 struct mbox_msghdr *msg) 723 { 724 int devid; 725 726 if (msg->id >= MBOX_MSG_MAX) { 727 dev_err(pf->dev, 728 "Mbox msg with unknown ID 0x%x\n", msg->id); 729 return; 730 } 731 732 if (msg->sig != OTX2_MBOX_RSP_SIG) { 733 dev_err(pf->dev, 734 "Mbox msg with wrong signature %x, ID 0x%x\n", 735 msg->sig, msg->id); 736 return; 737 } 738 739 /* message response heading VF */ 740 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 741 if (devid) { 742 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 743 struct delayed_work *dwork; 744 745 switch (msg->id) { 746 case MBOX_MSG_NIX_LF_START_RX: 747 config->intf_down = false; 748 dwork = &config->link_event_work; 749 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 750 break; 751 case MBOX_MSG_NIX_LF_STOP_RX: 752 config->intf_down = true; 753 break; 754 } 755 756 return; 757 } 758 759 switch (msg->id) { 760 case MBOX_MSG_READY: 761 pf->pcifunc = msg->pcifunc; 762 break; 763 case MBOX_MSG_MSIX_OFFSET: 764 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 765 break; 766 case MBOX_MSG_NPA_LF_ALLOC: 767 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 768 break; 769 case MBOX_MSG_NIX_LF_ALLOC: 770 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 771 break; 772 case MBOX_MSG_NIX_TXSCH_ALLOC: 773 mbox_handler_nix_txsch_alloc(pf, 774 (struct nix_txsch_alloc_rsp *)msg); 775 break; 776 case MBOX_MSG_NIX_BP_ENABLE: 777 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 778 break; 779 case MBOX_MSG_CGX_STATS: 780 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 781 break; 782 default: 783 if (msg->rc) 784 dev_err(pf->dev, 785 "Mbox msg response has err %d, ID 0x%x\n", 786 msg->rc, msg->id); 787 break; 788 } 789 } 790 791 static void otx2_pfaf_mbox_handler(struct work_struct *work) 792 { 793 struct otx2_mbox_dev *mdev; 794 struct mbox_hdr *rsp_hdr; 795 struct mbox_msghdr *msg; 796 struct otx2_mbox *mbox; 797 struct mbox *af_mbox; 798 struct otx2_nic *pf; 799 int offset, id; 800 801 af_mbox = container_of(work, struct mbox, mbox_wrk); 802 mbox = &af_mbox->mbox; 803 mdev = &mbox->dev[0]; 804 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 805 806 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 807 pf = af_mbox->pfvf; 808 809 for (id = 0; id < af_mbox->num_msgs; id++) { 810 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 811 otx2_process_pfaf_mbox_msg(pf, msg); 812 offset = mbox->rx_start + msg->next_msgoff; 813 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 814 __otx2_mbox_reset(mbox, 0); 815 mdev->msgs_acked++; 816 } 817 818 } 819 820 static void otx2_handle_link_event(struct otx2_nic *pf) 821 { 822 struct cgx_link_user_info *linfo = &pf->linfo; 823 struct net_device *netdev = pf->netdev; 824 825 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 826 linfo->link_up ? "UP" : "DOWN", linfo->speed, 827 linfo->full_duplex ? "Full" : "Half"); 828 if (linfo->link_up) { 829 netif_carrier_on(netdev); 830 netif_tx_start_all_queues(netdev); 831 } else { 832 netif_tx_stop_all_queues(netdev); 833 netif_carrier_off(netdev); 834 } 835 } 836 837 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 838 struct cgx_link_info_msg *msg, 839 struct msg_rsp *rsp) 840 { 841 int i; 842 843 /* Copy the link info sent by AF */ 844 pf->linfo = msg->link_info; 845 846 /* notify VFs about link event */ 847 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 848 struct otx2_vf_config *config = &pf->vf_configs[i]; 849 struct delayed_work *dwork = &config->link_event_work; 850 851 if (config->intf_down) 852 continue; 853 854 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 855 } 856 857 /* interface has not been fully configured yet */ 858 if (pf->flags & OTX2_FLAG_INTF_DOWN) 859 return 0; 860 861 otx2_handle_link_event(pf); 862 return 0; 863 } 864 865 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 866 struct mbox_msghdr *req) 867 { 868 /* Check if valid, if not reply with a invalid msg */ 869 if (req->sig != OTX2_MBOX_REQ_SIG) { 870 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 871 return -ENODEV; 872 } 873 874 switch (req->id) { 875 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 876 case _id: { \ 877 struct _rsp_type *rsp; \ 878 int err; \ 879 \ 880 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 881 &pf->mbox.mbox_up, 0, \ 882 sizeof(struct _rsp_type)); \ 883 if (!rsp) \ 884 return -ENOMEM; \ 885 \ 886 rsp->hdr.id = _id; \ 887 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 888 rsp->hdr.pcifunc = 0; \ 889 rsp->hdr.rc = 0; \ 890 \ 891 err = otx2_mbox_up_handler_ ## _fn_name( \ 892 pf, (struct _req_type *)req, rsp); \ 893 return err; \ 894 } 895 MBOX_UP_CGX_MESSAGES 896 #undef M 897 break; 898 default: 899 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 900 return -ENODEV; 901 } 902 return 0; 903 } 904 905 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 906 { 907 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 908 struct otx2_mbox *mbox = &af_mbox->mbox_up; 909 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 910 struct otx2_nic *pf = af_mbox->pfvf; 911 int offset, id, devid = 0; 912 struct mbox_hdr *rsp_hdr; 913 struct mbox_msghdr *msg; 914 915 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 916 917 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 918 919 for (id = 0; id < af_mbox->up_num_msgs; id++) { 920 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 921 922 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 923 /* Skip processing VF's messages */ 924 if (!devid) 925 otx2_process_mbox_msg_up(pf, msg); 926 offset = mbox->rx_start + msg->next_msgoff; 927 } 928 if (devid) { 929 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 930 MBOX_DIR_PFVF_UP, devid - 1, 931 af_mbox->up_num_msgs); 932 return; 933 } 934 935 otx2_mbox_msg_send(mbox, 0); 936 } 937 938 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 939 { 940 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 941 struct mbox *mbox; 942 943 /* Clear the IRQ */ 944 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 945 946 mbox = &pf->mbox; 947 948 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 949 950 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 951 952 return IRQ_HANDLED; 953 } 954 955 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 956 { 957 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 958 959 /* Disable AF => PF mailbox IRQ */ 960 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 961 free_irq(vector, pf); 962 } 963 964 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 965 { 966 struct otx2_hw *hw = &pf->hw; 967 struct msg_req *req; 968 char *irq_name; 969 int err; 970 971 /* Register mailbox interrupt handler */ 972 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 973 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 974 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 975 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 976 if (err) { 977 dev_err(pf->dev, 978 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 979 return err; 980 } 981 982 /* Enable mailbox interrupt for msgs coming from AF. 983 * First clear to avoid spurious interrupts, if any. 984 */ 985 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 986 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 987 988 if (!probe_af) 989 return 0; 990 991 /* Check mailbox communication with AF */ 992 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 993 if (!req) { 994 otx2_disable_mbox_intr(pf); 995 return -ENOMEM; 996 } 997 err = otx2_sync_mbox_msg(&pf->mbox); 998 if (err) { 999 dev_warn(pf->dev, 1000 "AF not responding to mailbox, deferring probe\n"); 1001 otx2_disable_mbox_intr(pf); 1002 return -EPROBE_DEFER; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1009 { 1010 struct mbox *mbox = &pf->mbox; 1011 1012 if (pf->mbox_wq) { 1013 destroy_workqueue(pf->mbox_wq); 1014 pf->mbox_wq = NULL; 1015 } 1016 1017 if (mbox->mbox.hwbase) 1018 iounmap((void __iomem *)mbox->mbox.hwbase); 1019 1020 otx2_mbox_destroy(&mbox->mbox); 1021 otx2_mbox_destroy(&mbox->mbox_up); 1022 } 1023 1024 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1025 { 1026 struct mbox *mbox = &pf->mbox; 1027 void __iomem *hwbase; 1028 int err; 1029 1030 mbox->pfvf = pf; 1031 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1032 WQ_UNBOUND | WQ_HIGHPRI | 1033 WQ_MEM_RECLAIM, 1); 1034 if (!pf->mbox_wq) 1035 return -ENOMEM; 1036 1037 /* Mailbox is a reserved memory (in RAM) region shared between 1038 * admin function (i.e AF) and this PF, shouldn't be mapped as 1039 * device memory to allow unaligned accesses. 1040 */ 1041 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1042 pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM)); 1043 if (!hwbase) { 1044 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1045 err = -ENOMEM; 1046 goto exit; 1047 } 1048 1049 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1050 MBOX_DIR_PFAF, 1); 1051 if (err) 1052 goto exit; 1053 1054 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1055 MBOX_DIR_PFAF_UP, 1); 1056 if (err) 1057 goto exit; 1058 1059 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1060 if (err) 1061 goto exit; 1062 1063 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1064 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1065 mutex_init(&mbox->lock); 1066 1067 return 0; 1068 exit: 1069 otx2_pfaf_mbox_destroy(pf); 1070 return err; 1071 } 1072 1073 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1074 { 1075 struct msg_req *msg; 1076 int err; 1077 1078 mutex_lock(&pf->mbox.lock); 1079 if (enable) 1080 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1081 else 1082 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1083 1084 if (!msg) { 1085 mutex_unlock(&pf->mbox.lock); 1086 return -ENOMEM; 1087 } 1088 1089 err = otx2_sync_mbox_msg(&pf->mbox); 1090 mutex_unlock(&pf->mbox.lock); 1091 return err; 1092 } 1093 1094 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1095 { 1096 struct msg_req *msg; 1097 int err; 1098 1099 mutex_lock(&pf->mbox.lock); 1100 if (enable) 1101 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1102 else 1103 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1104 1105 if (!msg) { 1106 mutex_unlock(&pf->mbox.lock); 1107 return -ENOMEM; 1108 } 1109 1110 err = otx2_sync_mbox_msg(&pf->mbox); 1111 mutex_unlock(&pf->mbox.lock); 1112 return err; 1113 } 1114 1115 int otx2_set_real_num_queues(struct net_device *netdev, 1116 int tx_queues, int rx_queues) 1117 { 1118 int err; 1119 1120 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1121 if (err) { 1122 netdev_err(netdev, 1123 "Failed to set no of Tx queues: %d\n", tx_queues); 1124 return err; 1125 } 1126 1127 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1128 if (err) 1129 netdev_err(netdev, 1130 "Failed to set no of Rx queues: %d\n", rx_queues); 1131 return err; 1132 } 1133 EXPORT_SYMBOL(otx2_set_real_num_queues); 1134 1135 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1136 { 1137 struct otx2_nic *pf = data; 1138 u64 val, *ptr; 1139 u64 qidx = 0; 1140 1141 /* CQ */ 1142 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1143 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1144 val = otx2_atomic64_add((qidx << 44), ptr); 1145 1146 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1147 (val & NIX_CQERRINT_BITS)); 1148 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1149 continue; 1150 1151 if (val & BIT_ULL(42)) { 1152 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1153 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1154 } else { 1155 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1156 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1157 qidx); 1158 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1159 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1160 qidx); 1161 } 1162 1163 schedule_work(&pf->reset_task); 1164 } 1165 1166 /* SQ */ 1167 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1168 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1169 val = otx2_atomic64_add((qidx << 44), ptr); 1170 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1171 (val & NIX_SQINT_BITS)); 1172 1173 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1174 continue; 1175 1176 if (val & BIT_ULL(42)) { 1177 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1178 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1179 } else { 1180 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1181 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1182 qidx, 1183 otx2_read64(pf, 1184 NIX_LF_SQ_OP_ERR_DBG)); 1185 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1186 BIT_ULL(44)); 1187 } 1188 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1189 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1190 qidx, 1191 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1192 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1193 BIT_ULL(44)); 1194 } 1195 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1196 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1197 qidx, 1198 otx2_read64(pf, 1199 NIX_LF_SEND_ERR_DBG)); 1200 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1201 BIT_ULL(44)); 1202 } 1203 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1204 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1205 qidx); 1206 } 1207 1208 schedule_work(&pf->reset_task); 1209 } 1210 1211 return IRQ_HANDLED; 1212 } 1213 1214 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1215 { 1216 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1217 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1218 int qidx = cq_poll->cint_idx; 1219 1220 /* Disable interrupts. 1221 * 1222 * Completion interrupts behave in a level-triggered interrupt 1223 * fashion, and hence have to be cleared only after it is serviced. 1224 */ 1225 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1226 1227 /* Schedule NAPI */ 1228 napi_schedule_irqoff(&cq_poll->napi); 1229 1230 return IRQ_HANDLED; 1231 } 1232 1233 static void otx2_disable_napi(struct otx2_nic *pf) 1234 { 1235 struct otx2_qset *qset = &pf->qset; 1236 struct otx2_cq_poll *cq_poll; 1237 int qidx; 1238 1239 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1240 cq_poll = &qset->napi[qidx]; 1241 napi_disable(&cq_poll->napi); 1242 netif_napi_del(&cq_poll->napi); 1243 } 1244 } 1245 1246 static void otx2_free_cq_res(struct otx2_nic *pf) 1247 { 1248 struct otx2_qset *qset = &pf->qset; 1249 struct otx2_cq_queue *cq; 1250 int qidx; 1251 1252 /* Disable CQs */ 1253 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1254 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1255 cq = &qset->cq[qidx]; 1256 qmem_free(pf->dev, cq->cqe); 1257 } 1258 } 1259 1260 static void otx2_free_sq_res(struct otx2_nic *pf) 1261 { 1262 struct otx2_qset *qset = &pf->qset; 1263 struct otx2_snd_queue *sq; 1264 int qidx; 1265 1266 /* Disable SQs */ 1267 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1268 /* Free SQB pointers */ 1269 otx2_sq_free_sqbs(pf); 1270 for (qidx = 0; qidx < pf->hw.tx_queues; qidx++) { 1271 sq = &qset->sq[qidx]; 1272 qmem_free(pf->dev, sq->sqe); 1273 qmem_free(pf->dev, sq->tso_hdrs); 1274 kfree(sq->sg); 1275 kfree(sq->sqb_ptrs); 1276 } 1277 } 1278 1279 static int otx2_init_hw_resources(struct otx2_nic *pf) 1280 { 1281 struct nix_lf_free_req *free_req; 1282 struct mbox *mbox = &pf->mbox; 1283 struct otx2_hw *hw = &pf->hw; 1284 struct msg_req *req; 1285 int err = 0, lvl; 1286 1287 /* Set required NPA LF's pool counts 1288 * Auras and Pools are used in a 1:1 mapping, 1289 * so, aura count = pool count. 1290 */ 1291 hw->rqpool_cnt = hw->rx_queues; 1292 hw->sqpool_cnt = hw->tx_queues; 1293 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1294 1295 /* Get the size of receive buffers to allocate */ 1296 pf->rbsize = RCV_FRAG_LEN(OTX2_HW_TIMESTAMP_LEN + pf->netdev->mtu + 1297 OTX2_ETH_HLEN); 1298 1299 mutex_lock(&mbox->lock); 1300 /* NPA init */ 1301 err = otx2_config_npa(pf); 1302 if (err) 1303 goto exit; 1304 1305 /* NIX init */ 1306 err = otx2_config_nix(pf); 1307 if (err) 1308 goto err_free_npa_lf; 1309 1310 /* Enable backpressure */ 1311 otx2_nix_config_bp(pf, true); 1312 1313 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1314 err = otx2_rq_aura_pool_init(pf); 1315 if (err) { 1316 mutex_unlock(&mbox->lock); 1317 goto err_free_nix_lf; 1318 } 1319 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1320 err = otx2_sq_aura_pool_init(pf); 1321 if (err) { 1322 mutex_unlock(&mbox->lock); 1323 goto err_free_rq_ptrs; 1324 } 1325 1326 err = otx2_txsch_alloc(pf); 1327 if (err) { 1328 mutex_unlock(&mbox->lock); 1329 goto err_free_sq_ptrs; 1330 } 1331 1332 err = otx2_config_nix_queues(pf); 1333 if (err) { 1334 mutex_unlock(&mbox->lock); 1335 goto err_free_txsch; 1336 } 1337 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1338 err = otx2_txschq_config(pf, lvl); 1339 if (err) { 1340 mutex_unlock(&mbox->lock); 1341 goto err_free_nix_queues; 1342 } 1343 } 1344 mutex_unlock(&mbox->lock); 1345 return err; 1346 1347 err_free_nix_queues: 1348 otx2_free_sq_res(pf); 1349 otx2_free_cq_res(pf); 1350 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1351 err_free_txsch: 1352 if (otx2_txschq_stop(pf)) 1353 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1354 err_free_sq_ptrs: 1355 otx2_sq_free_sqbs(pf); 1356 err_free_rq_ptrs: 1357 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1358 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1359 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1360 otx2_aura_pool_free(pf); 1361 err_free_nix_lf: 1362 mutex_lock(&mbox->lock); 1363 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1364 if (free_req) { 1365 free_req->flags = NIX_LF_DISABLE_FLOWS; 1366 if (otx2_sync_mbox_msg(mbox)) 1367 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1368 } 1369 err_free_npa_lf: 1370 /* Reset NPA LF */ 1371 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1372 if (req) { 1373 if (otx2_sync_mbox_msg(mbox)) 1374 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1375 } 1376 exit: 1377 mutex_unlock(&mbox->lock); 1378 return err; 1379 } 1380 1381 static void otx2_free_hw_resources(struct otx2_nic *pf) 1382 { 1383 struct otx2_qset *qset = &pf->qset; 1384 struct nix_lf_free_req *free_req; 1385 struct mbox *mbox = &pf->mbox; 1386 struct otx2_cq_queue *cq; 1387 struct msg_req *req; 1388 int qidx, err; 1389 1390 /* Ensure all SQE are processed */ 1391 otx2_sqb_flush(pf); 1392 1393 /* Stop transmission */ 1394 err = otx2_txschq_stop(pf); 1395 if (err) 1396 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1397 1398 mutex_lock(&mbox->lock); 1399 /* Disable backpressure */ 1400 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1401 otx2_nix_config_bp(pf, false); 1402 mutex_unlock(&mbox->lock); 1403 1404 /* Disable RQs */ 1405 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1406 1407 /*Dequeue all CQEs */ 1408 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1409 cq = &qset->cq[qidx]; 1410 if (cq->cq_type == CQ_RX) 1411 otx2_cleanup_rx_cqes(pf, cq); 1412 else 1413 otx2_cleanup_tx_cqes(pf, cq); 1414 } 1415 1416 otx2_free_sq_res(pf); 1417 1418 /* Free RQ buffer pointers*/ 1419 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1420 1421 otx2_free_cq_res(pf); 1422 1423 mutex_lock(&mbox->lock); 1424 /* Reset NIX LF */ 1425 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1426 if (free_req) { 1427 free_req->flags = NIX_LF_DISABLE_FLOWS; 1428 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1429 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1430 if (otx2_sync_mbox_msg(mbox)) 1431 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1432 } 1433 mutex_unlock(&mbox->lock); 1434 1435 /* Disable NPA Pool and Aura hw context */ 1436 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1437 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1438 otx2_aura_pool_free(pf); 1439 1440 mutex_lock(&mbox->lock); 1441 /* Reset NPA LF */ 1442 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1443 if (req) { 1444 if (otx2_sync_mbox_msg(mbox)) 1445 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1446 } 1447 mutex_unlock(&mbox->lock); 1448 } 1449 1450 int otx2_open(struct net_device *netdev) 1451 { 1452 struct otx2_nic *pf = netdev_priv(netdev); 1453 struct otx2_cq_poll *cq_poll = NULL; 1454 struct otx2_qset *qset = &pf->qset; 1455 int err = 0, qidx, vec; 1456 char *irq_name; 1457 1458 netif_carrier_off(netdev); 1459 1460 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues; 1461 /* RQ and SQs are mapped to different CQs, 1462 * so find out max CQ IRQs (i.e CINTs) needed. 1463 */ 1464 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1465 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1466 if (!qset->napi) 1467 return -ENOMEM; 1468 1469 /* CQ size of RQ */ 1470 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1471 /* CQ size of SQ */ 1472 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1473 1474 err = -ENOMEM; 1475 qset->cq = kcalloc(pf->qset.cq_cnt, 1476 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1477 if (!qset->cq) 1478 goto err_free_mem; 1479 1480 qset->sq = kcalloc(pf->hw.tx_queues, 1481 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1482 if (!qset->sq) 1483 goto err_free_mem; 1484 1485 qset->rq = kcalloc(pf->hw.rx_queues, 1486 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1487 if (!qset->rq) 1488 goto err_free_mem; 1489 1490 err = otx2_init_hw_resources(pf); 1491 if (err) 1492 goto err_free_mem; 1493 1494 /* Register NAPI handler */ 1495 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1496 cq_poll = &qset->napi[qidx]; 1497 cq_poll->cint_idx = qidx; 1498 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1499 * 'cq_ids[0]' points to RQ's CQ and 1500 * 'cq_ids[1]' points to SQ's CQ and 1501 */ 1502 cq_poll->cq_ids[CQ_RX] = 1503 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1504 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1505 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1506 cq_poll->dev = (void *)pf; 1507 netif_napi_add(netdev, &cq_poll->napi, 1508 otx2_napi_handler, NAPI_POLL_WEIGHT); 1509 napi_enable(&cq_poll->napi); 1510 } 1511 1512 /* Set maximum frame size allowed in HW */ 1513 err = otx2_hw_set_mtu(pf, netdev->mtu); 1514 if (err) 1515 goto err_disable_napi; 1516 1517 /* Setup segmentation algorithms, if failed, clear offload capability */ 1518 otx2_setup_segmentation(pf); 1519 1520 /* Initialize RSS */ 1521 err = otx2_rss_init(pf); 1522 if (err) 1523 goto err_disable_napi; 1524 1525 /* Register Queue IRQ handlers */ 1526 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1527 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1528 1529 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1530 1531 err = request_irq(pci_irq_vector(pf->pdev, vec), 1532 otx2_q_intr_handler, 0, irq_name, pf); 1533 if (err) { 1534 dev_err(pf->dev, 1535 "RVUPF%d: IRQ registration failed for QERR\n", 1536 rvu_get_pf(pf->pcifunc)); 1537 goto err_disable_napi; 1538 } 1539 1540 /* Enable QINT IRQ */ 1541 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1542 1543 /* Register CQ IRQ handlers */ 1544 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1545 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1546 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1547 1548 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1549 qidx); 1550 1551 err = request_irq(pci_irq_vector(pf->pdev, vec), 1552 otx2_cq_intr_handler, 0, irq_name, 1553 &qset->napi[qidx]); 1554 if (err) { 1555 dev_err(pf->dev, 1556 "RVUPF%d: IRQ registration failed for CQ%d\n", 1557 rvu_get_pf(pf->pcifunc), qidx); 1558 goto err_free_cints; 1559 } 1560 vec++; 1561 1562 otx2_config_irq_coalescing(pf, qidx); 1563 1564 /* Enable CQ IRQ */ 1565 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1566 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1567 } 1568 1569 otx2_set_cints_affinity(pf); 1570 1571 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1572 otx2_enable_rxvlan(pf, true); 1573 1574 /* When reinitializing enable time stamping if it is enabled before */ 1575 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1576 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1577 otx2_config_hw_tx_tstamp(pf, true); 1578 } 1579 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1580 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1581 otx2_config_hw_rx_tstamp(pf, true); 1582 } 1583 1584 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1585 /* 'intf_down' may be checked on any cpu */ 1586 smp_wmb(); 1587 1588 /* we have already received link status notification */ 1589 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1590 otx2_handle_link_event(pf); 1591 1592 /* Restore pause frame settings */ 1593 otx2_config_pause_frm(pf); 1594 1595 err = otx2_rxtx_enable(pf, true); 1596 if (err) 1597 goto err_tx_stop_queues; 1598 1599 return 0; 1600 1601 err_tx_stop_queues: 1602 netif_tx_stop_all_queues(netdev); 1603 netif_carrier_off(netdev); 1604 err_free_cints: 1605 otx2_free_cints(pf, qidx); 1606 vec = pci_irq_vector(pf->pdev, 1607 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1608 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1609 synchronize_irq(vec); 1610 free_irq(vec, pf); 1611 err_disable_napi: 1612 otx2_disable_napi(pf); 1613 otx2_free_hw_resources(pf); 1614 err_free_mem: 1615 kfree(qset->sq); 1616 kfree(qset->cq); 1617 kfree(qset->rq); 1618 kfree(qset->napi); 1619 return err; 1620 } 1621 EXPORT_SYMBOL(otx2_open); 1622 1623 int otx2_stop(struct net_device *netdev) 1624 { 1625 struct otx2_nic *pf = netdev_priv(netdev); 1626 struct otx2_cq_poll *cq_poll = NULL; 1627 struct otx2_qset *qset = &pf->qset; 1628 int qidx, vec, wrk; 1629 1630 netif_carrier_off(netdev); 1631 netif_tx_stop_all_queues(netdev); 1632 1633 pf->flags |= OTX2_FLAG_INTF_DOWN; 1634 /* 'intf_down' may be checked on any cpu */ 1635 smp_wmb(); 1636 1637 /* First stop packet Rx/Tx */ 1638 otx2_rxtx_enable(pf, false); 1639 1640 /* Cleanup Queue IRQ */ 1641 vec = pci_irq_vector(pf->pdev, 1642 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1643 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1644 synchronize_irq(vec); 1645 free_irq(vec, pf); 1646 1647 /* Cleanup CQ NAPI and IRQ */ 1648 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1649 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1650 /* Disable interrupt */ 1651 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1652 1653 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1654 1655 cq_poll = &qset->napi[qidx]; 1656 napi_synchronize(&cq_poll->napi); 1657 vec++; 1658 } 1659 1660 netif_tx_disable(netdev); 1661 1662 otx2_free_hw_resources(pf); 1663 otx2_free_cints(pf, pf->hw.cint_cnt); 1664 otx2_disable_napi(pf); 1665 1666 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1667 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1668 1669 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1670 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1671 devm_kfree(pf->dev, pf->refill_wrk); 1672 1673 kfree(qset->sq); 1674 kfree(qset->cq); 1675 kfree(qset->rq); 1676 kfree(qset->napi); 1677 /* Do not clear RQ/SQ ringsize settings */ 1678 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1679 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1680 return 0; 1681 } 1682 EXPORT_SYMBOL(otx2_stop); 1683 1684 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1685 { 1686 struct otx2_nic *pf = netdev_priv(netdev); 1687 int qidx = skb_get_queue_mapping(skb); 1688 struct otx2_snd_queue *sq; 1689 struct netdev_queue *txq; 1690 1691 /* Check for minimum and maximum packet length */ 1692 if (skb->len <= ETH_HLEN || 1693 (!skb_shinfo(skb)->gso_size && skb->len > pf->max_frs)) { 1694 dev_kfree_skb(skb); 1695 return NETDEV_TX_OK; 1696 } 1697 1698 sq = &pf->qset.sq[qidx]; 1699 txq = netdev_get_tx_queue(netdev, qidx); 1700 1701 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1702 netif_tx_stop_queue(txq); 1703 1704 /* Check again, incase SQBs got freed up */ 1705 smp_mb(); 1706 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1707 > sq->sqe_thresh) 1708 netif_tx_wake_queue(txq); 1709 1710 return NETDEV_TX_BUSY; 1711 } 1712 1713 return NETDEV_TX_OK; 1714 } 1715 1716 static void otx2_set_rx_mode(struct net_device *netdev) 1717 { 1718 struct otx2_nic *pf = netdev_priv(netdev); 1719 1720 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1721 } 1722 1723 static void otx2_do_set_rx_mode(struct work_struct *work) 1724 { 1725 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1726 struct net_device *netdev = pf->netdev; 1727 struct nix_rx_mode *req; 1728 bool promisc = false; 1729 1730 if (!(netdev->flags & IFF_UP)) 1731 return; 1732 1733 if ((netdev->flags & IFF_PROMISC) || 1734 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1735 promisc = true; 1736 } 1737 1738 /* Write unicast address to mcam entries or del from mcam */ 1739 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1740 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1741 1742 mutex_lock(&pf->mbox.lock); 1743 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1744 if (!req) { 1745 mutex_unlock(&pf->mbox.lock); 1746 return; 1747 } 1748 1749 req->mode = NIX_RX_MODE_UCAST; 1750 1751 if (promisc) 1752 req->mode |= NIX_RX_MODE_PROMISC; 1753 else if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1754 req->mode |= NIX_RX_MODE_ALLMULTI; 1755 1756 otx2_sync_mbox_msg(&pf->mbox); 1757 mutex_unlock(&pf->mbox.lock); 1758 } 1759 1760 static int otx2_set_features(struct net_device *netdev, 1761 netdev_features_t features) 1762 { 1763 netdev_features_t changed = features ^ netdev->features; 1764 bool ntuple = !!(features & NETIF_F_NTUPLE); 1765 struct otx2_nic *pf = netdev_priv(netdev); 1766 1767 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1768 return otx2_cgx_config_loopback(pf, 1769 features & NETIF_F_LOOPBACK); 1770 1771 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1772 return otx2_enable_rxvlan(pf, 1773 features & NETIF_F_HW_VLAN_CTAG_RX); 1774 1775 if ((changed & NETIF_F_NTUPLE) && !ntuple) 1776 otx2_destroy_ntuple_flows(pf); 1777 1778 return 0; 1779 } 1780 1781 static void otx2_reset_task(struct work_struct *work) 1782 { 1783 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1784 1785 if (!netif_running(pf->netdev)) 1786 return; 1787 1788 rtnl_lock(); 1789 otx2_stop(pf->netdev); 1790 pf->reset_count++; 1791 otx2_open(pf->netdev); 1792 netif_trans_update(pf->netdev); 1793 rtnl_unlock(); 1794 } 1795 1796 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1797 { 1798 struct msg_req *req; 1799 int err; 1800 1801 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1802 return 0; 1803 1804 mutex_lock(&pfvf->mbox.lock); 1805 if (enable) 1806 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1807 else 1808 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1809 if (!req) { 1810 mutex_unlock(&pfvf->mbox.lock); 1811 return -ENOMEM; 1812 } 1813 1814 err = otx2_sync_mbox_msg(&pfvf->mbox); 1815 if (err) { 1816 mutex_unlock(&pfvf->mbox.lock); 1817 return err; 1818 } 1819 1820 mutex_unlock(&pfvf->mbox.lock); 1821 if (enable) 1822 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1823 else 1824 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1825 return 0; 1826 } 1827 1828 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1829 { 1830 struct msg_req *req; 1831 int err; 1832 1833 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1834 return 0; 1835 1836 mutex_lock(&pfvf->mbox.lock); 1837 if (enable) 1838 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1839 else 1840 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1841 if (!req) { 1842 mutex_unlock(&pfvf->mbox.lock); 1843 return -ENOMEM; 1844 } 1845 1846 err = otx2_sync_mbox_msg(&pfvf->mbox); 1847 if (err) { 1848 mutex_unlock(&pfvf->mbox.lock); 1849 return err; 1850 } 1851 1852 mutex_unlock(&pfvf->mbox.lock); 1853 if (enable) 1854 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1855 else 1856 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1857 return 0; 1858 } 1859 1860 static int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1861 { 1862 struct otx2_nic *pfvf = netdev_priv(netdev); 1863 struct hwtstamp_config config; 1864 1865 if (!pfvf->ptp) 1866 return -ENODEV; 1867 1868 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1869 return -EFAULT; 1870 1871 /* reserved for future extensions */ 1872 if (config.flags) 1873 return -EINVAL; 1874 1875 switch (config.tx_type) { 1876 case HWTSTAMP_TX_OFF: 1877 otx2_config_hw_tx_tstamp(pfvf, false); 1878 break; 1879 case HWTSTAMP_TX_ON: 1880 otx2_config_hw_tx_tstamp(pfvf, true); 1881 break; 1882 default: 1883 return -ERANGE; 1884 } 1885 1886 switch (config.rx_filter) { 1887 case HWTSTAMP_FILTER_NONE: 1888 otx2_config_hw_rx_tstamp(pfvf, false); 1889 break; 1890 case HWTSTAMP_FILTER_ALL: 1891 case HWTSTAMP_FILTER_SOME: 1892 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1893 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1894 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1895 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1896 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1897 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1898 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1899 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1900 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1901 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1902 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1903 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1904 otx2_config_hw_rx_tstamp(pfvf, true); 1905 config.rx_filter = HWTSTAMP_FILTER_ALL; 1906 break; 1907 default: 1908 return -ERANGE; 1909 } 1910 1911 memcpy(&pfvf->tstamp, &config, sizeof(config)); 1912 1913 return copy_to_user(ifr->ifr_data, &config, 1914 sizeof(config)) ? -EFAULT : 0; 1915 } 1916 1917 static int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 1918 { 1919 struct otx2_nic *pfvf = netdev_priv(netdev); 1920 struct hwtstamp_config *cfg = &pfvf->tstamp; 1921 1922 switch (cmd) { 1923 case SIOCSHWTSTAMP: 1924 return otx2_config_hwtstamp(netdev, req); 1925 case SIOCGHWTSTAMP: 1926 return copy_to_user(req->ifr_data, cfg, 1927 sizeof(*cfg)) ? -EFAULT : 0; 1928 default: 1929 return -EOPNOTSUPP; 1930 } 1931 } 1932 1933 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 1934 { 1935 struct npc_install_flow_req *req; 1936 int err; 1937 1938 mutex_lock(&pf->mbox.lock); 1939 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 1940 if (!req) { 1941 err = -ENOMEM; 1942 goto out; 1943 } 1944 1945 ether_addr_copy(req->packet.dmac, mac); 1946 eth_broadcast_addr((u8 *)&req->mask.dmac); 1947 req->features = BIT_ULL(NPC_DMAC); 1948 req->channel = pf->hw.rx_chan_base; 1949 req->intf = NIX_INTF_RX; 1950 req->default_rule = 1; 1951 req->append = 1; 1952 req->vf = vf + 1; 1953 req->op = NIX_RX_ACTION_DEFAULT; 1954 1955 err = otx2_sync_mbox_msg(&pf->mbox); 1956 out: 1957 mutex_unlock(&pf->mbox.lock); 1958 return err; 1959 } 1960 1961 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1962 { 1963 struct otx2_nic *pf = netdev_priv(netdev); 1964 struct pci_dev *pdev = pf->pdev; 1965 struct otx2_vf_config *config; 1966 int ret; 1967 1968 if (!netif_running(netdev)) 1969 return -EAGAIN; 1970 1971 if (vf >= pci_num_vf(pdev)) 1972 return -EINVAL; 1973 1974 if (!is_valid_ether_addr(mac)) 1975 return -EINVAL; 1976 1977 config = &pf->vf_configs[vf]; 1978 ether_addr_copy(config->mac, mac); 1979 1980 ret = otx2_do_set_vf_mac(pf, vf, mac); 1981 if (ret == 0) 1982 dev_info(&pdev->dev, "Reload VF driver to apply the changes\n"); 1983 1984 return ret; 1985 } 1986 1987 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 1988 __be16 proto) 1989 { 1990 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 1991 struct nix_vtag_config_rsp *vtag_rsp; 1992 struct npc_delete_flow_req *del_req; 1993 struct nix_vtag_config *vtag_req; 1994 struct npc_install_flow_req *req; 1995 struct otx2_vf_config *config; 1996 int err = 0; 1997 u32 idx; 1998 1999 config = &pf->vf_configs[vf]; 2000 2001 if (!vlan && !config->vlan) 2002 goto out; 2003 2004 mutex_lock(&pf->mbox.lock); 2005 2006 /* free old tx vtag entry */ 2007 if (config->vlan) { 2008 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2009 if (!vtag_req) { 2010 err = -ENOMEM; 2011 goto out; 2012 } 2013 vtag_req->cfg_type = 0; 2014 vtag_req->tx.free_vtag0 = 1; 2015 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2016 2017 err = otx2_sync_mbox_msg(&pf->mbox); 2018 if (err) 2019 goto out; 2020 } 2021 2022 if (!vlan && config->vlan) { 2023 /* rx */ 2024 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2025 if (!del_req) { 2026 err = -ENOMEM; 2027 goto out; 2028 } 2029 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2030 del_req->entry = 2031 flow_cfg->entry[flow_cfg->vf_vlan_offset + idx]; 2032 err = otx2_sync_mbox_msg(&pf->mbox); 2033 if (err) 2034 goto out; 2035 2036 /* tx */ 2037 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2038 if (!del_req) { 2039 err = -ENOMEM; 2040 goto out; 2041 } 2042 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2043 del_req->entry = 2044 flow_cfg->entry[flow_cfg->vf_vlan_offset + idx]; 2045 err = otx2_sync_mbox_msg(&pf->mbox); 2046 2047 goto out; 2048 } 2049 2050 /* rx */ 2051 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2052 if (!req) { 2053 err = -ENOMEM; 2054 goto out; 2055 } 2056 2057 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2058 req->entry = flow_cfg->entry[flow_cfg->vf_vlan_offset + idx]; 2059 req->packet.vlan_tci = htons(vlan); 2060 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2061 /* af fills the destination mac addr */ 2062 eth_broadcast_addr((u8 *)&req->mask.dmac); 2063 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2064 req->channel = pf->hw.rx_chan_base; 2065 req->intf = NIX_INTF_RX; 2066 req->vf = vf + 1; 2067 req->op = NIX_RX_ACTION_DEFAULT; 2068 req->vtag0_valid = true; 2069 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2070 req->set_cntr = 1; 2071 2072 err = otx2_sync_mbox_msg(&pf->mbox); 2073 if (err) 2074 goto out; 2075 2076 /* tx */ 2077 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2078 if (!vtag_req) { 2079 err = -ENOMEM; 2080 goto out; 2081 } 2082 2083 /* configure tx vtag params */ 2084 vtag_req->vtag_size = VTAGSIZE_T4; 2085 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2086 vtag_req->tx.cfg_vtag0 = 1; 2087 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2088 2089 err = otx2_sync_mbox_msg(&pf->mbox); 2090 if (err) 2091 goto out; 2092 2093 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2094 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2095 if (IS_ERR(vtag_rsp)) { 2096 err = PTR_ERR(vtag_rsp); 2097 goto out; 2098 } 2099 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2100 2101 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2102 if (!req) { 2103 err = -ENOMEM; 2104 goto out; 2105 } 2106 2107 eth_zero_addr((u8 *)&req->mask.dmac); 2108 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2109 req->entry = flow_cfg->entry[flow_cfg->vf_vlan_offset + idx]; 2110 req->features = BIT_ULL(NPC_DMAC); 2111 req->channel = pf->hw.tx_chan_base; 2112 req->intf = NIX_INTF_TX; 2113 req->vf = vf + 1; 2114 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2115 req->vtag0_def = vtag_rsp->vtag0_idx; 2116 req->vtag0_op = VTAG_INSERT; 2117 req->set_cntr = 1; 2118 2119 err = otx2_sync_mbox_msg(&pf->mbox); 2120 out: 2121 config->vlan = vlan; 2122 mutex_unlock(&pf->mbox.lock); 2123 return err; 2124 } 2125 2126 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2127 __be16 proto) 2128 { 2129 struct otx2_nic *pf = netdev_priv(netdev); 2130 struct pci_dev *pdev = pf->pdev; 2131 2132 if (!netif_running(netdev)) 2133 return -EAGAIN; 2134 2135 if (vf >= pci_num_vf(pdev)) 2136 return -EINVAL; 2137 2138 /* qos is currently unsupported */ 2139 if (vlan >= VLAN_N_VID || qos) 2140 return -EINVAL; 2141 2142 if (proto != htons(ETH_P_8021Q)) 2143 return -EPROTONOSUPPORT; 2144 2145 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2146 return -EOPNOTSUPP; 2147 2148 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2149 } 2150 2151 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2152 struct ifla_vf_info *ivi) 2153 { 2154 struct otx2_nic *pf = netdev_priv(netdev); 2155 struct pci_dev *pdev = pf->pdev; 2156 struct otx2_vf_config *config; 2157 2158 if (!netif_running(netdev)) 2159 return -EAGAIN; 2160 2161 if (vf >= pci_num_vf(pdev)) 2162 return -EINVAL; 2163 2164 config = &pf->vf_configs[vf]; 2165 ivi->vf = vf; 2166 ether_addr_copy(ivi->mac, config->mac); 2167 ivi->vlan = config->vlan; 2168 2169 return 0; 2170 } 2171 2172 static const struct net_device_ops otx2_netdev_ops = { 2173 .ndo_open = otx2_open, 2174 .ndo_stop = otx2_stop, 2175 .ndo_start_xmit = otx2_xmit, 2176 .ndo_set_mac_address = otx2_set_mac_address, 2177 .ndo_change_mtu = otx2_change_mtu, 2178 .ndo_set_rx_mode = otx2_set_rx_mode, 2179 .ndo_set_features = otx2_set_features, 2180 .ndo_tx_timeout = otx2_tx_timeout, 2181 .ndo_get_stats64 = otx2_get_stats64, 2182 .ndo_do_ioctl = otx2_ioctl, 2183 .ndo_set_vf_mac = otx2_set_vf_mac, 2184 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2185 .ndo_get_vf_config = otx2_get_vf_config, 2186 }; 2187 2188 static int otx2_wq_init(struct otx2_nic *pf) 2189 { 2190 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2191 if (!pf->otx2_wq) 2192 return -ENOMEM; 2193 2194 INIT_WORK(&pf->rx_mode_work, otx2_do_set_rx_mode); 2195 INIT_WORK(&pf->reset_task, otx2_reset_task); 2196 return 0; 2197 } 2198 2199 static int otx2_check_pf_usable(struct otx2_nic *nic) 2200 { 2201 u64 rev; 2202 2203 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2204 rev = (rev >> 12) & 0xFF; 2205 /* Check if AF has setup revision for RVUM block, 2206 * otherwise this driver probe should be deferred 2207 * until AF driver comes up. 2208 */ 2209 if (!rev) { 2210 dev_warn(nic->dev, 2211 "AF is not initialized, deferring probe\n"); 2212 return -EPROBE_DEFER; 2213 } 2214 return 0; 2215 } 2216 2217 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2218 { 2219 struct otx2_hw *hw = &pf->hw; 2220 int num_vec, err; 2221 2222 /* NPA interrupts are inot registered, so alloc only 2223 * upto NIX vector offset. 2224 */ 2225 num_vec = hw->nix_msixoff; 2226 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2227 2228 otx2_disable_mbox_intr(pf); 2229 pci_free_irq_vectors(hw->pdev); 2230 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2231 if (err < 0) { 2232 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2233 __func__, num_vec); 2234 return err; 2235 } 2236 2237 return otx2_register_mbox_intr(pf, false); 2238 } 2239 2240 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2241 { 2242 struct device *dev = &pdev->dev; 2243 struct net_device *netdev; 2244 struct otx2_nic *pf; 2245 struct otx2_hw *hw; 2246 int err, qcount; 2247 int num_vec; 2248 2249 err = pcim_enable_device(pdev); 2250 if (err) { 2251 dev_err(dev, "Failed to enable PCI device\n"); 2252 return err; 2253 } 2254 2255 err = pci_request_regions(pdev, DRV_NAME); 2256 if (err) { 2257 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2258 return err; 2259 } 2260 2261 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2262 if (err) { 2263 dev_err(dev, "DMA mask config failed, abort\n"); 2264 goto err_release_regions; 2265 } 2266 2267 pci_set_master(pdev); 2268 2269 /* Set number of queues */ 2270 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2271 2272 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2273 if (!netdev) { 2274 err = -ENOMEM; 2275 goto err_release_regions; 2276 } 2277 2278 pci_set_drvdata(pdev, netdev); 2279 SET_NETDEV_DEV(netdev, &pdev->dev); 2280 pf = netdev_priv(netdev); 2281 pf->netdev = netdev; 2282 pf->pdev = pdev; 2283 pf->dev = dev; 2284 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2285 pf->flags |= OTX2_FLAG_INTF_DOWN; 2286 2287 hw = &pf->hw; 2288 hw->pdev = pdev; 2289 hw->rx_queues = qcount; 2290 hw->tx_queues = qcount; 2291 hw->max_queues = qcount; 2292 2293 num_vec = pci_msix_vec_count(pdev); 2294 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2295 GFP_KERNEL); 2296 if (!hw->irq_name) { 2297 err = -ENOMEM; 2298 goto err_free_netdev; 2299 } 2300 2301 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2302 sizeof(cpumask_var_t), GFP_KERNEL); 2303 if (!hw->affinity_mask) { 2304 err = -ENOMEM; 2305 goto err_free_netdev; 2306 } 2307 2308 /* Map CSRs */ 2309 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2310 if (!pf->reg_base) { 2311 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2312 err = -ENOMEM; 2313 goto err_free_netdev; 2314 } 2315 2316 err = otx2_check_pf_usable(pf); 2317 if (err) 2318 goto err_free_netdev; 2319 2320 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2321 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2322 if (err < 0) { 2323 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2324 __func__, num_vec); 2325 goto err_free_netdev; 2326 } 2327 2328 /* Init PF <=> AF mailbox stuff */ 2329 err = otx2_pfaf_mbox_init(pf); 2330 if (err) 2331 goto err_free_irq_vectors; 2332 2333 /* Register mailbox interrupt */ 2334 err = otx2_register_mbox_intr(pf, true); 2335 if (err) 2336 goto err_mbox_destroy; 2337 2338 /* Request AF to attach NPA and NIX LFs to this PF. 2339 * NIX and NPA LFs are needed for this PF to function as a NIC. 2340 */ 2341 err = otx2_attach_npa_nix(pf); 2342 if (err) 2343 goto err_disable_mbox_intr; 2344 2345 err = otx2_realloc_msix_vectors(pf); 2346 if (err) 2347 goto err_detach_rsrc; 2348 2349 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2350 if (err) 2351 goto err_detach_rsrc; 2352 2353 otx2_setup_dev_hw_settings(pf); 2354 2355 /* Assign default mac address */ 2356 otx2_get_mac_from_af(netdev); 2357 2358 /* Don't check for error. Proceed without ptp */ 2359 otx2_ptp_init(pf); 2360 2361 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2362 * HW allocates buffer pointer from stack and uses it for DMA'ing 2363 * ingress packet. In some scenarios HW can free back allocated buffer 2364 * pointers to pool. This makes it impossible for SW to maintain a 2365 * parallel list where physical addresses of buffer pointers (IOVAs) 2366 * given to HW can be saved for later reference. 2367 * 2368 * So the only way to convert Rx packet's buffer address is to use 2369 * IOMMU's iova_to_phys() handler which translates the address by 2370 * walking through the translation tables. 2371 */ 2372 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2373 2374 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2375 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2376 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2377 NETIF_F_GSO_UDP_L4); 2378 netdev->features |= netdev->hw_features; 2379 2380 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2381 2382 err = otx2_mcam_flow_init(pf); 2383 if (err) 2384 goto err_ptp_destroy; 2385 2386 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2387 netdev->hw_features |= NETIF_F_NTUPLE; 2388 2389 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2390 netdev->priv_flags |= IFF_UNICAST_FLT; 2391 2392 /* Support TSO on tag interface */ 2393 netdev->vlan_features |= netdev->features; 2394 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2395 NETIF_F_HW_VLAN_STAG_TX; 2396 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2397 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2398 NETIF_F_HW_VLAN_STAG_RX; 2399 netdev->features |= netdev->hw_features; 2400 2401 netdev->gso_max_segs = OTX2_MAX_GSO_SEGS; 2402 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2403 2404 netdev->netdev_ops = &otx2_netdev_ops; 2405 2406 /* MTU range: 64 - 9190 */ 2407 netdev->min_mtu = OTX2_MIN_MTU; 2408 netdev->max_mtu = OTX2_MAX_MTU; 2409 2410 err = register_netdev(netdev); 2411 if (err) { 2412 dev_err(dev, "Failed to register netdevice\n"); 2413 goto err_del_mcam_entries; 2414 } 2415 2416 err = otx2_wq_init(pf); 2417 if (err) 2418 goto err_unreg_netdev; 2419 2420 otx2_set_ethtool_ops(netdev); 2421 2422 /* Enable link notifications */ 2423 otx2_cgx_config_linkevents(pf, true); 2424 2425 /* Enable pause frames by default */ 2426 pf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 2427 pf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 2428 2429 return 0; 2430 2431 err_unreg_netdev: 2432 unregister_netdev(netdev); 2433 err_del_mcam_entries: 2434 otx2_mcam_flow_del(pf); 2435 err_ptp_destroy: 2436 otx2_ptp_destroy(pf); 2437 err_detach_rsrc: 2438 otx2_detach_resources(&pf->mbox); 2439 err_disable_mbox_intr: 2440 otx2_disable_mbox_intr(pf); 2441 err_mbox_destroy: 2442 otx2_pfaf_mbox_destroy(pf); 2443 err_free_irq_vectors: 2444 pci_free_irq_vectors(hw->pdev); 2445 err_free_netdev: 2446 pci_set_drvdata(pdev, NULL); 2447 free_netdev(netdev); 2448 err_release_regions: 2449 pci_release_regions(pdev); 2450 return err; 2451 } 2452 2453 static void otx2_vf_link_event_task(struct work_struct *work) 2454 { 2455 struct otx2_vf_config *config; 2456 struct cgx_link_info_msg *req; 2457 struct mbox_msghdr *msghdr; 2458 struct otx2_nic *pf; 2459 int vf_idx; 2460 2461 config = container_of(work, struct otx2_vf_config, 2462 link_event_work.work); 2463 vf_idx = config - config->pf->vf_configs; 2464 pf = config->pf; 2465 2466 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2467 sizeof(*req), sizeof(struct msg_rsp)); 2468 if (!msghdr) { 2469 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2470 return; 2471 } 2472 2473 req = (struct cgx_link_info_msg *)msghdr; 2474 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2475 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2476 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2477 2478 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2479 } 2480 2481 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2482 { 2483 struct net_device *netdev = pci_get_drvdata(pdev); 2484 struct otx2_nic *pf = netdev_priv(netdev); 2485 int ret, i; 2486 2487 /* Init PF <=> VF mailbox stuff */ 2488 ret = otx2_pfvf_mbox_init(pf, numvfs); 2489 if (ret) 2490 return ret; 2491 2492 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2493 if (ret) 2494 goto free_mbox; 2495 2496 pf->vf_configs = kcalloc(numvfs, sizeof(struct otx2_vf_config), 2497 GFP_KERNEL); 2498 if (!pf->vf_configs) { 2499 ret = -ENOMEM; 2500 goto free_intr; 2501 } 2502 2503 for (i = 0; i < numvfs; i++) { 2504 pf->vf_configs[i].pf = pf; 2505 pf->vf_configs[i].intf_down = true; 2506 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2507 otx2_vf_link_event_task); 2508 } 2509 2510 ret = otx2_pf_flr_init(pf, numvfs); 2511 if (ret) 2512 goto free_configs; 2513 2514 ret = otx2_register_flr_me_intr(pf, numvfs); 2515 if (ret) 2516 goto free_flr; 2517 2518 ret = pci_enable_sriov(pdev, numvfs); 2519 if (ret) 2520 goto free_flr_intr; 2521 2522 return numvfs; 2523 free_flr_intr: 2524 otx2_disable_flr_me_intr(pf); 2525 free_flr: 2526 otx2_flr_wq_destroy(pf); 2527 free_configs: 2528 kfree(pf->vf_configs); 2529 free_intr: 2530 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2531 free_mbox: 2532 otx2_pfvf_mbox_destroy(pf); 2533 return ret; 2534 } 2535 2536 static int otx2_sriov_disable(struct pci_dev *pdev) 2537 { 2538 struct net_device *netdev = pci_get_drvdata(pdev); 2539 struct otx2_nic *pf = netdev_priv(netdev); 2540 int numvfs = pci_num_vf(pdev); 2541 int i; 2542 2543 if (!numvfs) 2544 return 0; 2545 2546 pci_disable_sriov(pdev); 2547 2548 for (i = 0; i < pci_num_vf(pdev); i++) 2549 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2550 kfree(pf->vf_configs); 2551 2552 otx2_disable_flr_me_intr(pf); 2553 otx2_flr_wq_destroy(pf); 2554 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2555 otx2_pfvf_mbox_destroy(pf); 2556 2557 return 0; 2558 } 2559 2560 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2561 { 2562 if (numvfs == 0) 2563 return otx2_sriov_disable(pdev); 2564 else 2565 return otx2_sriov_enable(pdev, numvfs); 2566 } 2567 2568 static void otx2_remove(struct pci_dev *pdev) 2569 { 2570 struct net_device *netdev = pci_get_drvdata(pdev); 2571 struct otx2_nic *pf; 2572 2573 if (!netdev) 2574 return; 2575 2576 pf = netdev_priv(netdev); 2577 2578 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2579 2580 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2581 otx2_config_hw_tx_tstamp(pf, false); 2582 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2583 otx2_config_hw_rx_tstamp(pf, false); 2584 2585 cancel_work_sync(&pf->reset_task); 2586 /* Disable link notifications */ 2587 otx2_cgx_config_linkevents(pf, false); 2588 2589 unregister_netdev(netdev); 2590 otx2_sriov_disable(pf->pdev); 2591 if (pf->otx2_wq) 2592 destroy_workqueue(pf->otx2_wq); 2593 2594 otx2_ptp_destroy(pf); 2595 otx2_mcam_flow_del(pf); 2596 otx2_detach_resources(&pf->mbox); 2597 otx2_disable_mbox_intr(pf); 2598 otx2_pfaf_mbox_destroy(pf); 2599 pci_free_irq_vectors(pf->pdev); 2600 pci_set_drvdata(pdev, NULL); 2601 free_netdev(netdev); 2602 2603 pci_release_regions(pdev); 2604 } 2605 2606 static struct pci_driver otx2_pf_driver = { 2607 .name = DRV_NAME, 2608 .id_table = otx2_pf_id_table, 2609 .probe = otx2_probe, 2610 .shutdown = otx2_remove, 2611 .remove = otx2_remove, 2612 .sriov_configure = otx2_sriov_configure 2613 }; 2614 2615 static int __init otx2_rvupf_init_module(void) 2616 { 2617 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2618 2619 return pci_register_driver(&otx2_pf_driver); 2620 } 2621 2622 static void __exit otx2_rvupf_cleanup_module(void) 2623 { 2624 pci_unregister_driver(&otx2_pf_driver); 2625 } 2626 2627 module_init(otx2_rvupf_init_module); 2628 module_exit(otx2_rvupf_cleanup_module); 2629