1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 30 #define DRV_NAME "rvu_nicpf" 31 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 32 33 /* Supported devices */ 34 static const struct pci_device_id otx2_pf_id_table[] = { 35 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 36 { 0, } /* end of table */ 37 }; 38 39 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 40 MODULE_DESCRIPTION(DRV_STRING); 41 MODULE_LICENSE("GPL v2"); 42 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 43 44 static void otx2_vf_link_event_task(struct work_struct *work); 45 46 enum { 47 TYPE_PFAF, 48 TYPE_PFVF, 49 }; 50 51 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 52 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 53 54 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 55 { 56 struct otx2_nic *pf = netdev_priv(netdev); 57 bool if_up = netif_running(netdev); 58 int err = 0; 59 60 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 61 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 62 netdev->mtu); 63 return -EINVAL; 64 } 65 if (if_up) 66 otx2_stop(netdev); 67 68 netdev_info(netdev, "Changing MTU from %d to %d\n", 69 netdev->mtu, new_mtu); 70 netdev->mtu = new_mtu; 71 72 if (if_up) 73 err = otx2_open(netdev); 74 75 return err; 76 } 77 78 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 79 { 80 int irq, vfs = pf->total_vfs; 81 82 /* Disable VFs ME interrupts */ 83 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 84 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 85 free_irq(irq, pf); 86 87 /* Disable VFs FLR interrupts */ 88 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 89 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 90 free_irq(irq, pf); 91 92 if (vfs <= 64) 93 return; 94 95 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 96 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 97 free_irq(irq, pf); 98 99 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 100 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 101 free_irq(irq, pf); 102 } 103 104 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 105 { 106 if (!pf->flr_wq) 107 return; 108 destroy_workqueue(pf->flr_wq); 109 pf->flr_wq = NULL; 110 devm_kfree(pf->dev, pf->flr_wrk); 111 } 112 113 static void otx2_flr_handler(struct work_struct *work) 114 { 115 struct flr_work *flrwork = container_of(work, struct flr_work, work); 116 struct otx2_nic *pf = flrwork->pf; 117 struct mbox *mbox = &pf->mbox; 118 struct msg_req *req; 119 int vf, reg = 0; 120 121 vf = flrwork - pf->flr_wrk; 122 123 mutex_lock(&mbox->lock); 124 req = otx2_mbox_alloc_msg_vf_flr(mbox); 125 if (!req) { 126 mutex_unlock(&mbox->lock); 127 return; 128 } 129 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 130 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 131 132 if (!otx2_sync_mbox_msg(&pf->mbox)) { 133 if (vf >= 64) { 134 reg = 1; 135 vf = vf - 64; 136 } 137 /* clear transcation pending bit */ 138 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 139 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 140 } 141 142 mutex_unlock(&mbox->lock); 143 } 144 145 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 146 { 147 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 148 int reg, dev, vf, start_vf, num_reg = 1; 149 u64 intr; 150 151 if (pf->total_vfs > 64) 152 num_reg = 2; 153 154 for (reg = 0; reg < num_reg; reg++) { 155 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 156 if (!intr) 157 continue; 158 start_vf = 64 * reg; 159 for (vf = 0; vf < 64; vf++) { 160 if (!(intr & BIT_ULL(vf))) 161 continue; 162 dev = vf + start_vf; 163 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 164 /* Clear interrupt */ 165 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 166 /* Disable the interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 168 BIT_ULL(vf)); 169 } 170 } 171 return IRQ_HANDLED; 172 } 173 174 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 175 { 176 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 177 int vf, reg, num_reg = 1; 178 u64 intr; 179 180 if (pf->total_vfs > 64) 181 num_reg = 2; 182 183 for (reg = 0; reg < num_reg; reg++) { 184 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 185 if (!intr) 186 continue; 187 for (vf = 0; vf < 64; vf++) { 188 if (!(intr & BIT_ULL(vf))) 189 continue; 190 /* clear trpend bit */ 191 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 192 /* clear interrupt */ 193 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 194 } 195 } 196 return IRQ_HANDLED; 197 } 198 199 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 200 { 201 struct otx2_hw *hw = &pf->hw; 202 char *irq_name; 203 int ret; 204 205 /* Register ME interrupt handler*/ 206 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 207 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 208 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 209 otx2_pf_me_intr_handler, 0, irq_name, pf); 210 if (ret) { 211 dev_err(pf->dev, 212 "RVUPF: IRQ registration failed for ME0\n"); 213 } 214 215 /* Register FLR interrupt handler */ 216 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 217 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 218 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 219 otx2_pf_flr_intr_handler, 0, irq_name, pf); 220 if (ret) { 221 dev_err(pf->dev, 222 "RVUPF: IRQ registration failed for FLR0\n"); 223 return ret; 224 } 225 226 if (numvfs > 64) { 227 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 228 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 229 rvu_get_pf(pf->pcifunc)); 230 ret = request_irq(pci_irq_vector 231 (pf->pdev, RVU_PF_INT_VEC_VFME1), 232 otx2_pf_me_intr_handler, 0, irq_name, pf); 233 if (ret) { 234 dev_err(pf->dev, 235 "RVUPF: IRQ registration failed for ME1\n"); 236 } 237 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 238 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 239 rvu_get_pf(pf->pcifunc)); 240 ret = request_irq(pci_irq_vector 241 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 242 otx2_pf_flr_intr_handler, 0, irq_name, pf); 243 if (ret) { 244 dev_err(pf->dev, 245 "RVUPF: IRQ registration failed for FLR1\n"); 246 return ret; 247 } 248 } 249 250 /* Enable ME interrupt for all VFs*/ 251 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 252 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 253 254 /* Enable FLR interrupt for all VFs*/ 255 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 256 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 257 258 if (numvfs > 64) { 259 numvfs -= 64; 260 261 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 262 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 263 INTR_MASK(numvfs)); 264 265 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 266 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 267 INTR_MASK(numvfs)); 268 } 269 return 0; 270 } 271 272 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 273 { 274 int vf; 275 276 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 277 if (!pf->flr_wq) 278 return -ENOMEM; 279 280 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 281 sizeof(struct flr_work), GFP_KERNEL); 282 if (!pf->flr_wrk) { 283 destroy_workqueue(pf->flr_wq); 284 return -ENOMEM; 285 } 286 287 for (vf = 0; vf < num_vfs; vf++) { 288 pf->flr_wrk[vf].pf = pf; 289 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 290 } 291 292 return 0; 293 } 294 295 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 296 int first, int mdevs, u64 intr, int type) 297 { 298 struct otx2_mbox_dev *mdev; 299 struct otx2_mbox *mbox; 300 struct mbox_hdr *hdr; 301 int i; 302 303 for (i = first; i < mdevs; i++) { 304 /* start from 0 */ 305 if (!(intr & BIT_ULL(i - first))) 306 continue; 307 308 mbox = &mw->mbox; 309 mdev = &mbox->dev[i]; 310 if (type == TYPE_PFAF) 311 otx2_sync_mbox_bbuf(mbox, i); 312 hdr = mdev->mbase + mbox->rx_start; 313 /* The hdr->num_msgs is set to zero immediately in the interrupt 314 * handler to ensure that it holds a correct value next time 315 * when the interrupt handler is called. 316 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 317 * pf>mbox.up_num_msgs holds the data for use in 318 * pfaf_mbox_up_handler. 319 */ 320 if (hdr->num_msgs) { 321 mw[i].num_msgs = hdr->num_msgs; 322 hdr->num_msgs = 0; 323 if (type == TYPE_PFAF) 324 memset(mbox->hwbase + mbox->rx_start, 0, 325 ALIGN(sizeof(struct mbox_hdr), 326 sizeof(u64))); 327 328 queue_work(mbox_wq, &mw[i].mbox_wrk); 329 } 330 331 mbox = &mw->mbox_up; 332 mdev = &mbox->dev[i]; 333 if (type == TYPE_PFAF) 334 otx2_sync_mbox_bbuf(mbox, i); 335 hdr = mdev->mbase + mbox->rx_start; 336 if (hdr->num_msgs) { 337 mw[i].up_num_msgs = hdr->num_msgs; 338 hdr->num_msgs = 0; 339 if (type == TYPE_PFAF) 340 memset(mbox->hwbase + mbox->rx_start, 0, 341 ALIGN(sizeof(struct mbox_hdr), 342 sizeof(u64))); 343 344 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 345 } 346 } 347 } 348 349 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 350 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 351 int devid) 352 { 353 struct otx2_mbox_dev *src_mdev = mdev; 354 int offset; 355 356 /* Msgs are already copied, trigger VF's mbox irq */ 357 smp_wmb(); 358 359 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 360 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 361 362 /* Restore VF's mbox bounce buffer region address */ 363 src_mdev->mbase = bbuf_base; 364 } 365 366 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 367 struct otx2_mbox *src_mbox, 368 int dir, int vf, int num_msgs) 369 { 370 struct otx2_mbox_dev *src_mdev, *dst_mdev; 371 struct mbox_hdr *mbox_hdr; 372 struct mbox_hdr *req_hdr; 373 struct mbox *dst_mbox; 374 int dst_size, err; 375 376 if (dir == MBOX_DIR_PFAF) { 377 /* Set VF's mailbox memory as PF's bounce buffer memory, so 378 * that explicit copying of VF's msgs to PF=>AF mbox region 379 * and AF=>PF responses to VF's mbox region can be avoided. 380 */ 381 src_mdev = &src_mbox->dev[vf]; 382 mbox_hdr = src_mbox->hwbase + 383 src_mbox->rx_start + (vf * MBOX_SIZE); 384 385 dst_mbox = &pf->mbox; 386 dst_size = dst_mbox->mbox.tx_size - 387 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 388 /* Check if msgs fit into destination area and has valid size */ 389 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 390 return -EINVAL; 391 392 dst_mdev = &dst_mbox->mbox.dev[0]; 393 394 mutex_lock(&pf->mbox.lock); 395 dst_mdev->mbase = src_mdev->mbase; 396 dst_mdev->msg_size = mbox_hdr->msg_size; 397 dst_mdev->num_msgs = num_msgs; 398 err = otx2_sync_mbox_msg(dst_mbox); 399 /* Error code -EIO indicate there is a communication failure 400 * to the AF. Rest of the error codes indicate that AF processed 401 * VF messages and set the error codes in response messages 402 * (if any) so simply forward responses to VF. 403 */ 404 if (err == -EIO) { 405 dev_warn(pf->dev, 406 "AF not responding to VF%d messages\n", vf); 407 /* restore PF mbase and exit */ 408 dst_mdev->mbase = pf->mbox.bbuf_base; 409 mutex_unlock(&pf->mbox.lock); 410 return err; 411 } 412 /* At this point, all the VF messages sent to AF are acked 413 * with proper responses and responses are copied to VF 414 * mailbox hence raise interrupt to VF. 415 */ 416 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 417 dst_mbox->mbox.rx_start); 418 req_hdr->num_msgs = num_msgs; 419 420 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 421 pf->mbox.bbuf_base, vf); 422 mutex_unlock(&pf->mbox.lock); 423 } else if (dir == MBOX_DIR_PFVF_UP) { 424 src_mdev = &src_mbox->dev[0]; 425 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 426 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 427 src_mbox->rx_start); 428 req_hdr->num_msgs = num_msgs; 429 430 dst_mbox = &pf->mbox_pfvf[0]; 431 dst_size = dst_mbox->mbox_up.tx_size - 432 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 433 /* Check if msgs fit into destination area */ 434 if (mbox_hdr->msg_size > dst_size) 435 return -EINVAL; 436 437 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 438 dst_mdev->mbase = src_mdev->mbase; 439 dst_mdev->msg_size = mbox_hdr->msg_size; 440 dst_mdev->num_msgs = mbox_hdr->num_msgs; 441 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 442 if (err) { 443 dev_warn(pf->dev, 444 "VF%d is not responding to mailbox\n", vf); 445 return err; 446 } 447 } else if (dir == MBOX_DIR_VFPF_UP) { 448 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 449 src_mbox->rx_start); 450 req_hdr->num_msgs = num_msgs; 451 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 452 &pf->mbox.mbox_up, 453 pf->mbox_pfvf[vf].bbuf_base, 454 0); 455 } 456 457 return 0; 458 } 459 460 static void otx2_pfvf_mbox_handler(struct work_struct *work) 461 { 462 struct mbox_msghdr *msg = NULL; 463 int offset, vf_idx, id, err; 464 struct otx2_mbox_dev *mdev; 465 struct mbox_hdr *req_hdr; 466 struct otx2_mbox *mbox; 467 struct mbox *vf_mbox; 468 struct otx2_nic *pf; 469 470 vf_mbox = container_of(work, struct mbox, mbox_wrk); 471 pf = vf_mbox->pfvf; 472 vf_idx = vf_mbox - pf->mbox_pfvf; 473 474 mbox = &pf->mbox_pfvf[0].mbox; 475 mdev = &mbox->dev[vf_idx]; 476 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 477 478 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 479 480 for (id = 0; id < vf_mbox->num_msgs; id++) { 481 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 482 offset); 483 484 if (msg->sig != OTX2_MBOX_REQ_SIG) 485 goto inval_msg; 486 487 /* Set VF's number in each of the msg */ 488 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 489 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 490 offset = msg->next_msgoff; 491 } 492 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 493 vf_mbox->num_msgs); 494 if (err) 495 goto inval_msg; 496 return; 497 498 inval_msg: 499 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 500 otx2_mbox_msg_send(mbox, vf_idx); 501 } 502 503 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 504 { 505 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 506 struct otx2_nic *pf = vf_mbox->pfvf; 507 struct otx2_mbox_dev *mdev; 508 int offset, id, vf_idx = 0; 509 struct mbox_hdr *rsp_hdr; 510 struct mbox_msghdr *msg; 511 struct otx2_mbox *mbox; 512 513 vf_idx = vf_mbox - pf->mbox_pfvf; 514 mbox = &pf->mbox_pfvf[0].mbox_up; 515 mdev = &mbox->dev[vf_idx]; 516 517 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 518 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 519 520 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 521 msg = mdev->mbase + offset; 522 523 if (msg->id >= MBOX_MSG_MAX) { 524 dev_err(pf->dev, 525 "Mbox msg with unknown ID 0x%x\n", msg->id); 526 goto end; 527 } 528 529 if (msg->sig != OTX2_MBOX_RSP_SIG) { 530 dev_err(pf->dev, 531 "Mbox msg with wrong signature %x, ID 0x%x\n", 532 msg->sig, msg->id); 533 goto end; 534 } 535 536 switch (msg->id) { 537 case MBOX_MSG_CGX_LINK_EVENT: 538 break; 539 default: 540 if (msg->rc) 541 dev_err(pf->dev, 542 "Mbox msg response has err %d, ID 0x%x\n", 543 msg->rc, msg->id); 544 break; 545 } 546 547 end: 548 offset = mbox->rx_start + msg->next_msgoff; 549 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 550 __otx2_mbox_reset(mbox, 0); 551 mdev->msgs_acked++; 552 } 553 } 554 555 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 556 { 557 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 558 int vfs = pf->total_vfs; 559 struct mbox *mbox; 560 u64 intr; 561 562 mbox = pf->mbox_pfvf; 563 /* Handle VF interrupts */ 564 if (vfs > 64) { 565 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 566 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 567 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 568 TYPE_PFVF); 569 if (intr) 570 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 571 vfs = 64; 572 } 573 574 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 575 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 576 577 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 578 579 if (intr) 580 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 581 582 return IRQ_HANDLED; 583 } 584 585 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 586 { 587 void __iomem *hwbase; 588 struct mbox *mbox; 589 int err, vf; 590 u64 base; 591 592 if (!numvfs) 593 return -EINVAL; 594 595 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 596 sizeof(struct mbox), GFP_KERNEL); 597 if (!pf->mbox_pfvf) 598 return -ENOMEM; 599 600 pf->mbox_pfvf_wq = alloc_ordered_workqueue("otx2_pfvf_mailbox", 601 WQ_HIGHPRI | WQ_MEM_RECLAIM); 602 if (!pf->mbox_pfvf_wq) 603 return -ENOMEM; 604 605 /* On CN10K platform, PF <-> VF mailbox region follows after 606 * PF <-> AF mailbox region. 607 */ 608 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 609 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 610 MBOX_SIZE; 611 else 612 base = readq((void __iomem *)((u64)pf->reg_base + 613 RVU_PF_VF_BAR4_ADDR)); 614 615 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 616 if (!hwbase) { 617 err = -ENOMEM; 618 goto free_wq; 619 } 620 621 mbox = &pf->mbox_pfvf[0]; 622 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 623 MBOX_DIR_PFVF, numvfs); 624 if (err) 625 goto free_iomem; 626 627 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 628 MBOX_DIR_PFVF_UP, numvfs); 629 if (err) 630 goto free_iomem; 631 632 for (vf = 0; vf < numvfs; vf++) { 633 mbox->pfvf = pf; 634 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 635 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 636 mbox++; 637 } 638 639 return 0; 640 641 free_iomem: 642 if (hwbase) 643 iounmap(hwbase); 644 free_wq: 645 destroy_workqueue(pf->mbox_pfvf_wq); 646 return err; 647 } 648 649 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 650 { 651 struct mbox *mbox = &pf->mbox_pfvf[0]; 652 653 if (!mbox) 654 return; 655 656 if (pf->mbox_pfvf_wq) { 657 destroy_workqueue(pf->mbox_pfvf_wq); 658 pf->mbox_pfvf_wq = NULL; 659 } 660 661 if (mbox->mbox.hwbase) 662 iounmap(mbox->mbox.hwbase); 663 664 otx2_mbox_destroy(&mbox->mbox); 665 } 666 667 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 668 { 669 /* Clear PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 671 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 672 673 /* Enable PF <=> VF mailbox IRQ */ 674 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 675 if (numvfs > 64) { 676 numvfs -= 64; 677 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 678 INTR_MASK(numvfs)); 679 } 680 } 681 682 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 683 { 684 int vector; 685 686 /* Disable PF <=> VF mailbox IRQ */ 687 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 688 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 689 690 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 691 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 692 free_irq(vector, pf); 693 694 if (numvfs > 64) { 695 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 696 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 697 free_irq(vector, pf); 698 } 699 } 700 701 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 702 { 703 struct otx2_hw *hw = &pf->hw; 704 char *irq_name; 705 int err; 706 707 /* Register MBOX0 interrupt handler */ 708 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 709 if (pf->pcifunc) 710 snprintf(irq_name, NAME_SIZE, 711 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 712 else 713 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 714 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 715 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 716 if (err) { 717 dev_err(pf->dev, 718 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 719 return err; 720 } 721 722 if (numvfs > 64) { 723 /* Register MBOX1 interrupt handler */ 724 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 725 if (pf->pcifunc) 726 snprintf(irq_name, NAME_SIZE, 727 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 728 else 729 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 730 err = request_irq(pci_irq_vector(pf->pdev, 731 RVU_PF_INT_VEC_VFPF_MBOX1), 732 otx2_pfvf_mbox_intr_handler, 733 0, irq_name, pf); 734 if (err) { 735 dev_err(pf->dev, 736 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 737 return err; 738 } 739 } 740 741 otx2_enable_pfvf_mbox_intr(pf, numvfs); 742 743 return 0; 744 } 745 746 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 747 struct mbox_msghdr *msg) 748 { 749 int devid; 750 751 if (msg->id >= MBOX_MSG_MAX) { 752 dev_err(pf->dev, 753 "Mbox msg with unknown ID 0x%x\n", msg->id); 754 return; 755 } 756 757 if (msg->sig != OTX2_MBOX_RSP_SIG) { 758 dev_err(pf->dev, 759 "Mbox msg with wrong signature %x, ID 0x%x\n", 760 msg->sig, msg->id); 761 return; 762 } 763 764 /* message response heading VF */ 765 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 766 if (devid) { 767 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 768 struct delayed_work *dwork; 769 770 switch (msg->id) { 771 case MBOX_MSG_NIX_LF_START_RX: 772 config->intf_down = false; 773 dwork = &config->link_event_work; 774 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 775 break; 776 case MBOX_MSG_NIX_LF_STOP_RX: 777 config->intf_down = true; 778 break; 779 } 780 781 return; 782 } 783 784 switch (msg->id) { 785 case MBOX_MSG_READY: 786 pf->pcifunc = msg->pcifunc; 787 break; 788 case MBOX_MSG_MSIX_OFFSET: 789 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 790 break; 791 case MBOX_MSG_NPA_LF_ALLOC: 792 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 793 break; 794 case MBOX_MSG_NIX_LF_ALLOC: 795 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 796 break; 797 case MBOX_MSG_NIX_BP_ENABLE: 798 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_STATS: 801 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 802 break; 803 case MBOX_MSG_CGX_FEC_STATS: 804 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 805 break; 806 default: 807 if (msg->rc) 808 dev_err(pf->dev, 809 "Mbox msg response has err %d, ID 0x%x\n", 810 msg->rc, msg->id); 811 break; 812 } 813 } 814 815 static void otx2_pfaf_mbox_handler(struct work_struct *work) 816 { 817 struct otx2_mbox_dev *mdev; 818 struct mbox_hdr *rsp_hdr; 819 struct mbox_msghdr *msg; 820 struct otx2_mbox *mbox; 821 struct mbox *af_mbox; 822 struct otx2_nic *pf; 823 int offset, id; 824 825 af_mbox = container_of(work, struct mbox, mbox_wrk); 826 mbox = &af_mbox->mbox; 827 mdev = &mbox->dev[0]; 828 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 829 830 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 831 pf = af_mbox->pfvf; 832 833 for (id = 0; id < af_mbox->num_msgs; id++) { 834 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 835 otx2_process_pfaf_mbox_msg(pf, msg); 836 offset = mbox->rx_start + msg->next_msgoff; 837 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 838 __otx2_mbox_reset(mbox, 0); 839 mdev->msgs_acked++; 840 } 841 842 } 843 844 static void otx2_handle_link_event(struct otx2_nic *pf) 845 { 846 struct cgx_link_user_info *linfo = &pf->linfo; 847 struct net_device *netdev = pf->netdev; 848 849 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 850 linfo->link_up ? "UP" : "DOWN", linfo->speed, 851 linfo->full_duplex ? "Full" : "Half"); 852 if (linfo->link_up) { 853 netif_carrier_on(netdev); 854 netif_tx_start_all_queues(netdev); 855 } else { 856 netif_tx_stop_all_queues(netdev); 857 netif_carrier_off(netdev); 858 } 859 } 860 861 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 862 struct mcs_intr_info *event, 863 struct msg_rsp *rsp) 864 { 865 cn10k_handle_mcs_event(pf, event); 866 867 return 0; 868 } 869 870 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 871 struct cgx_link_info_msg *msg, 872 struct msg_rsp *rsp) 873 { 874 int i; 875 876 /* Copy the link info sent by AF */ 877 pf->linfo = msg->link_info; 878 879 /* notify VFs about link event */ 880 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 881 struct otx2_vf_config *config = &pf->vf_configs[i]; 882 struct delayed_work *dwork = &config->link_event_work; 883 884 if (config->intf_down) 885 continue; 886 887 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 888 } 889 890 /* interface has not been fully configured yet */ 891 if (pf->flags & OTX2_FLAG_INTF_DOWN) 892 return 0; 893 894 otx2_handle_link_event(pf); 895 return 0; 896 } 897 898 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 899 struct mbox_msghdr *req) 900 { 901 /* Check if valid, if not reply with a invalid msg */ 902 if (req->sig != OTX2_MBOX_REQ_SIG) { 903 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 904 return -ENODEV; 905 } 906 907 switch (req->id) { 908 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 909 case _id: { \ 910 struct _rsp_type *rsp; \ 911 int err; \ 912 \ 913 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 914 &pf->mbox.mbox_up, 0, \ 915 sizeof(struct _rsp_type)); \ 916 if (!rsp) \ 917 return -ENOMEM; \ 918 \ 919 rsp->hdr.id = _id; \ 920 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 921 rsp->hdr.pcifunc = 0; \ 922 rsp->hdr.rc = 0; \ 923 \ 924 err = otx2_mbox_up_handler_ ## _fn_name( \ 925 pf, (struct _req_type *)req, rsp); \ 926 return err; \ 927 } 928 MBOX_UP_CGX_MESSAGES 929 MBOX_UP_MCS_MESSAGES 930 #undef M 931 break; 932 default: 933 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 934 return -ENODEV; 935 } 936 return 0; 937 } 938 939 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 940 { 941 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 942 struct otx2_mbox *mbox = &af_mbox->mbox_up; 943 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 944 struct otx2_nic *pf = af_mbox->pfvf; 945 int offset, id, devid = 0; 946 struct mbox_hdr *rsp_hdr; 947 struct mbox_msghdr *msg; 948 949 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 950 951 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 952 953 for (id = 0; id < af_mbox->up_num_msgs; id++) { 954 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 955 956 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 957 /* Skip processing VF's messages */ 958 if (!devid) 959 otx2_process_mbox_msg_up(pf, msg); 960 offset = mbox->rx_start + msg->next_msgoff; 961 } 962 if (devid) { 963 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 964 MBOX_DIR_PFVF_UP, devid - 1, 965 af_mbox->up_num_msgs); 966 return; 967 } 968 969 otx2_mbox_msg_send(mbox, 0); 970 } 971 972 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 973 { 974 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 975 struct mbox *mbox; 976 977 /* Clear the IRQ */ 978 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 979 980 mbox = &pf->mbox; 981 982 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 983 984 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 985 986 return IRQ_HANDLED; 987 } 988 989 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 990 { 991 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 992 993 /* Disable AF => PF mailbox IRQ */ 994 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 995 free_irq(vector, pf); 996 } 997 998 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 999 { 1000 struct otx2_hw *hw = &pf->hw; 1001 struct msg_req *req; 1002 char *irq_name; 1003 int err; 1004 1005 /* Register mailbox interrupt handler */ 1006 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1007 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1008 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1009 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1010 if (err) { 1011 dev_err(pf->dev, 1012 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1013 return err; 1014 } 1015 1016 /* Enable mailbox interrupt for msgs coming from AF. 1017 * First clear to avoid spurious interrupts, if any. 1018 */ 1019 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1020 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1021 1022 if (!probe_af) 1023 return 0; 1024 1025 /* Check mailbox communication with AF */ 1026 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1027 if (!req) { 1028 otx2_disable_mbox_intr(pf); 1029 return -ENOMEM; 1030 } 1031 err = otx2_sync_mbox_msg(&pf->mbox); 1032 if (err) { 1033 dev_warn(pf->dev, 1034 "AF not responding to mailbox, deferring probe\n"); 1035 otx2_disable_mbox_intr(pf); 1036 return -EPROBE_DEFER; 1037 } 1038 1039 return 0; 1040 } 1041 1042 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1043 { 1044 struct mbox *mbox = &pf->mbox; 1045 1046 if (pf->mbox_wq) { 1047 destroy_workqueue(pf->mbox_wq); 1048 pf->mbox_wq = NULL; 1049 } 1050 1051 if (mbox->mbox.hwbase) 1052 iounmap((void __iomem *)mbox->mbox.hwbase); 1053 1054 otx2_mbox_destroy(&mbox->mbox); 1055 otx2_mbox_destroy(&mbox->mbox_up); 1056 } 1057 1058 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1059 { 1060 struct mbox *mbox = &pf->mbox; 1061 void __iomem *hwbase; 1062 int err; 1063 1064 mbox->pfvf = pf; 1065 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1066 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1067 if (!pf->mbox_wq) 1068 return -ENOMEM; 1069 1070 /* Mailbox is a reserved memory (in RAM) region shared between 1071 * admin function (i.e AF) and this PF, shouldn't be mapped as 1072 * device memory to allow unaligned accesses. 1073 */ 1074 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1075 MBOX_SIZE); 1076 if (!hwbase) { 1077 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1078 err = -ENOMEM; 1079 goto exit; 1080 } 1081 1082 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1083 MBOX_DIR_PFAF, 1); 1084 if (err) 1085 goto exit; 1086 1087 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1088 MBOX_DIR_PFAF_UP, 1); 1089 if (err) 1090 goto exit; 1091 1092 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1093 if (err) 1094 goto exit; 1095 1096 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1097 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1098 mutex_init(&mbox->lock); 1099 1100 return 0; 1101 exit: 1102 otx2_pfaf_mbox_destroy(pf); 1103 return err; 1104 } 1105 1106 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1107 { 1108 struct msg_req *msg; 1109 int err; 1110 1111 mutex_lock(&pf->mbox.lock); 1112 if (enable) 1113 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1114 else 1115 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1116 1117 if (!msg) { 1118 mutex_unlock(&pf->mbox.lock); 1119 return -ENOMEM; 1120 } 1121 1122 err = otx2_sync_mbox_msg(&pf->mbox); 1123 mutex_unlock(&pf->mbox.lock); 1124 return err; 1125 } 1126 1127 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1128 { 1129 struct msg_req *msg; 1130 int err; 1131 1132 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1133 pf->flow_cfg->dmacflt_max_flows)) 1134 netdev_warn(pf->netdev, 1135 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1136 1137 mutex_lock(&pf->mbox.lock); 1138 if (enable) 1139 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1140 else 1141 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1142 1143 if (!msg) { 1144 mutex_unlock(&pf->mbox.lock); 1145 return -ENOMEM; 1146 } 1147 1148 err = otx2_sync_mbox_msg(&pf->mbox); 1149 mutex_unlock(&pf->mbox.lock); 1150 return err; 1151 } 1152 1153 int otx2_set_real_num_queues(struct net_device *netdev, 1154 int tx_queues, int rx_queues) 1155 { 1156 int err; 1157 1158 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1159 if (err) { 1160 netdev_err(netdev, 1161 "Failed to set no of Tx queues: %d\n", tx_queues); 1162 return err; 1163 } 1164 1165 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1166 if (err) 1167 netdev_err(netdev, 1168 "Failed to set no of Rx queues: %d\n", rx_queues); 1169 return err; 1170 } 1171 EXPORT_SYMBOL(otx2_set_real_num_queues); 1172 1173 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1174 "NIX_SQOPERR_OOR", 1175 "NIX_SQOPERR_CTX_FAULT", 1176 "NIX_SQOPERR_CTX_POISON", 1177 "NIX_SQOPERR_DISABLED", 1178 "NIX_SQOPERR_SIZE_ERR", 1179 "NIX_SQOPERR_OFLOW", 1180 "NIX_SQOPERR_SQB_NULL", 1181 "NIX_SQOPERR_SQB_FAULT", 1182 "NIX_SQOPERR_SQE_SZ_ZERO", 1183 }; 1184 1185 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1186 "NIX_MNQERR_SQ_CTX_FAULT", 1187 "NIX_MNQERR_SQ_CTX_POISON", 1188 "NIX_MNQERR_SQB_FAULT", 1189 "NIX_MNQERR_SQB_POISON", 1190 "NIX_MNQERR_TOTAL_ERR", 1191 "NIX_MNQERR_LSO_ERR", 1192 "NIX_MNQERR_CQ_QUERY_ERR", 1193 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1194 "NIX_MNQERR_MAXLEN_ERR", 1195 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1196 }; 1197 1198 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1199 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1200 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1201 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1202 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1203 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1204 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1205 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1206 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1207 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1208 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1209 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1210 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1211 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1212 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1213 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1214 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1215 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1216 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1217 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1218 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1219 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1220 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1221 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1222 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1223 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1224 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1225 }; 1226 1227 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1228 { 1229 struct otx2_nic *pf = data; 1230 struct otx2_snd_queue *sq; 1231 u64 val, *ptr; 1232 u64 qidx = 0; 1233 1234 /* CQ */ 1235 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1236 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1237 val = otx2_atomic64_add((qidx << 44), ptr); 1238 1239 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1240 (val & NIX_CQERRINT_BITS)); 1241 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1242 continue; 1243 1244 if (val & BIT_ULL(42)) { 1245 netdev_err(pf->netdev, 1246 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1247 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1248 } else { 1249 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1250 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1251 qidx); 1252 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1253 netdev_err(pf->netdev, 1254 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1255 qidx); 1256 } 1257 1258 schedule_work(&pf->reset_task); 1259 } 1260 1261 /* SQ */ 1262 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1263 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1264 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1265 1266 sq = &pf->qset.sq[qidx]; 1267 if (!sq->sqb_ptrs) 1268 continue; 1269 1270 /* Below debug registers captures first errors corresponding to 1271 * those registers. We don't have to check against SQ qid as 1272 * these are fatal errors. 1273 */ 1274 1275 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1276 val = otx2_atomic64_add((qidx << 44), ptr); 1277 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1278 (val & NIX_SQINT_BITS)); 1279 1280 if (val & BIT_ULL(42)) { 1281 netdev_err(pf->netdev, 1282 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1283 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1284 goto done; 1285 } 1286 1287 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1288 if (!(sq_op_err_dbg & BIT(44))) 1289 goto chk_mnq_err_dbg; 1290 1291 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1292 netdev_err(pf->netdev, 1293 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1294 qidx, sq_op_err_dbg, 1295 nix_sqoperr_e_str[sq_op_err_code], 1296 sq_op_err_code); 1297 1298 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1299 1300 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1301 goto chk_mnq_err_dbg; 1302 1303 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1304 * TODO: But we are in irq context. How to call mbox functions which does sleep 1305 */ 1306 1307 chk_mnq_err_dbg: 1308 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1309 if (!(mnq_err_dbg & BIT(44))) 1310 goto chk_snd_err_dbg; 1311 1312 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1313 netdev_err(pf->netdev, 1314 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1315 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1316 mnq_err_code); 1317 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1318 1319 chk_snd_err_dbg: 1320 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1321 if (snd_err_dbg & BIT(44)) { 1322 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1323 netdev_err(pf->netdev, 1324 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1325 qidx, snd_err_dbg, 1326 nix_snd_status_e_str[snd_err_code], 1327 snd_err_code); 1328 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1329 } 1330 1331 done: 1332 /* Print values and reset */ 1333 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1334 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1335 qidx); 1336 1337 schedule_work(&pf->reset_task); 1338 } 1339 1340 return IRQ_HANDLED; 1341 } 1342 1343 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1344 { 1345 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1346 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1347 int qidx = cq_poll->cint_idx; 1348 1349 /* Disable interrupts. 1350 * 1351 * Completion interrupts behave in a level-triggered interrupt 1352 * fashion, and hence have to be cleared only after it is serviced. 1353 */ 1354 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1355 1356 /* Schedule NAPI */ 1357 pf->napi_events++; 1358 napi_schedule_irqoff(&cq_poll->napi); 1359 1360 return IRQ_HANDLED; 1361 } 1362 1363 static void otx2_disable_napi(struct otx2_nic *pf) 1364 { 1365 struct otx2_qset *qset = &pf->qset; 1366 struct otx2_cq_poll *cq_poll; 1367 int qidx; 1368 1369 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1370 cq_poll = &qset->napi[qidx]; 1371 cancel_work_sync(&cq_poll->dim.work); 1372 napi_disable(&cq_poll->napi); 1373 netif_napi_del(&cq_poll->napi); 1374 } 1375 } 1376 1377 static void otx2_free_cq_res(struct otx2_nic *pf) 1378 { 1379 struct otx2_qset *qset = &pf->qset; 1380 struct otx2_cq_queue *cq; 1381 int qidx; 1382 1383 /* Disable CQs */ 1384 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1385 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1386 cq = &qset->cq[qidx]; 1387 qmem_free(pf->dev, cq->cqe); 1388 } 1389 } 1390 1391 static void otx2_free_sq_res(struct otx2_nic *pf) 1392 { 1393 struct otx2_qset *qset = &pf->qset; 1394 struct otx2_snd_queue *sq; 1395 int qidx; 1396 1397 /* Disable SQs */ 1398 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1399 /* Free SQB pointers */ 1400 otx2_sq_free_sqbs(pf); 1401 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1402 sq = &qset->sq[qidx]; 1403 /* Skip freeing Qos queues if they are not initialized */ 1404 if (!sq->sqe) 1405 continue; 1406 qmem_free(pf->dev, sq->sqe); 1407 qmem_free(pf->dev, sq->tso_hdrs); 1408 kfree(sq->sg); 1409 kfree(sq->sqb_ptrs); 1410 } 1411 } 1412 1413 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1414 { 1415 int frame_size; 1416 int total_size; 1417 int rbuf_size; 1418 1419 if (pf->hw.rbuf_len) 1420 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1421 1422 /* The data transferred by NIX to memory consists of actual packet 1423 * plus additional data which has timestamp and/or EDSA/HIGIG2 1424 * headers if interface is configured in corresponding modes. 1425 * NIX transfers entire data using 6 segments/buffers and writes 1426 * a CQE_RX descriptor with those segment addresses. First segment 1427 * has additional data prepended to packet. Also software omits a 1428 * headroom of 128 bytes in each segment. Hence the total size of 1429 * memory needed to receive a packet with 'mtu' is: 1430 * frame size = mtu + additional data; 1431 * memory = frame_size + headroom * 6; 1432 * each receive buffer size = memory / 6; 1433 */ 1434 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1435 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1436 rbuf_size = total_size / 6; 1437 1438 return ALIGN(rbuf_size, 2048); 1439 } 1440 1441 static int otx2_init_hw_resources(struct otx2_nic *pf) 1442 { 1443 struct nix_lf_free_req *free_req; 1444 struct mbox *mbox = &pf->mbox; 1445 struct otx2_hw *hw = &pf->hw; 1446 struct msg_req *req; 1447 int err = 0, lvl; 1448 1449 /* Set required NPA LF's pool counts 1450 * Auras and Pools are used in a 1:1 mapping, 1451 * so, aura count = pool count. 1452 */ 1453 hw->rqpool_cnt = hw->rx_queues; 1454 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1455 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1456 1457 /* Maximum hardware supported transmit length */ 1458 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1459 1460 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1461 1462 mutex_lock(&mbox->lock); 1463 /* NPA init */ 1464 err = otx2_config_npa(pf); 1465 if (err) 1466 goto exit; 1467 1468 /* NIX init */ 1469 err = otx2_config_nix(pf); 1470 if (err) 1471 goto err_free_npa_lf; 1472 1473 /* Enable backpressure for CGX mapped PF/VFs */ 1474 if (!is_otx2_lbkvf(pf->pdev)) 1475 otx2_nix_config_bp(pf, true); 1476 1477 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1478 err = otx2_rq_aura_pool_init(pf); 1479 if (err) { 1480 mutex_unlock(&mbox->lock); 1481 goto err_free_nix_lf; 1482 } 1483 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1484 err = otx2_sq_aura_pool_init(pf); 1485 if (err) { 1486 mutex_unlock(&mbox->lock); 1487 goto err_free_rq_ptrs; 1488 } 1489 1490 err = otx2_txsch_alloc(pf); 1491 if (err) { 1492 mutex_unlock(&mbox->lock); 1493 goto err_free_sq_ptrs; 1494 } 1495 1496 #ifdef CONFIG_DCB 1497 if (pf->pfc_en) { 1498 err = otx2_pfc_txschq_alloc(pf); 1499 if (err) { 1500 mutex_unlock(&mbox->lock); 1501 goto err_free_sq_ptrs; 1502 } 1503 } 1504 #endif 1505 1506 err = otx2_config_nix_queues(pf); 1507 if (err) { 1508 mutex_unlock(&mbox->lock); 1509 goto err_free_txsch; 1510 } 1511 1512 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1513 err = otx2_txschq_config(pf, lvl, 0, false); 1514 if (err) { 1515 mutex_unlock(&mbox->lock); 1516 goto err_free_nix_queues; 1517 } 1518 } 1519 1520 #ifdef CONFIG_DCB 1521 if (pf->pfc_en) { 1522 err = otx2_pfc_txschq_config(pf); 1523 if (err) { 1524 mutex_unlock(&mbox->lock); 1525 goto err_free_nix_queues; 1526 } 1527 } 1528 #endif 1529 1530 mutex_unlock(&mbox->lock); 1531 return err; 1532 1533 err_free_nix_queues: 1534 otx2_free_sq_res(pf); 1535 otx2_free_cq_res(pf); 1536 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1537 err_free_txsch: 1538 otx2_txschq_stop(pf); 1539 err_free_sq_ptrs: 1540 otx2_sq_free_sqbs(pf); 1541 err_free_rq_ptrs: 1542 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1543 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1544 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1545 otx2_aura_pool_free(pf); 1546 err_free_nix_lf: 1547 mutex_lock(&mbox->lock); 1548 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1549 if (free_req) { 1550 free_req->flags = NIX_LF_DISABLE_FLOWS; 1551 if (otx2_sync_mbox_msg(mbox)) 1552 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1553 } 1554 err_free_npa_lf: 1555 /* Reset NPA LF */ 1556 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1557 if (req) { 1558 if (otx2_sync_mbox_msg(mbox)) 1559 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1560 } 1561 exit: 1562 mutex_unlock(&mbox->lock); 1563 return err; 1564 } 1565 1566 static void otx2_free_hw_resources(struct otx2_nic *pf) 1567 { 1568 struct otx2_qset *qset = &pf->qset; 1569 struct nix_lf_free_req *free_req; 1570 struct mbox *mbox = &pf->mbox; 1571 struct otx2_cq_queue *cq; 1572 struct otx2_pool *pool; 1573 struct msg_req *req; 1574 int pool_id; 1575 int qidx; 1576 1577 /* Ensure all SQE are processed */ 1578 otx2_sqb_flush(pf); 1579 1580 /* Stop transmission */ 1581 otx2_txschq_stop(pf); 1582 1583 #ifdef CONFIG_DCB 1584 if (pf->pfc_en) 1585 otx2_pfc_txschq_stop(pf); 1586 #endif 1587 1588 otx2_clean_qos_queues(pf); 1589 1590 mutex_lock(&mbox->lock); 1591 /* Disable backpressure */ 1592 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1593 otx2_nix_config_bp(pf, false); 1594 mutex_unlock(&mbox->lock); 1595 1596 /* Disable RQs */ 1597 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1598 1599 /*Dequeue all CQEs */ 1600 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1601 cq = &qset->cq[qidx]; 1602 if (cq->cq_type == CQ_RX) 1603 otx2_cleanup_rx_cqes(pf, cq, qidx); 1604 else 1605 otx2_cleanup_tx_cqes(pf, cq); 1606 } 1607 otx2_free_pending_sqe(pf); 1608 1609 otx2_free_sq_res(pf); 1610 1611 /* Free RQ buffer pointers*/ 1612 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1613 1614 for (qidx = 0; qidx < pf->hw.rx_queues; qidx++) { 1615 pool_id = otx2_get_pool_idx(pf, AURA_NIX_RQ, qidx); 1616 pool = &pf->qset.pool[pool_id]; 1617 page_pool_destroy(pool->page_pool); 1618 pool->page_pool = NULL; 1619 } 1620 1621 otx2_free_cq_res(pf); 1622 1623 /* Free all ingress bandwidth profiles allocated */ 1624 cn10k_free_all_ipolicers(pf); 1625 1626 mutex_lock(&mbox->lock); 1627 /* Reset NIX LF */ 1628 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1629 if (free_req) { 1630 free_req->flags = NIX_LF_DISABLE_FLOWS; 1631 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1632 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1633 if (otx2_sync_mbox_msg(mbox)) 1634 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1635 } 1636 mutex_unlock(&mbox->lock); 1637 1638 /* Disable NPA Pool and Aura hw context */ 1639 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1640 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1641 otx2_aura_pool_free(pf); 1642 1643 mutex_lock(&mbox->lock); 1644 /* Reset NPA LF */ 1645 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1646 if (req) { 1647 if (otx2_sync_mbox_msg(mbox)) 1648 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1649 } 1650 mutex_unlock(&mbox->lock); 1651 } 1652 1653 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1654 { 1655 struct net_device *netdev = pf->netdev; 1656 struct nix_rx_mode *req; 1657 bool promisc = false; 1658 1659 if (!(netdev->flags & IFF_UP)) 1660 return; 1661 1662 if ((netdev->flags & IFF_PROMISC) || 1663 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1664 promisc = true; 1665 } 1666 1667 /* Write unicast address to mcam entries or del from mcam */ 1668 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1669 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1670 1671 mutex_lock(&pf->mbox.lock); 1672 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1673 if (!req) { 1674 mutex_unlock(&pf->mbox.lock); 1675 return; 1676 } 1677 1678 req->mode = NIX_RX_MODE_UCAST; 1679 1680 if (promisc) 1681 req->mode |= NIX_RX_MODE_PROMISC; 1682 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1683 req->mode |= NIX_RX_MODE_ALLMULTI; 1684 1685 req->mode |= NIX_RX_MODE_USE_MCE; 1686 1687 otx2_sync_mbox_msg(&pf->mbox); 1688 mutex_unlock(&pf->mbox.lock); 1689 } 1690 1691 static void otx2_dim_work(struct work_struct *w) 1692 { 1693 struct dim_cq_moder cur_moder; 1694 struct otx2_cq_poll *cq_poll; 1695 struct otx2_nic *pfvf; 1696 struct dim *dim; 1697 1698 dim = container_of(w, struct dim, work); 1699 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1700 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1701 pfvf = (struct otx2_nic *)cq_poll->dev; 1702 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1703 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1704 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1705 NAPI_POLL_WEIGHT : cur_moder.pkts; 1706 dim->state = DIM_START_MEASURE; 1707 } 1708 1709 int otx2_open(struct net_device *netdev) 1710 { 1711 struct otx2_nic *pf = netdev_priv(netdev); 1712 struct otx2_cq_poll *cq_poll = NULL; 1713 struct otx2_qset *qset = &pf->qset; 1714 int err = 0, qidx, vec; 1715 char *irq_name; 1716 1717 netif_carrier_off(netdev); 1718 1719 /* RQ and SQs are mapped to different CQs, 1720 * so find out max CQ IRQs (i.e CINTs) needed. 1721 */ 1722 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1723 pf->hw.tc_tx_queues); 1724 1725 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1726 1727 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1728 if (!qset->napi) 1729 return -ENOMEM; 1730 1731 /* CQ size of RQ */ 1732 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1733 /* CQ size of SQ */ 1734 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1735 1736 err = -ENOMEM; 1737 qset->cq = kcalloc(pf->qset.cq_cnt, 1738 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1739 if (!qset->cq) 1740 goto err_free_mem; 1741 1742 qset->sq = kcalloc(otx2_get_total_tx_queues(pf), 1743 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1744 if (!qset->sq) 1745 goto err_free_mem; 1746 1747 qset->rq = kcalloc(pf->hw.rx_queues, 1748 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1749 if (!qset->rq) 1750 goto err_free_mem; 1751 1752 err = otx2_init_hw_resources(pf); 1753 if (err) 1754 goto err_free_mem; 1755 1756 /* Register NAPI handler */ 1757 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1758 cq_poll = &qset->napi[qidx]; 1759 cq_poll->cint_idx = qidx; 1760 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1761 * 'cq_ids[0]' points to RQ's CQ and 1762 * 'cq_ids[1]' points to SQ's CQ and 1763 * 'cq_ids[2]' points to XDP's CQ and 1764 */ 1765 cq_poll->cq_ids[CQ_RX] = 1766 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1767 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1768 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1769 if (pf->xdp_prog) 1770 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1771 (qidx + pf->hw.rx_queues + 1772 pf->hw.tx_queues) : 1773 CINT_INVALID_CQ; 1774 else 1775 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1776 1777 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 1778 (qidx + pf->hw.rx_queues + 1779 pf->hw.non_qos_queues) : 1780 CINT_INVALID_CQ; 1781 1782 cq_poll->dev = (void *)pf; 1783 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1784 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1785 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1786 napi_enable(&cq_poll->napi); 1787 } 1788 1789 /* Set maximum frame size allowed in HW */ 1790 err = otx2_hw_set_mtu(pf, netdev->mtu); 1791 if (err) 1792 goto err_disable_napi; 1793 1794 /* Setup segmentation algorithms, if failed, clear offload capability */ 1795 otx2_setup_segmentation(pf); 1796 1797 /* Initialize RSS */ 1798 err = otx2_rss_init(pf); 1799 if (err) 1800 goto err_disable_napi; 1801 1802 /* Register Queue IRQ handlers */ 1803 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1804 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1805 1806 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1807 1808 err = request_irq(pci_irq_vector(pf->pdev, vec), 1809 otx2_q_intr_handler, 0, irq_name, pf); 1810 if (err) { 1811 dev_err(pf->dev, 1812 "RVUPF%d: IRQ registration failed for QERR\n", 1813 rvu_get_pf(pf->pcifunc)); 1814 goto err_disable_napi; 1815 } 1816 1817 /* Enable QINT IRQ */ 1818 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1819 1820 /* Register CQ IRQ handlers */ 1821 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1822 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1823 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1824 1825 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1826 qidx); 1827 1828 err = request_irq(pci_irq_vector(pf->pdev, vec), 1829 otx2_cq_intr_handler, 0, irq_name, 1830 &qset->napi[qidx]); 1831 if (err) { 1832 dev_err(pf->dev, 1833 "RVUPF%d: IRQ registration failed for CQ%d\n", 1834 rvu_get_pf(pf->pcifunc), qidx); 1835 goto err_free_cints; 1836 } 1837 vec++; 1838 1839 otx2_config_irq_coalescing(pf, qidx); 1840 1841 /* Enable CQ IRQ */ 1842 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1843 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1844 } 1845 1846 otx2_set_cints_affinity(pf); 1847 1848 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1849 otx2_enable_rxvlan(pf, true); 1850 1851 /* When reinitializing enable time stamping if it is enabled before */ 1852 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1853 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1854 otx2_config_hw_tx_tstamp(pf, true); 1855 } 1856 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1857 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1858 otx2_config_hw_rx_tstamp(pf, true); 1859 } 1860 1861 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1862 /* 'intf_down' may be checked on any cpu */ 1863 smp_wmb(); 1864 1865 /* Enable QoS configuration before starting tx queues */ 1866 otx2_qos_config_txschq(pf); 1867 1868 /* we have already received link status notification */ 1869 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1870 otx2_handle_link_event(pf); 1871 1872 /* Install DMAC Filters */ 1873 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1874 otx2_dmacflt_reinstall_flows(pf); 1875 1876 otx2_tc_apply_ingress_police_rules(pf); 1877 1878 err = otx2_rxtx_enable(pf, true); 1879 /* If a mbox communication error happens at this point then interface 1880 * will end up in a state such that it is in down state but hardware 1881 * mcam entries are enabled to receive the packets. Hence disable the 1882 * packet I/O. 1883 */ 1884 if (err == EIO) 1885 goto err_disable_rxtx; 1886 else if (err) 1887 goto err_tx_stop_queues; 1888 1889 otx2_do_set_rx_mode(pf); 1890 1891 return 0; 1892 1893 err_disable_rxtx: 1894 otx2_rxtx_enable(pf, false); 1895 err_tx_stop_queues: 1896 netif_tx_stop_all_queues(netdev); 1897 netif_carrier_off(netdev); 1898 pf->flags |= OTX2_FLAG_INTF_DOWN; 1899 err_free_cints: 1900 otx2_free_cints(pf, qidx); 1901 vec = pci_irq_vector(pf->pdev, 1902 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1903 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1904 free_irq(vec, pf); 1905 err_disable_napi: 1906 otx2_disable_napi(pf); 1907 otx2_free_hw_resources(pf); 1908 err_free_mem: 1909 kfree(qset->sq); 1910 kfree(qset->cq); 1911 kfree(qset->rq); 1912 kfree(qset->napi); 1913 return err; 1914 } 1915 EXPORT_SYMBOL(otx2_open); 1916 1917 int otx2_stop(struct net_device *netdev) 1918 { 1919 struct otx2_nic *pf = netdev_priv(netdev); 1920 struct otx2_cq_poll *cq_poll = NULL; 1921 struct otx2_qset *qset = &pf->qset; 1922 struct otx2_rss_info *rss; 1923 int qidx, vec, wrk; 1924 1925 /* If the DOWN flag is set resources are already freed */ 1926 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1927 return 0; 1928 1929 netif_carrier_off(netdev); 1930 netif_tx_stop_all_queues(netdev); 1931 1932 pf->flags |= OTX2_FLAG_INTF_DOWN; 1933 /* 'intf_down' may be checked on any cpu */ 1934 smp_wmb(); 1935 1936 /* First stop packet Rx/Tx */ 1937 otx2_rxtx_enable(pf, false); 1938 1939 /* Clear RSS enable flag */ 1940 rss = &pf->hw.rss_info; 1941 rss->enable = false; 1942 if (!netif_is_rxfh_configured(netdev)) 1943 kfree(rss->rss_ctx[DEFAULT_RSS_CONTEXT_GROUP]); 1944 1945 /* Cleanup Queue IRQ */ 1946 vec = pci_irq_vector(pf->pdev, 1947 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1948 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1949 free_irq(vec, pf); 1950 1951 /* Cleanup CQ NAPI and IRQ */ 1952 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1953 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1954 /* Disable interrupt */ 1955 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1956 1957 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1958 1959 cq_poll = &qset->napi[qidx]; 1960 napi_synchronize(&cq_poll->napi); 1961 vec++; 1962 } 1963 1964 netif_tx_disable(netdev); 1965 1966 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1967 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1968 devm_kfree(pf->dev, pf->refill_wrk); 1969 1970 otx2_free_hw_resources(pf); 1971 otx2_free_cints(pf, pf->hw.cint_cnt); 1972 otx2_disable_napi(pf); 1973 1974 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1975 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1976 1977 1978 kfree(qset->sq); 1979 kfree(qset->cq); 1980 kfree(qset->rq); 1981 kfree(qset->napi); 1982 /* Do not clear RQ/SQ ringsize settings */ 1983 memset_startat(qset, 0, sqe_cnt); 1984 return 0; 1985 } 1986 EXPORT_SYMBOL(otx2_stop); 1987 1988 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1989 { 1990 struct otx2_nic *pf = netdev_priv(netdev); 1991 int qidx = skb_get_queue_mapping(skb); 1992 struct otx2_snd_queue *sq; 1993 struct netdev_queue *txq; 1994 int sq_idx; 1995 1996 /* XDP SQs are not mapped with TXQs 1997 * advance qid to derive correct sq mapped with QOS 1998 */ 1999 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2000 2001 /* Check for minimum and maximum packet length */ 2002 if (skb->len <= ETH_HLEN || 2003 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2004 dev_kfree_skb(skb); 2005 return NETDEV_TX_OK; 2006 } 2007 2008 sq = &pf->qset.sq[sq_idx]; 2009 txq = netdev_get_tx_queue(netdev, qidx); 2010 2011 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 2012 netif_tx_stop_queue(txq); 2013 2014 /* Check again, incase SQBs got freed up */ 2015 smp_mb(); 2016 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2017 > sq->sqe_thresh) 2018 netif_tx_wake_queue(txq); 2019 2020 return NETDEV_TX_BUSY; 2021 } 2022 2023 return NETDEV_TX_OK; 2024 } 2025 2026 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2027 u16 htb_maj_id) 2028 { 2029 u16 classid; 2030 2031 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2032 classid = TC_H_MIN(skb->priority); 2033 else 2034 classid = READ_ONCE(pf->qos.defcls); 2035 2036 if (!classid) 2037 return 0; 2038 2039 return otx2_get_txq_by_classid(pf, classid); 2040 } 2041 2042 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2043 struct net_device *sb_dev) 2044 { 2045 struct otx2_nic *pf = netdev_priv(netdev); 2046 bool qos_enabled; 2047 #ifdef CONFIG_DCB 2048 u8 vlan_prio; 2049 #endif 2050 int txq; 2051 2052 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2053 if (unlikely(qos_enabled)) { 2054 /* This smp_load_acquire() pairs with smp_store_release() in 2055 * otx2_qos_root_add() called from htb offload root creation 2056 */ 2057 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2058 2059 if (unlikely(htb_maj_id)) { 2060 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2061 if (txq > 0) 2062 return txq; 2063 goto process_pfc; 2064 } 2065 } 2066 2067 process_pfc: 2068 #ifdef CONFIG_DCB 2069 if (!skb_vlan_tag_present(skb)) 2070 goto pick_tx; 2071 2072 vlan_prio = skb->vlan_tci >> 13; 2073 if ((vlan_prio > pf->hw.tx_queues - 1) || 2074 !pf->pfc_alloc_status[vlan_prio]) 2075 goto pick_tx; 2076 2077 return vlan_prio; 2078 2079 pick_tx: 2080 #endif 2081 txq = netdev_pick_tx(netdev, skb, NULL); 2082 if (unlikely(qos_enabled)) 2083 return txq % pf->hw.tx_queues; 2084 2085 return txq; 2086 } 2087 EXPORT_SYMBOL(otx2_select_queue); 2088 2089 static netdev_features_t otx2_fix_features(struct net_device *dev, 2090 netdev_features_t features) 2091 { 2092 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2093 features |= NETIF_F_HW_VLAN_STAG_RX; 2094 else 2095 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2096 2097 return features; 2098 } 2099 2100 static void otx2_set_rx_mode(struct net_device *netdev) 2101 { 2102 struct otx2_nic *pf = netdev_priv(netdev); 2103 2104 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2105 } 2106 2107 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2108 { 2109 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2110 2111 otx2_do_set_rx_mode(pf); 2112 } 2113 2114 static int otx2_set_features(struct net_device *netdev, 2115 netdev_features_t features) 2116 { 2117 netdev_features_t changed = features ^ netdev->features; 2118 struct otx2_nic *pf = netdev_priv(netdev); 2119 2120 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2121 return otx2_cgx_config_loopback(pf, 2122 features & NETIF_F_LOOPBACK); 2123 2124 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2125 return otx2_enable_rxvlan(pf, 2126 features & NETIF_F_HW_VLAN_CTAG_RX); 2127 2128 return otx2_handle_ntuple_tc_features(netdev, features); 2129 } 2130 2131 static void otx2_reset_task(struct work_struct *work) 2132 { 2133 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2134 2135 if (!netif_running(pf->netdev)) 2136 return; 2137 2138 rtnl_lock(); 2139 otx2_stop(pf->netdev); 2140 pf->reset_count++; 2141 otx2_open(pf->netdev); 2142 netif_trans_update(pf->netdev); 2143 rtnl_unlock(); 2144 } 2145 2146 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2147 { 2148 struct msg_req *req; 2149 int err; 2150 2151 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2152 return 0; 2153 2154 mutex_lock(&pfvf->mbox.lock); 2155 if (enable) 2156 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2157 else 2158 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2159 if (!req) { 2160 mutex_unlock(&pfvf->mbox.lock); 2161 return -ENOMEM; 2162 } 2163 2164 err = otx2_sync_mbox_msg(&pfvf->mbox); 2165 if (err) { 2166 mutex_unlock(&pfvf->mbox.lock); 2167 return err; 2168 } 2169 2170 mutex_unlock(&pfvf->mbox.lock); 2171 if (enable) 2172 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2173 else 2174 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2175 return 0; 2176 } 2177 2178 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2179 { 2180 struct msg_req *req; 2181 int err; 2182 2183 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2184 return 0; 2185 2186 mutex_lock(&pfvf->mbox.lock); 2187 if (enable) 2188 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2189 else 2190 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2191 if (!req) { 2192 mutex_unlock(&pfvf->mbox.lock); 2193 return -ENOMEM; 2194 } 2195 2196 err = otx2_sync_mbox_msg(&pfvf->mbox); 2197 if (err) { 2198 mutex_unlock(&pfvf->mbox.lock); 2199 return err; 2200 } 2201 2202 mutex_unlock(&pfvf->mbox.lock); 2203 if (enable) 2204 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2205 else 2206 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2207 return 0; 2208 } 2209 2210 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2211 { 2212 struct otx2_nic *pfvf = netdev_priv(netdev); 2213 struct hwtstamp_config config; 2214 2215 if (!pfvf->ptp) 2216 return -ENODEV; 2217 2218 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2219 return -EFAULT; 2220 2221 switch (config.tx_type) { 2222 case HWTSTAMP_TX_OFF: 2223 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2224 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2225 2226 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2227 otx2_config_hw_tx_tstamp(pfvf, false); 2228 break; 2229 case HWTSTAMP_TX_ONESTEP_SYNC: 2230 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2231 return -ERANGE; 2232 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2233 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2234 msecs_to_jiffies(500)); 2235 fallthrough; 2236 case HWTSTAMP_TX_ON: 2237 otx2_config_hw_tx_tstamp(pfvf, true); 2238 break; 2239 default: 2240 return -ERANGE; 2241 } 2242 2243 switch (config.rx_filter) { 2244 case HWTSTAMP_FILTER_NONE: 2245 otx2_config_hw_rx_tstamp(pfvf, false); 2246 break; 2247 case HWTSTAMP_FILTER_ALL: 2248 case HWTSTAMP_FILTER_SOME: 2249 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2250 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2251 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2252 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2253 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2254 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2255 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2256 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2257 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2258 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2259 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2260 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2261 otx2_config_hw_rx_tstamp(pfvf, true); 2262 config.rx_filter = HWTSTAMP_FILTER_ALL; 2263 break; 2264 default: 2265 return -ERANGE; 2266 } 2267 2268 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2269 2270 return copy_to_user(ifr->ifr_data, &config, 2271 sizeof(config)) ? -EFAULT : 0; 2272 } 2273 EXPORT_SYMBOL(otx2_config_hwtstamp); 2274 2275 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2276 { 2277 struct otx2_nic *pfvf = netdev_priv(netdev); 2278 struct hwtstamp_config *cfg = &pfvf->tstamp; 2279 2280 switch (cmd) { 2281 case SIOCSHWTSTAMP: 2282 return otx2_config_hwtstamp(netdev, req); 2283 case SIOCGHWTSTAMP: 2284 return copy_to_user(req->ifr_data, cfg, 2285 sizeof(*cfg)) ? -EFAULT : 0; 2286 default: 2287 return -EOPNOTSUPP; 2288 } 2289 } 2290 EXPORT_SYMBOL(otx2_ioctl); 2291 2292 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2293 { 2294 struct npc_install_flow_req *req; 2295 int err; 2296 2297 mutex_lock(&pf->mbox.lock); 2298 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2299 if (!req) { 2300 err = -ENOMEM; 2301 goto out; 2302 } 2303 2304 ether_addr_copy(req->packet.dmac, mac); 2305 eth_broadcast_addr((u8 *)&req->mask.dmac); 2306 req->features = BIT_ULL(NPC_DMAC); 2307 req->channel = pf->hw.rx_chan_base; 2308 req->intf = NIX_INTF_RX; 2309 req->default_rule = 1; 2310 req->append = 1; 2311 req->vf = vf + 1; 2312 req->op = NIX_RX_ACTION_DEFAULT; 2313 2314 err = otx2_sync_mbox_msg(&pf->mbox); 2315 out: 2316 mutex_unlock(&pf->mbox.lock); 2317 return err; 2318 } 2319 2320 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2321 { 2322 struct otx2_nic *pf = netdev_priv(netdev); 2323 struct pci_dev *pdev = pf->pdev; 2324 struct otx2_vf_config *config; 2325 int ret; 2326 2327 if (!netif_running(netdev)) 2328 return -EAGAIN; 2329 2330 if (vf >= pf->total_vfs) 2331 return -EINVAL; 2332 2333 if (!is_valid_ether_addr(mac)) 2334 return -EINVAL; 2335 2336 config = &pf->vf_configs[vf]; 2337 ether_addr_copy(config->mac, mac); 2338 2339 ret = otx2_do_set_vf_mac(pf, vf, mac); 2340 if (ret == 0) 2341 dev_info(&pdev->dev, 2342 "Load/Reload VF driver\n"); 2343 2344 return ret; 2345 } 2346 2347 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2348 __be16 proto) 2349 { 2350 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2351 struct nix_vtag_config_rsp *vtag_rsp; 2352 struct npc_delete_flow_req *del_req; 2353 struct nix_vtag_config *vtag_req; 2354 struct npc_install_flow_req *req; 2355 struct otx2_vf_config *config; 2356 int err = 0; 2357 u32 idx; 2358 2359 config = &pf->vf_configs[vf]; 2360 2361 if (!vlan && !config->vlan) 2362 goto out; 2363 2364 mutex_lock(&pf->mbox.lock); 2365 2366 /* free old tx vtag entry */ 2367 if (config->vlan) { 2368 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2369 if (!vtag_req) { 2370 err = -ENOMEM; 2371 goto out; 2372 } 2373 vtag_req->cfg_type = 0; 2374 vtag_req->tx.free_vtag0 = 1; 2375 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2376 2377 err = otx2_sync_mbox_msg(&pf->mbox); 2378 if (err) 2379 goto out; 2380 } 2381 2382 if (!vlan && config->vlan) { 2383 /* rx */ 2384 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2385 if (!del_req) { 2386 err = -ENOMEM; 2387 goto out; 2388 } 2389 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2390 del_req->entry = 2391 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2392 err = otx2_sync_mbox_msg(&pf->mbox); 2393 if (err) 2394 goto out; 2395 2396 /* tx */ 2397 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2398 if (!del_req) { 2399 err = -ENOMEM; 2400 goto out; 2401 } 2402 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2403 del_req->entry = 2404 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2405 err = otx2_sync_mbox_msg(&pf->mbox); 2406 2407 goto out; 2408 } 2409 2410 /* rx */ 2411 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2412 if (!req) { 2413 err = -ENOMEM; 2414 goto out; 2415 } 2416 2417 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2418 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2419 req->packet.vlan_tci = htons(vlan); 2420 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2421 /* af fills the destination mac addr */ 2422 eth_broadcast_addr((u8 *)&req->mask.dmac); 2423 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2424 req->channel = pf->hw.rx_chan_base; 2425 req->intf = NIX_INTF_RX; 2426 req->vf = vf + 1; 2427 req->op = NIX_RX_ACTION_DEFAULT; 2428 req->vtag0_valid = true; 2429 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2430 req->set_cntr = 1; 2431 2432 err = otx2_sync_mbox_msg(&pf->mbox); 2433 if (err) 2434 goto out; 2435 2436 /* tx */ 2437 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2438 if (!vtag_req) { 2439 err = -ENOMEM; 2440 goto out; 2441 } 2442 2443 /* configure tx vtag params */ 2444 vtag_req->vtag_size = VTAGSIZE_T4; 2445 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2446 vtag_req->tx.cfg_vtag0 = 1; 2447 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2448 2449 err = otx2_sync_mbox_msg(&pf->mbox); 2450 if (err) 2451 goto out; 2452 2453 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2454 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2455 if (IS_ERR(vtag_rsp)) { 2456 err = PTR_ERR(vtag_rsp); 2457 goto out; 2458 } 2459 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2460 2461 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2462 if (!req) { 2463 err = -ENOMEM; 2464 goto out; 2465 } 2466 2467 eth_zero_addr((u8 *)&req->mask.dmac); 2468 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2469 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2470 req->features = BIT_ULL(NPC_DMAC); 2471 req->channel = pf->hw.tx_chan_base; 2472 req->intf = NIX_INTF_TX; 2473 req->vf = vf + 1; 2474 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2475 req->vtag0_def = vtag_rsp->vtag0_idx; 2476 req->vtag0_op = VTAG_INSERT; 2477 req->set_cntr = 1; 2478 2479 err = otx2_sync_mbox_msg(&pf->mbox); 2480 out: 2481 config->vlan = vlan; 2482 mutex_unlock(&pf->mbox.lock); 2483 return err; 2484 } 2485 2486 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2487 __be16 proto) 2488 { 2489 struct otx2_nic *pf = netdev_priv(netdev); 2490 struct pci_dev *pdev = pf->pdev; 2491 2492 if (!netif_running(netdev)) 2493 return -EAGAIN; 2494 2495 if (vf >= pci_num_vf(pdev)) 2496 return -EINVAL; 2497 2498 /* qos is currently unsupported */ 2499 if (vlan >= VLAN_N_VID || qos) 2500 return -EINVAL; 2501 2502 if (proto != htons(ETH_P_8021Q)) 2503 return -EPROTONOSUPPORT; 2504 2505 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2506 return -EOPNOTSUPP; 2507 2508 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2509 } 2510 2511 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2512 struct ifla_vf_info *ivi) 2513 { 2514 struct otx2_nic *pf = netdev_priv(netdev); 2515 struct pci_dev *pdev = pf->pdev; 2516 struct otx2_vf_config *config; 2517 2518 if (!netif_running(netdev)) 2519 return -EAGAIN; 2520 2521 if (vf >= pci_num_vf(pdev)) 2522 return -EINVAL; 2523 2524 config = &pf->vf_configs[vf]; 2525 ivi->vf = vf; 2526 ether_addr_copy(ivi->mac, config->mac); 2527 ivi->vlan = config->vlan; 2528 ivi->trusted = config->trusted; 2529 2530 return 0; 2531 } 2532 2533 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2534 int qidx) 2535 { 2536 struct page *page; 2537 u64 dma_addr; 2538 int err = 0; 2539 2540 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2541 offset_in_page(xdpf->data), xdpf->len, 2542 DMA_TO_DEVICE); 2543 if (dma_mapping_error(pf->dev, dma_addr)) 2544 return -ENOMEM; 2545 2546 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2547 if (!err) { 2548 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2549 page = virt_to_page(xdpf->data); 2550 put_page(page); 2551 return -ENOMEM; 2552 } 2553 return 0; 2554 } 2555 2556 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2557 struct xdp_frame **frames, u32 flags) 2558 { 2559 struct otx2_nic *pf = netdev_priv(netdev); 2560 int qidx = smp_processor_id(); 2561 struct otx2_snd_queue *sq; 2562 int drops = 0, i; 2563 2564 if (!netif_running(netdev)) 2565 return -ENETDOWN; 2566 2567 qidx += pf->hw.tx_queues; 2568 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2569 2570 /* Abort xmit if xdp queue is not */ 2571 if (unlikely(!sq)) 2572 return -ENXIO; 2573 2574 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2575 return -EINVAL; 2576 2577 for (i = 0; i < n; i++) { 2578 struct xdp_frame *xdpf = frames[i]; 2579 int err; 2580 2581 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2582 if (err) 2583 drops++; 2584 } 2585 return n - drops; 2586 } 2587 2588 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2589 { 2590 struct net_device *dev = pf->netdev; 2591 bool if_up = netif_running(pf->netdev); 2592 struct bpf_prog *old_prog; 2593 2594 if (prog && dev->mtu > MAX_XDP_MTU) { 2595 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (if_up) 2600 otx2_stop(pf->netdev); 2601 2602 old_prog = xchg(&pf->xdp_prog, prog); 2603 2604 if (old_prog) 2605 bpf_prog_put(old_prog); 2606 2607 if (pf->xdp_prog) 2608 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2609 2610 /* Network stack and XDP shared same rx queues. 2611 * Use separate tx queues for XDP and network stack. 2612 */ 2613 if (pf->xdp_prog) { 2614 pf->hw.xdp_queues = pf->hw.rx_queues; 2615 xdp_features_set_redirect_target(dev, false); 2616 } else { 2617 pf->hw.xdp_queues = 0; 2618 xdp_features_clear_redirect_target(dev); 2619 } 2620 2621 pf->hw.non_qos_queues += pf->hw.xdp_queues; 2622 2623 if (if_up) 2624 otx2_open(pf->netdev); 2625 2626 return 0; 2627 } 2628 2629 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2630 { 2631 struct otx2_nic *pf = netdev_priv(netdev); 2632 2633 switch (xdp->command) { 2634 case XDP_SETUP_PROG: 2635 return otx2_xdp_setup(pf, xdp->prog); 2636 default: 2637 return -EINVAL; 2638 } 2639 } 2640 2641 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2642 int req_perm) 2643 { 2644 struct set_vf_perm *req; 2645 int rc; 2646 2647 mutex_lock(&pf->mbox.lock); 2648 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2649 if (!req) { 2650 rc = -ENOMEM; 2651 goto out; 2652 } 2653 2654 /* Let AF reset VF permissions as sriov is disabled */ 2655 if (req_perm == OTX2_RESET_VF_PERM) { 2656 req->flags |= RESET_VF_PERM; 2657 } else if (req_perm == OTX2_TRUSTED_VF) { 2658 if (pf->vf_configs[vf].trusted) 2659 req->flags |= VF_TRUSTED; 2660 } 2661 2662 req->vf = vf; 2663 rc = otx2_sync_mbox_msg(&pf->mbox); 2664 out: 2665 mutex_unlock(&pf->mbox.lock); 2666 return rc; 2667 } 2668 2669 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2670 bool enable) 2671 { 2672 struct otx2_nic *pf = netdev_priv(netdev); 2673 struct pci_dev *pdev = pf->pdev; 2674 int rc; 2675 2676 if (vf >= pci_num_vf(pdev)) 2677 return -EINVAL; 2678 2679 if (pf->vf_configs[vf].trusted == enable) 2680 return 0; 2681 2682 pf->vf_configs[vf].trusted = enable; 2683 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2684 2685 if (rc) 2686 pf->vf_configs[vf].trusted = !enable; 2687 else 2688 netdev_info(pf->netdev, "VF %d is %strusted\n", 2689 vf, enable ? "" : "not "); 2690 return rc; 2691 } 2692 2693 static const struct net_device_ops otx2_netdev_ops = { 2694 .ndo_open = otx2_open, 2695 .ndo_stop = otx2_stop, 2696 .ndo_start_xmit = otx2_xmit, 2697 .ndo_select_queue = otx2_select_queue, 2698 .ndo_fix_features = otx2_fix_features, 2699 .ndo_set_mac_address = otx2_set_mac_address, 2700 .ndo_change_mtu = otx2_change_mtu, 2701 .ndo_set_rx_mode = otx2_set_rx_mode, 2702 .ndo_set_features = otx2_set_features, 2703 .ndo_tx_timeout = otx2_tx_timeout, 2704 .ndo_get_stats64 = otx2_get_stats64, 2705 .ndo_eth_ioctl = otx2_ioctl, 2706 .ndo_set_vf_mac = otx2_set_vf_mac, 2707 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2708 .ndo_get_vf_config = otx2_get_vf_config, 2709 .ndo_bpf = otx2_xdp, 2710 .ndo_xdp_xmit = otx2_xdp_xmit, 2711 .ndo_setup_tc = otx2_setup_tc, 2712 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2713 }; 2714 2715 static int otx2_wq_init(struct otx2_nic *pf) 2716 { 2717 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2718 if (!pf->otx2_wq) 2719 return -ENOMEM; 2720 2721 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2722 INIT_WORK(&pf->reset_task, otx2_reset_task); 2723 return 0; 2724 } 2725 2726 static int otx2_check_pf_usable(struct otx2_nic *nic) 2727 { 2728 u64 rev; 2729 2730 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2731 rev = (rev >> 12) & 0xFF; 2732 /* Check if AF has setup revision for RVUM block, 2733 * otherwise this driver probe should be deferred 2734 * until AF driver comes up. 2735 */ 2736 if (!rev) { 2737 dev_warn(nic->dev, 2738 "AF is not initialized, deferring probe\n"); 2739 return -EPROBE_DEFER; 2740 } 2741 return 0; 2742 } 2743 2744 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2745 { 2746 struct otx2_hw *hw = &pf->hw; 2747 int num_vec, err; 2748 2749 /* NPA interrupts are inot registered, so alloc only 2750 * upto NIX vector offset. 2751 */ 2752 num_vec = hw->nix_msixoff; 2753 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2754 2755 otx2_disable_mbox_intr(pf); 2756 pci_free_irq_vectors(hw->pdev); 2757 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2758 if (err < 0) { 2759 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2760 __func__, num_vec); 2761 return err; 2762 } 2763 2764 return otx2_register_mbox_intr(pf, false); 2765 } 2766 2767 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2768 { 2769 int i; 2770 2771 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2772 sizeof(struct otx2_vf_config), 2773 GFP_KERNEL); 2774 if (!pf->vf_configs) 2775 return -ENOMEM; 2776 2777 for (i = 0; i < pf->total_vfs; i++) { 2778 pf->vf_configs[i].pf = pf; 2779 pf->vf_configs[i].intf_down = true; 2780 pf->vf_configs[i].trusted = false; 2781 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2782 otx2_vf_link_event_task); 2783 } 2784 2785 return 0; 2786 } 2787 2788 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2789 { 2790 int i; 2791 2792 if (!pf->vf_configs) 2793 return; 2794 2795 for (i = 0; i < pf->total_vfs; i++) { 2796 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2797 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2798 } 2799 } 2800 2801 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2802 { 2803 struct device *dev = &pdev->dev; 2804 int err, qcount, qos_txqs; 2805 struct net_device *netdev; 2806 struct otx2_nic *pf; 2807 struct otx2_hw *hw; 2808 int num_vec; 2809 2810 err = pcim_enable_device(pdev); 2811 if (err) { 2812 dev_err(dev, "Failed to enable PCI device\n"); 2813 return err; 2814 } 2815 2816 err = pci_request_regions(pdev, DRV_NAME); 2817 if (err) { 2818 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2819 return err; 2820 } 2821 2822 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2823 if (err) { 2824 dev_err(dev, "DMA mask config failed, abort\n"); 2825 goto err_release_regions; 2826 } 2827 2828 pci_set_master(pdev); 2829 2830 /* Set number of queues */ 2831 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2832 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 2833 2834 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 2835 if (!netdev) { 2836 err = -ENOMEM; 2837 goto err_release_regions; 2838 } 2839 2840 pci_set_drvdata(pdev, netdev); 2841 SET_NETDEV_DEV(netdev, &pdev->dev); 2842 pf = netdev_priv(netdev); 2843 pf->netdev = netdev; 2844 pf->pdev = pdev; 2845 pf->dev = dev; 2846 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2847 pf->flags |= OTX2_FLAG_INTF_DOWN; 2848 2849 hw = &pf->hw; 2850 hw->pdev = pdev; 2851 hw->rx_queues = qcount; 2852 hw->tx_queues = qcount; 2853 hw->non_qos_queues = qcount; 2854 hw->max_queues = qcount; 2855 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2856 /* Use CQE of 128 byte descriptor size by default */ 2857 hw->xqe_size = 128; 2858 2859 num_vec = pci_msix_vec_count(pdev); 2860 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2861 GFP_KERNEL); 2862 if (!hw->irq_name) { 2863 err = -ENOMEM; 2864 goto err_free_netdev; 2865 } 2866 2867 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2868 sizeof(cpumask_var_t), GFP_KERNEL); 2869 if (!hw->affinity_mask) { 2870 err = -ENOMEM; 2871 goto err_free_netdev; 2872 } 2873 2874 /* Map CSRs */ 2875 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2876 if (!pf->reg_base) { 2877 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2878 err = -ENOMEM; 2879 goto err_free_netdev; 2880 } 2881 2882 err = otx2_check_pf_usable(pf); 2883 if (err) 2884 goto err_free_netdev; 2885 2886 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2887 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2888 if (err < 0) { 2889 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2890 __func__, num_vec); 2891 goto err_free_netdev; 2892 } 2893 2894 otx2_setup_dev_hw_settings(pf); 2895 2896 /* Init PF <=> AF mailbox stuff */ 2897 err = otx2_pfaf_mbox_init(pf); 2898 if (err) 2899 goto err_free_irq_vectors; 2900 2901 /* Register mailbox interrupt */ 2902 err = otx2_register_mbox_intr(pf, true); 2903 if (err) 2904 goto err_mbox_destroy; 2905 2906 /* Request AF to attach NPA and NIX LFs to this PF. 2907 * NIX and NPA LFs are needed for this PF to function as a NIC. 2908 */ 2909 err = otx2_attach_npa_nix(pf); 2910 if (err) 2911 goto err_disable_mbox_intr; 2912 2913 err = otx2_realloc_msix_vectors(pf); 2914 if (err) 2915 goto err_detach_rsrc; 2916 2917 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2918 if (err) 2919 goto err_detach_rsrc; 2920 2921 err = cn10k_lmtst_init(pf); 2922 if (err) 2923 goto err_detach_rsrc; 2924 2925 /* Assign default mac address */ 2926 otx2_get_mac_from_af(netdev); 2927 2928 /* Don't check for error. Proceed without ptp */ 2929 otx2_ptp_init(pf); 2930 2931 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2932 * HW allocates buffer pointer from stack and uses it for DMA'ing 2933 * ingress packet. In some scenarios HW can free back allocated buffer 2934 * pointers to pool. This makes it impossible for SW to maintain a 2935 * parallel list where physical addresses of buffer pointers (IOVAs) 2936 * given to HW can be saved for later reference. 2937 * 2938 * So the only way to convert Rx packet's buffer address is to use 2939 * IOMMU's iova_to_phys() handler which translates the address by 2940 * walking through the translation tables. 2941 */ 2942 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2943 2944 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2945 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2946 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2947 NETIF_F_GSO_UDP_L4); 2948 netdev->features |= netdev->hw_features; 2949 2950 err = otx2_mcam_flow_init(pf); 2951 if (err) 2952 goto err_ptp_destroy; 2953 2954 err = cn10k_mcs_init(pf); 2955 if (err) 2956 goto err_del_mcam_entries; 2957 2958 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2959 netdev->hw_features |= NETIF_F_NTUPLE; 2960 2961 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2962 netdev->priv_flags |= IFF_UNICAST_FLT; 2963 2964 /* Support TSO on tag interface */ 2965 netdev->vlan_features |= netdev->features; 2966 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2967 NETIF_F_HW_VLAN_STAG_TX; 2968 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2969 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2970 NETIF_F_HW_VLAN_STAG_RX; 2971 netdev->features |= netdev->hw_features; 2972 2973 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2974 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2975 netdev->hw_features |= NETIF_F_HW_TC; 2976 2977 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2978 2979 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2980 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2981 2982 netdev->netdev_ops = &otx2_netdev_ops; 2983 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT; 2984 2985 netdev->min_mtu = OTX2_MIN_MTU; 2986 netdev->max_mtu = otx2_get_max_mtu(pf); 2987 2988 err = register_netdev(netdev); 2989 if (err) { 2990 dev_err(dev, "Failed to register netdevice\n"); 2991 goto err_mcs_free; 2992 } 2993 2994 err = otx2_wq_init(pf); 2995 if (err) 2996 goto err_unreg_netdev; 2997 2998 otx2_set_ethtool_ops(netdev); 2999 3000 err = otx2_init_tc(pf); 3001 if (err) 3002 goto err_mcam_flow_del; 3003 3004 err = otx2_register_dl(pf); 3005 if (err) 3006 goto err_mcam_flow_del; 3007 3008 /* Initialize SR-IOV resources */ 3009 err = otx2_sriov_vfcfg_init(pf); 3010 if (err) 3011 goto err_pf_sriov_init; 3012 3013 /* Enable link notifications */ 3014 otx2_cgx_config_linkevents(pf, true); 3015 3016 #ifdef CONFIG_DCB 3017 err = otx2_dcbnl_set_ops(netdev); 3018 if (err) 3019 goto err_pf_sriov_init; 3020 #endif 3021 3022 otx2_qos_init(pf, qos_txqs); 3023 3024 return 0; 3025 3026 err_pf_sriov_init: 3027 otx2_shutdown_tc(pf); 3028 err_mcam_flow_del: 3029 otx2_mcam_flow_del(pf); 3030 err_unreg_netdev: 3031 unregister_netdev(netdev); 3032 err_mcs_free: 3033 cn10k_mcs_free(pf); 3034 err_del_mcam_entries: 3035 otx2_mcam_flow_del(pf); 3036 err_ptp_destroy: 3037 otx2_ptp_destroy(pf); 3038 err_detach_rsrc: 3039 if (pf->hw.lmt_info) 3040 free_percpu(pf->hw.lmt_info); 3041 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3042 qmem_free(pf->dev, pf->dync_lmt); 3043 otx2_detach_resources(&pf->mbox); 3044 err_disable_mbox_intr: 3045 otx2_disable_mbox_intr(pf); 3046 err_mbox_destroy: 3047 otx2_pfaf_mbox_destroy(pf); 3048 err_free_irq_vectors: 3049 pci_free_irq_vectors(hw->pdev); 3050 err_free_netdev: 3051 pci_set_drvdata(pdev, NULL); 3052 free_netdev(netdev); 3053 err_release_regions: 3054 pci_release_regions(pdev); 3055 return err; 3056 } 3057 3058 static void otx2_vf_link_event_task(struct work_struct *work) 3059 { 3060 struct otx2_vf_config *config; 3061 struct cgx_link_info_msg *req; 3062 struct mbox_msghdr *msghdr; 3063 struct otx2_nic *pf; 3064 int vf_idx; 3065 3066 config = container_of(work, struct otx2_vf_config, 3067 link_event_work.work); 3068 vf_idx = config - config->pf->vf_configs; 3069 pf = config->pf; 3070 3071 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3072 sizeof(*req), sizeof(struct msg_rsp)); 3073 if (!msghdr) { 3074 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3075 return; 3076 } 3077 3078 req = (struct cgx_link_info_msg *)msghdr; 3079 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3080 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3081 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3082 3083 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3084 } 3085 3086 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3087 { 3088 struct net_device *netdev = pci_get_drvdata(pdev); 3089 struct otx2_nic *pf = netdev_priv(netdev); 3090 int ret; 3091 3092 /* Init PF <=> VF mailbox stuff */ 3093 ret = otx2_pfvf_mbox_init(pf, numvfs); 3094 if (ret) 3095 return ret; 3096 3097 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3098 if (ret) 3099 goto free_mbox; 3100 3101 ret = otx2_pf_flr_init(pf, numvfs); 3102 if (ret) 3103 goto free_intr; 3104 3105 ret = otx2_register_flr_me_intr(pf, numvfs); 3106 if (ret) 3107 goto free_flr; 3108 3109 ret = pci_enable_sriov(pdev, numvfs); 3110 if (ret) 3111 goto free_flr_intr; 3112 3113 return numvfs; 3114 free_flr_intr: 3115 otx2_disable_flr_me_intr(pf); 3116 free_flr: 3117 otx2_flr_wq_destroy(pf); 3118 free_intr: 3119 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3120 free_mbox: 3121 otx2_pfvf_mbox_destroy(pf); 3122 return ret; 3123 } 3124 3125 static int otx2_sriov_disable(struct pci_dev *pdev) 3126 { 3127 struct net_device *netdev = pci_get_drvdata(pdev); 3128 struct otx2_nic *pf = netdev_priv(netdev); 3129 int numvfs = pci_num_vf(pdev); 3130 3131 if (!numvfs) 3132 return 0; 3133 3134 pci_disable_sriov(pdev); 3135 3136 otx2_disable_flr_me_intr(pf); 3137 otx2_flr_wq_destroy(pf); 3138 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3139 otx2_pfvf_mbox_destroy(pf); 3140 3141 return 0; 3142 } 3143 3144 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3145 { 3146 if (numvfs == 0) 3147 return otx2_sriov_disable(pdev); 3148 else 3149 return otx2_sriov_enable(pdev, numvfs); 3150 } 3151 3152 static void otx2_remove(struct pci_dev *pdev) 3153 { 3154 struct net_device *netdev = pci_get_drvdata(pdev); 3155 struct otx2_nic *pf; 3156 3157 if (!netdev) 3158 return; 3159 3160 pf = netdev_priv(netdev); 3161 3162 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3163 3164 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3165 otx2_config_hw_tx_tstamp(pf, false); 3166 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3167 otx2_config_hw_rx_tstamp(pf, false); 3168 3169 /* Disable 802.3x pause frames */ 3170 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3171 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3172 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3173 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3174 otx2_config_pause_frm(pf); 3175 } 3176 3177 #ifdef CONFIG_DCB 3178 /* Disable PFC config */ 3179 if (pf->pfc_en) { 3180 pf->pfc_en = 0; 3181 otx2_config_priority_flow_ctrl(pf); 3182 } 3183 #endif 3184 cancel_work_sync(&pf->reset_task); 3185 /* Disable link notifications */ 3186 otx2_cgx_config_linkevents(pf, false); 3187 3188 otx2_unregister_dl(pf); 3189 unregister_netdev(netdev); 3190 cn10k_mcs_free(pf); 3191 otx2_sriov_disable(pf->pdev); 3192 otx2_sriov_vfcfg_cleanup(pf); 3193 if (pf->otx2_wq) 3194 destroy_workqueue(pf->otx2_wq); 3195 3196 otx2_ptp_destroy(pf); 3197 otx2_mcam_flow_del(pf); 3198 otx2_shutdown_tc(pf); 3199 otx2_shutdown_qos(pf); 3200 otx2_detach_resources(&pf->mbox); 3201 if (pf->hw.lmt_info) 3202 free_percpu(pf->hw.lmt_info); 3203 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3204 qmem_free(pf->dev, pf->dync_lmt); 3205 otx2_disable_mbox_intr(pf); 3206 otx2_pfaf_mbox_destroy(pf); 3207 pci_free_irq_vectors(pf->pdev); 3208 pci_set_drvdata(pdev, NULL); 3209 free_netdev(netdev); 3210 3211 pci_release_regions(pdev); 3212 } 3213 3214 static struct pci_driver otx2_pf_driver = { 3215 .name = DRV_NAME, 3216 .id_table = otx2_pf_id_table, 3217 .probe = otx2_probe, 3218 .shutdown = otx2_remove, 3219 .remove = otx2_remove, 3220 .sriov_configure = otx2_sriov_configure 3221 }; 3222 3223 static int __init otx2_rvupf_init_module(void) 3224 { 3225 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3226 3227 return pci_register_driver(&otx2_pf_driver); 3228 } 3229 3230 static void __exit otx2_rvupf_cleanup_module(void) 3231 { 3232 pci_unregister_driver(&otx2_pf_driver); 3233 } 3234 3235 module_init(otx2_rvupf_init_module); 3236 module_exit(otx2_rvupf_cleanup_module); 3237