1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 19 #include "otx2_reg.h" 20 #include "otx2_common.h" 21 #include "otx2_txrx.h" 22 #include "otx2_struct.h" 23 #include "otx2_ptp.h" 24 #include "cn10k.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "rvu_nicpf" 28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 static void otx2_vf_link_event_task(struct work_struct *work); 42 43 enum { 44 TYPE_PFAF, 45 TYPE_PFVF, 46 }; 47 48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 50 51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 52 { 53 struct otx2_nic *pf = netdev_priv(netdev); 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 59 netdev->mtu); 60 return -EINVAL; 61 } 62 if (if_up) 63 otx2_stop(netdev); 64 65 netdev_info(netdev, "Changing MTU from %d to %d\n", 66 netdev->mtu, new_mtu); 67 netdev->mtu = new_mtu; 68 69 if (if_up) 70 err = otx2_open(netdev); 71 72 return err; 73 } 74 75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 76 { 77 int irq, vfs = pf->total_vfs; 78 79 /* Disable VFs ME interrupts */ 80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 82 free_irq(irq, pf); 83 84 /* Disable VFs FLR interrupts */ 85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 87 free_irq(irq, pf); 88 89 if (vfs <= 64) 90 return; 91 92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 94 free_irq(irq, pf); 95 96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 98 free_irq(irq, pf); 99 } 100 101 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 102 { 103 if (!pf->flr_wq) 104 return; 105 destroy_workqueue(pf->flr_wq); 106 pf->flr_wq = NULL; 107 devm_kfree(pf->dev, pf->flr_wrk); 108 } 109 110 static void otx2_flr_handler(struct work_struct *work) 111 { 112 struct flr_work *flrwork = container_of(work, struct flr_work, work); 113 struct otx2_nic *pf = flrwork->pf; 114 struct mbox *mbox = &pf->mbox; 115 struct msg_req *req; 116 int vf, reg = 0; 117 118 vf = flrwork - pf->flr_wrk; 119 120 mutex_lock(&mbox->lock); 121 req = otx2_mbox_alloc_msg_vf_flr(mbox); 122 if (!req) { 123 mutex_unlock(&mbox->lock); 124 return; 125 } 126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 128 129 if (!otx2_sync_mbox_msg(&pf->mbox)) { 130 if (vf >= 64) { 131 reg = 1; 132 vf = vf - 64; 133 } 134 /* clear transcation pending bit */ 135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 137 } 138 139 mutex_unlock(&mbox->lock); 140 } 141 142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 143 { 144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 145 int reg, dev, vf, start_vf, num_reg = 1; 146 u64 intr; 147 148 if (pf->total_vfs > 64) 149 num_reg = 2; 150 151 for (reg = 0; reg < num_reg; reg++) { 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 153 if (!intr) 154 continue; 155 start_vf = 64 * reg; 156 for (vf = 0; vf < 64; vf++) { 157 if (!(intr & BIT_ULL(vf))) 158 continue; 159 dev = vf + start_vf; 160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 161 /* Clear interrupt */ 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 163 /* Disable the interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 165 BIT_ULL(vf)); 166 } 167 } 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 172 { 173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 174 int vf, reg, num_reg = 1; 175 u64 intr; 176 177 if (pf->total_vfs > 64) 178 num_reg = 2; 179 180 for (reg = 0; reg < num_reg; reg++) { 181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 182 if (!intr) 183 continue; 184 for (vf = 0; vf < 64; vf++) { 185 if (!(intr & BIT_ULL(vf))) 186 continue; 187 /* clear trpend bit */ 188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 189 /* clear interrupt */ 190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 191 } 192 } 193 return IRQ_HANDLED; 194 } 195 196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 197 { 198 struct otx2_hw *hw = &pf->hw; 199 char *irq_name; 200 int ret; 201 202 /* Register ME interrupt handler*/ 203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 206 otx2_pf_me_intr_handler, 0, irq_name, pf); 207 if (ret) { 208 dev_err(pf->dev, 209 "RVUPF: IRQ registration failed for ME0\n"); 210 } 211 212 /* Register FLR interrupt handler */ 213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 216 otx2_pf_flr_intr_handler, 0, irq_name, pf); 217 if (ret) { 218 dev_err(pf->dev, 219 "RVUPF: IRQ registration failed for FLR0\n"); 220 return ret; 221 } 222 223 if (numvfs > 64) { 224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 226 rvu_get_pf(pf->pcifunc)); 227 ret = request_irq(pci_irq_vector 228 (pf->pdev, RVU_PF_INT_VEC_VFME1), 229 otx2_pf_me_intr_handler, 0, irq_name, pf); 230 if (ret) { 231 dev_err(pf->dev, 232 "RVUPF: IRQ registration failed for ME1\n"); 233 } 234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 236 rvu_get_pf(pf->pcifunc)); 237 ret = request_irq(pci_irq_vector 238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 239 otx2_pf_flr_intr_handler, 0, irq_name, pf); 240 if (ret) { 241 dev_err(pf->dev, 242 "RVUPF: IRQ registration failed for FLR1\n"); 243 return ret; 244 } 245 } 246 247 /* Enable ME interrupt for all VFs*/ 248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 250 251 /* Enable FLR interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 if (numvfs > 64) { 256 numvfs -= 64; 257 258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 260 INTR_MASK(numvfs)); 261 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 } 266 return 0; 267 } 268 269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 270 { 271 int vf; 272 273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 274 WQ_UNBOUND | WQ_HIGHPRI, 1); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 /* Error code -EIO indicate there is a communication failure 398 * to the AF. Rest of the error codes indicate that AF processed 399 * VF messages and set the error codes in response messages 400 * (if any) so simply forward responses to VF. 401 */ 402 if (err == -EIO) { 403 dev_warn(pf->dev, 404 "AF not responding to VF%d messages\n", vf); 405 /* restore PF mbase and exit */ 406 dst_mdev->mbase = pf->mbox.bbuf_base; 407 mutex_unlock(&pf->mbox.lock); 408 return err; 409 } 410 /* At this point, all the VF messages sent to AF are acked 411 * with proper responses and responses are copied to VF 412 * mailbox hence raise interrupt to VF. 413 */ 414 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 415 dst_mbox->mbox.rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 419 pf->mbox.bbuf_base, vf); 420 mutex_unlock(&pf->mbox.lock); 421 } else if (dir == MBOX_DIR_PFVF_UP) { 422 src_mdev = &src_mbox->dev[0]; 423 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 424 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 425 src_mbox->rx_start); 426 req_hdr->num_msgs = num_msgs; 427 428 dst_mbox = &pf->mbox_pfvf[0]; 429 dst_size = dst_mbox->mbox_up.tx_size - 430 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 431 /* Check if msgs fit into destination area */ 432 if (mbox_hdr->msg_size > dst_size) 433 return -EINVAL; 434 435 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 436 dst_mdev->mbase = src_mdev->mbase; 437 dst_mdev->msg_size = mbox_hdr->msg_size; 438 dst_mdev->num_msgs = mbox_hdr->num_msgs; 439 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 440 if (err) { 441 dev_warn(pf->dev, 442 "VF%d is not responding to mailbox\n", vf); 443 return err; 444 } 445 } else if (dir == MBOX_DIR_VFPF_UP) { 446 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 447 src_mbox->rx_start); 448 req_hdr->num_msgs = num_msgs; 449 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 450 &pf->mbox.mbox_up, 451 pf->mbox_pfvf[vf].bbuf_base, 452 0); 453 } 454 455 return 0; 456 } 457 458 static void otx2_pfvf_mbox_handler(struct work_struct *work) 459 { 460 struct mbox_msghdr *msg = NULL; 461 int offset, vf_idx, id, err; 462 struct otx2_mbox_dev *mdev; 463 struct mbox_hdr *req_hdr; 464 struct otx2_mbox *mbox; 465 struct mbox *vf_mbox; 466 struct otx2_nic *pf; 467 468 vf_mbox = container_of(work, struct mbox, mbox_wrk); 469 pf = vf_mbox->pfvf; 470 vf_idx = vf_mbox - pf->mbox_pfvf; 471 472 mbox = &pf->mbox_pfvf[0].mbox; 473 mdev = &mbox->dev[vf_idx]; 474 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 475 476 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 477 478 for (id = 0; id < vf_mbox->num_msgs; id++) { 479 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 480 offset); 481 482 if (msg->sig != OTX2_MBOX_REQ_SIG) 483 goto inval_msg; 484 485 /* Set VF's number in each of the msg */ 486 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 487 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 488 offset = msg->next_msgoff; 489 } 490 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 491 vf_mbox->num_msgs); 492 if (err) 493 goto inval_msg; 494 return; 495 496 inval_msg: 497 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 498 otx2_mbox_msg_send(mbox, vf_idx); 499 } 500 501 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 502 { 503 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 504 struct otx2_nic *pf = vf_mbox->pfvf; 505 struct otx2_mbox_dev *mdev; 506 int offset, id, vf_idx = 0; 507 struct mbox_hdr *rsp_hdr; 508 struct mbox_msghdr *msg; 509 struct otx2_mbox *mbox; 510 511 vf_idx = vf_mbox - pf->mbox_pfvf; 512 mbox = &pf->mbox_pfvf[0].mbox_up; 513 mdev = &mbox->dev[vf_idx]; 514 515 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 516 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 517 518 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 519 msg = mdev->mbase + offset; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(pf->dev, 523 "Mbox msg with unknown ID 0x%x\n", msg->id); 524 goto end; 525 } 526 527 if (msg->sig != OTX2_MBOX_RSP_SIG) { 528 dev_err(pf->dev, 529 "Mbox msg with wrong signature %x, ID 0x%x\n", 530 msg->sig, msg->id); 531 goto end; 532 } 533 534 switch (msg->id) { 535 case MBOX_MSG_CGX_LINK_EVENT: 536 break; 537 default: 538 if (msg->rc) 539 dev_err(pf->dev, 540 "Mbox msg response has err %d, ID 0x%x\n", 541 msg->rc, msg->id); 542 break; 543 } 544 545 end: 546 offset = mbox->rx_start + msg->next_msgoff; 547 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 548 __otx2_mbox_reset(mbox, 0); 549 mdev->msgs_acked++; 550 } 551 } 552 553 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 554 { 555 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 556 int vfs = pf->total_vfs; 557 struct mbox *mbox; 558 u64 intr; 559 560 mbox = pf->mbox_pfvf; 561 /* Handle VF interrupts */ 562 if (vfs > 64) { 563 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 564 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 566 TYPE_PFVF); 567 vfs -= 64; 568 } 569 570 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 571 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 572 573 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 574 575 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 576 577 return IRQ_HANDLED; 578 } 579 580 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 581 { 582 void __iomem *hwbase; 583 struct mbox *mbox; 584 int err, vf; 585 u64 base; 586 587 if (!numvfs) 588 return -EINVAL; 589 590 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 591 sizeof(struct mbox), GFP_KERNEL); 592 if (!pf->mbox_pfvf) 593 return -ENOMEM; 594 595 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 596 WQ_UNBOUND | WQ_HIGHPRI | 597 WQ_MEM_RECLAIM, 1); 598 if (!pf->mbox_pfvf_wq) 599 return -ENOMEM; 600 601 /* On CN10K platform, PF <-> VF mailbox region follows after 602 * PF <-> AF mailbox region. 603 */ 604 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 605 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 606 MBOX_SIZE; 607 else 608 base = readq((void __iomem *)((u64)pf->reg_base + 609 RVU_PF_VF_BAR4_ADDR)); 610 611 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 612 if (!hwbase) { 613 err = -ENOMEM; 614 goto free_wq; 615 } 616 617 mbox = &pf->mbox_pfvf[0]; 618 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF, numvfs); 620 if (err) 621 goto free_iomem; 622 623 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 624 MBOX_DIR_PFVF_UP, numvfs); 625 if (err) 626 goto free_iomem; 627 628 for (vf = 0; vf < numvfs; vf++) { 629 mbox->pfvf = pf; 630 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 631 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 632 mbox++; 633 } 634 635 return 0; 636 637 free_iomem: 638 if (hwbase) 639 iounmap(hwbase); 640 free_wq: 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 return err; 643 } 644 645 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 646 { 647 struct mbox *mbox = &pf->mbox_pfvf[0]; 648 649 if (!mbox) 650 return; 651 652 if (pf->mbox_pfvf_wq) { 653 destroy_workqueue(pf->mbox_pfvf_wq); 654 pf->mbox_pfvf_wq = NULL; 655 } 656 657 if (mbox->mbox.hwbase) 658 iounmap(mbox->mbox.hwbase); 659 660 otx2_mbox_destroy(&mbox->mbox); 661 } 662 663 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 664 { 665 /* Clear PF <=> VF mailbox IRQ */ 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 669 /* Enable PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 671 if (numvfs > 64) { 672 numvfs -= 64; 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 674 INTR_MASK(numvfs)); 675 } 676 } 677 678 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 679 { 680 int vector; 681 682 /* Disable PF <=> VF mailbox IRQ */ 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 685 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 688 free_irq(vector, pf); 689 690 if (numvfs > 64) { 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 692 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 693 free_irq(vector, pf); 694 } 695 } 696 697 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 698 { 699 struct otx2_hw *hw = &pf->hw; 700 char *irq_name; 701 int err; 702 703 /* Register MBOX0 interrupt handler */ 704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 705 if (pf->pcifunc) 706 snprintf(irq_name, NAME_SIZE, 707 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 708 else 709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 710 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 711 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 712 if (err) { 713 dev_err(pf->dev, 714 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 715 return err; 716 } 717 718 if (numvfs > 64) { 719 /* Register MBOX1 interrupt handler */ 720 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 721 if (pf->pcifunc) 722 snprintf(irq_name, NAME_SIZE, 723 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 724 else 725 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 726 err = request_irq(pci_irq_vector(pf->pdev, 727 RVU_PF_INT_VEC_VFPF_MBOX1), 728 otx2_pfvf_mbox_intr_handler, 729 0, irq_name, pf); 730 if (err) { 731 dev_err(pf->dev, 732 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 733 return err; 734 } 735 } 736 737 otx2_enable_pfvf_mbox_intr(pf, numvfs); 738 739 return 0; 740 } 741 742 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 743 struct mbox_msghdr *msg) 744 { 745 int devid; 746 747 if (msg->id >= MBOX_MSG_MAX) { 748 dev_err(pf->dev, 749 "Mbox msg with unknown ID 0x%x\n", msg->id); 750 return; 751 } 752 753 if (msg->sig != OTX2_MBOX_RSP_SIG) { 754 dev_err(pf->dev, 755 "Mbox msg with wrong signature %x, ID 0x%x\n", 756 msg->sig, msg->id); 757 return; 758 } 759 760 /* message response heading VF */ 761 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 762 if (devid) { 763 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 764 struct delayed_work *dwork; 765 766 switch (msg->id) { 767 case MBOX_MSG_NIX_LF_START_RX: 768 config->intf_down = false; 769 dwork = &config->link_event_work; 770 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 771 break; 772 case MBOX_MSG_NIX_LF_STOP_RX: 773 config->intf_down = true; 774 break; 775 } 776 777 return; 778 } 779 780 switch (msg->id) { 781 case MBOX_MSG_READY: 782 pf->pcifunc = msg->pcifunc; 783 break; 784 case MBOX_MSG_MSIX_OFFSET: 785 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 786 break; 787 case MBOX_MSG_NPA_LF_ALLOC: 788 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 789 break; 790 case MBOX_MSG_NIX_LF_ALLOC: 791 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 792 break; 793 case MBOX_MSG_NIX_TXSCH_ALLOC: 794 mbox_handler_nix_txsch_alloc(pf, 795 (struct nix_txsch_alloc_rsp *)msg); 796 break; 797 case MBOX_MSG_NIX_BP_ENABLE: 798 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_STATS: 801 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 802 break; 803 case MBOX_MSG_CGX_FEC_STATS: 804 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 805 break; 806 default: 807 if (msg->rc) 808 dev_err(pf->dev, 809 "Mbox msg response has err %d, ID 0x%x\n", 810 msg->rc, msg->id); 811 break; 812 } 813 } 814 815 static void otx2_pfaf_mbox_handler(struct work_struct *work) 816 { 817 struct otx2_mbox_dev *mdev; 818 struct mbox_hdr *rsp_hdr; 819 struct mbox_msghdr *msg; 820 struct otx2_mbox *mbox; 821 struct mbox *af_mbox; 822 struct otx2_nic *pf; 823 int offset, id; 824 825 af_mbox = container_of(work, struct mbox, mbox_wrk); 826 mbox = &af_mbox->mbox; 827 mdev = &mbox->dev[0]; 828 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 829 830 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 831 pf = af_mbox->pfvf; 832 833 for (id = 0; id < af_mbox->num_msgs; id++) { 834 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 835 otx2_process_pfaf_mbox_msg(pf, msg); 836 offset = mbox->rx_start + msg->next_msgoff; 837 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 838 __otx2_mbox_reset(mbox, 0); 839 mdev->msgs_acked++; 840 } 841 842 } 843 844 static void otx2_handle_link_event(struct otx2_nic *pf) 845 { 846 struct cgx_link_user_info *linfo = &pf->linfo; 847 struct net_device *netdev = pf->netdev; 848 849 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 850 linfo->link_up ? "UP" : "DOWN", linfo->speed, 851 linfo->full_duplex ? "Full" : "Half"); 852 if (linfo->link_up) { 853 netif_carrier_on(netdev); 854 netif_tx_start_all_queues(netdev); 855 } else { 856 netif_tx_stop_all_queues(netdev); 857 netif_carrier_off(netdev); 858 } 859 } 860 861 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 862 struct mcs_intr_info *event, 863 struct msg_rsp *rsp) 864 { 865 cn10k_handle_mcs_event(pf, event); 866 867 return 0; 868 } 869 870 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 871 struct cgx_link_info_msg *msg, 872 struct msg_rsp *rsp) 873 { 874 int i; 875 876 /* Copy the link info sent by AF */ 877 pf->linfo = msg->link_info; 878 879 /* notify VFs about link event */ 880 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 881 struct otx2_vf_config *config = &pf->vf_configs[i]; 882 struct delayed_work *dwork = &config->link_event_work; 883 884 if (config->intf_down) 885 continue; 886 887 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 888 } 889 890 /* interface has not been fully configured yet */ 891 if (pf->flags & OTX2_FLAG_INTF_DOWN) 892 return 0; 893 894 otx2_handle_link_event(pf); 895 return 0; 896 } 897 898 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 899 struct mbox_msghdr *req) 900 { 901 /* Check if valid, if not reply with a invalid msg */ 902 if (req->sig != OTX2_MBOX_REQ_SIG) { 903 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 904 return -ENODEV; 905 } 906 907 switch (req->id) { 908 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 909 case _id: { \ 910 struct _rsp_type *rsp; \ 911 int err; \ 912 \ 913 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 914 &pf->mbox.mbox_up, 0, \ 915 sizeof(struct _rsp_type)); \ 916 if (!rsp) \ 917 return -ENOMEM; \ 918 \ 919 rsp->hdr.id = _id; \ 920 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 921 rsp->hdr.pcifunc = 0; \ 922 rsp->hdr.rc = 0; \ 923 \ 924 err = otx2_mbox_up_handler_ ## _fn_name( \ 925 pf, (struct _req_type *)req, rsp); \ 926 return err; \ 927 } 928 MBOX_UP_CGX_MESSAGES 929 MBOX_UP_MCS_MESSAGES 930 #undef M 931 break; 932 default: 933 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 934 return -ENODEV; 935 } 936 return 0; 937 } 938 939 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 940 { 941 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 942 struct otx2_mbox *mbox = &af_mbox->mbox_up; 943 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 944 struct otx2_nic *pf = af_mbox->pfvf; 945 int offset, id, devid = 0; 946 struct mbox_hdr *rsp_hdr; 947 struct mbox_msghdr *msg; 948 949 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 950 951 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 952 953 for (id = 0; id < af_mbox->up_num_msgs; id++) { 954 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 955 956 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 957 /* Skip processing VF's messages */ 958 if (!devid) 959 otx2_process_mbox_msg_up(pf, msg); 960 offset = mbox->rx_start + msg->next_msgoff; 961 } 962 if (devid) { 963 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 964 MBOX_DIR_PFVF_UP, devid - 1, 965 af_mbox->up_num_msgs); 966 return; 967 } 968 969 otx2_mbox_msg_send(mbox, 0); 970 } 971 972 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 973 { 974 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 975 struct mbox *mbox; 976 977 /* Clear the IRQ */ 978 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 979 980 mbox = &pf->mbox; 981 982 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 983 984 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 985 986 return IRQ_HANDLED; 987 } 988 989 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 990 { 991 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 992 993 /* Disable AF => PF mailbox IRQ */ 994 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 995 free_irq(vector, pf); 996 } 997 998 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 999 { 1000 struct otx2_hw *hw = &pf->hw; 1001 struct msg_req *req; 1002 char *irq_name; 1003 int err; 1004 1005 /* Register mailbox interrupt handler */ 1006 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1007 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 1008 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1009 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1010 if (err) { 1011 dev_err(pf->dev, 1012 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1013 return err; 1014 } 1015 1016 /* Enable mailbox interrupt for msgs coming from AF. 1017 * First clear to avoid spurious interrupts, if any. 1018 */ 1019 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1020 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1021 1022 if (!probe_af) 1023 return 0; 1024 1025 /* Check mailbox communication with AF */ 1026 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1027 if (!req) { 1028 otx2_disable_mbox_intr(pf); 1029 return -ENOMEM; 1030 } 1031 err = otx2_sync_mbox_msg(&pf->mbox); 1032 if (err) { 1033 dev_warn(pf->dev, 1034 "AF not responding to mailbox, deferring probe\n"); 1035 otx2_disable_mbox_intr(pf); 1036 return -EPROBE_DEFER; 1037 } 1038 1039 return 0; 1040 } 1041 1042 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1043 { 1044 struct mbox *mbox = &pf->mbox; 1045 1046 if (pf->mbox_wq) { 1047 destroy_workqueue(pf->mbox_wq); 1048 pf->mbox_wq = NULL; 1049 } 1050 1051 if (mbox->mbox.hwbase) 1052 iounmap((void __iomem *)mbox->mbox.hwbase); 1053 1054 otx2_mbox_destroy(&mbox->mbox); 1055 otx2_mbox_destroy(&mbox->mbox_up); 1056 } 1057 1058 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1059 { 1060 struct mbox *mbox = &pf->mbox; 1061 void __iomem *hwbase; 1062 int err; 1063 1064 mbox->pfvf = pf; 1065 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1066 WQ_UNBOUND | WQ_HIGHPRI | 1067 WQ_MEM_RECLAIM, 1); 1068 if (!pf->mbox_wq) 1069 return -ENOMEM; 1070 1071 /* Mailbox is a reserved memory (in RAM) region shared between 1072 * admin function (i.e AF) and this PF, shouldn't be mapped as 1073 * device memory to allow unaligned accesses. 1074 */ 1075 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1076 MBOX_SIZE); 1077 if (!hwbase) { 1078 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1079 err = -ENOMEM; 1080 goto exit; 1081 } 1082 1083 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1084 MBOX_DIR_PFAF, 1); 1085 if (err) 1086 goto exit; 1087 1088 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1089 MBOX_DIR_PFAF_UP, 1); 1090 if (err) 1091 goto exit; 1092 1093 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1094 if (err) 1095 goto exit; 1096 1097 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1098 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1099 mutex_init(&mbox->lock); 1100 1101 return 0; 1102 exit: 1103 otx2_pfaf_mbox_destroy(pf); 1104 return err; 1105 } 1106 1107 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1108 { 1109 struct msg_req *msg; 1110 int err; 1111 1112 mutex_lock(&pf->mbox.lock); 1113 if (enable) 1114 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1115 else 1116 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1117 1118 if (!msg) { 1119 mutex_unlock(&pf->mbox.lock); 1120 return -ENOMEM; 1121 } 1122 1123 err = otx2_sync_mbox_msg(&pf->mbox); 1124 mutex_unlock(&pf->mbox.lock); 1125 return err; 1126 } 1127 1128 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1129 { 1130 struct msg_req *msg; 1131 int err; 1132 1133 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1134 pf->flow_cfg->dmacflt_max_flows)) 1135 netdev_warn(pf->netdev, 1136 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1137 1138 mutex_lock(&pf->mbox.lock); 1139 if (enable) 1140 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1141 else 1142 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1143 1144 if (!msg) { 1145 mutex_unlock(&pf->mbox.lock); 1146 return -ENOMEM; 1147 } 1148 1149 err = otx2_sync_mbox_msg(&pf->mbox); 1150 mutex_unlock(&pf->mbox.lock); 1151 return err; 1152 } 1153 1154 int otx2_set_real_num_queues(struct net_device *netdev, 1155 int tx_queues, int rx_queues) 1156 { 1157 int err; 1158 1159 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1160 if (err) { 1161 netdev_err(netdev, 1162 "Failed to set no of Tx queues: %d\n", tx_queues); 1163 return err; 1164 } 1165 1166 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1167 if (err) 1168 netdev_err(netdev, 1169 "Failed to set no of Rx queues: %d\n", rx_queues); 1170 return err; 1171 } 1172 EXPORT_SYMBOL(otx2_set_real_num_queues); 1173 1174 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1175 { 1176 struct otx2_nic *pf = data; 1177 u64 val, *ptr; 1178 u64 qidx = 0; 1179 1180 /* CQ */ 1181 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1182 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1183 val = otx2_atomic64_add((qidx << 44), ptr); 1184 1185 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1186 (val & NIX_CQERRINT_BITS)); 1187 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1188 continue; 1189 1190 if (val & BIT_ULL(42)) { 1191 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1192 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1193 } else { 1194 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1195 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1196 qidx); 1197 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1198 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1199 qidx); 1200 } 1201 1202 schedule_work(&pf->reset_task); 1203 } 1204 1205 /* SQ */ 1206 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1207 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1208 val = otx2_atomic64_add((qidx << 44), ptr); 1209 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1210 (val & NIX_SQINT_BITS)); 1211 1212 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1213 continue; 1214 1215 if (val & BIT_ULL(42)) { 1216 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1217 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1218 } else { 1219 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1220 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1221 qidx, 1222 otx2_read64(pf, 1223 NIX_LF_SQ_OP_ERR_DBG)); 1224 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1225 BIT_ULL(44)); 1226 } 1227 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1228 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1229 qidx, 1230 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1231 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1232 BIT_ULL(44)); 1233 } 1234 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1235 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1236 qidx, 1237 otx2_read64(pf, 1238 NIX_LF_SEND_ERR_DBG)); 1239 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1240 BIT_ULL(44)); 1241 } 1242 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1243 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1244 qidx); 1245 } 1246 1247 schedule_work(&pf->reset_task); 1248 } 1249 1250 return IRQ_HANDLED; 1251 } 1252 1253 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1254 { 1255 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1256 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1257 int qidx = cq_poll->cint_idx; 1258 1259 /* Disable interrupts. 1260 * 1261 * Completion interrupts behave in a level-triggered interrupt 1262 * fashion, and hence have to be cleared only after it is serviced. 1263 */ 1264 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1265 1266 /* Schedule NAPI */ 1267 pf->napi_events++; 1268 napi_schedule_irqoff(&cq_poll->napi); 1269 1270 return IRQ_HANDLED; 1271 } 1272 1273 static void otx2_disable_napi(struct otx2_nic *pf) 1274 { 1275 struct otx2_qset *qset = &pf->qset; 1276 struct otx2_cq_poll *cq_poll; 1277 int qidx; 1278 1279 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1280 cq_poll = &qset->napi[qidx]; 1281 cancel_work_sync(&cq_poll->dim.work); 1282 napi_disable(&cq_poll->napi); 1283 netif_napi_del(&cq_poll->napi); 1284 } 1285 } 1286 1287 static void otx2_free_cq_res(struct otx2_nic *pf) 1288 { 1289 struct otx2_qset *qset = &pf->qset; 1290 struct otx2_cq_queue *cq; 1291 int qidx; 1292 1293 /* Disable CQs */ 1294 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1295 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1296 cq = &qset->cq[qidx]; 1297 qmem_free(pf->dev, cq->cqe); 1298 } 1299 } 1300 1301 static void otx2_free_sq_res(struct otx2_nic *pf) 1302 { 1303 struct otx2_qset *qset = &pf->qset; 1304 struct otx2_snd_queue *sq; 1305 int qidx; 1306 1307 /* Disable SQs */ 1308 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1309 /* Free SQB pointers */ 1310 otx2_sq_free_sqbs(pf); 1311 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1312 sq = &qset->sq[qidx]; 1313 qmem_free(pf->dev, sq->sqe); 1314 qmem_free(pf->dev, sq->tso_hdrs); 1315 kfree(sq->sg); 1316 kfree(sq->sqb_ptrs); 1317 } 1318 } 1319 1320 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1321 { 1322 int frame_size; 1323 int total_size; 1324 int rbuf_size; 1325 1326 if (pf->hw.rbuf_len) 1327 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1328 1329 /* The data transferred by NIX to memory consists of actual packet 1330 * plus additional data which has timestamp and/or EDSA/HIGIG2 1331 * headers if interface is configured in corresponding modes. 1332 * NIX transfers entire data using 6 segments/buffers and writes 1333 * a CQE_RX descriptor with those segment addresses. First segment 1334 * has additional data prepended to packet. Also software omits a 1335 * headroom of 128 bytes in each segment. Hence the total size of 1336 * memory needed to receive a packet with 'mtu' is: 1337 * frame size = mtu + additional data; 1338 * memory = frame_size + headroom * 6; 1339 * each receive buffer size = memory / 6; 1340 */ 1341 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1342 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1343 rbuf_size = total_size / 6; 1344 1345 return ALIGN(rbuf_size, 2048); 1346 } 1347 1348 static int otx2_init_hw_resources(struct otx2_nic *pf) 1349 { 1350 struct nix_lf_free_req *free_req; 1351 struct mbox *mbox = &pf->mbox; 1352 struct otx2_hw *hw = &pf->hw; 1353 struct msg_req *req; 1354 int err = 0, lvl; 1355 1356 /* Set required NPA LF's pool counts 1357 * Auras and Pools are used in a 1:1 mapping, 1358 * so, aura count = pool count. 1359 */ 1360 hw->rqpool_cnt = hw->rx_queues; 1361 hw->sqpool_cnt = hw->tot_tx_queues; 1362 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1363 1364 /* Maximum hardware supported transmit length */ 1365 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1366 1367 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1368 1369 mutex_lock(&mbox->lock); 1370 /* NPA init */ 1371 err = otx2_config_npa(pf); 1372 if (err) 1373 goto exit; 1374 1375 /* NIX init */ 1376 err = otx2_config_nix(pf); 1377 if (err) 1378 goto err_free_npa_lf; 1379 1380 /* Enable backpressure */ 1381 otx2_nix_config_bp(pf, true); 1382 1383 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1384 err = otx2_rq_aura_pool_init(pf); 1385 if (err) { 1386 mutex_unlock(&mbox->lock); 1387 goto err_free_nix_lf; 1388 } 1389 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1390 err = otx2_sq_aura_pool_init(pf); 1391 if (err) { 1392 mutex_unlock(&mbox->lock); 1393 goto err_free_rq_ptrs; 1394 } 1395 1396 err = otx2_txsch_alloc(pf); 1397 if (err) { 1398 mutex_unlock(&mbox->lock); 1399 goto err_free_sq_ptrs; 1400 } 1401 1402 #ifdef CONFIG_DCB 1403 if (pf->pfc_en) { 1404 err = otx2_pfc_txschq_alloc(pf); 1405 if (err) { 1406 mutex_unlock(&mbox->lock); 1407 goto err_free_sq_ptrs; 1408 } 1409 } 1410 #endif 1411 1412 err = otx2_config_nix_queues(pf); 1413 if (err) { 1414 mutex_unlock(&mbox->lock); 1415 goto err_free_txsch; 1416 } 1417 1418 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1419 err = otx2_txschq_config(pf, lvl, 0, false); 1420 if (err) { 1421 mutex_unlock(&mbox->lock); 1422 goto err_free_nix_queues; 1423 } 1424 } 1425 1426 #ifdef CONFIG_DCB 1427 if (pf->pfc_en) { 1428 err = otx2_pfc_txschq_config(pf); 1429 if (err) { 1430 mutex_unlock(&mbox->lock); 1431 goto err_free_nix_queues; 1432 } 1433 } 1434 #endif 1435 1436 mutex_unlock(&mbox->lock); 1437 return err; 1438 1439 err_free_nix_queues: 1440 otx2_free_sq_res(pf); 1441 otx2_free_cq_res(pf); 1442 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1443 err_free_txsch: 1444 if (otx2_txschq_stop(pf)) 1445 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1446 err_free_sq_ptrs: 1447 otx2_sq_free_sqbs(pf); 1448 err_free_rq_ptrs: 1449 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1450 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1451 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1452 otx2_aura_pool_free(pf); 1453 err_free_nix_lf: 1454 mutex_lock(&mbox->lock); 1455 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1456 if (free_req) { 1457 free_req->flags = NIX_LF_DISABLE_FLOWS; 1458 if (otx2_sync_mbox_msg(mbox)) 1459 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1460 } 1461 err_free_npa_lf: 1462 /* Reset NPA LF */ 1463 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1464 if (req) { 1465 if (otx2_sync_mbox_msg(mbox)) 1466 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1467 } 1468 exit: 1469 mutex_unlock(&mbox->lock); 1470 return err; 1471 } 1472 1473 static void otx2_free_hw_resources(struct otx2_nic *pf) 1474 { 1475 struct otx2_qset *qset = &pf->qset; 1476 struct nix_lf_free_req *free_req; 1477 struct mbox *mbox = &pf->mbox; 1478 struct otx2_cq_queue *cq; 1479 struct msg_req *req; 1480 int qidx, err; 1481 1482 /* Ensure all SQE are processed */ 1483 otx2_sqb_flush(pf); 1484 1485 /* Stop transmission */ 1486 err = otx2_txschq_stop(pf); 1487 if (err) 1488 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1489 1490 #ifdef CONFIG_DCB 1491 if (pf->pfc_en) 1492 otx2_pfc_txschq_stop(pf); 1493 #endif 1494 1495 mutex_lock(&mbox->lock); 1496 /* Disable backpressure */ 1497 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1498 otx2_nix_config_bp(pf, false); 1499 mutex_unlock(&mbox->lock); 1500 1501 /* Disable RQs */ 1502 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1503 1504 /*Dequeue all CQEs */ 1505 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1506 cq = &qset->cq[qidx]; 1507 if (cq->cq_type == CQ_RX) 1508 otx2_cleanup_rx_cqes(pf, cq); 1509 else 1510 otx2_cleanup_tx_cqes(pf, cq); 1511 } 1512 1513 otx2_free_sq_res(pf); 1514 1515 /* Free RQ buffer pointers*/ 1516 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1517 1518 otx2_free_cq_res(pf); 1519 1520 /* Free all ingress bandwidth profiles allocated */ 1521 cn10k_free_all_ipolicers(pf); 1522 1523 mutex_lock(&mbox->lock); 1524 /* Reset NIX LF */ 1525 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1526 if (free_req) { 1527 free_req->flags = NIX_LF_DISABLE_FLOWS; 1528 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1529 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1530 if (otx2_sync_mbox_msg(mbox)) 1531 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1532 } 1533 mutex_unlock(&mbox->lock); 1534 1535 /* Disable NPA Pool and Aura hw context */ 1536 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1537 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1538 otx2_aura_pool_free(pf); 1539 1540 mutex_lock(&mbox->lock); 1541 /* Reset NPA LF */ 1542 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1543 if (req) { 1544 if (otx2_sync_mbox_msg(mbox)) 1545 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1546 } 1547 mutex_unlock(&mbox->lock); 1548 } 1549 1550 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1551 { 1552 struct net_device *netdev = pf->netdev; 1553 struct nix_rx_mode *req; 1554 bool promisc = false; 1555 1556 if (!(netdev->flags & IFF_UP)) 1557 return; 1558 1559 if ((netdev->flags & IFF_PROMISC) || 1560 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1561 promisc = true; 1562 } 1563 1564 /* Write unicast address to mcam entries or del from mcam */ 1565 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1566 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1567 1568 mutex_lock(&pf->mbox.lock); 1569 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1570 if (!req) { 1571 mutex_unlock(&pf->mbox.lock); 1572 return; 1573 } 1574 1575 req->mode = NIX_RX_MODE_UCAST; 1576 1577 if (promisc) 1578 req->mode |= NIX_RX_MODE_PROMISC; 1579 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1580 req->mode |= NIX_RX_MODE_ALLMULTI; 1581 1582 req->mode |= NIX_RX_MODE_USE_MCE; 1583 1584 otx2_sync_mbox_msg(&pf->mbox); 1585 mutex_unlock(&pf->mbox.lock); 1586 } 1587 1588 static void otx2_dim_work(struct work_struct *w) 1589 { 1590 struct dim_cq_moder cur_moder; 1591 struct otx2_cq_poll *cq_poll; 1592 struct otx2_nic *pfvf; 1593 struct dim *dim; 1594 1595 dim = container_of(w, struct dim, work); 1596 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1597 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1598 pfvf = (struct otx2_nic *)cq_poll->dev; 1599 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1600 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1601 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1602 NAPI_POLL_WEIGHT : cur_moder.pkts; 1603 dim->state = DIM_START_MEASURE; 1604 } 1605 1606 int otx2_open(struct net_device *netdev) 1607 { 1608 struct otx2_nic *pf = netdev_priv(netdev); 1609 struct otx2_cq_poll *cq_poll = NULL; 1610 struct otx2_qset *qset = &pf->qset; 1611 int err = 0, qidx, vec; 1612 char *irq_name; 1613 1614 netif_carrier_off(netdev); 1615 1616 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1617 /* RQ and SQs are mapped to different CQs, 1618 * so find out max CQ IRQs (i.e CINTs) needed. 1619 */ 1620 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1621 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1622 if (!qset->napi) 1623 return -ENOMEM; 1624 1625 /* CQ size of RQ */ 1626 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1627 /* CQ size of SQ */ 1628 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1629 1630 err = -ENOMEM; 1631 qset->cq = kcalloc(pf->qset.cq_cnt, 1632 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1633 if (!qset->cq) 1634 goto err_free_mem; 1635 1636 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1637 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1638 if (!qset->sq) 1639 goto err_free_mem; 1640 1641 qset->rq = kcalloc(pf->hw.rx_queues, 1642 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1643 if (!qset->rq) 1644 goto err_free_mem; 1645 1646 err = otx2_init_hw_resources(pf); 1647 if (err) 1648 goto err_free_mem; 1649 1650 /* Register NAPI handler */ 1651 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1652 cq_poll = &qset->napi[qidx]; 1653 cq_poll->cint_idx = qidx; 1654 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1655 * 'cq_ids[0]' points to RQ's CQ and 1656 * 'cq_ids[1]' points to SQ's CQ and 1657 * 'cq_ids[2]' points to XDP's CQ and 1658 */ 1659 cq_poll->cq_ids[CQ_RX] = 1660 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1661 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1662 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1663 if (pf->xdp_prog) 1664 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1665 (qidx + pf->hw.rx_queues + 1666 pf->hw.tx_queues) : 1667 CINT_INVALID_CQ; 1668 else 1669 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1670 1671 cq_poll->dev = (void *)pf; 1672 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 1673 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 1674 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 1675 napi_enable(&cq_poll->napi); 1676 } 1677 1678 /* Set maximum frame size allowed in HW */ 1679 err = otx2_hw_set_mtu(pf, netdev->mtu); 1680 if (err) 1681 goto err_disable_napi; 1682 1683 /* Setup segmentation algorithms, if failed, clear offload capability */ 1684 otx2_setup_segmentation(pf); 1685 1686 /* Initialize RSS */ 1687 err = otx2_rss_init(pf); 1688 if (err) 1689 goto err_disable_napi; 1690 1691 /* Register Queue IRQ handlers */ 1692 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1693 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1694 1695 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1696 1697 err = request_irq(pci_irq_vector(pf->pdev, vec), 1698 otx2_q_intr_handler, 0, irq_name, pf); 1699 if (err) { 1700 dev_err(pf->dev, 1701 "RVUPF%d: IRQ registration failed for QERR\n", 1702 rvu_get_pf(pf->pcifunc)); 1703 goto err_disable_napi; 1704 } 1705 1706 /* Enable QINT IRQ */ 1707 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1708 1709 /* Register CQ IRQ handlers */ 1710 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1711 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1712 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1713 1714 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1715 qidx); 1716 1717 err = request_irq(pci_irq_vector(pf->pdev, vec), 1718 otx2_cq_intr_handler, 0, irq_name, 1719 &qset->napi[qidx]); 1720 if (err) { 1721 dev_err(pf->dev, 1722 "RVUPF%d: IRQ registration failed for CQ%d\n", 1723 rvu_get_pf(pf->pcifunc), qidx); 1724 goto err_free_cints; 1725 } 1726 vec++; 1727 1728 otx2_config_irq_coalescing(pf, qidx); 1729 1730 /* Enable CQ IRQ */ 1731 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1732 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1733 } 1734 1735 otx2_set_cints_affinity(pf); 1736 1737 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1738 otx2_enable_rxvlan(pf, true); 1739 1740 /* When reinitializing enable time stamping if it is enabled before */ 1741 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1742 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1743 otx2_config_hw_tx_tstamp(pf, true); 1744 } 1745 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1746 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1747 otx2_config_hw_rx_tstamp(pf, true); 1748 } 1749 1750 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1751 /* 'intf_down' may be checked on any cpu */ 1752 smp_wmb(); 1753 1754 /* we have already received link status notification */ 1755 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1756 otx2_handle_link_event(pf); 1757 1758 /* Install DMAC Filters */ 1759 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1760 otx2_dmacflt_reinstall_flows(pf); 1761 1762 err = otx2_rxtx_enable(pf, true); 1763 if (err) 1764 goto err_tx_stop_queues; 1765 1766 otx2_do_set_rx_mode(pf); 1767 1768 return 0; 1769 1770 err_tx_stop_queues: 1771 netif_tx_stop_all_queues(netdev); 1772 netif_carrier_off(netdev); 1773 pf->flags |= OTX2_FLAG_INTF_DOWN; 1774 err_free_cints: 1775 otx2_free_cints(pf, qidx); 1776 vec = pci_irq_vector(pf->pdev, 1777 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1778 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1779 free_irq(vec, pf); 1780 err_disable_napi: 1781 otx2_disable_napi(pf); 1782 otx2_free_hw_resources(pf); 1783 err_free_mem: 1784 kfree(qset->sq); 1785 kfree(qset->cq); 1786 kfree(qset->rq); 1787 kfree(qset->napi); 1788 return err; 1789 } 1790 EXPORT_SYMBOL(otx2_open); 1791 1792 int otx2_stop(struct net_device *netdev) 1793 { 1794 struct otx2_nic *pf = netdev_priv(netdev); 1795 struct otx2_cq_poll *cq_poll = NULL; 1796 struct otx2_qset *qset = &pf->qset; 1797 struct otx2_rss_info *rss; 1798 int qidx, vec, wrk; 1799 1800 /* If the DOWN flag is set resources are already freed */ 1801 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1802 return 0; 1803 1804 netif_carrier_off(netdev); 1805 netif_tx_stop_all_queues(netdev); 1806 1807 pf->flags |= OTX2_FLAG_INTF_DOWN; 1808 /* 'intf_down' may be checked on any cpu */ 1809 smp_wmb(); 1810 1811 /* First stop packet Rx/Tx */ 1812 otx2_rxtx_enable(pf, false); 1813 1814 /* Clear RSS enable flag */ 1815 rss = &pf->hw.rss_info; 1816 rss->enable = false; 1817 1818 /* Cleanup Queue IRQ */ 1819 vec = pci_irq_vector(pf->pdev, 1820 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1821 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1822 free_irq(vec, pf); 1823 1824 /* Cleanup CQ NAPI and IRQ */ 1825 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1826 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1827 /* Disable interrupt */ 1828 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1829 1830 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1831 1832 cq_poll = &qset->napi[qidx]; 1833 napi_synchronize(&cq_poll->napi); 1834 vec++; 1835 } 1836 1837 netif_tx_disable(netdev); 1838 1839 otx2_free_hw_resources(pf); 1840 otx2_free_cints(pf, pf->hw.cint_cnt); 1841 otx2_disable_napi(pf); 1842 1843 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1844 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1845 1846 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1847 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1848 devm_kfree(pf->dev, pf->refill_wrk); 1849 1850 kfree(qset->sq); 1851 kfree(qset->cq); 1852 kfree(qset->rq); 1853 kfree(qset->napi); 1854 /* Do not clear RQ/SQ ringsize settings */ 1855 memset_startat(qset, 0, sqe_cnt); 1856 return 0; 1857 } 1858 EXPORT_SYMBOL(otx2_stop); 1859 1860 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1861 { 1862 struct otx2_nic *pf = netdev_priv(netdev); 1863 int qidx = skb_get_queue_mapping(skb); 1864 struct otx2_snd_queue *sq; 1865 struct netdev_queue *txq; 1866 1867 /* Check for minimum and maximum packet length */ 1868 if (skb->len <= ETH_HLEN || 1869 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1870 dev_kfree_skb(skb); 1871 return NETDEV_TX_OK; 1872 } 1873 1874 sq = &pf->qset.sq[qidx]; 1875 txq = netdev_get_tx_queue(netdev, qidx); 1876 1877 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1878 netif_tx_stop_queue(txq); 1879 1880 /* Check again, incase SQBs got freed up */ 1881 smp_mb(); 1882 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1883 > sq->sqe_thresh) 1884 netif_tx_wake_queue(txq); 1885 1886 return NETDEV_TX_BUSY; 1887 } 1888 1889 return NETDEV_TX_OK; 1890 } 1891 1892 static u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 1893 struct net_device *sb_dev) 1894 { 1895 #ifdef CONFIG_DCB 1896 struct otx2_nic *pf = netdev_priv(netdev); 1897 u8 vlan_prio; 1898 #endif 1899 1900 #ifdef CONFIG_DCB 1901 if (!skb->vlan_present) 1902 goto pick_tx; 1903 1904 vlan_prio = skb->vlan_tci >> 13; 1905 if ((vlan_prio > pf->hw.tx_queues - 1) || 1906 !pf->pfc_alloc_status[vlan_prio]) 1907 goto pick_tx; 1908 1909 return vlan_prio; 1910 1911 pick_tx: 1912 #endif 1913 return netdev_pick_tx(netdev, skb, NULL); 1914 } 1915 1916 static netdev_features_t otx2_fix_features(struct net_device *dev, 1917 netdev_features_t features) 1918 { 1919 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1920 features |= NETIF_F_HW_VLAN_STAG_RX; 1921 else 1922 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1923 1924 return features; 1925 } 1926 1927 static void otx2_set_rx_mode(struct net_device *netdev) 1928 { 1929 struct otx2_nic *pf = netdev_priv(netdev); 1930 1931 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1932 } 1933 1934 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 1935 { 1936 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1937 1938 otx2_do_set_rx_mode(pf); 1939 } 1940 1941 static int otx2_set_features(struct net_device *netdev, 1942 netdev_features_t features) 1943 { 1944 netdev_features_t changed = features ^ netdev->features; 1945 struct otx2_nic *pf = netdev_priv(netdev); 1946 1947 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1948 return otx2_cgx_config_loopback(pf, 1949 features & NETIF_F_LOOPBACK); 1950 1951 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1952 return otx2_enable_rxvlan(pf, 1953 features & NETIF_F_HW_VLAN_CTAG_RX); 1954 1955 return otx2_handle_ntuple_tc_features(netdev, features); 1956 } 1957 1958 static void otx2_reset_task(struct work_struct *work) 1959 { 1960 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1961 1962 if (!netif_running(pf->netdev)) 1963 return; 1964 1965 rtnl_lock(); 1966 otx2_stop(pf->netdev); 1967 pf->reset_count++; 1968 otx2_open(pf->netdev); 1969 netif_trans_update(pf->netdev); 1970 rtnl_unlock(); 1971 } 1972 1973 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1974 { 1975 struct msg_req *req; 1976 int err; 1977 1978 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1979 return 0; 1980 1981 mutex_lock(&pfvf->mbox.lock); 1982 if (enable) 1983 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1984 else 1985 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1986 if (!req) { 1987 mutex_unlock(&pfvf->mbox.lock); 1988 return -ENOMEM; 1989 } 1990 1991 err = otx2_sync_mbox_msg(&pfvf->mbox); 1992 if (err) { 1993 mutex_unlock(&pfvf->mbox.lock); 1994 return err; 1995 } 1996 1997 mutex_unlock(&pfvf->mbox.lock); 1998 if (enable) 1999 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2000 else 2001 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2002 return 0; 2003 } 2004 2005 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2006 { 2007 struct msg_req *req; 2008 int err; 2009 2010 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2011 return 0; 2012 2013 mutex_lock(&pfvf->mbox.lock); 2014 if (enable) 2015 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2016 else 2017 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2018 if (!req) { 2019 mutex_unlock(&pfvf->mbox.lock); 2020 return -ENOMEM; 2021 } 2022 2023 err = otx2_sync_mbox_msg(&pfvf->mbox); 2024 if (err) { 2025 mutex_unlock(&pfvf->mbox.lock); 2026 return err; 2027 } 2028 2029 mutex_unlock(&pfvf->mbox.lock); 2030 if (enable) 2031 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2032 else 2033 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2034 return 0; 2035 } 2036 2037 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 2038 { 2039 struct otx2_nic *pfvf = netdev_priv(netdev); 2040 struct hwtstamp_config config; 2041 2042 if (!pfvf->ptp) 2043 return -ENODEV; 2044 2045 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2046 return -EFAULT; 2047 2048 switch (config.tx_type) { 2049 case HWTSTAMP_TX_OFF: 2050 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2051 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2052 2053 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2054 otx2_config_hw_tx_tstamp(pfvf, false); 2055 break; 2056 case HWTSTAMP_TX_ONESTEP_SYNC: 2057 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) 2058 return -ERANGE; 2059 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2060 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2061 msecs_to_jiffies(500)); 2062 fallthrough; 2063 case HWTSTAMP_TX_ON: 2064 otx2_config_hw_tx_tstamp(pfvf, true); 2065 break; 2066 default: 2067 return -ERANGE; 2068 } 2069 2070 switch (config.rx_filter) { 2071 case HWTSTAMP_FILTER_NONE: 2072 otx2_config_hw_rx_tstamp(pfvf, false); 2073 break; 2074 case HWTSTAMP_FILTER_ALL: 2075 case HWTSTAMP_FILTER_SOME: 2076 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2077 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2078 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2079 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2080 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2081 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2082 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2083 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2084 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2085 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2086 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2087 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2088 otx2_config_hw_rx_tstamp(pfvf, true); 2089 config.rx_filter = HWTSTAMP_FILTER_ALL; 2090 break; 2091 default: 2092 return -ERANGE; 2093 } 2094 2095 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2096 2097 return copy_to_user(ifr->ifr_data, &config, 2098 sizeof(config)) ? -EFAULT : 0; 2099 } 2100 EXPORT_SYMBOL(otx2_config_hwtstamp); 2101 2102 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2103 { 2104 struct otx2_nic *pfvf = netdev_priv(netdev); 2105 struct hwtstamp_config *cfg = &pfvf->tstamp; 2106 2107 switch (cmd) { 2108 case SIOCSHWTSTAMP: 2109 return otx2_config_hwtstamp(netdev, req); 2110 case SIOCGHWTSTAMP: 2111 return copy_to_user(req->ifr_data, cfg, 2112 sizeof(*cfg)) ? -EFAULT : 0; 2113 default: 2114 return -EOPNOTSUPP; 2115 } 2116 } 2117 EXPORT_SYMBOL(otx2_ioctl); 2118 2119 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2120 { 2121 struct npc_install_flow_req *req; 2122 int err; 2123 2124 mutex_lock(&pf->mbox.lock); 2125 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2126 if (!req) { 2127 err = -ENOMEM; 2128 goto out; 2129 } 2130 2131 ether_addr_copy(req->packet.dmac, mac); 2132 eth_broadcast_addr((u8 *)&req->mask.dmac); 2133 req->features = BIT_ULL(NPC_DMAC); 2134 req->channel = pf->hw.rx_chan_base; 2135 req->intf = NIX_INTF_RX; 2136 req->default_rule = 1; 2137 req->append = 1; 2138 req->vf = vf + 1; 2139 req->op = NIX_RX_ACTION_DEFAULT; 2140 2141 err = otx2_sync_mbox_msg(&pf->mbox); 2142 out: 2143 mutex_unlock(&pf->mbox.lock); 2144 return err; 2145 } 2146 2147 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2148 { 2149 struct otx2_nic *pf = netdev_priv(netdev); 2150 struct pci_dev *pdev = pf->pdev; 2151 struct otx2_vf_config *config; 2152 int ret; 2153 2154 if (!netif_running(netdev)) 2155 return -EAGAIN; 2156 2157 if (vf >= pf->total_vfs) 2158 return -EINVAL; 2159 2160 if (!is_valid_ether_addr(mac)) 2161 return -EINVAL; 2162 2163 config = &pf->vf_configs[vf]; 2164 ether_addr_copy(config->mac, mac); 2165 2166 ret = otx2_do_set_vf_mac(pf, vf, mac); 2167 if (ret == 0) 2168 dev_info(&pdev->dev, 2169 "Load/Reload VF driver\n"); 2170 2171 return ret; 2172 } 2173 2174 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2175 __be16 proto) 2176 { 2177 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2178 struct nix_vtag_config_rsp *vtag_rsp; 2179 struct npc_delete_flow_req *del_req; 2180 struct nix_vtag_config *vtag_req; 2181 struct npc_install_flow_req *req; 2182 struct otx2_vf_config *config; 2183 int err = 0; 2184 u32 idx; 2185 2186 config = &pf->vf_configs[vf]; 2187 2188 if (!vlan && !config->vlan) 2189 goto out; 2190 2191 mutex_lock(&pf->mbox.lock); 2192 2193 /* free old tx vtag entry */ 2194 if (config->vlan) { 2195 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2196 if (!vtag_req) { 2197 err = -ENOMEM; 2198 goto out; 2199 } 2200 vtag_req->cfg_type = 0; 2201 vtag_req->tx.free_vtag0 = 1; 2202 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2203 2204 err = otx2_sync_mbox_msg(&pf->mbox); 2205 if (err) 2206 goto out; 2207 } 2208 2209 if (!vlan && config->vlan) { 2210 /* rx */ 2211 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2212 if (!del_req) { 2213 err = -ENOMEM; 2214 goto out; 2215 } 2216 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2217 del_req->entry = 2218 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2219 err = otx2_sync_mbox_msg(&pf->mbox); 2220 if (err) 2221 goto out; 2222 2223 /* tx */ 2224 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2225 if (!del_req) { 2226 err = -ENOMEM; 2227 goto out; 2228 } 2229 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2230 del_req->entry = 2231 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2232 err = otx2_sync_mbox_msg(&pf->mbox); 2233 2234 goto out; 2235 } 2236 2237 /* rx */ 2238 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2239 if (!req) { 2240 err = -ENOMEM; 2241 goto out; 2242 } 2243 2244 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2245 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2246 req->packet.vlan_tci = htons(vlan); 2247 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2248 /* af fills the destination mac addr */ 2249 eth_broadcast_addr((u8 *)&req->mask.dmac); 2250 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2251 req->channel = pf->hw.rx_chan_base; 2252 req->intf = NIX_INTF_RX; 2253 req->vf = vf + 1; 2254 req->op = NIX_RX_ACTION_DEFAULT; 2255 req->vtag0_valid = true; 2256 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2257 req->set_cntr = 1; 2258 2259 err = otx2_sync_mbox_msg(&pf->mbox); 2260 if (err) 2261 goto out; 2262 2263 /* tx */ 2264 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2265 if (!vtag_req) { 2266 err = -ENOMEM; 2267 goto out; 2268 } 2269 2270 /* configure tx vtag params */ 2271 vtag_req->vtag_size = VTAGSIZE_T4; 2272 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2273 vtag_req->tx.cfg_vtag0 = 1; 2274 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2275 2276 err = otx2_sync_mbox_msg(&pf->mbox); 2277 if (err) 2278 goto out; 2279 2280 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2281 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2282 if (IS_ERR(vtag_rsp)) { 2283 err = PTR_ERR(vtag_rsp); 2284 goto out; 2285 } 2286 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2287 2288 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2289 if (!req) { 2290 err = -ENOMEM; 2291 goto out; 2292 } 2293 2294 eth_zero_addr((u8 *)&req->mask.dmac); 2295 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2296 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2297 req->features = BIT_ULL(NPC_DMAC); 2298 req->channel = pf->hw.tx_chan_base; 2299 req->intf = NIX_INTF_TX; 2300 req->vf = vf + 1; 2301 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2302 req->vtag0_def = vtag_rsp->vtag0_idx; 2303 req->vtag0_op = VTAG_INSERT; 2304 req->set_cntr = 1; 2305 2306 err = otx2_sync_mbox_msg(&pf->mbox); 2307 out: 2308 config->vlan = vlan; 2309 mutex_unlock(&pf->mbox.lock); 2310 return err; 2311 } 2312 2313 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2314 __be16 proto) 2315 { 2316 struct otx2_nic *pf = netdev_priv(netdev); 2317 struct pci_dev *pdev = pf->pdev; 2318 2319 if (!netif_running(netdev)) 2320 return -EAGAIN; 2321 2322 if (vf >= pci_num_vf(pdev)) 2323 return -EINVAL; 2324 2325 /* qos is currently unsupported */ 2326 if (vlan >= VLAN_N_VID || qos) 2327 return -EINVAL; 2328 2329 if (proto != htons(ETH_P_8021Q)) 2330 return -EPROTONOSUPPORT; 2331 2332 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2333 return -EOPNOTSUPP; 2334 2335 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2336 } 2337 2338 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2339 struct ifla_vf_info *ivi) 2340 { 2341 struct otx2_nic *pf = netdev_priv(netdev); 2342 struct pci_dev *pdev = pf->pdev; 2343 struct otx2_vf_config *config; 2344 2345 if (!netif_running(netdev)) 2346 return -EAGAIN; 2347 2348 if (vf >= pci_num_vf(pdev)) 2349 return -EINVAL; 2350 2351 config = &pf->vf_configs[vf]; 2352 ivi->vf = vf; 2353 ether_addr_copy(ivi->mac, config->mac); 2354 ivi->vlan = config->vlan; 2355 ivi->trusted = config->trusted; 2356 2357 return 0; 2358 } 2359 2360 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2361 int qidx) 2362 { 2363 struct page *page; 2364 u64 dma_addr; 2365 int err = 0; 2366 2367 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2368 offset_in_page(xdpf->data), xdpf->len, 2369 DMA_TO_DEVICE); 2370 if (dma_mapping_error(pf->dev, dma_addr)) 2371 return -ENOMEM; 2372 2373 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2374 if (!err) { 2375 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2376 page = virt_to_page(xdpf->data); 2377 put_page(page); 2378 return -ENOMEM; 2379 } 2380 return 0; 2381 } 2382 2383 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2384 struct xdp_frame **frames, u32 flags) 2385 { 2386 struct otx2_nic *pf = netdev_priv(netdev); 2387 int qidx = smp_processor_id(); 2388 struct otx2_snd_queue *sq; 2389 int drops = 0, i; 2390 2391 if (!netif_running(netdev)) 2392 return -ENETDOWN; 2393 2394 qidx += pf->hw.tx_queues; 2395 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2396 2397 /* Abort xmit if xdp queue is not */ 2398 if (unlikely(!sq)) 2399 return -ENXIO; 2400 2401 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2402 return -EINVAL; 2403 2404 for (i = 0; i < n; i++) { 2405 struct xdp_frame *xdpf = frames[i]; 2406 int err; 2407 2408 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2409 if (err) 2410 drops++; 2411 } 2412 return n - drops; 2413 } 2414 2415 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2416 { 2417 struct net_device *dev = pf->netdev; 2418 bool if_up = netif_running(pf->netdev); 2419 struct bpf_prog *old_prog; 2420 2421 if (prog && dev->mtu > MAX_XDP_MTU) { 2422 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2423 return -EOPNOTSUPP; 2424 } 2425 2426 if (if_up) 2427 otx2_stop(pf->netdev); 2428 2429 old_prog = xchg(&pf->xdp_prog, prog); 2430 2431 if (old_prog) 2432 bpf_prog_put(old_prog); 2433 2434 if (pf->xdp_prog) 2435 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2436 2437 /* Network stack and XDP shared same rx queues. 2438 * Use separate tx queues for XDP and network stack. 2439 */ 2440 if (pf->xdp_prog) 2441 pf->hw.xdp_queues = pf->hw.rx_queues; 2442 else 2443 pf->hw.xdp_queues = 0; 2444 2445 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2446 2447 if (if_up) 2448 otx2_open(pf->netdev); 2449 2450 return 0; 2451 } 2452 2453 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2454 { 2455 struct otx2_nic *pf = netdev_priv(netdev); 2456 2457 switch (xdp->command) { 2458 case XDP_SETUP_PROG: 2459 return otx2_xdp_setup(pf, xdp->prog); 2460 default: 2461 return -EINVAL; 2462 } 2463 } 2464 2465 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2466 int req_perm) 2467 { 2468 struct set_vf_perm *req; 2469 int rc; 2470 2471 mutex_lock(&pf->mbox.lock); 2472 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2473 if (!req) { 2474 rc = -ENOMEM; 2475 goto out; 2476 } 2477 2478 /* Let AF reset VF permissions as sriov is disabled */ 2479 if (req_perm == OTX2_RESET_VF_PERM) { 2480 req->flags |= RESET_VF_PERM; 2481 } else if (req_perm == OTX2_TRUSTED_VF) { 2482 if (pf->vf_configs[vf].trusted) 2483 req->flags |= VF_TRUSTED; 2484 } 2485 2486 req->vf = vf; 2487 rc = otx2_sync_mbox_msg(&pf->mbox); 2488 out: 2489 mutex_unlock(&pf->mbox.lock); 2490 return rc; 2491 } 2492 2493 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2494 bool enable) 2495 { 2496 struct otx2_nic *pf = netdev_priv(netdev); 2497 struct pci_dev *pdev = pf->pdev; 2498 int rc; 2499 2500 if (vf >= pci_num_vf(pdev)) 2501 return -EINVAL; 2502 2503 if (pf->vf_configs[vf].trusted == enable) 2504 return 0; 2505 2506 pf->vf_configs[vf].trusted = enable; 2507 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2508 2509 if (rc) 2510 pf->vf_configs[vf].trusted = !enable; 2511 else 2512 netdev_info(pf->netdev, "VF %d is %strusted\n", 2513 vf, enable ? "" : "not "); 2514 return rc; 2515 } 2516 2517 static const struct net_device_ops otx2_netdev_ops = { 2518 .ndo_open = otx2_open, 2519 .ndo_stop = otx2_stop, 2520 .ndo_start_xmit = otx2_xmit, 2521 .ndo_select_queue = otx2_select_queue, 2522 .ndo_fix_features = otx2_fix_features, 2523 .ndo_set_mac_address = otx2_set_mac_address, 2524 .ndo_change_mtu = otx2_change_mtu, 2525 .ndo_set_rx_mode = otx2_set_rx_mode, 2526 .ndo_set_features = otx2_set_features, 2527 .ndo_tx_timeout = otx2_tx_timeout, 2528 .ndo_get_stats64 = otx2_get_stats64, 2529 .ndo_eth_ioctl = otx2_ioctl, 2530 .ndo_set_vf_mac = otx2_set_vf_mac, 2531 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2532 .ndo_get_vf_config = otx2_get_vf_config, 2533 .ndo_bpf = otx2_xdp, 2534 .ndo_xdp_xmit = otx2_xdp_xmit, 2535 .ndo_setup_tc = otx2_setup_tc, 2536 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2537 }; 2538 2539 static int otx2_wq_init(struct otx2_nic *pf) 2540 { 2541 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2542 if (!pf->otx2_wq) 2543 return -ENOMEM; 2544 2545 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2546 INIT_WORK(&pf->reset_task, otx2_reset_task); 2547 return 0; 2548 } 2549 2550 static int otx2_check_pf_usable(struct otx2_nic *nic) 2551 { 2552 u64 rev; 2553 2554 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2555 rev = (rev >> 12) & 0xFF; 2556 /* Check if AF has setup revision for RVUM block, 2557 * otherwise this driver probe should be deferred 2558 * until AF driver comes up. 2559 */ 2560 if (!rev) { 2561 dev_warn(nic->dev, 2562 "AF is not initialized, deferring probe\n"); 2563 return -EPROBE_DEFER; 2564 } 2565 return 0; 2566 } 2567 2568 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2569 { 2570 struct otx2_hw *hw = &pf->hw; 2571 int num_vec, err; 2572 2573 /* NPA interrupts are inot registered, so alloc only 2574 * upto NIX vector offset. 2575 */ 2576 num_vec = hw->nix_msixoff; 2577 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2578 2579 otx2_disable_mbox_intr(pf); 2580 pci_free_irq_vectors(hw->pdev); 2581 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2582 if (err < 0) { 2583 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2584 __func__, num_vec); 2585 return err; 2586 } 2587 2588 return otx2_register_mbox_intr(pf, false); 2589 } 2590 2591 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2592 { 2593 int i; 2594 2595 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2596 sizeof(struct otx2_vf_config), 2597 GFP_KERNEL); 2598 if (!pf->vf_configs) 2599 return -ENOMEM; 2600 2601 for (i = 0; i < pf->total_vfs; i++) { 2602 pf->vf_configs[i].pf = pf; 2603 pf->vf_configs[i].intf_down = true; 2604 pf->vf_configs[i].trusted = false; 2605 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2606 otx2_vf_link_event_task); 2607 } 2608 2609 return 0; 2610 } 2611 2612 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2613 { 2614 int i; 2615 2616 if (!pf->vf_configs) 2617 return; 2618 2619 for (i = 0; i < pf->total_vfs; i++) { 2620 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2621 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2622 } 2623 } 2624 2625 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2626 { 2627 struct device *dev = &pdev->dev; 2628 struct net_device *netdev; 2629 struct otx2_nic *pf; 2630 struct otx2_hw *hw; 2631 int err, qcount; 2632 int num_vec; 2633 2634 err = pcim_enable_device(pdev); 2635 if (err) { 2636 dev_err(dev, "Failed to enable PCI device\n"); 2637 return err; 2638 } 2639 2640 err = pci_request_regions(pdev, DRV_NAME); 2641 if (err) { 2642 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2643 return err; 2644 } 2645 2646 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2647 if (err) { 2648 dev_err(dev, "DMA mask config failed, abort\n"); 2649 goto err_release_regions; 2650 } 2651 2652 pci_set_master(pdev); 2653 2654 /* Set number of queues */ 2655 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2656 2657 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2658 if (!netdev) { 2659 err = -ENOMEM; 2660 goto err_release_regions; 2661 } 2662 2663 pci_set_drvdata(pdev, netdev); 2664 SET_NETDEV_DEV(netdev, &pdev->dev); 2665 pf = netdev_priv(netdev); 2666 pf->netdev = netdev; 2667 pf->pdev = pdev; 2668 pf->dev = dev; 2669 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2670 pf->flags |= OTX2_FLAG_INTF_DOWN; 2671 2672 hw = &pf->hw; 2673 hw->pdev = pdev; 2674 hw->rx_queues = qcount; 2675 hw->tx_queues = qcount; 2676 hw->tot_tx_queues = qcount; 2677 hw->max_queues = qcount; 2678 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2679 /* Use CQE of 128 byte descriptor size by default */ 2680 hw->xqe_size = 128; 2681 2682 num_vec = pci_msix_vec_count(pdev); 2683 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2684 GFP_KERNEL); 2685 if (!hw->irq_name) { 2686 err = -ENOMEM; 2687 goto err_free_netdev; 2688 } 2689 2690 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2691 sizeof(cpumask_var_t), GFP_KERNEL); 2692 if (!hw->affinity_mask) { 2693 err = -ENOMEM; 2694 goto err_free_netdev; 2695 } 2696 2697 /* Map CSRs */ 2698 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2699 if (!pf->reg_base) { 2700 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2701 err = -ENOMEM; 2702 goto err_free_netdev; 2703 } 2704 2705 err = otx2_check_pf_usable(pf); 2706 if (err) 2707 goto err_free_netdev; 2708 2709 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2710 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2711 if (err < 0) { 2712 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2713 __func__, num_vec); 2714 goto err_free_netdev; 2715 } 2716 2717 otx2_setup_dev_hw_settings(pf); 2718 2719 /* Init PF <=> AF mailbox stuff */ 2720 err = otx2_pfaf_mbox_init(pf); 2721 if (err) 2722 goto err_free_irq_vectors; 2723 2724 /* Register mailbox interrupt */ 2725 err = otx2_register_mbox_intr(pf, true); 2726 if (err) 2727 goto err_mbox_destroy; 2728 2729 /* Request AF to attach NPA and NIX LFs to this PF. 2730 * NIX and NPA LFs are needed for this PF to function as a NIC. 2731 */ 2732 err = otx2_attach_npa_nix(pf); 2733 if (err) 2734 goto err_disable_mbox_intr; 2735 2736 err = otx2_realloc_msix_vectors(pf); 2737 if (err) 2738 goto err_detach_rsrc; 2739 2740 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2741 if (err) 2742 goto err_detach_rsrc; 2743 2744 err = cn10k_lmtst_init(pf); 2745 if (err) 2746 goto err_detach_rsrc; 2747 2748 /* Assign default mac address */ 2749 otx2_get_mac_from_af(netdev); 2750 2751 /* Don't check for error. Proceed without ptp */ 2752 otx2_ptp_init(pf); 2753 2754 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2755 * HW allocates buffer pointer from stack and uses it for DMA'ing 2756 * ingress packet. In some scenarios HW can free back allocated buffer 2757 * pointers to pool. This makes it impossible for SW to maintain a 2758 * parallel list where physical addresses of buffer pointers (IOVAs) 2759 * given to HW can be saved for later reference. 2760 * 2761 * So the only way to convert Rx packet's buffer address is to use 2762 * IOMMU's iova_to_phys() handler which translates the address by 2763 * walking through the translation tables. 2764 */ 2765 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2766 2767 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2768 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2769 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2770 NETIF_F_GSO_UDP_L4); 2771 netdev->features |= netdev->hw_features; 2772 2773 err = otx2_mcam_flow_init(pf); 2774 if (err) 2775 goto err_ptp_destroy; 2776 2777 err = cn10k_mcs_init(pf); 2778 if (err) 2779 goto err_del_mcam_entries; 2780 2781 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2782 netdev->hw_features |= NETIF_F_NTUPLE; 2783 2784 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2785 netdev->priv_flags |= IFF_UNICAST_FLT; 2786 2787 /* Support TSO on tag interface */ 2788 netdev->vlan_features |= netdev->features; 2789 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2790 NETIF_F_HW_VLAN_STAG_TX; 2791 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2792 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2793 NETIF_F_HW_VLAN_STAG_RX; 2794 netdev->features |= netdev->hw_features; 2795 2796 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2797 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2798 netdev->hw_features |= NETIF_F_HW_TC; 2799 2800 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2801 2802 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2803 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2804 2805 netdev->netdev_ops = &otx2_netdev_ops; 2806 2807 netdev->min_mtu = OTX2_MIN_MTU; 2808 netdev->max_mtu = otx2_get_max_mtu(pf); 2809 2810 err = register_netdev(netdev); 2811 if (err) { 2812 dev_err(dev, "Failed to register netdevice\n"); 2813 goto err_mcs_free; 2814 } 2815 2816 err = otx2_wq_init(pf); 2817 if (err) 2818 goto err_unreg_netdev; 2819 2820 otx2_set_ethtool_ops(netdev); 2821 2822 err = otx2_init_tc(pf); 2823 if (err) 2824 goto err_mcam_flow_del; 2825 2826 err = otx2_register_dl(pf); 2827 if (err) 2828 goto err_mcam_flow_del; 2829 2830 /* Initialize SR-IOV resources */ 2831 err = otx2_sriov_vfcfg_init(pf); 2832 if (err) 2833 goto err_pf_sriov_init; 2834 2835 /* Enable link notifications */ 2836 otx2_cgx_config_linkevents(pf, true); 2837 2838 #ifdef CONFIG_DCB 2839 err = otx2_dcbnl_set_ops(netdev); 2840 if (err) 2841 goto err_pf_sriov_init; 2842 #endif 2843 2844 return 0; 2845 2846 err_pf_sriov_init: 2847 otx2_shutdown_tc(pf); 2848 err_mcam_flow_del: 2849 otx2_mcam_flow_del(pf); 2850 err_unreg_netdev: 2851 unregister_netdev(netdev); 2852 err_mcs_free: 2853 cn10k_mcs_free(pf); 2854 err_del_mcam_entries: 2855 otx2_mcam_flow_del(pf); 2856 err_ptp_destroy: 2857 otx2_ptp_destroy(pf); 2858 err_detach_rsrc: 2859 if (pf->hw.lmt_info) 2860 free_percpu(pf->hw.lmt_info); 2861 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2862 qmem_free(pf->dev, pf->dync_lmt); 2863 otx2_detach_resources(&pf->mbox); 2864 err_disable_mbox_intr: 2865 otx2_disable_mbox_intr(pf); 2866 err_mbox_destroy: 2867 otx2_pfaf_mbox_destroy(pf); 2868 err_free_irq_vectors: 2869 pci_free_irq_vectors(hw->pdev); 2870 err_free_netdev: 2871 pci_set_drvdata(pdev, NULL); 2872 free_netdev(netdev); 2873 err_release_regions: 2874 pci_release_regions(pdev); 2875 return err; 2876 } 2877 2878 static void otx2_vf_link_event_task(struct work_struct *work) 2879 { 2880 struct otx2_vf_config *config; 2881 struct cgx_link_info_msg *req; 2882 struct mbox_msghdr *msghdr; 2883 struct otx2_nic *pf; 2884 int vf_idx; 2885 2886 config = container_of(work, struct otx2_vf_config, 2887 link_event_work.work); 2888 vf_idx = config - config->pf->vf_configs; 2889 pf = config->pf; 2890 2891 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2892 sizeof(*req), sizeof(struct msg_rsp)); 2893 if (!msghdr) { 2894 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2895 return; 2896 } 2897 2898 req = (struct cgx_link_info_msg *)msghdr; 2899 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2900 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2901 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2902 2903 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2904 } 2905 2906 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2907 { 2908 struct net_device *netdev = pci_get_drvdata(pdev); 2909 struct otx2_nic *pf = netdev_priv(netdev); 2910 int ret; 2911 2912 /* Init PF <=> VF mailbox stuff */ 2913 ret = otx2_pfvf_mbox_init(pf, numvfs); 2914 if (ret) 2915 return ret; 2916 2917 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2918 if (ret) 2919 goto free_mbox; 2920 2921 ret = otx2_pf_flr_init(pf, numvfs); 2922 if (ret) 2923 goto free_intr; 2924 2925 ret = otx2_register_flr_me_intr(pf, numvfs); 2926 if (ret) 2927 goto free_flr; 2928 2929 ret = pci_enable_sriov(pdev, numvfs); 2930 if (ret) 2931 goto free_flr_intr; 2932 2933 return numvfs; 2934 free_flr_intr: 2935 otx2_disable_flr_me_intr(pf); 2936 free_flr: 2937 otx2_flr_wq_destroy(pf); 2938 free_intr: 2939 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2940 free_mbox: 2941 otx2_pfvf_mbox_destroy(pf); 2942 return ret; 2943 } 2944 2945 static int otx2_sriov_disable(struct pci_dev *pdev) 2946 { 2947 struct net_device *netdev = pci_get_drvdata(pdev); 2948 struct otx2_nic *pf = netdev_priv(netdev); 2949 int numvfs = pci_num_vf(pdev); 2950 2951 if (!numvfs) 2952 return 0; 2953 2954 pci_disable_sriov(pdev); 2955 2956 otx2_disable_flr_me_intr(pf); 2957 otx2_flr_wq_destroy(pf); 2958 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2959 otx2_pfvf_mbox_destroy(pf); 2960 2961 return 0; 2962 } 2963 2964 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2965 { 2966 if (numvfs == 0) 2967 return otx2_sriov_disable(pdev); 2968 else 2969 return otx2_sriov_enable(pdev, numvfs); 2970 } 2971 2972 static void otx2_remove(struct pci_dev *pdev) 2973 { 2974 struct net_device *netdev = pci_get_drvdata(pdev); 2975 struct otx2_nic *pf; 2976 2977 if (!netdev) 2978 return; 2979 2980 pf = netdev_priv(netdev); 2981 2982 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2983 2984 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2985 otx2_config_hw_tx_tstamp(pf, false); 2986 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2987 otx2_config_hw_rx_tstamp(pf, false); 2988 2989 /* Disable 802.3x pause frames */ 2990 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 2991 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 2992 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 2993 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 2994 otx2_config_pause_frm(pf); 2995 } 2996 2997 cn10k_mcs_free(pf); 2998 2999 #ifdef CONFIG_DCB 3000 /* Disable PFC config */ 3001 if (pf->pfc_en) { 3002 pf->pfc_en = 0; 3003 otx2_config_priority_flow_ctrl(pf); 3004 } 3005 #endif 3006 cancel_work_sync(&pf->reset_task); 3007 /* Disable link notifications */ 3008 otx2_cgx_config_linkevents(pf, false); 3009 3010 otx2_unregister_dl(pf); 3011 unregister_netdev(netdev); 3012 otx2_sriov_disable(pf->pdev); 3013 otx2_sriov_vfcfg_cleanup(pf); 3014 if (pf->otx2_wq) 3015 destroy_workqueue(pf->otx2_wq); 3016 3017 otx2_ptp_destroy(pf); 3018 otx2_mcam_flow_del(pf); 3019 otx2_shutdown_tc(pf); 3020 otx2_detach_resources(&pf->mbox); 3021 if (pf->hw.lmt_info) 3022 free_percpu(pf->hw.lmt_info); 3023 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3024 qmem_free(pf->dev, pf->dync_lmt); 3025 otx2_disable_mbox_intr(pf); 3026 otx2_pfaf_mbox_destroy(pf); 3027 pci_free_irq_vectors(pf->pdev); 3028 pci_set_drvdata(pdev, NULL); 3029 free_netdev(netdev); 3030 3031 pci_release_regions(pdev); 3032 } 3033 3034 static struct pci_driver otx2_pf_driver = { 3035 .name = DRV_NAME, 3036 .id_table = otx2_pf_id_table, 3037 .probe = otx2_probe, 3038 .shutdown = otx2_remove, 3039 .remove = otx2_remove, 3040 .sriov_configure = otx2_sriov_configure 3041 }; 3042 3043 static int __init otx2_rvupf_init_module(void) 3044 { 3045 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3046 3047 return pci_register_driver(&otx2_pf_driver); 3048 } 3049 3050 static void __exit otx2_rvupf_cleanup_module(void) 3051 { 3052 pci_unregister_driver(&otx2_pf_driver); 3053 } 3054 3055 module_init(otx2_rvupf_init_module); 3056 module_exit(otx2_rvupf_cleanup_module); 3057