1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 19 #include "otx2_reg.h" 20 #include "otx2_common.h" 21 #include "otx2_txrx.h" 22 #include "otx2_struct.h" 23 #include "otx2_ptp.h" 24 #include "cn10k.h" 25 #include <rvu_trace.h> 26 27 #define DRV_NAME "rvu_nicpf" 28 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 29 30 /* Supported devices */ 31 static const struct pci_device_id otx2_pf_id_table[] = { 32 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 33 { 0, } /* end of table */ 34 }; 35 36 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 37 MODULE_DESCRIPTION(DRV_STRING); 38 MODULE_LICENSE("GPL v2"); 39 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 40 41 static void otx2_vf_link_event_task(struct work_struct *work); 42 43 enum { 44 TYPE_PFAF, 45 TYPE_PFVF, 46 }; 47 48 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 49 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 50 51 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 52 { 53 struct otx2_nic *pf = netdev_priv(netdev); 54 bool if_up = netif_running(netdev); 55 int err = 0; 56 57 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 58 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 59 netdev->mtu); 60 return -EINVAL; 61 } 62 if (if_up) 63 otx2_stop(netdev); 64 65 netdev_info(netdev, "Changing MTU from %d to %d\n", 66 netdev->mtu, new_mtu); 67 netdev->mtu = new_mtu; 68 69 if (if_up) 70 err = otx2_open(netdev); 71 72 return err; 73 } 74 75 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 76 { 77 int irq, vfs = pf->total_vfs; 78 79 /* Disable VFs ME interrupts */ 80 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 81 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 82 free_irq(irq, pf); 83 84 /* Disable VFs FLR interrupts */ 85 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 87 free_irq(irq, pf); 88 89 if (vfs <= 64) 90 return; 91 92 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 93 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 94 free_irq(irq, pf); 95 96 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 97 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 98 free_irq(irq, pf); 99 } 100 101 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 102 { 103 if (!pf->flr_wq) 104 return; 105 destroy_workqueue(pf->flr_wq); 106 pf->flr_wq = NULL; 107 devm_kfree(pf->dev, pf->flr_wrk); 108 } 109 110 static void otx2_flr_handler(struct work_struct *work) 111 { 112 struct flr_work *flrwork = container_of(work, struct flr_work, work); 113 struct otx2_nic *pf = flrwork->pf; 114 struct mbox *mbox = &pf->mbox; 115 struct msg_req *req; 116 int vf, reg = 0; 117 118 vf = flrwork - pf->flr_wrk; 119 120 mutex_lock(&mbox->lock); 121 req = otx2_mbox_alloc_msg_vf_flr(mbox); 122 if (!req) { 123 mutex_unlock(&mbox->lock); 124 return; 125 } 126 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 127 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 128 129 if (!otx2_sync_mbox_msg(&pf->mbox)) { 130 if (vf >= 64) { 131 reg = 1; 132 vf = vf - 64; 133 } 134 /* clear transcation pending bit */ 135 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 136 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 137 } 138 139 mutex_unlock(&mbox->lock); 140 } 141 142 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 143 { 144 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 145 int reg, dev, vf, start_vf, num_reg = 1; 146 u64 intr; 147 148 if (pf->total_vfs > 64) 149 num_reg = 2; 150 151 for (reg = 0; reg < num_reg; reg++) { 152 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 153 if (!intr) 154 continue; 155 start_vf = 64 * reg; 156 for (vf = 0; vf < 64; vf++) { 157 if (!(intr & BIT_ULL(vf))) 158 continue; 159 dev = vf + start_vf; 160 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 161 /* Clear interrupt */ 162 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 163 /* Disable the interrupt */ 164 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 165 BIT_ULL(vf)); 166 } 167 } 168 return IRQ_HANDLED; 169 } 170 171 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 172 { 173 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 174 int vf, reg, num_reg = 1; 175 u64 intr; 176 177 if (pf->total_vfs > 64) 178 num_reg = 2; 179 180 for (reg = 0; reg < num_reg; reg++) { 181 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 182 if (!intr) 183 continue; 184 for (vf = 0; vf < 64; vf++) { 185 if (!(intr & BIT_ULL(vf))) 186 continue; 187 /* clear trpend bit */ 188 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 189 /* clear interrupt */ 190 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 191 } 192 } 193 return IRQ_HANDLED; 194 } 195 196 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 197 { 198 struct otx2_hw *hw = &pf->hw; 199 char *irq_name; 200 int ret; 201 202 /* Register ME interrupt handler*/ 203 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 204 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", rvu_get_pf(pf->pcifunc)); 205 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 206 otx2_pf_me_intr_handler, 0, irq_name, pf); 207 if (ret) { 208 dev_err(pf->dev, 209 "RVUPF: IRQ registration failed for ME0\n"); 210 } 211 212 /* Register FLR interrupt handler */ 213 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 214 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", rvu_get_pf(pf->pcifunc)); 215 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 216 otx2_pf_flr_intr_handler, 0, irq_name, pf); 217 if (ret) { 218 dev_err(pf->dev, 219 "RVUPF: IRQ registration failed for FLR0\n"); 220 return ret; 221 } 222 223 if (numvfs > 64) { 224 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 225 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 226 rvu_get_pf(pf->pcifunc)); 227 ret = request_irq(pci_irq_vector 228 (pf->pdev, RVU_PF_INT_VEC_VFME1), 229 otx2_pf_me_intr_handler, 0, irq_name, pf); 230 if (ret) { 231 dev_err(pf->dev, 232 "RVUPF: IRQ registration failed for ME1\n"); 233 } 234 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 235 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 236 rvu_get_pf(pf->pcifunc)); 237 ret = request_irq(pci_irq_vector 238 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 239 otx2_pf_flr_intr_handler, 0, irq_name, pf); 240 if (ret) { 241 dev_err(pf->dev, 242 "RVUPF: IRQ registration failed for FLR1\n"); 243 return ret; 244 } 245 } 246 247 /* Enable ME interrupt for all VFs*/ 248 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 249 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 250 251 /* Enable FLR interrupt for all VFs*/ 252 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 253 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 254 255 if (numvfs > 64) { 256 numvfs -= 64; 257 258 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 259 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 260 INTR_MASK(numvfs)); 261 262 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 263 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 264 INTR_MASK(numvfs)); 265 } 266 return 0; 267 } 268 269 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 270 { 271 int vf; 272 273 pf->flr_wq = alloc_workqueue("otx2_pf_flr_wq", 274 WQ_UNBOUND | WQ_HIGHPRI, 1); 275 if (!pf->flr_wq) 276 return -ENOMEM; 277 278 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 279 sizeof(struct flr_work), GFP_KERNEL); 280 if (!pf->flr_wrk) { 281 destroy_workqueue(pf->flr_wq); 282 return -ENOMEM; 283 } 284 285 for (vf = 0; vf < num_vfs; vf++) { 286 pf->flr_wrk[vf].pf = pf; 287 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 288 } 289 290 return 0; 291 } 292 293 static void otx2_queue_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 294 int first, int mdevs, u64 intr, int type) 295 { 296 struct otx2_mbox_dev *mdev; 297 struct otx2_mbox *mbox; 298 struct mbox_hdr *hdr; 299 int i; 300 301 for (i = first; i < mdevs; i++) { 302 /* start from 0 */ 303 if (!(intr & BIT_ULL(i - first))) 304 continue; 305 306 mbox = &mw->mbox; 307 mdev = &mbox->dev[i]; 308 if (type == TYPE_PFAF) 309 otx2_sync_mbox_bbuf(mbox, i); 310 hdr = mdev->mbase + mbox->rx_start; 311 /* The hdr->num_msgs is set to zero immediately in the interrupt 312 * handler to ensure that it holds a correct value next time 313 * when the interrupt handler is called. 314 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler 315 * pf>mbox.up_num_msgs holds the data for use in 316 * pfaf_mbox_up_handler. 317 */ 318 if (hdr->num_msgs) { 319 mw[i].num_msgs = hdr->num_msgs; 320 hdr->num_msgs = 0; 321 if (type == TYPE_PFAF) 322 memset(mbox->hwbase + mbox->rx_start, 0, 323 ALIGN(sizeof(struct mbox_hdr), 324 sizeof(u64))); 325 326 queue_work(mbox_wq, &mw[i].mbox_wrk); 327 } 328 329 mbox = &mw->mbox_up; 330 mdev = &mbox->dev[i]; 331 if (type == TYPE_PFAF) 332 otx2_sync_mbox_bbuf(mbox, i); 333 hdr = mdev->mbase + mbox->rx_start; 334 if (hdr->num_msgs) { 335 mw[i].up_num_msgs = hdr->num_msgs; 336 hdr->num_msgs = 0; 337 if (type == TYPE_PFAF) 338 memset(mbox->hwbase + mbox->rx_start, 0, 339 ALIGN(sizeof(struct mbox_hdr), 340 sizeof(u64))); 341 342 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 343 } 344 } 345 } 346 347 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 348 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 349 int devid) 350 { 351 struct otx2_mbox_dev *src_mdev = mdev; 352 int offset; 353 354 /* Msgs are already copied, trigger VF's mbox irq */ 355 smp_wmb(); 356 357 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 358 writeq(1, (void __iomem *)pfvf_mbox->reg_base + offset); 359 360 /* Restore VF's mbox bounce buffer region address */ 361 src_mdev->mbase = bbuf_base; 362 } 363 364 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 365 struct otx2_mbox *src_mbox, 366 int dir, int vf, int num_msgs) 367 { 368 struct otx2_mbox_dev *src_mdev, *dst_mdev; 369 struct mbox_hdr *mbox_hdr; 370 struct mbox_hdr *req_hdr; 371 struct mbox *dst_mbox; 372 int dst_size, err; 373 374 if (dir == MBOX_DIR_PFAF) { 375 /* Set VF's mailbox memory as PF's bounce buffer memory, so 376 * that explicit copying of VF's msgs to PF=>AF mbox region 377 * and AF=>PF responses to VF's mbox region can be avoided. 378 */ 379 src_mdev = &src_mbox->dev[vf]; 380 mbox_hdr = src_mbox->hwbase + 381 src_mbox->rx_start + (vf * MBOX_SIZE); 382 383 dst_mbox = &pf->mbox; 384 dst_size = dst_mbox->mbox.tx_size - 385 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 386 /* Check if msgs fit into destination area and has valid size */ 387 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 388 return -EINVAL; 389 390 dst_mdev = &dst_mbox->mbox.dev[0]; 391 392 mutex_lock(&pf->mbox.lock); 393 dst_mdev->mbase = src_mdev->mbase; 394 dst_mdev->msg_size = mbox_hdr->msg_size; 395 dst_mdev->num_msgs = num_msgs; 396 err = otx2_sync_mbox_msg(dst_mbox); 397 /* Error code -EIO indicate there is a communication failure 398 * to the AF. Rest of the error codes indicate that AF processed 399 * VF messages and set the error codes in response messages 400 * (if any) so simply forward responses to VF. 401 */ 402 if (err == -EIO) { 403 dev_warn(pf->dev, 404 "AF not responding to VF%d messages\n", vf); 405 /* restore PF mbase and exit */ 406 dst_mdev->mbase = pf->mbox.bbuf_base; 407 mutex_unlock(&pf->mbox.lock); 408 return err; 409 } 410 /* At this point, all the VF messages sent to AF are acked 411 * with proper responses and responses are copied to VF 412 * mailbox hence raise interrupt to VF. 413 */ 414 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 415 dst_mbox->mbox.rx_start); 416 req_hdr->num_msgs = num_msgs; 417 418 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 419 pf->mbox.bbuf_base, vf); 420 mutex_unlock(&pf->mbox.lock); 421 } else if (dir == MBOX_DIR_PFVF_UP) { 422 src_mdev = &src_mbox->dev[0]; 423 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 424 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 425 src_mbox->rx_start); 426 req_hdr->num_msgs = num_msgs; 427 428 dst_mbox = &pf->mbox_pfvf[0]; 429 dst_size = dst_mbox->mbox_up.tx_size - 430 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 431 /* Check if msgs fit into destination area */ 432 if (mbox_hdr->msg_size > dst_size) 433 return -EINVAL; 434 435 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 436 dst_mdev->mbase = src_mdev->mbase; 437 dst_mdev->msg_size = mbox_hdr->msg_size; 438 dst_mdev->num_msgs = mbox_hdr->num_msgs; 439 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 440 if (err) { 441 dev_warn(pf->dev, 442 "VF%d is not responding to mailbox\n", vf); 443 return err; 444 } 445 } else if (dir == MBOX_DIR_VFPF_UP) { 446 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 447 src_mbox->rx_start); 448 req_hdr->num_msgs = num_msgs; 449 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 450 &pf->mbox.mbox_up, 451 pf->mbox_pfvf[vf].bbuf_base, 452 0); 453 } 454 455 return 0; 456 } 457 458 static void otx2_pfvf_mbox_handler(struct work_struct *work) 459 { 460 struct mbox_msghdr *msg = NULL; 461 int offset, vf_idx, id, err; 462 struct otx2_mbox_dev *mdev; 463 struct mbox_hdr *req_hdr; 464 struct otx2_mbox *mbox; 465 struct mbox *vf_mbox; 466 struct otx2_nic *pf; 467 468 vf_mbox = container_of(work, struct mbox, mbox_wrk); 469 pf = vf_mbox->pfvf; 470 vf_idx = vf_mbox - pf->mbox_pfvf; 471 472 mbox = &pf->mbox_pfvf[0].mbox; 473 mdev = &mbox->dev[vf_idx]; 474 req_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 475 476 offset = ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN); 477 478 for (id = 0; id < vf_mbox->num_msgs; id++) { 479 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 480 offset); 481 482 if (msg->sig != OTX2_MBOX_REQ_SIG) 483 goto inval_msg; 484 485 /* Set VF's number in each of the msg */ 486 msg->pcifunc &= RVU_PFVF_FUNC_MASK; 487 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 488 offset = msg->next_msgoff; 489 } 490 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 491 vf_mbox->num_msgs); 492 if (err) 493 goto inval_msg; 494 return; 495 496 inval_msg: 497 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 498 otx2_mbox_msg_send(mbox, vf_idx); 499 } 500 501 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 502 { 503 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 504 struct otx2_nic *pf = vf_mbox->pfvf; 505 struct otx2_mbox_dev *mdev; 506 int offset, id, vf_idx = 0; 507 struct mbox_hdr *rsp_hdr; 508 struct mbox_msghdr *msg; 509 struct otx2_mbox *mbox; 510 511 vf_idx = vf_mbox - pf->mbox_pfvf; 512 mbox = &pf->mbox_pfvf[0].mbox_up; 513 mdev = &mbox->dev[vf_idx]; 514 515 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 516 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 517 518 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 519 msg = mdev->mbase + offset; 520 521 if (msg->id >= MBOX_MSG_MAX) { 522 dev_err(pf->dev, 523 "Mbox msg with unknown ID 0x%x\n", msg->id); 524 goto end; 525 } 526 527 if (msg->sig != OTX2_MBOX_RSP_SIG) { 528 dev_err(pf->dev, 529 "Mbox msg with wrong signature %x, ID 0x%x\n", 530 msg->sig, msg->id); 531 goto end; 532 } 533 534 switch (msg->id) { 535 case MBOX_MSG_CGX_LINK_EVENT: 536 break; 537 default: 538 if (msg->rc) 539 dev_err(pf->dev, 540 "Mbox msg response has err %d, ID 0x%x\n", 541 msg->rc, msg->id); 542 break; 543 } 544 545 end: 546 offset = mbox->rx_start + msg->next_msgoff; 547 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 548 __otx2_mbox_reset(mbox, 0); 549 mdev->msgs_acked++; 550 } 551 } 552 553 static irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 554 { 555 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 556 int vfs = pf->total_vfs; 557 struct mbox *mbox; 558 u64 intr; 559 560 mbox = pf->mbox_pfvf; 561 /* Handle VF interrupts */ 562 if (vfs > 64) { 563 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 564 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 565 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr, 566 TYPE_PFVF); 567 vfs -= 64; 568 } 569 570 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 571 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 572 573 otx2_queue_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr, TYPE_PFVF); 574 575 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 576 577 return IRQ_HANDLED; 578 } 579 580 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 581 { 582 void __iomem *hwbase; 583 struct mbox *mbox; 584 int err, vf; 585 u64 base; 586 587 if (!numvfs) 588 return -EINVAL; 589 590 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 591 sizeof(struct mbox), GFP_KERNEL); 592 if (!pf->mbox_pfvf) 593 return -ENOMEM; 594 595 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 596 WQ_UNBOUND | WQ_HIGHPRI | 597 WQ_MEM_RECLAIM, 1); 598 if (!pf->mbox_pfvf_wq) 599 return -ENOMEM; 600 601 /* On CN10K platform, PF <-> VF mailbox region follows after 602 * PF <-> AF mailbox region. 603 */ 604 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 605 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 606 MBOX_SIZE; 607 else 608 base = readq((void __iomem *)((u64)pf->reg_base + 609 RVU_PF_VF_BAR4_ADDR)); 610 611 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 612 if (!hwbase) { 613 err = -ENOMEM; 614 goto free_wq; 615 } 616 617 mbox = &pf->mbox_pfvf[0]; 618 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 619 MBOX_DIR_PFVF, numvfs); 620 if (err) 621 goto free_iomem; 622 623 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 624 MBOX_DIR_PFVF_UP, numvfs); 625 if (err) 626 goto free_iomem; 627 628 for (vf = 0; vf < numvfs; vf++) { 629 mbox->pfvf = pf; 630 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 631 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 632 mbox++; 633 } 634 635 return 0; 636 637 free_iomem: 638 if (hwbase) 639 iounmap(hwbase); 640 free_wq: 641 destroy_workqueue(pf->mbox_pfvf_wq); 642 return err; 643 } 644 645 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 646 { 647 struct mbox *mbox = &pf->mbox_pfvf[0]; 648 649 if (!mbox) 650 return; 651 652 if (pf->mbox_pfvf_wq) { 653 destroy_workqueue(pf->mbox_pfvf_wq); 654 pf->mbox_pfvf_wq = NULL; 655 } 656 657 if (mbox->mbox.hwbase) 658 iounmap(mbox->mbox.hwbase); 659 660 otx2_mbox_destroy(&mbox->mbox); 661 } 662 663 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 664 { 665 /* Clear PF <=> VF mailbox IRQ */ 666 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 667 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 668 669 /* Enable PF <=> VF mailbox IRQ */ 670 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 671 if (numvfs > 64) { 672 numvfs -= 64; 673 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 674 INTR_MASK(numvfs)); 675 } 676 } 677 678 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 679 { 680 int vector; 681 682 /* Disable PF <=> VF mailbox IRQ */ 683 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 684 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 685 686 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 687 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 688 free_irq(vector, pf); 689 690 if (numvfs > 64) { 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 692 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 693 free_irq(vector, pf); 694 } 695 } 696 697 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 698 { 699 struct otx2_hw *hw = &pf->hw; 700 char *irq_name; 701 int err; 702 703 /* Register MBOX0 interrupt handler */ 704 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 705 if (pf->pcifunc) 706 snprintf(irq_name, NAME_SIZE, 707 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pcifunc)); 708 else 709 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 710 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 711 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 712 if (err) { 713 dev_err(pf->dev, 714 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 715 return err; 716 } 717 718 if (numvfs > 64) { 719 /* Register MBOX1 interrupt handler */ 720 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 721 if (pf->pcifunc) 722 snprintf(irq_name, NAME_SIZE, 723 "RVUPF%d_VF Mbox1", rvu_get_pf(pf->pcifunc)); 724 else 725 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 726 err = request_irq(pci_irq_vector(pf->pdev, 727 RVU_PF_INT_VEC_VFPF_MBOX1), 728 otx2_pfvf_mbox_intr_handler, 729 0, irq_name, pf); 730 if (err) { 731 dev_err(pf->dev, 732 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 733 return err; 734 } 735 } 736 737 otx2_enable_pfvf_mbox_intr(pf, numvfs); 738 739 return 0; 740 } 741 742 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 743 struct mbox_msghdr *msg) 744 { 745 int devid; 746 747 if (msg->id >= MBOX_MSG_MAX) { 748 dev_err(pf->dev, 749 "Mbox msg with unknown ID 0x%x\n", msg->id); 750 return; 751 } 752 753 if (msg->sig != OTX2_MBOX_RSP_SIG) { 754 dev_err(pf->dev, 755 "Mbox msg with wrong signature %x, ID 0x%x\n", 756 msg->sig, msg->id); 757 return; 758 } 759 760 /* message response heading VF */ 761 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 762 if (devid) { 763 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 764 struct delayed_work *dwork; 765 766 switch (msg->id) { 767 case MBOX_MSG_NIX_LF_START_RX: 768 config->intf_down = false; 769 dwork = &config->link_event_work; 770 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 771 break; 772 case MBOX_MSG_NIX_LF_STOP_RX: 773 config->intf_down = true; 774 break; 775 } 776 777 return; 778 } 779 780 switch (msg->id) { 781 case MBOX_MSG_READY: 782 pf->pcifunc = msg->pcifunc; 783 break; 784 case MBOX_MSG_MSIX_OFFSET: 785 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 786 break; 787 case MBOX_MSG_NPA_LF_ALLOC: 788 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 789 break; 790 case MBOX_MSG_NIX_LF_ALLOC: 791 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 792 break; 793 case MBOX_MSG_NIX_TXSCH_ALLOC: 794 mbox_handler_nix_txsch_alloc(pf, 795 (struct nix_txsch_alloc_rsp *)msg); 796 break; 797 case MBOX_MSG_NIX_BP_ENABLE: 798 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 799 break; 800 case MBOX_MSG_CGX_STATS: 801 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 802 break; 803 case MBOX_MSG_CGX_FEC_STATS: 804 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 805 break; 806 default: 807 if (msg->rc) 808 dev_err(pf->dev, 809 "Mbox msg response has err %d, ID 0x%x\n", 810 msg->rc, msg->id); 811 break; 812 } 813 } 814 815 static void otx2_pfaf_mbox_handler(struct work_struct *work) 816 { 817 struct otx2_mbox_dev *mdev; 818 struct mbox_hdr *rsp_hdr; 819 struct mbox_msghdr *msg; 820 struct otx2_mbox *mbox; 821 struct mbox *af_mbox; 822 struct otx2_nic *pf; 823 int offset, id; 824 825 af_mbox = container_of(work, struct mbox, mbox_wrk); 826 mbox = &af_mbox->mbox; 827 mdev = &mbox->dev[0]; 828 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 829 830 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 831 pf = af_mbox->pfvf; 832 833 for (id = 0; id < af_mbox->num_msgs; id++) { 834 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 835 otx2_process_pfaf_mbox_msg(pf, msg); 836 offset = mbox->rx_start + msg->next_msgoff; 837 if (mdev->msgs_acked == (af_mbox->num_msgs - 1)) 838 __otx2_mbox_reset(mbox, 0); 839 mdev->msgs_acked++; 840 } 841 842 } 843 844 static void otx2_handle_link_event(struct otx2_nic *pf) 845 { 846 struct cgx_link_user_info *linfo = &pf->linfo; 847 struct net_device *netdev = pf->netdev; 848 849 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 850 linfo->link_up ? "UP" : "DOWN", linfo->speed, 851 linfo->full_duplex ? "Full" : "Half"); 852 if (linfo->link_up) { 853 netif_carrier_on(netdev); 854 netif_tx_start_all_queues(netdev); 855 } else { 856 netif_tx_stop_all_queues(netdev); 857 netif_carrier_off(netdev); 858 } 859 } 860 861 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 862 struct cgx_link_info_msg *msg, 863 struct msg_rsp *rsp) 864 { 865 int i; 866 867 /* Copy the link info sent by AF */ 868 pf->linfo = msg->link_info; 869 870 /* notify VFs about link event */ 871 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 872 struct otx2_vf_config *config = &pf->vf_configs[i]; 873 struct delayed_work *dwork = &config->link_event_work; 874 875 if (config->intf_down) 876 continue; 877 878 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 879 } 880 881 /* interface has not been fully configured yet */ 882 if (pf->flags & OTX2_FLAG_INTF_DOWN) 883 return 0; 884 885 otx2_handle_link_event(pf); 886 return 0; 887 } 888 889 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 890 struct mbox_msghdr *req) 891 { 892 /* Check if valid, if not reply with a invalid msg */ 893 if (req->sig != OTX2_MBOX_REQ_SIG) { 894 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 895 return -ENODEV; 896 } 897 898 switch (req->id) { 899 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 900 case _id: { \ 901 struct _rsp_type *rsp; \ 902 int err; \ 903 \ 904 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 905 &pf->mbox.mbox_up, 0, \ 906 sizeof(struct _rsp_type)); \ 907 if (!rsp) \ 908 return -ENOMEM; \ 909 \ 910 rsp->hdr.id = _id; \ 911 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 912 rsp->hdr.pcifunc = 0; \ 913 rsp->hdr.rc = 0; \ 914 \ 915 err = otx2_mbox_up_handler_ ## _fn_name( \ 916 pf, (struct _req_type *)req, rsp); \ 917 return err; \ 918 } 919 MBOX_UP_CGX_MESSAGES 920 #undef M 921 break; 922 default: 923 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 924 return -ENODEV; 925 } 926 return 0; 927 } 928 929 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 930 { 931 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 932 struct otx2_mbox *mbox = &af_mbox->mbox_up; 933 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 934 struct otx2_nic *pf = af_mbox->pfvf; 935 int offset, id, devid = 0; 936 struct mbox_hdr *rsp_hdr; 937 struct mbox_msghdr *msg; 938 939 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 940 941 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 942 943 for (id = 0; id < af_mbox->up_num_msgs; id++) { 944 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 945 946 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 947 /* Skip processing VF's messages */ 948 if (!devid) 949 otx2_process_mbox_msg_up(pf, msg); 950 offset = mbox->rx_start + msg->next_msgoff; 951 } 952 if (devid) { 953 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 954 MBOX_DIR_PFVF_UP, devid - 1, 955 af_mbox->up_num_msgs); 956 return; 957 } 958 959 otx2_mbox_msg_send(mbox, 0); 960 } 961 962 static irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 963 { 964 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 965 struct mbox *mbox; 966 967 /* Clear the IRQ */ 968 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 969 970 mbox = &pf->mbox; 971 972 trace_otx2_msg_interrupt(mbox->mbox.pdev, "AF to PF", BIT_ULL(0)); 973 974 otx2_queue_work(mbox, pf->mbox_wq, 0, 1, 1, TYPE_PFAF); 975 976 return IRQ_HANDLED; 977 } 978 979 static void otx2_disable_mbox_intr(struct otx2_nic *pf) 980 { 981 int vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 982 983 /* Disable AF => PF mailbox IRQ */ 984 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 985 free_irq(vector, pf); 986 } 987 988 static int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 989 { 990 struct otx2_hw *hw = &pf->hw; 991 struct msg_req *req; 992 char *irq_name; 993 int err; 994 995 /* Register mailbox interrupt handler */ 996 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 997 snprintf(irq_name, NAME_SIZE, "RVUPFAF Mbox"); 998 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 999 otx2_pfaf_mbox_intr_handler, 0, irq_name, pf); 1000 if (err) { 1001 dev_err(pf->dev, 1002 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1003 return err; 1004 } 1005 1006 /* Enable mailbox interrupt for msgs coming from AF. 1007 * First clear to avoid spurious interrupts, if any. 1008 */ 1009 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1010 otx2_write64(pf, RVU_PF_INT_ENA_W1S, BIT_ULL(0)); 1011 1012 if (!probe_af) 1013 return 0; 1014 1015 /* Check mailbox communication with AF */ 1016 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1017 if (!req) { 1018 otx2_disable_mbox_intr(pf); 1019 return -ENOMEM; 1020 } 1021 err = otx2_sync_mbox_msg(&pf->mbox); 1022 if (err) { 1023 dev_warn(pf->dev, 1024 "AF not responding to mailbox, deferring probe\n"); 1025 otx2_disable_mbox_intr(pf); 1026 return -EPROBE_DEFER; 1027 } 1028 1029 return 0; 1030 } 1031 1032 static void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1033 { 1034 struct mbox *mbox = &pf->mbox; 1035 1036 if (pf->mbox_wq) { 1037 destroy_workqueue(pf->mbox_wq); 1038 pf->mbox_wq = NULL; 1039 } 1040 1041 if (mbox->mbox.hwbase) 1042 iounmap((void __iomem *)mbox->mbox.hwbase); 1043 1044 otx2_mbox_destroy(&mbox->mbox); 1045 otx2_mbox_destroy(&mbox->mbox_up); 1046 } 1047 1048 static int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1049 { 1050 struct mbox *mbox = &pf->mbox; 1051 void __iomem *hwbase; 1052 int err; 1053 1054 mbox->pfvf = pf; 1055 pf->mbox_wq = alloc_workqueue("otx2_pfaf_mailbox", 1056 WQ_UNBOUND | WQ_HIGHPRI | 1057 WQ_MEM_RECLAIM, 1); 1058 if (!pf->mbox_wq) 1059 return -ENOMEM; 1060 1061 /* Mailbox is a reserved memory (in RAM) region shared between 1062 * admin function (i.e AF) and this PF, shouldn't be mapped as 1063 * device memory to allow unaligned accesses. 1064 */ 1065 hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM), 1066 MBOX_SIZE); 1067 if (!hwbase) { 1068 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1069 err = -ENOMEM; 1070 goto exit; 1071 } 1072 1073 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1074 MBOX_DIR_PFAF, 1); 1075 if (err) 1076 goto exit; 1077 1078 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1079 MBOX_DIR_PFAF_UP, 1); 1080 if (err) 1081 goto exit; 1082 1083 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1084 if (err) 1085 goto exit; 1086 1087 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1088 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1089 mutex_init(&mbox->lock); 1090 1091 return 0; 1092 exit: 1093 otx2_pfaf_mbox_destroy(pf); 1094 return err; 1095 } 1096 1097 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1098 { 1099 struct msg_req *msg; 1100 int err; 1101 1102 mutex_lock(&pf->mbox.lock); 1103 if (enable) 1104 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1105 else 1106 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1107 1108 if (!msg) { 1109 mutex_unlock(&pf->mbox.lock); 1110 return -ENOMEM; 1111 } 1112 1113 err = otx2_sync_mbox_msg(&pf->mbox); 1114 mutex_unlock(&pf->mbox.lock); 1115 return err; 1116 } 1117 1118 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1119 { 1120 struct msg_req *msg; 1121 int err; 1122 1123 if (enable && bitmap_weight(&pf->flow_cfg->dmacflt_bmap, 1124 pf->flow_cfg->dmacflt_max_flows)) 1125 netdev_warn(pf->netdev, 1126 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1127 1128 mutex_lock(&pf->mbox.lock); 1129 if (enable) 1130 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1131 else 1132 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1133 1134 if (!msg) { 1135 mutex_unlock(&pf->mbox.lock); 1136 return -ENOMEM; 1137 } 1138 1139 err = otx2_sync_mbox_msg(&pf->mbox); 1140 mutex_unlock(&pf->mbox.lock); 1141 return err; 1142 } 1143 1144 int otx2_set_real_num_queues(struct net_device *netdev, 1145 int tx_queues, int rx_queues) 1146 { 1147 int err; 1148 1149 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1150 if (err) { 1151 netdev_err(netdev, 1152 "Failed to set no of Tx queues: %d\n", tx_queues); 1153 return err; 1154 } 1155 1156 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1157 if (err) 1158 netdev_err(netdev, 1159 "Failed to set no of Rx queues: %d\n", rx_queues); 1160 return err; 1161 } 1162 EXPORT_SYMBOL(otx2_set_real_num_queues); 1163 1164 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1165 { 1166 struct otx2_nic *pf = data; 1167 u64 val, *ptr; 1168 u64 qidx = 0; 1169 1170 /* CQ */ 1171 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1172 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1173 val = otx2_atomic64_add((qidx << 44), ptr); 1174 1175 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1176 (val & NIX_CQERRINT_BITS)); 1177 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1178 continue; 1179 1180 if (val & BIT_ULL(42)) { 1181 netdev_err(pf->netdev, "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1182 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1183 } else { 1184 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1185 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1186 qidx); 1187 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1188 netdev_err(pf->netdev, "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1189 qidx); 1190 } 1191 1192 schedule_work(&pf->reset_task); 1193 } 1194 1195 /* SQ */ 1196 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1197 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1198 val = otx2_atomic64_add((qidx << 44), ptr); 1199 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1200 (val & NIX_SQINT_BITS)); 1201 1202 if (!(val & (NIX_SQINT_BITS | BIT_ULL(42)))) 1203 continue; 1204 1205 if (val & BIT_ULL(42)) { 1206 netdev_err(pf->netdev, "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1207 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1208 } else { 1209 if (val & BIT_ULL(NIX_SQINT_LMT_ERR)) { 1210 netdev_err(pf->netdev, "SQ%lld: LMT store error NIX_LF_SQ_OP_ERR_DBG:0x%llx", 1211 qidx, 1212 otx2_read64(pf, 1213 NIX_LF_SQ_OP_ERR_DBG)); 1214 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, 1215 BIT_ULL(44)); 1216 } 1217 if (val & BIT_ULL(NIX_SQINT_MNQ_ERR)) { 1218 netdev_err(pf->netdev, "SQ%lld: Meta-descriptor enqueue error NIX_LF_MNQ_ERR_DGB:0x%llx\n", 1219 qidx, 1220 otx2_read64(pf, NIX_LF_MNQ_ERR_DBG)); 1221 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, 1222 BIT_ULL(44)); 1223 } 1224 if (val & BIT_ULL(NIX_SQINT_SEND_ERR)) { 1225 netdev_err(pf->netdev, "SQ%lld: Send error, NIX_LF_SEND_ERR_DBG 0x%llx", 1226 qidx, 1227 otx2_read64(pf, 1228 NIX_LF_SEND_ERR_DBG)); 1229 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, 1230 BIT_ULL(44)); 1231 } 1232 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1233 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1234 qidx); 1235 } 1236 1237 schedule_work(&pf->reset_task); 1238 } 1239 1240 return IRQ_HANDLED; 1241 } 1242 1243 static irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1244 { 1245 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1246 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1247 int qidx = cq_poll->cint_idx; 1248 1249 /* Disable interrupts. 1250 * 1251 * Completion interrupts behave in a level-triggered interrupt 1252 * fashion, and hence have to be cleared only after it is serviced. 1253 */ 1254 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1255 1256 /* Schedule NAPI */ 1257 napi_schedule_irqoff(&cq_poll->napi); 1258 1259 return IRQ_HANDLED; 1260 } 1261 1262 static void otx2_disable_napi(struct otx2_nic *pf) 1263 { 1264 struct otx2_qset *qset = &pf->qset; 1265 struct otx2_cq_poll *cq_poll; 1266 int qidx; 1267 1268 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1269 cq_poll = &qset->napi[qidx]; 1270 napi_disable(&cq_poll->napi); 1271 netif_napi_del(&cq_poll->napi); 1272 } 1273 } 1274 1275 static void otx2_free_cq_res(struct otx2_nic *pf) 1276 { 1277 struct otx2_qset *qset = &pf->qset; 1278 struct otx2_cq_queue *cq; 1279 int qidx; 1280 1281 /* Disable CQs */ 1282 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1283 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1284 cq = &qset->cq[qidx]; 1285 qmem_free(pf->dev, cq->cqe); 1286 } 1287 } 1288 1289 static void otx2_free_sq_res(struct otx2_nic *pf) 1290 { 1291 struct otx2_qset *qset = &pf->qset; 1292 struct otx2_snd_queue *sq; 1293 int qidx; 1294 1295 /* Disable SQs */ 1296 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1297 /* Free SQB pointers */ 1298 otx2_sq_free_sqbs(pf); 1299 for (qidx = 0; qidx < pf->hw.tot_tx_queues; qidx++) { 1300 sq = &qset->sq[qidx]; 1301 qmem_free(pf->dev, sq->sqe); 1302 qmem_free(pf->dev, sq->tso_hdrs); 1303 kfree(sq->sg); 1304 kfree(sq->sqb_ptrs); 1305 } 1306 } 1307 1308 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1309 { 1310 int frame_size; 1311 int total_size; 1312 int rbuf_size; 1313 1314 if (pf->hw.rbuf_len) 1315 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1316 1317 /* The data transferred by NIX to memory consists of actual packet 1318 * plus additional data which has timestamp and/or EDSA/HIGIG2 1319 * headers if interface is configured in corresponding modes. 1320 * NIX transfers entire data using 6 segments/buffers and writes 1321 * a CQE_RX descriptor with those segment addresses. First segment 1322 * has additional data prepended to packet. Also software omits a 1323 * headroom of 128 bytes in each segment. Hence the total size of 1324 * memory needed to receive a packet with 'mtu' is: 1325 * frame size = mtu + additional data; 1326 * memory = frame_size + headroom * 6; 1327 * each receive buffer size = memory / 6; 1328 */ 1329 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1330 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1331 rbuf_size = total_size / 6; 1332 1333 return ALIGN(rbuf_size, 2048); 1334 } 1335 1336 static int otx2_init_hw_resources(struct otx2_nic *pf) 1337 { 1338 struct nix_lf_free_req *free_req; 1339 struct mbox *mbox = &pf->mbox; 1340 struct otx2_hw *hw = &pf->hw; 1341 struct msg_req *req; 1342 int err = 0, lvl; 1343 1344 /* Set required NPA LF's pool counts 1345 * Auras and Pools are used in a 1:1 mapping, 1346 * so, aura count = pool count. 1347 */ 1348 hw->rqpool_cnt = hw->rx_queues; 1349 hw->sqpool_cnt = hw->tot_tx_queues; 1350 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1351 1352 /* Maximum hardware supported transmit length */ 1353 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1354 1355 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1356 1357 mutex_lock(&mbox->lock); 1358 /* NPA init */ 1359 err = otx2_config_npa(pf); 1360 if (err) 1361 goto exit; 1362 1363 /* NIX init */ 1364 err = otx2_config_nix(pf); 1365 if (err) 1366 goto err_free_npa_lf; 1367 1368 /* Enable backpressure */ 1369 otx2_nix_config_bp(pf, true); 1370 1371 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1372 err = otx2_rq_aura_pool_init(pf); 1373 if (err) { 1374 mutex_unlock(&mbox->lock); 1375 goto err_free_nix_lf; 1376 } 1377 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1378 err = otx2_sq_aura_pool_init(pf); 1379 if (err) { 1380 mutex_unlock(&mbox->lock); 1381 goto err_free_rq_ptrs; 1382 } 1383 1384 err = otx2_txsch_alloc(pf); 1385 if (err) { 1386 mutex_unlock(&mbox->lock); 1387 goto err_free_sq_ptrs; 1388 } 1389 1390 err = otx2_config_nix_queues(pf); 1391 if (err) { 1392 mutex_unlock(&mbox->lock); 1393 goto err_free_txsch; 1394 } 1395 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1396 err = otx2_txschq_config(pf, lvl); 1397 if (err) { 1398 mutex_unlock(&mbox->lock); 1399 goto err_free_nix_queues; 1400 } 1401 } 1402 mutex_unlock(&mbox->lock); 1403 return err; 1404 1405 err_free_nix_queues: 1406 otx2_free_sq_res(pf); 1407 otx2_free_cq_res(pf); 1408 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1409 err_free_txsch: 1410 if (otx2_txschq_stop(pf)) 1411 dev_err(pf->dev, "%s failed to stop TX schedulers\n", __func__); 1412 err_free_sq_ptrs: 1413 otx2_sq_free_sqbs(pf); 1414 err_free_rq_ptrs: 1415 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1416 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1417 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1418 otx2_aura_pool_free(pf); 1419 err_free_nix_lf: 1420 mutex_lock(&mbox->lock); 1421 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1422 if (free_req) { 1423 free_req->flags = NIX_LF_DISABLE_FLOWS; 1424 if (otx2_sync_mbox_msg(mbox)) 1425 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1426 } 1427 err_free_npa_lf: 1428 /* Reset NPA LF */ 1429 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1430 if (req) { 1431 if (otx2_sync_mbox_msg(mbox)) 1432 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1433 } 1434 exit: 1435 mutex_unlock(&mbox->lock); 1436 return err; 1437 } 1438 1439 static void otx2_free_hw_resources(struct otx2_nic *pf) 1440 { 1441 struct otx2_qset *qset = &pf->qset; 1442 struct nix_lf_free_req *free_req; 1443 struct mbox *mbox = &pf->mbox; 1444 struct otx2_cq_queue *cq; 1445 struct msg_req *req; 1446 int qidx, err; 1447 1448 /* Ensure all SQE are processed */ 1449 otx2_sqb_flush(pf); 1450 1451 /* Stop transmission */ 1452 err = otx2_txschq_stop(pf); 1453 if (err) 1454 dev_err(pf->dev, "RVUPF: Failed to stop/free TX schedulers\n"); 1455 1456 mutex_lock(&mbox->lock); 1457 /* Disable backpressure */ 1458 if (!(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1459 otx2_nix_config_bp(pf, false); 1460 mutex_unlock(&mbox->lock); 1461 1462 /* Disable RQs */ 1463 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1464 1465 /*Dequeue all CQEs */ 1466 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1467 cq = &qset->cq[qidx]; 1468 if (cq->cq_type == CQ_RX) 1469 otx2_cleanup_rx_cqes(pf, cq); 1470 else 1471 otx2_cleanup_tx_cqes(pf, cq); 1472 } 1473 1474 otx2_free_sq_res(pf); 1475 1476 /* Free RQ buffer pointers*/ 1477 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1478 1479 otx2_free_cq_res(pf); 1480 1481 /* Free all ingress bandwidth profiles allocated */ 1482 cn10k_free_all_ipolicers(pf); 1483 1484 mutex_lock(&mbox->lock); 1485 /* Reset NIX LF */ 1486 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1487 if (free_req) { 1488 free_req->flags = NIX_LF_DISABLE_FLOWS; 1489 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1490 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1491 if (otx2_sync_mbox_msg(mbox)) 1492 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1493 } 1494 mutex_unlock(&mbox->lock); 1495 1496 /* Disable NPA Pool and Aura hw context */ 1497 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1498 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1499 otx2_aura_pool_free(pf); 1500 1501 mutex_lock(&mbox->lock); 1502 /* Reset NPA LF */ 1503 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1504 if (req) { 1505 if (otx2_sync_mbox_msg(mbox)) 1506 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1507 } 1508 mutex_unlock(&mbox->lock); 1509 } 1510 1511 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1512 { 1513 struct net_device *netdev = pf->netdev; 1514 struct nix_rx_mode *req; 1515 bool promisc = false; 1516 1517 if (!(netdev->flags & IFF_UP)) 1518 return; 1519 1520 if ((netdev->flags & IFF_PROMISC) || 1521 (netdev_uc_count(netdev) > OTX2_MAX_UNICAST_FLOWS)) { 1522 promisc = true; 1523 } 1524 1525 /* Write unicast address to mcam entries or del from mcam */ 1526 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1527 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1528 1529 mutex_lock(&pf->mbox.lock); 1530 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1531 if (!req) { 1532 mutex_unlock(&pf->mbox.lock); 1533 return; 1534 } 1535 1536 req->mode = NIX_RX_MODE_UCAST; 1537 1538 if (promisc) 1539 req->mode |= NIX_RX_MODE_PROMISC; 1540 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1541 req->mode |= NIX_RX_MODE_ALLMULTI; 1542 1543 req->mode |= NIX_RX_MODE_USE_MCE; 1544 1545 otx2_sync_mbox_msg(&pf->mbox); 1546 mutex_unlock(&pf->mbox.lock); 1547 } 1548 1549 int otx2_open(struct net_device *netdev) 1550 { 1551 struct otx2_nic *pf = netdev_priv(netdev); 1552 struct otx2_cq_poll *cq_poll = NULL; 1553 struct otx2_qset *qset = &pf->qset; 1554 int err = 0, qidx, vec; 1555 char *irq_name; 1556 1557 netif_carrier_off(netdev); 1558 1559 pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tot_tx_queues; 1560 /* RQ and SQs are mapped to different CQs, 1561 * so find out max CQ IRQs (i.e CINTs) needed. 1562 */ 1563 pf->hw.cint_cnt = max(pf->hw.rx_queues, pf->hw.tx_queues); 1564 qset->napi = kcalloc(pf->hw.cint_cnt, sizeof(*cq_poll), GFP_KERNEL); 1565 if (!qset->napi) 1566 return -ENOMEM; 1567 1568 /* CQ size of RQ */ 1569 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1570 /* CQ size of SQ */ 1571 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1572 1573 err = -ENOMEM; 1574 qset->cq = kcalloc(pf->qset.cq_cnt, 1575 sizeof(struct otx2_cq_queue), GFP_KERNEL); 1576 if (!qset->cq) 1577 goto err_free_mem; 1578 1579 qset->sq = kcalloc(pf->hw.tot_tx_queues, 1580 sizeof(struct otx2_snd_queue), GFP_KERNEL); 1581 if (!qset->sq) 1582 goto err_free_mem; 1583 1584 qset->rq = kcalloc(pf->hw.rx_queues, 1585 sizeof(struct otx2_rcv_queue), GFP_KERNEL); 1586 if (!qset->rq) 1587 goto err_free_mem; 1588 1589 err = otx2_init_hw_resources(pf); 1590 if (err) 1591 goto err_free_mem; 1592 1593 /* Register NAPI handler */ 1594 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1595 cq_poll = &qset->napi[qidx]; 1596 cq_poll->cint_idx = qidx; 1597 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 1598 * 'cq_ids[0]' points to RQ's CQ and 1599 * 'cq_ids[1]' points to SQ's CQ and 1600 * 'cq_ids[2]' points to XDP's CQ and 1601 */ 1602 cq_poll->cq_ids[CQ_RX] = 1603 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 1604 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 1605 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 1606 if (pf->xdp_prog) 1607 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 1608 (qidx + pf->hw.rx_queues + 1609 pf->hw.tx_queues) : 1610 CINT_INVALID_CQ; 1611 else 1612 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 1613 1614 cq_poll->dev = (void *)pf; 1615 netif_napi_add(netdev, &cq_poll->napi, 1616 otx2_napi_handler, NAPI_POLL_WEIGHT); 1617 napi_enable(&cq_poll->napi); 1618 } 1619 1620 /* Set maximum frame size allowed in HW */ 1621 err = otx2_hw_set_mtu(pf, netdev->mtu); 1622 if (err) 1623 goto err_disable_napi; 1624 1625 /* Setup segmentation algorithms, if failed, clear offload capability */ 1626 otx2_setup_segmentation(pf); 1627 1628 /* Initialize RSS */ 1629 err = otx2_rss_init(pf); 1630 if (err) 1631 goto err_disable_napi; 1632 1633 /* Register Queue IRQ handlers */ 1634 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 1635 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1636 1637 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 1638 1639 err = request_irq(pci_irq_vector(pf->pdev, vec), 1640 otx2_q_intr_handler, 0, irq_name, pf); 1641 if (err) { 1642 dev_err(pf->dev, 1643 "RVUPF%d: IRQ registration failed for QERR\n", 1644 rvu_get_pf(pf->pcifunc)); 1645 goto err_disable_napi; 1646 } 1647 1648 /* Enable QINT IRQ */ 1649 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 1650 1651 /* Register CQ IRQ handlers */ 1652 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1653 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1654 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 1655 1656 snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", pf->netdev->name, 1657 qidx); 1658 1659 err = request_irq(pci_irq_vector(pf->pdev, vec), 1660 otx2_cq_intr_handler, 0, irq_name, 1661 &qset->napi[qidx]); 1662 if (err) { 1663 dev_err(pf->dev, 1664 "RVUPF%d: IRQ registration failed for CQ%d\n", 1665 rvu_get_pf(pf->pcifunc), qidx); 1666 goto err_free_cints; 1667 } 1668 vec++; 1669 1670 otx2_config_irq_coalescing(pf, qidx); 1671 1672 /* Enable CQ IRQ */ 1673 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 1674 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 1675 } 1676 1677 otx2_set_cints_affinity(pf); 1678 1679 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 1680 otx2_enable_rxvlan(pf, true); 1681 1682 /* When reinitializing enable time stamping if it is enabled before */ 1683 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 1684 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1685 otx2_config_hw_tx_tstamp(pf, true); 1686 } 1687 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 1688 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1689 otx2_config_hw_rx_tstamp(pf, true); 1690 } 1691 1692 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 1693 /* 'intf_down' may be checked on any cpu */ 1694 smp_wmb(); 1695 1696 /* we have already received link status notification */ 1697 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 1698 otx2_handle_link_event(pf); 1699 1700 /* Install DMAC Filters */ 1701 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 1702 otx2_dmacflt_reinstall_flows(pf); 1703 1704 err = otx2_rxtx_enable(pf, true); 1705 if (err) 1706 goto err_tx_stop_queues; 1707 1708 otx2_do_set_rx_mode(pf); 1709 1710 return 0; 1711 1712 err_tx_stop_queues: 1713 netif_tx_stop_all_queues(netdev); 1714 netif_carrier_off(netdev); 1715 pf->flags |= OTX2_FLAG_INTF_DOWN; 1716 err_free_cints: 1717 otx2_free_cints(pf, qidx); 1718 vec = pci_irq_vector(pf->pdev, 1719 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1720 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1721 synchronize_irq(vec); 1722 free_irq(vec, pf); 1723 err_disable_napi: 1724 otx2_disable_napi(pf); 1725 otx2_free_hw_resources(pf); 1726 err_free_mem: 1727 kfree(qset->sq); 1728 kfree(qset->cq); 1729 kfree(qset->rq); 1730 kfree(qset->napi); 1731 return err; 1732 } 1733 EXPORT_SYMBOL(otx2_open); 1734 1735 int otx2_stop(struct net_device *netdev) 1736 { 1737 struct otx2_nic *pf = netdev_priv(netdev); 1738 struct otx2_cq_poll *cq_poll = NULL; 1739 struct otx2_qset *qset = &pf->qset; 1740 struct otx2_rss_info *rss; 1741 int qidx, vec, wrk; 1742 1743 /* If the DOWN flag is set resources are already freed */ 1744 if (pf->flags & OTX2_FLAG_INTF_DOWN) 1745 return 0; 1746 1747 netif_carrier_off(netdev); 1748 netif_tx_stop_all_queues(netdev); 1749 1750 pf->flags |= OTX2_FLAG_INTF_DOWN; 1751 /* 'intf_down' may be checked on any cpu */ 1752 smp_wmb(); 1753 1754 /* First stop packet Rx/Tx */ 1755 otx2_rxtx_enable(pf, false); 1756 1757 /* Clear RSS enable flag */ 1758 rss = &pf->hw.rss_info; 1759 rss->enable = false; 1760 1761 /* Cleanup Queue IRQ */ 1762 vec = pci_irq_vector(pf->pdev, 1763 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 1764 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 1765 synchronize_irq(vec); 1766 free_irq(vec, pf); 1767 1768 /* Cleanup CQ NAPI and IRQ */ 1769 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 1770 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1771 /* Disable interrupt */ 1772 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1773 1774 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 1775 1776 cq_poll = &qset->napi[qidx]; 1777 napi_synchronize(&cq_poll->napi); 1778 vec++; 1779 } 1780 1781 netif_tx_disable(netdev); 1782 1783 otx2_free_hw_resources(pf); 1784 otx2_free_cints(pf, pf->hw.cint_cnt); 1785 otx2_disable_napi(pf); 1786 1787 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 1788 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 1789 1790 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 1791 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 1792 devm_kfree(pf->dev, pf->refill_wrk); 1793 1794 kfree(qset->sq); 1795 kfree(qset->cq); 1796 kfree(qset->rq); 1797 kfree(qset->napi); 1798 /* Do not clear RQ/SQ ringsize settings */ 1799 memset((void *)qset + offsetof(struct otx2_qset, sqe_cnt), 0, 1800 sizeof(*qset) - offsetof(struct otx2_qset, sqe_cnt)); 1801 return 0; 1802 } 1803 EXPORT_SYMBOL(otx2_stop); 1804 1805 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 1806 { 1807 struct otx2_nic *pf = netdev_priv(netdev); 1808 int qidx = skb_get_queue_mapping(skb); 1809 struct otx2_snd_queue *sq; 1810 struct netdev_queue *txq; 1811 1812 /* Check for minimum and maximum packet length */ 1813 if (skb->len <= ETH_HLEN || 1814 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 1815 dev_kfree_skb(skb); 1816 return NETDEV_TX_OK; 1817 } 1818 1819 sq = &pf->qset.sq[qidx]; 1820 txq = netdev_get_tx_queue(netdev, qidx); 1821 1822 if (!otx2_sq_append_skb(netdev, sq, skb, qidx)) { 1823 netif_tx_stop_queue(txq); 1824 1825 /* Check again, incase SQBs got freed up */ 1826 smp_mb(); 1827 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 1828 > sq->sqe_thresh) 1829 netif_tx_wake_queue(txq); 1830 1831 return NETDEV_TX_BUSY; 1832 } 1833 1834 return NETDEV_TX_OK; 1835 } 1836 1837 static netdev_features_t otx2_fix_features(struct net_device *dev, 1838 netdev_features_t features) 1839 { 1840 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1841 features |= NETIF_F_HW_VLAN_STAG_RX; 1842 else 1843 features &= ~NETIF_F_HW_VLAN_STAG_RX; 1844 1845 return features; 1846 } 1847 1848 static void otx2_set_rx_mode(struct net_device *netdev) 1849 { 1850 struct otx2_nic *pf = netdev_priv(netdev); 1851 1852 queue_work(pf->otx2_wq, &pf->rx_mode_work); 1853 } 1854 1855 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 1856 { 1857 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 1858 1859 otx2_do_set_rx_mode(pf); 1860 } 1861 1862 static int otx2_set_features(struct net_device *netdev, 1863 netdev_features_t features) 1864 { 1865 netdev_features_t changed = features ^ netdev->features; 1866 struct otx2_nic *pf = netdev_priv(netdev); 1867 1868 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 1869 return otx2_cgx_config_loopback(pf, 1870 features & NETIF_F_LOOPBACK); 1871 1872 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 1873 return otx2_enable_rxvlan(pf, 1874 features & NETIF_F_HW_VLAN_CTAG_RX); 1875 1876 return otx2_handle_ntuple_tc_features(netdev, features); 1877 } 1878 1879 static void otx2_reset_task(struct work_struct *work) 1880 { 1881 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 1882 1883 if (!netif_running(pf->netdev)) 1884 return; 1885 1886 rtnl_lock(); 1887 otx2_stop(pf->netdev); 1888 pf->reset_count++; 1889 otx2_open(pf->netdev); 1890 netif_trans_update(pf->netdev); 1891 rtnl_unlock(); 1892 } 1893 1894 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 1895 { 1896 struct msg_req *req; 1897 int err; 1898 1899 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 1900 return 0; 1901 1902 mutex_lock(&pfvf->mbox.lock); 1903 if (enable) 1904 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 1905 else 1906 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 1907 if (!req) { 1908 mutex_unlock(&pfvf->mbox.lock); 1909 return -ENOMEM; 1910 } 1911 1912 err = otx2_sync_mbox_msg(&pfvf->mbox); 1913 if (err) { 1914 mutex_unlock(&pfvf->mbox.lock); 1915 return err; 1916 } 1917 1918 mutex_unlock(&pfvf->mbox.lock); 1919 if (enable) 1920 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 1921 else 1922 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 1923 return 0; 1924 } 1925 1926 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 1927 { 1928 struct msg_req *req; 1929 int err; 1930 1931 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 1932 return 0; 1933 1934 mutex_lock(&pfvf->mbox.lock); 1935 if (enable) 1936 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 1937 else 1938 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 1939 if (!req) { 1940 mutex_unlock(&pfvf->mbox.lock); 1941 return -ENOMEM; 1942 } 1943 1944 err = otx2_sync_mbox_msg(&pfvf->mbox); 1945 if (err) { 1946 mutex_unlock(&pfvf->mbox.lock); 1947 return err; 1948 } 1949 1950 mutex_unlock(&pfvf->mbox.lock); 1951 if (enable) 1952 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 1953 else 1954 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 1955 return 0; 1956 } 1957 1958 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr) 1959 { 1960 struct otx2_nic *pfvf = netdev_priv(netdev); 1961 struct hwtstamp_config config; 1962 1963 if (!pfvf->ptp) 1964 return -ENODEV; 1965 1966 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1967 return -EFAULT; 1968 1969 switch (config.tx_type) { 1970 case HWTSTAMP_TX_OFF: 1971 otx2_config_hw_tx_tstamp(pfvf, false); 1972 break; 1973 case HWTSTAMP_TX_ON: 1974 otx2_config_hw_tx_tstamp(pfvf, true); 1975 break; 1976 default: 1977 return -ERANGE; 1978 } 1979 1980 switch (config.rx_filter) { 1981 case HWTSTAMP_FILTER_NONE: 1982 otx2_config_hw_rx_tstamp(pfvf, false); 1983 break; 1984 case HWTSTAMP_FILTER_ALL: 1985 case HWTSTAMP_FILTER_SOME: 1986 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1987 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1988 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1989 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1990 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1991 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1992 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1993 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1994 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1995 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1996 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1997 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1998 otx2_config_hw_rx_tstamp(pfvf, true); 1999 config.rx_filter = HWTSTAMP_FILTER_ALL; 2000 break; 2001 default: 2002 return -ERANGE; 2003 } 2004 2005 memcpy(&pfvf->tstamp, &config, sizeof(config)); 2006 2007 return copy_to_user(ifr->ifr_data, &config, 2008 sizeof(config)) ? -EFAULT : 0; 2009 } 2010 EXPORT_SYMBOL(otx2_config_hwtstamp); 2011 2012 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) 2013 { 2014 struct otx2_nic *pfvf = netdev_priv(netdev); 2015 struct hwtstamp_config *cfg = &pfvf->tstamp; 2016 2017 switch (cmd) { 2018 case SIOCSHWTSTAMP: 2019 return otx2_config_hwtstamp(netdev, req); 2020 case SIOCGHWTSTAMP: 2021 return copy_to_user(req->ifr_data, cfg, 2022 sizeof(*cfg)) ? -EFAULT : 0; 2023 default: 2024 return -EOPNOTSUPP; 2025 } 2026 } 2027 EXPORT_SYMBOL(otx2_ioctl); 2028 2029 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2030 { 2031 struct npc_install_flow_req *req; 2032 int err; 2033 2034 mutex_lock(&pf->mbox.lock); 2035 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2036 if (!req) { 2037 err = -ENOMEM; 2038 goto out; 2039 } 2040 2041 ether_addr_copy(req->packet.dmac, mac); 2042 eth_broadcast_addr((u8 *)&req->mask.dmac); 2043 req->features = BIT_ULL(NPC_DMAC); 2044 req->channel = pf->hw.rx_chan_base; 2045 req->intf = NIX_INTF_RX; 2046 req->default_rule = 1; 2047 req->append = 1; 2048 req->vf = vf + 1; 2049 req->op = NIX_RX_ACTION_DEFAULT; 2050 2051 err = otx2_sync_mbox_msg(&pf->mbox); 2052 out: 2053 mutex_unlock(&pf->mbox.lock); 2054 return err; 2055 } 2056 2057 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2058 { 2059 struct otx2_nic *pf = netdev_priv(netdev); 2060 struct pci_dev *pdev = pf->pdev; 2061 struct otx2_vf_config *config; 2062 int ret; 2063 2064 if (!netif_running(netdev)) 2065 return -EAGAIN; 2066 2067 if (vf >= pf->total_vfs) 2068 return -EINVAL; 2069 2070 if (!is_valid_ether_addr(mac)) 2071 return -EINVAL; 2072 2073 config = &pf->vf_configs[vf]; 2074 ether_addr_copy(config->mac, mac); 2075 2076 ret = otx2_do_set_vf_mac(pf, vf, mac); 2077 if (ret == 0) 2078 dev_info(&pdev->dev, 2079 "Load/Reload VF driver\n"); 2080 2081 return ret; 2082 } 2083 2084 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2085 __be16 proto) 2086 { 2087 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2088 struct nix_vtag_config_rsp *vtag_rsp; 2089 struct npc_delete_flow_req *del_req; 2090 struct nix_vtag_config *vtag_req; 2091 struct npc_install_flow_req *req; 2092 struct otx2_vf_config *config; 2093 int err = 0; 2094 u32 idx; 2095 2096 config = &pf->vf_configs[vf]; 2097 2098 if (!vlan && !config->vlan) 2099 goto out; 2100 2101 mutex_lock(&pf->mbox.lock); 2102 2103 /* free old tx vtag entry */ 2104 if (config->vlan) { 2105 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2106 if (!vtag_req) { 2107 err = -ENOMEM; 2108 goto out; 2109 } 2110 vtag_req->cfg_type = 0; 2111 vtag_req->tx.free_vtag0 = 1; 2112 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2113 2114 err = otx2_sync_mbox_msg(&pf->mbox); 2115 if (err) 2116 goto out; 2117 } 2118 2119 if (!vlan && config->vlan) { 2120 /* rx */ 2121 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2122 if (!del_req) { 2123 err = -ENOMEM; 2124 goto out; 2125 } 2126 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2127 del_req->entry = 2128 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2129 err = otx2_sync_mbox_msg(&pf->mbox); 2130 if (err) 2131 goto out; 2132 2133 /* tx */ 2134 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2135 if (!del_req) { 2136 err = -ENOMEM; 2137 goto out; 2138 } 2139 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2140 del_req->entry = 2141 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2142 err = otx2_sync_mbox_msg(&pf->mbox); 2143 2144 goto out; 2145 } 2146 2147 /* rx */ 2148 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2149 if (!req) { 2150 err = -ENOMEM; 2151 goto out; 2152 } 2153 2154 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2155 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2156 req->packet.vlan_tci = htons(vlan); 2157 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2158 /* af fills the destination mac addr */ 2159 eth_broadcast_addr((u8 *)&req->mask.dmac); 2160 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2161 req->channel = pf->hw.rx_chan_base; 2162 req->intf = NIX_INTF_RX; 2163 req->vf = vf + 1; 2164 req->op = NIX_RX_ACTION_DEFAULT; 2165 req->vtag0_valid = true; 2166 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2167 req->set_cntr = 1; 2168 2169 err = otx2_sync_mbox_msg(&pf->mbox); 2170 if (err) 2171 goto out; 2172 2173 /* tx */ 2174 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2175 if (!vtag_req) { 2176 err = -ENOMEM; 2177 goto out; 2178 } 2179 2180 /* configure tx vtag params */ 2181 vtag_req->vtag_size = VTAGSIZE_T4; 2182 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2183 vtag_req->tx.cfg_vtag0 = 1; 2184 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2185 2186 err = otx2_sync_mbox_msg(&pf->mbox); 2187 if (err) 2188 goto out; 2189 2190 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2191 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2192 if (IS_ERR(vtag_rsp)) { 2193 err = PTR_ERR(vtag_rsp); 2194 goto out; 2195 } 2196 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2197 2198 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2199 if (!req) { 2200 err = -ENOMEM; 2201 goto out; 2202 } 2203 2204 eth_zero_addr((u8 *)&req->mask.dmac); 2205 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2206 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2207 req->features = BIT_ULL(NPC_DMAC); 2208 req->channel = pf->hw.tx_chan_base; 2209 req->intf = NIX_INTF_TX; 2210 req->vf = vf + 1; 2211 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2212 req->vtag0_def = vtag_rsp->vtag0_idx; 2213 req->vtag0_op = VTAG_INSERT; 2214 req->set_cntr = 1; 2215 2216 err = otx2_sync_mbox_msg(&pf->mbox); 2217 out: 2218 config->vlan = vlan; 2219 mutex_unlock(&pf->mbox.lock); 2220 return err; 2221 } 2222 2223 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2224 __be16 proto) 2225 { 2226 struct otx2_nic *pf = netdev_priv(netdev); 2227 struct pci_dev *pdev = pf->pdev; 2228 2229 if (!netif_running(netdev)) 2230 return -EAGAIN; 2231 2232 if (vf >= pci_num_vf(pdev)) 2233 return -EINVAL; 2234 2235 /* qos is currently unsupported */ 2236 if (vlan >= VLAN_N_VID || qos) 2237 return -EINVAL; 2238 2239 if (proto != htons(ETH_P_8021Q)) 2240 return -EPROTONOSUPPORT; 2241 2242 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2243 return -EOPNOTSUPP; 2244 2245 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2246 } 2247 2248 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2249 struct ifla_vf_info *ivi) 2250 { 2251 struct otx2_nic *pf = netdev_priv(netdev); 2252 struct pci_dev *pdev = pf->pdev; 2253 struct otx2_vf_config *config; 2254 2255 if (!netif_running(netdev)) 2256 return -EAGAIN; 2257 2258 if (vf >= pci_num_vf(pdev)) 2259 return -EINVAL; 2260 2261 config = &pf->vf_configs[vf]; 2262 ivi->vf = vf; 2263 ether_addr_copy(ivi->mac, config->mac); 2264 ivi->vlan = config->vlan; 2265 ivi->trusted = config->trusted; 2266 2267 return 0; 2268 } 2269 2270 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2271 int qidx) 2272 { 2273 struct page *page; 2274 u64 dma_addr; 2275 int err = 0; 2276 2277 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2278 offset_in_page(xdpf->data), xdpf->len, 2279 DMA_TO_DEVICE); 2280 if (dma_mapping_error(pf->dev, dma_addr)) 2281 return -ENOMEM; 2282 2283 err = otx2_xdp_sq_append_pkt(pf, dma_addr, xdpf->len, qidx); 2284 if (!err) { 2285 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2286 page = virt_to_page(xdpf->data); 2287 put_page(page); 2288 return -ENOMEM; 2289 } 2290 return 0; 2291 } 2292 2293 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2294 struct xdp_frame **frames, u32 flags) 2295 { 2296 struct otx2_nic *pf = netdev_priv(netdev); 2297 int qidx = smp_processor_id(); 2298 struct otx2_snd_queue *sq; 2299 int drops = 0, i; 2300 2301 if (!netif_running(netdev)) 2302 return -ENETDOWN; 2303 2304 qidx += pf->hw.tx_queues; 2305 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2306 2307 /* Abort xmit if xdp queue is not */ 2308 if (unlikely(!sq)) 2309 return -ENXIO; 2310 2311 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2312 return -EINVAL; 2313 2314 for (i = 0; i < n; i++) { 2315 struct xdp_frame *xdpf = frames[i]; 2316 int err; 2317 2318 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2319 if (err) 2320 drops++; 2321 } 2322 return n - drops; 2323 } 2324 2325 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2326 { 2327 struct net_device *dev = pf->netdev; 2328 bool if_up = netif_running(pf->netdev); 2329 struct bpf_prog *old_prog; 2330 2331 if (prog && dev->mtu > MAX_XDP_MTU) { 2332 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2333 return -EOPNOTSUPP; 2334 } 2335 2336 if (if_up) 2337 otx2_stop(pf->netdev); 2338 2339 old_prog = xchg(&pf->xdp_prog, prog); 2340 2341 if (old_prog) 2342 bpf_prog_put(old_prog); 2343 2344 if (pf->xdp_prog) 2345 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2346 2347 /* Network stack and XDP shared same rx queues. 2348 * Use separate tx queues for XDP and network stack. 2349 */ 2350 if (pf->xdp_prog) 2351 pf->hw.xdp_queues = pf->hw.rx_queues; 2352 else 2353 pf->hw.xdp_queues = 0; 2354 2355 pf->hw.tot_tx_queues += pf->hw.xdp_queues; 2356 2357 if (if_up) 2358 otx2_open(pf->netdev); 2359 2360 return 0; 2361 } 2362 2363 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2364 { 2365 struct otx2_nic *pf = netdev_priv(netdev); 2366 2367 switch (xdp->command) { 2368 case XDP_SETUP_PROG: 2369 return otx2_xdp_setup(pf, xdp->prog); 2370 default: 2371 return -EINVAL; 2372 } 2373 } 2374 2375 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2376 int req_perm) 2377 { 2378 struct set_vf_perm *req; 2379 int rc; 2380 2381 mutex_lock(&pf->mbox.lock); 2382 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2383 if (!req) { 2384 rc = -ENOMEM; 2385 goto out; 2386 } 2387 2388 /* Let AF reset VF permissions as sriov is disabled */ 2389 if (req_perm == OTX2_RESET_VF_PERM) { 2390 req->flags |= RESET_VF_PERM; 2391 } else if (req_perm == OTX2_TRUSTED_VF) { 2392 if (pf->vf_configs[vf].trusted) 2393 req->flags |= VF_TRUSTED; 2394 } 2395 2396 req->vf = vf; 2397 rc = otx2_sync_mbox_msg(&pf->mbox); 2398 out: 2399 mutex_unlock(&pf->mbox.lock); 2400 return rc; 2401 } 2402 2403 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 2404 bool enable) 2405 { 2406 struct otx2_nic *pf = netdev_priv(netdev); 2407 struct pci_dev *pdev = pf->pdev; 2408 int rc; 2409 2410 if (vf >= pci_num_vf(pdev)) 2411 return -EINVAL; 2412 2413 if (pf->vf_configs[vf].trusted == enable) 2414 return 0; 2415 2416 pf->vf_configs[vf].trusted = enable; 2417 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 2418 2419 if (rc) 2420 pf->vf_configs[vf].trusted = !enable; 2421 else 2422 netdev_info(pf->netdev, "VF %d is %strusted\n", 2423 vf, enable ? "" : "not "); 2424 return rc; 2425 } 2426 2427 static const struct net_device_ops otx2_netdev_ops = { 2428 .ndo_open = otx2_open, 2429 .ndo_stop = otx2_stop, 2430 .ndo_start_xmit = otx2_xmit, 2431 .ndo_fix_features = otx2_fix_features, 2432 .ndo_set_mac_address = otx2_set_mac_address, 2433 .ndo_change_mtu = otx2_change_mtu, 2434 .ndo_set_rx_mode = otx2_set_rx_mode, 2435 .ndo_set_features = otx2_set_features, 2436 .ndo_tx_timeout = otx2_tx_timeout, 2437 .ndo_get_stats64 = otx2_get_stats64, 2438 .ndo_eth_ioctl = otx2_ioctl, 2439 .ndo_set_vf_mac = otx2_set_vf_mac, 2440 .ndo_set_vf_vlan = otx2_set_vf_vlan, 2441 .ndo_get_vf_config = otx2_get_vf_config, 2442 .ndo_bpf = otx2_xdp, 2443 .ndo_xdp_xmit = otx2_xdp_xmit, 2444 .ndo_setup_tc = otx2_setup_tc, 2445 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 2446 }; 2447 2448 static int otx2_wq_init(struct otx2_nic *pf) 2449 { 2450 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 2451 if (!pf->otx2_wq) 2452 return -ENOMEM; 2453 2454 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 2455 INIT_WORK(&pf->reset_task, otx2_reset_task); 2456 return 0; 2457 } 2458 2459 static int otx2_check_pf_usable(struct otx2_nic *nic) 2460 { 2461 u64 rev; 2462 2463 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 2464 rev = (rev >> 12) & 0xFF; 2465 /* Check if AF has setup revision for RVUM block, 2466 * otherwise this driver probe should be deferred 2467 * until AF driver comes up. 2468 */ 2469 if (!rev) { 2470 dev_warn(nic->dev, 2471 "AF is not initialized, deferring probe\n"); 2472 return -EPROBE_DEFER; 2473 } 2474 return 0; 2475 } 2476 2477 static int otx2_realloc_msix_vectors(struct otx2_nic *pf) 2478 { 2479 struct otx2_hw *hw = &pf->hw; 2480 int num_vec, err; 2481 2482 /* NPA interrupts are inot registered, so alloc only 2483 * upto NIX vector offset. 2484 */ 2485 num_vec = hw->nix_msixoff; 2486 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 2487 2488 otx2_disable_mbox_intr(pf); 2489 pci_free_irq_vectors(hw->pdev); 2490 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 2491 if (err < 0) { 2492 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 2493 __func__, num_vec); 2494 return err; 2495 } 2496 2497 return otx2_register_mbox_intr(pf, false); 2498 } 2499 2500 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 2501 { 2502 int i; 2503 2504 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 2505 sizeof(struct otx2_vf_config), 2506 GFP_KERNEL); 2507 if (!pf->vf_configs) 2508 return -ENOMEM; 2509 2510 for (i = 0; i < pf->total_vfs; i++) { 2511 pf->vf_configs[i].pf = pf; 2512 pf->vf_configs[i].intf_down = true; 2513 pf->vf_configs[i].trusted = false; 2514 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 2515 otx2_vf_link_event_task); 2516 } 2517 2518 return 0; 2519 } 2520 2521 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 2522 { 2523 int i; 2524 2525 if (!pf->vf_configs) 2526 return; 2527 2528 for (i = 0; i < pf->total_vfs; i++) { 2529 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 2530 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 2531 } 2532 } 2533 2534 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2535 { 2536 struct device *dev = &pdev->dev; 2537 struct net_device *netdev; 2538 struct otx2_nic *pf; 2539 struct otx2_hw *hw; 2540 int err, qcount; 2541 int num_vec; 2542 2543 err = pcim_enable_device(pdev); 2544 if (err) { 2545 dev_err(dev, "Failed to enable PCI device\n"); 2546 return err; 2547 } 2548 2549 err = pci_request_regions(pdev, DRV_NAME); 2550 if (err) { 2551 dev_err(dev, "PCI request regions failed 0x%x\n", err); 2552 return err; 2553 } 2554 2555 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2556 if (err) { 2557 dev_err(dev, "DMA mask config failed, abort\n"); 2558 goto err_release_regions; 2559 } 2560 2561 pci_set_master(pdev); 2562 2563 /* Set number of queues */ 2564 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 2565 2566 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount); 2567 if (!netdev) { 2568 err = -ENOMEM; 2569 goto err_release_regions; 2570 } 2571 2572 pci_set_drvdata(pdev, netdev); 2573 SET_NETDEV_DEV(netdev, &pdev->dev); 2574 pf = netdev_priv(netdev); 2575 pf->netdev = netdev; 2576 pf->pdev = pdev; 2577 pf->dev = dev; 2578 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 2579 pf->flags |= OTX2_FLAG_INTF_DOWN; 2580 2581 hw = &pf->hw; 2582 hw->pdev = pdev; 2583 hw->rx_queues = qcount; 2584 hw->tx_queues = qcount; 2585 hw->tot_tx_queues = qcount; 2586 hw->max_queues = qcount; 2587 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 2588 /* Use CQE of 128 byte descriptor size by default */ 2589 hw->xqe_size = 128; 2590 2591 num_vec = pci_msix_vec_count(pdev); 2592 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 2593 GFP_KERNEL); 2594 if (!hw->irq_name) { 2595 err = -ENOMEM; 2596 goto err_free_netdev; 2597 } 2598 2599 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 2600 sizeof(cpumask_var_t), GFP_KERNEL); 2601 if (!hw->affinity_mask) { 2602 err = -ENOMEM; 2603 goto err_free_netdev; 2604 } 2605 2606 /* Map CSRs */ 2607 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 2608 if (!pf->reg_base) { 2609 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 2610 err = -ENOMEM; 2611 goto err_free_netdev; 2612 } 2613 2614 err = otx2_check_pf_usable(pf); 2615 if (err) 2616 goto err_free_netdev; 2617 2618 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 2619 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 2620 if (err < 0) { 2621 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 2622 __func__, num_vec); 2623 goto err_free_netdev; 2624 } 2625 2626 otx2_setup_dev_hw_settings(pf); 2627 2628 /* Init PF <=> AF mailbox stuff */ 2629 err = otx2_pfaf_mbox_init(pf); 2630 if (err) 2631 goto err_free_irq_vectors; 2632 2633 /* Register mailbox interrupt */ 2634 err = otx2_register_mbox_intr(pf, true); 2635 if (err) 2636 goto err_mbox_destroy; 2637 2638 /* Request AF to attach NPA and NIX LFs to this PF. 2639 * NIX and NPA LFs are needed for this PF to function as a NIC. 2640 */ 2641 err = otx2_attach_npa_nix(pf); 2642 if (err) 2643 goto err_disable_mbox_intr; 2644 2645 err = otx2_realloc_msix_vectors(pf); 2646 if (err) 2647 goto err_detach_rsrc; 2648 2649 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 2650 if (err) 2651 goto err_detach_rsrc; 2652 2653 err = cn10k_lmtst_init(pf); 2654 if (err) 2655 goto err_detach_rsrc; 2656 2657 /* Assign default mac address */ 2658 otx2_get_mac_from_af(netdev); 2659 2660 /* Don't check for error. Proceed without ptp */ 2661 otx2_ptp_init(pf); 2662 2663 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 2664 * HW allocates buffer pointer from stack and uses it for DMA'ing 2665 * ingress packet. In some scenarios HW can free back allocated buffer 2666 * pointers to pool. This makes it impossible for SW to maintain a 2667 * parallel list where physical addresses of buffer pointers (IOVAs) 2668 * given to HW can be saved for later reference. 2669 * 2670 * So the only way to convert Rx packet's buffer address is to use 2671 * IOMMU's iova_to_phys() handler which translates the address by 2672 * walking through the translation tables. 2673 */ 2674 pf->iommu_domain = iommu_get_domain_for_dev(dev); 2675 2676 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 2677 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 2678 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 2679 NETIF_F_GSO_UDP_L4); 2680 netdev->features |= netdev->hw_features; 2681 2682 err = otx2_mcam_flow_init(pf); 2683 if (err) 2684 goto err_ptp_destroy; 2685 2686 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 2687 netdev->hw_features |= NETIF_F_NTUPLE; 2688 2689 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 2690 netdev->priv_flags |= IFF_UNICAST_FLT; 2691 2692 /* Support TSO on tag interface */ 2693 netdev->vlan_features |= netdev->features; 2694 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 2695 NETIF_F_HW_VLAN_STAG_TX; 2696 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2697 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 2698 NETIF_F_HW_VLAN_STAG_RX; 2699 netdev->features |= netdev->hw_features; 2700 2701 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 2702 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 2703 netdev->hw_features |= NETIF_F_HW_TC; 2704 2705 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 2706 2707 netif_set_gso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 2708 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 2709 2710 netdev->netdev_ops = &otx2_netdev_ops; 2711 2712 netdev->min_mtu = OTX2_MIN_MTU; 2713 netdev->max_mtu = otx2_get_max_mtu(pf); 2714 2715 err = register_netdev(netdev); 2716 if (err) { 2717 dev_err(dev, "Failed to register netdevice\n"); 2718 goto err_del_mcam_entries; 2719 } 2720 2721 err = otx2_wq_init(pf); 2722 if (err) 2723 goto err_unreg_netdev; 2724 2725 otx2_set_ethtool_ops(netdev); 2726 2727 err = otx2_init_tc(pf); 2728 if (err) 2729 goto err_mcam_flow_del; 2730 2731 err = otx2_register_dl(pf); 2732 if (err) 2733 goto err_mcam_flow_del; 2734 2735 /* Initialize SR-IOV resources */ 2736 err = otx2_sriov_vfcfg_init(pf); 2737 if (err) 2738 goto err_pf_sriov_init; 2739 2740 /* Enable link notifications */ 2741 otx2_cgx_config_linkevents(pf, true); 2742 2743 #ifdef CONFIG_DCB 2744 err = otx2_dcbnl_set_ops(netdev); 2745 if (err) 2746 goto err_pf_sriov_init; 2747 #endif 2748 2749 return 0; 2750 2751 err_pf_sriov_init: 2752 otx2_shutdown_tc(pf); 2753 err_mcam_flow_del: 2754 otx2_mcam_flow_del(pf); 2755 err_unreg_netdev: 2756 unregister_netdev(netdev); 2757 err_del_mcam_entries: 2758 otx2_mcam_flow_del(pf); 2759 err_ptp_destroy: 2760 otx2_ptp_destroy(pf); 2761 err_detach_rsrc: 2762 if (pf->hw.lmt_info) 2763 free_percpu(pf->hw.lmt_info); 2764 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2765 qmem_free(pf->dev, pf->dync_lmt); 2766 otx2_detach_resources(&pf->mbox); 2767 err_disable_mbox_intr: 2768 otx2_disable_mbox_intr(pf); 2769 err_mbox_destroy: 2770 otx2_pfaf_mbox_destroy(pf); 2771 err_free_irq_vectors: 2772 pci_free_irq_vectors(hw->pdev); 2773 err_free_netdev: 2774 pci_set_drvdata(pdev, NULL); 2775 free_netdev(netdev); 2776 err_release_regions: 2777 pci_release_regions(pdev); 2778 return err; 2779 } 2780 2781 static void otx2_vf_link_event_task(struct work_struct *work) 2782 { 2783 struct otx2_vf_config *config; 2784 struct cgx_link_info_msg *req; 2785 struct mbox_msghdr *msghdr; 2786 struct otx2_nic *pf; 2787 int vf_idx; 2788 2789 config = container_of(work, struct otx2_vf_config, 2790 link_event_work.work); 2791 vf_idx = config - config->pf->vf_configs; 2792 pf = config->pf; 2793 2794 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 2795 sizeof(*req), sizeof(struct msg_rsp)); 2796 if (!msghdr) { 2797 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 2798 return; 2799 } 2800 2801 req = (struct cgx_link_info_msg *)msghdr; 2802 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 2803 req->hdr.sig = OTX2_MBOX_REQ_SIG; 2804 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 2805 2806 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 2807 } 2808 2809 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 2810 { 2811 struct net_device *netdev = pci_get_drvdata(pdev); 2812 struct otx2_nic *pf = netdev_priv(netdev); 2813 int ret; 2814 2815 /* Init PF <=> VF mailbox stuff */ 2816 ret = otx2_pfvf_mbox_init(pf, numvfs); 2817 if (ret) 2818 return ret; 2819 2820 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 2821 if (ret) 2822 goto free_mbox; 2823 2824 ret = otx2_pf_flr_init(pf, numvfs); 2825 if (ret) 2826 goto free_intr; 2827 2828 ret = otx2_register_flr_me_intr(pf, numvfs); 2829 if (ret) 2830 goto free_flr; 2831 2832 ret = pci_enable_sriov(pdev, numvfs); 2833 if (ret) 2834 goto free_flr_intr; 2835 2836 return numvfs; 2837 free_flr_intr: 2838 otx2_disable_flr_me_intr(pf); 2839 free_flr: 2840 otx2_flr_wq_destroy(pf); 2841 free_intr: 2842 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2843 free_mbox: 2844 otx2_pfvf_mbox_destroy(pf); 2845 return ret; 2846 } 2847 2848 static int otx2_sriov_disable(struct pci_dev *pdev) 2849 { 2850 struct net_device *netdev = pci_get_drvdata(pdev); 2851 struct otx2_nic *pf = netdev_priv(netdev); 2852 int numvfs = pci_num_vf(pdev); 2853 2854 if (!numvfs) 2855 return 0; 2856 2857 pci_disable_sriov(pdev); 2858 2859 otx2_disable_flr_me_intr(pf); 2860 otx2_flr_wq_destroy(pf); 2861 otx2_disable_pfvf_mbox_intr(pf, numvfs); 2862 otx2_pfvf_mbox_destroy(pf); 2863 2864 return 0; 2865 } 2866 2867 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 2868 { 2869 if (numvfs == 0) 2870 return otx2_sriov_disable(pdev); 2871 else 2872 return otx2_sriov_enable(pdev, numvfs); 2873 } 2874 2875 static void otx2_remove(struct pci_dev *pdev) 2876 { 2877 struct net_device *netdev = pci_get_drvdata(pdev); 2878 struct otx2_nic *pf; 2879 2880 if (!netdev) 2881 return; 2882 2883 pf = netdev_priv(netdev); 2884 2885 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 2886 2887 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 2888 otx2_config_hw_tx_tstamp(pf, false); 2889 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 2890 otx2_config_hw_rx_tstamp(pf, false); 2891 2892 /* Disable 802.3x pause frames */ 2893 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 2894 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 2895 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 2896 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 2897 otx2_config_pause_frm(pf); 2898 } 2899 2900 #ifdef CONFIG_DCB 2901 /* Disable PFC config */ 2902 if (pf->pfc_en) { 2903 pf->pfc_en = 0; 2904 otx2_config_priority_flow_ctrl(pf); 2905 } 2906 #endif 2907 cancel_work_sync(&pf->reset_task); 2908 /* Disable link notifications */ 2909 otx2_cgx_config_linkevents(pf, false); 2910 2911 otx2_unregister_dl(pf); 2912 unregister_netdev(netdev); 2913 otx2_sriov_disable(pf->pdev); 2914 otx2_sriov_vfcfg_cleanup(pf); 2915 if (pf->otx2_wq) 2916 destroy_workqueue(pf->otx2_wq); 2917 2918 otx2_ptp_destroy(pf); 2919 otx2_mcam_flow_del(pf); 2920 otx2_shutdown_tc(pf); 2921 otx2_detach_resources(&pf->mbox); 2922 if (pf->hw.lmt_info) 2923 free_percpu(pf->hw.lmt_info); 2924 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 2925 qmem_free(pf->dev, pf->dync_lmt); 2926 otx2_disable_mbox_intr(pf); 2927 otx2_pfaf_mbox_destroy(pf); 2928 pci_free_irq_vectors(pf->pdev); 2929 pci_set_drvdata(pdev, NULL); 2930 free_netdev(netdev); 2931 2932 pci_release_regions(pdev); 2933 } 2934 2935 static struct pci_driver otx2_pf_driver = { 2936 .name = DRV_NAME, 2937 .id_table = otx2_pf_id_table, 2938 .probe = otx2_probe, 2939 .shutdown = otx2_remove, 2940 .remove = otx2_remove, 2941 .sriov_configure = otx2_sriov_configure 2942 }; 2943 2944 static int __init otx2_rvupf_init_module(void) 2945 { 2946 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 2947 2948 return pci_register_driver(&otx2_pf_driver); 2949 } 2950 2951 static void __exit otx2_rvupf_cleanup_module(void) 2952 { 2953 pci_unregister_driver(&otx2_pf_driver); 2954 } 2955 2956 module_init(otx2_rvupf_init_module); 2957 module_exit(otx2_rvupf_cleanup_module); 2958