1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/pci.h> 9 #include <linux/ethtool.h> 10 #include <linux/stddef.h> 11 #include <linux/etherdevice.h> 12 #include <linux/log2.h> 13 #include <linux/net_tstamp.h> 14 #include <linux/linkmode.h> 15 16 #include "otx2_common.h" 17 #include "otx2_ptp.h" 18 19 #define DRV_NAME "rvu-nicpf" 20 #define DRV_VF_NAME "rvu-nicvf" 21 22 struct otx2_stat { 23 char name[ETH_GSTRING_LEN]; 24 unsigned int index; 25 }; 26 27 /* HW device stats */ 28 #define OTX2_DEV_STAT(stat) { \ 29 .name = #stat, \ 30 .index = offsetof(struct otx2_dev_stats, stat) / sizeof(u64), \ 31 } 32 33 enum link_mode { 34 OTX2_MODE_SUPPORTED, 35 OTX2_MODE_ADVERTISED 36 }; 37 38 static const struct otx2_stat otx2_dev_stats[] = { 39 OTX2_DEV_STAT(rx_ucast_frames), 40 OTX2_DEV_STAT(rx_bcast_frames), 41 OTX2_DEV_STAT(rx_mcast_frames), 42 43 OTX2_DEV_STAT(tx_ucast_frames), 44 OTX2_DEV_STAT(tx_bcast_frames), 45 OTX2_DEV_STAT(tx_mcast_frames), 46 }; 47 48 /* Driver level stats */ 49 #define OTX2_DRV_STAT(stat) { \ 50 .name = #stat, \ 51 .index = offsetof(struct otx2_drv_stats, stat) / sizeof(atomic_t), \ 52 } 53 54 static const struct otx2_stat otx2_drv_stats[] = { 55 OTX2_DRV_STAT(rx_fcs_errs), 56 OTX2_DRV_STAT(rx_oversize_errs), 57 OTX2_DRV_STAT(rx_undersize_errs), 58 OTX2_DRV_STAT(rx_csum_errs), 59 OTX2_DRV_STAT(rx_len_errs), 60 OTX2_DRV_STAT(rx_other_errs), 61 }; 62 63 static const struct otx2_stat otx2_queue_stats[] = { 64 { "bytes", 0 }, 65 { "frames", 1 }, 66 }; 67 68 static const unsigned int otx2_n_dev_stats = ARRAY_SIZE(otx2_dev_stats); 69 static const unsigned int otx2_n_drv_stats = ARRAY_SIZE(otx2_drv_stats); 70 static const unsigned int otx2_n_queue_stats = ARRAY_SIZE(otx2_queue_stats); 71 72 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf); 73 74 static void otx2_get_drvinfo(struct net_device *netdev, 75 struct ethtool_drvinfo *info) 76 { 77 struct otx2_nic *pfvf = netdev_priv(netdev); 78 79 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 80 strlcpy(info->bus_info, pci_name(pfvf->pdev), sizeof(info->bus_info)); 81 } 82 83 static void otx2_get_qset_strings(struct otx2_nic *pfvf, u8 **data, int qset) 84 { 85 int start_qidx = qset * pfvf->hw.rx_queues; 86 int qidx, stats; 87 88 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 89 for (stats = 0; stats < otx2_n_queue_stats; stats++) { 90 sprintf(*data, "rxq%d: %s", qidx + start_qidx, 91 otx2_queue_stats[stats].name); 92 *data += ETH_GSTRING_LEN; 93 } 94 } 95 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 96 for (stats = 0; stats < otx2_n_queue_stats; stats++) { 97 sprintf(*data, "txq%d: %s", qidx + start_qidx, 98 otx2_queue_stats[stats].name); 99 *data += ETH_GSTRING_LEN; 100 } 101 } 102 } 103 104 static void otx2_get_strings(struct net_device *netdev, u32 sset, u8 *data) 105 { 106 struct otx2_nic *pfvf = netdev_priv(netdev); 107 int stats; 108 109 if (sset != ETH_SS_STATS) 110 return; 111 112 for (stats = 0; stats < otx2_n_dev_stats; stats++) { 113 memcpy(data, otx2_dev_stats[stats].name, ETH_GSTRING_LEN); 114 data += ETH_GSTRING_LEN; 115 } 116 117 for (stats = 0; stats < otx2_n_drv_stats; stats++) { 118 memcpy(data, otx2_drv_stats[stats].name, ETH_GSTRING_LEN); 119 data += ETH_GSTRING_LEN; 120 } 121 122 otx2_get_qset_strings(pfvf, &data, 0); 123 124 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 125 for (stats = 0; stats < CGX_RX_STATS_COUNT; stats++) { 126 sprintf(data, "cgx_rxstat%d: ", stats); 127 data += ETH_GSTRING_LEN; 128 } 129 130 for (stats = 0; stats < CGX_TX_STATS_COUNT; stats++) { 131 sprintf(data, "cgx_txstat%d: ", stats); 132 data += ETH_GSTRING_LEN; 133 } 134 } 135 136 strcpy(data, "reset_count"); 137 data += ETH_GSTRING_LEN; 138 sprintf(data, "Fec Corrected Errors: "); 139 data += ETH_GSTRING_LEN; 140 sprintf(data, "Fec Uncorrected Errors: "); 141 data += ETH_GSTRING_LEN; 142 } 143 144 static void otx2_get_qset_stats(struct otx2_nic *pfvf, 145 struct ethtool_stats *stats, u64 **data) 146 { 147 int stat, qidx; 148 149 if (!pfvf) 150 return; 151 for (qidx = 0; qidx < pfvf->hw.rx_queues; qidx++) { 152 if (!otx2_update_rq_stats(pfvf, qidx)) { 153 for (stat = 0; stat < otx2_n_queue_stats; stat++) 154 *((*data)++) = 0; 155 continue; 156 } 157 for (stat = 0; stat < otx2_n_queue_stats; stat++) 158 *((*data)++) = ((u64 *)&pfvf->qset.rq[qidx].stats) 159 [otx2_queue_stats[stat].index]; 160 } 161 162 for (qidx = 0; qidx < pfvf->hw.tx_queues; qidx++) { 163 if (!otx2_update_sq_stats(pfvf, qidx)) { 164 for (stat = 0; stat < otx2_n_queue_stats; stat++) 165 *((*data)++) = 0; 166 continue; 167 } 168 for (stat = 0; stat < otx2_n_queue_stats; stat++) 169 *((*data)++) = ((u64 *)&pfvf->qset.sq[qidx].stats) 170 [otx2_queue_stats[stat].index]; 171 } 172 } 173 174 static int otx2_get_phy_fec_stats(struct otx2_nic *pfvf) 175 { 176 struct msg_req *req; 177 int rc = -ENOMEM; 178 179 mutex_lock(&pfvf->mbox.lock); 180 req = otx2_mbox_alloc_msg_cgx_get_phy_fec_stats(&pfvf->mbox); 181 if (!req) 182 goto end; 183 184 if (!otx2_sync_mbox_msg(&pfvf->mbox)) 185 rc = 0; 186 end: 187 mutex_unlock(&pfvf->mbox.lock); 188 return rc; 189 } 190 191 /* Get device and per queue statistics */ 192 static void otx2_get_ethtool_stats(struct net_device *netdev, 193 struct ethtool_stats *stats, u64 *data) 194 { 195 struct otx2_nic *pfvf = netdev_priv(netdev); 196 u64 fec_corr_blks, fec_uncorr_blks; 197 struct cgx_fw_data *rsp; 198 int stat; 199 200 otx2_get_dev_stats(pfvf); 201 for (stat = 0; stat < otx2_n_dev_stats; stat++) 202 *(data++) = ((u64 *)&pfvf->hw.dev_stats) 203 [otx2_dev_stats[stat].index]; 204 205 for (stat = 0; stat < otx2_n_drv_stats; stat++) 206 *(data++) = atomic_read(&((atomic_t *)&pfvf->hw.drv_stats) 207 [otx2_drv_stats[stat].index]); 208 209 otx2_get_qset_stats(pfvf, stats, &data); 210 211 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) { 212 otx2_update_lmac_stats(pfvf); 213 for (stat = 0; stat < CGX_RX_STATS_COUNT; stat++) 214 *(data++) = pfvf->hw.cgx_rx_stats[stat]; 215 for (stat = 0; stat < CGX_TX_STATS_COUNT; stat++) 216 *(data++) = pfvf->hw.cgx_tx_stats[stat]; 217 } 218 219 *(data++) = pfvf->reset_count; 220 221 fec_corr_blks = pfvf->hw.cgx_fec_corr_blks; 222 fec_uncorr_blks = pfvf->hw.cgx_fec_uncorr_blks; 223 224 rsp = otx2_get_fwdata(pfvf); 225 if (!IS_ERR(rsp) && rsp->fwdata.phy.misc.has_fec_stats && 226 !otx2_get_phy_fec_stats(pfvf)) { 227 /* Fetch fwdata again because it's been recently populated with 228 * latest PHY FEC stats. 229 */ 230 rsp = otx2_get_fwdata(pfvf); 231 if (!IS_ERR(rsp)) { 232 struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; 233 234 if (pfvf->linfo.fec == OTX2_FEC_BASER) { 235 fec_corr_blks = p->brfec_corr_blks; 236 fec_uncorr_blks = p->brfec_uncorr_blks; 237 } else { 238 fec_corr_blks = p->rsfec_corr_cws; 239 fec_uncorr_blks = p->rsfec_uncorr_cws; 240 } 241 } 242 } 243 244 *(data++) = fec_corr_blks; 245 *(data++) = fec_uncorr_blks; 246 } 247 248 static int otx2_get_sset_count(struct net_device *netdev, int sset) 249 { 250 struct otx2_nic *pfvf = netdev_priv(netdev); 251 int qstats_count, mac_stats = 0; 252 253 if (sset != ETH_SS_STATS) 254 return -EINVAL; 255 256 qstats_count = otx2_n_queue_stats * 257 (pfvf->hw.rx_queues + pfvf->hw.tx_queues); 258 if (!test_bit(CN10K_RPM, &pfvf->hw.cap_flag)) 259 mac_stats = CGX_RX_STATS_COUNT + CGX_TX_STATS_COUNT; 260 otx2_update_lmac_fec_stats(pfvf); 261 262 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 263 mac_stats + OTX2_FEC_STATS_CNT + 1; 264 } 265 266 /* Get no of queues device supports and current queue count */ 267 static void otx2_get_channels(struct net_device *dev, 268 struct ethtool_channels *channel) 269 { 270 struct otx2_nic *pfvf = netdev_priv(dev); 271 272 channel->max_rx = pfvf->hw.max_queues; 273 channel->max_tx = pfvf->hw.max_queues; 274 275 channel->rx_count = pfvf->hw.rx_queues; 276 channel->tx_count = pfvf->hw.tx_queues; 277 } 278 279 /* Set no of Tx, Rx queues to be used */ 280 static int otx2_set_channels(struct net_device *dev, 281 struct ethtool_channels *channel) 282 { 283 struct otx2_nic *pfvf = netdev_priv(dev); 284 bool if_up = netif_running(dev); 285 int err = 0; 286 287 if (!channel->rx_count || !channel->tx_count) 288 return -EINVAL; 289 290 if (bitmap_weight(&pfvf->rq_bmap, pfvf->hw.rx_queues) > 1) { 291 netdev_err(dev, 292 "Receive queues are in use by TC police action\n"); 293 return -EINVAL; 294 } 295 296 if (if_up) 297 dev->netdev_ops->ndo_stop(dev); 298 299 err = otx2_set_real_num_queues(dev, channel->tx_count, 300 channel->rx_count); 301 if (err) 302 return err; 303 304 pfvf->hw.rx_queues = channel->rx_count; 305 pfvf->hw.tx_queues = channel->tx_count; 306 pfvf->qset.cq_cnt = pfvf->hw.tx_queues + pfvf->hw.rx_queues; 307 308 if (if_up) 309 err = dev->netdev_ops->ndo_open(dev); 310 311 netdev_info(dev, "Setting num Tx rings to %d, Rx rings to %d success\n", 312 pfvf->hw.tx_queues, pfvf->hw.rx_queues); 313 314 return err; 315 } 316 317 static void otx2_get_pauseparam(struct net_device *netdev, 318 struct ethtool_pauseparam *pause) 319 { 320 struct otx2_nic *pfvf = netdev_priv(netdev); 321 struct cgx_pause_frm_cfg *req, *rsp; 322 323 if (is_otx2_lbkvf(pfvf->pdev)) 324 return; 325 326 req = otx2_mbox_alloc_msg_cgx_cfg_pause_frm(&pfvf->mbox); 327 if (!req) 328 return; 329 330 if (!otx2_sync_mbox_msg(&pfvf->mbox)) { 331 rsp = (struct cgx_pause_frm_cfg *) 332 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 333 pause->rx_pause = rsp->rx_pause; 334 pause->tx_pause = rsp->tx_pause; 335 } 336 } 337 338 static int otx2_set_pauseparam(struct net_device *netdev, 339 struct ethtool_pauseparam *pause) 340 { 341 struct otx2_nic *pfvf = netdev_priv(netdev); 342 343 if (pause->autoneg) 344 return -EOPNOTSUPP; 345 346 if (is_otx2_lbkvf(pfvf->pdev)) 347 return -EOPNOTSUPP; 348 349 if (pause->rx_pause) 350 pfvf->flags |= OTX2_FLAG_RX_PAUSE_ENABLED; 351 else 352 pfvf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 353 354 if (pause->tx_pause) 355 pfvf->flags |= OTX2_FLAG_TX_PAUSE_ENABLED; 356 else 357 pfvf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 358 359 return otx2_config_pause_frm(pfvf); 360 } 361 362 static void otx2_get_ringparam(struct net_device *netdev, 363 struct ethtool_ringparam *ring) 364 { 365 struct otx2_nic *pfvf = netdev_priv(netdev); 366 struct otx2_qset *qs = &pfvf->qset; 367 368 ring->rx_max_pending = Q_COUNT(Q_SIZE_MAX); 369 ring->rx_pending = qs->rqe_cnt ? qs->rqe_cnt : Q_COUNT(Q_SIZE_256); 370 ring->tx_max_pending = Q_COUNT(Q_SIZE_MAX); 371 ring->tx_pending = qs->sqe_cnt ? qs->sqe_cnt : Q_COUNT(Q_SIZE_4K); 372 } 373 374 static int otx2_set_ringparam(struct net_device *netdev, 375 struct ethtool_ringparam *ring) 376 { 377 struct otx2_nic *pfvf = netdev_priv(netdev); 378 bool if_up = netif_running(netdev); 379 struct otx2_qset *qs = &pfvf->qset; 380 u32 rx_count, tx_count; 381 382 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 383 return -EINVAL; 384 385 /* Permitted lengths are 16 64 256 1K 4K 16K 64K 256K 1M */ 386 rx_count = ring->rx_pending; 387 /* On some silicon variants a skid or reserved CQEs are 388 * needed to avoid CQ overflow. 389 */ 390 if (rx_count < pfvf->hw.rq_skid) 391 rx_count = pfvf->hw.rq_skid; 392 rx_count = Q_COUNT(Q_SIZE(rx_count, 3)); 393 394 /* Due pipelining impact minimum 2000 unused SQ CQE's 395 * need to be maintained to avoid CQ overflow, hence the 396 * minimum 4K size. 397 */ 398 tx_count = clamp_t(u32, ring->tx_pending, 399 Q_COUNT(Q_SIZE_4K), Q_COUNT(Q_SIZE_MAX)); 400 tx_count = Q_COUNT(Q_SIZE(tx_count, 3)); 401 402 if (tx_count == qs->sqe_cnt && rx_count == qs->rqe_cnt) 403 return 0; 404 405 if (if_up) 406 netdev->netdev_ops->ndo_stop(netdev); 407 408 /* Assigned to the nearest possible exponent. */ 409 qs->sqe_cnt = tx_count; 410 qs->rqe_cnt = rx_count; 411 412 if (if_up) 413 return netdev->netdev_ops->ndo_open(netdev); 414 415 return 0; 416 } 417 418 static int otx2_get_coalesce(struct net_device *netdev, 419 struct ethtool_coalesce *cmd, 420 struct kernel_ethtool_coalesce *kernel_coal, 421 struct netlink_ext_ack *extack) 422 { 423 struct otx2_nic *pfvf = netdev_priv(netdev); 424 struct otx2_hw *hw = &pfvf->hw; 425 426 cmd->rx_coalesce_usecs = hw->cq_time_wait; 427 cmd->rx_max_coalesced_frames = hw->cq_ecount_wait; 428 cmd->tx_coalesce_usecs = hw->cq_time_wait; 429 cmd->tx_max_coalesced_frames = hw->cq_ecount_wait; 430 431 return 0; 432 } 433 434 static int otx2_set_coalesce(struct net_device *netdev, 435 struct ethtool_coalesce *ec, 436 struct kernel_ethtool_coalesce *kernel_coal, 437 struct netlink_ext_ack *extack) 438 { 439 struct otx2_nic *pfvf = netdev_priv(netdev); 440 struct otx2_hw *hw = &pfvf->hw; 441 int qidx; 442 443 if (!ec->rx_max_coalesced_frames || !ec->tx_max_coalesced_frames) 444 return 0; 445 446 /* 'cq_time_wait' is 8bit and is in multiple of 100ns, 447 * so clamp the user given value to the range of 1 to 25usec. 448 */ 449 ec->rx_coalesce_usecs = clamp_t(u32, ec->rx_coalesce_usecs, 450 1, CQ_TIMER_THRESH_MAX); 451 ec->tx_coalesce_usecs = clamp_t(u32, ec->tx_coalesce_usecs, 452 1, CQ_TIMER_THRESH_MAX); 453 454 /* Rx and Tx are mapped to same CQ, check which one 455 * is changed, if both then choose the min. 456 */ 457 if (hw->cq_time_wait == ec->rx_coalesce_usecs) 458 hw->cq_time_wait = ec->tx_coalesce_usecs; 459 else if (hw->cq_time_wait == ec->tx_coalesce_usecs) 460 hw->cq_time_wait = ec->rx_coalesce_usecs; 461 else 462 hw->cq_time_wait = min_t(u8, ec->rx_coalesce_usecs, 463 ec->tx_coalesce_usecs); 464 465 /* Max ecount_wait supported is 16bit, 466 * so clamp the user given value to the range of 1 to 64k. 467 */ 468 ec->rx_max_coalesced_frames = clamp_t(u32, ec->rx_max_coalesced_frames, 469 1, U16_MAX); 470 ec->tx_max_coalesced_frames = clamp_t(u32, ec->tx_max_coalesced_frames, 471 1, U16_MAX); 472 473 /* Rx and Tx are mapped to same CQ, check which one 474 * is changed, if both then choose the min. 475 */ 476 if (hw->cq_ecount_wait == ec->rx_max_coalesced_frames) 477 hw->cq_ecount_wait = ec->tx_max_coalesced_frames; 478 else if (hw->cq_ecount_wait == ec->tx_max_coalesced_frames) 479 hw->cq_ecount_wait = ec->rx_max_coalesced_frames; 480 else 481 hw->cq_ecount_wait = min_t(u16, ec->rx_max_coalesced_frames, 482 ec->tx_max_coalesced_frames); 483 484 if (netif_running(netdev)) { 485 for (qidx = 0; qidx < pfvf->hw.cint_cnt; qidx++) 486 otx2_config_irq_coalescing(pfvf, qidx); 487 } 488 489 return 0; 490 } 491 492 static int otx2_get_rss_hash_opts(struct otx2_nic *pfvf, 493 struct ethtool_rxnfc *nfc) 494 { 495 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 496 497 if (!(rss->flowkey_cfg & 498 (NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))) 499 return 0; 500 501 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 502 nfc->data = RXH_IP_SRC | RXH_IP_DST; 503 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_VLAN) 504 nfc->data |= RXH_VLAN; 505 506 switch (nfc->flow_type) { 507 case TCP_V4_FLOW: 508 case TCP_V6_FLOW: 509 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_TCP) 510 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 511 break; 512 case UDP_V4_FLOW: 513 case UDP_V6_FLOW: 514 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_UDP) 515 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 516 break; 517 case SCTP_V4_FLOW: 518 case SCTP_V6_FLOW: 519 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_SCTP) 520 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 521 break; 522 case AH_ESP_V4_FLOW: 523 case AH_ESP_V6_FLOW: 524 if (rss->flowkey_cfg & NIX_FLOW_KEY_TYPE_ESP) 525 nfc->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 526 break; 527 case AH_V4_FLOW: 528 case ESP_V4_FLOW: 529 case IPV4_FLOW: 530 break; 531 case AH_V6_FLOW: 532 case ESP_V6_FLOW: 533 case IPV6_FLOW: 534 break; 535 default: 536 return -EINVAL; 537 } 538 539 return 0; 540 } 541 542 static int otx2_set_rss_hash_opts(struct otx2_nic *pfvf, 543 struct ethtool_rxnfc *nfc) 544 { 545 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 546 u32 rxh_l4 = RXH_L4_B_0_1 | RXH_L4_B_2_3; 547 u32 rss_cfg = rss->flowkey_cfg; 548 549 if (!rss->enable) { 550 netdev_err(pfvf->netdev, 551 "RSS is disabled, cannot change settings\n"); 552 return -EIO; 553 } 554 555 /* Mimimum is IPv4 and IPv6, SIP/DIP */ 556 if (!(nfc->data & RXH_IP_SRC) || !(nfc->data & RXH_IP_DST)) 557 return -EINVAL; 558 559 if (nfc->data & RXH_VLAN) 560 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN; 561 else 562 rss_cfg &= ~NIX_FLOW_KEY_TYPE_VLAN; 563 564 switch (nfc->flow_type) { 565 case TCP_V4_FLOW: 566 case TCP_V6_FLOW: 567 /* Different config for v4 and v6 is not supported. 568 * Both of them have to be either 4-tuple or 2-tuple. 569 */ 570 switch (nfc->data & rxh_l4) { 571 case 0: 572 rss_cfg &= ~NIX_FLOW_KEY_TYPE_TCP; 573 break; 574 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 575 rss_cfg |= NIX_FLOW_KEY_TYPE_TCP; 576 break; 577 default: 578 return -EINVAL; 579 } 580 break; 581 case UDP_V4_FLOW: 582 case UDP_V6_FLOW: 583 switch (nfc->data & rxh_l4) { 584 case 0: 585 rss_cfg &= ~NIX_FLOW_KEY_TYPE_UDP; 586 break; 587 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 588 rss_cfg |= NIX_FLOW_KEY_TYPE_UDP; 589 break; 590 default: 591 return -EINVAL; 592 } 593 break; 594 case SCTP_V4_FLOW: 595 case SCTP_V6_FLOW: 596 switch (nfc->data & rxh_l4) { 597 case 0: 598 rss_cfg &= ~NIX_FLOW_KEY_TYPE_SCTP; 599 break; 600 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 601 rss_cfg |= NIX_FLOW_KEY_TYPE_SCTP; 602 break; 603 default: 604 return -EINVAL; 605 } 606 break; 607 case AH_ESP_V4_FLOW: 608 case AH_ESP_V6_FLOW: 609 switch (nfc->data & rxh_l4) { 610 case 0: 611 rss_cfg &= ~(NIX_FLOW_KEY_TYPE_ESP | 612 NIX_FLOW_KEY_TYPE_AH); 613 rss_cfg |= NIX_FLOW_KEY_TYPE_VLAN | 614 NIX_FLOW_KEY_TYPE_IPV4_PROTO; 615 break; 616 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 617 /* If VLAN hashing is also requested for ESP then do not 618 * allow because of hardware 40 bytes flow key limit. 619 */ 620 if (rss_cfg & NIX_FLOW_KEY_TYPE_VLAN) { 621 netdev_err(pfvf->netdev, 622 "RSS hash of ESP or AH with VLAN is not supported\n"); 623 return -EOPNOTSUPP; 624 } 625 626 rss_cfg |= NIX_FLOW_KEY_TYPE_ESP | NIX_FLOW_KEY_TYPE_AH; 627 /* Disable IPv4 proto hashing since IPv6 SA+DA(32 bytes) 628 * and ESP SPI+sequence(8 bytes) uses hardware maximum 629 * limit of 40 byte flow key. 630 */ 631 rss_cfg &= ~NIX_FLOW_KEY_TYPE_IPV4_PROTO; 632 break; 633 default: 634 return -EINVAL; 635 } 636 break; 637 case IPV4_FLOW: 638 case IPV6_FLOW: 639 rss_cfg = NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 rss->flowkey_cfg = rss_cfg; 646 otx2_set_flowkey_cfg(pfvf); 647 return 0; 648 } 649 650 static int otx2_get_rxnfc(struct net_device *dev, 651 struct ethtool_rxnfc *nfc, u32 *rules) 652 { 653 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 654 struct otx2_nic *pfvf = netdev_priv(dev); 655 int ret = -EOPNOTSUPP; 656 657 switch (nfc->cmd) { 658 case ETHTOOL_GRXRINGS: 659 nfc->data = pfvf->hw.rx_queues; 660 ret = 0; 661 break; 662 case ETHTOOL_GRXCLSRLCNT: 663 if (netif_running(dev) && ntuple) { 664 nfc->rule_cnt = pfvf->flow_cfg->nr_flows; 665 ret = 0; 666 } 667 break; 668 case ETHTOOL_GRXCLSRULE: 669 if (netif_running(dev) && ntuple) 670 ret = otx2_get_flow(pfvf, nfc, nfc->fs.location); 671 break; 672 case ETHTOOL_GRXCLSRLALL: 673 if (netif_running(dev) && ntuple) 674 ret = otx2_get_all_flows(pfvf, nfc, rules); 675 break; 676 case ETHTOOL_GRXFH: 677 return otx2_get_rss_hash_opts(pfvf, nfc); 678 default: 679 break; 680 } 681 return ret; 682 } 683 684 static int otx2_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *nfc) 685 { 686 bool ntuple = !!(dev->features & NETIF_F_NTUPLE); 687 struct otx2_nic *pfvf = netdev_priv(dev); 688 int ret = -EOPNOTSUPP; 689 690 switch (nfc->cmd) { 691 case ETHTOOL_SRXFH: 692 ret = otx2_set_rss_hash_opts(pfvf, nfc); 693 break; 694 case ETHTOOL_SRXCLSRLINS: 695 if (netif_running(dev) && ntuple) 696 ret = otx2_add_flow(pfvf, nfc); 697 break; 698 case ETHTOOL_SRXCLSRLDEL: 699 if (netif_running(dev) && ntuple) 700 ret = otx2_remove_flow(pfvf, nfc->fs.location); 701 break; 702 default: 703 break; 704 } 705 706 return ret; 707 } 708 709 static u32 otx2_get_rxfh_key_size(struct net_device *netdev) 710 { 711 struct otx2_nic *pfvf = netdev_priv(netdev); 712 struct otx2_rss_info *rss; 713 714 rss = &pfvf->hw.rss_info; 715 716 return sizeof(rss->key); 717 } 718 719 static u32 otx2_get_rxfh_indir_size(struct net_device *dev) 720 { 721 return MAX_RSS_INDIR_TBL_SIZE; 722 } 723 724 static int otx2_rss_ctx_delete(struct otx2_nic *pfvf, int ctx_id) 725 { 726 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 727 728 otx2_rss_ctx_flow_del(pfvf, ctx_id); 729 kfree(rss->rss_ctx[ctx_id]); 730 rss->rss_ctx[ctx_id] = NULL; 731 732 return 0; 733 } 734 735 static int otx2_rss_ctx_create(struct otx2_nic *pfvf, 736 u32 *rss_context) 737 { 738 struct otx2_rss_info *rss = &pfvf->hw.rss_info; 739 u8 ctx; 740 741 for (ctx = 0; ctx < MAX_RSS_GROUPS; ctx++) { 742 if (!rss->rss_ctx[ctx]) 743 break; 744 } 745 if (ctx == MAX_RSS_GROUPS) 746 return -EINVAL; 747 748 rss->rss_ctx[ctx] = kzalloc(sizeof(*rss->rss_ctx[ctx]), GFP_KERNEL); 749 if (!rss->rss_ctx[ctx]) 750 return -ENOMEM; 751 *rss_context = ctx; 752 753 return 0; 754 } 755 756 /* RSS context configuration */ 757 static int otx2_set_rxfh_context(struct net_device *dev, const u32 *indir, 758 const u8 *hkey, const u8 hfunc, 759 u32 *rss_context, bool delete) 760 { 761 struct otx2_nic *pfvf = netdev_priv(dev); 762 struct otx2_rss_ctx *rss_ctx; 763 struct otx2_rss_info *rss; 764 int ret, idx; 765 766 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) 767 return -EOPNOTSUPP; 768 769 if (*rss_context != ETH_RXFH_CONTEXT_ALLOC && 770 *rss_context >= MAX_RSS_GROUPS) 771 return -EINVAL; 772 773 rss = &pfvf->hw.rss_info; 774 775 if (!rss->enable) { 776 netdev_err(dev, "RSS is disabled, cannot change settings\n"); 777 return -EIO; 778 } 779 780 if (hkey) { 781 memcpy(rss->key, hkey, sizeof(rss->key)); 782 otx2_set_rss_key(pfvf); 783 } 784 if (delete) 785 return otx2_rss_ctx_delete(pfvf, *rss_context); 786 787 if (*rss_context == ETH_RXFH_CONTEXT_ALLOC) { 788 ret = otx2_rss_ctx_create(pfvf, rss_context); 789 if (ret) 790 return ret; 791 } 792 if (indir) { 793 rss_ctx = rss->rss_ctx[*rss_context]; 794 for (idx = 0; idx < rss->rss_size; idx++) 795 rss_ctx->ind_tbl[idx] = indir[idx]; 796 } 797 otx2_set_rss_table(pfvf, *rss_context); 798 799 return 0; 800 } 801 802 static int otx2_get_rxfh_context(struct net_device *dev, u32 *indir, 803 u8 *hkey, u8 *hfunc, u32 rss_context) 804 { 805 struct otx2_nic *pfvf = netdev_priv(dev); 806 struct otx2_rss_ctx *rss_ctx; 807 struct otx2_rss_info *rss; 808 int idx, rx_queues; 809 810 rss = &pfvf->hw.rss_info; 811 812 if (hfunc) 813 *hfunc = ETH_RSS_HASH_TOP; 814 815 if (!indir) 816 return 0; 817 818 if (!rss->enable && rss_context == DEFAULT_RSS_CONTEXT_GROUP) { 819 rx_queues = pfvf->hw.rx_queues; 820 for (idx = 0; idx < MAX_RSS_INDIR_TBL_SIZE; idx++) 821 indir[idx] = ethtool_rxfh_indir_default(idx, rx_queues); 822 return 0; 823 } 824 if (rss_context >= MAX_RSS_GROUPS) 825 return -ENOENT; 826 827 rss_ctx = rss->rss_ctx[rss_context]; 828 if (!rss_ctx) 829 return -ENOENT; 830 831 if (indir) { 832 for (idx = 0; idx < rss->rss_size; idx++) 833 indir[idx] = rss_ctx->ind_tbl[idx]; 834 } 835 if (hkey) 836 memcpy(hkey, rss->key, sizeof(rss->key)); 837 838 return 0; 839 } 840 841 /* Get RSS configuration */ 842 static int otx2_get_rxfh(struct net_device *dev, u32 *indir, 843 u8 *hkey, u8 *hfunc) 844 { 845 return otx2_get_rxfh_context(dev, indir, hkey, hfunc, 846 DEFAULT_RSS_CONTEXT_GROUP); 847 } 848 849 /* Configure RSS table and hash key */ 850 static int otx2_set_rxfh(struct net_device *dev, const u32 *indir, 851 const u8 *hkey, const u8 hfunc) 852 { 853 854 u32 rss_context = DEFAULT_RSS_CONTEXT_GROUP; 855 856 return otx2_set_rxfh_context(dev, indir, hkey, hfunc, &rss_context, 0); 857 } 858 859 static u32 otx2_get_msglevel(struct net_device *netdev) 860 { 861 struct otx2_nic *pfvf = netdev_priv(netdev); 862 863 return pfvf->msg_enable; 864 } 865 866 static void otx2_set_msglevel(struct net_device *netdev, u32 val) 867 { 868 struct otx2_nic *pfvf = netdev_priv(netdev); 869 870 pfvf->msg_enable = val; 871 } 872 873 static u32 otx2_get_link(struct net_device *netdev) 874 { 875 struct otx2_nic *pfvf = netdev_priv(netdev); 876 877 /* LBK link is internal and always UP */ 878 if (is_otx2_lbkvf(pfvf->pdev)) 879 return 1; 880 return pfvf->linfo.link_up; 881 } 882 883 static int otx2_get_ts_info(struct net_device *netdev, 884 struct ethtool_ts_info *info) 885 { 886 struct otx2_nic *pfvf = netdev_priv(netdev); 887 888 if (!pfvf->ptp) 889 return ethtool_op_get_ts_info(netdev, info); 890 891 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 892 SOF_TIMESTAMPING_RX_SOFTWARE | 893 SOF_TIMESTAMPING_SOFTWARE | 894 SOF_TIMESTAMPING_TX_HARDWARE | 895 SOF_TIMESTAMPING_RX_HARDWARE | 896 SOF_TIMESTAMPING_RAW_HARDWARE; 897 898 info->phc_index = otx2_ptp_clock_index(pfvf); 899 900 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 901 902 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | 903 (1 << HWTSTAMP_FILTER_ALL); 904 905 return 0; 906 } 907 908 static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf) 909 { 910 struct cgx_fw_data *rsp = NULL; 911 struct msg_req *req; 912 int err = 0; 913 914 mutex_lock(&pfvf->mbox.lock); 915 req = otx2_mbox_alloc_msg_cgx_get_aux_link_info(&pfvf->mbox); 916 if (!req) { 917 mutex_unlock(&pfvf->mbox.lock); 918 return ERR_PTR(-ENOMEM); 919 } 920 921 err = otx2_sync_mbox_msg(&pfvf->mbox); 922 if (!err) { 923 rsp = (struct cgx_fw_data *) 924 otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); 925 } else { 926 rsp = ERR_PTR(err); 927 } 928 929 mutex_unlock(&pfvf->mbox.lock); 930 return rsp; 931 } 932 933 static int otx2_get_fecparam(struct net_device *netdev, 934 struct ethtool_fecparam *fecparam) 935 { 936 struct otx2_nic *pfvf = netdev_priv(netdev); 937 struct cgx_fw_data *rsp; 938 const int fec[] = { 939 ETHTOOL_FEC_OFF, 940 ETHTOOL_FEC_BASER, 941 ETHTOOL_FEC_RS, 942 ETHTOOL_FEC_BASER | ETHTOOL_FEC_RS}; 943 #define FEC_MAX_INDEX 4 944 if (pfvf->linfo.fec < FEC_MAX_INDEX) 945 fecparam->active_fec = fec[pfvf->linfo.fec]; 946 947 rsp = otx2_get_fwdata(pfvf); 948 if (IS_ERR(rsp)) 949 return PTR_ERR(rsp); 950 951 if (rsp->fwdata.supported_fec < FEC_MAX_INDEX) { 952 if (!rsp->fwdata.supported_fec) 953 fecparam->fec = ETHTOOL_FEC_NONE; 954 else 955 fecparam->fec = fec[rsp->fwdata.supported_fec]; 956 } 957 return 0; 958 } 959 960 static int otx2_set_fecparam(struct net_device *netdev, 961 struct ethtool_fecparam *fecparam) 962 { 963 struct otx2_nic *pfvf = netdev_priv(netdev); 964 struct mbox *mbox = &pfvf->mbox; 965 struct fec_mode *req, *rsp; 966 int err = 0, fec = 0; 967 968 switch (fecparam->fec) { 969 /* Firmware does not support AUTO mode consider it as FEC_OFF */ 970 case ETHTOOL_FEC_OFF: 971 case ETHTOOL_FEC_AUTO: 972 fec = OTX2_FEC_OFF; 973 break; 974 case ETHTOOL_FEC_RS: 975 fec = OTX2_FEC_RS; 976 break; 977 case ETHTOOL_FEC_BASER: 978 fec = OTX2_FEC_BASER; 979 break; 980 default: 981 netdev_warn(pfvf->netdev, "Unsupported FEC mode: %d", 982 fecparam->fec); 983 return -EINVAL; 984 } 985 986 if (fec == pfvf->linfo.fec) 987 return 0; 988 989 mutex_lock(&mbox->lock); 990 req = otx2_mbox_alloc_msg_cgx_set_fec_param(&pfvf->mbox); 991 if (!req) { 992 err = -ENOMEM; 993 goto end; 994 } 995 req->fec = fec; 996 err = otx2_sync_mbox_msg(&pfvf->mbox); 997 if (err) 998 goto end; 999 1000 rsp = (struct fec_mode *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 1001 0, &req->hdr); 1002 if (rsp->fec >= 0) 1003 pfvf->linfo.fec = rsp->fec; 1004 else 1005 err = rsp->fec; 1006 end: 1007 mutex_unlock(&mbox->lock); 1008 return err; 1009 } 1010 1011 static void otx2_get_fec_info(u64 index, int req_mode, 1012 struct ethtool_link_ksettings *link_ksettings) 1013 { 1014 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_fec_modes) = { 0, }; 1015 1016 switch (index) { 1017 case OTX2_FEC_NONE: 1018 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_NONE_BIT, 1019 otx2_fec_modes); 1020 break; 1021 case OTX2_FEC_BASER: 1022 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1023 otx2_fec_modes); 1024 break; 1025 case OTX2_FEC_RS: 1026 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1027 otx2_fec_modes); 1028 break; 1029 case OTX2_FEC_BASER | OTX2_FEC_RS: 1030 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_BASER_BIT, 1031 otx2_fec_modes); 1032 linkmode_set_bit(ETHTOOL_LINK_MODE_FEC_RS_BIT, 1033 otx2_fec_modes); 1034 break; 1035 } 1036 1037 /* Add fec modes to existing modes */ 1038 if (req_mode == OTX2_MODE_ADVERTISED) 1039 linkmode_or(link_ksettings->link_modes.advertising, 1040 link_ksettings->link_modes.advertising, 1041 otx2_fec_modes); 1042 else 1043 linkmode_or(link_ksettings->link_modes.supported, 1044 link_ksettings->link_modes.supported, 1045 otx2_fec_modes); 1046 } 1047 1048 static void otx2_get_link_mode_info(u64 link_mode_bmap, 1049 bool req_mode, 1050 struct ethtool_link_ksettings 1051 *link_ksettings) 1052 { 1053 __ETHTOOL_DECLARE_LINK_MODE_MASK(otx2_link_modes) = { 0, }; 1054 const int otx2_sgmii_features[6] = { 1055 ETHTOOL_LINK_MODE_10baseT_Half_BIT, 1056 ETHTOOL_LINK_MODE_10baseT_Full_BIT, 1057 ETHTOOL_LINK_MODE_100baseT_Half_BIT, 1058 ETHTOOL_LINK_MODE_100baseT_Full_BIT, 1059 ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 1060 ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 1061 }; 1062 /* CGX link modes to Ethtool link mode mapping */ 1063 const int cgx_link_mode[27] = { 1064 0, /* SGMII Mode */ 1065 ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1066 ETHTOOL_LINK_MODE_10000baseT_Full_BIT, 1067 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, 1068 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT, 1069 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, 1070 0, 1071 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, 1072 0, 1073 0, 1074 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT, 1075 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT, 1076 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT, 1077 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT, 1078 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, 1079 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, 1080 0, 1081 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT, 1082 0, 1083 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT, 1084 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT, 1085 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT, 1086 0, 1087 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, 1088 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT, 1089 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, 1090 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT 1091 }; 1092 u8 bit; 1093 1094 for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { 1095 /* SGMII mode is set */ 1096 if (bit == 0) 1097 linkmode_set_bit_array(otx2_sgmii_features, 1098 ARRAY_SIZE(otx2_sgmii_features), 1099 otx2_link_modes); 1100 else 1101 linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); 1102 } 1103 1104 if (req_mode == OTX2_MODE_ADVERTISED) 1105 linkmode_copy(link_ksettings->link_modes.advertising, 1106 otx2_link_modes); 1107 else 1108 linkmode_copy(link_ksettings->link_modes.supported, 1109 otx2_link_modes); 1110 } 1111 1112 static int otx2_get_link_ksettings(struct net_device *netdev, 1113 struct ethtool_link_ksettings *cmd) 1114 { 1115 struct otx2_nic *pfvf = netdev_priv(netdev); 1116 struct cgx_fw_data *rsp = NULL; 1117 1118 cmd->base.duplex = pfvf->linfo.full_duplex; 1119 cmd->base.speed = pfvf->linfo.speed; 1120 cmd->base.autoneg = pfvf->linfo.an; 1121 1122 rsp = otx2_get_fwdata(pfvf); 1123 if (IS_ERR(rsp)) 1124 return PTR_ERR(rsp); 1125 1126 if (rsp->fwdata.supported_an) 1127 ethtool_link_ksettings_add_link_mode(cmd, 1128 supported, 1129 Autoneg); 1130 1131 otx2_get_link_mode_info(rsp->fwdata.advertised_link_modes, 1132 OTX2_MODE_ADVERTISED, cmd); 1133 otx2_get_fec_info(rsp->fwdata.advertised_fec, 1134 OTX2_MODE_ADVERTISED, cmd); 1135 otx2_get_link_mode_info(rsp->fwdata.supported_link_modes, 1136 OTX2_MODE_SUPPORTED, cmd); 1137 otx2_get_fec_info(rsp->fwdata.supported_fec, 1138 OTX2_MODE_SUPPORTED, cmd); 1139 return 0; 1140 } 1141 1142 static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *cmd, 1143 u64 *mode) 1144 { 1145 u32 bit_pos; 1146 1147 /* Firmware does not support requesting multiple advertised modes 1148 * return first set bit 1149 */ 1150 bit_pos = find_first_bit(cmd->link_modes.advertising, 1151 __ETHTOOL_LINK_MODE_MASK_NBITS); 1152 if (bit_pos != __ETHTOOL_LINK_MODE_MASK_NBITS) 1153 *mode = bit_pos; 1154 } 1155 1156 static int otx2_set_link_ksettings(struct net_device *netdev, 1157 const struct ethtool_link_ksettings *cmd) 1158 { 1159 struct otx2_nic *pf = netdev_priv(netdev); 1160 struct ethtool_link_ksettings cur_ks; 1161 struct cgx_set_link_mode_req *req; 1162 struct mbox *mbox = &pf->mbox; 1163 int err = 0; 1164 1165 memset(&cur_ks, 0, sizeof(struct ethtool_link_ksettings)); 1166 1167 if (!ethtool_validate_speed(cmd->base.speed) || 1168 !ethtool_validate_duplex(cmd->base.duplex)) 1169 return -EINVAL; 1170 1171 if (cmd->base.autoneg != AUTONEG_ENABLE && 1172 cmd->base.autoneg != AUTONEG_DISABLE) 1173 return -EINVAL; 1174 1175 otx2_get_link_ksettings(netdev, &cur_ks); 1176 1177 /* Check requested modes against supported modes by hardware */ 1178 if (!linkmode_subset(cmd->link_modes.advertising, 1179 cur_ks.link_modes.supported)) 1180 return -EINVAL; 1181 1182 mutex_lock(&mbox->lock); 1183 req = otx2_mbox_alloc_msg_cgx_set_link_mode(&pf->mbox); 1184 if (!req) { 1185 err = -ENOMEM; 1186 goto end; 1187 } 1188 1189 req->args.speed = cmd->base.speed; 1190 /* firmware expects 1 for half duplex and 0 for full duplex 1191 * hence inverting 1192 */ 1193 req->args.duplex = cmd->base.duplex ^ 0x1; 1194 req->args.an = cmd->base.autoneg; 1195 otx2_get_advertised_mode(cmd, &req->args.mode); 1196 1197 err = otx2_sync_mbox_msg(&pf->mbox); 1198 end: 1199 mutex_unlock(&mbox->lock); 1200 return err; 1201 } 1202 1203 static const struct ethtool_ops otx2_ethtool_ops = { 1204 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1205 ETHTOOL_COALESCE_MAX_FRAMES, 1206 .get_link = otx2_get_link, 1207 .get_drvinfo = otx2_get_drvinfo, 1208 .get_strings = otx2_get_strings, 1209 .get_ethtool_stats = otx2_get_ethtool_stats, 1210 .get_sset_count = otx2_get_sset_count, 1211 .set_channels = otx2_set_channels, 1212 .get_channels = otx2_get_channels, 1213 .get_ringparam = otx2_get_ringparam, 1214 .set_ringparam = otx2_set_ringparam, 1215 .get_coalesce = otx2_get_coalesce, 1216 .set_coalesce = otx2_set_coalesce, 1217 .get_rxnfc = otx2_get_rxnfc, 1218 .set_rxnfc = otx2_set_rxnfc, 1219 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1220 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1221 .get_rxfh = otx2_get_rxfh, 1222 .set_rxfh = otx2_set_rxfh, 1223 .get_rxfh_context = otx2_get_rxfh_context, 1224 .set_rxfh_context = otx2_set_rxfh_context, 1225 .get_msglevel = otx2_get_msglevel, 1226 .set_msglevel = otx2_set_msglevel, 1227 .get_pauseparam = otx2_get_pauseparam, 1228 .set_pauseparam = otx2_set_pauseparam, 1229 .get_ts_info = otx2_get_ts_info, 1230 .get_fecparam = otx2_get_fecparam, 1231 .set_fecparam = otx2_set_fecparam, 1232 .get_link_ksettings = otx2_get_link_ksettings, 1233 .set_link_ksettings = otx2_set_link_ksettings, 1234 }; 1235 1236 void otx2_set_ethtool_ops(struct net_device *netdev) 1237 { 1238 netdev->ethtool_ops = &otx2_ethtool_ops; 1239 } 1240 1241 /* VF's ethtool APIs */ 1242 static void otx2vf_get_drvinfo(struct net_device *netdev, 1243 struct ethtool_drvinfo *info) 1244 { 1245 struct otx2_nic *vf = netdev_priv(netdev); 1246 1247 strlcpy(info->driver, DRV_VF_NAME, sizeof(info->driver)); 1248 strlcpy(info->bus_info, pci_name(vf->pdev), sizeof(info->bus_info)); 1249 } 1250 1251 static void otx2vf_get_strings(struct net_device *netdev, u32 sset, u8 *data) 1252 { 1253 struct otx2_nic *vf = netdev_priv(netdev); 1254 int stats; 1255 1256 if (sset != ETH_SS_STATS) 1257 return; 1258 1259 for (stats = 0; stats < otx2_n_dev_stats; stats++) { 1260 memcpy(data, otx2_dev_stats[stats].name, ETH_GSTRING_LEN); 1261 data += ETH_GSTRING_LEN; 1262 } 1263 1264 for (stats = 0; stats < otx2_n_drv_stats; stats++) { 1265 memcpy(data, otx2_drv_stats[stats].name, ETH_GSTRING_LEN); 1266 data += ETH_GSTRING_LEN; 1267 } 1268 1269 otx2_get_qset_strings(vf, &data, 0); 1270 1271 strcpy(data, "reset_count"); 1272 data += ETH_GSTRING_LEN; 1273 } 1274 1275 static void otx2vf_get_ethtool_stats(struct net_device *netdev, 1276 struct ethtool_stats *stats, u64 *data) 1277 { 1278 struct otx2_nic *vf = netdev_priv(netdev); 1279 int stat; 1280 1281 otx2_get_dev_stats(vf); 1282 for (stat = 0; stat < otx2_n_dev_stats; stat++) 1283 *(data++) = ((u64 *)&vf->hw.dev_stats) 1284 [otx2_dev_stats[stat].index]; 1285 1286 for (stat = 0; stat < otx2_n_drv_stats; stat++) 1287 *(data++) = atomic_read(&((atomic_t *)&vf->hw.drv_stats) 1288 [otx2_drv_stats[stat].index]); 1289 1290 otx2_get_qset_stats(vf, stats, &data); 1291 *(data++) = vf->reset_count; 1292 } 1293 1294 static int otx2vf_get_sset_count(struct net_device *netdev, int sset) 1295 { 1296 struct otx2_nic *vf = netdev_priv(netdev); 1297 int qstats_count; 1298 1299 if (sset != ETH_SS_STATS) 1300 return -EINVAL; 1301 1302 qstats_count = otx2_n_queue_stats * 1303 (vf->hw.rx_queues + vf->hw.tx_queues); 1304 1305 return otx2_n_dev_stats + otx2_n_drv_stats + qstats_count + 1; 1306 } 1307 1308 static int otx2vf_get_link_ksettings(struct net_device *netdev, 1309 struct ethtool_link_ksettings *cmd) 1310 { 1311 struct otx2_nic *pfvf = netdev_priv(netdev); 1312 1313 if (is_otx2_lbkvf(pfvf->pdev)) { 1314 cmd->base.duplex = DUPLEX_FULL; 1315 cmd->base.speed = SPEED_100000; 1316 } else { 1317 return otx2_get_link_ksettings(netdev, cmd); 1318 } 1319 return 0; 1320 } 1321 1322 static const struct ethtool_ops otx2vf_ethtool_ops = { 1323 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1324 ETHTOOL_COALESCE_MAX_FRAMES, 1325 .get_link = otx2_get_link, 1326 .get_drvinfo = otx2vf_get_drvinfo, 1327 .get_strings = otx2vf_get_strings, 1328 .get_ethtool_stats = otx2vf_get_ethtool_stats, 1329 .get_sset_count = otx2vf_get_sset_count, 1330 .set_channels = otx2_set_channels, 1331 .get_channels = otx2_get_channels, 1332 .get_rxnfc = otx2_get_rxnfc, 1333 .set_rxnfc = otx2_set_rxnfc, 1334 .get_rxfh_key_size = otx2_get_rxfh_key_size, 1335 .get_rxfh_indir_size = otx2_get_rxfh_indir_size, 1336 .get_rxfh = otx2_get_rxfh, 1337 .set_rxfh = otx2_set_rxfh, 1338 .get_rxfh_context = otx2_get_rxfh_context, 1339 .set_rxfh_context = otx2_set_rxfh_context, 1340 .get_ringparam = otx2_get_ringparam, 1341 .set_ringparam = otx2_set_ringparam, 1342 .get_coalesce = otx2_get_coalesce, 1343 .set_coalesce = otx2_set_coalesce, 1344 .get_msglevel = otx2_get_msglevel, 1345 .set_msglevel = otx2_set_msglevel, 1346 .get_pauseparam = otx2_get_pauseparam, 1347 .set_pauseparam = otx2_set_pauseparam, 1348 .get_link_ksettings = otx2vf_get_link_ksettings, 1349 .get_ts_info = otx2_get_ts_info, 1350 }; 1351 1352 void otx2vf_set_ethtool_ops(struct net_device *netdev) 1353 { 1354 netdev->ethtool_ops = &otx2vf_ethtool_ops; 1355 } 1356 EXPORT_SYMBOL(otx2vf_set_ethtool_ops); 1357