1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/ethtool.h> 15 #include <linux/pci.h> 16 #include <linux/iommu.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/timecounter.h> 20 #include <linux/soc/marvell/octeontx2/asm.h> 21 #include <net/pkt_cls.h> 22 23 #include <mbox.h> 24 #include <npc.h> 25 #include "otx2_reg.h" 26 #include "otx2_txrx.h" 27 #include <rvu_trace.h> 28 29 /* PCI device IDs */ 30 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 31 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 32 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 33 34 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 35 36 /* PCI BAR nos */ 37 #define PCI_CFG_REG_BAR_NUM 2 38 #define PCI_MBOX_BAR_NUM 4 39 40 #define NAME_SIZE 32 41 42 enum arua_mapped_qtypes { 43 AURA_NIX_RQ, 44 AURA_NIX_SQ, 45 }; 46 47 /* NIX LF interrupts range*/ 48 #define NIX_LF_QINT_VEC_START 0x00 49 #define NIX_LF_CINT_VEC_START 0x40 50 #define NIX_LF_GINT_VEC 0x80 51 #define NIX_LF_ERR_VEC 0x81 52 #define NIX_LF_POISON_VEC 0x82 53 54 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 55 #define SEND_CQ_SKID 2000 56 57 /* RSS configuration */ 58 struct otx2_rss_ctx { 59 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 60 }; 61 62 struct otx2_rss_info { 63 u8 enable; 64 u32 flowkey_cfg; 65 u16 rss_size; 66 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 67 u8 key[RSS_HASH_KEY_SIZE]; 68 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 69 }; 70 71 /* NIX (or NPC) RX errors */ 72 enum otx2_errlvl { 73 NPC_ERRLVL_RE, 74 NPC_ERRLVL_LID_LA, 75 NPC_ERRLVL_LID_LB, 76 NPC_ERRLVL_LID_LC, 77 NPC_ERRLVL_LID_LD, 78 NPC_ERRLVL_LID_LE, 79 NPC_ERRLVL_LID_LF, 80 NPC_ERRLVL_LID_LG, 81 NPC_ERRLVL_LID_LH, 82 NPC_ERRLVL_NIX = 0x0F, 83 }; 84 85 enum otx2_errcodes_re { 86 /* NPC_ERRLVL_RE errcodes */ 87 ERRCODE_FCS = 0x7, 88 ERRCODE_FCS_RCV = 0x8, 89 ERRCODE_UNDERSIZE = 0x10, 90 ERRCODE_OVERSIZE = 0x11, 91 ERRCODE_OL2_LEN_MISMATCH = 0x12, 92 /* NPC_ERRLVL_NIX errcodes */ 93 ERRCODE_OL3_LEN = 0x10, 94 ERRCODE_OL4_LEN = 0x11, 95 ERRCODE_OL4_CSUM = 0x12, 96 ERRCODE_IL3_LEN = 0x20, 97 ERRCODE_IL4_LEN = 0x21, 98 ERRCODE_IL4_CSUM = 0x22, 99 }; 100 101 /* NIX TX stats */ 102 enum nix_stat_lf_tx { 103 TX_UCAST = 0x0, 104 TX_BCAST = 0x1, 105 TX_MCAST = 0x2, 106 TX_DROP = 0x3, 107 TX_OCTS = 0x4, 108 TX_STATS_ENUM_LAST, 109 }; 110 111 /* NIX RX stats */ 112 enum nix_stat_lf_rx { 113 RX_OCTS = 0x0, 114 RX_UCAST = 0x1, 115 RX_BCAST = 0x2, 116 RX_MCAST = 0x3, 117 RX_DROP = 0x4, 118 RX_DROP_OCTS = 0x5, 119 RX_FCS = 0x6, 120 RX_ERR = 0x7, 121 RX_DRP_BCAST = 0x8, 122 RX_DRP_MCAST = 0x9, 123 RX_DRP_L3BCAST = 0xa, 124 RX_DRP_L3MCAST = 0xb, 125 RX_STATS_ENUM_LAST, 126 }; 127 128 struct otx2_dev_stats { 129 u64 rx_bytes; 130 u64 rx_frames; 131 u64 rx_ucast_frames; 132 u64 rx_bcast_frames; 133 u64 rx_mcast_frames; 134 u64 rx_drops; 135 136 u64 tx_bytes; 137 u64 tx_frames; 138 u64 tx_ucast_frames; 139 u64 tx_bcast_frames; 140 u64 tx_mcast_frames; 141 u64 tx_drops; 142 }; 143 144 /* Driver counted stats */ 145 struct otx2_drv_stats { 146 atomic_t rx_fcs_errs; 147 atomic_t rx_oversize_errs; 148 atomic_t rx_undersize_errs; 149 atomic_t rx_csum_errs; 150 atomic_t rx_len_errs; 151 atomic_t rx_other_errs; 152 }; 153 154 struct mbox { 155 struct otx2_mbox mbox; 156 struct work_struct mbox_wrk; 157 struct otx2_mbox mbox_up; 158 struct work_struct mbox_up_wrk; 159 struct otx2_nic *pfvf; 160 void *bbuf_base; /* Bounce buffer for mbox memory */ 161 struct mutex lock; /* serialize mailbox access */ 162 int num_msgs; /* mbox number of messages */ 163 int up_num_msgs; /* mbox_up number of messages */ 164 }; 165 166 struct otx2_hw { 167 struct pci_dev *pdev; 168 struct otx2_rss_info rss_info; 169 u16 rx_queues; 170 u16 tx_queues; 171 u16 max_queues; 172 u16 pool_cnt; 173 u16 rqpool_cnt; 174 u16 sqpool_cnt; 175 176 /* NPA */ 177 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 178 u32 stack_pg_bytes; /* Size of stack page */ 179 u16 sqb_size; 180 181 /* NIX */ 182 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 183 184 /* HW settings, coalescing etc */ 185 u16 rx_chan_base; 186 u16 tx_chan_base; 187 u16 cq_qcount_wait; 188 u16 cq_ecount_wait; 189 u16 rq_skid; 190 u8 cq_time_wait; 191 192 /* Segmentation */ 193 u8 lso_tsov4_idx; 194 u8 lso_tsov6_idx; 195 u8 lso_udpv4_idx; 196 u8 lso_udpv6_idx; 197 198 /* MSI-X */ 199 u8 cint_cnt; /* CQ interrupt count */ 200 u16 npa_msixoff; /* Offset of NPA vectors */ 201 u16 nix_msixoff; /* Offset of NIX vectors */ 202 char *irq_name; 203 cpumask_var_t *affinity_mask; 204 205 /* Stats */ 206 struct otx2_dev_stats dev_stats; 207 struct otx2_drv_stats drv_stats; 208 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 209 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 210 u64 cgx_fec_corr_blks; 211 u64 cgx_fec_uncorr_blks; 212 u8 cgx_links; /* No. of CGX links present in HW */ 213 u8 lbk_links; /* No. of LBK links present in HW */ 214 #define HW_TSO 0 215 #define CN10K_MBOX 1 216 #define CN10K_LMTST 2 217 unsigned long cap_flag; 218 219 #define LMT_LINE_SIZE 128 220 #define NIX_LMTID_BASE 72 /* RX + TX + XDP */ 221 void __iomem *lmt_base; 222 u64 *npa_lmt_base; 223 u64 *nix_lmt_base; 224 }; 225 226 enum vfperm { 227 OTX2_RESET_VF_PERM, 228 OTX2_TRUSTED_VF, 229 }; 230 231 struct otx2_vf_config { 232 struct otx2_nic *pf; 233 struct delayed_work link_event_work; 234 bool intf_down; /* interface was either configured or not */ 235 u8 mac[ETH_ALEN]; 236 u16 vlan; 237 int tx_vtag_idx; 238 bool trusted; 239 }; 240 241 struct flr_work { 242 struct work_struct work; 243 struct otx2_nic *pf; 244 }; 245 246 struct refill_work { 247 struct delayed_work pool_refill_work; 248 struct otx2_nic *pf; 249 }; 250 251 struct otx2_ptp { 252 struct ptp_clock_info ptp_info; 253 struct ptp_clock *ptp_clock; 254 struct otx2_nic *nic; 255 256 struct cyclecounter cycle_counter; 257 struct timecounter time_counter; 258 }; 259 260 #define OTX2_HW_TIMESTAMP_LEN 8 261 262 struct otx2_mac_table { 263 u8 addr[ETH_ALEN]; 264 u16 mcam_entry; 265 bool inuse; 266 }; 267 268 struct otx2_flow_config { 269 u16 entry[NPC_MAX_NONCONTIG_ENTRIES]; 270 u32 nr_flows; 271 #define OTX2_MAX_NTUPLE_FLOWS 32 272 #define OTX2_MAX_UNICAST_FLOWS 8 273 #define OTX2_MAX_VLAN_FLOWS 1 274 #define OTX2_MAX_TC_FLOWS OTX2_MAX_NTUPLE_FLOWS 275 #define OTX2_MCAM_COUNT (OTX2_MAX_NTUPLE_FLOWS + \ 276 OTX2_MAX_UNICAST_FLOWS + \ 277 OTX2_MAX_VLAN_FLOWS) 278 u32 ntuple_offset; 279 u32 unicast_offset; 280 u32 rx_vlan_offset; 281 u32 vf_vlan_offset; 282 #define OTX2_PER_VF_VLAN_FLOWS 2 /* rx+tx per VF */ 283 #define OTX2_VF_VLAN_RX_INDEX 0 284 #define OTX2_VF_VLAN_TX_INDEX 1 285 u32 tc_flower_offset; 286 u32 ntuple_max_flows; 287 u32 tc_max_flows; 288 struct list_head flow_list; 289 }; 290 291 struct otx2_tc_info { 292 /* hash table to store TC offloaded flows */ 293 struct rhashtable flow_table; 294 struct rhashtable_params flow_ht_params; 295 DECLARE_BITMAP(tc_entries_bitmap, OTX2_MAX_TC_FLOWS); 296 unsigned long num_entries; 297 }; 298 299 struct dev_hw_ops { 300 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 301 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 302 int size, int qidx); 303 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 304 void (*aura_freeptr)(void *dev, int aura, u64 buf); 305 }; 306 307 struct otx2_nic { 308 void __iomem *reg_base; 309 struct net_device *netdev; 310 struct dev_hw_ops *hw_ops; 311 void *iommu_domain; 312 u16 max_frs; 313 u16 rbsize; /* Receive buffer size */ 314 315 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 316 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 317 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 318 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 319 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 320 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 321 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 322 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 323 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 324 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 325 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 326 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 327 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 328 u64 flags; 329 330 struct otx2_qset qset; 331 struct otx2_hw hw; 332 struct pci_dev *pdev; 333 struct device *dev; 334 335 /* Mbox */ 336 struct mbox mbox; 337 struct mbox *mbox_pfvf; 338 struct workqueue_struct *mbox_wq; 339 struct workqueue_struct *mbox_pfvf_wq; 340 341 u8 total_vfs; 342 u16 pcifunc; /* RVU PF_FUNC */ 343 u16 bpid[NIX_MAX_BPID_CHAN]; 344 struct otx2_vf_config *vf_configs; 345 struct cgx_link_user_info linfo; 346 347 u64 reset_count; 348 struct work_struct reset_task; 349 struct workqueue_struct *flr_wq; 350 struct flr_work *flr_wrk; 351 struct refill_work *refill_wrk; 352 struct workqueue_struct *otx2_wq; 353 struct work_struct rx_mode_work; 354 struct otx2_mac_table *mac_table; 355 356 /* Ethtool stuff */ 357 u32 msg_enable; 358 359 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 360 int nix_blkaddr; 361 /* LMTST Lines info */ 362 u16 tot_lmt_lines; 363 u16 nix_lmt_lines; 364 u32 nix_lmt_size; 365 366 struct otx2_ptp *ptp; 367 struct hwtstamp_config tstamp; 368 369 struct otx2_flow_config *flow_cfg; 370 struct otx2_tc_info tc_info; 371 }; 372 373 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 374 { 375 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 376 } 377 378 static inline bool is_96xx_A0(struct pci_dev *pdev) 379 { 380 return (pdev->revision == 0x00) && 381 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 382 } 383 384 static inline bool is_96xx_B0(struct pci_dev *pdev) 385 { 386 return (pdev->revision == 0x01) && 387 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 388 } 389 390 /* REVID for PCIe devices. 391 * Bits 0..1: minor pass, bit 3..2: major pass 392 * bits 7..4: midr id 393 */ 394 #define PCI_REVISION_ID_96XX 0x00 395 #define PCI_REVISION_ID_95XX 0x10 396 #define PCI_REVISION_ID_LOKI 0x20 397 #define PCI_REVISION_ID_98XX 0x30 398 #define PCI_REVISION_ID_95XXMM 0x40 399 400 static inline bool is_dev_otx2(struct pci_dev *pdev) 401 { 402 u8 midr = pdev->revision & 0xF0; 403 404 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 405 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || 406 midr == PCI_REVISION_ID_95XXMM); 407 } 408 409 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 410 { 411 struct otx2_hw *hw = &pfvf->hw; 412 413 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 414 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 415 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 416 417 __set_bit(HW_TSO, &hw->cap_flag); 418 419 if (is_96xx_A0(pfvf->pdev)) { 420 __clear_bit(HW_TSO, &hw->cap_flag); 421 422 /* Time based irq coalescing is not supported */ 423 pfvf->hw.cq_qcount_wait = 0x0; 424 425 /* Due to HW issue previous silicons required minimum 426 * 600 unused CQE to avoid CQ overflow. 427 */ 428 pfvf->hw.rq_skid = 600; 429 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 430 } 431 if (is_96xx_B0(pfvf->pdev)) 432 __clear_bit(HW_TSO, &hw->cap_flag); 433 434 if (!is_dev_otx2(pfvf->pdev)) { 435 __set_bit(CN10K_MBOX, &hw->cap_flag); 436 __set_bit(CN10K_LMTST, &hw->cap_flag); 437 } 438 } 439 440 /* Register read/write APIs */ 441 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 442 { 443 u64 blkaddr; 444 445 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 446 case BLKTYPE_NIX: 447 blkaddr = nic->nix_blkaddr; 448 break; 449 case BLKTYPE_NPA: 450 blkaddr = BLKADDR_NPA; 451 break; 452 default: 453 blkaddr = BLKADDR_RVUM; 454 break; 455 } 456 457 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 458 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 459 460 return nic->reg_base + offset; 461 } 462 463 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 464 { 465 void __iomem *addr = otx2_get_regaddr(nic, offset); 466 467 writeq(val, addr); 468 } 469 470 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 471 { 472 void __iomem *addr = otx2_get_regaddr(nic, offset); 473 474 return readq(addr); 475 } 476 477 /* Mbox bounce buffer APIs */ 478 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 479 { 480 struct otx2_mbox *otx2_mbox; 481 struct otx2_mbox_dev *mdev; 482 483 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 484 if (!mbox->bbuf_base) 485 return -ENOMEM; 486 487 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 488 * prepare all mbox messages in bounce buffer instead of directly 489 * in hw mbox memory. 490 */ 491 otx2_mbox = &mbox->mbox; 492 mdev = &otx2_mbox->dev[0]; 493 mdev->mbase = mbox->bbuf_base; 494 495 otx2_mbox = &mbox->mbox_up; 496 mdev = &otx2_mbox->dev[0]; 497 mdev->mbase = mbox->bbuf_base; 498 return 0; 499 } 500 501 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 502 { 503 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 504 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 505 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 506 struct mbox_hdr *hdr; 507 u64 msg_size; 508 509 if (mdev->mbase == hw_mbase) 510 return; 511 512 hdr = hw_mbase + mbox->rx_start; 513 msg_size = hdr->msg_size; 514 515 if (msg_size > mbox->rx_size - msgs_offset) 516 msg_size = mbox->rx_size - msgs_offset; 517 518 /* Copy mbox messages from mbox memory to bounce buffer */ 519 memcpy(mdev->mbase + mbox->rx_start, 520 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 521 } 522 523 /* With the absence of API for 128-bit IO memory access for arm64, 524 * implement required operations at place. 525 */ 526 #if defined(CONFIG_ARM64) 527 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 528 { 529 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 530 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 531 } 532 533 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 534 { 535 u64 result; 536 537 __asm__ volatile(".cpu generic+lse\n" 538 "ldadd %x[i], %x[r], [%[b]]" 539 : [r]"=r"(result), "+m"(*ptr) 540 : [i]"r"(incr), [b]"r"(ptr) 541 : "memory"); 542 return result; 543 } 544 545 #else 546 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 547 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 548 #endif 549 550 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 551 u64 *ptrs, u64 num_ptrs, 552 u64 *lmt_addr) 553 { 554 u64 size = 0, count_eot = 0; 555 u64 tar_addr, val = 0; 556 557 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 558 /* LMTID is same as AURA Id */ 559 val = (aura & 0x7FF) | BIT_ULL(63); 560 /* Set if [127:64] of last 128bit word has a valid pointer */ 561 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 562 /* Set AURA ID to free pointer */ 563 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 564 /* Target address for LMTST flush tells HW how many 128bit 565 * words are valid from NPA_LF_AURA_BATCH_FREE0. 566 * 567 * tar_addr[6:4] is LMTST size-1 in units of 128b. 568 */ 569 if (num_ptrs > 2) { 570 size = (sizeof(u64) * num_ptrs) / 16; 571 if (!count_eot) 572 size++; 573 tar_addr |= ((size - 1) & 0x7) << 4; 574 } 575 memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs); 576 /* Perform LMTST flush */ 577 cn10k_lmt_flush(val, tar_addr); 578 } 579 580 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 581 { 582 struct otx2_nic *pfvf = dev; 583 struct otx2_pool *pool; 584 u64 ptrs[2]; 585 586 pool = &pfvf->qset.pool[aura]; 587 ptrs[1] = buf; 588 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr); 589 } 590 591 /* Alloc pointer from pool/aura */ 592 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 593 { 594 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 595 NPA_LF_AURA_OP_ALLOCX(0)); 596 u64 incr = (u64)aura | BIT_ULL(63); 597 598 return otx2_atomic64_add(incr, ptr); 599 } 600 601 /* Free pointer to a pool/aura */ 602 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 603 { 604 struct otx2_nic *pfvf = dev; 605 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 606 607 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 608 } 609 610 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 611 { 612 if (type == AURA_NIX_SQ) 613 return pfvf->hw.rqpool_cnt + idx; 614 615 /* AURA_NIX_RQ */ 616 return idx; 617 } 618 619 /* Mbox APIs */ 620 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 621 { 622 int err; 623 624 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 625 return 0; 626 otx2_mbox_msg_send(&mbox->mbox, 0); 627 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 628 if (err) 629 return err; 630 631 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 632 } 633 634 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 635 { 636 int err; 637 638 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 639 return 0; 640 otx2_mbox_msg_send(&mbox->mbox_up, devid); 641 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 642 if (err) 643 return err; 644 645 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 646 } 647 648 /* Use this API to send mbox msgs in atomic context 649 * where sleeping is not allowed 650 */ 651 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 652 { 653 int err; 654 655 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 656 return 0; 657 otx2_mbox_msg_send(&mbox->mbox, 0); 658 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 659 if (err) 660 return err; 661 662 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 663 } 664 665 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 666 static struct _req_type __maybe_unused \ 667 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 668 { \ 669 struct _req_type *req; \ 670 \ 671 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 672 &mbox->mbox, 0, sizeof(struct _req_type), \ 673 sizeof(struct _rsp_type)); \ 674 if (!req) \ 675 return NULL; \ 676 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 677 req->hdr.id = _id; \ 678 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 679 return req; \ 680 } 681 682 MBOX_MESSAGES 683 #undef M 684 685 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 686 int \ 687 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 688 struct _req_type *req, \ 689 struct _rsp_type *rsp); \ 690 691 MBOX_UP_CGX_MESSAGES 692 #undef M 693 694 /* Time to wait before watchdog kicks off */ 695 #define OTX2_TX_TIMEOUT (100 * HZ) 696 697 #define RVU_PFVF_PF_SHIFT 10 698 #define RVU_PFVF_PF_MASK 0x3F 699 #define RVU_PFVF_FUNC_SHIFT 0 700 #define RVU_PFVF_FUNC_MASK 0x3FF 701 702 static inline int rvu_get_pf(u16 pcifunc) 703 { 704 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 705 } 706 707 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 708 struct page *page, 709 size_t offset, size_t size, 710 enum dma_data_direction dir) 711 { 712 dma_addr_t iova; 713 714 iova = dma_map_page_attrs(pfvf->dev, page, 715 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 716 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 717 return (dma_addr_t)NULL; 718 return iova; 719 } 720 721 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 722 dma_addr_t addr, size_t size, 723 enum dma_data_direction dir) 724 { 725 dma_unmap_page_attrs(pfvf->dev, addr, size, 726 dir, DMA_ATTR_SKIP_CPU_SYNC); 727 } 728 729 /* MSI-X APIs */ 730 void otx2_free_cints(struct otx2_nic *pfvf, int n); 731 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 732 int otx2_set_mac_address(struct net_device *netdev, void *p); 733 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 734 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 735 void otx2_get_mac_from_af(struct net_device *netdev); 736 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 737 int otx2_config_pause_frm(struct otx2_nic *pfvf); 738 void otx2_setup_segmentation(struct otx2_nic *pfvf); 739 740 /* RVU block related APIs */ 741 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 742 int otx2_detach_resources(struct mbox *mbox); 743 int otx2_config_npa(struct otx2_nic *pfvf); 744 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 745 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 746 void otx2_aura_pool_free(struct otx2_nic *pfvf); 747 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 748 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 749 int otx2_config_nix(struct otx2_nic *pfvf); 750 int otx2_config_nix_queues(struct otx2_nic *pfvf); 751 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 752 int otx2_txsch_alloc(struct otx2_nic *pfvf); 753 int otx2_txschq_stop(struct otx2_nic *pfvf); 754 void otx2_sqb_flush(struct otx2_nic *pfvf); 755 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 756 dma_addr_t *dma); 757 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 758 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 759 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 760 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 761 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 762 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 763 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 764 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 765 dma_addr_t *dma); 766 767 /* RSS configuration APIs*/ 768 int otx2_rss_init(struct otx2_nic *pfvf); 769 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 770 void otx2_set_rss_key(struct otx2_nic *pfvf); 771 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 772 773 /* Mbox handlers */ 774 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 775 struct msix_offset_rsp *rsp); 776 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 777 struct npa_lf_alloc_rsp *rsp); 778 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 779 struct nix_lf_alloc_rsp *rsp); 780 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 781 struct nix_txsch_alloc_rsp *rsp); 782 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 783 struct cgx_stats_rsp *rsp); 784 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 785 struct cgx_fec_stats_rsp *rsp); 786 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 787 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 788 struct nix_bp_cfg_rsp *rsp); 789 790 /* Device stats APIs */ 791 void otx2_get_dev_stats(struct otx2_nic *pfvf); 792 void otx2_get_stats64(struct net_device *netdev, 793 struct rtnl_link_stats64 *stats); 794 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 795 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 796 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 797 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 798 void otx2_set_ethtool_ops(struct net_device *netdev); 799 void otx2vf_set_ethtool_ops(struct net_device *netdev); 800 801 int otx2_open(struct net_device *netdev); 802 int otx2_stop(struct net_device *netdev); 803 int otx2_set_real_num_queues(struct net_device *netdev, 804 int tx_queues, int rx_queues); 805 /* MCAM filter related APIs */ 806 int otx2_mcam_flow_init(struct otx2_nic *pf); 807 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf); 808 void otx2_mcam_flow_del(struct otx2_nic *pf); 809 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 810 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 811 int otx2_get_flow(struct otx2_nic *pfvf, 812 struct ethtool_rxnfc *nfc, u32 location); 813 int otx2_get_all_flows(struct otx2_nic *pfvf, 814 struct ethtool_rxnfc *nfc, u32 *rule_locs); 815 int otx2_add_flow(struct otx2_nic *pfvf, 816 struct ethtool_rxnfc *nfc); 817 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 818 int otx2_prepare_flow_request(struct ethtool_rx_flow_spec *fsp, 819 struct npc_install_flow_req *req); 820 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 821 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 822 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 823 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 824 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 825 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 826 /* tc support */ 827 int otx2_init_tc(struct otx2_nic *nic); 828 void otx2_shutdown_tc(struct otx2_nic *nic); 829 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 830 void *type_data); 831 #endif /* OTX2_COMMON_H */ 832