1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef OTX2_COMMON_H 12 #define OTX2_COMMON_H 13 14 #include <linux/ethtool.h> 15 #include <linux/pci.h> 16 #include <linux/iommu.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/ptp_clock_kernel.h> 19 #include <linux/timecounter.h> 20 #include <linux/soc/marvell/octeontx2/asm.h> 21 #include <net/pkt_cls.h> 22 #include <net/devlink.h> 23 24 #include <mbox.h> 25 #include <npc.h> 26 #include "otx2_reg.h" 27 #include "otx2_txrx.h" 28 #include "otx2_devlink.h" 29 #include <rvu_trace.h> 30 31 /* PCI device IDs */ 32 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 33 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 34 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 35 36 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 37 38 /* PCI BAR nos */ 39 #define PCI_CFG_REG_BAR_NUM 2 40 #define PCI_MBOX_BAR_NUM 4 41 42 #define NAME_SIZE 32 43 44 enum arua_mapped_qtypes { 45 AURA_NIX_RQ, 46 AURA_NIX_SQ, 47 }; 48 49 /* NIX LF interrupts range*/ 50 #define NIX_LF_QINT_VEC_START 0x00 51 #define NIX_LF_CINT_VEC_START 0x40 52 #define NIX_LF_GINT_VEC 0x80 53 #define NIX_LF_ERR_VEC 0x81 54 #define NIX_LF_POISON_VEC 0x82 55 56 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 57 #define SEND_CQ_SKID 2000 58 59 /* RSS configuration */ 60 struct otx2_rss_ctx { 61 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 62 }; 63 64 struct otx2_rss_info { 65 u8 enable; 66 u32 flowkey_cfg; 67 u16 rss_size; 68 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 69 u8 key[RSS_HASH_KEY_SIZE]; 70 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 71 }; 72 73 /* NIX (or NPC) RX errors */ 74 enum otx2_errlvl { 75 NPC_ERRLVL_RE, 76 NPC_ERRLVL_LID_LA, 77 NPC_ERRLVL_LID_LB, 78 NPC_ERRLVL_LID_LC, 79 NPC_ERRLVL_LID_LD, 80 NPC_ERRLVL_LID_LE, 81 NPC_ERRLVL_LID_LF, 82 NPC_ERRLVL_LID_LG, 83 NPC_ERRLVL_LID_LH, 84 NPC_ERRLVL_NIX = 0x0F, 85 }; 86 87 enum otx2_errcodes_re { 88 /* NPC_ERRLVL_RE errcodes */ 89 ERRCODE_FCS = 0x7, 90 ERRCODE_FCS_RCV = 0x8, 91 ERRCODE_UNDERSIZE = 0x10, 92 ERRCODE_OVERSIZE = 0x11, 93 ERRCODE_OL2_LEN_MISMATCH = 0x12, 94 /* NPC_ERRLVL_NIX errcodes */ 95 ERRCODE_OL3_LEN = 0x10, 96 ERRCODE_OL4_LEN = 0x11, 97 ERRCODE_OL4_CSUM = 0x12, 98 ERRCODE_IL3_LEN = 0x20, 99 ERRCODE_IL4_LEN = 0x21, 100 ERRCODE_IL4_CSUM = 0x22, 101 }; 102 103 /* NIX TX stats */ 104 enum nix_stat_lf_tx { 105 TX_UCAST = 0x0, 106 TX_BCAST = 0x1, 107 TX_MCAST = 0x2, 108 TX_DROP = 0x3, 109 TX_OCTS = 0x4, 110 TX_STATS_ENUM_LAST, 111 }; 112 113 /* NIX RX stats */ 114 enum nix_stat_lf_rx { 115 RX_OCTS = 0x0, 116 RX_UCAST = 0x1, 117 RX_BCAST = 0x2, 118 RX_MCAST = 0x3, 119 RX_DROP = 0x4, 120 RX_DROP_OCTS = 0x5, 121 RX_FCS = 0x6, 122 RX_ERR = 0x7, 123 RX_DRP_BCAST = 0x8, 124 RX_DRP_MCAST = 0x9, 125 RX_DRP_L3BCAST = 0xa, 126 RX_DRP_L3MCAST = 0xb, 127 RX_STATS_ENUM_LAST, 128 }; 129 130 struct otx2_dev_stats { 131 u64 rx_bytes; 132 u64 rx_frames; 133 u64 rx_ucast_frames; 134 u64 rx_bcast_frames; 135 u64 rx_mcast_frames; 136 u64 rx_drops; 137 138 u64 tx_bytes; 139 u64 tx_frames; 140 u64 tx_ucast_frames; 141 u64 tx_bcast_frames; 142 u64 tx_mcast_frames; 143 u64 tx_drops; 144 }; 145 146 /* Driver counted stats */ 147 struct otx2_drv_stats { 148 atomic_t rx_fcs_errs; 149 atomic_t rx_oversize_errs; 150 atomic_t rx_undersize_errs; 151 atomic_t rx_csum_errs; 152 atomic_t rx_len_errs; 153 atomic_t rx_other_errs; 154 }; 155 156 struct mbox { 157 struct otx2_mbox mbox; 158 struct work_struct mbox_wrk; 159 struct otx2_mbox mbox_up; 160 struct work_struct mbox_up_wrk; 161 struct otx2_nic *pfvf; 162 void *bbuf_base; /* Bounce buffer for mbox memory */ 163 struct mutex lock; /* serialize mailbox access */ 164 int num_msgs; /* mbox number of messages */ 165 int up_num_msgs; /* mbox_up number of messages */ 166 }; 167 168 struct otx2_hw { 169 struct pci_dev *pdev; 170 struct otx2_rss_info rss_info; 171 u16 rx_queues; 172 u16 tx_queues; 173 u16 max_queues; 174 u16 pool_cnt; 175 u16 rqpool_cnt; 176 u16 sqpool_cnt; 177 178 /* NPA */ 179 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 180 u32 stack_pg_bytes; /* Size of stack page */ 181 u16 sqb_size; 182 183 /* NIX */ 184 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 185 u16 matchall_ipolicer; 186 u32 dwrr_mtu; 187 188 /* HW settings, coalescing etc */ 189 u16 rx_chan_base; 190 u16 tx_chan_base; 191 u16 cq_qcount_wait; 192 u16 cq_ecount_wait; 193 u16 rq_skid; 194 u8 cq_time_wait; 195 196 /* Segmentation */ 197 u8 lso_tsov4_idx; 198 u8 lso_tsov6_idx; 199 u8 lso_udpv4_idx; 200 u8 lso_udpv6_idx; 201 202 /* RSS */ 203 u8 flowkey_alg_idx; 204 205 /* MSI-X */ 206 u8 cint_cnt; /* CQ interrupt count */ 207 u16 npa_msixoff; /* Offset of NPA vectors */ 208 u16 nix_msixoff; /* Offset of NIX vectors */ 209 char *irq_name; 210 cpumask_var_t *affinity_mask; 211 212 /* Stats */ 213 struct otx2_dev_stats dev_stats; 214 struct otx2_drv_stats drv_stats; 215 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 216 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 217 u64 cgx_fec_corr_blks; 218 u64 cgx_fec_uncorr_blks; 219 u8 cgx_links; /* No. of CGX links present in HW */ 220 u8 lbk_links; /* No. of LBK links present in HW */ 221 u8 tx_link; /* Transmit channel link number */ 222 #define HW_TSO 0 223 #define CN10K_MBOX 1 224 #define CN10K_LMTST 2 225 unsigned long cap_flag; 226 227 #define LMT_LINE_SIZE 128 228 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 229 u64 *lmt_base; 230 u64 *npa_lmt_base; 231 u64 *nix_lmt_base; 232 }; 233 234 enum vfperm { 235 OTX2_RESET_VF_PERM, 236 OTX2_TRUSTED_VF, 237 }; 238 239 struct otx2_vf_config { 240 struct otx2_nic *pf; 241 struct delayed_work link_event_work; 242 bool intf_down; /* interface was either configured or not */ 243 u8 mac[ETH_ALEN]; 244 u16 vlan; 245 int tx_vtag_idx; 246 bool trusted; 247 }; 248 249 struct flr_work { 250 struct work_struct work; 251 struct otx2_nic *pf; 252 }; 253 254 struct refill_work { 255 struct delayed_work pool_refill_work; 256 struct otx2_nic *pf; 257 }; 258 259 struct otx2_ptp { 260 struct ptp_clock_info ptp_info; 261 struct ptp_clock *ptp_clock; 262 struct otx2_nic *nic; 263 264 struct cyclecounter cycle_counter; 265 struct timecounter time_counter; 266 }; 267 268 #define OTX2_HW_TIMESTAMP_LEN 8 269 270 struct otx2_mac_table { 271 u8 addr[ETH_ALEN]; 272 u16 mcam_entry; 273 bool inuse; 274 }; 275 276 struct otx2_flow_config { 277 u16 *flow_ent; 278 u16 *def_ent; 279 u16 nr_flows; 280 #define OTX2_DEFAULT_FLOWCOUNT 16 281 #define OTX2_MAX_UNICAST_FLOWS 8 282 #define OTX2_MAX_VLAN_FLOWS 1 283 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 284 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 285 OTX2_MAX_UNICAST_FLOWS + \ 286 OTX2_MAX_VLAN_FLOWS) 287 u16 unicast_offset; 288 u16 rx_vlan_offset; 289 u16 vf_vlan_offset; 290 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 291 #define OTX2_VF_VLAN_RX_INDEX 0 292 #define OTX2_VF_VLAN_TX_INDEX 1 293 u16 max_flows; 294 u8 dmacflt_max_flows; 295 u8 *bmap_to_dmacindex; 296 unsigned long dmacflt_bmap; 297 struct list_head flow_list; 298 }; 299 300 struct otx2_tc_info { 301 /* hash table to store TC offloaded flows */ 302 struct rhashtable flow_table; 303 struct rhashtable_params flow_ht_params; 304 unsigned long *tc_entries_bitmap; 305 }; 306 307 struct dev_hw_ops { 308 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 309 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 310 int size, int qidx); 311 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 312 void (*aura_freeptr)(void *dev, int aura, u64 buf); 313 }; 314 315 struct otx2_nic { 316 void __iomem *reg_base; 317 struct net_device *netdev; 318 struct dev_hw_ops *hw_ops; 319 void *iommu_domain; 320 u16 max_frs; 321 u16 rbsize; /* Receive buffer size */ 322 323 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 324 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 325 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 326 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 327 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 328 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 329 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 330 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 331 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 332 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 333 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 334 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 335 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 336 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 337 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 338 u64 flags; 339 340 struct otx2_qset qset; 341 struct otx2_hw hw; 342 struct pci_dev *pdev; 343 struct device *dev; 344 345 /* Mbox */ 346 struct mbox mbox; 347 struct mbox *mbox_pfvf; 348 struct workqueue_struct *mbox_wq; 349 struct workqueue_struct *mbox_pfvf_wq; 350 351 u8 total_vfs; 352 u16 pcifunc; /* RVU PF_FUNC */ 353 u16 bpid[NIX_MAX_BPID_CHAN]; 354 struct otx2_vf_config *vf_configs; 355 struct cgx_link_user_info linfo; 356 357 /* NPC MCAM */ 358 struct otx2_flow_config *flow_cfg; 359 struct otx2_mac_table *mac_table; 360 struct otx2_tc_info tc_info; 361 362 u64 reset_count; 363 struct work_struct reset_task; 364 struct workqueue_struct *flr_wq; 365 struct flr_work *flr_wrk; 366 struct refill_work *refill_wrk; 367 struct workqueue_struct *otx2_wq; 368 struct work_struct rx_mode_work; 369 370 /* Ethtool stuff */ 371 u32 msg_enable; 372 373 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 374 int nix_blkaddr; 375 /* LMTST Lines info */ 376 struct qmem *dync_lmt; 377 u16 tot_lmt_lines; 378 u16 npa_lmt_lines; 379 u32 nix_lmt_size; 380 381 struct otx2_ptp *ptp; 382 struct hwtstamp_config tstamp; 383 384 unsigned long rq_bmap; 385 386 /* Devlink */ 387 struct otx2_devlink *dl; 388 }; 389 390 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 391 { 392 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 393 } 394 395 static inline bool is_96xx_A0(struct pci_dev *pdev) 396 { 397 return (pdev->revision == 0x00) && 398 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 399 } 400 401 static inline bool is_96xx_B0(struct pci_dev *pdev) 402 { 403 return (pdev->revision == 0x01) && 404 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 405 } 406 407 /* REVID for PCIe devices. 408 * Bits 0..1: minor pass, bit 3..2: major pass 409 * bits 7..4: midr id 410 */ 411 #define PCI_REVISION_ID_96XX 0x00 412 #define PCI_REVISION_ID_95XX 0x10 413 #define PCI_REVISION_ID_LOKI 0x20 414 #define PCI_REVISION_ID_98XX 0x30 415 #define PCI_REVISION_ID_95XXMM 0x40 416 417 static inline bool is_dev_otx2(struct pci_dev *pdev) 418 { 419 u8 midr = pdev->revision & 0xF0; 420 421 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 422 midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX || 423 midr == PCI_REVISION_ID_95XXMM); 424 } 425 426 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 427 { 428 struct otx2_hw *hw = &pfvf->hw; 429 430 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 431 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 432 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 433 434 __set_bit(HW_TSO, &hw->cap_flag); 435 436 if (is_96xx_A0(pfvf->pdev)) { 437 __clear_bit(HW_TSO, &hw->cap_flag); 438 439 /* Time based irq coalescing is not supported */ 440 pfvf->hw.cq_qcount_wait = 0x0; 441 442 /* Due to HW issue previous silicons required minimum 443 * 600 unused CQE to avoid CQ overflow. 444 */ 445 pfvf->hw.rq_skid = 600; 446 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 447 } 448 if (is_96xx_B0(pfvf->pdev)) 449 __clear_bit(HW_TSO, &hw->cap_flag); 450 451 if (!is_dev_otx2(pfvf->pdev)) { 452 __set_bit(CN10K_MBOX, &hw->cap_flag); 453 __set_bit(CN10K_LMTST, &hw->cap_flag); 454 } 455 } 456 457 /* Register read/write APIs */ 458 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 459 { 460 u64 blkaddr; 461 462 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 463 case BLKTYPE_NIX: 464 blkaddr = nic->nix_blkaddr; 465 break; 466 case BLKTYPE_NPA: 467 blkaddr = BLKADDR_NPA; 468 break; 469 default: 470 blkaddr = BLKADDR_RVUM; 471 break; 472 } 473 474 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 475 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 476 477 return nic->reg_base + offset; 478 } 479 480 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 481 { 482 void __iomem *addr = otx2_get_regaddr(nic, offset); 483 484 writeq(val, addr); 485 } 486 487 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 488 { 489 void __iomem *addr = otx2_get_regaddr(nic, offset); 490 491 return readq(addr); 492 } 493 494 /* Mbox bounce buffer APIs */ 495 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 496 { 497 struct otx2_mbox *otx2_mbox; 498 struct otx2_mbox_dev *mdev; 499 500 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 501 if (!mbox->bbuf_base) 502 return -ENOMEM; 503 504 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 505 * prepare all mbox messages in bounce buffer instead of directly 506 * in hw mbox memory. 507 */ 508 otx2_mbox = &mbox->mbox; 509 mdev = &otx2_mbox->dev[0]; 510 mdev->mbase = mbox->bbuf_base; 511 512 otx2_mbox = &mbox->mbox_up; 513 mdev = &otx2_mbox->dev[0]; 514 mdev->mbase = mbox->bbuf_base; 515 return 0; 516 } 517 518 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 519 { 520 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 521 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 522 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 523 struct mbox_hdr *hdr; 524 u64 msg_size; 525 526 if (mdev->mbase == hw_mbase) 527 return; 528 529 hdr = hw_mbase + mbox->rx_start; 530 msg_size = hdr->msg_size; 531 532 if (msg_size > mbox->rx_size - msgs_offset) 533 msg_size = mbox->rx_size - msgs_offset; 534 535 /* Copy mbox messages from mbox memory to bounce buffer */ 536 memcpy(mdev->mbase + mbox->rx_start, 537 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 538 } 539 540 /* With the absence of API for 128-bit IO memory access for arm64, 541 * implement required operations at place. 542 */ 543 #if defined(CONFIG_ARM64) 544 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 545 { 546 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 547 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 548 } 549 550 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 551 { 552 u64 result; 553 554 __asm__ volatile(".cpu generic+lse\n" 555 "ldadd %x[i], %x[r], [%[b]]" 556 : [r]"=r"(result), "+m"(*ptr) 557 : [i]"r"(incr), [b]"r"(ptr) 558 : "memory"); 559 return result; 560 } 561 562 #else 563 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 564 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 565 #endif 566 567 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 568 u64 *ptrs, u64 num_ptrs, 569 u64 *lmt_addr) 570 { 571 u64 size = 0, count_eot = 0; 572 u64 tar_addr, val = 0; 573 574 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 575 /* LMTID is same as AURA Id */ 576 val = (aura & 0x7FF) | BIT_ULL(63); 577 /* Set if [127:64] of last 128bit word has a valid pointer */ 578 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 579 /* Set AURA ID to free pointer */ 580 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 581 /* Target address for LMTST flush tells HW how many 128bit 582 * words are valid from NPA_LF_AURA_BATCH_FREE0. 583 * 584 * tar_addr[6:4] is LMTST size-1 in units of 128b. 585 */ 586 if (num_ptrs > 2) { 587 size = (sizeof(u64) * num_ptrs) / 16; 588 if (!count_eot) 589 size++; 590 tar_addr |= ((size - 1) & 0x7) << 4; 591 } 592 memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs); 593 /* Perform LMTST flush */ 594 cn10k_lmt_flush(val, tar_addr); 595 } 596 597 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 598 { 599 struct otx2_nic *pfvf = dev; 600 struct otx2_pool *pool; 601 u64 ptrs[2]; 602 603 pool = &pfvf->qset.pool[aura]; 604 ptrs[1] = buf; 605 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr); 606 } 607 608 /* Alloc pointer from pool/aura */ 609 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 610 { 611 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 612 NPA_LF_AURA_OP_ALLOCX(0)); 613 u64 incr = (u64)aura | BIT_ULL(63); 614 615 return otx2_atomic64_add(incr, ptr); 616 } 617 618 /* Free pointer to a pool/aura */ 619 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 620 { 621 struct otx2_nic *pfvf = dev; 622 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 623 624 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 625 } 626 627 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 628 { 629 if (type == AURA_NIX_SQ) 630 return pfvf->hw.rqpool_cnt + idx; 631 632 /* AURA_NIX_RQ */ 633 return idx; 634 } 635 636 /* Mbox APIs */ 637 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 638 { 639 int err; 640 641 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 642 return 0; 643 otx2_mbox_msg_send(&mbox->mbox, 0); 644 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 645 if (err) 646 return err; 647 648 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 649 } 650 651 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 652 { 653 int err; 654 655 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 656 return 0; 657 otx2_mbox_msg_send(&mbox->mbox_up, devid); 658 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 659 if (err) 660 return err; 661 662 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 663 } 664 665 /* Use this API to send mbox msgs in atomic context 666 * where sleeping is not allowed 667 */ 668 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 669 { 670 int err; 671 672 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 673 return 0; 674 otx2_mbox_msg_send(&mbox->mbox, 0); 675 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 676 if (err) 677 return err; 678 679 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 680 } 681 682 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 683 static struct _req_type __maybe_unused \ 684 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 685 { \ 686 struct _req_type *req; \ 687 \ 688 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 689 &mbox->mbox, 0, sizeof(struct _req_type), \ 690 sizeof(struct _rsp_type)); \ 691 if (!req) \ 692 return NULL; \ 693 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 694 req->hdr.id = _id; \ 695 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 696 return req; \ 697 } 698 699 MBOX_MESSAGES 700 #undef M 701 702 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 703 int \ 704 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 705 struct _req_type *req, \ 706 struct _rsp_type *rsp); \ 707 708 MBOX_UP_CGX_MESSAGES 709 #undef M 710 711 /* Time to wait before watchdog kicks off */ 712 #define OTX2_TX_TIMEOUT (100 * HZ) 713 714 #define RVU_PFVF_PF_SHIFT 10 715 #define RVU_PFVF_PF_MASK 0x3F 716 #define RVU_PFVF_FUNC_SHIFT 0 717 #define RVU_PFVF_FUNC_MASK 0x3FF 718 719 static inline bool is_otx2_vf(u16 pcifunc) 720 { 721 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 722 } 723 724 static inline int rvu_get_pf(u16 pcifunc) 725 { 726 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 727 } 728 729 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 730 struct page *page, 731 size_t offset, size_t size, 732 enum dma_data_direction dir) 733 { 734 dma_addr_t iova; 735 736 iova = dma_map_page_attrs(pfvf->dev, page, 737 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 738 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 739 return (dma_addr_t)NULL; 740 return iova; 741 } 742 743 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 744 dma_addr_t addr, size_t size, 745 enum dma_data_direction dir) 746 { 747 dma_unmap_page_attrs(pfvf->dev, addr, size, 748 dir, DMA_ATTR_SKIP_CPU_SYNC); 749 } 750 751 /* MSI-X APIs */ 752 void otx2_free_cints(struct otx2_nic *pfvf, int n); 753 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 754 int otx2_set_mac_address(struct net_device *netdev, void *p); 755 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 756 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 757 void otx2_get_mac_from_af(struct net_device *netdev); 758 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 759 int otx2_config_pause_frm(struct otx2_nic *pfvf); 760 void otx2_setup_segmentation(struct otx2_nic *pfvf); 761 762 /* RVU block related APIs */ 763 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 764 int otx2_detach_resources(struct mbox *mbox); 765 int otx2_config_npa(struct otx2_nic *pfvf); 766 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 767 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 768 void otx2_aura_pool_free(struct otx2_nic *pfvf); 769 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 770 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 771 int otx2_config_nix(struct otx2_nic *pfvf); 772 int otx2_config_nix_queues(struct otx2_nic *pfvf); 773 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 774 int otx2_txsch_alloc(struct otx2_nic *pfvf); 775 int otx2_txschq_stop(struct otx2_nic *pfvf); 776 void otx2_sqb_flush(struct otx2_nic *pfvf); 777 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 778 dma_addr_t *dma); 779 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 780 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 781 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 782 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 783 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 784 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 785 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 786 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 787 dma_addr_t *dma); 788 789 /* RSS configuration APIs*/ 790 int otx2_rss_init(struct otx2_nic *pfvf); 791 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 792 void otx2_set_rss_key(struct otx2_nic *pfvf); 793 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 794 795 /* Mbox handlers */ 796 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 797 struct msix_offset_rsp *rsp); 798 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 799 struct npa_lf_alloc_rsp *rsp); 800 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 801 struct nix_lf_alloc_rsp *rsp); 802 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 803 struct nix_txsch_alloc_rsp *rsp); 804 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 805 struct cgx_stats_rsp *rsp); 806 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 807 struct cgx_fec_stats_rsp *rsp); 808 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 809 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 810 struct nix_bp_cfg_rsp *rsp); 811 812 /* Device stats APIs */ 813 void otx2_get_dev_stats(struct otx2_nic *pfvf); 814 void otx2_get_stats64(struct net_device *netdev, 815 struct rtnl_link_stats64 *stats); 816 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 817 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 818 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 819 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 820 void otx2_set_ethtool_ops(struct net_device *netdev); 821 void otx2vf_set_ethtool_ops(struct net_device *netdev); 822 823 int otx2_open(struct net_device *netdev); 824 int otx2_stop(struct net_device *netdev); 825 int otx2_set_real_num_queues(struct net_device *netdev, 826 int tx_queues, int rx_queues); 827 /* MCAM filter related APIs */ 828 int otx2_mcam_flow_init(struct otx2_nic *pf); 829 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 830 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 831 void otx2_mcam_flow_del(struct otx2_nic *pf); 832 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 833 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 834 int otx2_get_flow(struct otx2_nic *pfvf, 835 struct ethtool_rxnfc *nfc, u32 location); 836 int otx2_get_all_flows(struct otx2_nic *pfvf, 837 struct ethtool_rxnfc *nfc, u32 *rule_locs); 838 int otx2_add_flow(struct otx2_nic *pfvf, 839 struct ethtool_rxnfc *nfc); 840 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 841 int otx2_prepare_flow_request(struct ethtool_rx_flow_spec *fsp, 842 struct npc_install_flow_req *req); 843 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 844 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 845 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 846 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 847 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 848 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 849 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 850 /* tc support */ 851 int otx2_init_tc(struct otx2_nic *nic); 852 void otx2_shutdown_tc(struct otx2_nic *nic); 853 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 854 void *type_data); 855 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic); 856 /* CGX/RPM DMAC filters support */ 857 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 858 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); 859 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); 860 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos); 861 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 862 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 863 #endif /* OTX2_COMMON_H */ 864