1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #ifndef OTX2_COMMON_H 9 #define OTX2_COMMON_H 10 11 #include <linux/ethtool.h> 12 #include <linux/pci.h> 13 #include <linux/iommu.h> 14 #include <linux/net_tstamp.h> 15 #include <linux/ptp_clock_kernel.h> 16 #include <linux/timecounter.h> 17 #include <linux/soc/marvell/octeontx2/asm.h> 18 #include <net/pkt_cls.h> 19 #include <net/devlink.h> 20 #include <linux/time64.h> 21 #include <linux/dim.h> 22 23 #include <mbox.h> 24 #include <npc.h> 25 #include "otx2_reg.h" 26 #include "otx2_txrx.h" 27 #include "otx2_devlink.h" 28 #include <rvu_trace.h> 29 30 /* PCI device IDs */ 31 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063 32 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064 33 #define PCI_DEVID_OCTEONTX2_RVU_AFVF 0xA0F8 34 35 #define PCI_SUBSYS_DEVID_96XX_RVU_PFVF 0xB200 36 37 /* PCI BAR nos */ 38 #define PCI_CFG_REG_BAR_NUM 2 39 #define PCI_MBOX_BAR_NUM 4 40 41 #define NAME_SIZE 32 42 43 enum arua_mapped_qtypes { 44 AURA_NIX_RQ, 45 AURA_NIX_SQ, 46 }; 47 48 /* NIX LF interrupts range*/ 49 #define NIX_LF_QINT_VEC_START 0x00 50 #define NIX_LF_CINT_VEC_START 0x40 51 #define NIX_LF_GINT_VEC 0x80 52 #define NIX_LF_ERR_VEC 0x81 53 #define NIX_LF_POISON_VEC 0x82 54 55 /* Send skid of 2000 packets required for CQ size of 4K CQEs. */ 56 #define SEND_CQ_SKID 2000 57 58 #define OTX2_GET_RX_STATS(reg) \ 59 otx2_read64(pfvf, NIX_LF_RX_STATX(reg)) 60 #define OTX2_GET_TX_STATS(reg) \ 61 otx2_read64(pfvf, NIX_LF_TX_STATX(reg)) 62 63 struct otx2_lmt_info { 64 u64 lmt_addr; 65 u16 lmt_id; 66 }; 67 /* RSS configuration */ 68 struct otx2_rss_ctx { 69 u8 ind_tbl[MAX_RSS_INDIR_TBL_SIZE]; 70 }; 71 72 struct otx2_rss_info { 73 u8 enable; 74 u32 flowkey_cfg; 75 u16 rss_size; 76 #define RSS_HASH_KEY_SIZE 44 /* 352 bit key */ 77 u8 key[RSS_HASH_KEY_SIZE]; 78 struct otx2_rss_ctx *rss_ctx[MAX_RSS_GROUPS]; 79 }; 80 81 /* NIX (or NPC) RX errors */ 82 enum otx2_errlvl { 83 NPC_ERRLVL_RE, 84 NPC_ERRLVL_LID_LA, 85 NPC_ERRLVL_LID_LB, 86 NPC_ERRLVL_LID_LC, 87 NPC_ERRLVL_LID_LD, 88 NPC_ERRLVL_LID_LE, 89 NPC_ERRLVL_LID_LF, 90 NPC_ERRLVL_LID_LG, 91 NPC_ERRLVL_LID_LH, 92 NPC_ERRLVL_NIX = 0x0F, 93 }; 94 95 enum otx2_errcodes_re { 96 /* NPC_ERRLVL_RE errcodes */ 97 ERRCODE_FCS = 0x7, 98 ERRCODE_FCS_RCV = 0x8, 99 ERRCODE_UNDERSIZE = 0x10, 100 ERRCODE_OVERSIZE = 0x11, 101 ERRCODE_OL2_LEN_MISMATCH = 0x12, 102 /* NPC_ERRLVL_NIX errcodes */ 103 ERRCODE_OL3_LEN = 0x10, 104 ERRCODE_OL4_LEN = 0x11, 105 ERRCODE_OL4_CSUM = 0x12, 106 ERRCODE_IL3_LEN = 0x20, 107 ERRCODE_IL4_LEN = 0x21, 108 ERRCODE_IL4_CSUM = 0x22, 109 }; 110 111 /* NIX TX stats */ 112 enum nix_stat_lf_tx { 113 TX_UCAST = 0x0, 114 TX_BCAST = 0x1, 115 TX_MCAST = 0x2, 116 TX_DROP = 0x3, 117 TX_OCTS = 0x4, 118 TX_STATS_ENUM_LAST, 119 }; 120 121 /* NIX RX stats */ 122 enum nix_stat_lf_rx { 123 RX_OCTS = 0x0, 124 RX_UCAST = 0x1, 125 RX_BCAST = 0x2, 126 RX_MCAST = 0x3, 127 RX_DROP = 0x4, 128 RX_DROP_OCTS = 0x5, 129 RX_FCS = 0x6, 130 RX_ERR = 0x7, 131 RX_DRP_BCAST = 0x8, 132 RX_DRP_MCAST = 0x9, 133 RX_DRP_L3BCAST = 0xa, 134 RX_DRP_L3MCAST = 0xb, 135 RX_STATS_ENUM_LAST, 136 }; 137 138 struct otx2_dev_stats { 139 u64 rx_bytes; 140 u64 rx_frames; 141 u64 rx_ucast_frames; 142 u64 rx_bcast_frames; 143 u64 rx_mcast_frames; 144 u64 rx_drops; 145 146 u64 tx_bytes; 147 u64 tx_frames; 148 u64 tx_ucast_frames; 149 u64 tx_bcast_frames; 150 u64 tx_mcast_frames; 151 u64 tx_drops; 152 }; 153 154 /* Driver counted stats */ 155 struct otx2_drv_stats { 156 atomic_t rx_fcs_errs; 157 atomic_t rx_oversize_errs; 158 atomic_t rx_undersize_errs; 159 atomic_t rx_csum_errs; 160 atomic_t rx_len_errs; 161 atomic_t rx_other_errs; 162 }; 163 164 struct mbox { 165 struct otx2_mbox mbox; 166 struct work_struct mbox_wrk; 167 struct otx2_mbox mbox_up; 168 struct work_struct mbox_up_wrk; 169 struct otx2_nic *pfvf; 170 void *bbuf_base; /* Bounce buffer for mbox memory */ 171 struct mutex lock; /* serialize mailbox access */ 172 int num_msgs; /* mbox number of messages */ 173 int up_num_msgs; /* mbox_up number of messages */ 174 }; 175 176 struct otx2_hw { 177 struct pci_dev *pdev; 178 struct otx2_rss_info rss_info; 179 u16 rx_queues; 180 u16 tx_queues; 181 u16 xdp_queues; 182 u16 tot_tx_queues; 183 u16 max_queues; 184 u16 pool_cnt; 185 u16 rqpool_cnt; 186 u16 sqpool_cnt; 187 188 #define OTX2_DEFAULT_RBUF_LEN 2048 189 u16 rbuf_len; 190 u32 xqe_size; 191 192 /* NPA */ 193 u32 stack_pg_ptrs; /* No of ptrs per stack page */ 194 u32 stack_pg_bytes; /* Size of stack page */ 195 u16 sqb_size; 196 197 /* NIX */ 198 u16 txschq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; 199 u16 matchall_ipolicer; 200 u32 dwrr_mtu; 201 202 /* HW settings, coalescing etc */ 203 u16 rx_chan_base; 204 u16 tx_chan_base; 205 u16 cq_qcount_wait; 206 u16 cq_ecount_wait; 207 u16 rq_skid; 208 u8 cq_time_wait; 209 210 /* Segmentation */ 211 u8 lso_tsov4_idx; 212 u8 lso_tsov6_idx; 213 u8 lso_udpv4_idx; 214 u8 lso_udpv6_idx; 215 216 /* RSS */ 217 u8 flowkey_alg_idx; 218 219 /* MSI-X */ 220 u8 cint_cnt; /* CQ interrupt count */ 221 u16 npa_msixoff; /* Offset of NPA vectors */ 222 u16 nix_msixoff; /* Offset of NIX vectors */ 223 char *irq_name; 224 cpumask_var_t *affinity_mask; 225 226 /* Stats */ 227 struct otx2_dev_stats dev_stats; 228 struct otx2_drv_stats drv_stats; 229 u64 cgx_rx_stats[CGX_RX_STATS_COUNT]; 230 u64 cgx_tx_stats[CGX_TX_STATS_COUNT]; 231 u64 cgx_fec_corr_blks; 232 u64 cgx_fec_uncorr_blks; 233 u8 cgx_links; /* No. of CGX links present in HW */ 234 u8 lbk_links; /* No. of LBK links present in HW */ 235 u8 tx_link; /* Transmit channel link number */ 236 #define HW_TSO 0 237 #define CN10K_MBOX 1 238 #define CN10K_LMTST 2 239 #define CN10K_RPM 3 240 unsigned long cap_flag; 241 242 #define LMT_LINE_SIZE 128 243 #define LMT_BURST_SIZE 32 /* 32 LMTST lines for burst SQE flush */ 244 u64 *lmt_base; 245 struct otx2_lmt_info __percpu *lmt_info; 246 }; 247 248 enum vfperm { 249 OTX2_RESET_VF_PERM, 250 OTX2_TRUSTED_VF, 251 }; 252 253 struct otx2_vf_config { 254 struct otx2_nic *pf; 255 struct delayed_work link_event_work; 256 bool intf_down; /* interface was either configured or not */ 257 u8 mac[ETH_ALEN]; 258 u16 vlan; 259 int tx_vtag_idx; 260 bool trusted; 261 }; 262 263 struct flr_work { 264 struct work_struct work; 265 struct otx2_nic *pf; 266 }; 267 268 struct refill_work { 269 struct delayed_work pool_refill_work; 270 struct otx2_nic *pf; 271 }; 272 273 struct otx2_ptp { 274 struct ptp_clock_info ptp_info; 275 struct ptp_clock *ptp_clock; 276 struct otx2_nic *nic; 277 278 struct cyclecounter cycle_counter; 279 struct timecounter time_counter; 280 281 struct delayed_work extts_work; 282 u64 last_extts; 283 u64 thresh; 284 285 struct ptp_pin_desc extts_config; 286 u64 (*convert_rx_ptp_tstmp)(u64 timestamp); 287 u64 (*convert_tx_ptp_tstmp)(u64 timestamp); 288 }; 289 290 #define OTX2_HW_TIMESTAMP_LEN 8 291 292 struct otx2_mac_table { 293 u8 addr[ETH_ALEN]; 294 u16 mcam_entry; 295 bool inuse; 296 }; 297 298 struct otx2_flow_config { 299 u16 *flow_ent; 300 u16 *def_ent; 301 u16 nr_flows; 302 #define OTX2_DEFAULT_FLOWCOUNT 16 303 #define OTX2_MAX_UNICAST_FLOWS 8 304 #define OTX2_MAX_VLAN_FLOWS 1 305 #define OTX2_MAX_TC_FLOWS OTX2_DEFAULT_FLOWCOUNT 306 #define OTX2_MCAM_COUNT (OTX2_DEFAULT_FLOWCOUNT + \ 307 OTX2_MAX_UNICAST_FLOWS + \ 308 OTX2_MAX_VLAN_FLOWS) 309 u16 unicast_offset; 310 u16 rx_vlan_offset; 311 u16 vf_vlan_offset; 312 #define OTX2_PER_VF_VLAN_FLOWS 2 /* Rx + Tx per VF */ 313 #define OTX2_VF_VLAN_RX_INDEX 0 314 #define OTX2_VF_VLAN_TX_INDEX 1 315 u16 max_flows; 316 u8 dmacflt_max_flows; 317 u8 *bmap_to_dmacindex; 318 unsigned long dmacflt_bmap; 319 struct list_head flow_list; 320 }; 321 322 struct otx2_tc_info { 323 /* hash table to store TC offloaded flows */ 324 struct rhashtable flow_table; 325 struct rhashtable_params flow_ht_params; 326 unsigned long *tc_entries_bitmap; 327 }; 328 329 struct dev_hw_ops { 330 int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); 331 void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, 332 int size, int qidx); 333 void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); 334 void (*aura_freeptr)(void *dev, int aura, u64 buf); 335 }; 336 337 struct otx2_nic { 338 void __iomem *reg_base; 339 struct net_device *netdev; 340 struct dev_hw_ops *hw_ops; 341 void *iommu_domain; 342 u16 tx_max_pktlen; 343 u16 rbsize; /* Receive buffer size */ 344 345 #define OTX2_FLAG_RX_TSTAMP_ENABLED BIT_ULL(0) 346 #define OTX2_FLAG_TX_TSTAMP_ENABLED BIT_ULL(1) 347 #define OTX2_FLAG_INTF_DOWN BIT_ULL(2) 348 #define OTX2_FLAG_MCAM_ENTRIES_ALLOC BIT_ULL(3) 349 #define OTX2_FLAG_NTUPLE_SUPPORT BIT_ULL(4) 350 #define OTX2_FLAG_UCAST_FLTR_SUPPORT BIT_ULL(5) 351 #define OTX2_FLAG_RX_VLAN_SUPPORT BIT_ULL(6) 352 #define OTX2_FLAG_VF_VLAN_SUPPORT BIT_ULL(7) 353 #define OTX2_FLAG_PF_SHUTDOWN BIT_ULL(8) 354 #define OTX2_FLAG_RX_PAUSE_ENABLED BIT_ULL(9) 355 #define OTX2_FLAG_TX_PAUSE_ENABLED BIT_ULL(10) 356 #define OTX2_FLAG_TC_FLOWER_SUPPORT BIT_ULL(11) 357 #define OTX2_FLAG_TC_MATCHALL_EGRESS_ENABLED BIT_ULL(12) 358 #define OTX2_FLAG_TC_MATCHALL_INGRESS_ENABLED BIT_ULL(13) 359 #define OTX2_FLAG_DMACFLTR_SUPPORT BIT_ULL(14) 360 #define OTX2_FLAG_ADPTV_INT_COAL_ENABLED BIT_ULL(16) 361 u64 flags; 362 u64 *cq_op_addr; 363 364 struct bpf_prog *xdp_prog; 365 struct otx2_qset qset; 366 struct otx2_hw hw; 367 struct pci_dev *pdev; 368 struct device *dev; 369 370 /* Mbox */ 371 struct mbox mbox; 372 struct mbox *mbox_pfvf; 373 struct workqueue_struct *mbox_wq; 374 struct workqueue_struct *mbox_pfvf_wq; 375 376 u8 total_vfs; 377 u16 pcifunc; /* RVU PF_FUNC */ 378 u16 bpid[NIX_MAX_BPID_CHAN]; 379 struct otx2_vf_config *vf_configs; 380 struct cgx_link_user_info linfo; 381 382 /* NPC MCAM */ 383 struct otx2_flow_config *flow_cfg; 384 struct otx2_mac_table *mac_table; 385 struct otx2_tc_info tc_info; 386 387 u64 reset_count; 388 struct work_struct reset_task; 389 struct workqueue_struct *flr_wq; 390 struct flr_work *flr_wrk; 391 struct refill_work *refill_wrk; 392 struct workqueue_struct *otx2_wq; 393 struct work_struct rx_mode_work; 394 395 /* Ethtool stuff */ 396 u32 msg_enable; 397 398 /* Block address of NIX either BLKADDR_NIX0 or BLKADDR_NIX1 */ 399 int nix_blkaddr; 400 /* LMTST Lines info */ 401 struct qmem *dync_lmt; 402 u16 tot_lmt_lines; 403 u16 npa_lmt_lines; 404 u32 nix_lmt_size; 405 406 struct otx2_ptp *ptp; 407 struct hwtstamp_config tstamp; 408 409 unsigned long rq_bmap; 410 411 /* Devlink */ 412 struct otx2_devlink *dl; 413 #ifdef CONFIG_DCB 414 /* PFC */ 415 u8 pfc_en; 416 u8 *queue_to_pfc_map; 417 #endif 418 419 /* napi event count. It is needed for adaptive irq coalescing. */ 420 u32 napi_events; 421 }; 422 423 static inline bool is_otx2_lbkvf(struct pci_dev *pdev) 424 { 425 return pdev->device == PCI_DEVID_OCTEONTX2_RVU_AFVF; 426 } 427 428 static inline bool is_96xx_A0(struct pci_dev *pdev) 429 { 430 return (pdev->revision == 0x00) && 431 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 432 } 433 434 static inline bool is_96xx_B0(struct pci_dev *pdev) 435 { 436 return (pdev->revision == 0x01) && 437 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF); 438 } 439 440 /* REVID for PCIe devices. 441 * Bits 0..1: minor pass, bit 3..2: major pass 442 * bits 7..4: midr id 443 */ 444 #define PCI_REVISION_ID_96XX 0x00 445 #define PCI_REVISION_ID_95XX 0x10 446 #define PCI_REVISION_ID_95XXN 0x20 447 #define PCI_REVISION_ID_98XX 0x30 448 #define PCI_REVISION_ID_95XXMM 0x40 449 #define PCI_REVISION_ID_95XXO 0xE0 450 451 static inline bool is_dev_otx2(struct pci_dev *pdev) 452 { 453 u8 midr = pdev->revision & 0xF0; 454 455 return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX || 456 midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX || 457 midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO); 458 } 459 460 static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf) 461 { 462 struct otx2_hw *hw = &pfvf->hw; 463 464 pfvf->hw.cq_time_wait = CQ_TIMER_THRESH_DEFAULT; 465 pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT; 466 pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT; 467 468 __set_bit(HW_TSO, &hw->cap_flag); 469 470 if (is_96xx_A0(pfvf->pdev)) { 471 __clear_bit(HW_TSO, &hw->cap_flag); 472 473 /* Time based irq coalescing is not supported */ 474 pfvf->hw.cq_qcount_wait = 0x0; 475 476 /* Due to HW issue previous silicons required minimum 477 * 600 unused CQE to avoid CQ overflow. 478 */ 479 pfvf->hw.rq_skid = 600; 480 pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K); 481 } 482 if (is_96xx_B0(pfvf->pdev)) 483 __clear_bit(HW_TSO, &hw->cap_flag); 484 485 if (!is_dev_otx2(pfvf->pdev)) { 486 __set_bit(CN10K_MBOX, &hw->cap_flag); 487 __set_bit(CN10K_LMTST, &hw->cap_flag); 488 __set_bit(CN10K_RPM, &hw->cap_flag); 489 } 490 } 491 492 /* Register read/write APIs */ 493 static inline void __iomem *otx2_get_regaddr(struct otx2_nic *nic, u64 offset) 494 { 495 u64 blkaddr; 496 497 switch ((offset >> RVU_FUNC_BLKADDR_SHIFT) & RVU_FUNC_BLKADDR_MASK) { 498 case BLKTYPE_NIX: 499 blkaddr = nic->nix_blkaddr; 500 break; 501 case BLKTYPE_NPA: 502 blkaddr = BLKADDR_NPA; 503 break; 504 default: 505 blkaddr = BLKADDR_RVUM; 506 break; 507 } 508 509 offset &= ~(RVU_FUNC_BLKADDR_MASK << RVU_FUNC_BLKADDR_SHIFT); 510 offset |= (blkaddr << RVU_FUNC_BLKADDR_SHIFT); 511 512 return nic->reg_base + offset; 513 } 514 515 static inline void otx2_write64(struct otx2_nic *nic, u64 offset, u64 val) 516 { 517 void __iomem *addr = otx2_get_regaddr(nic, offset); 518 519 writeq(val, addr); 520 } 521 522 static inline u64 otx2_read64(struct otx2_nic *nic, u64 offset) 523 { 524 void __iomem *addr = otx2_get_regaddr(nic, offset); 525 526 return readq(addr); 527 } 528 529 /* Mbox bounce buffer APIs */ 530 static inline int otx2_mbox_bbuf_init(struct mbox *mbox, struct pci_dev *pdev) 531 { 532 struct otx2_mbox *otx2_mbox; 533 struct otx2_mbox_dev *mdev; 534 535 mbox->bbuf_base = devm_kmalloc(&pdev->dev, MBOX_SIZE, GFP_KERNEL); 536 if (!mbox->bbuf_base) 537 return -ENOMEM; 538 539 /* Overwrite mbox mbase to point to bounce buffer, so that PF/VF 540 * prepare all mbox messages in bounce buffer instead of directly 541 * in hw mbox memory. 542 */ 543 otx2_mbox = &mbox->mbox; 544 mdev = &otx2_mbox->dev[0]; 545 mdev->mbase = mbox->bbuf_base; 546 547 otx2_mbox = &mbox->mbox_up; 548 mdev = &otx2_mbox->dev[0]; 549 mdev->mbase = mbox->bbuf_base; 550 return 0; 551 } 552 553 static inline void otx2_sync_mbox_bbuf(struct otx2_mbox *mbox, int devid) 554 { 555 u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 556 void *hw_mbase = mbox->hwbase + (devid * MBOX_SIZE); 557 struct otx2_mbox_dev *mdev = &mbox->dev[devid]; 558 struct mbox_hdr *hdr; 559 u64 msg_size; 560 561 if (mdev->mbase == hw_mbase) 562 return; 563 564 hdr = hw_mbase + mbox->rx_start; 565 msg_size = hdr->msg_size; 566 567 if (msg_size > mbox->rx_size - msgs_offset) 568 msg_size = mbox->rx_size - msgs_offset; 569 570 /* Copy mbox messages from mbox memory to bounce buffer */ 571 memcpy(mdev->mbase + mbox->rx_start, 572 hw_mbase + mbox->rx_start, msg_size + msgs_offset); 573 } 574 575 /* With the absence of API for 128-bit IO memory access for arm64, 576 * implement required operations at place. 577 */ 578 #if defined(CONFIG_ARM64) 579 static inline void otx2_write128(u64 lo, u64 hi, void __iomem *addr) 580 { 581 __asm__ volatile("stp %x[x0], %x[x1], [%x[p1],#0]!" 582 ::[x0]"r"(lo), [x1]"r"(hi), [p1]"r"(addr)); 583 } 584 585 static inline u64 otx2_atomic64_add(u64 incr, u64 *ptr) 586 { 587 u64 result; 588 589 __asm__ volatile(".cpu generic+lse\n" 590 "ldadd %x[i], %x[r], [%[b]]" 591 : [r]"=r"(result), "+m"(*ptr) 592 : [i]"r"(incr), [b]"r"(ptr) 593 : "memory"); 594 return result; 595 } 596 597 #else 598 #define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) 599 #define otx2_atomic64_add(incr, ptr) ({ *ptr += incr; }) 600 #endif 601 602 static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, 603 u64 *ptrs, u64 num_ptrs) 604 { 605 struct otx2_lmt_info *lmt_info; 606 u64 size = 0, count_eot = 0; 607 u64 tar_addr, val = 0; 608 609 lmt_info = per_cpu_ptr(pfvf->hw.lmt_info, smp_processor_id()); 610 tar_addr = (__force u64)otx2_get_regaddr(pfvf, NPA_LF_AURA_BATCH_FREE0); 611 /* LMTID is same as AURA Id */ 612 val = (lmt_info->lmt_id & 0x7FF) | BIT_ULL(63); 613 /* Set if [127:64] of last 128bit word has a valid pointer */ 614 count_eot = (num_ptrs % 2) ? 0ULL : 1ULL; 615 /* Set AURA ID to free pointer */ 616 ptrs[0] = (count_eot << 32) | (aura & 0xFFFFF); 617 /* Target address for LMTST flush tells HW how many 128bit 618 * words are valid from NPA_LF_AURA_BATCH_FREE0. 619 * 620 * tar_addr[6:4] is LMTST size-1 in units of 128b. 621 */ 622 if (num_ptrs > 2) { 623 size = (sizeof(u64) * num_ptrs) / 16; 624 if (!count_eot) 625 size++; 626 tar_addr |= ((size - 1) & 0x7) << 4; 627 } 628 dma_wmb(); 629 memcpy((u64 *)lmt_info->lmt_addr, ptrs, sizeof(u64) * num_ptrs); 630 /* Perform LMTST flush */ 631 cn10k_lmt_flush(val, tar_addr); 632 } 633 634 static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) 635 { 636 struct otx2_nic *pfvf = dev; 637 u64 ptrs[2]; 638 639 ptrs[1] = buf; 640 /* Free only one buffer at time during init and teardown */ 641 __cn10k_aura_freeptr(pfvf, aura, ptrs, 2); 642 } 643 644 /* Alloc pointer from pool/aura */ 645 static inline u64 otx2_aura_allocptr(struct otx2_nic *pfvf, int aura) 646 { 647 u64 *ptr = (u64 *)otx2_get_regaddr(pfvf, 648 NPA_LF_AURA_OP_ALLOCX(0)); 649 u64 incr = (u64)aura | BIT_ULL(63); 650 651 return otx2_atomic64_add(incr, ptr); 652 } 653 654 /* Free pointer to a pool/aura */ 655 static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) 656 { 657 struct otx2_nic *pfvf = dev; 658 void __iomem *addr = otx2_get_regaddr(pfvf, NPA_LF_AURA_OP_FREE0); 659 660 otx2_write128(buf, (u64)aura | BIT_ULL(63), addr); 661 } 662 663 static inline int otx2_get_pool_idx(struct otx2_nic *pfvf, int type, int idx) 664 { 665 if (type == AURA_NIX_SQ) 666 return pfvf->hw.rqpool_cnt + idx; 667 668 /* AURA_NIX_RQ */ 669 return idx; 670 } 671 672 /* Mbox APIs */ 673 static inline int otx2_sync_mbox_msg(struct mbox *mbox) 674 { 675 int err; 676 677 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 678 return 0; 679 otx2_mbox_msg_send(&mbox->mbox, 0); 680 err = otx2_mbox_wait_for_rsp(&mbox->mbox, 0); 681 if (err) 682 return err; 683 684 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 685 } 686 687 static inline int otx2_sync_mbox_up_msg(struct mbox *mbox, int devid) 688 { 689 int err; 690 691 if (!otx2_mbox_nonempty(&mbox->mbox_up, devid)) 692 return 0; 693 otx2_mbox_msg_send(&mbox->mbox_up, devid); 694 err = otx2_mbox_wait_for_rsp(&mbox->mbox_up, devid); 695 if (err) 696 return err; 697 698 return otx2_mbox_check_rsp_msgs(&mbox->mbox_up, devid); 699 } 700 701 /* Use this API to send mbox msgs in atomic context 702 * where sleeping is not allowed 703 */ 704 static inline int otx2_sync_mbox_msg_busy_poll(struct mbox *mbox) 705 { 706 int err; 707 708 if (!otx2_mbox_nonempty(&mbox->mbox, 0)) 709 return 0; 710 otx2_mbox_msg_send(&mbox->mbox, 0); 711 err = otx2_mbox_busy_poll_for_rsp(&mbox->mbox, 0); 712 if (err) 713 return err; 714 715 return otx2_mbox_check_rsp_msgs(&mbox->mbox, 0); 716 } 717 718 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 719 static struct _req_type __maybe_unused \ 720 *otx2_mbox_alloc_msg_ ## _fn_name(struct mbox *mbox) \ 721 { \ 722 struct _req_type *req; \ 723 \ 724 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \ 725 &mbox->mbox, 0, sizeof(struct _req_type), \ 726 sizeof(struct _rsp_type)); \ 727 if (!req) \ 728 return NULL; \ 729 req->hdr.sig = OTX2_MBOX_REQ_SIG; \ 730 req->hdr.id = _id; \ 731 trace_otx2_msg_alloc(mbox->mbox.pdev, _id, sizeof(*req)); \ 732 return req; \ 733 } 734 735 MBOX_MESSAGES 736 #undef M 737 738 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 739 int \ 740 otx2_mbox_up_handler_ ## _fn_name(struct otx2_nic *pfvf, \ 741 struct _req_type *req, \ 742 struct _rsp_type *rsp); \ 743 744 MBOX_UP_CGX_MESSAGES 745 #undef M 746 747 /* Time to wait before watchdog kicks off */ 748 #define OTX2_TX_TIMEOUT (100 * HZ) 749 750 #define RVU_PFVF_PF_SHIFT 10 751 #define RVU_PFVF_PF_MASK 0x3F 752 #define RVU_PFVF_FUNC_SHIFT 0 753 #define RVU_PFVF_FUNC_MASK 0x3FF 754 755 static inline bool is_otx2_vf(u16 pcifunc) 756 { 757 return !!(pcifunc & RVU_PFVF_FUNC_MASK); 758 } 759 760 static inline int rvu_get_pf(u16 pcifunc) 761 { 762 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK; 763 } 764 765 static inline dma_addr_t otx2_dma_map_page(struct otx2_nic *pfvf, 766 struct page *page, 767 size_t offset, size_t size, 768 enum dma_data_direction dir) 769 { 770 dma_addr_t iova; 771 772 iova = dma_map_page_attrs(pfvf->dev, page, 773 offset, size, dir, DMA_ATTR_SKIP_CPU_SYNC); 774 if (unlikely(dma_mapping_error(pfvf->dev, iova))) 775 return (dma_addr_t)NULL; 776 return iova; 777 } 778 779 static inline void otx2_dma_unmap_page(struct otx2_nic *pfvf, 780 dma_addr_t addr, size_t size, 781 enum dma_data_direction dir) 782 { 783 dma_unmap_page_attrs(pfvf->dev, addr, size, 784 dir, DMA_ATTR_SKIP_CPU_SYNC); 785 } 786 787 /* MSI-X APIs */ 788 void otx2_free_cints(struct otx2_nic *pfvf, int n); 789 void otx2_set_cints_affinity(struct otx2_nic *pfvf); 790 int otx2_set_mac_address(struct net_device *netdev, void *p); 791 int otx2_hw_set_mtu(struct otx2_nic *pfvf, int mtu); 792 void otx2_tx_timeout(struct net_device *netdev, unsigned int txq); 793 void otx2_get_mac_from_af(struct net_device *netdev); 794 void otx2_config_irq_coalescing(struct otx2_nic *pfvf, int qidx); 795 int otx2_config_pause_frm(struct otx2_nic *pfvf); 796 void otx2_setup_segmentation(struct otx2_nic *pfvf); 797 798 /* RVU block related APIs */ 799 int otx2_attach_npa_nix(struct otx2_nic *pfvf); 800 int otx2_detach_resources(struct mbox *mbox); 801 int otx2_config_npa(struct otx2_nic *pfvf); 802 int otx2_sq_aura_pool_init(struct otx2_nic *pfvf); 803 int otx2_rq_aura_pool_init(struct otx2_nic *pfvf); 804 void otx2_aura_pool_free(struct otx2_nic *pfvf); 805 void otx2_free_aura_ptr(struct otx2_nic *pfvf, int type); 806 void otx2_sq_free_sqbs(struct otx2_nic *pfvf); 807 int otx2_config_nix(struct otx2_nic *pfvf); 808 int otx2_config_nix_queues(struct otx2_nic *pfvf); 809 int otx2_txschq_config(struct otx2_nic *pfvf, int lvl); 810 int otx2_txsch_alloc(struct otx2_nic *pfvf); 811 int otx2_txschq_stop(struct otx2_nic *pfvf); 812 void otx2_sqb_flush(struct otx2_nic *pfvf); 813 int __otx2_alloc_rbuf(struct otx2_nic *pfvf, struct otx2_pool *pool, 814 dma_addr_t *dma); 815 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable); 816 void otx2_ctx_disable(struct mbox *mbox, int type, bool npa); 817 int otx2_nix_config_bp(struct otx2_nic *pfvf, bool enable); 818 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 819 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq); 820 int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 821 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); 822 int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, 823 dma_addr_t *dma); 824 825 /* RSS configuration APIs*/ 826 int otx2_rss_init(struct otx2_nic *pfvf); 827 int otx2_set_flowkey_cfg(struct otx2_nic *pfvf); 828 void otx2_set_rss_key(struct otx2_nic *pfvf); 829 int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); 830 831 /* Mbox handlers */ 832 void mbox_handler_msix_offset(struct otx2_nic *pfvf, 833 struct msix_offset_rsp *rsp); 834 void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf, 835 struct npa_lf_alloc_rsp *rsp); 836 void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf, 837 struct nix_lf_alloc_rsp *rsp); 838 void mbox_handler_nix_txsch_alloc(struct otx2_nic *pf, 839 struct nix_txsch_alloc_rsp *rsp); 840 void mbox_handler_cgx_stats(struct otx2_nic *pfvf, 841 struct cgx_stats_rsp *rsp); 842 void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, 843 struct cgx_fec_stats_rsp *rsp); 844 void otx2_set_fec_stats_count(struct otx2_nic *pfvf); 845 void mbox_handler_nix_bp_enable(struct otx2_nic *pfvf, 846 struct nix_bp_cfg_rsp *rsp); 847 848 /* Device stats APIs */ 849 void otx2_get_dev_stats(struct otx2_nic *pfvf); 850 void otx2_get_stats64(struct net_device *netdev, 851 struct rtnl_link_stats64 *stats); 852 void otx2_update_lmac_stats(struct otx2_nic *pfvf); 853 void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); 854 int otx2_update_rq_stats(struct otx2_nic *pfvf, int qidx); 855 int otx2_update_sq_stats(struct otx2_nic *pfvf, int qidx); 856 void otx2_set_ethtool_ops(struct net_device *netdev); 857 void otx2vf_set_ethtool_ops(struct net_device *netdev); 858 859 int otx2_open(struct net_device *netdev); 860 int otx2_stop(struct net_device *netdev); 861 int otx2_set_real_num_queues(struct net_device *netdev, 862 int tx_queues, int rx_queues); 863 int otx2_ioctl(struct net_device *netdev, struct ifreq *req, int cmd); 864 int otx2_config_hwtstamp(struct net_device *netdev, struct ifreq *ifr); 865 866 /* MCAM filter related APIs */ 867 int otx2_mcam_flow_init(struct otx2_nic *pf); 868 int otx2vf_mcam_flow_init(struct otx2_nic *pfvf); 869 int otx2_alloc_mcam_entries(struct otx2_nic *pfvf, u16 count); 870 void otx2_mcam_flow_del(struct otx2_nic *pf); 871 int otx2_destroy_ntuple_flows(struct otx2_nic *pf); 872 int otx2_destroy_mcam_flows(struct otx2_nic *pfvf); 873 int otx2_get_flow(struct otx2_nic *pfvf, 874 struct ethtool_rxnfc *nfc, u32 location); 875 int otx2_get_all_flows(struct otx2_nic *pfvf, 876 struct ethtool_rxnfc *nfc, u32 *rule_locs); 877 int otx2_add_flow(struct otx2_nic *pfvf, 878 struct ethtool_rxnfc *nfc); 879 int otx2_remove_flow(struct otx2_nic *pfvf, u32 location); 880 int otx2_get_maxflows(struct otx2_flow_config *flow_cfg); 881 void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); 882 int otx2_del_macfilter(struct net_device *netdev, const u8 *mac); 883 int otx2_add_macfilter(struct net_device *netdev, const u8 *mac); 884 int otx2_enable_rxvlan(struct otx2_nic *pf, bool enable); 885 int otx2_install_rxvlan_offload_flow(struct otx2_nic *pfvf); 886 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx); 887 u16 otx2_get_max_mtu(struct otx2_nic *pfvf); 888 int otx2_handle_ntuple_tc_features(struct net_device *netdev, 889 netdev_features_t features); 890 /* tc support */ 891 int otx2_init_tc(struct otx2_nic *nic); 892 void otx2_shutdown_tc(struct otx2_nic *nic); 893 int otx2_setup_tc(struct net_device *netdev, enum tc_setup_type type, 894 void *type_data); 895 int otx2_tc_alloc_ent_bitmap(struct otx2_nic *nic); 896 /* CGX/RPM DMAC filters support */ 897 int otx2_dmacflt_get_max_cnt(struct otx2_nic *pf); 898 int otx2_dmacflt_add(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); 899 int otx2_dmacflt_remove(struct otx2_nic *pf, const u8 *mac, u8 bit_pos); 900 int otx2_dmacflt_update(struct otx2_nic *pf, u8 *mac, u8 bit_pos); 901 void otx2_dmacflt_reinstall_flows(struct otx2_nic *pf); 902 void otx2_dmacflt_update_pfmac_flow(struct otx2_nic *pfvf); 903 904 #ifdef CONFIG_DCB 905 /* DCB support*/ 906 void otx2_update_bpid_in_rqctx(struct otx2_nic *pfvf, int vlan_prio, int qidx, bool pfc_enable); 907 int otx2_config_priority_flow_ctrl(struct otx2_nic *pfvf); 908 int otx2_dcbnl_set_ops(struct net_device *dev); 909 #endif 910 #endif /* OTX2_COMMON_H */ 911